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drm/amd/display: remove destructive verify link for TMDS
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
d38ceaf9 25#include <drm/amdgpu_drm.h>
6848c291 26#include <drm/drm_aperture.h>
fdf2f6c5 27#include <drm/drm_drv.h>
d38ceaf9 28#include <drm/drm_gem.h>
fdf2f6c5 29#include <drm/drm_vblank.h>
8aba21b7 30#include <drm/drm_managed.h>
d38ceaf9
AD		 31#include "amdgpu_drv.h"
32
33#include <drm/drm_pciids.h>
d38ceaf9
AD		 34#include <linux/module.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
fcd70cd3 37#include <drm/drm_probe_helper.h>
c7d8b782 38#include <linux/mmu_notifier.h>
e25443d2 39#include <linux/suspend.h>
e9d1d2bb 40#include <linux/cc_platform.h>
b95dc06a 41#include <linux/fb.h>
d38ceaf9
AD		 42
43#include "amdgpu.h"
44#include "amdgpu_irq.h"
2fbd6f94 45#include "amdgpu_dma_buf.h"
5088d657 46#include "amdgpu_sched.h"
87444254 47#include "amdgpu_fdinfo.h"
130e0371
OG		 48#include "amdgpu_amdkfd.h"
49
7c6e68c7 50#include "amdgpu_ras.h"
e3c1b071 51#include "amdgpu_xgmi.h"
04442bf7 52#include "amdgpu_reset.h"
7c6e68c7 53
d38ceaf9
AD		 54/*
55 * KMS wrapper.
56 * - 3.0.0 - initial driver
6055f37a 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
59 * at the end of IBs.
d347ce66 60 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 62 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 64 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 65 * - 3.8.0 - Add support raster config init in the kernel
ef704318 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 69 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 70 * - 3.13.0 - Add PRT support
203eb0cb 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 72 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 73 * - 3.16.0 - Add reserved vmid support
68e2c5ff 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 75 * - 3.18.0 - Export gpu always on cu bitmap
33476319 76 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 77 * - 3.20.0 - Add support for local BOs
7ca24cf2 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 80 * - 3.23.0 - Add query for VRAM lost counter
f8e3e0ee 81 * - 3.24.0 - Add high priority compute support for gfx9
7b158d16 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
d240cd9e 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
964d0fbf 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
67dd1a36 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
41cca166 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
767e06a9 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
df8368be 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
1afeb314 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
635e2c5f 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
965ebe3d 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
815fb4c9 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
664fe85a 93 * - 3.36.0 - Allow reading more status registers on si/cik
ff532461 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
43c8546b 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
174b328b 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
16c642ec 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
b50368da 98 * - 3.41.0 - Add video codec query
915821a7 99 * - 3.42.0 - Add 16bpc fixed point display support
5c67ff3a 100 * - 3.43.0 - Add device hot plug/unplug support
f2e7d856 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
ded81d5b 102 * - 3.45.0 - Add context ioctl stable pstate interface
5aa06147 103 * * 3.46.0 - To enable hot plug amdgpu tests in libdrm
d38ceaf9
AD		 104 */
105#define KMS_DRIVER_MAJOR 3
5aa06147 106#define KMS_DRIVER_MINOR 46
d38ceaf9
AD		 107#define KMS_DRIVER_PATCHLEVEL 0
108
87fb7833
DV		 109int amdgpu_vram_limit;
110int amdgpu_vis_vram_limit;
83e74db6 111int amdgpu_gart_size = -1; /* auto */
36d38372 112int amdgpu_gtt_size = -1; /* auto */
95844d20 113int amdgpu_moverate = -1; /* auto */
d38ceaf9 114int amdgpu_audio = -1;
87fb7833
DV		 115int amdgpu_disp_priority;
116int amdgpu_hw_i2c;
d38ceaf9
AD		 117int amdgpu_pcie_gen2 = -1;
118int amdgpu_msi = -1;
f440ff44 119char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
d38ceaf9 120int amdgpu_dpm = -1;
e635ee07 121int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 122int amdgpu_aspm = -1;
123int amdgpu_runtime_pm = -1;
0b693f0b 124uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9 125int amdgpu_bapm = -1;
87fb7833 126int amdgpu_deep_color;
bab4fee7 127int amdgpu_vm_size = -1;
d07f14be 128int amdgpu_vm_fragment_size = -1;
d38ceaf9 129int amdgpu_vm_block_size = -1;
87fb7833
DV		 130int amdgpu_vm_fault_stop;
131int amdgpu_vm_debug;
9a4b7d4c 132int amdgpu_vm_update_mode = -1;
87fb7833 133int amdgpu_exp_hw_support;
4562236b 134int amdgpu_dc = -1;
b70f014d 135int amdgpu_sched_jobs = 32;
4afcb303 136int amdgpu_sched_hw_submission = 2;
87fb7833
DV		 137uint amdgpu_pcie_gen_cap;
138uint amdgpu_pcie_lane_cap;
0b693f0b
RZ		 139uint amdgpu_cg_mask = 0xffffffff;
140uint amdgpu_pg_mask = 0xffffffff;
141uint amdgpu_sdma_phase_quantum = 32;
6f8941a2 142char *amdgpu_disable_cu = NULL;
9accf2fd 143char *amdgpu_virtual_display = NULL;
680602d6
KF		 144
145/*
146 * OverDrive(bit 14) disabled by default
147 * GFX DCS(bit 19) disabled by default
148 */
149uint amdgpu_pp_feature_mask = 0xfff7bfff;
87fb7833
DV		 150uint amdgpu_force_long_training;
151int amdgpu_job_hang_limit;
e8835e0e 152int amdgpu_lbpw = -1;
4a75aefe 153int amdgpu_compute_multipipe = -1;
dcebf026 154int amdgpu_gpu_recovery = -1; /* auto */
87fb7833
DV		 155int amdgpu_emu_mode;
156uint amdgpu_smu_memory_pool_size;
8738a82b 157int amdgpu_smu_pptable_id = -1;
191a3c04
EQ		 158/*
159 * FBC (bit 0) disabled by default
160 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
161 * - With this, for multiple monitors in sync(e.g. with the same model),
162 * mclk switching will be allowed. And the mclk will be not foced to the
163 * highest. That helps saving some idle power.
164 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
165 * PSR (bit 3) disabled by default
a5148245 166 * EDP NO POWER SEQUENCING (bit 4) disabled by default
191a3c04
EQ		 167 */
168uint amdgpu_dc_feature_mask = 2;
87fb7833 169uint amdgpu_dc_debug_mask;
5bfca069 170int amdgpu_async_gfx_ring = 1;
87fb7833 171int amdgpu_mcbp;
63e2fef6 172int amdgpu_discovery = -1;
87fb7833 173int amdgpu_mes;
d5cc02d9 174int amdgpu_noretry = -1;
4e66d7d2 175int amdgpu_force_asic_type = -1;
58aa7790 176int amdgpu_tmz = -1; /* auto */
273da6ff 177int amdgpu_reset_method = -1; /* auto */
a300de40 178int amdgpu_num_kcq = -1;
30d95a37 179int amdgpu_smartshift_bias;
158a05a0 180int amdgpu_use_xgmi_p2p = 1;
11eb648d 181int amdgpu_vcnfw_log;
7875a226 182
e3c1b071 183static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
184
62d73fbc
EQ		 185struct amdgpu_mgpu_info mgpu_info = {
186 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
e3c1b071 187 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
188 mgpu_info.delayed_reset_work,
189 amdgpu_drv_delayed_reset_work_handler, 0),
62d73fbc 190};
1218252f 191int amdgpu_ras_enable = -1;
e53aec7e 192uint amdgpu_ras_mask = 0xffffffff;
acc0204c 193int amdgpu_bad_page_threshold = -1;
88f8575b
DL		 194struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
195 .timeout_fatal_disable = false,
28a5d7a5 196 .period = 0x0, /* default to 0x0 (timeout disable) */
88f8575b 197};
d38ceaf9 198
8405cf39
SJ		 199/**
200 * DOC: vramlimit (int)
201 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
202 */
d38ceaf9
AD		 203MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
204module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
205
8405cf39
SJ		 206/**
207 * DOC: vis_vramlimit (int)
208 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
209 */
218b5dcd
JB		 210MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
211module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
212
8405cf39
SJ		 213/**
214 * DOC: gartsize (uint)
215 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
216 */
a4da14cc 217MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 218module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 219
8405cf39
SJ		 220/**
221 * DOC: gttsize (int)
222 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
223 * otherwise 3/4 RAM size).
224 */
36d38372
CK		 225MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
226module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 227
8405cf39
SJ		 228/**
229 * DOC: moverate (int)
230 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
231 */
95844d20
MO		 232MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
233module_param_named(moverate, amdgpu_moverate, int, 0600);
234
8405cf39
SJ		 235/**
236 * DOC: audio (int)
237 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
238 */
d38ceaf9
AD		 239MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
240module_param_named(audio, amdgpu_audio, int, 0444);
241
8405cf39
SJ		 242/**
243 * DOC: disp_priority (int)
244 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
245 */
d38ceaf9
AD		 246MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
247module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
248
8405cf39
SJ		 249/**
250 * DOC: hw_i2c (int)
251 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
252 */
d38ceaf9
AD		 253MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
254module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
255
8405cf39
SJ		 256/**
257 * DOC: pcie_gen2 (int)
258 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
259 */
d38ceaf9
AD		 260MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
261module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
262
8405cf39
SJ		 263/**
264 * DOC: msi (int)
265 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
266 */
d38ceaf9
AD		 267MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
268module_param_named(msi, amdgpu_msi, int, 0444);
269
8405cf39 270/**
912dfc84
EQ		 271 * DOC: lockup_timeout (string)
272 * Set GPU scheduler timeout value in ms.
273 *
274 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
275 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
879e723d
AZ		 276 * to the default timeout.
277 *
278 * - With one value specified, the setting will apply to all non-compute jobs.
279 * - With multiple values specified, the first one will be for GFX.
280 * The second one is for Compute. The third and fourth ones are
281 * for SDMA and Video.
282 *
912dfc84 283 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
67387dfe 284 * jobs is 10000. The timeout for compute is 60000.
912dfc84 285 */
67387dfe 286MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
bcccee89 287 "for passthrough or sriov, 10000 for all jobs."
71cc9ef3 288 " 0: keep default value. negative: infinity timeout), "
bcccee89
ED		 289 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
290 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
912dfc84 291module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
d38ceaf9 292
8405cf39
SJ		 293/**
294 * DOC: dpm (int)
54b998ca 295 * Override for dynamic power management setting
5c9a6272 296 * (0 = disable, 1 = enable)
54b998ca 297 * The default is -1 (auto).
8405cf39 298 */
d38ceaf9
AD		 299MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
300module_param_named(dpm, amdgpu_dpm, int, 0444);
301
8405cf39
SJ		 302/**
303 * DOC: fw_load_type (int)
ddb267b6
YD		 304 * Set different firmware loading type for debugging, if supported.
305 * Set to 0 to force direct loading if supported by the ASIC. Set
306 * to -1 to select the default loading mode for the ASIC, as defined
307 * by the driver. The default is -1 (auto).
8405cf39 308 */
ddb267b6 309MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)");
e635ee07 310module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9 311
8405cf39
SJ		 312/**
313 * DOC: aspm (int)
314 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
315 */
d38ceaf9
AD		 316MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
317module_param_named(aspm, amdgpu_aspm, int, 0444);
318
8405cf39
SJ		 319/**
320 * DOC: runpm (int)
4d625a97
AD		 321 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
322 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
323 * Setting the value to 0 disables this functionality.
8405cf39 324 */
4d625a97 325MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
d38ceaf9
AD		 326module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
327
8405cf39
SJ		 328/**
329 * DOC: ip_block_mask (uint)
330 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
331 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
332 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
333 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
334 */
d38ceaf9
AD		 335MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
336module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
337
8405cf39
SJ		 338/**
339 * DOC: bapm (int)
340 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
341 * The default -1 (auto, enabled)
342 */
d38ceaf9
AD		 343MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
344module_param_named(bapm, amdgpu_bapm, int, 0444);
345
8405cf39
SJ		 346/**
347 * DOC: deep_color (int)
348 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
349 */
d38ceaf9
AD		 350MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
351module_param_named(deep_color, amdgpu_deep_color, int, 0444);
352
8405cf39
SJ		 353/**
354 * DOC: vm_size (int)
355 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
356 */
ed885b21 357MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 358module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be 359
8405cf39
SJ		 360/**
361 * DOC: vm_fragment_size (int)
362 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
363 */
d07f14be
RH		 364MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
365module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9 366
8405cf39
SJ		 367/**
368 * DOC: vm_block_size (int)
369 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
370 */
d38ceaf9
AD		 371MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
372module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
373
8405cf39
SJ		 374/**
375 * DOC: vm_fault_stop (int)
376 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
377 */
d9c13156
CK		 378MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
379module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
380
8405cf39
SJ		 381/**
382 * DOC: vm_debug (int)
383 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
384 */
b495bd3a
CK		 385MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
386module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
387
8405cf39
SJ		 388/**
389 * DOC: vm_update_mode (int)
390 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
391 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
392 */
9a4b7d4c
HK		 393MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
394module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
395
8405cf39
SJ		 396/**
397 * DOC: exp_hw_support (int)
398 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
399 */
d38ceaf9
AD		 400MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
401module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
402
8405cf39
SJ		 403/**
404 * DOC: dc (int)
405 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
406 */
4562236b
HW		 407MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
408module_param_named(dc, amdgpu_dc, int, 0444);
409
8405cf39
SJ		 410/**
411 * DOC: sched_jobs (int)
412 * Override the max number of jobs supported in the sw queue. The default is 32.
413 */
b70f014d 414MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 415module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
416
8405cf39
SJ		 417/**
418 * DOC: sched_hw_submission (int)
419 * Override the max number of HW submissions. The default is 2.
420 */
4afcb303
JZ		 421MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
422module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
423
8405cf39 424/**
7427a7a0 425 * DOC: ppfeaturemask (hexint)
8405cf39
SJ		 426 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
427 * The default is the current set of stable power features.
428 */
5141e9d2 429MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
7427a7a0 430module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
3a74f6f2 431
367039bf
TY		 432/**
433 * DOC: forcelongtraining (uint)
434 * Force long memory training in resume.
435 * The default is zero, indicates short training in resume.
436 */
437MODULE_PARM_DESC(forcelongtraining, "force memory long training");
438module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
439
8405cf39
SJ		 440/**
441 * DOC: pcie_gen_cap (uint)
442 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
443 * The default is 0 (automatic for each asic).
444 */
cd474ba0
AD		 445MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
446module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
447
8405cf39
SJ		 448/**
449 * DOC: pcie_lane_cap (uint)
450 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
451 * The default is 0 (automatic for each asic).
452 */
cd474ba0
AD		 453MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
454module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
455
8405cf39
SJ		 456/**
457 * DOC: cg_mask (uint)
458 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
459 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
460 */
395d1fb9
NH		 461MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
462module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
463
8405cf39
SJ		 464/**
465 * DOC: pg_mask (uint)
466 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
467 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
468 */
395d1fb9
NH		 469MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
470module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
471
8405cf39
SJ		 472/**
473 * DOC: sdma_phase_quantum (uint)
474 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
475 */
a667386c
FK		 476MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
477module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
478
8405cf39
SJ		 479/**
480 * DOC: disable_cu (charp)
481 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
482 */
6f8941a2
NH		 483MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
484module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
485
8405cf39
SJ		 486/**
487 * DOC: virtual_display (charp)
488 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
489 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
490 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
491 * device at 26:00.0. The default is NULL.
492 */
0f66356d
ED		 493MODULE_PARM_DESC(virtual_display,
494 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 495module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 496
8405cf39
SJ		 497/**
498 * DOC: job_hang_limit (int)
499 * Set how much time allow a job hang and not drop it. The default is 0.
500 */
65781c78
ML		 501MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
502module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
503
8405cf39
SJ		 504/**
505 * DOC: lbpw (int)
506 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
507 */
e8835e0e
HZ		 508MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
509module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 510
4a75aefe
AR		 511MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
512module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
513
8405cf39
SJ		 514/**
515 * DOC: gpu_recovery (int)
516 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
517 */
e6c6338f 518MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
dcebf026
AG		 519module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
520
8405cf39
SJ		 521/**
522 * DOC: emu_mode (int)
523 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
524 */
d869ae09 525MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
bfca0289
SL		 526module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
527
1218252f 528/**
2f3940e9 529 * DOC: ras_enable (int)
1218252f 530 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
531 */
2f3940e9 532MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
1218252f 533module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
534
535/**
2f3940e9 536 * DOC: ras_mask (uint)
1218252f 537 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
538 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
539 */
2f3940e9 540MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
1218252f 541module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
542
88f8575b
DL		 543/**
544 * DOC: timeout_fatal_disable (bool)
545 * Disable Watchdog timeout fatal error event
546 */
547MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
548module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
549
550/**
551 * DOC: timeout_period (uint)
552 * Modify the watchdog timeout max_cycles as (1 << period)
553 */
28a5d7a5 554MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
88f8575b
DL		 555module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
556
8405cf39
SJ		 557/**
558 * DOC: si_support (int)
559 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
560 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
561 * otherwise using amdgpu driver.
562 */
6dd13096 563#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56
MD		 564
565#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
6dd13096
FK		 566int amdgpu_si_support = 0;
567MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 568#else
569int amdgpu_si_support = 1;
570MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
571#endif
572
6dd13096
FK		 573module_param_named(si_support, amdgpu_si_support, int, 0444);
574#endif
575
8405cf39
SJ		 576/**
577 * DOC: cik_support (int)
578 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
580 * otherwise using amdgpu driver.
581 */
7df28986 582#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56
MD		 583
584#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
2b059658
MD		 585int amdgpu_cik_support = 0;
586MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 587#else
588int amdgpu_cik_support = 1;
589MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
590#endif
591
7df28986
FK		 592module_param_named(cik_support, amdgpu_cik_support, int, 0444);
593#endif
594
8405cf39
SJ		 595/**
596 * DOC: smu_memory_pool_size (uint)
597 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
598 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
599 */
7951e376
RZ		 600MODULE_PARM_DESC(smu_memory_pool_size,
601 "reserve gtt for smu debug usage, 0 = disable,"
602 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
603module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
604
51bcce46
HZ		 605/**
606 * DOC: async_gfx_ring (int)
607 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
608 */
609MODULE_PARM_DESC(async_gfx_ring,
5bfca069 610 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
51bcce46
HZ		 611module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
612
40562787
AD		 613/**
614 * DOC: mcbp (int)
615 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
616 */
b239c017
JX		 617MODULE_PARM_DESC(mcbp,
618 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
619module_param_named(mcbp, amdgpu_mcbp, int, 0444);
620
40562787
AD		 621/**
622 * DOC: discovery (int)
623 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
a79d3709 624 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
40562787 625 */
a190d1c7
XY		 626MODULE_PARM_DESC(discovery,
627 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
628module_param_named(discovery, amdgpu_discovery, int, 0444);
629
40562787
AD		 630/**
631 * DOC: mes (int)
632 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
633 * (0 = disabled (default), 1 = enabled)
634 */
38487284
JX		 635MODULE_PARM_DESC(mes,
636 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
637module_param_named(mes, amdgpu_mes, int, 0444);
638
d5cc02d9
AD		 639/**
640 * DOC: noretry (int)
9705c85f
FK		 641 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
642 * do not support per-process XNACK this also disables retry page faults.
d5cc02d9
AD		 643 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
644 */
75ee6487 645MODULE_PARM_DESC(noretry,
d5cc02d9 646 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
75ee6487
FK		 647module_param_named(noretry, amdgpu_noretry, int, 0644);
648
4e66d7d2
YZ		 649/**
650 * DOC: force_asic_type (int)
651 * A non negative value used to specify the asic type for all supported GPUs.
652 */
653MODULE_PARM_DESC(force_asic_type,
654 "A non negative value used to specify the asic type for all supported GPUs");
655module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
656
158a05a0
AS		 657/**
658 * DOC: use_xgmi_p2p (int)
659 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
660 */
661MODULE_PARM_DESC(use_xgmi_p2p,
662 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
663module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
4e66d7d2
YZ		 664
665
2690262e 666#ifdef CONFIG_HSA_AMD
521fb7d0
AL		 667/**
668 * DOC: sched_policy (int)
669 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
670 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
671 * assigns queues to HQDs.
672 */
2690262e 673int sched_policy = KFD_SCHED_POLICY_HWS;
521fb7d0
AL		 674module_param(sched_policy, int, 0444);
675MODULE_PARM_DESC(sched_policy,
676 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
677
678/**
679 * DOC: hws_max_conc_proc (int)
680 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
681 * number of VMIDs assigned to the HWS, which is also the default.
682 */
2690262e 683int hws_max_conc_proc = 8;
521fb7d0
AL		 684module_param(hws_max_conc_proc, int, 0444);
685MODULE_PARM_DESC(hws_max_conc_proc,
686 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
687
688/**
689 * DOC: cwsr_enable (int)
690 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
691 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
692 * disables it.
693 */
2690262e 694int cwsr_enable = 1;
521fb7d0
AL		 695module_param(cwsr_enable, int, 0444);
696MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
697
698/**
699 * DOC: max_num_of_queues_per_device (int)
700 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
701 * is 4096.
702 */
2690262e 703int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
521fb7d0
AL		 704module_param(max_num_of_queues_per_device, int, 0444);
705MODULE_PARM_DESC(max_num_of_queues_per_device,
706 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
707
708/**
709 * DOC: send_sigterm (int)
710 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
711 * but just print errors on dmesg. Setting 1 enables sending sigterm.
712 */
2690262e 713int send_sigterm;
521fb7d0
AL		 714module_param(send_sigterm, int, 0444);
715MODULE_PARM_DESC(send_sigterm,
716 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
717
718/**
719 * DOC: debug_largebar (int)
720 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
721 * system. This limits the VRAM size reported to ROCm applications to the visible
722 * size, usually 256MB.
723 * Default value is 0, diabled.
724 */
2690262e 725int debug_largebar;
521fb7d0
AL		 726module_param(debug_largebar, int, 0444);
727MODULE_PARM_DESC(debug_largebar,
728 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
729
730/**
731 * DOC: ignore_crat (int)
732 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
733 * table to get information about AMD APUs. This option can serve as a workaround on
734 * systems with a broken CRAT table.
6127896f
HR		 735 *
736 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
cec2cc7b 737 * whether use CRAT)
521fb7d0 738 */
2690262e 739int ignore_crat;
521fb7d0
AL		 740module_param(ignore_crat, int, 0444);
741MODULE_PARM_DESC(ignore_crat,
6127896f 742 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
521fb7d0 743
521fb7d0
AL		 744/**
745 * DOC: halt_if_hws_hang (int)
746 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
747 * Setting 1 enables halt on hang.
748 */
2690262e 749int halt_if_hws_hang;
521fb7d0
AL		 750module_param(halt_if_hws_hang, int, 0644);
751MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
29e76462
OZ		 752
753/**
754 * DOC: hws_gws_support(bool)
29633d0e
JG		 755 * Assume that HWS supports GWS barriers regardless of what firmware version
756 * check says. Default value: false (rely on MEC2 firmware version check).
29e76462
OZ		 757 */
758bool hws_gws_support;
759module_param(hws_gws_support, bool, 0444);
29633d0e 760MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
14328aa5
PC		 761
762/**
763 * DOC: queue_preemption_timeout_ms (int)
764 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
765 */
f51af435 766int queue_preemption_timeout_ms = 9000;
14328aa5
PC		 767module_param(queue_preemption_timeout_ms, int, 0644);
768MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
b2057956
FK		 769
770/**
771 * DOC: debug_evictions(bool)
772 * Enable extra debug messages to help determine the cause of evictions
773 */
774bool debug_evictions;
775module_param(debug_evictions, bool, 0644);
776MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
b80f050f
PY		 777
778/**
779 * DOC: no_system_mem_limit(bool)
780 * Disable system memory limit, to support multiple process shared memory
781 */
782bool no_system_mem_limit;
783module_param(no_system_mem_limit, bool, 0644);
784MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
785
6d909c5d
OZ		 786/**
787 * DOC: no_queue_eviction_on_vm_fault (int)
788 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
789 */
790int amdgpu_no_queue_eviction_on_vm_fault = 0;
791MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
792module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
2690262e 793#endif
521fb7d0 794
7875a226
AD		 795/**
796 * DOC: dcfeaturemask (uint)
797 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
798 * The default is the current set of stable display features.
799 */
800MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
801module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
802
8a791dab
HW		 803/**
804 * DOC: dcdebugmask (uint)
805 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
806 */
807MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
808module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
809
ad4de27f
NK		 810/**
811 * DOC: abmlevel (uint)
812 * Override the default ABM (Adaptive Backlight Management) level used for DC
813 * enabled hardware. Requires DMCU to be supported and loaded.
814 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
815 * default. Values 1-4 control the maximum allowable brightness reduction via
816 * the ABM algorithm, with 1 being the least reduction and 4 being the most
817 * reduction.
818 *
819 * Defaults to 0, or disabled. Userspace can still override this level later
820 * after boot.
821 */
87fb7833 822uint amdgpu_dm_abm_level;
ad4de27f
NK		 823MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
824module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
825
7a46f05e
TI		 826int amdgpu_backlight = -1;
827MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
828module_param_named(backlight, amdgpu_backlight, bint, 0444);
829
d7ccb38d
HR		 830/**
831 * DOC: tmz (int)
832 * Trusted Memory Zone (TMZ) is a method to protect data being written
833 * to or read from memory.
834 *
835 * The default value: 0 (off). TODO: change to auto till it is completed.
836 */
58aa7790 837MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
d7ccb38d
HR		 838module_param_named(tmz, amdgpu_tmz, int, 0444);
839
273da6ff
WS		 840/**
841 * DOC: reset_method (int)
2656fd23 842 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
273da6ff 843 */
2656fd23 844MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
273da6ff
WS		 845module_param_named(reset_method, amdgpu_reset_method, int, 0444);
846
acc0204c 847/**
e4e6a589
LT		 848 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
849 * threshold value of faulty pages detected by RAS ECC, which may
850 * result in the GPU entering bad status when the number of total
851 * faulty pages by ECC exceeds the threshold value.
acc0204c 852 */
68daadf3 853MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
acc0204c
GC		 854module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
855
a300de40
ML		 856MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
857module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
858
11eb648d
RD		 859/**
860 * DOC: vcnfw_log (int)
861 * Enable vcnfw log output for debugging, the default is disabled.
862 */
863MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
864module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
865
8738a82b
LL		 866/**
867 * DOC: smu_pptable_id (int)
868 * Used to override pptable id. id = 0 use VBIOS pptable.
869 * id > 0 use the soft pptable with specicfied id.
870 */
871MODULE_PARM_DESC(smu_pptable_id,
872 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
873module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
874
bdbeb0dd
AD		 875/* These devices are not supported by amdgpu.
876 * They are supported by the mach64, r128, radeon drivers
877 */
878static const u16 amdgpu_unsupported_pciidlist[] = {
879 /* mach64 */
880 0x4354,
881 0x4358,
882 0x4554,
883 0x4742,
884 0x4744,
885 0x4749,
886 0x474C,
887 0x474D,
888 0x474E,
889 0x474F,
890 0x4750,
891 0x4751,
892 0x4752,
893 0x4753,
894 0x4754,
895 0x4755,
896 0x4756,
897 0x4757,
898 0x4758,
899 0x4759,
900 0x475A,
901 0x4C42,
902 0x4C44,
903 0x4C47,
904 0x4C49,
905 0x4C4D,
906 0x4C4E,
907 0x4C50,
908 0x4C51,
909 0x4C52,
910 0x4C53,
911 0x5654,
912 0x5655,
913 0x5656,
914 /* r128 */
915 0x4c45,
916 0x4c46,
917 0x4d46,
918 0x4d4c,
919 0x5041,
920 0x5042,
921 0x5043,
922 0x5044,
923 0x5045,
924 0x5046,
925 0x5047,
926 0x5048,
927 0x5049,
928 0x504A,
929 0x504B,
930 0x504C,
931 0x504D,
932 0x504E,
933 0x504F,
934 0x5050,
935 0x5051,
936 0x5052,
937 0x5053,
938 0x5054,
939 0x5055,
940 0x5056,
941 0x5057,
942 0x5058,
943 0x5245,
944 0x5246,
945 0x5247,
946 0x524b,
947 0x524c,
948 0x534d,
949 0x5446,
950 0x544C,
951 0x5452,
952 /* radeon */
953 0x3150,
954 0x3151,
955 0x3152,
956 0x3154,
957 0x3155,
958 0x3E50,
959 0x3E54,
960 0x4136,
961 0x4137,
962 0x4144,
963 0x4145,
964 0x4146,
965 0x4147,
966 0x4148,
967 0x4149,
968 0x414A,
969 0x414B,
970 0x4150,
971 0x4151,
972 0x4152,
973 0x4153,
974 0x4154,
975 0x4155,
976 0x4156,
977 0x4237,
978 0x4242,
979 0x4336,
980 0x4337,
981 0x4437,
982 0x4966,
983 0x4967,
984 0x4A48,
985 0x4A49,
986 0x4A4A,
987 0x4A4B,
988 0x4A4C,
989 0x4A4D,
990 0x4A4E,
991 0x4A4F,
992 0x4A50,
993 0x4A54,
994 0x4B48,
995 0x4B49,
996 0x4B4A,
997 0x4B4B,
998 0x4B4C,
999 0x4C57,
1000 0x4C58,
1001 0x4C59,
1002 0x4C5A,
1003 0x4C64,
1004 0x4C66,
1005 0x4C67,
1006 0x4E44,
1007 0x4E45,
1008 0x4E46,
1009 0x4E47,
1010 0x4E48,
1011 0x4E49,
1012 0x4E4A,
1013 0x4E4B,
1014 0x4E50,
1015 0x4E51,
1016 0x4E52,
1017 0x4E53,
1018 0x4E54,
1019 0x4E56,
1020 0x5144,
1021 0x5145,
1022 0x5146,
1023 0x5147,
1024 0x5148,
1025 0x514C,
1026 0x514D,
1027 0x5157,
1028 0x5158,
1029 0x5159,
1030 0x515A,
1031 0x515E,
1032 0x5460,
1033 0x5462,
1034 0x5464,
1035 0x5548,
1036 0x5549,
1037 0x554A,
1038 0x554B,
1039 0x554C,
1040 0x554D,
1041 0x554E,
1042 0x554F,
1043 0x5550,
1044 0x5551,
1045 0x5552,
1046 0x5554,
1047 0x564A,
1048 0x564B,
1049 0x564F,
1050 0x5652,
1051 0x5653,
1052 0x5657,
1053 0x5834,
1054 0x5835,
1055 0x5954,
1056 0x5955,
1057 0x5974,
1058 0x5975,
1059 0x5960,
1060 0x5961,
1061 0x5962,
1062 0x5964,
1063 0x5965,
1064 0x5969,
1065 0x5a41,
1066 0x5a42,
1067 0x5a61,
1068 0x5a62,
1069 0x5b60,
1070 0x5b62,
1071 0x5b63,
1072 0x5b64,
1073 0x5b65,
1074 0x5c61,
1075 0x5c63,
1076 0x5d48,
1077 0x5d49,
1078 0x5d4a,
1079 0x5d4c,
1080 0x5d4d,
1081 0x5d4e,
1082 0x5d4f,
1083 0x5d50,
1084 0x5d52,
1085 0x5d57,
1086 0x5e48,
1087 0x5e4a,
1088 0x5e4b,
1089 0x5e4c,
1090 0x5e4d,
1091 0x5e4f,
1092 0x6700,
1093 0x6701,
1094 0x6702,
1095 0x6703,
1096 0x6704,
1097 0x6705,
1098 0x6706,
1099 0x6707,
1100 0x6708,
1101 0x6709,
1102 0x6718,
1103 0x6719,
1104 0x671c,
1105 0x671d,
1106 0x671f,
1107 0x6720,
1108 0x6721,
1109 0x6722,
1110 0x6723,
1111 0x6724,
1112 0x6725,
1113 0x6726,
1114 0x6727,
1115 0x6728,
1116 0x6729,
1117 0x6738,
1118 0x6739,
1119 0x673e,
1120 0x6740,
1121 0x6741,
1122 0x6742,
1123 0x6743,
1124 0x6744,
1125 0x6745,
1126 0x6746,
1127 0x6747,
1128 0x6748,
1129 0x6749,
1130 0x674A,
1131 0x6750,
1132 0x6751,
1133 0x6758,
1134 0x6759,
1135 0x675B,
1136 0x675D,
1137 0x675F,
1138 0x6760,
1139 0x6761,
1140 0x6762,
1141 0x6763,
1142 0x6764,
1143 0x6765,
1144 0x6766,
1145 0x6767,
1146 0x6768,
1147 0x6770,
1148 0x6771,
1149 0x6772,
1150 0x6778,
1151 0x6779,
1152 0x677B,
1153 0x6840,
1154 0x6841,
1155 0x6842,
1156 0x6843,
1157 0x6849,
1158 0x684C,
1159 0x6850,
1160 0x6858,
1161 0x6859,
1162 0x6880,
1163 0x6888,
1164 0x6889,
1165 0x688A,
1166 0x688C,
1167 0x688D,
1168 0x6898,
1169 0x6899,
1170 0x689b,
1171 0x689c,
1172 0x689d,
1173 0x689e,
1174 0x68a0,
1175 0x68a1,
1176 0x68a8,
1177 0x68a9,
1178 0x68b0,
1179 0x68b8,
1180 0x68b9,
1181 0x68ba,
1182 0x68be,
1183 0x68bf,
1184 0x68c0,
1185 0x68c1,
1186 0x68c7,
1187 0x68c8,
1188 0x68c9,
1189 0x68d8,
1190 0x68d9,
1191 0x68da,
1192 0x68de,
1193 0x68e0,
1194 0x68e1,
1195 0x68e4,
1196 0x68e5,
1197 0x68e8,
1198 0x68e9,
1199 0x68f1,
1200 0x68f2,
1201 0x68f8,
1202 0x68f9,
1203 0x68fa,
1204 0x68fe,
1205 0x7100,
1206 0x7101,
1207 0x7102,
1208 0x7103,
1209 0x7104,
1210 0x7105,
1211 0x7106,
1212 0x7108,
1213 0x7109,
1214 0x710A,
1215 0x710B,
1216 0x710C,
1217 0x710E,
1218 0x710F,
1219 0x7140,
1220 0x7141,
1221 0x7142,
1222 0x7143,
1223 0x7144,
1224 0x7145,
1225 0x7146,
1226 0x7147,
1227 0x7149,
1228 0x714A,
1229 0x714B,
1230 0x714C,
1231 0x714D,
1232 0x714E,
1233 0x714F,
1234 0x7151,
1235 0x7152,
1236 0x7153,
1237 0x715E,
1238 0x715F,
1239 0x7180,
1240 0x7181,
1241 0x7183,
1242 0x7186,
1243 0x7187,
1244 0x7188,
1245 0x718A,
1246 0x718B,
1247 0x718C,
1248 0x718D,
1249 0x718F,
1250 0x7193,
1251 0x7196,
1252 0x719B,
1253 0x719F,
1254 0x71C0,
1255 0x71C1,
1256 0x71C2,
1257 0x71C3,
1258 0x71C4,
1259 0x71C5,
1260 0x71C6,
1261 0x71C7,
1262 0x71CD,
1263 0x71CE,
1264 0x71D2,
1265 0x71D4,
1266 0x71D5,
1267 0x71D6,
1268 0x71DA,
1269 0x71DE,
1270 0x7200,
1271 0x7210,
1272 0x7211,
1273 0x7240,
1274 0x7243,
1275 0x7244,
1276 0x7245,
1277 0x7246,
1278 0x7247,
1279 0x7248,
1280 0x7249,
1281 0x724A,
1282 0x724B,
1283 0x724C,
1284 0x724D,
1285 0x724E,
1286 0x724F,
1287 0x7280,
1288 0x7281,
1289 0x7283,
1290 0x7284,
1291 0x7287,
1292 0x7288,
1293 0x7289,
1294 0x728B,
1295 0x728C,
1296 0x7290,
1297 0x7291,
1298 0x7293,
1299 0x7297,
1300 0x7834,
1301 0x7835,
1302 0x791e,
1303 0x791f,
1304 0x793f,
1305 0x7941,
1306 0x7942,
1307 0x796c,
1308 0x796d,
1309 0x796e,
1310 0x796f,
1311 0x9400,
1312 0x9401,
1313 0x9402,
1314 0x9403,
1315 0x9405,
1316 0x940A,
1317 0x940B,
1318 0x940F,
1319 0x94A0,
1320 0x94A1,
1321 0x94A3,
1322 0x94B1,
1323 0x94B3,
1324 0x94B4,
1325 0x94B5,
1326 0x94B9,
1327 0x9440,
1328 0x9441,
1329 0x9442,
1330 0x9443,
1331 0x9444,
1332 0x9446,
1333 0x944A,
1334 0x944B,
1335 0x944C,
1336 0x944E,
1337 0x9450,
1338 0x9452,
1339 0x9456,
1340 0x945A,
1341 0x945B,
1342 0x945E,
1343 0x9460,
1344 0x9462,
1345 0x946A,
1346 0x946B,
1347 0x947A,
1348 0x947B,
1349 0x9480,
1350 0x9487,
1351 0x9488,
1352 0x9489,
1353 0x948A,
1354 0x948F,
1355 0x9490,
1356 0x9491,
1357 0x9495,
1358 0x9498,
1359 0x949C,
1360 0x949E,
1361 0x949F,
1362 0x94C0,
1363 0x94C1,
1364 0x94C3,
1365 0x94C4,
1366 0x94C5,
1367 0x94C6,
1368 0x94C7,
1369 0x94C8,
1370 0x94C9,
1371 0x94CB,
1372 0x94CC,
1373 0x94CD,
1374 0x9500,
1375 0x9501,
1376 0x9504,
1377 0x9505,
1378 0x9506,
1379 0x9507,
1380 0x9508,
1381 0x9509,
1382 0x950F,
1383 0x9511,
1384 0x9515,
1385 0x9517,
1386 0x9519,
1387 0x9540,
1388 0x9541,
1389 0x9542,
1390 0x954E,
1391 0x954F,
1392 0x9552,
1393 0x9553,
1394 0x9555,
1395 0x9557,
1396 0x955f,
1397 0x9580,
1398 0x9581,
1399 0x9583,
1400 0x9586,
1401 0x9587,
1402 0x9588,
1403 0x9589,
1404 0x958A,
1405 0x958B,
1406 0x958C,
1407 0x958D,
1408 0x958E,
1409 0x958F,
1410 0x9590,
1411 0x9591,
1412 0x9593,
1413 0x9595,
1414 0x9596,
1415 0x9597,
1416 0x9598,
1417 0x9599,
1418 0x959B,
1419 0x95C0,
1420 0x95C2,
1421 0x95C4,
1422 0x95C5,
1423 0x95C6,
1424 0x95C7,
1425 0x95C9,
1426 0x95CC,
1427 0x95CD,
1428 0x95CE,
1429 0x95CF,
1430 0x9610,
1431 0x9611,
1432 0x9612,
1433 0x9613,
1434 0x9614,
1435 0x9615,
1436 0x9616,
1437 0x9640,
1438 0x9641,
1439 0x9642,
1440 0x9643,
1441 0x9644,
1442 0x9645,
1443 0x9647,
1444 0x9648,
1445 0x9649,
1446 0x964a,
1447 0x964b,
1448 0x964c,
1449 0x964e,
1450 0x964f,
1451 0x9710,
1452 0x9711,
1453 0x9712,
1454 0x9713,
1455 0x9714,
1456 0x9715,
1457 0x9802,
1458 0x9803,
1459 0x9804,
1460 0x9805,
1461 0x9806,
1462 0x9807,
1463 0x9808,
1464 0x9809,
1465 0x980A,
1466 0x9900,
1467 0x9901,
1468 0x9903,
1469 0x9904,
1470 0x9905,
1471 0x9906,
1472 0x9907,
1473 0x9908,
1474 0x9909,
1475 0x990A,
1476 0x990B,
1477 0x990C,
1478 0x990D,
1479 0x990E,
1480 0x990F,
1481 0x9910,
1482 0x9913,
1483 0x9917,
1484 0x9918,
1485 0x9919,
1486 0x9990,
1487 0x9991,
1488 0x9992,
1489 0x9993,
1490 0x9994,
1491 0x9995,
1492 0x9996,
1493 0x9997,
1494 0x9998,
1495 0x9999,
1496 0x999A,
1497 0x999B,
1498 0x999C,
1499 0x999D,
1500 0x99A0,
1501 0x99A2,
1502 0x99A4,
9e5a14bc
AD		 1503 /* radeon secondary ids */
1504 0x3171,
1505 0x3e70,
1506 0x4164,
1507 0x4165,
1508 0x4166,
1509 0x4168,
1510 0x4170,
1511 0x4171,
1512 0x4172,
1513 0x4173,
1514 0x496e,
1515 0x4a69,
1516 0x4a6a,
1517 0x4a6b,
1518 0x4a70,
1519 0x4a74,
1520 0x4b69,
1521 0x4b6b,
1522 0x4b6c,
1523 0x4c6e,
1524 0x4e64,
1525 0x4e65,
1526 0x4e66,
1527 0x4e67,
1528 0x4e68,
1529 0x4e69,
1530 0x4e6a,
1531 0x4e71,
1532 0x4f73,
1533 0x5569,
1534 0x556b,
1535 0x556d,
1536 0x556f,
1537 0x5571,
1538 0x5854,
1539 0x5874,
1540 0x5940,
1541 0x5941,
1542 0x5b72,
1543 0x5b73,
1544 0x5b74,
1545 0x5b75,
1546 0x5d44,
1547 0x5d45,
1548 0x5d6d,
1549 0x5d6f,
1550 0x5d72,
1551 0x5d77,
1552 0x5e6b,
1553 0x5e6d,
1554 0x7120,
1555 0x7124,
1556 0x7129,
1557 0x712e,
1558 0x712f,
1559 0x7162,
1560 0x7163,
1561 0x7166,
1562 0x7167,
1563 0x7172,
1564 0x7173,
1565 0x71a0,
1566 0x71a1,
1567 0x71a3,
1568 0x71a7,
1569 0x71bb,
1570 0x71e0,
1571 0x71e1,
1572 0x71e2,
1573 0x71e6,
1574 0x71e7,
1575 0x71f2,
1576 0x7269,
1577 0x726b,
1578 0x726e,
1579 0x72a0,
1580 0x72a8,
1581 0x72b1,
1582 0x72b3,
1583 0x793f,
bdbeb0dd
AD		 1584};
1585
f498d9ed 1586static const struct pci_device_id pciidlist[] = {
78fbb685
KW		 1587#ifdef CONFIG_DRM_AMDGPU_SI
1588 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1589 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1590 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1591 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1592 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1593 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1594 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1595 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1596 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1597 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1598 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1599 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1600 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1601 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1602 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1603 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1604 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1605 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1606 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1607 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1608 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1609 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1610 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1611 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1612 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1613 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1614 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1615 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1616 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1617 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1618 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1619 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1620 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1621 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1622 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1623 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1624 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1625 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1626 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1627 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1628 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1629 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1630 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1631 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1632 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1633 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1634 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1635 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1636 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1637 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1638 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1639 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1640 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1641 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1642 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1643 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1644 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1645 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1646 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1647 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1648 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1649 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1650 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1651 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1652 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1653 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1654 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1655 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1656 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1657 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1658 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1659 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1660#endif
89330c39
AD		 1661#ifdef CONFIG_DRM_AMDGPU_CIK
1662 /* Kaveri */
2f7d10b3
JZ		 1663 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1664 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1665 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1666 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1667 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1668 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1669 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1670 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1671 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1672 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1673 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1674 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1675 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1676 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1677 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1678 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1679 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1680 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1681 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1682 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1683 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1684 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 1685 /* Bonaire */
2f7d10b3
JZ		 1686 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1687 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1688 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1689 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 1690 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1691 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1692 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1693 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1694 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1695 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 1696 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 1697 /* Hawaii */
1698 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1699 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1700 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1701 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1702 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1703 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1704 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1705 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1706 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1707 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1708 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1709 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1710 /* Kabini */
2f7d10b3
JZ		 1711 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1712 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1713 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1714 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1715 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1716 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1717 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1718 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1719 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1720 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1721 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1722 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1723 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1724 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1725 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1726 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 1727 /* mullins */
2f7d10b3
JZ		 1728 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1729 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1730 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1731 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1732 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1733 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1734 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1735 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1736 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1737 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1738 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1739 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1740 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1741 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1742 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1743 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 1744#endif
1256a8b8 1745 /* topaz */
dba280b2
AD		 1746 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1747 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1748 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1749 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1750 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 1751 /* tonga */
1752 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1753 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1754 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1755 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1756 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1757 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1758 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1759 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1760 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 1761 /* fiji */
1762 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 1763 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 1764 /* carrizo */
2f7d10b3
JZ		 1765 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1766 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1767 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1768 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1769 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 1770 /* stoney */
1771 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 1772 /* Polaris11 */
1773 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1774 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1775 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1776 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1777 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1778 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 1779 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1780 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1781 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 1782 /* Polaris10 */
1783 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1784 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1785 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1786 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1787 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 1788 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 1789 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1790 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1791 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1792 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1793 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1794 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
30f3984e 1795 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 1796 /* Polaris12 */
1797 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1798 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1799 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1800 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1801 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 1802 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 1803 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 1804 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
e9307932
LL		 1805 /* VEGAM */
1806 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1807 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
f6653a0e 1808 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
ca2f1cca 1809 /* Vega 10 */
dfbf0c14
AD		 1810 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1811 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1812 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1813 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1814 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1815 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1816 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1817 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1818 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1819 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1820 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1821 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1822 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1823 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1824 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dc53d543
AD		 1825 /* Vega 12 */
1826 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1827 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1828 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1829 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1830 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1204a26e 1831 /* Vega 20 */
6dddaeef
AD		 1832 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1833 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1834 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1835 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
ec5b2020 1836 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
6dddaeef
AD		 1837 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1838 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
df515052 1839 /* Raven */
acc34503 1840 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
741deade 1841 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
48c69cda 1842 /* Arcturus */
12c5365e
AD		 1843 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1844 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1845 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1846 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
bd1c0fdf
AD		 1847 /* Navi10 */
1848 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1849 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1850 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1851 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1852 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1853 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
89428811 1854 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1855 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
26051720 1856 /* Navi14 */
b62d9554
AD		 1857 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1858 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1859 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1860 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
df515052 1861
61bdb39c 1862 /* Renoir */
775da830 1863 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
23fe1390 1864 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
8bf08351 1865 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
278cdb68 1866 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
61bdb39c 1867
10e85054 1868 /* Navi12 */
d34c7b7b
AD		 1869 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1870 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
10e85054 1871
61278d14
LG		 1872 /* Sienna_Cichlid */
1873 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
d26bbbcc 1874 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14
LG		 1875 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1876 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1877 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1878 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1879 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1880 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1881 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1882 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1883 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
ed098aa3 1884 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1885 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
10e85054 1886
894052d6
HR		 1887 /* Van Gogh */
1888 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1889
27f5355f
AL		 1890 /* Yellow Carp */
1891 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1892 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1893
2c1eaddd
TZ		 1894 /* Navy_Flounder */
1895 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1896 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1897 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
8f0c93f4
AD		 1898 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1899 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1900 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1901 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1902 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2c1eaddd
TZ		 1903 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1904
e7de4aee
TZ		 1905 /* DIMGREY_CAVEFISH */
1906 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1907 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1908 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
06ac9b6c 1909 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
8f0c93f4
AD		 1910 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1911 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1912 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1913 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1914 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1915 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1916 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
e7de4aee
TZ		 1917 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1918
4c2e5f51 1919 /* Aldebaran */
3786a9bc
AD		 1920 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1921 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1922 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1923 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
4c2e5f51 1924
a8f70696
TZ		 1925 /* CYAN_SKILLFISH */
1926 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
dfcc3e8c 1927 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
a8f70696 1928
a2e9b166
CG		 1929 /* BEIGE_GOBY */
1930 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1931 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1932 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1933 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1934 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1935
eb4fd29a
AD		 1936 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1937 .class = PCI_CLASS_DISPLAY_VGA << 8,
1938 .class_mask = 0xffffff,
d0761fd2 1939 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a
AD		 1940
1941 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1942 .class = PCI_CLASS_DISPLAY_OTHER << 8,
1943 .class_mask = 0xffffff,
d0761fd2 1944 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a 1945
d38ceaf9
AD		 1946 {0, 0, 0}
1947};
1948
1949MODULE_DEVICE_TABLE(pci, pciidlist);
1950
5088d657 1951static const struct drm_driver amdgpu_kms_driver;
d38ceaf9 1952
b95dc06a
AD		 1953static bool amdgpu_is_fw_framebuffer(resource_size_t base,
1954 resource_size_t size)
1955{
1956 bool found = false;
1957#if IS_REACHABLE(CONFIG_FB)
1958 struct apertures_struct *a;
1959
1960 a = alloc_apertures(1);
1961 if (!a)
1962 return false;
1963
1964 a->ranges[0].base = base;
1965 a->ranges[0].size = size;
1966
1967 found = is_firmware_framebuffer(a);
1968 kfree(a);
1969#endif
1970 return found;
1971}
1972
243c719e 1973static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
d0d66b8c
AD		 1974{
1975 struct pci_dev *p = NULL;
243c719e 1976 int i;
d0d66b8c 1977
243c719e
AD		 1978 /* 0 - GPU
1979 * 1 - audio
1980 * 2 - USB
1981 * 3 - UCSI
1982 */
1983 for (i = 1; i < 4; i++) {
1984 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1985 adev->pdev->bus->number, i);
1986 if (p) {
1987 pm_runtime_get_sync(&p->dev);
1988 pm_runtime_mark_last_busy(&p->dev);
1989 pm_runtime_put_autosuspend(&p->dev);
1990 pci_dev_put(p);
1991 }
d0d66b8c
AD		 1992 }
1993}
1994
d38ceaf9
AD		 1995static int amdgpu_pci_probe(struct pci_dev *pdev,
1996 const struct pci_device_id *ent)
1997{
8aba21b7 1998 struct drm_device *ddev;
c6385e50 1999 struct amdgpu_device *adev;
d38ceaf9 2000 unsigned long flags = ent->driver_data;
bdbeb0dd 2001 int ret, retry = 0, i;
3fa203af 2002 bool supports_atomic = false;
b95dc06a
AD		 2003 bool is_fw_fb;
2004 resource_size_t base, size;
3fa203af 2005
bdbeb0dd
AD		 2006 /* skip devices which are owned by radeon */
2007 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2008 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2009 return -ENODEV;
2010 }
2011
7294863a
ML		 2012 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2013 amdgpu_aspm = 0;
2014
84ec374b 2015 if (amdgpu_virtual_display ||
3fa203af
AD		 2016 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2017 supports_atomic = true;
d38ceaf9 2018
2f7d10b3 2019 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 2020 DRM_INFO("This hardware requires experimental hardware support.\n"
2021 "See modparam exp_hw_support\n");
2022 return -ENODEV;
2023 }
2024
ea68573d
AD		 2025 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2026 * however, SME requires an indirect IOMMU mapping because the encryption
2027 * bit is beyond the DMA mask of the chip.
2028 */
e9d1d2bb
TL		 2029 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2030 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
ea68573d
AD		 2031 dev_info(&pdev->dev,
2032 "SME is not compatible with RAVEN\n");
2033 return -ENOTSUPP;
2034 }
2035
984d7a92
HG		 2036#ifdef CONFIG_DRM_AMDGPU_SI
2037 if (!amdgpu_si_support) {
2038 switch (flags & AMD_ASIC_MASK) {
2039 case CHIP_TAHITI:
2040 case CHIP_PITCAIRN:
2041 case CHIP_VERDE:
2042 case CHIP_OLAND:
2043 case CHIP_HAINAN:
2044 dev_info(&pdev->dev,
2045 "SI support provided by radeon.\n");
2046 dev_info(&pdev->dev,
2047 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2048 );
2049 return -ENODEV;
2050 }
2051 }
2052#endif
2053#ifdef CONFIG_DRM_AMDGPU_CIK
2054 if (!amdgpu_cik_support) {
2055 switch (flags & AMD_ASIC_MASK) {
2056 case CHIP_KAVERI:
2057 case CHIP_BONAIRE:
2058 case CHIP_HAWAII:
2059 case CHIP_KABINI:
2060 case CHIP_MULLINS:
2061 dev_info(&pdev->dev,
2062 "CIK support provided by radeon.\n");
2063 dev_info(&pdev->dev,
2064 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2065 );
2066 return -ENODEV;
2067 }
2068 }
2069#endif
2070
b95dc06a
AD		 2071 base = pci_resource_start(pdev, 0);
2072 size = pci_resource_len(pdev, 0);
2073 is_fw_fb = amdgpu_is_fw_framebuffer(base, size);
2074
d38ceaf9 2075 /* Get rid of things like offb */
97c9bfe3 2076 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
d38ceaf9
AD		 2077 if (ret)
2078 return ret;
2079
5088d657 2080 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
df2ce459
LT		 2081 if (IS_ERR(adev))
2082 return PTR_ERR(adev);
8aba21b7
LT		 2083
2084 adev->dev = &pdev->dev;
2085 adev->pdev = pdev;
2086 ddev = adev_to_drm(adev);
b95dc06a 2087 adev->is_fw_fb = is_fw_fb;
b58c1131 2088
351c4dbe 2089 if (!supports_atomic)
8aba21b7 2090 ddev->driver_features &= ~DRIVER_ATOMIC;
351c4dbe 2091
b58c1131
AD		 2092 ret = pci_enable_device(pdev);
2093 if (ret)
df2ce459 2094 return ret;
b58c1131 2095
8aba21b7 2096 pci_set_drvdata(pdev, ddev);
b58c1131 2097
8aba21b7 2098 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
7504d3bb
LC		 2099 if (ret)
2100 goto err_pci;
c6385e50 2101
1daee8b4 2102retry_init:
8aba21b7 2103 ret = drm_dev_register(ddev, ent->driver_data);
1daee8b4
PD		 2104 if (ret == -EAGAIN && ++retry <= 3) {
2105 DRM_INFO("retry init %d\n", retry);
2106 /* Don't request EX mode too frequently which is attacking */
2107 msleep(5000);
2108 goto retry_init;
8aba21b7 2109 } else if (ret) {
b58c1131 2110 goto err_pci;
8aba21b7 2111 }
b58c1131 2112
087451f3
EQ		 2113 /*
2114 * 1. don't init fbdev on hw without DCE
2115 * 2. don't init fbdev if there are no connectors
2116 */
2117 if (adev->mode_info.mode_config_initialized &&
2118 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2119 /* select 8 bpp console on low vram cards */
2120 if (adev->gmc.real_vram_size <= (32*1024*1024))
2121 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2122 else
2123 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2124 }
2125
c6385e50
AD		 2126 ret = amdgpu_debugfs_init(adev);
2127 if (ret)
2128 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2129
d0d66b8c
AD		 2130 if (adev->runpm) {
2131 /* only need to skip on ATPX */
2132 if (amdgpu_device_supports_px(ddev))
2133 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2134 /* we want direct complete for BOCO */
2135 if (amdgpu_device_supports_boco(ddev))
2136 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2137 DPM_FLAG_SMART_SUSPEND |
2138 DPM_FLAG_MAY_SKIP_RESUME);
2139 pm_runtime_use_autosuspend(ddev->dev);
2140 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2141
2142 pm_runtime_allow(ddev->dev);
2143
2144 pm_runtime_mark_last_busy(ddev->dev);
2145 pm_runtime_put_autosuspend(ddev->dev);
2146
2147 /*
2148 * For runpm implemented via BACO, PMFW will handle the
2149 * timing for BACO in and out:
2150 * - put ASIC into BACO state only when both video and
2151 * audio functions are in D3 state.
2152 * - pull ASIC out of BACO state when either video or
2153 * audio function is in D0 state.
2154 * Also, at startup, PMFW assumes both functions are in
2155 * D0 state.
2156 *
2157 * So if snd driver was loaded prior to amdgpu driver
2158 * and audio function was put into D3 state, there will
2159 * be no PMFW-aware D-state transition(D0->D3) on runpm
2160 * suspend. Thus the BACO will be not correctly kicked in.
2161 *
243c719e 2162 * Via amdgpu_get_secondary_funcs(), the audio dev is put
d0d66b8c
AD		 2163 * into D0 state. Then there will be a PMFW-aware D-state
2164 * transition(D0->D3) on runpm suspend.
2165 */
2166 if (amdgpu_device_supports_baco(ddev) &&
2167 !(adev->flags & AMD_IS_APU) &&
2168 (adev->asic_type >= CHIP_NAVI10))
243c719e 2169 amdgpu_get_secondary_funcs(adev);
d0d66b8c
AD		 2170 }
2171
b58c1131
AD		 2172 return 0;
2173
2174err_pci:
2175 pci_disable_device(pdev);
b58c1131 2176 return ret;
d38ceaf9
AD		 2177}
2178
2179static void
2180amdgpu_pci_remove(struct pci_dev *pdev)
2181{
2182 struct drm_device *dev = pci_get_drvdata(pdev);
d0d66b8c 2183 struct amdgpu_device *adev = drm_to_adev(dev);
d38ceaf9 2184
88b35d83 2185 drm_dev_unplug(dev);
d0d66b8c
AD		 2186
2187 if (adev->runpm) {
2188 pm_runtime_get_sync(dev->dev);
2189 pm_runtime_forbid(dev->dev);
2190 }
2191
c6385e50 2192 amdgpu_driver_unload_kms(dev);
72c8c97b 2193
98c6e6a7
AG		 2194 /*
2195 * Flush any in flight DMA operations from device.
2196 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2197 * StatusTransactions Pending bit.
2198 */
fd4495e5 2199 pci_disable_device(pdev);
98c6e6a7 2200 pci_wait_for_pending_transaction(pdev);
d38ceaf9
AD		 2201}
2202
61e11306
AD		 2203static void
2204amdgpu_pci_shutdown(struct pci_dev *pdev)
2205{
faefba95 2206 struct drm_device *dev = pci_get_drvdata(pdev);
1348969a 2207 struct amdgpu_device *adev = drm_to_adev(dev);
faefba95 2208
7c6e68c7
AG		 2209 if (amdgpu_ras_intr_triggered())
2210 return;
2211
61e11306 2212 /* if we are running in a VM, make sure the device
00ea8cba
AD		 2213 * torn down properly on reboot/shutdown.
2214 * unfortunately we can't detect certain
2215 * hypervisors so just do this all the time.
61e11306 2216 */
05cac1ae
ND		 2217 if (!amdgpu_passthrough(adev))
2218 adev->mp1_state = PP_MP1_STATE_UNLOAD;
cdd61df6 2219 amdgpu_device_ip_suspend(adev);
a3a09142 2220 adev->mp1_state = PP_MP1_STATE_NONE;
61e11306
AD		 2221}
2222
e3c1b071 2223/**
2224 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2225 *
2226 * @work: work_struct.
2227 */
2228static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2229{
2230 struct list_head device_list;
2231 struct amdgpu_device *adev;
2232 int i, r;
04442bf7
LL		 2233 struct amdgpu_reset_context reset_context;
2234
2235 memset(&reset_context, 0, sizeof(reset_context));
e3c1b071 2236
2237 mutex_lock(&mgpu_info.mutex);
2238 if (mgpu_info.pending_reset == true) {
2239 mutex_unlock(&mgpu_info.mutex);
2240 return;
2241 }
2242 mgpu_info.pending_reset = true;
2243 mutex_unlock(&mgpu_info.mutex);
2244
04442bf7
LL		 2245 /* Use a common context, just need to make sure full reset is done */
2246 reset_context.method = AMD_RESET_METHOD_NONE;
2247 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2248
e3c1b071 2249 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2250 adev = mgpu_info.gpu_ins[i].adev;
04442bf7
LL		 2251 reset_context.reset_req_dev = adev;
2252 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
e3c1b071 2253 if (r) {
2254 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2255 r, adev_to_drm(adev)->unique);
2256 }
2257 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2258 r = -EALREADY;
2259 }
2260 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2261 adev = mgpu_info.gpu_ins[i].adev;
e3c1b071 2262 flush_work(&adev->xgmi_reset_work);
050743da 2263 adev->gmc.xgmi.pending_reset = false;
e3c1b071 2264 }
2265
2266 /* reset function will rebuild the xgmi hive info , clear it now */
2267 for (i = 0; i < mgpu_info.num_dgpu; i++)
2268 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2269
2270 INIT_LIST_HEAD(&device_list);
2271
2272 for (i = 0; i < mgpu_info.num_dgpu; i++)
2273 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2274
2275 /* unregister the GPU first, reset function will add them back */
2276 list_for_each_entry(adev, &device_list, reset_list)
2277 amdgpu_unregister_gpu_instance(adev);
2278
04442bf7
LL		 2279 /* Use a common context, just need to make sure full reset is done */
2280 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2281 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2282
e3c1b071 2283 if (r) {
2284 DRM_ERROR("reinit gpus failure");
2285 return;
2286 }
2287 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2288 adev = mgpu_info.gpu_ins[i].adev;
2289 if (!adev->kfd.init_complete)
2290 amdgpu_amdkfd_device_init(adev);
2291 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2292 }
2293 return;
2294}
2295
e25443d2
AD		 2296static int amdgpu_pmops_prepare(struct device *dev)
2297{
2298 struct drm_device *drm_dev = dev_get_drvdata(dev);
d2a197a4 2299 struct amdgpu_device *adev = drm_to_adev(drm_dev);
e25443d2
AD		 2300
2301 /* Return a positive number here so
2302 * DPM_FLAG_SMART_SUSPEND works properly
2303 */
b98c6299 2304 if (amdgpu_device_supports_boco(drm_dev))
9308a49d 2305 return pm_runtime_suspended(dev);
e25443d2 2306
d2a197a4
ML		 2307 /* if we will not support s3 or s2i for the device
2308 * then skip suspend
2309 */
2310 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2311 !amdgpu_acpi_is_s3_active(adev))
2312 return 1;
e25443d2
AD		 2313
2314 return 0;
2315}
2316
2317static void amdgpu_pmops_complete(struct device *dev)
2318{
2319 /* nothing to do */
2320}
2321
d38ceaf9
AD		 2322static int amdgpu_pmops_suspend(struct device *dev)
2323{
911d8b30 2324 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2325 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2326 int r;
74b0b157 2327
d0260f62 2328 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2329 adev->in_s0ix = true;
eac4c54b
ML		 2330 else
2331 adev->in_s3 = true;
62498733 2332 r = amdgpu_device_suspend(drm_dev, true);
daf8de08
AD		 2333 if (r)
2334 return r;
2335 if (!adev->in_s0ix)
2336 r = amdgpu_asic_reset(adev);
62498733 2337 return r;
d38ceaf9
AD		 2338}
2339
2340static int amdgpu_pmops_resume(struct device *dev)
2341{
911d8b30 2342 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2343 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2344 int r;
85e154c2 2345
ebe86a57
AG		 2346 /* Avoids registers access if device is physically gone */
2347 if (!pci_device_is_present(adev->pdev))
2348 adev->no_hw_access = true;
2349
62498733 2350 r = amdgpu_device_resume(drm_dev, true);
d0260f62 2351 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2352 adev->in_s0ix = false;
eac4c54b
ML		 2353 else
2354 adev->in_s3 = false;
62498733 2355 return r;
d38ceaf9
AD		 2356}
2357
2358static int amdgpu_pmops_freeze(struct device *dev)
2359{
911d8b30 2360 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2361 struct amdgpu_device *adev = drm_to_adev(drm_dev);
897483d8 2362 int r;
74b0b157 2363
62498733 2364 adev->in_s4 = true;
de185019 2365 r = amdgpu_device_suspend(drm_dev, true);
62498733 2366 adev->in_s4 = false;
897483d8
AD		 2367 if (r)
2368 return r;
2369 return amdgpu_asic_reset(adev);
d38ceaf9
AD		 2370}
2371
2372static int amdgpu_pmops_thaw(struct device *dev)
2373{
911d8b30 2374 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2375
de185019 2376 return amdgpu_device_resume(drm_dev, true);
74b0b157 2377}
2378
2379static int amdgpu_pmops_poweroff(struct device *dev)
2380{
911d8b30 2381 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2382
62498733 2383 return amdgpu_device_suspend(drm_dev, true);
74b0b157 2384}
2385
2386static int amdgpu_pmops_restore(struct device *dev)
2387{
911d8b30 2388 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2389
de185019 2390 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 2391}
2392
2393static int amdgpu_pmops_runtime_suspend(struct device *dev)
2394{
2395 struct pci_dev *pdev = to_pci_dev(dev);
2396 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2397 struct amdgpu_device *adev = drm_to_adev(drm_dev);
719423f6 2398 int ret, i;
d38ceaf9 2399
6ae6c7d4 2400 if (!adev->runpm) {
d38ceaf9
AD		 2401 pm_runtime_forbid(dev);
2402 return -EBUSY;
2403 }
2404
719423f6
AD		 2405 /* wait for all rings to drain before suspending */
2406 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2407 struct amdgpu_ring *ring = adev->rings[i];
2408 if (ring && ring->sched.ready) {
2409 ret = amdgpu_fence_wait_empty(ring);
2410 if (ret)
2411 return -EBUSY;
2412 }
2413 }
2414
f0f7ddfc 2415 adev->in_runpm = true;
b98c6299 2416 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2417 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
d38ceaf9 2418
7be3be2b
EQ		 2419 /*
2420 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2421 * proper cleanups and put itself into a state ready for PNP. That
2422 * can address some random resuming failure observed on BOCO capable
2423 * platforms.
2424 * TODO: this may be also needed for PX capable platform.
2425 */
2426 if (amdgpu_device_supports_boco(drm_dev))
2427 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2428
de185019 2429 ret = amdgpu_device_suspend(drm_dev, false);
cef8b03b
AD		 2430 if (ret) {
2431 adev->in_runpm = false;
7be3be2b
EQ		 2432 if (amdgpu_device_supports_boco(drm_dev))
2433 adev->mp1_state = PP_MP1_STATE_NONE;
70bedd68 2434 return ret;
cef8b03b 2435 }
70bedd68 2436
7be3be2b
EQ		 2437 if (amdgpu_device_supports_boco(drm_dev))
2438 adev->mp1_state = PP_MP1_STATE_NONE;
2439
b98c6299 2440 if (amdgpu_device_supports_px(drm_dev)) {
562b49fc
AD		 2441 /* Only need to handle PCI state in the driver for ATPX
2442 * PCI core handles it for _PR3.
2443 */
b98c6299
AD		 2444 amdgpu_device_cache_pci_state(pdev);
2445 pci_disable_device(pdev);
2446 pci_ignore_hotplug(pdev);
2447 pci_set_power_state(pdev, PCI_D3cold);
b97e9d47 2448 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
11e612a0
AD		 2449 } else if (amdgpu_device_supports_boco(drm_dev)) {
2450 /* nothing to do */
19134317
AD		 2451 } else if (amdgpu_device_supports_baco(drm_dev)) {
2452 amdgpu_device_baco_enter(drm_dev);
b97e9d47 2453 }
d38ceaf9
AD		 2454
2455 return 0;
2456}
2457
2458static int amdgpu_pmops_runtime_resume(struct device *dev)
2459{
2460 struct pci_dev *pdev = to_pci_dev(dev);
2461 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2462 struct amdgpu_device *adev = drm_to_adev(drm_dev);
d38ceaf9
AD		 2463 int ret;
2464
6ae6c7d4 2465 if (!adev->runpm)
d38ceaf9
AD		 2466 return -EINVAL;
2467
e1543d83
AG		 2468 /* Avoids registers access if device is physically gone */
2469 if (!pci_device_is_present(adev->pdev))
2470 adev->no_hw_access = true;
2471
b98c6299 2472 if (amdgpu_device_supports_px(drm_dev)) {
b97e9d47
AD		 2473 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2474
562b49fc
AD		 2475 /* Only need to handle PCI state in the driver for ATPX
2476 * PCI core handles it for _PR3.
2477 */
b98c6299
AD		 2478 pci_set_power_state(pdev, PCI_D0);
2479 amdgpu_device_load_pci_state(pdev);
2480 ret = pci_enable_device(pdev);
2481 if (ret)
2482 return ret;
637bb036 2483 pci_set_master(pdev);
fd496ca8
AD		 2484 } else if (amdgpu_device_supports_boco(drm_dev)) {
2485 /* Only need to handle PCI state in the driver for ATPX
2486 * PCI core handles it for _PR3.
2487 */
2488 pci_set_master(pdev);
19134317
AD		 2489 } else if (amdgpu_device_supports_baco(drm_dev)) {
2490 amdgpu_device_baco_exit(drm_dev);
b97e9d47 2491 }
de185019 2492 ret = amdgpu_device_resume(drm_dev, false);
b45aeb2d
PKR		 2493 if (ret)
2494 return ret;
2495
b98c6299 2496 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2497 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
f0f7ddfc 2498 adev->in_runpm = false;
d38ceaf9
AD		 2499 return 0;
2500}
2501
2502static int amdgpu_pmops_runtime_idle(struct device *dev)
2503{
911d8b30 2504 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2505 struct amdgpu_device *adev = drm_to_adev(drm_dev);
97f6a21b
AG		 2506 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2507 int ret = 1;
d38ceaf9 2508
6ae6c7d4 2509 if (!adev->runpm) {
d38ceaf9
AD		 2510 pm_runtime_forbid(dev);
2511 return -EBUSY;
2512 }
2513
97f6a21b
AG		 2514 if (amdgpu_device_has_dc_support(adev)) {
2515 struct drm_crtc *crtc;
2516
97f6a21b 2517 drm_for_each_crtc(crtc, drm_dev) {
fb637265
FDF		 2518 drm_modeset_lock(&crtc->mutex, NULL);
2519 if (crtc->state->active)
97f6a21b 2520 ret = -EBUSY;
fb637265
FDF		 2521 drm_modeset_unlock(&crtc->mutex);
2522 if (ret < 0)
97f6a21b 2523 break;
d38ceaf9 2524 }
97f6a21b 2525
97f6a21b
AG		 2526 } else {
2527 struct drm_connector *list_connector;
2528 struct drm_connector_list_iter iter;
2529
2530 mutex_lock(&drm_dev->mode_config.mutex);
2531 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2532
2533 drm_connector_list_iter_begin(drm_dev, &iter);
2534 drm_for_each_connector_iter(list_connector, &iter) {
2535 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2536 ret = -EBUSY;
2537 break;
2538 }
2539 }
2540
2541 drm_connector_list_iter_end(&iter);
2542
2543 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2544 mutex_unlock(&drm_dev->mode_config.mutex);
d38ceaf9
AD		 2545 }
2546
97f6a21b
AG		 2547 if (ret == -EBUSY)
2548 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
2549
d38ceaf9
AD		 2550 pm_runtime_mark_last_busy(dev);
2551 pm_runtime_autosuspend(dev);
97f6a21b 2552 return ret;
d38ceaf9
AD		 2553}
2554
2555long amdgpu_drm_ioctl(struct file *filp,
2556 unsigned int cmd, unsigned long arg)
2557{
2558 struct drm_file *file_priv = filp->private_data;
2559 struct drm_device *dev;
2560 long ret;
2561 dev = file_priv->minor->dev;
2562 ret = pm_runtime_get_sync(dev->dev);
2563 if (ret < 0)
5509ac65 2564 goto out;
d38ceaf9
AD		 2565
2566 ret = drm_ioctl(filp, cmd, arg);
2567
2568 pm_runtime_mark_last_busy(dev->dev);
5509ac65 2569out:
d38ceaf9
AD		 2570 pm_runtime_put_autosuspend(dev->dev);
2571 return ret;
2572}
2573
2574static const struct dev_pm_ops amdgpu_pm_ops = {
e25443d2
AD		 2575 .prepare = amdgpu_pmops_prepare,
2576 .complete = amdgpu_pmops_complete,
d38ceaf9
AD		 2577 .suspend = amdgpu_pmops_suspend,
2578 .resume = amdgpu_pmops_resume,
2579 .freeze = amdgpu_pmops_freeze,
2580 .thaw = amdgpu_pmops_thaw,
74b0b157 2581 .poweroff = amdgpu_pmops_poweroff,
2582 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 2583 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2584 .runtime_resume = amdgpu_pmops_runtime_resume,
2585 .runtime_idle = amdgpu_pmops_runtime_idle,
2586};
2587
48ad368a
AG		 2588static int amdgpu_flush(struct file *f, fl_owner_t id)
2589{
2590 struct drm_file *file_priv = f->private_data;
2591 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
56753e73 2592 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
48ad368a 2593
56753e73
CK		 2594 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2595 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
48ad368a 2596
56753e73 2597 return timeout >= 0 ? 0 : timeout;
48ad368a
AG		 2598}
2599
d38ceaf9
AD		 2600static const struct file_operations amdgpu_driver_kms_fops = {
2601 .owner = THIS_MODULE,
2602 .open = drm_open,
48ad368a 2603 .flush = amdgpu_flush,
d38ceaf9
AD		 2604 .release = drm_release,
2605 .unlocked_ioctl = amdgpu_drm_ioctl,
71df0368 2606 .mmap = drm_gem_mmap,
d38ceaf9
AD		 2607 .poll = drm_poll,
2608 .read = drm_read,
2609#ifdef CONFIG_COMPAT
2610 .compat_ioctl = amdgpu_kms_compat_ioctl,
2611#endif
87444254
RS		 2612#ifdef CONFIG_PROC_FS
2613 .show_fdinfo = amdgpu_show_fdinfo
2614#endif
d38ceaf9
AD		 2615};
2616
021830d2
BN		 2617int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2618{
f3729f7b 2619 struct drm_file *file;
021830d2
BN		 2620
2621 if (!filp)
2622 return -EINVAL;
2623
2624 if (filp->f_op != &amdgpu_driver_kms_fops) {
2625 return -EINVAL;
2626 }
2627
2628 file = filp->private_data;
2629 *fpriv = file->driver_priv;
2630 return 0;
2631}
2632
5088d657
LT		 2633const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2634 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2635 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2636 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2637 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2638 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2639 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2640 /* KMS */
2641 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2642 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2643 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2644 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2645 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2646 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2647 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2648 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2649 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2650 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2651};
2652
2653static const struct drm_driver amdgpu_kms_driver = {
d38ceaf9 2654 .driver_features =
f3ed6739 2655 DRIVER_ATOMIC |
1ff49481 2656 DRIVER_GEM |
db4ff423
CZ		 2657 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2658 DRIVER_SYNCOBJ_TIMELINE,
d38ceaf9 2659 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 2660 .postclose = amdgpu_driver_postclose_kms,
2661 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9 2662 .ioctls = amdgpu_ioctls_kms,
5088d657 2663 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
d38ceaf9
AD		 2664 .dumb_create = amdgpu_mode_dumb_create,
2665 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9 2666 .fops = &amdgpu_driver_kms_fops,
72c8c97b 2667 .release = &amdgpu_driver_release_kms,
d38ceaf9
AD		 2668
2669 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2670 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
09052fc3 2671 .gem_prime_import = amdgpu_gem_prime_import,
71df0368 2672 .gem_prime_mmap = drm_gem_prime_mmap,
d38ceaf9
AD		 2673
2674 .name = DRIVER_NAME,
2675 .desc = DRIVER_DESC,
2676 .date = DRIVER_DATE,
2677 .major = KMS_DRIVER_MAJOR,
2678 .minor = KMS_DRIVER_MINOR,
2679 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2680};
2681
c9a6b82f
AG		 2682static struct pci_error_handlers amdgpu_pci_err_handler = {
2683 .error_detected = amdgpu_pci_error_detected,
2684 .mmio_enabled = amdgpu_pci_mmio_enabled,
2685 .slot_reset = amdgpu_pci_slot_reset,
2686 .resume = amdgpu_pci_resume,
2687};
2688
35bba831
AG		 2689extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2690extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2691extern const struct attribute_group amdgpu_vbios_version_attr_group;
2692
2693static const struct attribute_group *amdgpu_sysfs_groups[] = {
2694 &amdgpu_vram_mgr_attr_group,
2695 &amdgpu_gtt_mgr_attr_group,
2696 &amdgpu_vbios_version_attr_group,
2697 NULL,
2698};
2699
2700
d38ceaf9
AD		 2701static struct pci_driver amdgpu_kms_pci_driver = {
2702 .name = DRIVER_NAME,
2703 .id_table = pciidlist,
2704 .probe = amdgpu_pci_probe,
2705 .remove = amdgpu_pci_remove,
61e11306 2706 .shutdown = amdgpu_pci_shutdown,
d38ceaf9 2707 .driver.pm = &amdgpu_pm_ops,
c9a6b82f 2708 .err_handler = &amdgpu_pci_err_handler,
35bba831 2709 .dev_groups = amdgpu_sysfs_groups,
d38ceaf9
AD		 2710};
2711
2712static int __init amdgpu_init(void)
2713{
245ae5e9
CK		 2714 int r;
2715
6a2d2ddf 2716 if (drm_firmware_drivers_only())
c60e22f7 2717 return -EINVAL;
c60e22f7 2718
245ae5e9
CK		 2719 r = amdgpu_sync_init();
2720 if (r)
2721 goto error_sync;
2722
2723 r = amdgpu_fence_slab_init();
2724 if (r)
2725 goto error_fence;
2726
d38ceaf9 2727 DRM_INFO("amdgpu kernel modesetting enabled.\n");
d38ceaf9 2728 amdgpu_register_atpx_handler();
f9b7f370 2729 amdgpu_acpi_detect();
03a1c08d
FK		 2730
2731 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2732 amdgpu_amdkfd_init();
2733
d38ceaf9 2734 /* let modprobe override vga console setting */
448d1051 2735 return pci_register_driver(&amdgpu_kms_pci_driver);
245ae5e9 2736
245ae5e9
CK		 2737error_fence:
2738 amdgpu_sync_fini();
2739
2740error_sync:
2741 return r;
d38ceaf9
AD		 2742}
2743
2744static void __exit amdgpu_exit(void)
2745{
130e0371 2746 amdgpu_amdkfd_fini();
448d1051 2747 pci_unregister_driver(&amdgpu_kms_pci_driver);
d38ceaf9 2748 amdgpu_unregister_atpx_handler();
257bf15a 2749 amdgpu_sync_fini();
d573de2d 2750 amdgpu_fence_slab_fini();
c7d8b782 2751 mmu_notifier_synchronize();
d38ceaf9
AD		 2752}
2753
2754module_init(amdgpu_init);
2755module_exit(amdgpu_exit);
2756
2757MODULE_AUTHOR(DRIVER_AUTHOR);
2758MODULE_DESCRIPTION(DRIVER_DESC);
2759MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)