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drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
d38ceaf9 25#include <drm/amdgpu_drm.h>
fdf2f6c5 26#include <drm/drm_drv.h>
d38ceaf9 27#include <drm/drm_gem.h>
fdf2f6c5 28#include <drm/drm_vblank.h>
8aba21b7 29#include <drm/drm_managed.h>
d38ceaf9
AD		 30#include "amdgpu_drv.h"
31
32#include <drm/drm_pciids.h>
33#include <linux/console.h>
34#include <linux/module.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
fcd70cd3 37#include <drm/drm_probe_helper.h>
c7d8b782 38#include <linux/mmu_notifier.h>
d38ceaf9
AD		 39
40#include "amdgpu.h"
41#include "amdgpu_irq.h"
2fbd6f94 42#include "amdgpu_dma_buf.h"
d38ceaf9 43
130e0371
OG		 44#include "amdgpu_amdkfd.h"
45
7c6e68c7
AG		 46#include "amdgpu_ras.h"
47
d38ceaf9
AD		 48/*
49 * KMS wrapper.
50 * - 3.0.0 - initial driver
6055f37a 51 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 52 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
53 * at the end of IBs.
d347ce66 54 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 55 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 56 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 57 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 58 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 59 * - 3.8.0 - Add support raster config init in the kernel
ef704318 60 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 61 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 62 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 63 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 64 * - 3.13.0 - Add PRT support
203eb0cb 65 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 66 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 67 * - 3.16.0 - Add reserved vmid support
68e2c5ff 68 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 69 * - 3.18.0 - Export gpu always on cu bitmap
33476319 70 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 71 * - 3.20.0 - Add support for local BOs
7ca24cf2 72 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 73 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 74 * - 3.23.0 - Add query for VRAM lost counter
f8e3e0ee 75 * - 3.24.0 - Add high priority compute support for gfx9
7b158d16 76 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
d240cd9e 77 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
964d0fbf 78 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
67dd1a36 79 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
41cca166 80 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
767e06a9 81 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
df8368be 82 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
1afeb314 83 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
635e2c5f 84 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
965ebe3d 85 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
815fb4c9 86 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
664fe85a 87 * - 3.36.0 - Allow reading more status registers on si/cik
ff532461 88 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
43c8546b 89 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
174b328b 90 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
16c642ec 91 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
d38ceaf9
AD		 92 */
93#define KMS_DRIVER_MAJOR 3
16c642ec 94#define KMS_DRIVER_MINOR 40
d38ceaf9
AD		 95#define KMS_DRIVER_PATCHLEVEL 0
96
97int amdgpu_vram_limit = 0;
218b5dcd 98int amdgpu_vis_vram_limit = 0;
83e74db6 99int amdgpu_gart_size = -1; /* auto */
36d38372 100int amdgpu_gtt_size = -1; /* auto */
95844d20 101int amdgpu_moverate = -1; /* auto */
d38ceaf9
AD		 102int amdgpu_benchmarking = 0;
103int amdgpu_testing = 0;
104int amdgpu_audio = -1;
105int amdgpu_disp_priority = 0;
106int amdgpu_hw_i2c = 0;
107int amdgpu_pcie_gen2 = -1;
108int amdgpu_msi = -1;
f440ff44 109char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
d38ceaf9 110int amdgpu_dpm = -1;
e635ee07 111int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 112int amdgpu_aspm = -1;
113int amdgpu_runtime_pm = -1;
0b693f0b 114uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9
AD		 115int amdgpu_bapm = -1;
116int amdgpu_deep_color = 0;
bab4fee7 117int amdgpu_vm_size = -1;
d07f14be 118int amdgpu_vm_fragment_size = -1;
d38ceaf9 119int amdgpu_vm_block_size = -1;
d9c13156 120int amdgpu_vm_fault_stop = 0;
b495bd3a 121int amdgpu_vm_debug = 0;
9a4b7d4c 122int amdgpu_vm_update_mode = -1;
d38ceaf9 123int amdgpu_exp_hw_support = 0;
4562236b 124int amdgpu_dc = -1;
b70f014d 125int amdgpu_sched_jobs = 32;
4afcb303 126int amdgpu_sched_hw_submission = 2;
0b693f0b
RZ		 127uint amdgpu_pcie_gen_cap = 0;
128uint amdgpu_pcie_lane_cap = 0;
129uint amdgpu_cg_mask = 0xffffffff;
130uint amdgpu_pg_mask = 0xffffffff;
131uint amdgpu_sdma_phase_quantum = 32;
6f8941a2 132char *amdgpu_disable_cu = NULL;
9accf2fd 133char *amdgpu_virtual_display = NULL;
00544006
HR		 134/* OverDrive(bit 14) disabled by default*/
135uint amdgpu_pp_feature_mask = 0xffffbfff;
367039bf 136uint amdgpu_force_long_training = 0;
65781c78 137int amdgpu_job_hang_limit = 0;
e8835e0e 138int amdgpu_lbpw = -1;
4a75aefe 139int amdgpu_compute_multipipe = -1;
dcebf026 140int amdgpu_gpu_recovery = -1; /* auto */
bfca0289 141int amdgpu_emu_mode = 0;
7951e376 142uint amdgpu_smu_memory_pool_size = 0;
7875a226
AD		 143/* FBC (bit 0) disabled by default*/
144uint amdgpu_dc_feature_mask = 0;
8a791dab 145uint amdgpu_dc_debug_mask = 0;
5bfca069 146int amdgpu_async_gfx_ring = 1;
b239c017 147int amdgpu_mcbp = 0;
63e2fef6 148int amdgpu_discovery = -1;
38487284 149int amdgpu_mes = 0;
d5cc02d9 150int amdgpu_noretry = -1;
4e66d7d2 151int amdgpu_force_asic_type = -1;
d7ccb38d 152int amdgpu_tmz = 0;
273da6ff 153int amdgpu_reset_method = -1; /* auto */
a300de40 154int amdgpu_num_kcq = -1;
7875a226 155
62d73fbc
EQ		 156struct amdgpu_mgpu_info mgpu_info = {
157 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
158};
1218252f 159int amdgpu_ras_enable = -1;
e53aec7e 160uint amdgpu_ras_mask = 0xffffffff;
acc0204c 161int amdgpu_bad_page_threshold = -1;
d38ceaf9 162
8405cf39
SJ		 163/**
164 * DOC: vramlimit (int)
165 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
166 */
d38ceaf9
AD		 167MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
168module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
169
8405cf39
SJ		 170/**
171 * DOC: vis_vramlimit (int)
172 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
173 */
218b5dcd
JB		 174MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
175module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
176
8405cf39
SJ		 177/**
178 * DOC: gartsize (uint)
179 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
180 */
a4da14cc 181MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 182module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 183
8405cf39
SJ		 184/**
185 * DOC: gttsize (int)
186 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
187 * otherwise 3/4 RAM size).
188 */
36d38372
CK		 189MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
190module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 191
8405cf39
SJ		 192/**
193 * DOC: moverate (int)
194 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
195 */
95844d20
MO		 196MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
197module_param_named(moverate, amdgpu_moverate, int, 0600);
198
8405cf39
SJ		 199/**
200 * DOC: benchmark (int)
201 * Run benchmarks. The default is 0 (Skip benchmarks).
202 */
d38ceaf9
AD		 203MODULE_PARM_DESC(benchmark, "Run benchmark");
204module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
205
8405cf39
SJ		 206/**
207 * DOC: test (int)
208 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
209 */
d38ceaf9
AD		 210MODULE_PARM_DESC(test, "Run tests");
211module_param_named(test, amdgpu_testing, int, 0444);
212
8405cf39
SJ		 213/**
214 * DOC: audio (int)
215 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
216 */
d38ceaf9
AD		 217MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
218module_param_named(audio, amdgpu_audio, int, 0444);
219
8405cf39
SJ		 220/**
221 * DOC: disp_priority (int)
222 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
223 */
d38ceaf9
AD		 224MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
225module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
226
8405cf39
SJ		 227/**
228 * DOC: hw_i2c (int)
229 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
230 */
d38ceaf9
AD		 231MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
232module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
233
8405cf39
SJ		 234/**
235 * DOC: pcie_gen2 (int)
236 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
237 */
d38ceaf9
AD		 238MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
239module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
240
8405cf39
SJ		 241/**
242 * DOC: msi (int)
243 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
244 */
d38ceaf9
AD		 245MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
246module_param_named(msi, amdgpu_msi, int, 0444);
247
8405cf39 248/**
912dfc84
EQ		 249 * DOC: lockup_timeout (string)
250 * Set GPU scheduler timeout value in ms.
251 *
252 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
253 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
879e723d
AZ		 254 * to the default timeout.
255 *
256 * - With one value specified, the setting will apply to all non-compute jobs.
257 * - With multiple values specified, the first one will be for GFX.
258 * The second one is for Compute. The third and fourth ones are
259 * for SDMA and Video.
260 *
912dfc84
EQ		 261 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
262 * jobs is 10000. And there is no timeout enforced on compute jobs.
263 */
bcccee89
ED		 264MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
265 "for passthrough or sriov, 10000 for all jobs."
71cc9ef3 266 " 0: keep default value. negative: infinity timeout), "
bcccee89
ED		 267 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
268 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
912dfc84 269module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
d38ceaf9 270
8405cf39
SJ		 271/**
272 * DOC: dpm (int)
54b998ca
HZ		 273 * Override for dynamic power management setting
274 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20)
275 * The default is -1 (auto).
8405cf39 276 */
d38ceaf9
AD		 277MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
278module_param_named(dpm, amdgpu_dpm, int, 0444);
279
8405cf39
SJ		 280/**
281 * DOC: fw_load_type (int)
282 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
283 */
e635ee07
HR		 284MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
285module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9 286
8405cf39
SJ		 287/**
288 * DOC: aspm (int)
289 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
290 */
d38ceaf9
AD		 291MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
292module_param_named(aspm, amdgpu_aspm, int, 0444);
293
8405cf39
SJ		 294/**
295 * DOC: runpm (int)
296 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
297 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
298 */
d38ceaf9
AD		 299MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
300module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
301
8405cf39
SJ		 302/**
303 * DOC: ip_block_mask (uint)
304 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
305 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
306 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
307 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
308 */
d38ceaf9
AD		 309MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
310module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
311
8405cf39
SJ		 312/**
313 * DOC: bapm (int)
314 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
315 * The default -1 (auto, enabled)
316 */
d38ceaf9
AD		 317MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
318module_param_named(bapm, amdgpu_bapm, int, 0444);
319
8405cf39
SJ		 320/**
321 * DOC: deep_color (int)
322 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
323 */
d38ceaf9
AD		 324MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
325module_param_named(deep_color, amdgpu_deep_color, int, 0444);
326
8405cf39
SJ		 327/**
328 * DOC: vm_size (int)
329 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
330 */
ed885b21 331MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 332module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be 333
8405cf39
SJ		 334/**
335 * DOC: vm_fragment_size (int)
336 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
337 */
d07f14be
RH		 338MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
339module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9 340
8405cf39
SJ		 341/**
342 * DOC: vm_block_size (int)
343 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
344 */
d38ceaf9
AD		 345MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
346module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
347
8405cf39
SJ		 348/**
349 * DOC: vm_fault_stop (int)
350 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
351 */
d9c13156
CK		 352MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
353module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
354
8405cf39
SJ		 355/**
356 * DOC: vm_debug (int)
357 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
358 */
b495bd3a
CK		 359MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
360module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
361
8405cf39
SJ		 362/**
363 * DOC: vm_update_mode (int)
364 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
365 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
366 */
9a4b7d4c
HK		 367MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
368module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
369
8405cf39
SJ		 370/**
371 * DOC: exp_hw_support (int)
372 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
373 */
d38ceaf9
AD		 374MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
375module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
376
8405cf39
SJ		 377/**
378 * DOC: dc (int)
379 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
380 */
4562236b
HW		 381MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
382module_param_named(dc, amdgpu_dc, int, 0444);
383
8405cf39
SJ		 384/**
385 * DOC: sched_jobs (int)
386 * Override the max number of jobs supported in the sw queue. The default is 32.
387 */
b70f014d 388MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 389module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
390
8405cf39
SJ		 391/**
392 * DOC: sched_hw_submission (int)
393 * Override the max number of HW submissions. The default is 2.
394 */
4afcb303
JZ		 395MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
396module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
397
8405cf39 398/**
7427a7a0 399 * DOC: ppfeaturemask (hexint)
8405cf39
SJ		 400 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
401 * The default is the current set of stable power features.
402 */
5141e9d2 403MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
7427a7a0 404module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
3a74f6f2 405
367039bf
TY		 406/**
407 * DOC: forcelongtraining (uint)
408 * Force long memory training in resume.
409 * The default is zero, indicates short training in resume.
410 */
411MODULE_PARM_DESC(forcelongtraining, "force memory long training");
412module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
413
8405cf39
SJ		 414/**
415 * DOC: pcie_gen_cap (uint)
416 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
417 * The default is 0 (automatic for each asic).
418 */
cd474ba0
AD		 419MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
420module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
421
8405cf39
SJ		 422/**
423 * DOC: pcie_lane_cap (uint)
424 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
425 * The default is 0 (automatic for each asic).
426 */
cd474ba0
AD		 427MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
428module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
429
8405cf39
SJ		 430/**
431 * DOC: cg_mask (uint)
432 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
433 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
434 */
395d1fb9
NH		 435MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
436module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
437
8405cf39
SJ		 438/**
439 * DOC: pg_mask (uint)
440 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
441 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
442 */
395d1fb9
NH		 443MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
444module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
445
8405cf39
SJ		 446/**
447 * DOC: sdma_phase_quantum (uint)
448 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
449 */
a667386c
FK		 450MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
451module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
452
8405cf39
SJ		 453/**
454 * DOC: disable_cu (charp)
455 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
456 */
6f8941a2
NH		 457MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
458module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
459
8405cf39
SJ		 460/**
461 * DOC: virtual_display (charp)
462 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
463 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
464 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
465 * device at 26:00.0. The default is NULL.
466 */
0f66356d
ED		 467MODULE_PARM_DESC(virtual_display,
468 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 469module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 470
8405cf39
SJ		 471/**
472 * DOC: job_hang_limit (int)
473 * Set how much time allow a job hang and not drop it. The default is 0.
474 */
65781c78
ML		 475MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
476module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
477
8405cf39
SJ		 478/**
479 * DOC: lbpw (int)
480 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
481 */
e8835e0e
HZ		 482MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
483module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 484
4a75aefe
AR		 485MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
486module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
487
8405cf39
SJ		 488/**
489 * DOC: gpu_recovery (int)
490 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
491 */
d869ae09 492MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
dcebf026
AG		 493module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
494
8405cf39
SJ		 495/**
496 * DOC: emu_mode (int)
497 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
498 */
d869ae09 499MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
bfca0289
SL		 500module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
501
1218252f 502/**
2f3940e9 503 * DOC: ras_enable (int)
1218252f 504 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
505 */
2f3940e9 506MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
1218252f 507module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
508
509/**
2f3940e9 510 * DOC: ras_mask (uint)
1218252f 511 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
512 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
513 */
2f3940e9 514MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
1218252f 515module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
516
8405cf39
SJ		 517/**
518 * DOC: si_support (int)
519 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
520 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
521 * otherwise using amdgpu driver.
522 */
6dd13096 523#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56
MD		 524
525#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
6dd13096
FK		 526int amdgpu_si_support = 0;
527MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 528#else
529int amdgpu_si_support = 1;
530MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
531#endif
532
6dd13096
FK		 533module_param_named(si_support, amdgpu_si_support, int, 0444);
534#endif
535
8405cf39
SJ		 536/**
537 * DOC: cik_support (int)
538 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
539 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
540 * otherwise using amdgpu driver.
541 */
7df28986 542#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56
MD		 543
544#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
2b059658
MD		 545int amdgpu_cik_support = 0;
546MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 547#else
548int amdgpu_cik_support = 1;
549MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
550#endif
551
7df28986
FK		 552module_param_named(cik_support, amdgpu_cik_support, int, 0444);
553#endif
554
8405cf39
SJ		 555/**
556 * DOC: smu_memory_pool_size (uint)
557 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
558 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
559 */
7951e376
RZ		 560MODULE_PARM_DESC(smu_memory_pool_size,
561 "reserve gtt for smu debug usage, 0 = disable,"
562 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
563module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
564
51bcce46
HZ		 565/**
566 * DOC: async_gfx_ring (int)
567 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
568 */
569MODULE_PARM_DESC(async_gfx_ring,
5bfca069 570 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
51bcce46
HZ		 571module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
572
40562787
AD		 573/**
574 * DOC: mcbp (int)
575 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
576 */
b239c017
JX		 577MODULE_PARM_DESC(mcbp,
578 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
579module_param_named(mcbp, amdgpu_mcbp, int, 0444);
580
40562787
AD		 581/**
582 * DOC: discovery (int)
583 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
63e2fef6 584 * (-1 = auto (default), 0 = disabled, 1 = enabled)
40562787 585 */
a190d1c7
XY		 586MODULE_PARM_DESC(discovery,
587 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
588module_param_named(discovery, amdgpu_discovery, int, 0444);
589
40562787
AD		 590/**
591 * DOC: mes (int)
592 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
593 * (0 = disabled (default), 1 = enabled)
594 */
38487284
JX		 595MODULE_PARM_DESC(mes,
596 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
597module_param_named(mes, amdgpu_mes, int, 0444);
598
d5cc02d9
AD		 599/**
600 * DOC: noretry (int)
601 * Disable retry faults in the GPU memory controller.
602 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
603 */
75ee6487 604MODULE_PARM_DESC(noretry,
d5cc02d9 605 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
75ee6487
FK		 606module_param_named(noretry, amdgpu_noretry, int, 0644);
607
4e66d7d2
YZ		 608/**
609 * DOC: force_asic_type (int)
610 * A non negative value used to specify the asic type for all supported GPUs.
611 */
612MODULE_PARM_DESC(force_asic_type,
613 "A non negative value used to specify the asic type for all supported GPUs");
614module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
615
616
617
2690262e 618#ifdef CONFIG_HSA_AMD
521fb7d0
AL		 619/**
620 * DOC: sched_policy (int)
621 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
622 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
623 * assigns queues to HQDs.
624 */
2690262e 625int sched_policy = KFD_SCHED_POLICY_HWS;
521fb7d0
AL		 626module_param(sched_policy, int, 0444);
627MODULE_PARM_DESC(sched_policy,
628 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
629
630/**
631 * DOC: hws_max_conc_proc (int)
632 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
633 * number of VMIDs assigned to the HWS, which is also the default.
634 */
2690262e 635int hws_max_conc_proc = 8;
521fb7d0
AL		 636module_param(hws_max_conc_proc, int, 0444);
637MODULE_PARM_DESC(hws_max_conc_proc,
638 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
639
640/**
641 * DOC: cwsr_enable (int)
642 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
643 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
644 * disables it.
645 */
2690262e 646int cwsr_enable = 1;
521fb7d0
AL		 647module_param(cwsr_enable, int, 0444);
648MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
649
650/**
651 * DOC: max_num_of_queues_per_device (int)
652 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
653 * is 4096.
654 */
2690262e 655int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
521fb7d0
AL		 656module_param(max_num_of_queues_per_device, int, 0444);
657MODULE_PARM_DESC(max_num_of_queues_per_device,
658 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
659
660/**
661 * DOC: send_sigterm (int)
662 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
663 * but just print errors on dmesg. Setting 1 enables sending sigterm.
664 */
2690262e 665int send_sigterm;
521fb7d0
AL		 666module_param(send_sigterm, int, 0444);
667MODULE_PARM_DESC(send_sigterm,
668 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
669
670/**
671 * DOC: debug_largebar (int)
672 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
673 * system. This limits the VRAM size reported to ROCm applications to the visible
674 * size, usually 256MB.
675 * Default value is 0, diabled.
676 */
2690262e 677int debug_largebar;
521fb7d0
AL		 678module_param(debug_largebar, int, 0444);
679MODULE_PARM_DESC(debug_largebar,
680 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
681
682/**
683 * DOC: ignore_crat (int)
684 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
685 * table to get information about AMD APUs. This option can serve as a workaround on
686 * systems with a broken CRAT table.
6127896f
HR		 687 *
688 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
689 * whehter use CRAT)
521fb7d0 690 */
2690262e 691int ignore_crat;
521fb7d0
AL		 692module_param(ignore_crat, int, 0444);
693MODULE_PARM_DESC(ignore_crat,
6127896f 694 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
521fb7d0 695
521fb7d0
AL		 696/**
697 * DOC: halt_if_hws_hang (int)
698 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
699 * Setting 1 enables halt on hang.
700 */
2690262e 701int halt_if_hws_hang;
521fb7d0
AL		 702module_param(halt_if_hws_hang, int, 0644);
703MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
29e76462
OZ		 704
705/**
706 * DOC: hws_gws_support(bool)
29633d0e
JG		 707 * Assume that HWS supports GWS barriers regardless of what firmware version
708 * check says. Default value: false (rely on MEC2 firmware version check).
29e76462
OZ		 709 */
710bool hws_gws_support;
711module_param(hws_gws_support, bool, 0444);
29633d0e 712MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
14328aa5
PC		 713
714/**
715 * DOC: queue_preemption_timeout_ms (int)
716 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
717 */
f51af435 718int queue_preemption_timeout_ms = 9000;
14328aa5
PC		 719module_param(queue_preemption_timeout_ms, int, 0644);
720MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
b2057956
FK		 721
722/**
723 * DOC: debug_evictions(bool)
724 * Enable extra debug messages to help determine the cause of evictions
725 */
726bool debug_evictions;
727module_param(debug_evictions, bool, 0644);
728MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
b80f050f
PY		 729
730/**
731 * DOC: no_system_mem_limit(bool)
732 * Disable system memory limit, to support multiple process shared memory
733 */
734bool no_system_mem_limit;
735module_param(no_system_mem_limit, bool, 0644);
736MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
737
2690262e 738#endif
521fb7d0 739
7875a226
AD		 740/**
741 * DOC: dcfeaturemask (uint)
742 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
743 * The default is the current set of stable display features.
744 */
745MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
746module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
747
8a791dab
HW		 748/**
749 * DOC: dcdebugmask (uint)
750 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
751 */
752MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
753module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
754
ad4de27f
NK		 755/**
756 * DOC: abmlevel (uint)
757 * Override the default ABM (Adaptive Backlight Management) level used for DC
758 * enabled hardware. Requires DMCU to be supported and loaded.
759 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
760 * default. Values 1-4 control the maximum allowable brightness reduction via
761 * the ABM algorithm, with 1 being the least reduction and 4 being the most
762 * reduction.
763 *
764 * Defaults to 0, or disabled. Userspace can still override this level later
765 * after boot.
766 */
767uint amdgpu_dm_abm_level = 0;
768MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
769module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
770
d7ccb38d
HR		 771/**
772 * DOC: tmz (int)
773 * Trusted Memory Zone (TMZ) is a method to protect data being written
774 * to or read from memory.
775 *
776 * The default value: 0 (off). TODO: change to auto till it is completed.
777 */
778MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)");
779module_param_named(tmz, amdgpu_tmz, int, 0444);
780
273da6ff
WS		 781/**
782 * DOC: reset_method (int)
783 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
784 */
785MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)");
786module_param_named(reset_method, amdgpu_reset_method, int, 0444);
787
acc0204c
GC		 788/**
789 * DOC: bad_page_threshold (int)
790 * Bad page threshold is to specify the threshold value of faulty pages
791 * detected by RAS ECC, that may result in GPU entering bad status if total
792 * faulty pages by ECC exceed threshold value and leave it for user's further
793 * check.
794 */
795MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)");
796module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
797
a300de40
ML		 798MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
799module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
800
f498d9ed 801static const struct pci_device_id pciidlist[] = {
78fbb685
KW		 802#ifdef CONFIG_DRM_AMDGPU_SI
803 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
804 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
805 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
806 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
807 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
808 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
809 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
810 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
811 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
812 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
813 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
814 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
815 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
816 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
817 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
818 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
819 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
820 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
821 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
822 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
823 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
824 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
825 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
826 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
827 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
828 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
829 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
830 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
831 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
832 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
833 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
834 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
835 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
836 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
837 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
838 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
839 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
840 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
841 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
842 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
843 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
844 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
845 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
846 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
847 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
848 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
849 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
850 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
851 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
852 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
853 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
854 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
855 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
856 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
857 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
858 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
859 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
860 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
861 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
862 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
863 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
864 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
865 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
866 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
867 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
868 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
869 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
870 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
871 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
872 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
873 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
874 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
875#endif
89330c39
AD		 876#ifdef CONFIG_DRM_AMDGPU_CIK
877 /* Kaveri */
2f7d10b3
JZ		 878 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
879 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
880 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
881 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
882 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
883 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
884 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
885 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
886 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
887 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
888 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
889 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
890 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
891 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
892 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
893 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
894 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
895 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
896 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
897 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
898 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
899 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 900 /* Bonaire */
2f7d10b3
JZ		 901 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
902 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
903 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
904 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 905 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
906 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
907 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
908 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
909 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
910 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 911 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 912 /* Hawaii */
913 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
914 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
915 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
916 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
917 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
918 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
919 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
920 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
921 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
922 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
923 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
924 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
925 /* Kabini */
2f7d10b3
JZ		 926 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
927 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
928 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
929 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
930 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
931 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
932 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
933 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
934 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
935 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
936 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
937 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
938 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
939 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
940 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
941 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 942 /* mullins */
2f7d10b3
JZ		 943 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
944 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
945 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
946 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
947 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
948 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
949 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
950 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
951 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
952 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
953 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
954 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
955 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
956 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
957 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
958 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 959#endif
1256a8b8 960 /* topaz */
dba280b2
AD		 961 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
962 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
963 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
964 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
965 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 966 /* tonga */
967 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
968 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
969 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 970 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 971 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
972 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 973 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 974 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
975 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 976 /* fiji */
977 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 978 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 979 /* carrizo */
2f7d10b3
JZ		 980 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
981 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
982 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
983 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
984 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 985 /* stoney */
986 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 987 /* Polaris11 */
988 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 989 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 990 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 991 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 992 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 993 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 994 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
995 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
996 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 997 /* Polaris10 */
998 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 999 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1000 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1001 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1002 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 1003 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 1004 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1005 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1006 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1007 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1008 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1009 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
30f3984e 1010 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 1011 /* Polaris12 */
1012 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1013 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1014 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1015 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1016 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 1017 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 1018 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 1019 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
e9307932
LL		 1020 /* VEGAM */
1021 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1022 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
f6653a0e 1023 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
ca2f1cca 1024 /* Vega 10 */
dfbf0c14
AD		 1025 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1026 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1027 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1028 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1029 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1030 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1031 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1032 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1033 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1034 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1035 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1036 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1037 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1038 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1039 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dc53d543
AD		 1040 /* Vega 12 */
1041 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1042 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1043 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1044 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1045 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1204a26e 1046 /* Vega 20 */
6dddaeef
AD		 1047 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1048 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1049 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1050 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
ec5b2020 1051 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
6dddaeef
AD		 1052 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1053 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
df515052 1054 /* Raven */
acc34503 1055 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
741deade 1056 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
48c69cda 1057 /* Arcturus */
a08a4dae
AD		 1058 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1059 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1060 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
ea207b29 1061 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
bd1c0fdf
AD		 1062 /* Navi10 */
1063 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1064 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1065 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1066 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1067 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1068 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1069 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
26051720 1070 /* Navi14 */
b62d9554
AD		 1071 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1072 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1073 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1074 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
df515052 1075
61bdb39c 1076 /* Renoir */
23fe1390 1077 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
61bdb39c 1078
10e85054 1079 /* Navi12 */
d34c7b7b
AD		 1080 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1081 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
10e85054 1082
61278d14
LG		 1083 /* Sienna_Cichlid */
1084 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1085 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1086 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1087 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1088 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1089 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1090
d38ceaf9
AD		 1091 {0, 0, 0}
1092};
1093
1094MODULE_DEVICE_TABLE(pci, pciidlist);
1095
1096static struct drm_driver kms_driver;
1097
d38ceaf9
AD		 1098static int amdgpu_pci_probe(struct pci_dev *pdev,
1099 const struct pci_device_id *ent)
1100{
8aba21b7 1101 struct drm_device *ddev;
c6385e50 1102 struct amdgpu_device *adev;
d38ceaf9 1103 unsigned long flags = ent->driver_data;
1daee8b4 1104 int ret, retry = 0;
3fa203af
AD		 1105 bool supports_atomic = false;
1106
1107 if (!amdgpu_virtual_display &&
1108 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1109 supports_atomic = true;
d38ceaf9 1110
2f7d10b3 1111 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 1112 DRM_INFO("This hardware requires experimental hardware support.\n"
1113 "See modparam exp_hw_support\n");
1114 return -ENODEV;
1115 }
1116
ea68573d
AD		 1117 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
1118 * however, SME requires an indirect IOMMU mapping because the encryption
1119 * bit is beyond the DMA mask of the chip.
1120 */
1121 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
1122 dev_info(&pdev->dev,
1123 "SME is not compatible with RAVEN\n");
1124 return -ENOTSUPP;
1125 }
1126
984d7a92
HG		 1127#ifdef CONFIG_DRM_AMDGPU_SI
1128 if (!amdgpu_si_support) {
1129 switch (flags & AMD_ASIC_MASK) {
1130 case CHIP_TAHITI:
1131 case CHIP_PITCAIRN:
1132 case CHIP_VERDE:
1133 case CHIP_OLAND:
1134 case CHIP_HAINAN:
1135 dev_info(&pdev->dev,
1136 "SI support provided by radeon.\n");
1137 dev_info(&pdev->dev,
1138 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1139 );
1140 return -ENODEV;
1141 }
1142 }
1143#endif
1144#ifdef CONFIG_DRM_AMDGPU_CIK
1145 if (!amdgpu_cik_support) {
1146 switch (flags & AMD_ASIC_MASK) {
1147 case CHIP_KAVERI:
1148 case CHIP_BONAIRE:
1149 case CHIP_HAWAII:
1150 case CHIP_KABINI:
1151 case CHIP_MULLINS:
1152 dev_info(&pdev->dev,
1153 "CIK support provided by radeon.\n");
1154 dev_info(&pdev->dev,
1155 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1156 );
1157 return -ENODEV;
1158 }
1159 }
1160#endif
1161
d38ceaf9 1162 /* Get rid of things like offb */
35616a4a 1163 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb");
d38ceaf9
AD		 1164 if (ret)
1165 return ret;
1166
df2ce459
LT		 1167 adev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*adev), ddev);
1168 if (IS_ERR(adev))
1169 return PTR_ERR(adev);
8aba21b7
LT		 1170
1171 adev->dev = &pdev->dev;
1172 adev->pdev = pdev;
1173 ddev = adev_to_drm(adev);
b58c1131 1174
351c4dbe 1175 if (!supports_atomic)
8aba21b7 1176 ddev->driver_features &= ~DRIVER_ATOMIC;
351c4dbe 1177
b58c1131
AD		 1178 ret = pci_enable_device(pdev);
1179 if (ret)
df2ce459 1180 return ret;
b58c1131 1181
8aba21b7
LT		 1182 ddev->pdev = pdev;
1183 pci_set_drvdata(pdev, ddev);
b58c1131 1184
8aba21b7 1185 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
7504d3bb
LC		 1186 if (ret)
1187 goto err_pci;
c6385e50 1188
1daee8b4 1189retry_init:
8aba21b7 1190 ret = drm_dev_register(ddev, ent->driver_data);
1daee8b4
PD		 1191 if (ret == -EAGAIN && ++retry <= 3) {
1192 DRM_INFO("retry init %d\n", retry);
1193 /* Don't request EX mode too frequently which is attacking */
1194 msleep(5000);
1195 goto retry_init;
8aba21b7 1196 } else if (ret) {
b58c1131 1197 goto err_pci;
8aba21b7 1198 }
b58c1131 1199
c6385e50
AD		 1200 ret = amdgpu_debugfs_init(adev);
1201 if (ret)
1202 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
1203
b58c1131
AD		 1204 return 0;
1205
1206err_pci:
1207 pci_disable_device(pdev);
b58c1131 1208 return ret;
d38ceaf9
AD		 1209}
1210
1211static void
1212amdgpu_pci_remove(struct pci_dev *pdev)
1213{
1214 struct drm_device *dev = pci_get_drvdata(pdev);
1215
56f074d8
CK		 1216#ifdef MODULE
1217 if (THIS_MODULE->state != MODULE_STATE_GOING)
1218#endif
1219 DRM_ERROR("Hotplug removal is not supported\n");
88b35d83 1220 drm_dev_unplug(dev);
c6385e50 1221 amdgpu_driver_unload_kms(dev);
fd4495e5
XY		 1222 pci_disable_device(pdev);
1223 pci_set_drvdata(pdev, NULL);
d38ceaf9
AD		 1224}
1225
61e11306
AD		 1226static void
1227amdgpu_pci_shutdown(struct pci_dev *pdev)
1228{
faefba95 1229 struct drm_device *dev = pci_get_drvdata(pdev);
1348969a 1230 struct amdgpu_device *adev = drm_to_adev(dev);
faefba95 1231
7c6e68c7
AG		 1232 if (amdgpu_ras_intr_triggered())
1233 return;
1234
61e11306 1235 /* if we are running in a VM, make sure the device
00ea8cba
AD		 1236 * torn down properly on reboot/shutdown.
1237 * unfortunately we can't detect certain
1238 * hypervisors so just do this all the time.
61e11306 1239 */
05cac1ae
ND		 1240 if (!amdgpu_passthrough(adev))
1241 adev->mp1_state = PP_MP1_STATE_UNLOAD;
cdd61df6 1242 amdgpu_device_ip_suspend(adev);
a3a09142 1243 adev->mp1_state = PP_MP1_STATE_NONE;
61e11306
AD		 1244}
1245
d38ceaf9
AD		 1246static int amdgpu_pmops_suspend(struct device *dev)
1247{
911d8b30 1248 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 1249
de185019 1250 return amdgpu_device_suspend(drm_dev, true);
d38ceaf9
AD		 1251}
1252
1253static int amdgpu_pmops_resume(struct device *dev)
1254{
911d8b30 1255 struct drm_device *drm_dev = dev_get_drvdata(dev);
85e154c2 1256
de185019 1257 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 1258}
1259
1260static int amdgpu_pmops_freeze(struct device *dev)
1261{
911d8b30 1262 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 1263 struct amdgpu_device *adev = drm_to_adev(drm_dev);
897483d8 1264 int r;
74b0b157 1265
85625e64 1266 adev->in_hibernate = true;
de185019 1267 r = amdgpu_device_suspend(drm_dev, true);
85625e64 1268 adev->in_hibernate = false;
897483d8
AD		 1269 if (r)
1270 return r;
1271 return amdgpu_asic_reset(adev);
d38ceaf9
AD		 1272}
1273
1274static int amdgpu_pmops_thaw(struct device *dev)
1275{
911d8b30 1276 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 1277
de185019 1278 return amdgpu_device_resume(drm_dev, true);
74b0b157 1279}
1280
1281static int amdgpu_pmops_poweroff(struct device *dev)
1282{
911d8b30 1283 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 1284
de185019 1285 return amdgpu_device_suspend(drm_dev, true);
74b0b157 1286}
1287
1288static int amdgpu_pmops_restore(struct device *dev)
1289{
911d8b30 1290 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 1291
de185019 1292 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 1293}
1294
1295static int amdgpu_pmops_runtime_suspend(struct device *dev)
1296{
1297 struct pci_dev *pdev = to_pci_dev(dev);
1298 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 1299 struct amdgpu_device *adev = drm_to_adev(drm_dev);
719423f6 1300 int ret, i;
d38ceaf9 1301
6ae6c7d4 1302 if (!adev->runpm) {
d38ceaf9
AD		 1303 pm_runtime_forbid(dev);
1304 return -EBUSY;
1305 }
1306
719423f6
AD		 1307 /* wait for all rings to drain before suspending */
1308 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1309 struct amdgpu_ring *ring = adev->rings[i];
1310 if (ring && ring->sched.ready) {
1311 ret = amdgpu_fence_wait_empty(ring);
1312 if (ret)
1313 return -EBUSY;
1314 }
1315 }
1316
f0f7ddfc 1317 adev->in_runpm = true;
b97e9d47
AD		 1318 if (amdgpu_device_supports_boco(drm_dev))
1319 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
d38ceaf9 1320 drm_kms_helper_poll_disable(drm_dev);
d38ceaf9 1321
de185019 1322 ret = amdgpu_device_suspend(drm_dev, false);
70bedd68
RB		 1323 if (ret)
1324 return ret;
1325
b97e9d47 1326 if (amdgpu_device_supports_boco(drm_dev)) {
562b49fc
AD		 1327 /* Only need to handle PCI state in the driver for ATPX
1328 * PCI core handles it for _PR3.
1329 */
1330 if (amdgpu_is_atpx_hybrid()) {
1331 pci_ignore_hotplug(pdev);
1332 } else {
c1dd4aa6 1333 amdgpu_device_cache_pci_state(pdev);
562b49fc
AD		 1334 pci_disable_device(pdev);
1335 pci_ignore_hotplug(pdev);
b97e9d47 1336 pci_set_power_state(pdev, PCI_D3cold);
562b49fc 1337 }
b97e9d47 1338 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
19134317
AD		 1339 } else if (amdgpu_device_supports_baco(drm_dev)) {
1340 amdgpu_device_baco_enter(drm_dev);
b97e9d47 1341 }
d38ceaf9
AD		 1342
1343 return 0;
1344}
1345
1346static int amdgpu_pmops_runtime_resume(struct device *dev)
1347{
1348 struct pci_dev *pdev = to_pci_dev(dev);
1349 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 1350 struct amdgpu_device *adev = drm_to_adev(drm_dev);
d38ceaf9
AD		 1351 int ret;
1352
6ae6c7d4 1353 if (!adev->runpm)
d38ceaf9
AD		 1354 return -EINVAL;
1355
b97e9d47
AD		 1356 if (amdgpu_device_supports_boco(drm_dev)) {
1357 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1358
562b49fc
AD		 1359 /* Only need to handle PCI state in the driver for ATPX
1360 * PCI core handles it for _PR3.
1361 */
1362 if (amdgpu_is_atpx_hybrid()) {
1363 pci_set_master(pdev);
1364 } else {
b97e9d47 1365 pci_set_power_state(pdev, PCI_D0);
c1dd4aa6 1366 amdgpu_device_load_pci_state(pdev);
562b49fc
AD		 1367 ret = pci_enable_device(pdev);
1368 if (ret)
1369 return ret;
1370 pci_set_master(pdev);
1371 }
19134317
AD		 1372 } else if (amdgpu_device_supports_baco(drm_dev)) {
1373 amdgpu_device_baco_exit(drm_dev);
b97e9d47 1374 }
de185019 1375 ret = amdgpu_device_resume(drm_dev, false);
d38ceaf9 1376 drm_kms_helper_poll_enable(drm_dev);
b97e9d47
AD		 1377 if (amdgpu_device_supports_boco(drm_dev))
1378 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
f0f7ddfc 1379 adev->in_runpm = false;
d38ceaf9
AD		 1380 return 0;
1381}
1382
1383static int amdgpu_pmops_runtime_idle(struct device *dev)
1384{
911d8b30 1385 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 1386 struct amdgpu_device *adev = drm_to_adev(drm_dev);
97f6a21b
AG		 1387 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1388 int ret = 1;
d38ceaf9 1389
6ae6c7d4 1390 if (!adev->runpm) {
d38ceaf9
AD		 1391 pm_runtime_forbid(dev);
1392 return -EBUSY;
1393 }
1394
97f6a21b
AG		 1395 if (amdgpu_device_has_dc_support(adev)) {
1396 struct drm_crtc *crtc;
1397
1398 drm_modeset_lock_all(drm_dev);
1399
1400 drm_for_each_crtc(crtc, drm_dev) {
1401 if (crtc->state->active) {
1402 ret = -EBUSY;
1403 break;
1404 }
d38ceaf9 1405 }
97f6a21b
AG		 1406
1407 drm_modeset_unlock_all(drm_dev);
1408
1409 } else {
1410 struct drm_connector *list_connector;
1411 struct drm_connector_list_iter iter;
1412
1413 mutex_lock(&drm_dev->mode_config.mutex);
1414 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
1415
1416 drm_connector_list_iter_begin(drm_dev, &iter);
1417 drm_for_each_connector_iter(list_connector, &iter) {
1418 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
1419 ret = -EBUSY;
1420 break;
1421 }
1422 }
1423
1424 drm_connector_list_iter_end(&iter);
1425
1426 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
1427 mutex_unlock(&drm_dev->mode_config.mutex);
d38ceaf9
AD		 1428 }
1429
97f6a21b
AG		 1430 if (ret == -EBUSY)
1431 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1432
d38ceaf9
AD		 1433 pm_runtime_mark_last_busy(dev);
1434 pm_runtime_autosuspend(dev);
97f6a21b 1435 return ret;
d38ceaf9
AD		 1436}
1437
1438long amdgpu_drm_ioctl(struct file *filp,
1439 unsigned int cmd, unsigned long arg)
1440{
1441 struct drm_file *file_priv = filp->private_data;
1442 struct drm_device *dev;
1443 long ret;
1444 dev = file_priv->minor->dev;
1445 ret = pm_runtime_get_sync(dev->dev);
1446 if (ret < 0)
5509ac65 1447 goto out;
d38ceaf9
AD		 1448
1449 ret = drm_ioctl(filp, cmd, arg);
1450
1451 pm_runtime_mark_last_busy(dev->dev);
5509ac65 1452out:
d38ceaf9
AD		 1453 pm_runtime_put_autosuspend(dev->dev);
1454 return ret;
1455}
1456
1457static const struct dev_pm_ops amdgpu_pm_ops = {
1458 .suspend = amdgpu_pmops_suspend,
1459 .resume = amdgpu_pmops_resume,
1460 .freeze = amdgpu_pmops_freeze,
1461 .thaw = amdgpu_pmops_thaw,
74b0b157 1462 .poweroff = amdgpu_pmops_poweroff,
1463 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 1464 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1465 .runtime_resume = amdgpu_pmops_runtime_resume,
1466 .runtime_idle = amdgpu_pmops_runtime_idle,
1467};
1468
48ad368a
AG		 1469static int amdgpu_flush(struct file *f, fl_owner_t id)
1470{
1471 struct drm_file *file_priv = f->private_data;
1472 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
56753e73 1473 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
48ad368a 1474
56753e73
CK		 1475 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1476 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
48ad368a 1477
56753e73 1478 return timeout >= 0 ? 0 : timeout;
48ad368a
AG		 1479}
1480
d38ceaf9
AD		 1481static const struct file_operations amdgpu_driver_kms_fops = {
1482 .owner = THIS_MODULE,
1483 .open = drm_open,
48ad368a 1484 .flush = amdgpu_flush,
d38ceaf9
AD		 1485 .release = drm_release,
1486 .unlocked_ioctl = amdgpu_drm_ioctl,
1487 .mmap = amdgpu_mmap,
1488 .poll = drm_poll,
1489 .read = drm_read,
1490#ifdef CONFIG_COMPAT
1491 .compat_ioctl = amdgpu_kms_compat_ioctl,
1492#endif
1493};
1494
021830d2
BN		 1495int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1496{
1497 struct drm_file *file;
1498
1499 if (!filp)
1500 return -EINVAL;
1501
1502 if (filp->f_op != &amdgpu_driver_kms_fops) {
1503 return -EINVAL;
1504 }
1505
1506 file = filp->private_data;
1507 *fpriv = file->driver_priv;
1508 return 0;
1509}
1510
d38ceaf9
AD		 1511static struct drm_driver kms_driver = {
1512 .driver_features =
f3ed6739 1513 DRIVER_ATOMIC |
1ff49481 1514 DRIVER_GEM |
db4ff423
CZ		 1515 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
1516 DRIVER_SYNCOBJ_TIMELINE,
d38ceaf9 1517 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 1518 .postclose = amdgpu_driver_postclose_kms,
1519 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9
AD		 1520 .irq_handler = amdgpu_irq_handler,
1521 .ioctls = amdgpu_ioctls_kms,
e7294dee 1522 .gem_free_object_unlocked = amdgpu_gem_object_free,
d38ceaf9
AD		 1523 .gem_open_object = amdgpu_gem_object_open,
1524 .gem_close_object = amdgpu_gem_object_close,
1525 .dumb_create = amdgpu_mode_dumb_create,
1526 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9
AD		 1527 .fops = &amdgpu_driver_kms_fops,
1528
1529 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1530 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1531 .gem_prime_export = amdgpu_gem_prime_export,
09052fc3 1532 .gem_prime_import = amdgpu_gem_prime_import,
d38ceaf9
AD		 1533 .gem_prime_vmap = amdgpu_gem_prime_vmap,
1534 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
dfced2e4 1535 .gem_prime_mmap = amdgpu_gem_prime_mmap,
d38ceaf9
AD		 1536
1537 .name = DRIVER_NAME,
1538 .desc = DRIVER_DESC,
1539 .date = DRIVER_DATE,
1540 .major = KMS_DRIVER_MAJOR,
1541 .minor = KMS_DRIVER_MINOR,
1542 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1543};
1544
c9a6b82f
AG		 1545static struct pci_error_handlers amdgpu_pci_err_handler = {
1546 .error_detected = amdgpu_pci_error_detected,
1547 .mmio_enabled = amdgpu_pci_mmio_enabled,
1548 .slot_reset = amdgpu_pci_slot_reset,
1549 .resume = amdgpu_pci_resume,
1550};
1551
d38ceaf9
AD		 1552static struct pci_driver amdgpu_kms_pci_driver = {
1553 .name = DRIVER_NAME,
1554 .id_table = pciidlist,
1555 .probe = amdgpu_pci_probe,
1556 .remove = amdgpu_pci_remove,
61e11306 1557 .shutdown = amdgpu_pci_shutdown,
d38ceaf9 1558 .driver.pm = &amdgpu_pm_ops,
c9a6b82f 1559 .err_handler = &amdgpu_pci_err_handler,
d38ceaf9
AD		 1560};
1561
1562static int __init amdgpu_init(void)
1563{
245ae5e9
CK		 1564 int r;
1565
c60e22f7
TI		 1566 if (vgacon_text_force()) {
1567 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1568 return -EINVAL;
1569 }
1570
245ae5e9
CK		 1571 r = amdgpu_sync_init();
1572 if (r)
1573 goto error_sync;
1574
1575 r = amdgpu_fence_slab_init();
1576 if (r)
1577 goto error_fence;
1578
d38ceaf9 1579 DRM_INFO("amdgpu kernel modesetting enabled.\n");
448d1051 1580 kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
d38ceaf9 1581 amdgpu_register_atpx_handler();
03a1c08d
FK		 1582
1583 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1584 amdgpu_amdkfd_init();
1585
d38ceaf9 1586 /* let modprobe override vga console setting */
448d1051 1587 return pci_register_driver(&amdgpu_kms_pci_driver);
245ae5e9 1588
245ae5e9
CK		 1589error_fence:
1590 amdgpu_sync_fini();
1591
1592error_sync:
1593 return r;
d38ceaf9
AD		 1594}
1595
1596static void __exit amdgpu_exit(void)
1597{
130e0371 1598 amdgpu_amdkfd_fini();
448d1051 1599 pci_unregister_driver(&amdgpu_kms_pci_driver);
d38ceaf9 1600 amdgpu_unregister_atpx_handler();
257bf15a 1601 amdgpu_sync_fini();
d573de2d 1602 amdgpu_fence_slab_fini();
c7d8b782 1603 mmu_notifier_synchronize();
d38ceaf9
AD		 1604}
1605
1606module_init(amdgpu_init);
1607module_exit(amdgpu_exit);
1608
1609MODULE_AUTHOR(DRIVER_AUTHOR);
1610MODULE_DESCRIPTION(DRIVER_DESC);
1611MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)