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drm/amdgpu: Changed CU reservation golden settings
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
248a1d6f 42#include <drm/drm_crtc_helper.h>
d38ceaf9
AD		 43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
d347ce66 55 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 57 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 59 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 60 * - 3.8.0 - Add support raster config init in the kernel
ef704318 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 64 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 65 * - 3.13.0 - Add PRT support
203eb0cb 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 67 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 68 * - 3.16.0 - Add reserved vmid support
68e2c5ff 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 70 * - 3.18.0 - Export gpu always on cu bitmap
d38ceaf9
AD		 71 */
72#define KMS_DRIVER_MAJOR 3
dbfe85ea 73#define KMS_DRIVER_MINOR 18
d38ceaf9
AD		 74#define KMS_DRIVER_PATCHLEVEL 0
75
76int amdgpu_vram_limit = 0;
77int amdgpu_gart_size = -1; /* auto */
95844d20 78int amdgpu_moverate = -1; /* auto */
d38ceaf9
AD		 79int amdgpu_benchmarking = 0;
80int amdgpu_testing = 0;
81int amdgpu_audio = -1;
82int amdgpu_disp_priority = 0;
83int amdgpu_hw_i2c = 0;
84int amdgpu_pcie_gen2 = -1;
85int amdgpu_msi = -1;
a895c222 86int amdgpu_lockup_timeout = 0;
d38ceaf9 87int amdgpu_dpm = -1;
e635ee07 88int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 89int amdgpu_aspm = -1;
90int amdgpu_runtime_pm = -1;
d38ceaf9
AD		 91unsigned amdgpu_ip_block_mask = 0xffffffff;
92int amdgpu_bapm = -1;
93int amdgpu_deep_color = 0;
bab4fee7 94int amdgpu_vm_size = -1;
d38ceaf9 95int amdgpu_vm_block_size = -1;
d9c13156 96int amdgpu_vm_fault_stop = 0;
b495bd3a 97int amdgpu_vm_debug = 0;
60bfcd31 98int amdgpu_vram_page_split = 512;
9a4b7d4c 99int amdgpu_vm_update_mode = -1;
d38ceaf9 100int amdgpu_exp_hw_support = 0;
b70f014d 101int amdgpu_sched_jobs = 32;
4afcb303 102int amdgpu_sched_hw_submission = 2;
3ca67300
RZ		 103int amdgpu_no_evict = 0;
104int amdgpu_direct_gma_size = 0;
cd474ba0
AD		 105unsigned amdgpu_pcie_gen_cap = 0;
106unsigned amdgpu_pcie_lane_cap = 0;
395d1fb9
NH		 107unsigned amdgpu_cg_mask = 0xffffffff;
108unsigned amdgpu_pg_mask = 0xffffffff;
6f8941a2 109char *amdgpu_disable_cu = NULL;
9accf2fd 110char *amdgpu_virtual_display = NULL;
5141e9d2 111unsigned amdgpu_pp_feature_mask = 0xffffffff;
bce23e00
AD		 112int amdgpu_ngg = 0;
113int amdgpu_prim_buf_per_se = 0;
114int amdgpu_pos_buf_per_se = 0;
115int amdgpu_cntl_sb_buf_per_se = 0;
116int amdgpu_param_buf_per_se = 0;
65781c78 117int amdgpu_job_hang_limit = 0;
e8835e0e 118int amdgpu_lbpw = -1;
d38ceaf9
AD		 119
120MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
121module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
122
123MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
124module_param_named(gartsize, amdgpu_gart_size, int, 0600);
125
95844d20
MO		 126MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
127module_param_named(moverate, amdgpu_moverate, int, 0600);
128
d38ceaf9
AD		 129MODULE_PARM_DESC(benchmark, "Run benchmark");
130module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
131
132MODULE_PARM_DESC(test, "Run tests");
133module_param_named(test, amdgpu_testing, int, 0444);
134
135MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
136module_param_named(audio, amdgpu_audio, int, 0444);
137
138MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
139module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
140
141MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
142module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
143
144MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
145module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
146
147MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
148module_param_named(msi, amdgpu_msi, int, 0444);
149
a895c222 150MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 151module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
152
153MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
154module_param_named(dpm, amdgpu_dpm, int, 0444);
155
e635ee07
HR		 156MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
157module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9
AD		 158
159MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
160module_param_named(aspm, amdgpu_aspm, int, 0444);
161
162MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
163module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
164
d38ceaf9
AD		 165MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
166module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
167
168MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
169module_param_named(bapm, amdgpu_bapm, int, 0444);
170
171MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
172module_param_named(deep_color, amdgpu_deep_color, int, 0444);
173
ed885b21 174MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9
AD		 175module_param_named(vm_size, amdgpu_vm_size, int, 0444);
176
177MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
178module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
179
d9c13156
CK		 180MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
181module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
182
b495bd3a
CK		 183MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
184module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
185
9a4b7d4c
HK		 186MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
187module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
188
6a7f76e7
CK		 189MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)");
190module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
191
d38ceaf9
AD		 192MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
193module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
194
b70f014d 195MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 196module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
197
4afcb303
JZ		 198MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
199module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
200
5141e9d2
RZ		 201MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
202module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
3a74f6f2 203
3ca67300
RZ		 204MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
205module_param_named(no_evict, amdgpu_no_evict, int, 0444);
206
207MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
208module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
af223dfa 209
cd474ba0
AD		 210MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
211module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
212
213MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
214module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
215
395d1fb9
NH		 216MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
217module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
218
219MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
220module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
221
6f8941a2
NH		 222MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
223module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
224
0f66356d
ED		 225MODULE_PARM_DESC(virtual_display,
226 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 227module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 228
bce23e00
AD		 229MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
230module_param_named(ngg, amdgpu_ngg, int, 0444);
231
232MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
233module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
234
235MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
236module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
237
238MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
239module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
240
241MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
242module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
243
65781c78
ML		 244MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
245module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
246
e8835e0e
HZ		 247MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
248module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 249
6dd13096 250#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56
MD		 251
252#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
6dd13096
FK		 253int amdgpu_si_support = 0;
254MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 255#else
256int amdgpu_si_support = 1;
257MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
258#endif
259
6dd13096
FK		 260module_param_named(si_support, amdgpu_si_support, int, 0444);
261#endif
262
7df28986 263#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56
MD		 264
265#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
2b059658
MD		 266int amdgpu_cik_support = 0;
267MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 268#else
269int amdgpu_cik_support = 1;
270MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
271#endif
272
7df28986
FK		 273module_param_named(cik_support, amdgpu_cik_support, int, 0444);
274#endif
275
bce23e00 276
f498d9ed 277static const struct pci_device_id pciidlist[] = {
78fbb685
KW		 278#ifdef CONFIG_DRM_AMDGPU_SI
279 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
280 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
281 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
282 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
283 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
284 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
285 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
286 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
287 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
288 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
289 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
290 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
291 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
292 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
293 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
294 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
295 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
296 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
297 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
298 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
299 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
300 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
301 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
302 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
303 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
304 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
305 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
306 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
307 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
308 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
309 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
310 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
311 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
312 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
313 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
314 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
315 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
316 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
317 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
318 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
319 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
320 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
321 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
322 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
323 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
324 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
325 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
326 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
327 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
328 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
329 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
330 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
331 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
332 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
333 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
334 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
335 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
336 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
337 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
338 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
339 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
340 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
341 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
342 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
343 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
344 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
345 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
346 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
347 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
348 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
349 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
350 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
351#endif
89330c39
AD		 352#ifdef CONFIG_DRM_AMDGPU_CIK
353 /* Kaveri */
2f7d10b3
JZ		 354 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
355 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
356 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
357 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
358 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
359 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
360 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
361 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
362 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
363 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
364 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
365 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
366 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
367 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
368 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
369 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
370 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
371 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
372 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
373 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
374 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
375 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 376 /* Bonaire */
2f7d10b3
JZ		 377 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
378 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
379 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
380 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 381 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
382 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
383 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
384 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
385 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
386 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 387 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 388 /* Hawaii */
389 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
390 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
391 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
392 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
393 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
394 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
395 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
396 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
397 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
398 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
399 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
400 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
401 /* Kabini */
2f7d10b3
JZ		 402 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
403 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
404 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
405 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
406 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
407 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
408 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
409 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
410 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
411 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
412 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
413 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
414 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
415 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
416 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
417 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 418 /* mullins */
2f7d10b3
JZ		 419 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
420 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
421 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
422 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
423 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
424 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
425 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
426 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
427 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
428 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
429 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
430 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
431 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
432 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
433 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
434 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 435#endif
1256a8b8 436 /* topaz */
dba280b2
AD		 437 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
438 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
439 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
440 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
441 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 442 /* tonga */
443 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
444 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
445 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 446 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 447 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
448 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 449 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 450 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
451 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 452 /* fiji */
453 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 454 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 455 /* carrizo */
2f7d10b3
JZ		 456 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
457 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
458 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
459 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
460 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 461 /* stoney */
462 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 463 /* Polaris11 */
464 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 465 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 466 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 467 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 468 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 469 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 470 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
471 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
472 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 473 /* Polaris10 */
474 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 475 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
476 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
477 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
478 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 479 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 480 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 481 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
482 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
483 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
484 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
485 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 486 /* Polaris12 */
487 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
488 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
489 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
490 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
491 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 492 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 493 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 494 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
ca2f1cca
JZ		 495 /* Vega 10 */
496 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
497 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
498 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
499 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
09062ae1 500 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
ca2f1cca 501 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
09062ae1 502 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
ca2f1cca
JZ		 503 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
504 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
df515052
CZ		 505 /* Raven */
506 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
507
d38ceaf9
AD		 508 {0, 0, 0}
509};
510
511MODULE_DEVICE_TABLE(pci, pciidlist);
512
513static struct drm_driver kms_driver;
514
515static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
516{
517 struct apertures_struct *ap;
518 bool primary = false;
519
520 ap = alloc_apertures(1);
521 if (!ap)
522 return -ENOMEM;
523
524 ap->ranges[0].base = pci_resource_start(pdev, 0);
525 ap->ranges[0].size = pci_resource_len(pdev, 0);
526
527#ifdef CONFIG_X86
528 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
529#endif
44adece5 530 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
d38ceaf9
AD		 531 kfree(ap);
532
533 return 0;
534}
535
536static int amdgpu_pci_probe(struct pci_dev *pdev,
537 const struct pci_device_id *ent)
538{
b58c1131 539 struct drm_device *dev;
d38ceaf9
AD		 540 unsigned long flags = ent->driver_data;
541 int ret;
542
2f7d10b3 543 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 544 DRM_INFO("This hardware requires experimental hardware support.\n"
545 "See modparam exp_hw_support\n");
546 return -ENODEV;
547 }
548
efb1c658
OG		 549 /*
550 * Initialize amdkfd before starting radeon. If it was not loaded yet,
551 * defer radeon probing
552 */
553 ret = amdgpu_amdkfd_init();
554 if (ret == -EPROBE_DEFER)
555 return ret;
556
d38ceaf9
AD		 557 /* Get rid of things like offb */
558 ret = amdgpu_kick_out_firmware_fb(pdev);
559 if (ret)
560 return ret;
561
b58c1131
AD		 562 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
563 if (IS_ERR(dev))
564 return PTR_ERR(dev);
565
566 ret = pci_enable_device(pdev);
567 if (ret)
568 goto err_free;
569
570 dev->pdev = pdev;
571
572 pci_set_drvdata(pdev, dev);
573
574 ret = drm_dev_register(dev, ent->driver_data);
575 if (ret)
576 goto err_pci;
577
578 return 0;
579
580err_pci:
581 pci_disable_device(pdev);
582err_free:
583 drm_dev_unref(dev);
584 return ret;
d38ceaf9
AD		 585}
586
587static void
588amdgpu_pci_remove(struct pci_dev *pdev)
589{
590 struct drm_device *dev = pci_get_drvdata(pdev);
591
b58c1131
AD		 592 drm_dev_unregister(dev);
593 drm_dev_unref(dev);
d38ceaf9
AD		 594}
595
61e11306
AD		 596static void
597amdgpu_pci_shutdown(struct pci_dev *pdev)
598{
faefba95
AD		 599 struct drm_device *dev = pci_get_drvdata(pdev);
600 struct amdgpu_device *adev = dev->dev_private;
601
61e11306 602 /* if we are running in a VM, make sure the device
00ea8cba
AD		 603 * torn down properly on reboot/shutdown.
604 * unfortunately we can't detect certain
605 * hypervisors so just do this all the time.
61e11306 606 */
faefba95 607 amdgpu_suspend(adev);
61e11306
AD		 608}
609
d38ceaf9
AD		 610static int amdgpu_pmops_suspend(struct device *dev)
611{
612 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 613
d38ceaf9 614 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 615 return amdgpu_device_suspend(drm_dev, true, true);
d38ceaf9
AD		 616}
617
618static int amdgpu_pmops_resume(struct device *dev)
619{
620 struct pci_dev *pdev = to_pci_dev(dev);
621 struct drm_device *drm_dev = pci_get_drvdata(pdev);
85e154c2
AD		 622
623 /* GPU comes up enabled by the bios on resume */
624 if (amdgpu_device_is_px(drm_dev)) {
625 pm_runtime_disable(dev);
626 pm_runtime_set_active(dev);
627 pm_runtime_enable(dev);
628 }
629
810ddc3a 630 return amdgpu_device_resume(drm_dev, true, true);
d38ceaf9
AD		 631}
632
633static int amdgpu_pmops_freeze(struct device *dev)
634{
635 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 636
d38ceaf9 637 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 638 return amdgpu_device_suspend(drm_dev, false, true);
d38ceaf9
AD		 639}
640
641static int amdgpu_pmops_thaw(struct device *dev)
642{
643 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 644
645 struct drm_device *drm_dev = pci_get_drvdata(pdev);
646 return amdgpu_device_resume(drm_dev, false, true);
647}
648
649static int amdgpu_pmops_poweroff(struct device *dev)
650{
651 struct pci_dev *pdev = to_pci_dev(dev);
652
653 struct drm_device *drm_dev = pci_get_drvdata(pdev);
654 return amdgpu_device_suspend(drm_dev, true, true);
655}
656
657static int amdgpu_pmops_restore(struct device *dev)
658{
659 struct pci_dev *pdev = to_pci_dev(dev);
660
d38ceaf9 661 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 662 return amdgpu_device_resume(drm_dev, false, true);
d38ceaf9
AD		 663}
664
665static int amdgpu_pmops_runtime_suspend(struct device *dev)
666{
667 struct pci_dev *pdev = to_pci_dev(dev);
668 struct drm_device *drm_dev = pci_get_drvdata(pdev);
669 int ret;
670
671 if (!amdgpu_device_is_px(drm_dev)) {
672 pm_runtime_forbid(dev);
673 return -EBUSY;
674 }
675
676 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
677 drm_kms_helper_poll_disable(drm_dev);
678 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
679
810ddc3a 680 ret = amdgpu_device_suspend(drm_dev, false, false);
d38ceaf9
AD		 681 pci_save_state(pdev);
682 pci_disable_device(pdev);
683 pci_ignore_hotplug(pdev);
11670975
AD		 684 if (amdgpu_is_atpx_hybrid())
685 pci_set_power_state(pdev, PCI_D3cold);
522761cb 686 else if (!amdgpu_has_atpx_dgpu_power_cntl())
7e32aa61 687 pci_set_power_state(pdev, PCI_D3hot);
d38ceaf9
AD		 688 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
689
690 return 0;
691}
692
693static int amdgpu_pmops_runtime_resume(struct device *dev)
694{
695 struct pci_dev *pdev = to_pci_dev(dev);
696 struct drm_device *drm_dev = pci_get_drvdata(pdev);
697 int ret;
698
699 if (!amdgpu_device_is_px(drm_dev))
700 return -EINVAL;
701
702 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
703
522761cb
AD		 704 if (amdgpu_is_atpx_hybrid() ||
705 !amdgpu_has_atpx_dgpu_power_cntl())
706 pci_set_power_state(pdev, PCI_D0);
d38ceaf9
AD		 707 pci_restore_state(pdev);
708 ret = pci_enable_device(pdev);
709 if (ret)
710 return ret;
711 pci_set_master(pdev);
712
810ddc3a 713 ret = amdgpu_device_resume(drm_dev, false, false);
d38ceaf9
AD		 714 drm_kms_helper_poll_enable(drm_dev);
715 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
716 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
717 return 0;
718}
719
720static int amdgpu_pmops_runtime_idle(struct device *dev)
721{
722 struct pci_dev *pdev = to_pci_dev(dev);
723 struct drm_device *drm_dev = pci_get_drvdata(pdev);
724 struct drm_crtc *crtc;
725
726 if (!amdgpu_device_is_px(drm_dev)) {
727 pm_runtime_forbid(dev);
728 return -EBUSY;
729 }
730
731 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
732 if (crtc->enabled) {
733 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
734 return -EBUSY;
735 }
736 }
737
738 pm_runtime_mark_last_busy(dev);
739 pm_runtime_autosuspend(dev);
740 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
741 return 1;
742}
743
744long amdgpu_drm_ioctl(struct file *filp,
745 unsigned int cmd, unsigned long arg)
746{
747 struct drm_file *file_priv = filp->private_data;
748 struct drm_device *dev;
749 long ret;
750 dev = file_priv->minor->dev;
751 ret = pm_runtime_get_sync(dev->dev);
752 if (ret < 0)
753 return ret;
754
755 ret = drm_ioctl(filp, cmd, arg);
756
757 pm_runtime_mark_last_busy(dev->dev);
758 pm_runtime_put_autosuspend(dev->dev);
759 return ret;
760}
761
762static const struct dev_pm_ops amdgpu_pm_ops = {
763 .suspend = amdgpu_pmops_suspend,
764 .resume = amdgpu_pmops_resume,
765 .freeze = amdgpu_pmops_freeze,
766 .thaw = amdgpu_pmops_thaw,
74b0b157 767 .poweroff = amdgpu_pmops_poweroff,
768 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 769 .runtime_suspend = amdgpu_pmops_runtime_suspend,
770 .runtime_resume = amdgpu_pmops_runtime_resume,
771 .runtime_idle = amdgpu_pmops_runtime_idle,
772};
773
774static const struct file_operations amdgpu_driver_kms_fops = {
775 .owner = THIS_MODULE,
776 .open = drm_open,
777 .release = drm_release,
778 .unlocked_ioctl = amdgpu_drm_ioctl,
779 .mmap = amdgpu_mmap,
780 .poll = drm_poll,
781 .read = drm_read,
782#ifdef CONFIG_COMPAT
783 .compat_ioctl = amdgpu_kms_compat_ioctl,
784#endif
785};
786
1bf6ad62
DV		 787static bool
788amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
789 bool in_vblank_irq, int *vpos, int *hpos,
790 ktime_t *stime, ktime_t *etime,
791 const struct drm_display_mode *mode)
792{
793 return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
794 stime, etime, mode);
795}
796
d38ceaf9
AD		 797static struct drm_driver kms_driver = {
798 .driver_features =
799 DRIVER_USE_AGP |
800 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
660e8558 801 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
d38ceaf9
AD		 802 .load = amdgpu_driver_load_kms,
803 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 804 .postclose = amdgpu_driver_postclose_kms,
805 .lastclose = amdgpu_driver_lastclose_kms,
806 .set_busid = drm_pci_set_busid,
807 .unload = amdgpu_driver_unload_kms,
808 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
809 .enable_vblank = amdgpu_enable_vblank_kms,
810 .disable_vblank = amdgpu_disable_vblank_kms,
1bf6ad62
DV		 811 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
812 .get_scanout_position = amdgpu_get_crtc_scanout_position,
d38ceaf9
AD		 813#if defined(CONFIG_DEBUG_FS)
814 .debugfs_init = amdgpu_debugfs_init,
d38ceaf9
AD		 815#endif
816 .irq_preinstall = amdgpu_irq_preinstall,
817 .irq_postinstall = amdgpu_irq_postinstall,
818 .irq_uninstall = amdgpu_irq_uninstall,
819 .irq_handler = amdgpu_irq_handler,
820 .ioctls = amdgpu_ioctls_kms,
e7294dee 821 .gem_free_object_unlocked = amdgpu_gem_object_free,
d38ceaf9
AD		 822 .gem_open_object = amdgpu_gem_object_open,
823 .gem_close_object = amdgpu_gem_object_close,
824 .dumb_create = amdgpu_mode_dumb_create,
825 .dumb_map_offset = amdgpu_mode_dumb_mmap,
826 .dumb_destroy = drm_gem_dumb_destroy,
827 .fops = &amdgpu_driver_kms_fops,
828
829 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
830 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
831 .gem_prime_export = amdgpu_gem_prime_export,
832 .gem_prime_import = drm_gem_prime_import,
833 .gem_prime_pin = amdgpu_gem_prime_pin,
834 .gem_prime_unpin = amdgpu_gem_prime_unpin,
835 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
836 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
837 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
838 .gem_prime_vmap = amdgpu_gem_prime_vmap,
839 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
840
841 .name = DRIVER_NAME,
842 .desc = DRIVER_DESC,
843 .date = DRIVER_DATE,
844 .major = KMS_DRIVER_MAJOR,
845 .minor = KMS_DRIVER_MINOR,
846 .patchlevel = KMS_DRIVER_PATCHLEVEL,
847};
848
849static struct drm_driver *driver;
850static struct pci_driver *pdriver;
851
852static struct pci_driver amdgpu_kms_pci_driver = {
853 .name = DRIVER_NAME,
854 .id_table = pciidlist,
855 .probe = amdgpu_pci_probe,
856 .remove = amdgpu_pci_remove,
61e11306 857 .shutdown = amdgpu_pci_shutdown,
d38ceaf9
AD		 858 .driver.pm = &amdgpu_pm_ops,
859};
860
d573de2d
RZ		 861
862
d38ceaf9
AD		 863static int __init amdgpu_init(void)
864{
245ae5e9
CK		 865 int r;
866
867 r = amdgpu_sync_init();
868 if (r)
869 goto error_sync;
870
871 r = amdgpu_fence_slab_init();
872 if (r)
873 goto error_fence;
874
875 r = amd_sched_fence_slab_init();
876 if (r)
877 goto error_sched;
878
d38ceaf9
AD		 879 if (vgacon_text_force()) {
880 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
881 return -EINVAL;
882 }
d38ceaf9
AD		 883 DRM_INFO("amdgpu kernel modesetting enabled.\n");
884 driver = &kms_driver;
885 pdriver = &amdgpu_kms_pci_driver;
d38ceaf9
AD		 886 driver->num_ioctls = amdgpu_max_kms_ioctl;
887 amdgpu_register_atpx_handler();
d38ceaf9 888 /* let modprobe override vga console setting */
3c50c287 889 return pci_register_driver(pdriver);
245ae5e9
CK		 890
891error_sched:
892 amdgpu_fence_slab_fini();
893
894error_fence:
895 amdgpu_sync_fini();
896
897error_sync:
898 return r;
d38ceaf9
AD		 899}
900
901static void __exit amdgpu_exit(void)
902{
130e0371 903 amdgpu_amdkfd_fini();
3c50c287 904 pci_unregister_driver(pdriver);
d38ceaf9 905 amdgpu_unregister_atpx_handler();
257bf15a 906 amdgpu_sync_fini();
c24784f0 907 amd_sched_fence_slab_fini();
d573de2d 908 amdgpu_fence_slab_fini();
d38ceaf9
AD		 909}
910
911module_init(amdgpu_init);
912module_exit(amdgpu_exit);
913
914MODULE_AUTHOR(DRIVER_AUTHOR);
915MODULE_DESCRIPTION(DRIVER_DESC);
916MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)