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drm/amd/powerplay: move asic unrelated function to hwmgr.c.
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
d38ceaf9
AD		 55 */
56#define KMS_DRIVER_MAJOR 3
f84e63f2 57#define KMS_DRIVER_MINOR 2
d38ceaf9
AD		 58#define KMS_DRIVER_PATCHLEVEL 0
59
60int amdgpu_vram_limit = 0;
61int amdgpu_gart_size = -1; /* auto */
62int amdgpu_benchmarking = 0;
63int amdgpu_testing = 0;
64int amdgpu_audio = -1;
65int amdgpu_disp_priority = 0;
66int amdgpu_hw_i2c = 0;
67int amdgpu_pcie_gen2 = -1;
68int amdgpu_msi = -1;
a895c222 69int amdgpu_lockup_timeout = 0;
d38ceaf9
AD		 70int amdgpu_dpm = -1;
71int amdgpu_smc_load_fw = 1;
72int amdgpu_aspm = -1;
73int amdgpu_runtime_pm = -1;
d38ceaf9
AD		 74unsigned amdgpu_ip_block_mask = 0xffffffff;
75int amdgpu_bapm = -1;
76int amdgpu_deep_color = 0;
ed885b21 77int amdgpu_vm_size = 64;
d38ceaf9 78int amdgpu_vm_block_size = -1;
d9c13156 79int amdgpu_vm_fault_stop = 0;
b495bd3a 80int amdgpu_vm_debug = 0;
d38ceaf9 81int amdgpu_exp_hw_support = 0;
b70f014d 82int amdgpu_sched_jobs = 32;
4afcb303 83int amdgpu_sched_hw_submission = 2;
e61710c5 84int amdgpu_powerplay = -1;
cd474ba0
AD		 85unsigned amdgpu_pcie_gen_cap = 0;
86unsigned amdgpu_pcie_lane_cap = 0;
d38ceaf9
AD		 87
88MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
89module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
90
91MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
92module_param_named(gartsize, amdgpu_gart_size, int, 0600);
93
94MODULE_PARM_DESC(benchmark, "Run benchmark");
95module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
96
97MODULE_PARM_DESC(test, "Run tests");
98module_param_named(test, amdgpu_testing, int, 0444);
99
100MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
101module_param_named(audio, amdgpu_audio, int, 0444);
102
103MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
104module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
105
106MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
107module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
108
109MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
110module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
111
112MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
113module_param_named(msi, amdgpu_msi, int, 0444);
114
a895c222 115MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 116module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
117
118MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
119module_param_named(dpm, amdgpu_dpm, int, 0444);
120
121MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
122module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
123
124MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
125module_param_named(aspm, amdgpu_aspm, int, 0444);
126
127MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
128module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
129
d38ceaf9
AD		 130MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
131module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
132
133MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
134module_param_named(bapm, amdgpu_bapm, int, 0444);
135
136MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
137module_param_named(deep_color, amdgpu_deep_color, int, 0444);
138
ed885b21 139MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9
AD		 140module_param_named(vm_size, amdgpu_vm_size, int, 0444);
141
142MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
143module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
144
d9c13156
CK		 145MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
146module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
147
b495bd3a
CK		 148MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
149module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
150
d38ceaf9
AD		 151MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
152module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
153
b70f014d 154MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 155module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
156
4afcb303
JZ		 157MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
158module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
159
3a74f6f2 160#ifdef CONFIG_DRM_AMD_POWERPLAY
e61710c5 161MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
3a74f6f2
JZ		 162module_param_named(powerplay, amdgpu_powerplay, int, 0444);
163#endif
164
cd474ba0
AD		 165MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
166module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
167
168MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
169module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
170
f498d9ed 171static const struct pci_device_id pciidlist[] = {
89330c39
AD		 172#ifdef CONFIG_DRM_AMDGPU_CIK
173 /* Kaveri */
2f7d10b3
JZ		 174 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
175 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
176 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
177 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
178 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
179 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
180 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
181 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
182 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
183 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
184 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
185 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
186 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
187 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
188 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
189 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
190 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
191 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
192 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
193 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
194 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
195 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 196 /* Bonaire */
2f7d10b3
JZ		 197 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
198 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
199 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
200 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 201 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
202 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
203 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
204 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
205 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
206 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 207 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 208 /* Hawaii */
209 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
210 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
211 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
212 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
213 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
214 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
215 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
216 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
217 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
218 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
219 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
220 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
221 /* Kabini */
2f7d10b3
JZ		 222 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
223 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
224 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
225 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
226 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
227 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
228 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
229 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
230 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
231 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
232 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
233 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
234 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
235 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
236 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
237 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 238 /* mullins */
2f7d10b3
JZ		 239 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
240 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
241 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
242 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
243 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
244 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
245 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
246 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
247 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
248 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
249 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
250 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
251 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
252 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
253 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
254 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 255#endif
1256a8b8 256 /* topaz */
dba280b2
AD		 257 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
258 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
259 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
260 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
261 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 262 /* tonga */
263 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
264 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
265 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 266 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 267 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
268 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 269 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 270 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
271 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 272 /* fiji */
273 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 274 /* carrizo */
2f7d10b3
JZ		 275 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
276 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
277 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
278 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
279 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 280 /* stoney */
281 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 282 /* Polaris11 */
283 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
284 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
285 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
286 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
287 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
288 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
289 /* Polaris10 */
290 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
291 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
d38ceaf9
AD		 292
293 {0, 0, 0}
294};
295
296MODULE_DEVICE_TABLE(pci, pciidlist);
297
298static struct drm_driver kms_driver;
299
300static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
301{
302 struct apertures_struct *ap;
303 bool primary = false;
304
305 ap = alloc_apertures(1);
306 if (!ap)
307 return -ENOMEM;
308
309 ap->ranges[0].base = pci_resource_start(pdev, 0);
310 ap->ranges[0].size = pci_resource_len(pdev, 0);
311
312#ifdef CONFIG_X86
313 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
314#endif
315 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
316 kfree(ap);
317
318 return 0;
319}
320
321static int amdgpu_pci_probe(struct pci_dev *pdev,
322 const struct pci_device_id *ent)
323{
324 unsigned long flags = ent->driver_data;
325 int ret;
326
2f7d10b3 327 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 328 DRM_INFO("This hardware requires experimental hardware support.\n"
329 "See modparam exp_hw_support\n");
330 return -ENODEV;
331 }
332
efb1c658
OG		 333 /*
334 * Initialize amdkfd before starting radeon. If it was not loaded yet,
335 * defer radeon probing
336 */
337 ret = amdgpu_amdkfd_init();
338 if (ret == -EPROBE_DEFER)
339 return ret;
340
d38ceaf9
AD		 341 /* Get rid of things like offb */
342 ret = amdgpu_kick_out_firmware_fb(pdev);
343 if (ret)
344 return ret;
345
346 return drm_get_pci_dev(pdev, ent, &kms_driver);
347}
348
349static void
350amdgpu_pci_remove(struct pci_dev *pdev)
351{
352 struct drm_device *dev = pci_get_drvdata(pdev);
353
354 drm_put_dev(dev);
355}
356
357static int amdgpu_pmops_suspend(struct device *dev)
358{
359 struct pci_dev *pdev = to_pci_dev(dev);
360 struct drm_device *drm_dev = pci_get_drvdata(pdev);
361 return amdgpu_suspend_kms(drm_dev, true, true);
362}
363
364static int amdgpu_pmops_resume(struct device *dev)
365{
366 struct pci_dev *pdev = to_pci_dev(dev);
367 struct drm_device *drm_dev = pci_get_drvdata(pdev);
368 return amdgpu_resume_kms(drm_dev, true, true);
369}
370
371static int amdgpu_pmops_freeze(struct device *dev)
372{
373 struct pci_dev *pdev = to_pci_dev(dev);
374 struct drm_device *drm_dev = pci_get_drvdata(pdev);
375 return amdgpu_suspend_kms(drm_dev, false, true);
376}
377
378static int amdgpu_pmops_thaw(struct device *dev)
379{
380 struct pci_dev *pdev = to_pci_dev(dev);
381 struct drm_device *drm_dev = pci_get_drvdata(pdev);
382 return amdgpu_resume_kms(drm_dev, false, true);
383}
384
385static int amdgpu_pmops_runtime_suspend(struct device *dev)
386{
387 struct pci_dev *pdev = to_pci_dev(dev);
388 struct drm_device *drm_dev = pci_get_drvdata(pdev);
389 int ret;
390
391 if (!amdgpu_device_is_px(drm_dev)) {
392 pm_runtime_forbid(dev);
393 return -EBUSY;
394 }
395
396 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
397 drm_kms_helper_poll_disable(drm_dev);
398 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
399
400 ret = amdgpu_suspend_kms(drm_dev, false, false);
401 pci_save_state(pdev);
402 pci_disable_device(pdev);
403 pci_ignore_hotplug(pdev);
404 pci_set_power_state(pdev, PCI_D3cold);
405 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
406
407 return 0;
408}
409
410static int amdgpu_pmops_runtime_resume(struct device *dev)
411{
412 struct pci_dev *pdev = to_pci_dev(dev);
413 struct drm_device *drm_dev = pci_get_drvdata(pdev);
414 int ret;
415
416 if (!amdgpu_device_is_px(drm_dev))
417 return -EINVAL;
418
419 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
420
421 pci_set_power_state(pdev, PCI_D0);
422 pci_restore_state(pdev);
423 ret = pci_enable_device(pdev);
424 if (ret)
425 return ret;
426 pci_set_master(pdev);
427
428 ret = amdgpu_resume_kms(drm_dev, false, false);
429 drm_kms_helper_poll_enable(drm_dev);
430 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
431 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
432 return 0;
433}
434
435static int amdgpu_pmops_runtime_idle(struct device *dev)
436{
437 struct pci_dev *pdev = to_pci_dev(dev);
438 struct drm_device *drm_dev = pci_get_drvdata(pdev);
439 struct drm_crtc *crtc;
440
441 if (!amdgpu_device_is_px(drm_dev)) {
442 pm_runtime_forbid(dev);
443 return -EBUSY;
444 }
445
446 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
447 if (crtc->enabled) {
448 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
449 return -EBUSY;
450 }
451 }
452
453 pm_runtime_mark_last_busy(dev);
454 pm_runtime_autosuspend(dev);
455 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
456 return 1;
457}
458
459long amdgpu_drm_ioctl(struct file *filp,
460 unsigned int cmd, unsigned long arg)
461{
462 struct drm_file *file_priv = filp->private_data;
463 struct drm_device *dev;
464 long ret;
465 dev = file_priv->minor->dev;
466 ret = pm_runtime_get_sync(dev->dev);
467 if (ret < 0)
468 return ret;
469
470 ret = drm_ioctl(filp, cmd, arg);
471
472 pm_runtime_mark_last_busy(dev->dev);
473 pm_runtime_put_autosuspend(dev->dev);
474 return ret;
475}
476
477static const struct dev_pm_ops amdgpu_pm_ops = {
478 .suspend = amdgpu_pmops_suspend,
479 .resume = amdgpu_pmops_resume,
480 .freeze = amdgpu_pmops_freeze,
481 .thaw = amdgpu_pmops_thaw,
482 .poweroff = amdgpu_pmops_freeze,
483 .restore = amdgpu_pmops_resume,
484 .runtime_suspend = amdgpu_pmops_runtime_suspend,
485 .runtime_resume = amdgpu_pmops_runtime_resume,
486 .runtime_idle = amdgpu_pmops_runtime_idle,
487};
488
489static const struct file_operations amdgpu_driver_kms_fops = {
490 .owner = THIS_MODULE,
491 .open = drm_open,
492 .release = drm_release,
493 .unlocked_ioctl = amdgpu_drm_ioctl,
494 .mmap = amdgpu_mmap,
495 .poll = drm_poll,
496 .read = drm_read,
497#ifdef CONFIG_COMPAT
498 .compat_ioctl = amdgpu_kms_compat_ioctl,
499#endif
500};
501
502static struct drm_driver kms_driver = {
503 .driver_features =
504 DRIVER_USE_AGP |
505 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
506 DRIVER_PRIME | DRIVER_RENDER,
507 .dev_priv_size = 0,
508 .load = amdgpu_driver_load_kms,
509 .open = amdgpu_driver_open_kms,
510 .preclose = amdgpu_driver_preclose_kms,
511 .postclose = amdgpu_driver_postclose_kms,
512 .lastclose = amdgpu_driver_lastclose_kms,
513 .set_busid = drm_pci_set_busid,
514 .unload = amdgpu_driver_unload_kms,
515 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
516 .enable_vblank = amdgpu_enable_vblank_kms,
517 .disable_vblank = amdgpu_disable_vblank_kms,
518 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
519 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
520#if defined(CONFIG_DEBUG_FS)
521 .debugfs_init = amdgpu_debugfs_init,
522 .debugfs_cleanup = amdgpu_debugfs_cleanup,
523#endif
524 .irq_preinstall = amdgpu_irq_preinstall,
525 .irq_postinstall = amdgpu_irq_postinstall,
526 .irq_uninstall = amdgpu_irq_uninstall,
527 .irq_handler = amdgpu_irq_handler,
528 .ioctls = amdgpu_ioctls_kms,
e7294dee 529 .gem_free_object_unlocked = amdgpu_gem_object_free,
d38ceaf9
AD		 530 .gem_open_object = amdgpu_gem_object_open,
531 .gem_close_object = amdgpu_gem_object_close,
532 .dumb_create = amdgpu_mode_dumb_create,
533 .dumb_map_offset = amdgpu_mode_dumb_mmap,
534 .dumb_destroy = drm_gem_dumb_destroy,
535 .fops = &amdgpu_driver_kms_fops,
536
537 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
538 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
539 .gem_prime_export = amdgpu_gem_prime_export,
540 .gem_prime_import = drm_gem_prime_import,
541 .gem_prime_pin = amdgpu_gem_prime_pin,
542 .gem_prime_unpin = amdgpu_gem_prime_unpin,
543 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
544 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
545 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
546 .gem_prime_vmap = amdgpu_gem_prime_vmap,
547 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
548
549 .name = DRIVER_NAME,
550 .desc = DRIVER_DESC,
551 .date = DRIVER_DATE,
552 .major = KMS_DRIVER_MAJOR,
553 .minor = KMS_DRIVER_MINOR,
554 .patchlevel = KMS_DRIVER_PATCHLEVEL,
555};
556
557static struct drm_driver *driver;
558static struct pci_driver *pdriver;
559
560static struct pci_driver amdgpu_kms_pci_driver = {
561 .name = DRIVER_NAME,
562 .id_table = pciidlist,
563 .probe = amdgpu_pci_probe,
564 .remove = amdgpu_pci_remove,
565 .driver.pm = &amdgpu_pm_ops,
566};
567
568static int __init amdgpu_init(void)
569{
257bf15a 570 amdgpu_sync_init();
d38ceaf9
AD		 571 if (vgacon_text_force()) {
572 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
573 return -EINVAL;
574 }
d38ceaf9
AD		 575 DRM_INFO("amdgpu kernel modesetting enabled.\n");
576 driver = &kms_driver;
577 pdriver = &amdgpu_kms_pci_driver;
578 driver->driver_features |= DRIVER_MODESET;
579 driver->num_ioctls = amdgpu_max_kms_ioctl;
580 amdgpu_register_atpx_handler();
581
582 /* let modprobe override vga console setting */
583 return drm_pci_init(driver, pdriver);
584}
585
586static void __exit amdgpu_exit(void)
587{
130e0371 588 amdgpu_amdkfd_fini();
d38ceaf9
AD		 589 drm_pci_exit(driver, pdriver);
590 amdgpu_unregister_atpx_handler();
257bf15a 591 amdgpu_sync_fini();
d38ceaf9
AD		 592}
593
594module_init(amdgpu_init);
595module_exit(amdgpu_exit);
596
597MODULE_AUTHOR(DRIVER_AUTHOR);
598MODULE_DESCRIPTION(DRIVER_DESC);
599MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)