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drm/amdgpu: Add auto mode for compute partition
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
d38ceaf9 25#include <drm/amdgpu_drm.h>
fdf2f6c5 26#include <drm/drm_drv.h>
8ab59da2 27#include <drm/drm_fbdev_generic.h>
d38ceaf9 28#include <drm/drm_gem.h>
fdf2f6c5 29#include <drm/drm_vblank.h>
8aba21b7 30#include <drm/drm_managed.h>
d38ceaf9
AD		 31#include "amdgpu_drv.h"
32
33#include <drm/drm_pciids.h>
d38ceaf9
AD		 34#include <linux/module.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
fcd70cd3 37#include <drm/drm_probe_helper.h>
c7d8b782 38#include <linux/mmu_notifier.h>
e25443d2 39#include <linux/suspend.h>
e9d1d2bb 40#include <linux/cc_platform.h>
f158936b 41#include <linux/dynamic_debug.h>
d38ceaf9
AD		 42
43#include "amdgpu.h"
44#include "amdgpu_irq.h"
2fbd6f94 45#include "amdgpu_dma_buf.h"
5088d657 46#include "amdgpu_sched.h"
87444254 47#include "amdgpu_fdinfo.h"
130e0371
OG		 48#include "amdgpu_amdkfd.h"
49
7c6e68c7 50#include "amdgpu_ras.h"
e3c1b071 51#include "amdgpu_xgmi.h"
04442bf7 52#include "amdgpu_reset.h"
7c6e68c7 53
d38ceaf9
AD		 54/*
55 * KMS wrapper.
56 * - 3.0.0 - initial driver
6055f37a 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
59 * at the end of IBs.
d347ce66 60 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 62 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 64 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 65 * - 3.8.0 - Add support raster config init in the kernel
ef704318 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 69 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 70 * - 3.13.0 - Add PRT support
203eb0cb 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 72 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 73 * - 3.16.0 - Add reserved vmid support
68e2c5ff 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 75 * - 3.18.0 - Export gpu always on cu bitmap
33476319 76 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 77 * - 3.20.0 - Add support for local BOs
7ca24cf2 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 80 * - 3.23.0 - Add query for VRAM lost counter
f8e3e0ee 81 * - 3.24.0 - Add high priority compute support for gfx9
7b158d16 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
d240cd9e 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
c19a23fa 84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
67dd1a36 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
41cca166 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
767e06a9 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
df8368be 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
1afeb314 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
635e2c5f 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
965ebe3d 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
815fb4c9 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
664fe85a 93 * - 3.36.0 - Allow reading more status registers on si/cik
ff532461 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
43c8546b 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
174b328b 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
16c642ec 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
b50368da 98 * - 3.41.0 - Add video codec query
915821a7 99 * - 3.42.0 - Add 16bpc fixed point display support
5c67ff3a 100 * - 3.43.0 - Add device hot plug/unplug support
f2e7d856 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
ded81d5b 102 * - 3.45.0 - Add context ioctl stable pstate interface
08cffb3e 103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
465576ca
AD		 104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
105 * - 3.48.0 - Add IP discovery version info to HW INFO
cf5cf349
EQ		 106 * - 3.49.0 - Add gang submit into CS IOCTL
107 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
108 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
e3e84b0a 109 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
b299221f
MO		 110 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
111 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
112 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
8a93c691 113 * 3.53.0 - Support for GFX11 CP GFX shadowing
489763af 114 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
d38ceaf9
AD		 115 */
116#define KMS_DRIVER_MAJOR 3
489763af 117#define KMS_DRIVER_MINOR 54
d38ceaf9
AD		 118#define KMS_DRIVER_PATCHLEVEL 0
119
0b04ea39 120unsigned int amdgpu_vram_limit = UINT_MAX;
87fb7833 121int amdgpu_vis_vram_limit;
83e74db6 122int amdgpu_gart_size = -1; /* auto */
36d38372 123int amdgpu_gtt_size = -1; /* auto */
95844d20 124int amdgpu_moverate = -1; /* auto */
d38ceaf9 125int amdgpu_audio = -1;
87fb7833
DV		 126int amdgpu_disp_priority;
127int amdgpu_hw_i2c;
d38ceaf9
AD		 128int amdgpu_pcie_gen2 = -1;
129int amdgpu_msi = -1;
f440ff44 130char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
d38ceaf9 131int amdgpu_dpm = -1;
e635ee07 132int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 133int amdgpu_aspm = -1;
134int amdgpu_runtime_pm = -1;
0b693f0b 135uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9 136int amdgpu_bapm = -1;
87fb7833 137int amdgpu_deep_color;
bab4fee7 138int amdgpu_vm_size = -1;
d07f14be 139int amdgpu_vm_fragment_size = -1;
d38ceaf9 140int amdgpu_vm_block_size = -1;
87fb7833
DV		 141int amdgpu_vm_fault_stop;
142int amdgpu_vm_debug;
9a4b7d4c 143int amdgpu_vm_update_mode = -1;
87fb7833 144int amdgpu_exp_hw_support;
4562236b 145int amdgpu_dc = -1;
b70f014d 146int amdgpu_sched_jobs = 32;
4afcb303 147int amdgpu_sched_hw_submission = 2;
87fb7833
DV		 148uint amdgpu_pcie_gen_cap;
149uint amdgpu_pcie_lane_cap;
25faeddc 150u64 amdgpu_cg_mask = 0xffffffffffffffff;
0b693f0b
RZ		 151uint amdgpu_pg_mask = 0xffffffff;
152uint amdgpu_sdma_phase_quantum = 32;
e86c30e9
SS		 153char *amdgpu_disable_cu;
154char *amdgpu_virtual_display;
680602d6
KF		 155
156/*
157 * OverDrive(bit 14) disabled by default
158 * GFX DCS(bit 19) disabled by default
159 */
160uint amdgpu_pp_feature_mask = 0xfff7bfff;
87fb7833 161uint amdgpu_force_long_training;
e8835e0e 162int amdgpu_lbpw = -1;
4a75aefe 163int amdgpu_compute_multipipe = -1;
dcebf026 164int amdgpu_gpu_recovery = -1; /* auto */
87fb7833
DV		 165int amdgpu_emu_mode;
166uint amdgpu_smu_memory_pool_size;
8738a82b 167int amdgpu_smu_pptable_id = -1;
191a3c04
EQ		 168/*
169 * FBC (bit 0) disabled by default
170 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
171 * - With this, for multiple monitors in sync(e.g. with the same model),
172 * mclk switching will be allowed. And the mclk will be not foced to the
173 * highest. That helps saving some idle power.
174 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
175 * PSR (bit 3) disabled by default
a5148245 176 * EDP NO POWER SEQUENCING (bit 4) disabled by default
191a3c04
EQ		 177 */
178uint amdgpu_dc_feature_mask = 2;
87fb7833 179uint amdgpu_dc_debug_mask;
792a0cdd 180uint amdgpu_dc_visual_confirm;
5bfca069 181int amdgpu_async_gfx_ring = 1;
87fb7833 182int amdgpu_mcbp;
63e2fef6 183int amdgpu_discovery = -1;
87fb7833 184int amdgpu_mes;
928fe236 185int amdgpu_mes_kiq;
d5cc02d9 186int amdgpu_noretry = -1;
4e66d7d2 187int amdgpu_force_asic_type = -1;
58aa7790 188int amdgpu_tmz = -1; /* auto */
4243c84a 189uint amdgpu_freesync_vid_mode;
273da6ff 190int amdgpu_reset_method = -1; /* auto */
a300de40 191int amdgpu_num_kcq = -1;
30d95a37 192int amdgpu_smartshift_bias;
158a05a0 193int amdgpu_use_xgmi_p2p = 1;
11eb648d 194int amdgpu_vcnfw_log;
bf0207e1 195int amdgpu_sg_display = -1; /* auto */
570de94b 196int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
7875a226 197
e3c1b071 198static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
199
f158936b
JC		 200DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
201 "DRM_UT_CORE",
202 "DRM_UT_DRIVER",
203 "DRM_UT_KMS",
204 "DRM_UT_PRIME",
205 "DRM_UT_ATOMIC",
206 "DRM_UT_VBL",
207 "DRM_UT_STATE",
208 "DRM_UT_LEASE",
209 "DRM_UT_DP",
210 "DRM_UT_DRMRES");
211
62d73fbc
EQ		 212struct amdgpu_mgpu_info mgpu_info = {
213 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
e3c1b071 214 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
215 mgpu_info.delayed_reset_work,
216 amdgpu_drv_delayed_reset_work_handler, 0),
62d73fbc 217};
1218252f 218int amdgpu_ras_enable = -1;
e53aec7e 219uint amdgpu_ras_mask = 0xffffffff;
acc0204c 220int amdgpu_bad_page_threshold = -1;
88f8575b
DL		 221struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
222 .timeout_fatal_disable = false,
28a5d7a5 223 .period = 0x0, /* default to 0x0 (timeout disable) */
88f8575b 224};
d38ceaf9 225
8405cf39
SJ		 226/**
227 * DOC: vramlimit (int)
228 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
229 */
d38ceaf9
AD		 230MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
231module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
232
8405cf39
SJ		 233/**
234 * DOC: vis_vramlimit (int)
235 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
236 */
218b5dcd
JB		 237MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
238module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
239
8405cf39
SJ		 240/**
241 * DOC: gartsize (uint)
570513ba
PM		 242 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
243 * The default is -1 (The size depends on asic).
8405cf39 244 */
570513ba 245MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 246module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 247
8405cf39
SJ		 248/**
249 * DOC: gttsize (int)
570513ba
PM		 250 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
251 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
8405cf39 252 */
570513ba 253MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
36d38372 254module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 255
8405cf39
SJ		 256/**
257 * DOC: moverate (int)
258 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
259 */
95844d20
MO		 260MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
261module_param_named(moverate, amdgpu_moverate, int, 0600);
262
8405cf39
SJ		 263/**
264 * DOC: audio (int)
265 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
266 */
d38ceaf9
AD		 267MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
268module_param_named(audio, amdgpu_audio, int, 0444);
269
8405cf39
SJ		 270/**
271 * DOC: disp_priority (int)
272 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
273 */
d38ceaf9
AD		 274MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
275module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
276
8405cf39
SJ		 277/**
278 * DOC: hw_i2c (int)
279 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
280 */
d38ceaf9
AD		 281MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
282module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
283
8405cf39
SJ		 284/**
285 * DOC: pcie_gen2 (int)
286 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
287 */
d38ceaf9
AD		 288MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
289module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
290
8405cf39
SJ		 291/**
292 * DOC: msi (int)
293 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
294 */
d38ceaf9
AD		 295MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
296module_param_named(msi, amdgpu_msi, int, 0444);
297
8405cf39 298/**
912dfc84
EQ		 299 * DOC: lockup_timeout (string)
300 * Set GPU scheduler timeout value in ms.
301 *
302 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
303 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
879e723d
AZ		 304 * to the default timeout.
305 *
306 * - With one value specified, the setting will apply to all non-compute jobs.
307 * - With multiple values specified, the first one will be for GFX.
308 * The second one is for Compute. The third and fourth ones are
309 * for SDMA and Video.
310 *
912dfc84 311 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
67387dfe 312 * jobs is 10000. The timeout for compute is 60000.
912dfc84 313 */
67387dfe 314MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
bcccee89 315 "for passthrough or sriov, 10000 for all jobs."
71cc9ef3 316 " 0: keep default value. negative: infinity timeout), "
bcccee89
ED		 317 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
318 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
912dfc84 319module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
d38ceaf9 320
8405cf39
SJ		 321/**
322 * DOC: dpm (int)
54b998ca 323 * Override for dynamic power management setting
5c9a6272 324 * (0 = disable, 1 = enable)
54b998ca 325 * The default is -1 (auto).
8405cf39 326 */
d38ceaf9
AD		 327MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
328module_param_named(dpm, amdgpu_dpm, int, 0444);
329
8405cf39
SJ		 330/**
331 * DOC: fw_load_type (int)
ddb267b6
YD		 332 * Set different firmware loading type for debugging, if supported.
333 * Set to 0 to force direct loading if supported by the ASIC. Set
334 * to -1 to select the default loading mode for the ASIC, as defined
335 * by the driver. The default is -1 (auto).
8405cf39 336 */
a76be7bb 337MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
e635ee07 338module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9 339
8405cf39
SJ		 340/**
341 * DOC: aspm (int)
342 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
343 */
d38ceaf9
AD		 344MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
345module_param_named(aspm, amdgpu_aspm, int, 0444);
346
8405cf39
SJ		 347/**
348 * DOC: runpm (int)
4d625a97
AD		 349 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
350 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
351 * Setting the value to 0 disables this functionality.
8405cf39 352 */
4d625a97 353MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
d38ceaf9
AD		 354module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
355
8405cf39
SJ		 356/**
357 * DOC: ip_block_mask (uint)
358 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
359 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
360 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
361 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
362 */
d38ceaf9
AD		 363MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
364module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
365
8405cf39
SJ		 366/**
367 * DOC: bapm (int)
368 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
369 * The default -1 (auto, enabled)
370 */
d38ceaf9
AD		 371MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
372module_param_named(bapm, amdgpu_bapm, int, 0444);
373
8405cf39
SJ		 374/**
375 * DOC: deep_color (int)
376 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
377 */
d38ceaf9
AD		 378MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
379module_param_named(deep_color, amdgpu_deep_color, int, 0444);
380
8405cf39
SJ		 381/**
382 * DOC: vm_size (int)
383 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
384 */
ed885b21 385MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 386module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be 387
8405cf39
SJ		 388/**
389 * DOC: vm_fragment_size (int)
390 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
391 */
d07f14be
RH		 392MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
393module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9 394
8405cf39
SJ		 395/**
396 * DOC: vm_block_size (int)
397 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
398 */
d38ceaf9
AD		 399MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
400module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
401
8405cf39
SJ		 402/**
403 * DOC: vm_fault_stop (int)
404 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
405 */
d9c13156
CK		 406MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
407module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
408
8405cf39
SJ		 409/**
410 * DOC: vm_debug (int)
411 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
412 */
b495bd3a
CK		 413MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
414module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
415
8405cf39
SJ		 416/**
417 * DOC: vm_update_mode (int)
418 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
419 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
420 */
9a4b7d4c
HK		 421MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
422module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
423
8405cf39
SJ		 424/**
425 * DOC: exp_hw_support (int)
426 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
427 */
d38ceaf9
AD		 428MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
429module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
430
8405cf39
SJ		 431/**
432 * DOC: dc (int)
433 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
434 */
4562236b
HW		 435MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
436module_param_named(dc, amdgpu_dc, int, 0444);
437
8405cf39
SJ		 438/**
439 * DOC: sched_jobs (int)
440 * Override the max number of jobs supported in the sw queue. The default is 32.
441 */
b70f014d 442MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 443module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
444
8405cf39
SJ		 445/**
446 * DOC: sched_hw_submission (int)
447 * Override the max number of HW submissions. The default is 2.
448 */
4afcb303
JZ		 449MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
450module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
451
8405cf39 452/**
7427a7a0 453 * DOC: ppfeaturemask (hexint)
8405cf39
SJ		 454 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
455 * The default is the current set of stable power features.
456 */
5141e9d2 457MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
7427a7a0 458module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
3a74f6f2 459
367039bf
TY		 460/**
461 * DOC: forcelongtraining (uint)
462 * Force long memory training in resume.
463 * The default is zero, indicates short training in resume.
464 */
465MODULE_PARM_DESC(forcelongtraining, "force memory long training");
466module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
467
8405cf39
SJ		 468/**
469 * DOC: pcie_gen_cap (uint)
470 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
471 * The default is 0 (automatic for each asic).
472 */
cd474ba0
AD		 473MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
474module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
475
8405cf39
SJ		 476/**
477 * DOC: pcie_lane_cap (uint)
478 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
479 * The default is 0 (automatic for each asic).
480 */
cd474ba0
AD		 481MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
482module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
483
8405cf39 484/**
25faeddc 485 * DOC: cg_mask (ullong)
8405cf39 486 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
25faeddc 487 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
8405cf39 488 */
395d1fb9 489MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
25faeddc 490module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
395d1fb9 491
8405cf39
SJ		 492/**
493 * DOC: pg_mask (uint)
494 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
495 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
496 */
395d1fb9
NH		 497MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
498module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
499
8405cf39
SJ		 500/**
501 * DOC: sdma_phase_quantum (uint)
502 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
503 */
a667386c
FK		 504MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
505module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
506
8405cf39
SJ		 507/**
508 * DOC: disable_cu (charp)
509 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
510 */
6f8941a2
NH		 511MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
512module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
513
8405cf39
SJ		 514/**
515 * DOC: virtual_display (charp)
516 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
517 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
518 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
519 * device at 26:00.0. The default is NULL.
520 */
0f66356d
ED		 521MODULE_PARM_DESC(virtual_display,
522 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 523module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 524
8405cf39
SJ		 525/**
526 * DOC: lbpw (int)
527 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
528 */
e8835e0e
HZ		 529MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
530module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 531
4a75aefe
AR		 532MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
533module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
534
8405cf39
SJ		 535/**
536 * DOC: gpu_recovery (int)
537 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
538 */
06a2d7cc 539MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
dcebf026
AG		 540module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
541
8405cf39
SJ		 542/**
543 * DOC: emu_mode (int)
544 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
545 */
d869ae09 546MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
bfca0289
SL		 547module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
548
1218252f 549/**
2f3940e9 550 * DOC: ras_enable (int)
1218252f 551 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
552 */
2f3940e9 553MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
1218252f 554module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
555
556/**
2f3940e9 557 * DOC: ras_mask (uint)
1218252f 558 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
559 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
560 */
2f3940e9 561MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
1218252f 562module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
563
88f8575b
DL		 564/**
565 * DOC: timeout_fatal_disable (bool)
566 * Disable Watchdog timeout fatal error event
567 */
568MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
569module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
570
571/**
572 * DOC: timeout_period (uint)
573 * Modify the watchdog timeout max_cycles as (1 << period)
574 */
28a5d7a5 575MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
88f8575b
DL		 576module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
577
8405cf39
SJ		 578/**
579 * DOC: si_support (int)
580 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
581 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
582 * otherwise using amdgpu driver.
583 */
6dd13096 584#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56
MD		 585
586#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
6dd13096
FK		 587int amdgpu_si_support = 0;
588MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 589#else
590int amdgpu_si_support = 1;
591MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
592#endif
593
6dd13096
FK		 594module_param_named(si_support, amdgpu_si_support, int, 0444);
595#endif
596
8405cf39
SJ		 597/**
598 * DOC: cik_support (int)
599 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
600 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
601 * otherwise using amdgpu driver.
602 */
7df28986 603#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56
MD		 604
605#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
2b059658
MD		 606int amdgpu_cik_support = 0;
607MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 608#else
609int amdgpu_cik_support = 1;
610MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
611#endif
612
7df28986
FK		 613module_param_named(cik_support, amdgpu_cik_support, int, 0444);
614#endif
615
8405cf39
SJ		 616/**
617 * DOC: smu_memory_pool_size (uint)
618 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
619 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
620 */
7951e376
RZ		 621MODULE_PARM_DESC(smu_memory_pool_size,
622 "reserve gtt for smu debug usage, 0 = disable,"
623 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
624module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
625
51bcce46
HZ		 626/**
627 * DOC: async_gfx_ring (int)
628 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
629 */
630MODULE_PARM_DESC(async_gfx_ring,
5bfca069 631 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
51bcce46
HZ		 632module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
633
40562787
AD		 634/**
635 * DOC: mcbp (int)
636 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
637 */
b239c017
JX		 638MODULE_PARM_DESC(mcbp,
639 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
640module_param_named(mcbp, amdgpu_mcbp, int, 0444);
641
40562787
AD		 642/**
643 * DOC: discovery (int)
644 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
a79d3709 645 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
40562787 646 */
a190d1c7
XY		 647MODULE_PARM_DESC(discovery,
648 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
649module_param_named(discovery, amdgpu_discovery, int, 0444);
650
40562787
AD		 651/**
652 * DOC: mes (int)
653 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
654 * (0 = disabled (default), 1 = enabled)
655 */
38487284
JX		 656MODULE_PARM_DESC(mes,
657 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
658module_param_named(mes, amdgpu_mes, int, 0444);
659
928fe236
JX		 660/**
661 * DOC: mes_kiq (int)
662 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
663 * (0 = disabled (default), 1 = enabled)
664 */
665MODULE_PARM_DESC(mes_kiq,
666 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
667module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
668
d5cc02d9
AD		 669/**
670 * DOC: noretry (int)
9705c85f
FK		 671 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
672 * do not support per-process XNACK this also disables retry page faults.
d5cc02d9
AD		 673 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
674 */
75ee6487 675MODULE_PARM_DESC(noretry,
d5cc02d9 676 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
75ee6487
FK		 677module_param_named(noretry, amdgpu_noretry, int, 0644);
678
4e66d7d2
YZ		 679/**
680 * DOC: force_asic_type (int)
681 * A non negative value used to specify the asic type for all supported GPUs.
682 */
683MODULE_PARM_DESC(force_asic_type,
684 "A non negative value used to specify the asic type for all supported GPUs");
685module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
686
158a05a0
AS		 687/**
688 * DOC: use_xgmi_p2p (int)
689 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
690 */
691MODULE_PARM_DESC(use_xgmi_p2p,
692 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
693module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
4e66d7d2
YZ		 694
695
2690262e 696#ifdef CONFIG_HSA_AMD
521fb7d0
AL		 697/**
698 * DOC: sched_policy (int)
699 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
700 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
701 * assigns queues to HQDs.
702 */
2690262e 703int sched_policy = KFD_SCHED_POLICY_HWS;
521fb7d0
AL		 704module_param(sched_policy, int, 0444);
705MODULE_PARM_DESC(sched_policy,
706 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
707
708/**
709 * DOC: hws_max_conc_proc (int)
710 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
711 * number of VMIDs assigned to the HWS, which is also the default.
712 */
b7dfbd2e 713int hws_max_conc_proc = -1;
521fb7d0
AL		 714module_param(hws_max_conc_proc, int, 0444);
715MODULE_PARM_DESC(hws_max_conc_proc,
716 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
717
718/**
719 * DOC: cwsr_enable (int)
720 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
721 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
722 * disables it.
723 */
2690262e 724int cwsr_enable = 1;
521fb7d0
AL		 725module_param(cwsr_enable, int, 0444);
726MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
727
728/**
729 * DOC: max_num_of_queues_per_device (int)
730 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
731 * is 4096.
732 */
2690262e 733int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
521fb7d0
AL		 734module_param(max_num_of_queues_per_device, int, 0444);
735MODULE_PARM_DESC(max_num_of_queues_per_device,
736 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
737
738/**
739 * DOC: send_sigterm (int)
740 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
741 * but just print errors on dmesg. Setting 1 enables sending sigterm.
742 */
2690262e 743int send_sigterm;
521fb7d0
AL		 744module_param(send_sigterm, int, 0444);
745MODULE_PARM_DESC(send_sigterm,
746 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
747
748/**
749 * DOC: debug_largebar (int)
750 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
751 * system. This limits the VRAM size reported to ROCm applications to the visible
752 * size, usually 256MB.
753 * Default value is 0, diabled.
754 */
2690262e 755int debug_largebar;
521fb7d0
AL		 756module_param(debug_largebar, int, 0444);
757MODULE_PARM_DESC(debug_largebar,
758 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
759
760/**
761 * DOC: ignore_crat (int)
762 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
763 * table to get information about AMD APUs. This option can serve as a workaround on
764 * systems with a broken CRAT table.
6127896f
HR		 765 *
766 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
cec2cc7b 767 * whether use CRAT)
521fb7d0 768 */
2690262e 769int ignore_crat;
521fb7d0
AL		 770module_param(ignore_crat, int, 0444);
771MODULE_PARM_DESC(ignore_crat,
6127896f 772 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
521fb7d0 773
521fb7d0
AL		 774/**
775 * DOC: halt_if_hws_hang (int)
776 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
777 * Setting 1 enables halt on hang.
778 */
2690262e 779int halt_if_hws_hang;
521fb7d0
AL		 780module_param(halt_if_hws_hang, int, 0644);
781MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
29e76462
OZ		 782
783/**
784 * DOC: hws_gws_support(bool)
29633d0e
JG		 785 * Assume that HWS supports GWS barriers regardless of what firmware version
786 * check says. Default value: false (rely on MEC2 firmware version check).
29e76462
OZ		 787 */
788bool hws_gws_support;
789module_param(hws_gws_support, bool, 0444);
29633d0e 790MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
14328aa5
PC		 791
792/**
793 * DOC: queue_preemption_timeout_ms (int)
794 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
795 */
f51af435 796int queue_preemption_timeout_ms = 9000;
14328aa5
PC		 797module_param(queue_preemption_timeout_ms, int, 0644);
798MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
b2057956
FK		 799
800/**
801 * DOC: debug_evictions(bool)
802 * Enable extra debug messages to help determine the cause of evictions
803 */
804bool debug_evictions;
805module_param(debug_evictions, bool, 0644);
806MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
b80f050f
PY		 807
808/**
809 * DOC: no_system_mem_limit(bool)
810 * Disable system memory limit, to support multiple process shared memory
811 */
812bool no_system_mem_limit;
813module_param(no_system_mem_limit, bool, 0644);
814MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
815
6d909c5d
OZ		 816/**
817 * DOC: no_queue_eviction_on_vm_fault (int)
818 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
819 */
120ceaf7 820int amdgpu_no_queue_eviction_on_vm_fault;
6d909c5d
OZ		 821MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
822module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
2690262e 823#endif
521fb7d0 824
08a2fd23
RE		 825/**
826 * DOC: pcie_p2p (bool)
827 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
828 */
829#ifdef CONFIG_HSA_AMD_P2P
830bool pcie_p2p = true;
831module_param(pcie_p2p, bool, 0444);
832MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
833#endif
834
7875a226
AD		 835/**
836 * DOC: dcfeaturemask (uint)
837 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
838 * The default is the current set of stable display features.
839 */
840MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
841module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
842
8a791dab
HW		 843/**
844 * DOC: dcdebugmask (uint)
845 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
846 */
847MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
848module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
849
792a0cdd
LL		 850MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
851module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
852
ad4de27f
NK		 853/**
854 * DOC: abmlevel (uint)
855 * Override the default ABM (Adaptive Backlight Management) level used for DC
856 * enabled hardware. Requires DMCU to be supported and loaded.
857 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
858 * default. Values 1-4 control the maximum allowable brightness reduction via
859 * the ABM algorithm, with 1 being the least reduction and 4 being the most
860 * reduction.
861 *
862 * Defaults to 0, or disabled. Userspace can still override this level later
863 * after boot.
864 */
87fb7833 865uint amdgpu_dm_abm_level;
ad4de27f
NK		 866MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
867module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
868
7a46f05e
TI		 869int amdgpu_backlight = -1;
870MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
871module_param_named(backlight, amdgpu_backlight, bint, 0444);
872
d7ccb38d
HR		 873/**
874 * DOC: tmz (int)
875 * Trusted Memory Zone (TMZ) is a method to protect data being written
876 * to or read from memory.
877 *
878 * The default value: 0 (off). TODO: change to auto till it is completed.
879 */
58aa7790 880MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
d7ccb38d
HR		 881module_param_named(tmz, amdgpu_tmz, int, 0444);
882
4243c84a
MD		 883/**
884 * DOC: freesync_video (uint)
885 * Enable the optimization to adjust front porch timing to achieve seamless
886 * mode change experience when setting a freesync supported mode for which full
887 * modeset is not needed.
888 *
889 * The Display Core will add a set of modes derived from the base FreeSync
890 * video mode into the corresponding connector's mode list based on commonly
891 * used refresh rates and VRR range of the connected display, when users enable
892 * this feature. From the userspace perspective, they can see a seamless mode
893 * change experience when the change between different refresh rates under the
894 * same resolution. Additionally, userspace applications such as Video playback
895 * can read this modeset list and change the refresh rate based on the video
896 * frame rate. Finally, the userspace can also derive an appropriate mode for a
897 * particular refresh rate based on the FreeSync Mode and add it to the
898 * connector's mode list.
899 *
900 * Note: This is an experimental feature.
901 *
902 * The default value: 0 (off).
903 */
904MODULE_PARM_DESC(
905 freesync_video,
906 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
907module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
908
273da6ff
WS		 909/**
910 * DOC: reset_method (int)
2656fd23 911 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
273da6ff 912 */
2656fd23 913MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
273da6ff
WS		 914module_param_named(reset_method, amdgpu_reset_method, int, 0444);
915
acc0204c 916/**
e4e6a589
LT		 917 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
918 * threshold value of faulty pages detected by RAS ECC, which may
919 * result in the GPU entering bad status when the number of total
920 * faulty pages by ECC exceeds the threshold value.
acc0204c 921 */
f3cbe70e 922MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
acc0204c
GC		 923module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
924
a300de40
ML		 925MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
926module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
927
11eb648d
RD		 928/**
929 * DOC: vcnfw_log (int)
930 * Enable vcnfw log output for debugging, the default is disabled.
931 */
932MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
933module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
934
bf0207e1
AD		 935/**
936 * DOC: sg_display (int)
937 * Disable S/G (scatter/gather) display (i.e., display from system memory).
938 * This option is only relevant on APUs. Set this option to 0 to disable
939 * S/G display if you experience flickering or other issues under memory
940 * pressure and report the issue.
941 */
942MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
943module_param_named(sg_display, amdgpu_sg_display, int, 0444);
944
8738a82b
LL		 945/**
946 * DOC: smu_pptable_id (int)
947 * Used to override pptable id. id = 0 use VBIOS pptable.
948 * id > 0 use the soft pptable with specicfied id.
949 */
950MODULE_PARM_DESC(smu_pptable_id,
951 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
952module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
953
0fa49d10
SZ		 954/**
955 * DOC: partition_mode (int)
956 * Used to override the default SPX mode.
957 */
570de94b
LL		 958MODULE_PARM_DESC(
959 user_partt_mode,
960 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
961 0 = AMDGPU_SPX_PARTITION_MODE, \
0fa49d10
SZ		 962 1 = AMDGPU_DPX_PARTITION_MODE, \
963 2 = AMDGPU_TPX_PARTITION_MODE, \
964 3 = AMDGPU_QPX_PARTITION_MODE, \
965 4 = AMDGPU_CPX_PARTITION_MODE)");
966module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
967
bdbeb0dd
AD		 968/* These devices are not supported by amdgpu.
969 * They are supported by the mach64, r128, radeon drivers
970 */
971static const u16 amdgpu_unsupported_pciidlist[] = {
972 /* mach64 */
973 0x4354,
974 0x4358,
975 0x4554,
976 0x4742,
977 0x4744,
978 0x4749,
979 0x474C,
980 0x474D,
981 0x474E,
982 0x474F,
983 0x4750,
984 0x4751,
985 0x4752,
986 0x4753,
987 0x4754,
988 0x4755,
989 0x4756,
990 0x4757,
991 0x4758,
992 0x4759,
993 0x475A,
994 0x4C42,
995 0x4C44,
996 0x4C47,
997 0x4C49,
998 0x4C4D,
999 0x4C4E,
1000 0x4C50,
1001 0x4C51,
1002 0x4C52,
1003 0x4C53,
1004 0x5654,
1005 0x5655,
1006 0x5656,
1007 /* r128 */
1008 0x4c45,
1009 0x4c46,
1010 0x4d46,
1011 0x4d4c,
1012 0x5041,
1013 0x5042,
1014 0x5043,
1015 0x5044,
1016 0x5045,
1017 0x5046,
1018 0x5047,
1019 0x5048,
1020 0x5049,
1021 0x504A,
1022 0x504B,
1023 0x504C,
1024 0x504D,
1025 0x504E,
1026 0x504F,
1027 0x5050,
1028 0x5051,
1029 0x5052,
1030 0x5053,
1031 0x5054,
1032 0x5055,
1033 0x5056,
1034 0x5057,
1035 0x5058,
1036 0x5245,
1037 0x5246,
1038 0x5247,
1039 0x524b,
1040 0x524c,
1041 0x534d,
1042 0x5446,
1043 0x544C,
1044 0x5452,
1045 /* radeon */
1046 0x3150,
1047 0x3151,
1048 0x3152,
1049 0x3154,
1050 0x3155,
1051 0x3E50,
1052 0x3E54,
1053 0x4136,
1054 0x4137,
1055 0x4144,
1056 0x4145,
1057 0x4146,
1058 0x4147,
1059 0x4148,
1060 0x4149,
1061 0x414A,
1062 0x414B,
1063 0x4150,
1064 0x4151,
1065 0x4152,
1066 0x4153,
1067 0x4154,
1068 0x4155,
1069 0x4156,
1070 0x4237,
1071 0x4242,
1072 0x4336,
1073 0x4337,
1074 0x4437,
1075 0x4966,
1076 0x4967,
1077 0x4A48,
1078 0x4A49,
1079 0x4A4A,
1080 0x4A4B,
1081 0x4A4C,
1082 0x4A4D,
1083 0x4A4E,
1084 0x4A4F,
1085 0x4A50,
1086 0x4A54,
1087 0x4B48,
1088 0x4B49,
1089 0x4B4A,
1090 0x4B4B,
1091 0x4B4C,
1092 0x4C57,
1093 0x4C58,
1094 0x4C59,
1095 0x4C5A,
1096 0x4C64,
1097 0x4C66,
1098 0x4C67,
1099 0x4E44,
1100 0x4E45,
1101 0x4E46,
1102 0x4E47,
1103 0x4E48,
1104 0x4E49,
1105 0x4E4A,
1106 0x4E4B,
1107 0x4E50,
1108 0x4E51,
1109 0x4E52,
1110 0x4E53,
1111 0x4E54,
1112 0x4E56,
1113 0x5144,
1114 0x5145,
1115 0x5146,
1116 0x5147,
1117 0x5148,
1118 0x514C,
1119 0x514D,
1120 0x5157,
1121 0x5158,
1122 0x5159,
1123 0x515A,
1124 0x515E,
1125 0x5460,
1126 0x5462,
1127 0x5464,
1128 0x5548,
1129 0x5549,
1130 0x554A,
1131 0x554B,
1132 0x554C,
1133 0x554D,
1134 0x554E,
1135 0x554F,
1136 0x5550,
1137 0x5551,
1138 0x5552,
1139 0x5554,
1140 0x564A,
1141 0x564B,
1142 0x564F,
1143 0x5652,
1144 0x5653,
1145 0x5657,
1146 0x5834,
1147 0x5835,
1148 0x5954,
1149 0x5955,
1150 0x5974,
1151 0x5975,
1152 0x5960,
1153 0x5961,
1154 0x5962,
1155 0x5964,
1156 0x5965,
1157 0x5969,
1158 0x5a41,
1159 0x5a42,
1160 0x5a61,
1161 0x5a62,
1162 0x5b60,
1163 0x5b62,
1164 0x5b63,
1165 0x5b64,
1166 0x5b65,
1167 0x5c61,
1168 0x5c63,
1169 0x5d48,
1170 0x5d49,
1171 0x5d4a,
1172 0x5d4c,
1173 0x5d4d,
1174 0x5d4e,
1175 0x5d4f,
1176 0x5d50,
1177 0x5d52,
1178 0x5d57,
1179 0x5e48,
1180 0x5e4a,
1181 0x5e4b,
1182 0x5e4c,
1183 0x5e4d,
1184 0x5e4f,
1185 0x6700,
1186 0x6701,
1187 0x6702,
1188 0x6703,
1189 0x6704,
1190 0x6705,
1191 0x6706,
1192 0x6707,
1193 0x6708,
1194 0x6709,
1195 0x6718,
1196 0x6719,
1197 0x671c,
1198 0x671d,
1199 0x671f,
1200 0x6720,
1201 0x6721,
1202 0x6722,
1203 0x6723,
1204 0x6724,
1205 0x6725,
1206 0x6726,
1207 0x6727,
1208 0x6728,
1209 0x6729,
1210 0x6738,
1211 0x6739,
1212 0x673e,
1213 0x6740,
1214 0x6741,
1215 0x6742,
1216 0x6743,
1217 0x6744,
1218 0x6745,
1219 0x6746,
1220 0x6747,
1221 0x6748,
1222 0x6749,
1223 0x674A,
1224 0x6750,
1225 0x6751,
1226 0x6758,
1227 0x6759,
1228 0x675B,
1229 0x675D,
1230 0x675F,
1231 0x6760,
1232 0x6761,
1233 0x6762,
1234 0x6763,
1235 0x6764,
1236 0x6765,
1237 0x6766,
1238 0x6767,
1239 0x6768,
1240 0x6770,
1241 0x6771,
1242 0x6772,
1243 0x6778,
1244 0x6779,
1245 0x677B,
1246 0x6840,
1247 0x6841,
1248 0x6842,
1249 0x6843,
1250 0x6849,
1251 0x684C,
1252 0x6850,
1253 0x6858,
1254 0x6859,
1255 0x6880,
1256 0x6888,
1257 0x6889,
1258 0x688A,
1259 0x688C,
1260 0x688D,
1261 0x6898,
1262 0x6899,
1263 0x689b,
1264 0x689c,
1265 0x689d,
1266 0x689e,
1267 0x68a0,
1268 0x68a1,
1269 0x68a8,
1270 0x68a9,
1271 0x68b0,
1272 0x68b8,
1273 0x68b9,
1274 0x68ba,
1275 0x68be,
1276 0x68bf,
1277 0x68c0,
1278 0x68c1,
1279 0x68c7,
1280 0x68c8,
1281 0x68c9,
1282 0x68d8,
1283 0x68d9,
1284 0x68da,
1285 0x68de,
1286 0x68e0,
1287 0x68e1,
1288 0x68e4,
1289 0x68e5,
1290 0x68e8,
1291 0x68e9,
1292 0x68f1,
1293 0x68f2,
1294 0x68f8,
1295 0x68f9,
1296 0x68fa,
1297 0x68fe,
1298 0x7100,
1299 0x7101,
1300 0x7102,
1301 0x7103,
1302 0x7104,
1303 0x7105,
1304 0x7106,
1305 0x7108,
1306 0x7109,
1307 0x710A,
1308 0x710B,
1309 0x710C,
1310 0x710E,
1311 0x710F,
1312 0x7140,
1313 0x7141,
1314 0x7142,
1315 0x7143,
1316 0x7144,
1317 0x7145,
1318 0x7146,
1319 0x7147,
1320 0x7149,
1321 0x714A,
1322 0x714B,
1323 0x714C,
1324 0x714D,
1325 0x714E,
1326 0x714F,
1327 0x7151,
1328 0x7152,
1329 0x7153,
1330 0x715E,
1331 0x715F,
1332 0x7180,
1333 0x7181,
1334 0x7183,
1335 0x7186,
1336 0x7187,
1337 0x7188,
1338 0x718A,
1339 0x718B,
1340 0x718C,
1341 0x718D,
1342 0x718F,
1343 0x7193,
1344 0x7196,
1345 0x719B,
1346 0x719F,
1347 0x71C0,
1348 0x71C1,
1349 0x71C2,
1350 0x71C3,
1351 0x71C4,
1352 0x71C5,
1353 0x71C6,
1354 0x71C7,
1355 0x71CD,
1356 0x71CE,
1357 0x71D2,
1358 0x71D4,
1359 0x71D5,
1360 0x71D6,
1361 0x71DA,
1362 0x71DE,
1363 0x7200,
1364 0x7210,
1365 0x7211,
1366 0x7240,
1367 0x7243,
1368 0x7244,
1369 0x7245,
1370 0x7246,
1371 0x7247,
1372 0x7248,
1373 0x7249,
1374 0x724A,
1375 0x724B,
1376 0x724C,
1377 0x724D,
1378 0x724E,
1379 0x724F,
1380 0x7280,
1381 0x7281,
1382 0x7283,
1383 0x7284,
1384 0x7287,
1385 0x7288,
1386 0x7289,
1387 0x728B,
1388 0x728C,
1389 0x7290,
1390 0x7291,
1391 0x7293,
1392 0x7297,
1393 0x7834,
1394 0x7835,
1395 0x791e,
1396 0x791f,
1397 0x793f,
1398 0x7941,
1399 0x7942,
1400 0x796c,
1401 0x796d,
1402 0x796e,
1403 0x796f,
1404 0x9400,
1405 0x9401,
1406 0x9402,
1407 0x9403,
1408 0x9405,
1409 0x940A,
1410 0x940B,
1411 0x940F,
1412 0x94A0,
1413 0x94A1,
1414 0x94A3,
1415 0x94B1,
1416 0x94B3,
1417 0x94B4,
1418 0x94B5,
1419 0x94B9,
1420 0x9440,
1421 0x9441,
1422 0x9442,
1423 0x9443,
1424 0x9444,
1425 0x9446,
1426 0x944A,
1427 0x944B,
1428 0x944C,
1429 0x944E,
1430 0x9450,
1431 0x9452,
1432 0x9456,
1433 0x945A,
1434 0x945B,
1435 0x945E,
1436 0x9460,
1437 0x9462,
1438 0x946A,
1439 0x946B,
1440 0x947A,
1441 0x947B,
1442 0x9480,
1443 0x9487,
1444 0x9488,
1445 0x9489,
1446 0x948A,
1447 0x948F,
1448 0x9490,
1449 0x9491,
1450 0x9495,
1451 0x9498,
1452 0x949C,
1453 0x949E,
1454 0x949F,
1455 0x94C0,
1456 0x94C1,
1457 0x94C3,
1458 0x94C4,
1459 0x94C5,
1460 0x94C6,
1461 0x94C7,
1462 0x94C8,
1463 0x94C9,
1464 0x94CB,
1465 0x94CC,
1466 0x94CD,
1467 0x9500,
1468 0x9501,
1469 0x9504,
1470 0x9505,
1471 0x9506,
1472 0x9507,
1473 0x9508,
1474 0x9509,
1475 0x950F,
1476 0x9511,
1477 0x9515,
1478 0x9517,
1479 0x9519,
1480 0x9540,
1481 0x9541,
1482 0x9542,
1483 0x954E,
1484 0x954F,
1485 0x9552,
1486 0x9553,
1487 0x9555,
1488 0x9557,
1489 0x955f,
1490 0x9580,
1491 0x9581,
1492 0x9583,
1493 0x9586,
1494 0x9587,
1495 0x9588,
1496 0x9589,
1497 0x958A,
1498 0x958B,
1499 0x958C,
1500 0x958D,
1501 0x958E,
1502 0x958F,
1503 0x9590,
1504 0x9591,
1505 0x9593,
1506 0x9595,
1507 0x9596,
1508 0x9597,
1509 0x9598,
1510 0x9599,
1511 0x959B,
1512 0x95C0,
1513 0x95C2,
1514 0x95C4,
1515 0x95C5,
1516 0x95C6,
1517 0x95C7,
1518 0x95C9,
1519 0x95CC,
1520 0x95CD,
1521 0x95CE,
1522 0x95CF,
1523 0x9610,
1524 0x9611,
1525 0x9612,
1526 0x9613,
1527 0x9614,
1528 0x9615,
1529 0x9616,
1530 0x9640,
1531 0x9641,
1532 0x9642,
1533 0x9643,
1534 0x9644,
1535 0x9645,
1536 0x9647,
1537 0x9648,
1538 0x9649,
1539 0x964a,
1540 0x964b,
1541 0x964c,
1542 0x964e,
1543 0x964f,
1544 0x9710,
1545 0x9711,
1546 0x9712,
1547 0x9713,
1548 0x9714,
1549 0x9715,
1550 0x9802,
1551 0x9803,
1552 0x9804,
1553 0x9805,
1554 0x9806,
1555 0x9807,
1556 0x9808,
1557 0x9809,
1558 0x980A,
1559 0x9900,
1560 0x9901,
1561 0x9903,
1562 0x9904,
1563 0x9905,
1564 0x9906,
1565 0x9907,
1566 0x9908,
1567 0x9909,
1568 0x990A,
1569 0x990B,
1570 0x990C,
1571 0x990D,
1572 0x990E,
1573 0x990F,
1574 0x9910,
1575 0x9913,
1576 0x9917,
1577 0x9918,
1578 0x9919,
1579 0x9990,
1580 0x9991,
1581 0x9992,
1582 0x9993,
1583 0x9994,
1584 0x9995,
1585 0x9996,
1586 0x9997,
1587 0x9998,
1588 0x9999,
1589 0x999A,
1590 0x999B,
1591 0x999C,
1592 0x999D,
1593 0x99A0,
1594 0x99A2,
1595 0x99A4,
9e5a14bc
AD		 1596 /* radeon secondary ids */
1597 0x3171,
1598 0x3e70,
1599 0x4164,
1600 0x4165,
1601 0x4166,
1602 0x4168,
1603 0x4170,
1604 0x4171,
1605 0x4172,
1606 0x4173,
1607 0x496e,
1608 0x4a69,
1609 0x4a6a,
1610 0x4a6b,
1611 0x4a70,
1612 0x4a74,
1613 0x4b69,
1614 0x4b6b,
1615 0x4b6c,
1616 0x4c6e,
1617 0x4e64,
1618 0x4e65,
1619 0x4e66,
1620 0x4e67,
1621 0x4e68,
1622 0x4e69,
1623 0x4e6a,
1624 0x4e71,
1625 0x4f73,
1626 0x5569,
1627 0x556b,
1628 0x556d,
1629 0x556f,
1630 0x5571,
1631 0x5854,
1632 0x5874,
1633 0x5940,
1634 0x5941,
1635 0x5b72,
1636 0x5b73,
1637 0x5b74,
1638 0x5b75,
1639 0x5d44,
1640 0x5d45,
1641 0x5d6d,
1642 0x5d6f,
1643 0x5d72,
1644 0x5d77,
1645 0x5e6b,
1646 0x5e6d,
1647 0x7120,
1648 0x7124,
1649 0x7129,
1650 0x712e,
1651 0x712f,
1652 0x7162,
1653 0x7163,
1654 0x7166,
1655 0x7167,
1656 0x7172,
1657 0x7173,
1658 0x71a0,
1659 0x71a1,
1660 0x71a3,
1661 0x71a7,
1662 0x71bb,
1663 0x71e0,
1664 0x71e1,
1665 0x71e2,
1666 0x71e6,
1667 0x71e7,
1668 0x71f2,
1669 0x7269,
1670 0x726b,
1671 0x726e,
1672 0x72a0,
1673 0x72a8,
1674 0x72b1,
1675 0x72b3,
1676 0x793f,
bdbeb0dd
AD		 1677};
1678
f498d9ed 1679static const struct pci_device_id pciidlist[] = {
47fc644f 1680#ifdef CONFIG_DRM_AMDGPU_SI
78fbb685
KW		 1681 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1682 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1683 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1684 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1685 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1686 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1687 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1688 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1689 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1690 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1691 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1692 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1693 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1694 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1695 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1696 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1697 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1698 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1699 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1700 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1701 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1702 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1703 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1704 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1705 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1706 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1707 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1708 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1709 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1710 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1711 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1712 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1713 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1714 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1715 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1716 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1717 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1718 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1719 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1720 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1721 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1722 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1723 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1724 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1725 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1726 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1727 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1728 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1729 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1730 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1731 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1732 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1733 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1734 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1735 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1736 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1737 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1738 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1739 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1740 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1741 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1742 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1743 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1744 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1745 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1746 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1747 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1748 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1749 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1750 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1751 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1752 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1753#endif
89330c39
AD		 1754#ifdef CONFIG_DRM_AMDGPU_CIK
1755 /* Kaveri */
2f7d10b3
JZ		 1756 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1757 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1758 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1759 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1760 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1761 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1762 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1763 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1764 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1765 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1766 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1767 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1768 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1769 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1770 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1771 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1772 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1773 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1774 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1775 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1776 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1777 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 1778 /* Bonaire */
2f7d10b3
JZ		 1779 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1780 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1781 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1782 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 1783 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1784 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1785 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1786 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1787 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1788 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 1789 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 1790 /* Hawaii */
1791 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1792 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1793 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1794 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1795 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1796 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1797 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1798 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1799 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1800 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1801 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1802 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1803 /* Kabini */
2f7d10b3
JZ		 1804 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1805 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1806 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1807 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1808 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1809 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1810 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1811 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1812 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1813 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1814 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1815 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1816 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1817 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1818 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1819 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 1820 /* mullins */
2f7d10b3
JZ		 1821 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1822 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1823 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1824 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1825 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1826 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1827 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1828 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1829 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1830 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1831 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1832 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1833 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1834 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1835 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1836 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 1837#endif
1256a8b8 1838 /* topaz */
dba280b2
AD		 1839 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1840 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1841 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1842 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1843 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 1844 /* tonga */
1845 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1846 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1847 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1848 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1849 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1850 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1851 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1852 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1853 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 1854 /* fiji */
1855 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 1856 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 1857 /* carrizo */
2f7d10b3
JZ		 1858 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1859 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1860 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1861 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1862 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 1863 /* stoney */
1864 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 1865 /* Polaris11 */
1866 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1867 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1868 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1869 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1870 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1871 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 1872 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1873 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1874 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 1875 /* Polaris10 */
1876 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1877 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1878 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1879 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1880 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 1881 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 1882 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1883 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1884 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1885 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1886 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1887 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
30f3984e 1888 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 1889 /* Polaris12 */
1890 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1891 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1892 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1893 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1894 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 1895 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 1896 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 1897 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
e9307932
LL		 1898 /* VEGAM */
1899 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1900 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
f6653a0e 1901 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
ca2f1cca 1902 /* Vega 10 */
dfbf0c14
AD		 1903 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1904 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1905 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1906 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1907 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1908 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1909 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1910 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1911 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1912 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1913 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1914 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1915 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1916 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1917 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dc53d543
AD		 1918 /* Vega 12 */
1919 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1920 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1921 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1922 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1923 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1204a26e 1924 /* Vega 20 */
6dddaeef
AD		 1925 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1926 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1927 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1928 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
ec5b2020 1929 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
6dddaeef
AD		 1930 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1931 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
df515052 1932 /* Raven */
acc34503 1933 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
741deade 1934 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
48c69cda 1935 /* Arcturus */
12c5365e
AD		 1936 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1937 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1938 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1939 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
bd1c0fdf
AD		 1940 /* Navi10 */
1941 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1942 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1943 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1944 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1945 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1946 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
89428811 1947 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1948 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
26051720 1949 /* Navi14 */
b62d9554
AD		 1950 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1951 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1952 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1953 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
df515052 1954
61bdb39c 1955 /* Renoir */
775da830 1956 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
23fe1390 1957 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
8bf08351 1958 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
278cdb68 1959 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
61bdb39c 1960
10e85054 1961 /* Navi12 */
d34c7b7b
AD		 1962 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1963 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
10e85054 1964
61278d14
LG		 1965 /* Sienna_Cichlid */
1966 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
d26bbbcc 1967 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14
LG		 1968 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1969 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1970 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1971 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1972 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1973 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1974 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1975 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1976 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
ed098aa3 1977 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1978 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
10e85054 1979
27f5355f
AL		 1980 /* Yellow Carp */
1981 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1982 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1983
2c1eaddd
TZ		 1984 /* Navy_Flounder */
1985 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1986 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1987 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
8f0c93f4
AD		 1988 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1989 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1990 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1991 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1992 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2c1eaddd
TZ		 1993 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1994
e7de4aee
TZ		 1995 /* DIMGREY_CAVEFISH */
1996 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1997 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1998 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
06ac9b6c 1999 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
8f0c93f4
AD		 2000 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2001 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2002 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2003 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2004 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2005 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2006 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
e7de4aee
TZ		 2007 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2008
4c2e5f51 2009 /* Aldebaran */
3786a9bc
AD		 2010 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2011 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2012 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2013 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
4c2e5f51 2014
a8f70696
TZ		 2015 /* CYAN_SKILLFISH */
2016 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
dfcc3e8c 2017 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
a8f70696 2018
a2e9b166
CG		 2019 /* BEIGE_GOBY */
2020 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2021 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2022 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2023 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
62e9bd20 2024 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
a2e9b166
CG		 2025 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2026
eb4fd29a
AD		 2027 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2028 .class = PCI_CLASS_DISPLAY_VGA << 8,
2029 .class_mask = 0xffffff,
d0761fd2 2030 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a
AD		 2031
2032 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2033 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2034 .class_mask = 0xffffff,
d0761fd2 2035 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a 2036
d38ceaf9
AD		 2037 {0, 0, 0}
2038};
2039
2040MODULE_DEVICE_TABLE(pci, pciidlist);
2041
5088d657 2042static const struct drm_driver amdgpu_kms_driver;
d38ceaf9 2043
243c719e 2044static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
d0d66b8c
AD		 2045{
2046 struct pci_dev *p = NULL;
243c719e 2047 int i;
d0d66b8c 2048
243c719e
AD		 2049 /* 0 - GPU
2050 * 1 - audio
2051 * 2 - USB
2052 * 3 - UCSI
2053 */
2054 for (i = 1; i < 4; i++) {
2055 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2056 adev->pdev->bus->number, i);
2057 if (p) {
2058 pm_runtime_get_sync(&p->dev);
2059 pm_runtime_mark_last_busy(&p->dev);
2060 pm_runtime_put_autosuspend(&p->dev);
2061 pci_dev_put(p);
2062 }
d0d66b8c
AD		 2063 }
2064}
2065
d38ceaf9
AD		 2066static int amdgpu_pci_probe(struct pci_dev *pdev,
2067 const struct pci_device_id *ent)
2068{
8aba21b7 2069 struct drm_device *ddev;
c6385e50 2070 struct amdgpu_device *adev;
d38ceaf9 2071 unsigned long flags = ent->driver_data;
bdbeb0dd 2072 int ret, retry = 0, i;
3fa203af
AD		 2073 bool supports_atomic = false;
2074
bdbeb0dd
AD		 2075 /* skip devices which are owned by radeon */
2076 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2077 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2078 return -ENODEV;
2079 }
2080
7294863a
ML		 2081 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2082 amdgpu_aspm = 0;
2083
84ec374b 2084 if (amdgpu_virtual_display ||
3fa203af
AD		 2085 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2086 supports_atomic = true;
d38ceaf9 2087
2f7d10b3 2088 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 2089 DRM_INFO("This hardware requires experimental hardware support.\n"
2090 "See modparam exp_hw_support\n");
2091 return -ENODEV;
2092 }
1d4624cd
AD		 2093 /* differentiate between P10 and P11 asics with the same DID */
2094 if (pdev->device == 0x67FF &&
2095 (pdev->revision == 0xE3 ||
2096 pdev->revision == 0xE7 ||
2097 pdev->revision == 0xF3 ||
2098 pdev->revision == 0xF7)) {
2099 flags &= ~AMD_ASIC_MASK;
2100 flags |= CHIP_POLARIS10;
2101 }
d38ceaf9 2102
ea68573d
AD		 2103 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2104 * however, SME requires an indirect IOMMU mapping because the encryption
2105 * bit is beyond the DMA mask of the chip.
2106 */
e9d1d2bb
TL		 2107 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2108 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
ea68573d
AD		 2109 dev_info(&pdev->dev,
2110 "SME is not compatible with RAVEN\n");
2111 return -ENOTSUPP;
2112 }
2113
984d7a92
HG		 2114#ifdef CONFIG_DRM_AMDGPU_SI
2115 if (!amdgpu_si_support) {
2116 switch (flags & AMD_ASIC_MASK) {
2117 case CHIP_TAHITI:
2118 case CHIP_PITCAIRN:
2119 case CHIP_VERDE:
2120 case CHIP_OLAND:
2121 case CHIP_HAINAN:
2122 dev_info(&pdev->dev,
2123 "SI support provided by radeon.\n");
2124 dev_info(&pdev->dev,
2125 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2126 );
2127 return -ENODEV;
2128 }
2129 }
2130#endif
2131#ifdef CONFIG_DRM_AMDGPU_CIK
2132 if (!amdgpu_cik_support) {
2133 switch (flags & AMD_ASIC_MASK) {
2134 case CHIP_KAVERI:
2135 case CHIP_BONAIRE:
2136 case CHIP_HAWAII:
2137 case CHIP_KABINI:
2138 case CHIP_MULLINS:
2139 dev_info(&pdev->dev,
2140 "CIK support provided by radeon.\n");
2141 dev_info(&pdev->dev,
2142 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2143 );
2144 return -ENODEV;
2145 }
2146 }
2147#endif
2148
5088d657 2149 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
df2ce459
LT		 2150 if (IS_ERR(adev))
2151 return PTR_ERR(adev);
8aba21b7
LT		 2152
2153 adev->dev = &pdev->dev;
2154 adev->pdev = pdev;
2155 ddev = adev_to_drm(adev);
b58c1131 2156
351c4dbe 2157 if (!supports_atomic)
8aba21b7 2158 ddev->driver_features &= ~DRIVER_ATOMIC;
351c4dbe 2159
b58c1131
AD		 2160 ret = pci_enable_device(pdev);
2161 if (ret)
df2ce459 2162 return ret;
b58c1131 2163
8aba21b7 2164 pci_set_drvdata(pdev, ddev);
b58c1131 2165
1d4624cd 2166 ret = amdgpu_driver_load_kms(adev, flags);
7504d3bb
LC		 2167 if (ret)
2168 goto err_pci;
c6385e50 2169
1daee8b4 2170retry_init:
1d4624cd 2171 ret = drm_dev_register(ddev, flags);
1daee8b4
PD		 2172 if (ret == -EAGAIN && ++retry <= 3) {
2173 DRM_INFO("retry init %d\n", retry);
2174 /* Don't request EX mode too frequently which is attacking */
2175 msleep(5000);
2176 goto retry_init;
8aba21b7 2177 } else if (ret) {
b58c1131 2178 goto err_pci;
8aba21b7 2179 }
b58c1131 2180
087451f3
EQ		 2181 /*
2182 * 1. don't init fbdev on hw without DCE
2183 * 2. don't init fbdev if there are no connectors
2184 */
2185 if (adev->mode_info.mode_config_initialized &&
2186 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2187 /* select 8 bpp console on low vram cards */
2188 if (adev->gmc.real_vram_size <= (32*1024*1024))
2189 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2190 else
2191 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2192 }
2193
c6385e50
AD		 2194 ret = amdgpu_debugfs_init(adev);
2195 if (ret)
2196 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2197
9c913f38 2198 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
d0d66b8c
AD		 2199 /* only need to skip on ATPX */
2200 if (amdgpu_device_supports_px(ddev))
2201 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2202 /* we want direct complete for BOCO */
2203 if (amdgpu_device_supports_boco(ddev))
2204 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2205 DPM_FLAG_SMART_SUSPEND |
2206 DPM_FLAG_MAY_SKIP_RESUME);
2207 pm_runtime_use_autosuspend(ddev->dev);
2208 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2209
2210 pm_runtime_allow(ddev->dev);
2211
2212 pm_runtime_mark_last_busy(ddev->dev);
2213 pm_runtime_put_autosuspend(ddev->dev);
2214
2215 /*
2216 * For runpm implemented via BACO, PMFW will handle the
2217 * timing for BACO in and out:
2218 * - put ASIC into BACO state only when both video and
2219 * audio functions are in D3 state.
2220 * - pull ASIC out of BACO state when either video or
2221 * audio function is in D0 state.
2222 * Also, at startup, PMFW assumes both functions are in
2223 * D0 state.
2224 *
2225 * So if snd driver was loaded prior to amdgpu driver
2226 * and audio function was put into D3 state, there will
2227 * be no PMFW-aware D-state transition(D0->D3) on runpm
2228 * suspend. Thus the BACO will be not correctly kicked in.
2229 *
243c719e 2230 * Via amdgpu_get_secondary_funcs(), the audio dev is put
d0d66b8c
AD		 2231 * into D0 state. Then there will be a PMFW-aware D-state
2232 * transition(D0->D3) on runpm suspend.
2233 */
2234 if (amdgpu_device_supports_baco(ddev) &&
2235 !(adev->flags & AMD_IS_APU) &&
2236 (adev->asic_type >= CHIP_NAVI10))
243c719e 2237 amdgpu_get_secondary_funcs(adev);
d0d66b8c
AD		 2238 }
2239
b58c1131
AD		 2240 return 0;
2241
2242err_pci:
2243 pci_disable_device(pdev);
b58c1131 2244 return ret;
d38ceaf9
AD		 2245}
2246
2247static void
2248amdgpu_pci_remove(struct pci_dev *pdev)
2249{
2250 struct drm_device *dev = pci_get_drvdata(pdev);
d0d66b8c 2251 struct amdgpu_device *adev = drm_to_adev(dev);
d38ceaf9 2252
39934d3e
VP		 2253 drm_dev_unplug(dev);
2254
9c913f38 2255 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
d0d66b8c
AD		 2256 pm_runtime_get_sync(dev->dev);
2257 pm_runtime_forbid(dev->dev);
2258 }
2259
2103c421
GW		 2260 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2261 !amdgpu_sriov_vf(adev)) {
f5c7e779
YC		 2262 bool need_to_reset_gpu = false;
2263
2264 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2265 struct amdgpu_hive_info *hive;
2266
2267 hive = amdgpu_get_xgmi_hive(adev);
2268 if (hive->device_remove_count == 0)
2269 need_to_reset_gpu = true;
2270 hive->device_remove_count++;
2271 amdgpu_put_xgmi_hive(hive);
2272 } else {
2273 need_to_reset_gpu = true;
2274 }
2275
2276 /* Workaround for ASICs need to reset SMU.
2277 * Called only when the first device is removed.
2278 */
2279 if (need_to_reset_gpu) {
2280 struct amdgpu_reset_context reset_context;
2281
83d29a5f 2282 adev->shutdown = true;
f5c7e779
YC		 2283 memset(&reset_context, 0, sizeof(reset_context));
2284 reset_context.method = AMD_RESET_METHOD_NONE;
2285 reset_context.reset_req_dev = adev;
2286 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2287 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2288 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2289 }
2290 }
2291
c6385e50 2292 amdgpu_driver_unload_kms(dev);
72c8c97b 2293
98c6e6a7
AG		 2294 /*
2295 * Flush any in flight DMA operations from device.
2296 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2297 * StatusTransactions Pending bit.
2298 */
fd4495e5 2299 pci_disable_device(pdev);
98c6e6a7 2300 pci_wait_for_pending_transaction(pdev);
d38ceaf9
AD		 2301}
2302
61e11306
AD		 2303static void
2304amdgpu_pci_shutdown(struct pci_dev *pdev)
2305{
faefba95 2306 struct drm_device *dev = pci_get_drvdata(pdev);
1348969a 2307 struct amdgpu_device *adev = drm_to_adev(dev);
faefba95 2308
7c6e68c7
AG		 2309 if (amdgpu_ras_intr_triggered())
2310 return;
2311
61e11306 2312 /* if we are running in a VM, make sure the device
00ea8cba
AD		 2313 * torn down properly on reboot/shutdown.
2314 * unfortunately we can't detect certain
2315 * hypervisors so just do this all the time.
61e11306 2316 */
05cac1ae
ND		 2317 if (!amdgpu_passthrough(adev))
2318 adev->mp1_state = PP_MP1_STATE_UNLOAD;
cdd61df6 2319 amdgpu_device_ip_suspend(adev);
a3a09142 2320 adev->mp1_state = PP_MP1_STATE_NONE;
61e11306
AD		 2321}
2322
e3c1b071 2323/**
2324 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2325 *
2326 * @work: work_struct.
2327 */
2328static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2329{
2330 struct list_head device_list;
2331 struct amdgpu_device *adev;
2332 int i, r;
04442bf7
LL		 2333 struct amdgpu_reset_context reset_context;
2334
2335 memset(&reset_context, 0, sizeof(reset_context));
e3c1b071 2336
2337 mutex_lock(&mgpu_info.mutex);
2338 if (mgpu_info.pending_reset == true) {
2339 mutex_unlock(&mgpu_info.mutex);
2340 return;
2341 }
2342 mgpu_info.pending_reset = true;
2343 mutex_unlock(&mgpu_info.mutex);
2344
04442bf7
LL		 2345 /* Use a common context, just need to make sure full reset is done */
2346 reset_context.method = AMD_RESET_METHOD_NONE;
2347 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2348
e3c1b071 2349 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2350 adev = mgpu_info.gpu_ins[i].adev;
04442bf7
LL		 2351 reset_context.reset_req_dev = adev;
2352 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
e3c1b071 2353 if (r) {
2354 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2355 r, adev_to_drm(adev)->unique);
2356 }
2357 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2358 r = -EALREADY;
2359 }
2360 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2361 adev = mgpu_info.gpu_ins[i].adev;
e3c1b071 2362 flush_work(&adev->xgmi_reset_work);
050743da 2363 adev->gmc.xgmi.pending_reset = false;
e3c1b071 2364 }
2365
2366 /* reset function will rebuild the xgmi hive info , clear it now */
2367 for (i = 0; i < mgpu_info.num_dgpu; i++)
2368 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2369
2370 INIT_LIST_HEAD(&device_list);
2371
2372 for (i = 0; i < mgpu_info.num_dgpu; i++)
2373 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2374
2375 /* unregister the GPU first, reset function will add them back */
2376 list_for_each_entry(adev, &device_list, reset_list)
2377 amdgpu_unregister_gpu_instance(adev);
2378
04442bf7
LL		 2379 /* Use a common context, just need to make sure full reset is done */
2380 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2381 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2382
e3c1b071 2383 if (r) {
2384 DRM_ERROR("reinit gpus failure");
2385 return;
2386 }
2387 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2388 adev = mgpu_info.gpu_ins[i].adev;
2389 if (!adev->kfd.init_complete)
2390 amdgpu_amdkfd_device_init(adev);
2391 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2392 }
2393 return;
2394}
2395
e25443d2
AD		 2396static int amdgpu_pmops_prepare(struct device *dev)
2397{
2398 struct drm_device *drm_dev = dev_get_drvdata(dev);
d2a197a4 2399 struct amdgpu_device *adev = drm_to_adev(drm_dev);
e25443d2
AD		 2400
2401 /* Return a positive number here so
2402 * DPM_FLAG_SMART_SUSPEND works properly
2403 */
b98c6299 2404 if (amdgpu_device_supports_boco(drm_dev))
9308a49d 2405 return pm_runtime_suspended(dev);
e25443d2 2406
d2a197a4
ML		 2407 /* if we will not support s3 or s2i for the device
2408 * then skip suspend
2409 */
2410 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2411 !amdgpu_acpi_is_s3_active(adev))
2412 return 1;
e25443d2
AD		 2413
2414 return 0;
2415}
2416
2417static void amdgpu_pmops_complete(struct device *dev)
2418{
2419 /* nothing to do */
2420}
2421
d38ceaf9
AD		 2422static int amdgpu_pmops_suspend(struct device *dev)
2423{
911d8b30 2424 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733 2425 struct amdgpu_device *adev = drm_to_adev(drm_dev);
74b0b157 2426
d0260f62 2427 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2428 adev->in_s0ix = true;
ca475186 2429 else if (amdgpu_acpi_is_s3_active(adev))
eac4c54b 2430 adev->in_s3 = true;
ca475186
ML		 2431 if (!adev->in_s0ix && !adev->in_s3)
2432 return 0;
9e051720
KHF		 2433 return amdgpu_device_suspend(drm_dev, true);
2434}
2435
2436static int amdgpu_pmops_suspend_noirq(struct device *dev)
2437{
2438 struct drm_device *drm_dev = dev_get_drvdata(dev);
2439 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2440
0223e516 2441 if (amdgpu_acpi_should_gpu_reset(adev))
9e051720
KHF		 2442 return amdgpu_asic_reset(adev);
2443
2444 return 0;
d38ceaf9
AD		 2445}
2446
2447static int amdgpu_pmops_resume(struct device *dev)
2448{
911d8b30 2449 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2450 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2451 int r;
85e154c2 2452
ca475186
ML		 2453 if (!adev->in_s0ix && !adev->in_s3)
2454 return 0;
2455
ebe86a57
AG		 2456 /* Avoids registers access if device is physically gone */
2457 if (!pci_device_is_present(adev->pdev))
2458 adev->no_hw_access = true;
2459
62498733 2460 r = amdgpu_device_resume(drm_dev, true);
d0260f62 2461 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2462 adev->in_s0ix = false;
eac4c54b
ML		 2463 else
2464 adev->in_s3 = false;
62498733 2465 return r;
d38ceaf9
AD		 2466}
2467
2468static int amdgpu_pmops_freeze(struct device *dev)
2469{
911d8b30 2470 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2471 struct amdgpu_device *adev = drm_to_adev(drm_dev);
897483d8 2472 int r;
74b0b157 2473
62498733 2474 adev->in_s4 = true;
de185019 2475 r = amdgpu_device_suspend(drm_dev, true);
62498733 2476 adev->in_s4 = false;
897483d8
AD		 2477 if (r)
2478 return r;
af1f2985
TH		 2479
2480 if (amdgpu_acpi_should_gpu_reset(adev))
2481 return amdgpu_asic_reset(adev);
2482 return 0;
d38ceaf9
AD		 2483}
2484
2485static int amdgpu_pmops_thaw(struct device *dev)
2486{
911d8b30 2487 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2488
de185019 2489 return amdgpu_device_resume(drm_dev, true);
74b0b157 2490}
2491
2492static int amdgpu_pmops_poweroff(struct device *dev)
2493{
911d8b30 2494 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2495
62498733 2496 return amdgpu_device_suspend(drm_dev, true);
74b0b157 2497}
2498
2499static int amdgpu_pmops_restore(struct device *dev)
2500{
911d8b30 2501 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2502
de185019 2503 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 2504}
2505
4020c228
AD		 2506static int amdgpu_runtime_idle_check_display(struct device *dev)
2507{
2508 struct pci_dev *pdev = to_pci_dev(dev);
2509 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2510 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2511
2512 if (adev->mode_info.num_crtc) {
2513 struct drm_connector *list_connector;
2514 struct drm_connector_list_iter iter;
2515 int ret = 0;
2516
2517 /* XXX: Return busy if any displays are connected to avoid
2518 * possible display wakeups after runtime resume due to
2519 * hotplug events in case any displays were connected while
2520 * the GPU was in suspend. Remove this once that is fixed.
2521 */
2522 mutex_lock(&drm_dev->mode_config.mutex);
2523 drm_connector_list_iter_begin(drm_dev, &iter);
2524 drm_for_each_connector_iter(list_connector, &iter) {
2525 if (list_connector->status == connector_status_connected) {
2526 ret = -EBUSY;
2527 break;
2528 }
2529 }
2530 drm_connector_list_iter_end(&iter);
2531 mutex_unlock(&drm_dev->mode_config.mutex);
2532
2533 if (ret)
2534 return ret;
2535
d09ef243 2536 if (adev->dc_enabled) {
4020c228
AD		 2537 struct drm_crtc *crtc;
2538
2539 drm_for_each_crtc(crtc, drm_dev) {
2540 drm_modeset_lock(&crtc->mutex, NULL);
2541 if (crtc->state->active)
2542 ret = -EBUSY;
2543 drm_modeset_unlock(&crtc->mutex);
2544 if (ret < 0)
2545 break;
2546 }
2547 } else {
2548 mutex_lock(&drm_dev->mode_config.mutex);
2549 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2550
2551 drm_connector_list_iter_begin(drm_dev, &iter);
2552 drm_for_each_connector_iter(list_connector, &iter) {
2553 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2554 ret = -EBUSY;
2555 break;
2556 }
2557 }
2558
2559 drm_connector_list_iter_end(&iter);
2560
2561 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2562 mutex_unlock(&drm_dev->mode_config.mutex);
2563 }
2564 if (ret)
2565 return ret;
2566 }
2567
2568 return 0;
2569}
2570
d38ceaf9
AD		 2571static int amdgpu_pmops_runtime_suspend(struct device *dev)
2572{
2573 struct pci_dev *pdev = to_pci_dev(dev);
2574 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2575 struct amdgpu_device *adev = drm_to_adev(drm_dev);
719423f6 2576 int ret, i;
d38ceaf9 2577
9c913f38 2578 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
d38ceaf9
AD		 2579 pm_runtime_forbid(dev);
2580 return -EBUSY;
2581 }
2582
4020c228
AD		 2583 ret = amdgpu_runtime_idle_check_display(dev);
2584 if (ret)
2585 return ret;
2586
719423f6
AD		 2587 /* wait for all rings to drain before suspending */
2588 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2589 struct amdgpu_ring *ring = adev->rings[i];
2590 if (ring && ring->sched.ready) {
2591 ret = amdgpu_fence_wait_empty(ring);
2592 if (ret)
2593 return -EBUSY;
2594 }
2595 }
2596
f0f7ddfc 2597 adev->in_runpm = true;
b98c6299 2598 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2599 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
d38ceaf9 2600
7be3be2b
EQ		 2601 /*
2602 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2603 * proper cleanups and put itself into a state ready for PNP. That
2604 * can address some random resuming failure observed on BOCO capable
2605 * platforms.
2606 * TODO: this may be also needed for PX capable platform.
2607 */
2608 if (amdgpu_device_supports_boco(drm_dev))
2609 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2610
de185019 2611 ret = amdgpu_device_suspend(drm_dev, false);
cef8b03b
AD		 2612 if (ret) {
2613 adev->in_runpm = false;
7be3be2b
EQ		 2614 if (amdgpu_device_supports_boco(drm_dev))
2615 adev->mp1_state = PP_MP1_STATE_NONE;
70bedd68 2616 return ret;
cef8b03b 2617 }
70bedd68 2618
7be3be2b
EQ		 2619 if (amdgpu_device_supports_boco(drm_dev))
2620 adev->mp1_state = PP_MP1_STATE_NONE;
2621
b98c6299 2622 if (amdgpu_device_supports_px(drm_dev)) {
562b49fc
AD		 2623 /* Only need to handle PCI state in the driver for ATPX
2624 * PCI core handles it for _PR3.
2625 */
b98c6299
AD		 2626 amdgpu_device_cache_pci_state(pdev);
2627 pci_disable_device(pdev);
2628 pci_ignore_hotplug(pdev);
2629 pci_set_power_state(pdev, PCI_D3cold);
b97e9d47 2630 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
11e612a0
AD		 2631 } else if (amdgpu_device_supports_boco(drm_dev)) {
2632 /* nothing to do */
19134317
AD		 2633 } else if (amdgpu_device_supports_baco(drm_dev)) {
2634 amdgpu_device_baco_enter(drm_dev);
b97e9d47 2635 }
d38ceaf9 2636
abcb2ace 2637 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
f4b09c29 2638
d38ceaf9
AD		 2639 return 0;
2640}
2641
2642static int amdgpu_pmops_runtime_resume(struct device *dev)
2643{
2644 struct pci_dev *pdev = to_pci_dev(dev);
2645 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2646 struct amdgpu_device *adev = drm_to_adev(drm_dev);
d38ceaf9
AD		 2647 int ret;
2648
9c913f38 2649 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
d38ceaf9
AD		 2650 return -EINVAL;
2651
e1543d83
AG		 2652 /* Avoids registers access if device is physically gone */
2653 if (!pci_device_is_present(adev->pdev))
2654 adev->no_hw_access = true;
2655
b98c6299 2656 if (amdgpu_device_supports_px(drm_dev)) {
b97e9d47
AD		 2657 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2658
562b49fc
AD		 2659 /* Only need to handle PCI state in the driver for ATPX
2660 * PCI core handles it for _PR3.
2661 */
b98c6299
AD		 2662 pci_set_power_state(pdev, PCI_D0);
2663 amdgpu_device_load_pci_state(pdev);
2664 ret = pci_enable_device(pdev);
2665 if (ret)
2666 return ret;
637bb036 2667 pci_set_master(pdev);
fd496ca8
AD		 2668 } else if (amdgpu_device_supports_boco(drm_dev)) {
2669 /* Only need to handle PCI state in the driver for ATPX
2670 * PCI core handles it for _PR3.
2671 */
2672 pci_set_master(pdev);
19134317
AD		 2673 } else if (amdgpu_device_supports_baco(drm_dev)) {
2674 amdgpu_device_baco_exit(drm_dev);
b97e9d47 2675 }
de185019 2676 ret = amdgpu_device_resume(drm_dev, false);
6b11af6d
YY		 2677 if (ret) {
2678 if (amdgpu_device_supports_px(drm_dev))
2679 pci_disable_device(pdev);
b45aeb2d 2680 return ret;
6b11af6d 2681 }
b45aeb2d 2682
b98c6299 2683 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2684 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
f0f7ddfc 2685 adev->in_runpm = false;
d38ceaf9
AD		 2686 return 0;
2687}
2688
2689static int amdgpu_pmops_runtime_idle(struct device *dev)
2690{
911d8b30 2691 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2692 struct amdgpu_device *adev = drm_to_adev(drm_dev);
97f6a21b
AG		 2693 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2694 int ret = 1;
d38ceaf9 2695
9c913f38 2696 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
d38ceaf9
AD		 2697 pm_runtime_forbid(dev);
2698 return -EBUSY;
2699 }
2700
4020c228 2701 ret = amdgpu_runtime_idle_check_display(dev);
97f6a21b 2702
d38ceaf9
AD		 2703 pm_runtime_mark_last_busy(dev);
2704 pm_runtime_autosuspend(dev);
97f6a21b 2705 return ret;
d38ceaf9
AD		 2706}
2707
2708long amdgpu_drm_ioctl(struct file *filp,
2709 unsigned int cmd, unsigned long arg)
2710{
2711 struct drm_file *file_priv = filp->private_data;
2712 struct drm_device *dev;
2713 long ret;
2714 dev = file_priv->minor->dev;
2715 ret = pm_runtime_get_sync(dev->dev);
2716 if (ret < 0)
5509ac65 2717 goto out;
d38ceaf9
AD		 2718
2719 ret = drm_ioctl(filp, cmd, arg);
2720
2721 pm_runtime_mark_last_busy(dev->dev);
5509ac65 2722out:
d38ceaf9
AD		 2723 pm_runtime_put_autosuspend(dev->dev);
2724 return ret;
2725}
2726
2727static const struct dev_pm_ops amdgpu_pm_ops = {
e25443d2
AD		 2728 .prepare = amdgpu_pmops_prepare,
2729 .complete = amdgpu_pmops_complete,
d38ceaf9 2730 .suspend = amdgpu_pmops_suspend,
9e051720 2731 .suspend_noirq = amdgpu_pmops_suspend_noirq,
d38ceaf9
AD		 2732 .resume = amdgpu_pmops_resume,
2733 .freeze = amdgpu_pmops_freeze,
2734 .thaw = amdgpu_pmops_thaw,
74b0b157 2735 .poweroff = amdgpu_pmops_poweroff,
2736 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 2737 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2738 .runtime_resume = amdgpu_pmops_runtime_resume,
2739 .runtime_idle = amdgpu_pmops_runtime_idle,
2740};
2741
48ad368a
AG		 2742static int amdgpu_flush(struct file *f, fl_owner_t id)
2743{
2744 struct drm_file *file_priv = f->private_data;
2745 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
56753e73 2746 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
48ad368a 2747
56753e73
CK		 2748 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2749 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
48ad368a 2750
56753e73 2751 return timeout >= 0 ? 0 : timeout;
48ad368a
AG		 2752}
2753
d38ceaf9
AD		 2754static const struct file_operations amdgpu_driver_kms_fops = {
2755 .owner = THIS_MODULE,
2756 .open = drm_open,
48ad368a 2757 .flush = amdgpu_flush,
d38ceaf9
AD		 2758 .release = drm_release,
2759 .unlocked_ioctl = amdgpu_drm_ioctl,
71df0368 2760 .mmap = drm_gem_mmap,
d38ceaf9
AD		 2761 .poll = drm_poll,
2762 .read = drm_read,
2763#ifdef CONFIG_COMPAT
2764 .compat_ioctl = amdgpu_kms_compat_ioctl,
2765#endif
87444254
RS		 2766#ifdef CONFIG_PROC_FS
2767 .show_fdinfo = amdgpu_show_fdinfo
2768#endif
d38ceaf9
AD		 2769};
2770
021830d2
BN		 2771int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2772{
f3729f7b 2773 struct drm_file *file;
021830d2
BN		 2774
2775 if (!filp)
2776 return -EINVAL;
2777
2778 if (filp->f_op != &amdgpu_driver_kms_fops) {
2779 return -EINVAL;
2780 }
2781
2782 file = filp->private_data;
2783 *fpriv = file->driver_priv;
2784 return 0;
2785}
2786
5088d657
LT		 2787const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2788 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2789 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2790 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2791 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2792 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2793 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2794 /* KMS */
2795 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2796 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2797 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2798 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2799 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2800 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2801 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2802 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2803 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2804 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2805};
2806
2807static const struct drm_driver amdgpu_kms_driver = {
d38ceaf9 2808 .driver_features =
f3ed6739 2809 DRIVER_ATOMIC |
1ff49481 2810 DRIVER_GEM |
db4ff423
CZ		 2811 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2812 DRIVER_SYNCOBJ_TIMELINE,
d38ceaf9 2813 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 2814 .postclose = amdgpu_driver_postclose_kms,
2815 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9 2816 .ioctls = amdgpu_ioctls_kms,
5088d657 2817 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
d38ceaf9
AD		 2818 .dumb_create = amdgpu_mode_dumb_create,
2819 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9 2820 .fops = &amdgpu_driver_kms_fops,
72c8c97b 2821 .release = &amdgpu_driver_release_kms,
d38ceaf9
AD		 2822
2823 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2824 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
09052fc3 2825 .gem_prime_import = amdgpu_gem_prime_import,
71df0368 2826 .gem_prime_mmap = drm_gem_prime_mmap,
d38ceaf9
AD		 2827
2828 .name = DRIVER_NAME,
2829 .desc = DRIVER_DESC,
2830 .date = DRIVER_DATE,
2831 .major = KMS_DRIVER_MAJOR,
2832 .minor = KMS_DRIVER_MINOR,
2833 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2834};
2835
c9a6b82f
AG		 2836static struct pci_error_handlers amdgpu_pci_err_handler = {
2837 .error_detected = amdgpu_pci_error_detected,
2838 .mmio_enabled = amdgpu_pci_mmio_enabled,
2839 .slot_reset = amdgpu_pci_slot_reset,
2840 .resume = amdgpu_pci_resume,
2841};
2842
35bba831
AG		 2843extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2844extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2845extern const struct attribute_group amdgpu_vbios_version_attr_group;
2846
2847static const struct attribute_group *amdgpu_sysfs_groups[] = {
2848 &amdgpu_vram_mgr_attr_group,
2849 &amdgpu_gtt_mgr_attr_group,
2850 &amdgpu_vbios_version_attr_group,
2851 NULL,
2852};
2853
2854
d38ceaf9
AD		 2855static struct pci_driver amdgpu_kms_pci_driver = {
2856 .name = DRIVER_NAME,
2857 .id_table = pciidlist,
2858 .probe = amdgpu_pci_probe,
2859 .remove = amdgpu_pci_remove,
61e11306 2860 .shutdown = amdgpu_pci_shutdown,
d38ceaf9 2861 .driver.pm = &amdgpu_pm_ops,
c9a6b82f 2862 .err_handler = &amdgpu_pci_err_handler,
35bba831 2863 .dev_groups = amdgpu_sysfs_groups,
d38ceaf9
AD		 2864};
2865
2866static int __init amdgpu_init(void)
2867{
245ae5e9
CK		 2868 int r;
2869
6a2d2ddf 2870 if (drm_firmware_drivers_only())
c60e22f7 2871 return -EINVAL;
c60e22f7 2872
245ae5e9
CK		 2873 r = amdgpu_sync_init();
2874 if (r)
2875 goto error_sync;
2876
2877 r = amdgpu_fence_slab_init();
2878 if (r)
2879 goto error_fence;
2880
d38ceaf9 2881 DRM_INFO("amdgpu kernel modesetting enabled.\n");
d38ceaf9 2882 amdgpu_register_atpx_handler();
f9b7f370 2883 amdgpu_acpi_detect();
03a1c08d
FK		 2884
2885 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2886 amdgpu_amdkfd_init();
2887
d38ceaf9 2888 /* let modprobe override vga console setting */
448d1051 2889 return pci_register_driver(&amdgpu_kms_pci_driver);
245ae5e9 2890
245ae5e9
CK		 2891error_fence:
2892 amdgpu_sync_fini();
2893
2894error_sync:
2895 return r;
d38ceaf9
AD		 2896}
2897
2898static void __exit amdgpu_exit(void)
2899{
130e0371 2900 amdgpu_amdkfd_fini();
448d1051 2901 pci_unregister_driver(&amdgpu_kms_pci_driver);
d38ceaf9 2902 amdgpu_unregister_atpx_handler();
4d5275ab 2903 amdgpu_acpi_release();
257bf15a 2904 amdgpu_sync_fini();
d573de2d 2905 amdgpu_fence_slab_fini();
c7d8b782 2906 mmu_notifier_synchronize();
d38ceaf9
AD		 2907}
2908
2909module_init(amdgpu_init);
2910module_exit(amdgpu_exit);
2911
2912MODULE_AUTHOR(DRIVER_AUTHOR);
2913MODULE_DESCRIPTION(DRIVER_DESC);
2914MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)