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drm/amdgpu: add virtual dce support for iceland
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
d347ce66 55 * - 3.3.0 - Add VM support for UVD on supported hardware.
d38ceaf9
AD		 56 */
57#define KMS_DRIVER_MAJOR 3
d347ce66 58#define KMS_DRIVER_MINOR 3
d38ceaf9
AD		 59#define KMS_DRIVER_PATCHLEVEL 0
60
61int amdgpu_vram_limit = 0;
62int amdgpu_gart_size = -1; /* auto */
63int amdgpu_benchmarking = 0;
64int amdgpu_testing = 0;
65int amdgpu_audio = -1;
66int amdgpu_disp_priority = 0;
67int amdgpu_hw_i2c = 0;
68int amdgpu_pcie_gen2 = -1;
69int amdgpu_msi = -1;
a895c222 70int amdgpu_lockup_timeout = 0;
d38ceaf9
AD		 71int amdgpu_dpm = -1;
72int amdgpu_smc_load_fw = 1;
73int amdgpu_aspm = -1;
74int amdgpu_runtime_pm = -1;
d38ceaf9
AD		 75unsigned amdgpu_ip_block_mask = 0xffffffff;
76int amdgpu_bapm = -1;
77int amdgpu_deep_color = 0;
ed885b21 78int amdgpu_vm_size = 64;
d38ceaf9 79int amdgpu_vm_block_size = -1;
d9c13156 80int amdgpu_vm_fault_stop = 0;
b495bd3a 81int amdgpu_vm_debug = 0;
d38ceaf9 82int amdgpu_exp_hw_support = 0;
b70f014d 83int amdgpu_sched_jobs = 32;
4afcb303 84int amdgpu_sched_hw_submission = 2;
e61710c5 85int amdgpu_powerplay = -1;
6bb6b297 86int amdgpu_powercontainment = 1;
af223dfa 87int amdgpu_sclk_deep_sleep_en = 1;
cd474ba0
AD		 88unsigned amdgpu_pcie_gen_cap = 0;
89unsigned amdgpu_pcie_lane_cap = 0;
395d1fb9
NH		 90unsigned amdgpu_cg_mask = 0xffffffff;
91unsigned amdgpu_pg_mask = 0xffffffff;
6f8941a2 92char *amdgpu_disable_cu = NULL;
e443059d 93int amdgpu_virtual_display = 0;
d38ceaf9
AD		 94
95MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
96module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
97
98MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
99module_param_named(gartsize, amdgpu_gart_size, int, 0600);
100
101MODULE_PARM_DESC(benchmark, "Run benchmark");
102module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
103
104MODULE_PARM_DESC(test, "Run tests");
105module_param_named(test, amdgpu_testing, int, 0444);
106
107MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
108module_param_named(audio, amdgpu_audio, int, 0444);
109
110MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
111module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
112
113MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
114module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
115
116MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
117module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
118
119MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
120module_param_named(msi, amdgpu_msi, int, 0444);
121
a895c222 122MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 123module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
124
125MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
126module_param_named(dpm, amdgpu_dpm, int, 0444);
127
128MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
129module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
130
131MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
132module_param_named(aspm, amdgpu_aspm, int, 0444);
133
134MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
135module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
136
d38ceaf9
AD		 137MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
138module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
139
140MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
141module_param_named(bapm, amdgpu_bapm, int, 0444);
142
143MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
144module_param_named(deep_color, amdgpu_deep_color, int, 0444);
145
ed885b21 146MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9
AD		 147module_param_named(vm_size, amdgpu_vm_size, int, 0444);
148
149MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
150module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
151
d9c13156
CK		 152MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
153module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
154
b495bd3a
CK		 155MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
156module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
157
d38ceaf9
AD		 158MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
159module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
160
b70f014d 161MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 162module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
163
4afcb303
JZ		 164MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
165module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
166
3a74f6f2 167#ifdef CONFIG_DRM_AMD_POWERPLAY
e61710c5 168MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
3a74f6f2 169module_param_named(powerplay, amdgpu_powerplay, int, 0444);
6bb6b297
HR		 170
171MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)");
172module_param_named(powercontainment, amdgpu_powercontainment, int, 0444);
3a74f6f2
JZ		 173#endif
174
af223dfa
RZ		 175MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)");
176module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444);
177
cd474ba0
AD		 178MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
179module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
180
181MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
182module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
183
395d1fb9
NH		 184MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
185module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
186
187MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
188module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
189
6f8941a2
NH		 190MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
191module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
192
e443059d
ED		 193MODULE_PARM_DESC(virtual_display, "enable virtual display (0 = disable virtual display)");
194module_param_named(virtual_display, amdgpu_virtual_display, int, 0444);
195
f498d9ed 196static const struct pci_device_id pciidlist[] = {
89330c39
AD		 197#ifdef CONFIG_DRM_AMDGPU_CIK
198 /* Kaveri */
2f7d10b3
JZ		 199 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
200 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
201 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
202 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
203 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
204 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
205 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
206 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
207 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
208 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
209 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
210 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
211 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
212 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
213 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
214 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
215 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
216 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
217 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
218 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
219 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
220 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 221 /* Bonaire */
2f7d10b3
JZ		 222 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
223 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
224 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
225 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 226 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
227 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
228 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
229 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
230 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
231 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 232 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 233 /* Hawaii */
234 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
235 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
236 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
237 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
238 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
239 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
240 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
241 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
242 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
243 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
244 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
245 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
246 /* Kabini */
2f7d10b3
JZ		 247 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
248 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
249 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
250 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
251 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
252 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
253 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
254 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
255 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
256 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
257 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
258 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
259 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
260 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
261 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
262 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 263 /* mullins */
2f7d10b3
JZ		 264 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
265 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
266 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
267 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
268 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
269 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
270 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
271 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
272 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
273 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
274 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
275 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
276 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
277 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
278 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
279 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 280#endif
1256a8b8 281 /* topaz */
dba280b2
AD		 282 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
283 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
284 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
285 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
286 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 287 /* tonga */
288 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
289 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
290 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 291 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 292 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
293 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 294 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 295 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
296 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 297 /* fiji */
298 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 299 /* carrizo */
2f7d10b3
JZ		 300 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
301 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
302 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
303 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
304 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 305 /* stoney */
306 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 307 /* Polaris11 */
308 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 309 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 310 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 311 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 312 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 313 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 314 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
315 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
316 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 317 /* Polaris10 */
318 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 319 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
320 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
321 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
322 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 323 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 324 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
325 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
326 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
327 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
328 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
d38ceaf9
AD		 329
330 {0, 0, 0}
331};
332
333MODULE_DEVICE_TABLE(pci, pciidlist);
334
335static struct drm_driver kms_driver;
336
337static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
338{
339 struct apertures_struct *ap;
340 bool primary = false;
341
342 ap = alloc_apertures(1);
343 if (!ap)
344 return -ENOMEM;
345
346 ap->ranges[0].base = pci_resource_start(pdev, 0);
347 ap->ranges[0].size = pci_resource_len(pdev, 0);
348
349#ifdef CONFIG_X86
350 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
351#endif
352 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
353 kfree(ap);
354
355 return 0;
356}
357
358static int amdgpu_pci_probe(struct pci_dev *pdev,
359 const struct pci_device_id *ent)
360{
361 unsigned long flags = ent->driver_data;
362 int ret;
363
2f7d10b3 364 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 365 DRM_INFO("This hardware requires experimental hardware support.\n"
366 "See modparam exp_hw_support\n");
367 return -ENODEV;
368 }
369
efb1c658
OG		 370 /*
371 * Initialize amdkfd before starting radeon. If it was not loaded yet,
372 * defer radeon probing
373 */
374 ret = amdgpu_amdkfd_init();
375 if (ret == -EPROBE_DEFER)
376 return ret;
377
d38ceaf9
AD		 378 /* Get rid of things like offb */
379 ret = amdgpu_kick_out_firmware_fb(pdev);
380 if (ret)
381 return ret;
382
383 return drm_get_pci_dev(pdev, ent, &kms_driver);
384}
385
386static void
387amdgpu_pci_remove(struct pci_dev *pdev)
388{
389 struct drm_device *dev = pci_get_drvdata(pdev);
390
391 drm_put_dev(dev);
392}
393
394static int amdgpu_pmops_suspend(struct device *dev)
395{
396 struct pci_dev *pdev = to_pci_dev(dev);
397 struct drm_device *drm_dev = pci_get_drvdata(pdev);
398 return amdgpu_suspend_kms(drm_dev, true, true);
399}
400
401static int amdgpu_pmops_resume(struct device *dev)
402{
403 struct pci_dev *pdev = to_pci_dev(dev);
404 struct drm_device *drm_dev = pci_get_drvdata(pdev);
405 return amdgpu_resume_kms(drm_dev, true, true);
406}
407
408static int amdgpu_pmops_freeze(struct device *dev)
409{
410 struct pci_dev *pdev = to_pci_dev(dev);
411 struct drm_device *drm_dev = pci_get_drvdata(pdev);
412 return amdgpu_suspend_kms(drm_dev, false, true);
413}
414
415static int amdgpu_pmops_thaw(struct device *dev)
416{
417 struct pci_dev *pdev = to_pci_dev(dev);
418 struct drm_device *drm_dev = pci_get_drvdata(pdev);
419 return amdgpu_resume_kms(drm_dev, false, true);
420}
421
422static int amdgpu_pmops_runtime_suspend(struct device *dev)
423{
424 struct pci_dev *pdev = to_pci_dev(dev);
425 struct drm_device *drm_dev = pci_get_drvdata(pdev);
426 int ret;
427
428 if (!amdgpu_device_is_px(drm_dev)) {
429 pm_runtime_forbid(dev);
430 return -EBUSY;
431 }
432
433 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
434 drm_kms_helper_poll_disable(drm_dev);
435 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
436
437 ret = amdgpu_suspend_kms(drm_dev, false, false);
438 pci_save_state(pdev);
439 pci_disable_device(pdev);
440 pci_ignore_hotplug(pdev);
11670975
AD		 441 if (amdgpu_is_atpx_hybrid())
442 pci_set_power_state(pdev, PCI_D3cold);
522761cb 443 else if (!amdgpu_has_atpx_dgpu_power_cntl())
7e32aa61 444 pci_set_power_state(pdev, PCI_D3hot);
d38ceaf9
AD		 445 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
446
447 return 0;
448}
449
450static int amdgpu_pmops_runtime_resume(struct device *dev)
451{
452 struct pci_dev *pdev = to_pci_dev(dev);
453 struct drm_device *drm_dev = pci_get_drvdata(pdev);
454 int ret;
455
456 if (!amdgpu_device_is_px(drm_dev))
457 return -EINVAL;
458
459 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
460
522761cb
AD		 461 if (amdgpu_is_atpx_hybrid() ||
462 !amdgpu_has_atpx_dgpu_power_cntl())
463 pci_set_power_state(pdev, PCI_D0);
d38ceaf9
AD		 464 pci_restore_state(pdev);
465 ret = pci_enable_device(pdev);
466 if (ret)
467 return ret;
468 pci_set_master(pdev);
469
470 ret = amdgpu_resume_kms(drm_dev, false, false);
471 drm_kms_helper_poll_enable(drm_dev);
472 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
473 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
474 return 0;
475}
476
477static int amdgpu_pmops_runtime_idle(struct device *dev)
478{
479 struct pci_dev *pdev = to_pci_dev(dev);
480 struct drm_device *drm_dev = pci_get_drvdata(pdev);
481 struct drm_crtc *crtc;
482
483 if (!amdgpu_device_is_px(drm_dev)) {
484 pm_runtime_forbid(dev);
485 return -EBUSY;
486 }
487
488 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
489 if (crtc->enabled) {
490 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
491 return -EBUSY;
492 }
493 }
494
495 pm_runtime_mark_last_busy(dev);
496 pm_runtime_autosuspend(dev);
497 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
498 return 1;
499}
500
501long amdgpu_drm_ioctl(struct file *filp,
502 unsigned int cmd, unsigned long arg)
503{
504 struct drm_file *file_priv = filp->private_data;
505 struct drm_device *dev;
506 long ret;
507 dev = file_priv->minor->dev;
508 ret = pm_runtime_get_sync(dev->dev);
509 if (ret < 0)
510 return ret;
511
512 ret = drm_ioctl(filp, cmd, arg);
513
514 pm_runtime_mark_last_busy(dev->dev);
515 pm_runtime_put_autosuspend(dev->dev);
516 return ret;
517}
518
519static const struct dev_pm_ops amdgpu_pm_ops = {
520 .suspend = amdgpu_pmops_suspend,
521 .resume = amdgpu_pmops_resume,
522 .freeze = amdgpu_pmops_freeze,
523 .thaw = amdgpu_pmops_thaw,
524 .poweroff = amdgpu_pmops_freeze,
525 .restore = amdgpu_pmops_resume,
526 .runtime_suspend = amdgpu_pmops_runtime_suspend,
527 .runtime_resume = amdgpu_pmops_runtime_resume,
528 .runtime_idle = amdgpu_pmops_runtime_idle,
529};
530
531static const struct file_operations amdgpu_driver_kms_fops = {
532 .owner = THIS_MODULE,
533 .open = drm_open,
534 .release = drm_release,
535 .unlocked_ioctl = amdgpu_drm_ioctl,
536 .mmap = amdgpu_mmap,
537 .poll = drm_poll,
538 .read = drm_read,
539#ifdef CONFIG_COMPAT
540 .compat_ioctl = amdgpu_kms_compat_ioctl,
541#endif
542};
543
544static struct drm_driver kms_driver = {
545 .driver_features =
546 DRIVER_USE_AGP |
547 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
7056bb5c 548 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET,
d38ceaf9
AD		 549 .dev_priv_size = 0,
550 .load = amdgpu_driver_load_kms,
551 .open = amdgpu_driver_open_kms,
552 .preclose = amdgpu_driver_preclose_kms,
553 .postclose = amdgpu_driver_postclose_kms,
554 .lastclose = amdgpu_driver_lastclose_kms,
555 .set_busid = drm_pci_set_busid,
556 .unload = amdgpu_driver_unload_kms,
557 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
558 .enable_vblank = amdgpu_enable_vblank_kms,
559 .disable_vblank = amdgpu_disable_vblank_kms,
560 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
561 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
562#if defined(CONFIG_DEBUG_FS)
563 .debugfs_init = amdgpu_debugfs_init,
564 .debugfs_cleanup = amdgpu_debugfs_cleanup,
565#endif
566 .irq_preinstall = amdgpu_irq_preinstall,
567 .irq_postinstall = amdgpu_irq_postinstall,
568 .irq_uninstall = amdgpu_irq_uninstall,
569 .irq_handler = amdgpu_irq_handler,
570 .ioctls = amdgpu_ioctls_kms,
e7294dee 571 .gem_free_object_unlocked = amdgpu_gem_object_free,
d38ceaf9
AD		 572 .gem_open_object = amdgpu_gem_object_open,
573 .gem_close_object = amdgpu_gem_object_close,
574 .dumb_create = amdgpu_mode_dumb_create,
575 .dumb_map_offset = amdgpu_mode_dumb_mmap,
576 .dumb_destroy = drm_gem_dumb_destroy,
577 .fops = &amdgpu_driver_kms_fops,
578
579 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
580 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
581 .gem_prime_export = amdgpu_gem_prime_export,
582 .gem_prime_import = drm_gem_prime_import,
583 .gem_prime_pin = amdgpu_gem_prime_pin,
584 .gem_prime_unpin = amdgpu_gem_prime_unpin,
585 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
586 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
587 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
588 .gem_prime_vmap = amdgpu_gem_prime_vmap,
589 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
590
591 .name = DRIVER_NAME,
592 .desc = DRIVER_DESC,
593 .date = DRIVER_DATE,
594 .major = KMS_DRIVER_MAJOR,
595 .minor = KMS_DRIVER_MINOR,
596 .patchlevel = KMS_DRIVER_PATCHLEVEL,
597};
598
599static struct drm_driver *driver;
600static struct pci_driver *pdriver;
601
602static struct pci_driver amdgpu_kms_pci_driver = {
603 .name = DRIVER_NAME,
604 .id_table = pciidlist,
605 .probe = amdgpu_pci_probe,
606 .remove = amdgpu_pci_remove,
607 .driver.pm = &amdgpu_pm_ops,
608};
609
d573de2d
RZ		 610
611
d38ceaf9
AD		 612static int __init amdgpu_init(void)
613{
257bf15a 614 amdgpu_sync_init();
d573de2d 615 amdgpu_fence_slab_init();
d38ceaf9
AD		 616 if (vgacon_text_force()) {
617 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
618 return -EINVAL;
619 }
d38ceaf9
AD		 620 DRM_INFO("amdgpu kernel modesetting enabled.\n");
621 driver = &kms_driver;
622 pdriver = &amdgpu_kms_pci_driver;
d38ceaf9
AD		 623 driver->num_ioctls = amdgpu_max_kms_ioctl;
624 amdgpu_register_atpx_handler();
d38ceaf9
AD		 625 /* let modprobe override vga console setting */
626 return drm_pci_init(driver, pdriver);
627}
628
629static void __exit amdgpu_exit(void)
630{
130e0371 631 amdgpu_amdkfd_fini();
d38ceaf9
AD		 632 drm_pci_exit(driver, pdriver);
633 amdgpu_unregister_atpx_handler();
257bf15a 634 amdgpu_sync_fini();
d573de2d 635 amdgpu_fence_slab_fini();
d38ceaf9
AD		 636}
637
638module_init(amdgpu_init);
639module_exit(amdgpu_exit);
640
641MODULE_AUTHOR(DRIVER_AUTHOR);
642MODULE_DESCRIPTION(DRIVER_DESC);
643MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)