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d38ceaf9 AD |
1 | /** |
2 | * \file amdgpu_drv.c | |
3 | * AMD Amdgpu driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
32 | #include <drm/drmP.h> | |
33 | #include <drm/amdgpu_drm.h> | |
34 | #include <drm/drm_gem.h> | |
35 | #include "amdgpu_drv.h" | |
36 | ||
37 | #include <drm/drm_pciids.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/pm_runtime.h> | |
41 | #include <linux/vga_switcheroo.h> | |
42 | #include "drm_crtc_helper.h" | |
43 | ||
44 | #include "amdgpu.h" | |
45 | #include "amdgpu_irq.h" | |
46 | ||
130e0371 OG |
47 | #include "amdgpu_amdkfd.h" |
48 | ||
d38ceaf9 AD |
49 | /* |
50 | * KMS wrapper. | |
51 | * - 3.0.0 - initial driver | |
6055f37a | 52 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
f84e63f2 MO |
53 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same |
54 | * at the end of IBs. | |
d347ce66 | 55 | * - 3.3.0 - Add VM support for UVD on supported hardware. |
83a59b63 | 56 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. |
8dd31d74 | 57 | * - 3.5.0 - Add support for new UVD_NO_OP register. |
753ad49c | 58 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. |
9cee3c1f | 59 | * - 3.7.0 - Add support for VCE clock list packet |
b62b5931 | 60 | * - 3.8.0 - Add support raster config init in the kernel |
ef704318 | 61 | * - 3.9.0 - Add support for memory query info about VRAM and GTT. |
a5b11dac | 62 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags |
d38ceaf9 AD |
63 | */ |
64 | #define KMS_DRIVER_MAJOR 3 | |
a5b11dac | 65 | #define KMS_DRIVER_MINOR 10 |
d38ceaf9 AD |
66 | #define KMS_DRIVER_PATCHLEVEL 0 |
67 | ||
68 | int amdgpu_vram_limit = 0; | |
69 | int amdgpu_gart_size = -1; /* auto */ | |
95844d20 | 70 | int amdgpu_moverate = -1; /* auto */ |
d38ceaf9 AD |
71 | int amdgpu_benchmarking = 0; |
72 | int amdgpu_testing = 0; | |
73 | int amdgpu_audio = -1; | |
74 | int amdgpu_disp_priority = 0; | |
75 | int amdgpu_hw_i2c = 0; | |
76 | int amdgpu_pcie_gen2 = -1; | |
77 | int amdgpu_msi = -1; | |
a895c222 | 78 | int amdgpu_lockup_timeout = 0; |
d38ceaf9 AD |
79 | int amdgpu_dpm = -1; |
80 | int amdgpu_smc_load_fw = 1; | |
81 | int amdgpu_aspm = -1; | |
82 | int amdgpu_runtime_pm = -1; | |
d38ceaf9 AD |
83 | unsigned amdgpu_ip_block_mask = 0xffffffff; |
84 | int amdgpu_bapm = -1; | |
85 | int amdgpu_deep_color = 0; | |
ed885b21 | 86 | int amdgpu_vm_size = 64; |
d38ceaf9 | 87 | int amdgpu_vm_block_size = -1; |
d9c13156 | 88 | int amdgpu_vm_fault_stop = 0; |
b495bd3a | 89 | int amdgpu_vm_debug = 0; |
6a7f76e7 | 90 | int amdgpu_vram_page_split = 1024; |
d38ceaf9 | 91 | int amdgpu_exp_hw_support = 0; |
b70f014d | 92 | int amdgpu_sched_jobs = 32; |
4afcb303 | 93 | int amdgpu_sched_hw_submission = 2; |
3ca67300 RZ |
94 | int amdgpu_no_evict = 0; |
95 | int amdgpu_direct_gma_size = 0; | |
cd474ba0 AD |
96 | unsigned amdgpu_pcie_gen_cap = 0; |
97 | unsigned amdgpu_pcie_lane_cap = 0; | |
395d1fb9 NH |
98 | unsigned amdgpu_cg_mask = 0xffffffff; |
99 | unsigned amdgpu_pg_mask = 0xffffffff; | |
6f8941a2 | 100 | char *amdgpu_disable_cu = NULL; |
9accf2fd | 101 | char *amdgpu_virtual_display = NULL; |
5141e9d2 | 102 | unsigned amdgpu_pp_feature_mask = 0xffffffff; |
d38ceaf9 AD |
103 | |
104 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); | |
105 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); | |
106 | ||
107 | MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); | |
108 | module_param_named(gartsize, amdgpu_gart_size, int, 0600); | |
109 | ||
95844d20 MO |
110 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); |
111 | module_param_named(moverate, amdgpu_moverate, int, 0600); | |
112 | ||
d38ceaf9 AD |
113 | MODULE_PARM_DESC(benchmark, "Run benchmark"); |
114 | module_param_named(benchmark, amdgpu_benchmarking, int, 0444); | |
115 | ||
116 | MODULE_PARM_DESC(test, "Run tests"); | |
117 | module_param_named(test, amdgpu_testing, int, 0444); | |
118 | ||
119 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); | |
120 | module_param_named(audio, amdgpu_audio, int, 0444); | |
121 | ||
122 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); | |
123 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); | |
124 | ||
125 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); | |
126 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); | |
127 | ||
128 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); | |
129 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); | |
130 | ||
131 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); | |
132 | module_param_named(msi, amdgpu_msi, int, 0444); | |
133 | ||
a895c222 | 134 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); |
d38ceaf9 AD |
135 | module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); |
136 | ||
137 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); | |
138 | module_param_named(dpm, amdgpu_dpm, int, 0444); | |
139 | ||
140 | MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); | |
141 | module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); | |
142 | ||
143 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); | |
144 | module_param_named(aspm, amdgpu_aspm, int, 0444); | |
145 | ||
146 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); | |
147 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); | |
148 | ||
d38ceaf9 AD |
149 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); |
150 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); | |
151 | ||
152 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); | |
153 | module_param_named(bapm, amdgpu_bapm, int, 0444); | |
154 | ||
155 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); | |
156 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); | |
157 | ||
ed885b21 | 158 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
d38ceaf9 AD |
159 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
160 | ||
161 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); | |
162 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); | |
163 | ||
d9c13156 CK |
164 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
165 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); | |
166 | ||
b495bd3a CK |
167 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
168 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); | |
169 | ||
6a7f76e7 CK |
170 | MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); |
171 | module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); | |
172 | ||
d38ceaf9 AD |
173 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
174 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); | |
175 | ||
b70f014d | 176 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
1333f723 JZ |
177 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
178 | ||
4afcb303 JZ |
179 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
180 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); | |
181 | ||
5141e9d2 RZ |
182 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); |
183 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); | |
3a74f6f2 | 184 | |
3ca67300 RZ |
185 | MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); |
186 | module_param_named(no_evict, amdgpu_no_evict, int, 0444); | |
187 | ||
188 | MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); | |
189 | module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); | |
af223dfa | 190 | |
cd474ba0 AD |
191 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
192 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); | |
193 | ||
194 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); | |
195 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); | |
196 | ||
395d1fb9 NH |
197 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); |
198 | module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); | |
199 | ||
200 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); | |
201 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); | |
202 | ||
6f8941a2 NH |
203 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); |
204 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); | |
205 | ||
0f66356d ED |
206 | MODULE_PARM_DESC(virtual_display, |
207 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); | |
9accf2fd | 208 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); |
e443059d | 209 | |
f498d9ed | 210 | static const struct pci_device_id pciidlist[] = { |
78fbb685 KW |
211 | #ifdef CONFIG_DRM_AMDGPU_SI |
212 | {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
213 | {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
214 | {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
215 | {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
216 | {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
217 | {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
218 | {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
219 | {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
220 | {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
221 | {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
222 | {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
223 | {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
224 | {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
225 | {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
226 | {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
227 | {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
228 | {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
229 | {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
230 | {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
231 | {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
232 | {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
233 | {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
234 | {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
235 | {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
236 | {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
237 | {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
238 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
239 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
240 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
241 | {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
242 | {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
243 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
244 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
245 | {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
246 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
247 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
248 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
249 | {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
250 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
251 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
252 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
253 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
254 | {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
255 | {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
256 | {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
257 | {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
258 | {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
259 | {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
260 | {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
261 | {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
262 | {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
263 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
264 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
265 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
266 | {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
267 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
268 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
269 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
270 | {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
271 | {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
272 | {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
273 | {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
274 | {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
275 | {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
276 | {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
277 | {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
278 | {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
279 | {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
280 | {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
281 | {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
282 | {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
283 | {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
284 | #endif | |
89330c39 AD |
285 | #ifdef CONFIG_DRM_AMDGPU_CIK |
286 | /* Kaveri */ | |
2f7d10b3 JZ |
287 | {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
288 | {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
289 | {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
290 | {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
291 | {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
292 | {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
293 | {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
294 | {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
295 | {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
296 | {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
297 | {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
298 | {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
299 | {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
300 | {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
301 | {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
302 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
303 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
304 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
305 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
306 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
307 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
308 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
89330c39 | 309 | /* Bonaire */ |
2f7d10b3 JZ |
310 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
311 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
312 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
313 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
89330c39 AD |
314 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
315 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
316 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
317 | {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
318 | {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
319 | {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
fb4f1737 | 320 | {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
89330c39 AD |
321 | /* Hawaii */ |
322 | {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
323 | {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
324 | {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
325 | {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
326 | {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
327 | {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
328 | {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
329 | {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
330 | {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
331 | {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
332 | {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
333 | {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
334 | /* Kabini */ | |
2f7d10b3 JZ |
335 | {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
336 | {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
337 | {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
338 | {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
339 | {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
340 | {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
341 | {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
342 | {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
343 | {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
344 | {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
345 | {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
346 | {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
347 | {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
348 | {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
349 | {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
350 | {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
89330c39 | 351 | /* mullins */ |
2f7d10b3 JZ |
352 | {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
353 | {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
354 | {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
355 | {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
356 | {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
357 | {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
358 | {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
359 | {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
360 | {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
361 | {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
362 | {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
363 | {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
364 | {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
365 | {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
366 | {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
367 | {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
89330c39 | 368 | #endif |
1256a8b8 | 369 | /* topaz */ |
dba280b2 AD |
370 | {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
371 | {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
372 | {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
373 | {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
374 | {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
1256a8b8 AD |
375 | /* tonga */ |
376 | {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
377 | {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
378 | {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 379 | {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
380 | {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
381 | {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 382 | {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
383 | {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
384 | {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
2da78e21 DZ |
385 | /* fiji */ |
386 | {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, | |
e1d99217 | 387 | {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, |
1256a8b8 | 388 | /* carrizo */ |
2f7d10b3 JZ |
389 | {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
390 | {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
391 | {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
392 | {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
393 | {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
81b1509a SL |
394 | /* stoney */ |
395 | {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, | |
2cc0c0b5 FC |
396 | /* Polaris11 */ |
397 | {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
35621b80 | 398 | {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 399 | {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 400 | {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 | 401 | {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 402 | {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 FC |
403 | {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
404 | {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
405 | {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
2cc0c0b5 FC |
406 | /* Polaris10 */ |
407 | {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1dcf4801 FC |
408 | {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
409 | {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
410 | {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
411 | {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
2cc0c0b5 | 412 | {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
1dcf4801 FC |
413 | {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
414 | {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
415 | {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
416 | {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
417 | {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
fc8e9c54 JZ |
418 | /* Polaris12 */ |
419 | {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
420 | {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
421 | {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
422 | {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
423 | {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
cf8c73af | 424 | {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
fc8e9c54 | 425 | {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
d38ceaf9 AD |
426 | |
427 | {0, 0, 0} | |
428 | }; | |
429 | ||
430 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
431 | ||
432 | static struct drm_driver kms_driver; | |
433 | ||
434 | static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) | |
435 | { | |
436 | struct apertures_struct *ap; | |
437 | bool primary = false; | |
438 | ||
439 | ap = alloc_apertures(1); | |
440 | if (!ap) | |
441 | return -ENOMEM; | |
442 | ||
443 | ap->ranges[0].base = pci_resource_start(pdev, 0); | |
444 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
445 | ||
446 | #ifdef CONFIG_X86 | |
447 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
448 | #endif | |
44adece5 | 449 | drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); |
d38ceaf9 AD |
450 | kfree(ap); |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static int amdgpu_pci_probe(struct pci_dev *pdev, | |
456 | const struct pci_device_id *ent) | |
457 | { | |
458 | unsigned long flags = ent->driver_data; | |
459 | int ret; | |
460 | ||
2f7d10b3 | 461 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
d38ceaf9 AD |
462 | DRM_INFO("This hardware requires experimental hardware support.\n" |
463 | "See modparam exp_hw_support\n"); | |
464 | return -ENODEV; | |
465 | } | |
466 | ||
efb1c658 OG |
467 | /* |
468 | * Initialize amdkfd before starting radeon. If it was not loaded yet, | |
469 | * defer radeon probing | |
470 | */ | |
471 | ret = amdgpu_amdkfd_init(); | |
472 | if (ret == -EPROBE_DEFER) | |
473 | return ret; | |
474 | ||
d38ceaf9 AD |
475 | /* Get rid of things like offb */ |
476 | ret = amdgpu_kick_out_firmware_fb(pdev); | |
477 | if (ret) | |
478 | return ret; | |
479 | ||
480 | return drm_get_pci_dev(pdev, ent, &kms_driver); | |
481 | } | |
482 | ||
483 | static void | |
484 | amdgpu_pci_remove(struct pci_dev *pdev) | |
485 | { | |
486 | struct drm_device *dev = pci_get_drvdata(pdev); | |
487 | ||
488 | drm_put_dev(dev); | |
489 | } | |
490 | ||
61e11306 AD |
491 | static void |
492 | amdgpu_pci_shutdown(struct pci_dev *pdev) | |
493 | { | |
faefba95 AD |
494 | struct drm_device *dev = pci_get_drvdata(pdev); |
495 | struct amdgpu_device *adev = dev->dev_private; | |
496 | ||
61e11306 | 497 | /* if we are running in a VM, make sure the device |
00ea8cba AD |
498 | * torn down properly on reboot/shutdown. |
499 | * unfortunately we can't detect certain | |
500 | * hypervisors so just do this all the time. | |
61e11306 | 501 | */ |
faefba95 | 502 | amdgpu_suspend(adev); |
61e11306 AD |
503 | } |
504 | ||
d38ceaf9 AD |
505 | static int amdgpu_pmops_suspend(struct device *dev) |
506 | { | |
507 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 508 | |
d38ceaf9 | 509 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 510 | return amdgpu_device_suspend(drm_dev, true, true); |
d38ceaf9 AD |
511 | } |
512 | ||
513 | static int amdgpu_pmops_resume(struct device *dev) | |
514 | { | |
515 | struct pci_dev *pdev = to_pci_dev(dev); | |
516 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
85e154c2 AD |
517 | |
518 | /* GPU comes up enabled by the bios on resume */ | |
519 | if (amdgpu_device_is_px(drm_dev)) { | |
520 | pm_runtime_disable(dev); | |
521 | pm_runtime_set_active(dev); | |
522 | pm_runtime_enable(dev); | |
523 | } | |
524 | ||
810ddc3a | 525 | return amdgpu_device_resume(drm_dev, true, true); |
d38ceaf9 AD |
526 | } |
527 | ||
528 | static int amdgpu_pmops_freeze(struct device *dev) | |
529 | { | |
530 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 531 | |
d38ceaf9 | 532 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 533 | return amdgpu_device_suspend(drm_dev, false, true); |
d38ceaf9 AD |
534 | } |
535 | ||
536 | static int amdgpu_pmops_thaw(struct device *dev) | |
537 | { | |
538 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 539 | |
540 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
541 | return amdgpu_device_resume(drm_dev, false, true); | |
542 | } | |
543 | ||
544 | static int amdgpu_pmops_poweroff(struct device *dev) | |
545 | { | |
546 | struct pci_dev *pdev = to_pci_dev(dev); | |
547 | ||
548 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
549 | return amdgpu_device_suspend(drm_dev, true, true); | |
550 | } | |
551 | ||
552 | static int amdgpu_pmops_restore(struct device *dev) | |
553 | { | |
554 | struct pci_dev *pdev = to_pci_dev(dev); | |
555 | ||
d38ceaf9 | 556 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 557 | return amdgpu_device_resume(drm_dev, false, true); |
d38ceaf9 AD |
558 | } |
559 | ||
560 | static int amdgpu_pmops_runtime_suspend(struct device *dev) | |
561 | { | |
562 | struct pci_dev *pdev = to_pci_dev(dev); | |
563 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
564 | int ret; | |
565 | ||
566 | if (!amdgpu_device_is_px(drm_dev)) { | |
567 | pm_runtime_forbid(dev); | |
568 | return -EBUSY; | |
569 | } | |
570 | ||
571 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
572 | drm_kms_helper_poll_disable(drm_dev); | |
573 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); | |
574 | ||
810ddc3a | 575 | ret = amdgpu_device_suspend(drm_dev, false, false); |
d38ceaf9 AD |
576 | pci_save_state(pdev); |
577 | pci_disable_device(pdev); | |
578 | pci_ignore_hotplug(pdev); | |
11670975 AD |
579 | if (amdgpu_is_atpx_hybrid()) |
580 | pci_set_power_state(pdev, PCI_D3cold); | |
522761cb | 581 | else if (!amdgpu_has_atpx_dgpu_power_cntl()) |
7e32aa61 | 582 | pci_set_power_state(pdev, PCI_D3hot); |
d38ceaf9 AD |
583 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | static int amdgpu_pmops_runtime_resume(struct device *dev) | |
589 | { | |
590 | struct pci_dev *pdev = to_pci_dev(dev); | |
591 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
592 | int ret; | |
593 | ||
594 | if (!amdgpu_device_is_px(drm_dev)) | |
595 | return -EINVAL; | |
596 | ||
597 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
598 | ||
522761cb AD |
599 | if (amdgpu_is_atpx_hybrid() || |
600 | !amdgpu_has_atpx_dgpu_power_cntl()) | |
601 | pci_set_power_state(pdev, PCI_D0); | |
d38ceaf9 AD |
602 | pci_restore_state(pdev); |
603 | ret = pci_enable_device(pdev); | |
604 | if (ret) | |
605 | return ret; | |
606 | pci_set_master(pdev); | |
607 | ||
810ddc3a | 608 | ret = amdgpu_device_resume(drm_dev, false, false); |
d38ceaf9 AD |
609 | drm_kms_helper_poll_enable(drm_dev); |
610 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); | |
611 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
612 | return 0; | |
613 | } | |
614 | ||
615 | static int amdgpu_pmops_runtime_idle(struct device *dev) | |
616 | { | |
617 | struct pci_dev *pdev = to_pci_dev(dev); | |
618 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
619 | struct drm_crtc *crtc; | |
620 | ||
621 | if (!amdgpu_device_is_px(drm_dev)) { | |
622 | pm_runtime_forbid(dev); | |
623 | return -EBUSY; | |
624 | } | |
625 | ||
626 | list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { | |
627 | if (crtc->enabled) { | |
628 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
629 | return -EBUSY; | |
630 | } | |
631 | } | |
632 | ||
633 | pm_runtime_mark_last_busy(dev); | |
634 | pm_runtime_autosuspend(dev); | |
635 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
636 | return 1; | |
637 | } | |
638 | ||
639 | long amdgpu_drm_ioctl(struct file *filp, | |
640 | unsigned int cmd, unsigned long arg) | |
641 | { | |
642 | struct drm_file *file_priv = filp->private_data; | |
643 | struct drm_device *dev; | |
644 | long ret; | |
645 | dev = file_priv->minor->dev; | |
646 | ret = pm_runtime_get_sync(dev->dev); | |
647 | if (ret < 0) | |
648 | return ret; | |
649 | ||
650 | ret = drm_ioctl(filp, cmd, arg); | |
651 | ||
652 | pm_runtime_mark_last_busy(dev->dev); | |
653 | pm_runtime_put_autosuspend(dev->dev); | |
654 | return ret; | |
655 | } | |
656 | ||
657 | static const struct dev_pm_ops amdgpu_pm_ops = { | |
658 | .suspend = amdgpu_pmops_suspend, | |
659 | .resume = amdgpu_pmops_resume, | |
660 | .freeze = amdgpu_pmops_freeze, | |
661 | .thaw = amdgpu_pmops_thaw, | |
74b0b157 | 662 | .poweroff = amdgpu_pmops_poweroff, |
663 | .restore = amdgpu_pmops_restore, | |
d38ceaf9 AD |
664 | .runtime_suspend = amdgpu_pmops_runtime_suspend, |
665 | .runtime_resume = amdgpu_pmops_runtime_resume, | |
666 | .runtime_idle = amdgpu_pmops_runtime_idle, | |
667 | }; | |
668 | ||
669 | static const struct file_operations amdgpu_driver_kms_fops = { | |
670 | .owner = THIS_MODULE, | |
671 | .open = drm_open, | |
672 | .release = drm_release, | |
673 | .unlocked_ioctl = amdgpu_drm_ioctl, | |
674 | .mmap = amdgpu_mmap, | |
675 | .poll = drm_poll, | |
676 | .read = drm_read, | |
677 | #ifdef CONFIG_COMPAT | |
678 | .compat_ioctl = amdgpu_kms_compat_ioctl, | |
679 | #endif | |
680 | }; | |
681 | ||
682 | static struct drm_driver kms_driver = { | |
683 | .driver_features = | |
684 | DRIVER_USE_AGP | | |
685 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | | |
7056bb5c | 686 | DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, |
d38ceaf9 AD |
687 | .load = amdgpu_driver_load_kms, |
688 | .open = amdgpu_driver_open_kms, | |
689 | .preclose = amdgpu_driver_preclose_kms, | |
690 | .postclose = amdgpu_driver_postclose_kms, | |
691 | .lastclose = amdgpu_driver_lastclose_kms, | |
692 | .set_busid = drm_pci_set_busid, | |
693 | .unload = amdgpu_driver_unload_kms, | |
694 | .get_vblank_counter = amdgpu_get_vblank_counter_kms, | |
695 | .enable_vblank = amdgpu_enable_vblank_kms, | |
696 | .disable_vblank = amdgpu_disable_vblank_kms, | |
697 | .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, | |
698 | .get_scanout_position = amdgpu_get_crtc_scanoutpos, | |
699 | #if defined(CONFIG_DEBUG_FS) | |
700 | .debugfs_init = amdgpu_debugfs_init, | |
d38ceaf9 AD |
701 | #endif |
702 | .irq_preinstall = amdgpu_irq_preinstall, | |
703 | .irq_postinstall = amdgpu_irq_postinstall, | |
704 | .irq_uninstall = amdgpu_irq_uninstall, | |
705 | .irq_handler = amdgpu_irq_handler, | |
706 | .ioctls = amdgpu_ioctls_kms, | |
e7294dee | 707 | .gem_free_object_unlocked = amdgpu_gem_object_free, |
d38ceaf9 AD |
708 | .gem_open_object = amdgpu_gem_object_open, |
709 | .gem_close_object = amdgpu_gem_object_close, | |
710 | .dumb_create = amdgpu_mode_dumb_create, | |
711 | .dumb_map_offset = amdgpu_mode_dumb_mmap, | |
712 | .dumb_destroy = drm_gem_dumb_destroy, | |
713 | .fops = &amdgpu_driver_kms_fops, | |
714 | ||
715 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
716 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
717 | .gem_prime_export = amdgpu_gem_prime_export, | |
718 | .gem_prime_import = drm_gem_prime_import, | |
719 | .gem_prime_pin = amdgpu_gem_prime_pin, | |
720 | .gem_prime_unpin = amdgpu_gem_prime_unpin, | |
721 | .gem_prime_res_obj = amdgpu_gem_prime_res_obj, | |
722 | .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, | |
723 | .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, | |
724 | .gem_prime_vmap = amdgpu_gem_prime_vmap, | |
725 | .gem_prime_vunmap = amdgpu_gem_prime_vunmap, | |
726 | ||
727 | .name = DRIVER_NAME, | |
728 | .desc = DRIVER_DESC, | |
729 | .date = DRIVER_DATE, | |
730 | .major = KMS_DRIVER_MAJOR, | |
731 | .minor = KMS_DRIVER_MINOR, | |
732 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
733 | }; | |
734 | ||
735 | static struct drm_driver *driver; | |
736 | static struct pci_driver *pdriver; | |
737 | ||
738 | static struct pci_driver amdgpu_kms_pci_driver = { | |
739 | .name = DRIVER_NAME, | |
740 | .id_table = pciidlist, | |
741 | .probe = amdgpu_pci_probe, | |
742 | .remove = amdgpu_pci_remove, | |
61e11306 | 743 | .shutdown = amdgpu_pci_shutdown, |
d38ceaf9 AD |
744 | .driver.pm = &amdgpu_pm_ops, |
745 | }; | |
746 | ||
d573de2d RZ |
747 | |
748 | ||
d38ceaf9 AD |
749 | static int __init amdgpu_init(void) |
750 | { | |
245ae5e9 CK |
751 | int r; |
752 | ||
753 | r = amdgpu_sync_init(); | |
754 | if (r) | |
755 | goto error_sync; | |
756 | ||
757 | r = amdgpu_fence_slab_init(); | |
758 | if (r) | |
759 | goto error_fence; | |
760 | ||
761 | r = amd_sched_fence_slab_init(); | |
762 | if (r) | |
763 | goto error_sched; | |
764 | ||
d38ceaf9 AD |
765 | if (vgacon_text_force()) { |
766 | DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); | |
767 | return -EINVAL; | |
768 | } | |
d38ceaf9 AD |
769 | DRM_INFO("amdgpu kernel modesetting enabled.\n"); |
770 | driver = &kms_driver; | |
771 | pdriver = &amdgpu_kms_pci_driver; | |
d38ceaf9 AD |
772 | driver->num_ioctls = amdgpu_max_kms_ioctl; |
773 | amdgpu_register_atpx_handler(); | |
d38ceaf9 AD |
774 | /* let modprobe override vga console setting */ |
775 | return drm_pci_init(driver, pdriver); | |
245ae5e9 CK |
776 | |
777 | error_sched: | |
778 | amdgpu_fence_slab_fini(); | |
779 | ||
780 | error_fence: | |
781 | amdgpu_sync_fini(); | |
782 | ||
783 | error_sync: | |
784 | return r; | |
d38ceaf9 AD |
785 | } |
786 | ||
787 | static void __exit amdgpu_exit(void) | |
788 | { | |
130e0371 | 789 | amdgpu_amdkfd_fini(); |
d38ceaf9 AD |
790 | drm_pci_exit(driver, pdriver); |
791 | amdgpu_unregister_atpx_handler(); | |
257bf15a | 792 | amdgpu_sync_fini(); |
c24784f0 | 793 | amd_sched_fence_slab_fini(); |
d573de2d | 794 | amdgpu_fence_slab_fini(); |
d38ceaf9 AD |
795 | } |
796 | ||
797 | module_init(amdgpu_init); | |
798 | module_exit(amdgpu_exit); | |
799 | ||
800 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
801 | MODULE_DESCRIPTION(DRIVER_DESC); | |
802 | MODULE_LICENSE("GPL and additional rights"); |