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d38ceaf9 AD |
1 | /** |
2 | * \file amdgpu_drv.c | |
3 | * AMD Amdgpu driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
32 | #include <drm/drmP.h> | |
33 | #include <drm/amdgpu_drm.h> | |
34 | #include <drm/drm_gem.h> | |
35 | #include "amdgpu_drv.h" | |
36 | ||
37 | #include <drm/drm_pciids.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/pm_runtime.h> | |
41 | #include <linux/vga_switcheroo.h> | |
248a1d6f | 42 | #include <drm/drm_crtc_helper.h> |
d38ceaf9 AD |
43 | |
44 | #include "amdgpu.h" | |
45 | #include "amdgpu_irq.h" | |
46 | ||
130e0371 OG |
47 | #include "amdgpu_amdkfd.h" |
48 | ||
d38ceaf9 AD |
49 | /* |
50 | * KMS wrapper. | |
51 | * - 3.0.0 - initial driver | |
6055f37a | 52 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
f84e63f2 MO |
53 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same |
54 | * at the end of IBs. | |
d347ce66 | 55 | * - 3.3.0 - Add VM support for UVD on supported hardware. |
83a59b63 | 56 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. |
8dd31d74 | 57 | * - 3.5.0 - Add support for new UVD_NO_OP register. |
753ad49c | 58 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. |
9cee3c1f | 59 | * - 3.7.0 - Add support for VCE clock list packet |
b62b5931 | 60 | * - 3.8.0 - Add support raster config init in the kernel |
ef704318 | 61 | * - 3.9.0 - Add support for memory query info about VRAM and GTT. |
a5b11dac | 62 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags |
5ebbac4b | 63 | * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). |
dfe38bd8 | 64 | * - 3.12.0 - Add query for double offchip LDS buffers |
8eafd505 | 65 | * - 3.13.0 - Add PRT support |
203eb0cb | 66 | * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality |
44eb8c1b | 67 | * - 3.15.0 - Export more gpu info for gfx9 |
b98b8dbc | 68 | * - 3.16.0 - Add reserved vmid support |
68e2c5ff | 69 | * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. |
dbfe85ea | 70 | * - 3.18.0 - Export gpu always on cu bitmap |
33476319 | 71 | * - 3.19.0 - Add support for UVD MJPEG decode |
fd8bf087 | 72 | * - 3.20.0 - Add support for local BOs |
7ca24cf2 | 73 | * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl |
b285f1db | 74 | * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl |
c057c114 | 75 | * - 3.23.0 - Add query for VRAM lost counter |
f8e3e0ee | 76 | * - 3.24.0 - Add high priority compute support for gfx9 |
7b158d16 | 77 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). |
d38ceaf9 AD |
78 | */ |
79 | #define KMS_DRIVER_MAJOR 3 | |
7b158d16 | 80 | #define KMS_DRIVER_MINOR 25 |
d38ceaf9 AD |
81 | #define KMS_DRIVER_PATCHLEVEL 0 |
82 | ||
83 | int amdgpu_vram_limit = 0; | |
218b5dcd | 84 | int amdgpu_vis_vram_limit = 0; |
83e74db6 | 85 | int amdgpu_gart_size = -1; /* auto */ |
36d38372 | 86 | int amdgpu_gtt_size = -1; /* auto */ |
95844d20 | 87 | int amdgpu_moverate = -1; /* auto */ |
d38ceaf9 AD |
88 | int amdgpu_benchmarking = 0; |
89 | int amdgpu_testing = 0; | |
90 | int amdgpu_audio = -1; | |
91 | int amdgpu_disp_priority = 0; | |
92 | int amdgpu_hw_i2c = 0; | |
93 | int amdgpu_pcie_gen2 = -1; | |
94 | int amdgpu_msi = -1; | |
8854695a | 95 | int amdgpu_lockup_timeout = 10000; |
d38ceaf9 | 96 | int amdgpu_dpm = -1; |
e635ee07 | 97 | int amdgpu_fw_load_type = -1; |
d38ceaf9 AD |
98 | int amdgpu_aspm = -1; |
99 | int amdgpu_runtime_pm = -1; | |
0b693f0b | 100 | uint amdgpu_ip_block_mask = 0xffffffff; |
d38ceaf9 AD |
101 | int amdgpu_bapm = -1; |
102 | int amdgpu_deep_color = 0; | |
bab4fee7 | 103 | int amdgpu_vm_size = -1; |
d07f14be | 104 | int amdgpu_vm_fragment_size = -1; |
d38ceaf9 | 105 | int amdgpu_vm_block_size = -1; |
d9c13156 | 106 | int amdgpu_vm_fault_stop = 0; |
b495bd3a | 107 | int amdgpu_vm_debug = 0; |
60bfcd31 | 108 | int amdgpu_vram_page_split = 512; |
9a4b7d4c | 109 | int amdgpu_vm_update_mode = -1; |
d38ceaf9 | 110 | int amdgpu_exp_hw_support = 0; |
4562236b | 111 | int amdgpu_dc = -1; |
02e749dc | 112 | int amdgpu_dc_log = 0; |
b70f014d | 113 | int amdgpu_sched_jobs = 32; |
4afcb303 | 114 | int amdgpu_sched_hw_submission = 2; |
3ca67300 RZ |
115 | int amdgpu_no_evict = 0; |
116 | int amdgpu_direct_gma_size = 0; | |
0b693f0b RZ |
117 | uint amdgpu_pcie_gen_cap = 0; |
118 | uint amdgpu_pcie_lane_cap = 0; | |
119 | uint amdgpu_cg_mask = 0xffffffff; | |
120 | uint amdgpu_pg_mask = 0xffffffff; | |
121 | uint amdgpu_sdma_phase_quantum = 32; | |
6f8941a2 | 122 | char *amdgpu_disable_cu = NULL; |
9accf2fd | 123 | char *amdgpu_virtual_display = NULL; |
3d2fc081 | 124 | uint amdgpu_pp_feature_mask = 0xffffbfff; |
bce23e00 AD |
125 | int amdgpu_ngg = 0; |
126 | int amdgpu_prim_buf_per_se = 0; | |
127 | int amdgpu_pos_buf_per_se = 0; | |
128 | int amdgpu_cntl_sb_buf_per_se = 0; | |
129 | int amdgpu_param_buf_per_se = 0; | |
65781c78 | 130 | int amdgpu_job_hang_limit = 0; |
e8835e0e | 131 | int amdgpu_lbpw = -1; |
4a75aefe | 132 | int amdgpu_compute_multipipe = -1; |
dcebf026 | 133 | int amdgpu_gpu_recovery = -1; /* auto */ |
bfca0289 | 134 | int amdgpu_emu_mode = 0; |
d38ceaf9 AD |
135 | |
136 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); | |
137 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); | |
138 | ||
218b5dcd JB |
139 | MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); |
140 | module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); | |
141 | ||
a4da14cc | 142 | MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); |
f9321cc4 | 143 | module_param_named(gartsize, amdgpu_gart_size, uint, 0600); |
d38ceaf9 | 144 | |
36d38372 CK |
145 | MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); |
146 | module_param_named(gttsize, amdgpu_gtt_size, int, 0600); | |
d38ceaf9 | 147 | |
95844d20 MO |
148 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); |
149 | module_param_named(moverate, amdgpu_moverate, int, 0600); | |
150 | ||
d38ceaf9 AD |
151 | MODULE_PARM_DESC(benchmark, "Run benchmark"); |
152 | module_param_named(benchmark, amdgpu_benchmarking, int, 0444); | |
153 | ||
154 | MODULE_PARM_DESC(test, "Run tests"); | |
155 | module_param_named(test, amdgpu_testing, int, 0444); | |
156 | ||
157 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); | |
158 | module_param_named(audio, amdgpu_audio, int, 0444); | |
159 | ||
160 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); | |
161 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); | |
162 | ||
163 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); | |
164 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); | |
165 | ||
166 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); | |
167 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); | |
168 | ||
169 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); | |
170 | module_param_named(msi, amdgpu_msi, int, 0444); | |
171 | ||
8854695a | 172 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)"); |
d38ceaf9 AD |
173 | module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); |
174 | ||
175 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); | |
176 | module_param_named(dpm, amdgpu_dpm, int, 0444); | |
177 | ||
e635ee07 HR |
178 | MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); |
179 | module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); | |
d38ceaf9 AD |
180 | |
181 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); | |
182 | module_param_named(aspm, amdgpu_aspm, int, 0444); | |
183 | ||
184 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); | |
185 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); | |
186 | ||
d38ceaf9 AD |
187 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); |
188 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); | |
189 | ||
190 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); | |
191 | module_param_named(bapm, amdgpu_bapm, int, 0444); | |
192 | ||
193 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); | |
194 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); | |
195 | ||
ed885b21 | 196 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
d38ceaf9 | 197 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
d07f14be RH |
198 | |
199 | MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); | |
200 | module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); | |
d38ceaf9 AD |
201 | |
202 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); | |
203 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); | |
204 | ||
d9c13156 CK |
205 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
206 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); | |
207 | ||
b495bd3a CK |
208 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
209 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); | |
210 | ||
9a4b7d4c HK |
211 | MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); |
212 | module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); | |
213 | ||
ccfee95c | 214 | MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); |
6a7f76e7 CK |
215 | module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); |
216 | ||
d38ceaf9 AD |
217 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
218 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); | |
219 | ||
4562236b HW |
220 | MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); |
221 | module_param_named(dc, amdgpu_dc, int, 0444); | |
222 | ||
96b8af6e | 223 | MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty"); |
02e749dc HW |
224 | module_param_named(dc_log, amdgpu_dc_log, int, 0444); |
225 | ||
b70f014d | 226 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
1333f723 JZ |
227 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
228 | ||
4afcb303 JZ |
229 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
230 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); | |
231 | ||
5141e9d2 | 232 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); |
88826351 | 233 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); |
3a74f6f2 | 234 | |
3ca67300 RZ |
235 | MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); |
236 | module_param_named(no_evict, amdgpu_no_evict, int, 0444); | |
237 | ||
238 | MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); | |
239 | module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); | |
af223dfa | 240 | |
cd474ba0 AD |
241 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
242 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); | |
243 | ||
244 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); | |
245 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); | |
246 | ||
395d1fb9 NH |
247 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); |
248 | module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); | |
249 | ||
250 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); | |
251 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); | |
252 | ||
a667386c FK |
253 | MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); |
254 | module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); | |
255 | ||
6f8941a2 NH |
256 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); |
257 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); | |
258 | ||
0f66356d ED |
259 | MODULE_PARM_DESC(virtual_display, |
260 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); | |
9accf2fd | 261 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); |
e443059d | 262 | |
bce23e00 AD |
263 | MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); |
264 | module_param_named(ngg, amdgpu_ngg, int, 0444); | |
265 | ||
266 | MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); | |
267 | module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); | |
268 | ||
269 | MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); | |
270 | module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); | |
271 | ||
272 | MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); | |
273 | module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); | |
274 | ||
275 | MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); | |
276 | module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); | |
277 | ||
65781c78 ML |
278 | MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); |
279 | module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); | |
280 | ||
e8835e0e HZ |
281 | MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); |
282 | module_param_named(lbpw, amdgpu_lbpw, int, 0444); | |
bce23e00 | 283 | |
4a75aefe AR |
284 | MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); |
285 | module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); | |
286 | ||
d869ae09 | 287 | MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); |
dcebf026 AG |
288 | module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); |
289 | ||
d869ae09 | 290 | MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); |
bfca0289 SL |
291 | module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); |
292 | ||
6dd13096 | 293 | #ifdef CONFIG_DRM_AMDGPU_SI |
53efaf56 MD |
294 | |
295 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
6dd13096 FK |
296 | int amdgpu_si_support = 0; |
297 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
298 | #else |
299 | int amdgpu_si_support = 1; | |
300 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); | |
301 | #endif | |
302 | ||
6dd13096 FK |
303 | module_param_named(si_support, amdgpu_si_support, int, 0444); |
304 | #endif | |
305 | ||
7df28986 | 306 | #ifdef CONFIG_DRM_AMDGPU_CIK |
53efaf56 MD |
307 | |
308 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
2b059658 MD |
309 | int amdgpu_cik_support = 0; |
310 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
311 | #else |
312 | int amdgpu_cik_support = 1; | |
313 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); | |
314 | #endif | |
315 | ||
7df28986 FK |
316 | module_param_named(cik_support, amdgpu_cik_support, int, 0444); |
317 | #endif | |
318 | ||
f498d9ed | 319 | static const struct pci_device_id pciidlist[] = { |
78fbb685 KW |
320 | #ifdef CONFIG_DRM_AMDGPU_SI |
321 | {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
322 | {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
323 | {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
324 | {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
325 | {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
326 | {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
327 | {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
328 | {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
329 | {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
330 | {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
331 | {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
332 | {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
333 | {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
334 | {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
335 | {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
336 | {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
337 | {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
338 | {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
339 | {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
340 | {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
341 | {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
342 | {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
343 | {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
344 | {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
345 | {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
346 | {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
347 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
348 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
349 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
350 | {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
351 | {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
352 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
353 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
354 | {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
355 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
356 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
357 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
358 | {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
359 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
360 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
361 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
362 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
363 | {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
364 | {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
365 | {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
366 | {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
367 | {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
368 | {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
369 | {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
370 | {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
371 | {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
372 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
373 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
374 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
375 | {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
376 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
377 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
378 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
379 | {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
380 | {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
381 | {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
382 | {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
383 | {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
384 | {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
385 | {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
386 | {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
387 | {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
388 | {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
389 | {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
390 | {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
391 | {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
392 | {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
393 | #endif | |
89330c39 AD |
394 | #ifdef CONFIG_DRM_AMDGPU_CIK |
395 | /* Kaveri */ | |
2f7d10b3 JZ |
396 | {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
397 | {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
398 | {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
399 | {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
400 | {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
401 | {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
402 | {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
403 | {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
404 | {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
405 | {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
406 | {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
407 | {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
408 | {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
409 | {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
410 | {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
411 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
412 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
413 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
414 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
415 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
416 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
417 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
89330c39 | 418 | /* Bonaire */ |
2f7d10b3 JZ |
419 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
420 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
421 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
422 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
89330c39 AD |
423 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
424 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
425 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
426 | {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
427 | {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
428 | {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
fb4f1737 | 429 | {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
89330c39 AD |
430 | /* Hawaii */ |
431 | {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
432 | {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
433 | {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
434 | {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
435 | {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
436 | {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
437 | {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
438 | {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
439 | {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
440 | {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
441 | {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
442 | {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
443 | /* Kabini */ | |
2f7d10b3 JZ |
444 | {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
445 | {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
446 | {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
447 | {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
448 | {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
449 | {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
450 | {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
451 | {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
452 | {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
453 | {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
454 | {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
455 | {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
456 | {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
457 | {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
458 | {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
459 | {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
89330c39 | 460 | /* mullins */ |
2f7d10b3 JZ |
461 | {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
462 | {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
463 | {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
464 | {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
465 | {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
466 | {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
467 | {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
468 | {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
469 | {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
470 | {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
471 | {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
472 | {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
473 | {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
474 | {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
475 | {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
476 | {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
89330c39 | 477 | #endif |
1256a8b8 | 478 | /* topaz */ |
dba280b2 AD |
479 | {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
480 | {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
481 | {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
482 | {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
483 | {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
1256a8b8 AD |
484 | /* tonga */ |
485 | {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
486 | {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
487 | {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 488 | {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
489 | {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
490 | {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 491 | {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
492 | {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
493 | {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
2da78e21 DZ |
494 | /* fiji */ |
495 | {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, | |
e1d99217 | 496 | {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, |
1256a8b8 | 497 | /* carrizo */ |
2f7d10b3 JZ |
498 | {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
499 | {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
500 | {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
501 | {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
502 | {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
81b1509a SL |
503 | /* stoney */ |
504 | {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, | |
2cc0c0b5 FC |
505 | /* Polaris11 */ |
506 | {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
35621b80 | 507 | {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 508 | {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 509 | {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 | 510 | {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 511 | {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 FC |
512 | {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
513 | {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
514 | {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
2cc0c0b5 FC |
515 | /* Polaris10 */ |
516 | {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1dcf4801 FC |
517 | {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
518 | {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
519 | {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
520 | {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
7dae6181 | 521 | {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
2cc0c0b5 | 522 | {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
1dcf4801 FC |
523 | {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
524 | {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
525 | {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
526 | {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
527 | {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
fc8e9c54 JZ |
528 | /* Polaris12 */ |
529 | {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
530 | {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
531 | {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
532 | {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
533 | {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
cf8c73af | 534 | {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
6e88491c | 535 | {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
fc8e9c54 | 536 | {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
ca2f1cca | 537 | /* Vega 10 */ |
dfbf0c14 AD |
538 | {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
539 | {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
540 | {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
541 | {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
542 | {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
543 | {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
544 | {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
545 | {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
546 | {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
dc53d543 AD |
547 | /* Vega 12 */ |
548 | {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
549 | {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
550 | {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
551 | {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
552 | {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
df515052 | 553 | /* Raven */ |
acc34503 | 554 | {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
df515052 | 555 | |
d38ceaf9 AD |
556 | {0, 0, 0} |
557 | }; | |
558 | ||
559 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
560 | ||
561 | static struct drm_driver kms_driver; | |
562 | ||
563 | static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) | |
564 | { | |
565 | struct apertures_struct *ap; | |
566 | bool primary = false; | |
567 | ||
568 | ap = alloc_apertures(1); | |
569 | if (!ap) | |
570 | return -ENOMEM; | |
571 | ||
572 | ap->ranges[0].base = pci_resource_start(pdev, 0); | |
573 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
574 | ||
575 | #ifdef CONFIG_X86 | |
576 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
577 | #endif | |
44adece5 | 578 | drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); |
d38ceaf9 AD |
579 | kfree(ap); |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
1daee8b4 | 584 | |
d38ceaf9 AD |
585 | static int amdgpu_pci_probe(struct pci_dev *pdev, |
586 | const struct pci_device_id *ent) | |
587 | { | |
b58c1131 | 588 | struct drm_device *dev; |
d38ceaf9 | 589 | unsigned long flags = ent->driver_data; |
1daee8b4 | 590 | int ret, retry = 0; |
3fa203af AD |
591 | bool supports_atomic = false; |
592 | ||
593 | if (!amdgpu_virtual_display && | |
594 | amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) | |
595 | supports_atomic = true; | |
d38ceaf9 | 596 | |
2f7d10b3 | 597 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
d38ceaf9 AD |
598 | DRM_INFO("This hardware requires experimental hardware support.\n" |
599 | "See modparam exp_hw_support\n"); | |
600 | return -ENODEV; | |
601 | } | |
602 | ||
efb1c658 OG |
603 | /* |
604 | * Initialize amdkfd before starting radeon. If it was not loaded yet, | |
605 | * defer radeon probing | |
606 | */ | |
607 | ret = amdgpu_amdkfd_init(); | |
608 | if (ret == -EPROBE_DEFER) | |
609 | return ret; | |
610 | ||
d38ceaf9 AD |
611 | /* Get rid of things like offb */ |
612 | ret = amdgpu_kick_out_firmware_fb(pdev); | |
613 | if (ret) | |
614 | return ret; | |
615 | ||
3fa203af AD |
616 | /* warn the user if they mix atomic and non-atomic capable GPUs */ |
617 | if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) | |
618 | DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); | |
619 | /* support atomic early so the atomic debugfs stuff gets created */ | |
620 | if (supports_atomic) | |
621 | kms_driver.driver_features |= DRIVER_ATOMIC; | |
622 | ||
b58c1131 AD |
623 | dev = drm_dev_alloc(&kms_driver, &pdev->dev); |
624 | if (IS_ERR(dev)) | |
625 | return PTR_ERR(dev); | |
626 | ||
627 | ret = pci_enable_device(pdev); | |
628 | if (ret) | |
629 | goto err_free; | |
630 | ||
631 | dev->pdev = pdev; | |
632 | ||
633 | pci_set_drvdata(pdev, dev); | |
634 | ||
1daee8b4 | 635 | retry_init: |
b58c1131 | 636 | ret = drm_dev_register(dev, ent->driver_data); |
1daee8b4 PD |
637 | if (ret == -EAGAIN && ++retry <= 3) { |
638 | DRM_INFO("retry init %d\n", retry); | |
639 | /* Don't request EX mode too frequently which is attacking */ | |
640 | msleep(5000); | |
641 | goto retry_init; | |
642 | } else if (ret) | |
b58c1131 AD |
643 | goto err_pci; |
644 | ||
645 | return 0; | |
646 | ||
647 | err_pci: | |
648 | pci_disable_device(pdev); | |
649 | err_free: | |
650 | drm_dev_unref(dev); | |
651 | return ret; | |
d38ceaf9 AD |
652 | } |
653 | ||
654 | static void | |
655 | amdgpu_pci_remove(struct pci_dev *pdev) | |
656 | { | |
657 | struct drm_device *dev = pci_get_drvdata(pdev); | |
658 | ||
b58c1131 AD |
659 | drm_dev_unregister(dev); |
660 | drm_dev_unref(dev); | |
fd4495e5 XY |
661 | pci_disable_device(pdev); |
662 | pci_set_drvdata(pdev, NULL); | |
d38ceaf9 AD |
663 | } |
664 | ||
61e11306 AD |
665 | static void |
666 | amdgpu_pci_shutdown(struct pci_dev *pdev) | |
667 | { | |
faefba95 AD |
668 | struct drm_device *dev = pci_get_drvdata(pdev); |
669 | struct amdgpu_device *adev = dev->dev_private; | |
670 | ||
61e11306 | 671 | /* if we are running in a VM, make sure the device |
00ea8cba AD |
672 | * torn down properly on reboot/shutdown. |
673 | * unfortunately we can't detect certain | |
674 | * hypervisors so just do this all the time. | |
61e11306 | 675 | */ |
cdd61df6 | 676 | amdgpu_device_ip_suspend(adev); |
61e11306 AD |
677 | } |
678 | ||
d38ceaf9 AD |
679 | static int amdgpu_pmops_suspend(struct device *dev) |
680 | { | |
681 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 682 | |
d38ceaf9 | 683 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 684 | return amdgpu_device_suspend(drm_dev, true, true); |
d38ceaf9 AD |
685 | } |
686 | ||
687 | static int amdgpu_pmops_resume(struct device *dev) | |
688 | { | |
689 | struct pci_dev *pdev = to_pci_dev(dev); | |
690 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
85e154c2 AD |
691 | |
692 | /* GPU comes up enabled by the bios on resume */ | |
693 | if (amdgpu_device_is_px(drm_dev)) { | |
694 | pm_runtime_disable(dev); | |
695 | pm_runtime_set_active(dev); | |
696 | pm_runtime_enable(dev); | |
697 | } | |
698 | ||
810ddc3a | 699 | return amdgpu_device_resume(drm_dev, true, true); |
d38ceaf9 AD |
700 | } |
701 | ||
702 | static int amdgpu_pmops_freeze(struct device *dev) | |
703 | { | |
704 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 705 | |
d38ceaf9 | 706 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 707 | return amdgpu_device_suspend(drm_dev, false, true); |
d38ceaf9 AD |
708 | } |
709 | ||
710 | static int amdgpu_pmops_thaw(struct device *dev) | |
711 | { | |
712 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 713 | |
714 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
715 | return amdgpu_device_resume(drm_dev, false, true); | |
716 | } | |
717 | ||
718 | static int amdgpu_pmops_poweroff(struct device *dev) | |
719 | { | |
720 | struct pci_dev *pdev = to_pci_dev(dev); | |
721 | ||
722 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
723 | return amdgpu_device_suspend(drm_dev, true, true); | |
724 | } | |
725 | ||
726 | static int amdgpu_pmops_restore(struct device *dev) | |
727 | { | |
728 | struct pci_dev *pdev = to_pci_dev(dev); | |
729 | ||
d38ceaf9 | 730 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 731 | return amdgpu_device_resume(drm_dev, false, true); |
d38ceaf9 AD |
732 | } |
733 | ||
734 | static int amdgpu_pmops_runtime_suspend(struct device *dev) | |
735 | { | |
736 | struct pci_dev *pdev = to_pci_dev(dev); | |
737 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
738 | int ret; | |
739 | ||
740 | if (!amdgpu_device_is_px(drm_dev)) { | |
741 | pm_runtime_forbid(dev); | |
742 | return -EBUSY; | |
743 | } | |
744 | ||
745 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
746 | drm_kms_helper_poll_disable(drm_dev); | |
d38ceaf9 | 747 | |
810ddc3a | 748 | ret = amdgpu_device_suspend(drm_dev, false, false); |
d38ceaf9 AD |
749 | pci_save_state(pdev); |
750 | pci_disable_device(pdev); | |
751 | pci_ignore_hotplug(pdev); | |
11670975 AD |
752 | if (amdgpu_is_atpx_hybrid()) |
753 | pci_set_power_state(pdev, PCI_D3cold); | |
522761cb | 754 | else if (!amdgpu_has_atpx_dgpu_power_cntl()) |
7e32aa61 | 755 | pci_set_power_state(pdev, PCI_D3hot); |
d38ceaf9 AD |
756 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | static int amdgpu_pmops_runtime_resume(struct device *dev) | |
762 | { | |
763 | struct pci_dev *pdev = to_pci_dev(dev); | |
764 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
765 | int ret; | |
766 | ||
767 | if (!amdgpu_device_is_px(drm_dev)) | |
768 | return -EINVAL; | |
769 | ||
770 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
771 | ||
522761cb AD |
772 | if (amdgpu_is_atpx_hybrid() || |
773 | !amdgpu_has_atpx_dgpu_power_cntl()) | |
774 | pci_set_power_state(pdev, PCI_D0); | |
d38ceaf9 AD |
775 | pci_restore_state(pdev); |
776 | ret = pci_enable_device(pdev); | |
777 | if (ret) | |
778 | return ret; | |
779 | pci_set_master(pdev); | |
780 | ||
810ddc3a | 781 | ret = amdgpu_device_resume(drm_dev, false, false); |
d38ceaf9 | 782 | drm_kms_helper_poll_enable(drm_dev); |
d38ceaf9 AD |
783 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
784 | return 0; | |
785 | } | |
786 | ||
787 | static int amdgpu_pmops_runtime_idle(struct device *dev) | |
788 | { | |
789 | struct pci_dev *pdev = to_pci_dev(dev); | |
790 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
791 | struct drm_crtc *crtc; | |
792 | ||
793 | if (!amdgpu_device_is_px(drm_dev)) { | |
794 | pm_runtime_forbid(dev); | |
795 | return -EBUSY; | |
796 | } | |
797 | ||
798 | list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { | |
799 | if (crtc->enabled) { | |
800 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
801 | return -EBUSY; | |
802 | } | |
803 | } | |
804 | ||
805 | pm_runtime_mark_last_busy(dev); | |
806 | pm_runtime_autosuspend(dev); | |
807 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
808 | return 1; | |
809 | } | |
810 | ||
811 | long amdgpu_drm_ioctl(struct file *filp, | |
812 | unsigned int cmd, unsigned long arg) | |
813 | { | |
814 | struct drm_file *file_priv = filp->private_data; | |
815 | struct drm_device *dev; | |
816 | long ret; | |
817 | dev = file_priv->minor->dev; | |
818 | ret = pm_runtime_get_sync(dev->dev); | |
819 | if (ret < 0) | |
820 | return ret; | |
821 | ||
822 | ret = drm_ioctl(filp, cmd, arg); | |
823 | ||
824 | pm_runtime_mark_last_busy(dev->dev); | |
825 | pm_runtime_put_autosuspend(dev->dev); | |
826 | return ret; | |
827 | } | |
828 | ||
829 | static const struct dev_pm_ops amdgpu_pm_ops = { | |
830 | .suspend = amdgpu_pmops_suspend, | |
831 | .resume = amdgpu_pmops_resume, | |
832 | .freeze = amdgpu_pmops_freeze, | |
833 | .thaw = amdgpu_pmops_thaw, | |
74b0b157 | 834 | .poweroff = amdgpu_pmops_poweroff, |
835 | .restore = amdgpu_pmops_restore, | |
d38ceaf9 AD |
836 | .runtime_suspend = amdgpu_pmops_runtime_suspend, |
837 | .runtime_resume = amdgpu_pmops_runtime_resume, | |
838 | .runtime_idle = amdgpu_pmops_runtime_idle, | |
839 | }; | |
840 | ||
841 | static const struct file_operations amdgpu_driver_kms_fops = { | |
842 | .owner = THIS_MODULE, | |
843 | .open = drm_open, | |
844 | .release = drm_release, | |
845 | .unlocked_ioctl = amdgpu_drm_ioctl, | |
846 | .mmap = amdgpu_mmap, | |
847 | .poll = drm_poll, | |
848 | .read = drm_read, | |
849 | #ifdef CONFIG_COMPAT | |
850 | .compat_ioctl = amdgpu_kms_compat_ioctl, | |
851 | #endif | |
852 | }; | |
853 | ||
1bf6ad62 DV |
854 | static bool |
855 | amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, | |
856 | bool in_vblank_irq, int *vpos, int *hpos, | |
857 | ktime_t *stime, ktime_t *etime, | |
858 | const struct drm_display_mode *mode) | |
859 | { | |
aa8e286a SL |
860 | return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, |
861 | stime, etime, mode); | |
1bf6ad62 DV |
862 | } |
863 | ||
d38ceaf9 AD |
864 | static struct drm_driver kms_driver = { |
865 | .driver_features = | |
866 | DRIVER_USE_AGP | | |
867 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | | |
660e8558 | 868 | DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, |
d38ceaf9 AD |
869 | .load = amdgpu_driver_load_kms, |
870 | .open = amdgpu_driver_open_kms, | |
d38ceaf9 AD |
871 | .postclose = amdgpu_driver_postclose_kms, |
872 | .lastclose = amdgpu_driver_lastclose_kms, | |
d38ceaf9 AD |
873 | .unload = amdgpu_driver_unload_kms, |
874 | .get_vblank_counter = amdgpu_get_vblank_counter_kms, | |
875 | .enable_vblank = amdgpu_enable_vblank_kms, | |
876 | .disable_vblank = amdgpu_disable_vblank_kms, | |
1bf6ad62 DV |
877 | .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, |
878 | .get_scanout_position = amdgpu_get_crtc_scanout_position, | |
d38ceaf9 AD |
879 | .irq_handler = amdgpu_irq_handler, |
880 | .ioctls = amdgpu_ioctls_kms, | |
e7294dee | 881 | .gem_free_object_unlocked = amdgpu_gem_object_free, |
d38ceaf9 AD |
882 | .gem_open_object = amdgpu_gem_object_open, |
883 | .gem_close_object = amdgpu_gem_object_close, | |
884 | .dumb_create = amdgpu_mode_dumb_create, | |
885 | .dumb_map_offset = amdgpu_mode_dumb_mmap, | |
d38ceaf9 AD |
886 | .fops = &amdgpu_driver_kms_fops, |
887 | ||
888 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
889 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
890 | .gem_prime_export = amdgpu_gem_prime_export, | |
09052fc3 | 891 | .gem_prime_import = amdgpu_gem_prime_import, |
d38ceaf9 AD |
892 | .gem_prime_res_obj = amdgpu_gem_prime_res_obj, |
893 | .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, | |
894 | .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, | |
895 | .gem_prime_vmap = amdgpu_gem_prime_vmap, | |
896 | .gem_prime_vunmap = amdgpu_gem_prime_vunmap, | |
dfced2e4 | 897 | .gem_prime_mmap = amdgpu_gem_prime_mmap, |
d38ceaf9 AD |
898 | |
899 | .name = DRIVER_NAME, | |
900 | .desc = DRIVER_DESC, | |
901 | .date = DRIVER_DATE, | |
902 | .major = KMS_DRIVER_MAJOR, | |
903 | .minor = KMS_DRIVER_MINOR, | |
904 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
905 | }; | |
906 | ||
907 | static struct drm_driver *driver; | |
908 | static struct pci_driver *pdriver; | |
909 | ||
910 | static struct pci_driver amdgpu_kms_pci_driver = { | |
911 | .name = DRIVER_NAME, | |
912 | .id_table = pciidlist, | |
913 | .probe = amdgpu_pci_probe, | |
914 | .remove = amdgpu_pci_remove, | |
61e11306 | 915 | .shutdown = amdgpu_pci_shutdown, |
d38ceaf9 AD |
916 | .driver.pm = &amdgpu_pm_ops, |
917 | }; | |
918 | ||
d573de2d RZ |
919 | |
920 | ||
d38ceaf9 AD |
921 | static int __init amdgpu_init(void) |
922 | { | |
245ae5e9 CK |
923 | int r; |
924 | ||
c60e22f7 TI |
925 | if (vgacon_text_force()) { |
926 | DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); | |
927 | return -EINVAL; | |
928 | } | |
929 | ||
245ae5e9 CK |
930 | r = amdgpu_sync_init(); |
931 | if (r) | |
932 | goto error_sync; | |
933 | ||
934 | r = amdgpu_fence_slab_init(); | |
935 | if (r) | |
936 | goto error_fence; | |
937 | ||
d38ceaf9 AD |
938 | DRM_INFO("amdgpu kernel modesetting enabled.\n"); |
939 | driver = &kms_driver; | |
940 | pdriver = &amdgpu_kms_pci_driver; | |
d38ceaf9 AD |
941 | driver->num_ioctls = amdgpu_max_kms_ioctl; |
942 | amdgpu_register_atpx_handler(); | |
d38ceaf9 | 943 | /* let modprobe override vga console setting */ |
10631d72 | 944 | return pci_register_driver(pdriver); |
245ae5e9 | 945 | |
245ae5e9 CK |
946 | error_fence: |
947 | amdgpu_sync_fini(); | |
948 | ||
949 | error_sync: | |
950 | return r; | |
d38ceaf9 AD |
951 | } |
952 | ||
953 | static void __exit amdgpu_exit(void) | |
954 | { | |
130e0371 | 955 | amdgpu_amdkfd_fini(); |
10631d72 | 956 | pci_unregister_driver(pdriver); |
d38ceaf9 | 957 | amdgpu_unregister_atpx_handler(); |
257bf15a | 958 | amdgpu_sync_fini(); |
d573de2d | 959 | amdgpu_fence_slab_fini(); |
d38ceaf9 AD |
960 | } |
961 | ||
962 | module_init(amdgpu_init); | |
963 | module_exit(amdgpu_exit); | |
964 | ||
965 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
966 | MODULE_DESCRIPTION(DRIVER_DESC); | |
967 | MODULE_LICENSE("GPL and additional rights"); |