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drm/amdgpu: revert "Adjust removal control flow for smu v13_0_2"
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
d38ceaf9 25#include <drm/amdgpu_drm.h>
fdf2f6c5 26#include <drm/drm_drv.h>
8ab59da2 27#include <drm/drm_fbdev_generic.h>
d38ceaf9 28#include <drm/drm_gem.h>
8aba21b7 29#include <drm/drm_managed.h>
d38ceaf9 30#include <drm/drm_pciids.h>
fcd70cd3 31#include <drm/drm_probe_helper.h>
e2e42edf
SS		 32#include <drm/drm_vblank.h>
33
e9d1d2bb 34#include <linux/cc_platform.h>
f158936b 35#include <linux/dynamic_debug.h>
e2e42edf
SS		 36#include <linux/module.h>
37#include <linux/mmu_notifier.h>
38#include <linux/pm_runtime.h>
39#include <linux/suspend.h>
40#include <linux/vga_switcheroo.h>
d38ceaf9
AD		 41
42#include "amdgpu.h"
e2e42edf 43#include "amdgpu_amdkfd.h"
2fbd6f94 44#include "amdgpu_dma_buf.h"
e2e42edf 45#include "amdgpu_drv.h"
87444254 46#include "amdgpu_fdinfo.h"
e2e42edf 47#include "amdgpu_irq.h"
4e2abc19 48#include "amdgpu_psp.h"
7c6e68c7 49#include "amdgpu_ras.h"
04442bf7 50#include "amdgpu_reset.h"
e2e42edf
SS		 51#include "amdgpu_sched.h"
52#include "amdgpu_xgmi.h"
9938333a 53#include "../amdxcp/amdgpu_xcp_drv.h"
7c6e68c7 54
d38ceaf9
AD		 55/*
56 * KMS wrapper.
57 * - 3.0.0 - initial driver
6055f37a 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
60 * at the end of IBs.
d347ce66 61 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 63 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 65 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 66 * - 3.8.0 - Add support raster config init in the kernel
ef704318 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 70 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 71 * - 3.13.0 - Add PRT support
203eb0cb 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 73 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 74 * - 3.16.0 - Add reserved vmid support
68e2c5ff 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 76 * - 3.18.0 - Export gpu always on cu bitmap
33476319 77 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 78 * - 3.20.0 - Add support for local BOs
7ca24cf2 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 81 * - 3.23.0 - Add query for VRAM lost counter
f8e3e0ee 82 * - 3.24.0 - Add high priority compute support for gfx9
7b158d16 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
d240cd9e 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
c19a23fa 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
67dd1a36 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
41cca166 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
767e06a9 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
df8368be 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
1afeb314 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
635e2c5f 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
965ebe3d 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
815fb4c9 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
664fe85a 94 * - 3.36.0 - Allow reading more status registers on si/cik
ff532461 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
43c8546b 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
174b328b 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
16c642ec 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
b50368da 99 * - 3.41.0 - Add video codec query
915821a7 100 * - 3.42.0 - Add 16bpc fixed point display support
5c67ff3a 101 * - 3.43.0 - Add device hot plug/unplug support
f2e7d856 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
ded81d5b 103 * - 3.45.0 - Add context ioctl stable pstate interface
08cffb3e 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
465576ca
AD		 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106 * - 3.48.0 - Add IP discovery version info to HW INFO
cf5cf349
EQ		 107 * - 3.49.0 - Add gang submit into CS IOCTL
108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
e3e84b0a 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
b299221f
MO		 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
8a93c691 114 * 3.53.0 - Support for GFX11 CP GFX shadowing
489763af 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
7a41ed8b 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
6cb8e3ee 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode
91963397 118 * - 3.57.0 - Compute tunneling on GFX10+
d38ceaf9
AD		 119 */
120#define KMS_DRIVER_MAJOR 3
91963397 121#define KMS_DRIVER_MINOR 57
d38ceaf9
AD		 122#define KMS_DRIVER_PATCHLEVEL 0
123
887db1e4
AA		 124/*
125 * amdgpu.debug module options. Are all disabled by default
126 */
127enum AMDGPU_DEBUG_MASK {
128 AMDGPU_DEBUG_VM = BIT(0),
129 AMDGPU_DEBUG_LARGEBAR = BIT(1),
ffde7210 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
d20e1aec 131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
887db1e4
AA		 132};
133
0b04ea39 134unsigned int amdgpu_vram_limit = UINT_MAX;
87fb7833 135int amdgpu_vis_vram_limit;
83e74db6 136int amdgpu_gart_size = -1; /* auto */
36d38372 137int amdgpu_gtt_size = -1; /* auto */
95844d20 138int amdgpu_moverate = -1; /* auto */
d38ceaf9 139int amdgpu_audio = -1;
87fb7833
DV		 140int amdgpu_disp_priority;
141int amdgpu_hw_i2c;
d38ceaf9
AD		 142int amdgpu_pcie_gen2 = -1;
143int amdgpu_msi = -1;
f440ff44 144char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
d38ceaf9 145int amdgpu_dpm = -1;
e635ee07 146int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 147int amdgpu_aspm = -1;
148int amdgpu_runtime_pm = -1;
0b693f0b 149uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9 150int amdgpu_bapm = -1;
87fb7833 151int amdgpu_deep_color;
bab4fee7 152int amdgpu_vm_size = -1;
d07f14be 153int amdgpu_vm_fragment_size = -1;
d38ceaf9 154int amdgpu_vm_block_size = -1;
87fb7833 155int amdgpu_vm_fault_stop;
9a4b7d4c 156int amdgpu_vm_update_mode = -1;
87fb7833 157int amdgpu_exp_hw_support;
4562236b 158int amdgpu_dc = -1;
b70f014d 159int amdgpu_sched_jobs = 32;
4afcb303 160int amdgpu_sched_hw_submission = 2;
87fb7833
DV		 161uint amdgpu_pcie_gen_cap;
162uint amdgpu_pcie_lane_cap;
25faeddc 163u64 amdgpu_cg_mask = 0xffffffffffffffff;
0b693f0b
RZ		 164uint amdgpu_pg_mask = 0xffffffff;
165uint amdgpu_sdma_phase_quantum = 32;
e86c30e9
SS		 166char *amdgpu_disable_cu;
167char *amdgpu_virtual_display;
80e709ee 168bool enforce_isolation;
680602d6
KF		 169/*
170 * OverDrive(bit 14) disabled by default
171 * GFX DCS(bit 19) disabled by default
172 */
173uint amdgpu_pp_feature_mask = 0xfff7bfff;
87fb7833 174uint amdgpu_force_long_training;
e8835e0e 175int amdgpu_lbpw = -1;
4a75aefe 176int amdgpu_compute_multipipe = -1;
dcebf026 177int amdgpu_gpu_recovery = -1; /* auto */
87fb7833
DV		 178int amdgpu_emu_mode;
179uint amdgpu_smu_memory_pool_size;
8738a82b 180int amdgpu_smu_pptable_id = -1;
191a3c04
EQ		 181/*
182 * FBC (bit 0) disabled by default
183 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
184 * - With this, for multiple monitors in sync(e.g. with the same model),
185 * mclk switching will be allowed. And the mclk will be not foced to the
186 * highest. That helps saving some idle power.
187 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
188 * PSR (bit 3) disabled by default
a5148245 189 * EDP NO POWER SEQUENCING (bit 4) disabled by default
191a3c04
EQ		 190 */
191uint amdgpu_dc_feature_mask = 2;
87fb7833 192uint amdgpu_dc_debug_mask;
792a0cdd 193uint amdgpu_dc_visual_confirm;
5bfca069 194int amdgpu_async_gfx_ring = 1;
50a7c876 195int amdgpu_mcbp = -1;
63e2fef6 196int amdgpu_discovery = -1;
87fb7833 197int amdgpu_mes;
928fe236 198int amdgpu_mes_kiq;
d5cc02d9 199int amdgpu_noretry = -1;
4e66d7d2 200int amdgpu_force_asic_type = -1;
58aa7790 201int amdgpu_tmz = -1; /* auto */
273da6ff 202int amdgpu_reset_method = -1; /* auto */
a300de40 203int amdgpu_num_kcq = -1;
30d95a37 204int amdgpu_smartshift_bias;
158a05a0 205int amdgpu_use_xgmi_p2p = 1;
11eb648d 206int amdgpu_vcnfw_log;
bf0207e1 207int amdgpu_sg_display = -1; /* auto */
570de94b 208int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
eebb06d1 209int amdgpu_umsch_mm;
5dc270d3 210int amdgpu_seamless = -1; /* auto */
887db1e4 211uint amdgpu_debug_mask;
6ba5b613 212int amdgpu_agp = -1; /* auto */
b8b39de6 213int amdgpu_wbrf = -1;
7875a226 214
e3c1b071 215static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
216
f158936b
JC		 217DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
218 "DRM_UT_CORE",
219 "DRM_UT_DRIVER",
220 "DRM_UT_KMS",
221 "DRM_UT_PRIME",
222 "DRM_UT_ATOMIC",
223 "DRM_UT_VBL",
224 "DRM_UT_STATE",
225 "DRM_UT_LEASE",
226 "DRM_UT_DP",
227 "DRM_UT_DRMRES");
228
62d73fbc
EQ		 229struct amdgpu_mgpu_info mgpu_info = {
230 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
e3c1b071 231 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
232 mgpu_info.delayed_reset_work,
233 amdgpu_drv_delayed_reset_work_handler, 0),
62d73fbc 234};
1218252f 235int amdgpu_ras_enable = -1;
e53aec7e 236uint amdgpu_ras_mask = 0xffffffff;
acc0204c 237int amdgpu_bad_page_threshold = -1;
88f8575b
DL		 238struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
239 .timeout_fatal_disable = false,
28a5d7a5 240 .period = 0x0, /* default to 0x0 (timeout disable) */
88f8575b 241};
d38ceaf9 242
8405cf39
SJ		 243/**
244 * DOC: vramlimit (int)
245 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
246 */
d38ceaf9
AD		 247MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
248module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
249
8405cf39
SJ		 250/**
251 * DOC: vis_vramlimit (int)
252 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
253 */
218b5dcd
JB		 254MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
255module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
256
8405cf39
SJ		 257/**
258 * DOC: gartsize (uint)
570513ba
PM		 259 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
260 * The default is -1 (The size depends on asic).
8405cf39 261 */
570513ba 262MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 263module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 264
8405cf39
SJ		 265/**
266 * DOC: gttsize (int)
570513ba
PM		 267 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
268 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
8405cf39 269 */
570513ba 270MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
36d38372 271module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 272
8405cf39
SJ		 273/**
274 * DOC: moverate (int)
275 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
276 */
95844d20
MO		 277MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
278module_param_named(moverate, amdgpu_moverate, int, 0600);
279
8405cf39
SJ		 280/**
281 * DOC: audio (int)
282 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
283 */
d38ceaf9
AD		 284MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
285module_param_named(audio, amdgpu_audio, int, 0444);
286
8405cf39
SJ		 287/**
288 * DOC: disp_priority (int)
289 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
290 */
d38ceaf9
AD		 291MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
292module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
293
8405cf39
SJ		 294/**
295 * DOC: hw_i2c (int)
296 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
297 */
d38ceaf9
AD		 298MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
299module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
300
8405cf39
SJ		 301/**
302 * DOC: pcie_gen2 (int)
303 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
304 */
d38ceaf9
AD		 305MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
306module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
307
8405cf39
SJ		 308/**
309 * DOC: msi (int)
310 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
311 */
d38ceaf9
AD		 312MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
313module_param_named(msi, amdgpu_msi, int, 0444);
314
8405cf39 315/**
912dfc84
EQ		 316 * DOC: lockup_timeout (string)
317 * Set GPU scheduler timeout value in ms.
318 *
319 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
320 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
879e723d
AZ		 321 * to the default timeout.
322 *
323 * - With one value specified, the setting will apply to all non-compute jobs.
324 * - With multiple values specified, the first one will be for GFX.
325 * The second one is for Compute. The third and fourth ones are
326 * for SDMA and Video.
327 *
912dfc84 328 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
67387dfe 329 * jobs is 10000. The timeout for compute is 60000.
912dfc84 330 */
67387dfe 331MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
f9acfafc 332 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
bcccee89 333 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
912dfc84 334module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
d38ceaf9 335
8405cf39
SJ		 336/**
337 * DOC: dpm (int)
54b998ca 338 * Override for dynamic power management setting
5c9a6272 339 * (0 = disable, 1 = enable)
54b998ca 340 * The default is -1 (auto).
8405cf39 341 */
d38ceaf9
AD		 342MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
343module_param_named(dpm, amdgpu_dpm, int, 0444);
344
8405cf39
SJ		 345/**
346 * DOC: fw_load_type (int)
ddb267b6
YD		 347 * Set different firmware loading type for debugging, if supported.
348 * Set to 0 to force direct loading if supported by the ASIC. Set
349 * to -1 to select the default loading mode for the ASIC, as defined
350 * by the driver. The default is -1 (auto).
8405cf39 351 */
a76be7bb 352MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
e635ee07 353module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9 354
8405cf39
SJ		 355/**
356 * DOC: aspm (int)
357 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
358 */
d38ceaf9
AD		 359MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
360module_param_named(aspm, amdgpu_aspm, int, 0444);
361
8405cf39
SJ		 362/**
363 * DOC: runpm (int)
4d625a97
AD		 364 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
365 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
366 * Setting the value to 0 disables this functionality.
4d6fc55a 367 * Setting the value to -2 is auto enabled with power down when displays are attached.
8405cf39 368 */
4d6fc55a 369MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)");
d38ceaf9
AD		 370module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
371
8405cf39
SJ		 372/**
373 * DOC: ip_block_mask (uint)
374 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
375 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
376 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
377 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
378 */
d38ceaf9
AD		 379MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
380module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
381
8405cf39
SJ		 382/**
383 * DOC: bapm (int)
384 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
385 * The default -1 (auto, enabled)
386 */
d38ceaf9
AD		 387MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
388module_param_named(bapm, amdgpu_bapm, int, 0444);
389
8405cf39
SJ		 390/**
391 * DOC: deep_color (int)
392 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
393 */
d38ceaf9
AD		 394MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
395module_param_named(deep_color, amdgpu_deep_color, int, 0444);
396
8405cf39
SJ		 397/**
398 * DOC: vm_size (int)
399 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
400 */
ed885b21 401MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 402module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be 403
8405cf39
SJ		 404/**
405 * DOC: vm_fragment_size (int)
406 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
407 */
d07f14be
RH		 408MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
409module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9 410
8405cf39
SJ		 411/**
412 * DOC: vm_block_size (int)
413 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
414 */
d38ceaf9
AD		 415MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
416module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
417
8405cf39
SJ		 418/**
419 * DOC: vm_fault_stop (int)
420 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
421 */
d9c13156
CK		 422MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
423module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
424
8405cf39
SJ		 425/**
426 * DOC: vm_update_mode (int)
427 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
428 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
429 */
9a4b7d4c
HK		 430MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
431module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
432
8405cf39
SJ		 433/**
434 * DOC: exp_hw_support (int)
435 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
436 */
d38ceaf9
AD		 437MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
438module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
439
8405cf39
SJ		 440/**
441 * DOC: dc (int)
442 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
443 */
4562236b
HW		 444MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
445module_param_named(dc, amdgpu_dc, int, 0444);
446
8405cf39
SJ		 447/**
448 * DOC: sched_jobs (int)
449 * Override the max number of jobs supported in the sw queue. The default is 32.
450 */
b70f014d 451MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 452module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
453
8405cf39
SJ		 454/**
455 * DOC: sched_hw_submission (int)
456 * Override the max number of HW submissions. The default is 2.
457 */
4afcb303
JZ		 458MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
459module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
460
8405cf39 461/**
7427a7a0 462 * DOC: ppfeaturemask (hexint)
8405cf39
SJ		 463 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
464 * The default is the current set of stable power features.
465 */
5141e9d2 466MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
7427a7a0 467module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
3a74f6f2 468
367039bf
TY		 469/**
470 * DOC: forcelongtraining (uint)
471 * Force long memory training in resume.
472 * The default is zero, indicates short training in resume.
473 */
474MODULE_PARM_DESC(forcelongtraining, "force memory long training");
475module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
476
8405cf39
SJ		 477/**
478 * DOC: pcie_gen_cap (uint)
479 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
480 * The default is 0 (automatic for each asic).
481 */
cd474ba0
AD		 482MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
483module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
484
8405cf39
SJ		 485/**
486 * DOC: pcie_lane_cap (uint)
487 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
488 * The default is 0 (automatic for each asic).
489 */
cd474ba0
AD		 490MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
491module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
492
8405cf39 493/**
25faeddc 494 * DOC: cg_mask (ullong)
8405cf39 495 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
25faeddc 496 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
8405cf39 497 */
395d1fb9 498MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
25faeddc 499module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
395d1fb9 500
8405cf39
SJ		 501/**
502 * DOC: pg_mask (uint)
503 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
504 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
505 */
395d1fb9
NH		 506MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
507module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
508
8405cf39
SJ		 509/**
510 * DOC: sdma_phase_quantum (uint)
511 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
512 */
a667386c
FK		 513MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
514module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
515
8405cf39
SJ		 516/**
517 * DOC: disable_cu (charp)
518 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
519 */
6f8941a2
NH		 520MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
521module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
522
8405cf39
SJ		 523/**
524 * DOC: virtual_display (charp)
525 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
526 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
527 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
528 * device at 26:00.0. The default is NULL.
529 */
0f66356d
ED		 530MODULE_PARM_DESC(virtual_display,
531 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 532module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 533
8405cf39
SJ		 534/**
535 * DOC: lbpw (int)
536 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
537 */
e8835e0e
HZ		 538MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
539module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 540
4a75aefe
AR		 541MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
542module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
543
8405cf39
SJ		 544/**
545 * DOC: gpu_recovery (int)
546 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
547 */
06a2d7cc 548MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
dcebf026
AG		 549module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
550
8405cf39
SJ		 551/**
552 * DOC: emu_mode (int)
553 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
554 */
d869ae09 555MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
bfca0289
SL		 556module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
557
1218252f 558/**
2f3940e9 559 * DOC: ras_enable (int)
1218252f 560 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
561 */
2f3940e9 562MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
1218252f 563module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
564
565/**
2f3940e9 566 * DOC: ras_mask (uint)
1218252f 567 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
568 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
569 */
2f3940e9 570MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
1218252f 571module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
572
88f8575b
DL		 573/**
574 * DOC: timeout_fatal_disable (bool)
575 * Disable Watchdog timeout fatal error event
576 */
577MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
578module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
579
580/**
581 * DOC: timeout_period (uint)
582 * Modify the watchdog timeout max_cycles as (1 << period)
583 */
28a5d7a5 584MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
88f8575b
DL		 585module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
586
8405cf39
SJ		 587/**
588 * DOC: si_support (int)
589 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
590 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
591 * otherwise using amdgpu driver.
592 */
6dd13096 593#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56 594
b25b3599 595#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
b679566b 596int amdgpu_si_support;
6dd13096 597MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 598#else
599int amdgpu_si_support = 1;
600MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
601#endif
602
6dd13096
FK		 603module_param_named(si_support, amdgpu_si_support, int, 0444);
604#endif
605
8405cf39
SJ		 606/**
607 * DOC: cik_support (int)
608 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
609 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
610 * otherwise using amdgpu driver.
611 */
7df28986 612#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56 613
b25b3599 614#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
b679566b 615int amdgpu_cik_support;
2b059658 616MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 617#else
618int amdgpu_cik_support = 1;
619MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
620#endif
621
7df28986
FK		 622module_param_named(cik_support, amdgpu_cik_support, int, 0444);
623#endif
624
8405cf39
SJ		 625/**
626 * DOC: smu_memory_pool_size (uint)
627 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
628 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
629 */
7951e376 630MODULE_PARM_DESC(smu_memory_pool_size,
f9acfafc 631 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
7951e376
RZ		 632module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
633
51bcce46
HZ		 634/**
635 * DOC: async_gfx_ring (int)
636 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
637 */
638MODULE_PARM_DESC(async_gfx_ring,
5bfca069 639 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
51bcce46
HZ		 640module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
641
40562787
AD		 642/**
643 * DOC: mcbp (int)
50a7c876 644 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
40562787 645 */
b239c017 646MODULE_PARM_DESC(mcbp,
50a7c876 647 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
b239c017
JX		 648module_param_named(mcbp, amdgpu_mcbp, int, 0444);
649
40562787
AD		 650/**
651 * DOC: discovery (int)
652 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
a79d3709 653 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
40562787 654 */
a190d1c7
XY		 655MODULE_PARM_DESC(discovery,
656 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
657module_param_named(discovery, amdgpu_discovery, int, 0444);
658
40562787
AD		 659/**
660 * DOC: mes (int)
661 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
662 * (0 = disabled (default), 1 = enabled)
663 */
38487284
JX		 664MODULE_PARM_DESC(mes,
665 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
666module_param_named(mes, amdgpu_mes, int, 0444);
667
928fe236
JX		 668/**
669 * DOC: mes_kiq (int)
670 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
671 * (0 = disabled (default), 1 = enabled)
672 */
673MODULE_PARM_DESC(mes_kiq,
674 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
675module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
676
d5cc02d9
AD		 677/**
678 * DOC: noretry (int)
9705c85f
FK		 679 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
680 * do not support per-process XNACK this also disables retry page faults.
d5cc02d9
AD		 681 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
682 */
75ee6487 683MODULE_PARM_DESC(noretry,
d5cc02d9 684 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
75ee6487
FK		 685module_param_named(noretry, amdgpu_noretry, int, 0644);
686
4e66d7d2
YZ		 687/**
688 * DOC: force_asic_type (int)
689 * A non negative value used to specify the asic type for all supported GPUs.
690 */
691MODULE_PARM_DESC(force_asic_type,
692 "A non negative value used to specify the asic type for all supported GPUs");
693module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
694
158a05a0
AS		 695/**
696 * DOC: use_xgmi_p2p (int)
697 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
698 */
699MODULE_PARM_DESC(use_xgmi_p2p,
700 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
701module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
4e66d7d2
YZ		 702
703
2690262e 704#ifdef CONFIG_HSA_AMD
521fb7d0
AL		 705/**
706 * DOC: sched_policy (int)
707 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
708 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
709 * assigns queues to HQDs.
710 */
2690262e 711int sched_policy = KFD_SCHED_POLICY_HWS;
521fb7d0
AL		 712module_param(sched_policy, int, 0444);
713MODULE_PARM_DESC(sched_policy,
714 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
715
716/**
717 * DOC: hws_max_conc_proc (int)
718 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
719 * number of VMIDs assigned to the HWS, which is also the default.
720 */
b7dfbd2e 721int hws_max_conc_proc = -1;
521fb7d0
AL		 722module_param(hws_max_conc_proc, int, 0444);
723MODULE_PARM_DESC(hws_max_conc_proc,
724 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
725
726/**
727 * DOC: cwsr_enable (int)
728 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
729 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
730 * disables it.
731 */
2690262e 732int cwsr_enable = 1;
521fb7d0
AL		 733module_param(cwsr_enable, int, 0444);
734MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
735
736/**
737 * DOC: max_num_of_queues_per_device (int)
738 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
739 * is 4096.
740 */
2690262e 741int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
521fb7d0
AL		 742module_param(max_num_of_queues_per_device, int, 0444);
743MODULE_PARM_DESC(max_num_of_queues_per_device,
744 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
745
746/**
747 * DOC: send_sigterm (int)
748 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
749 * but just print errors on dmesg. Setting 1 enables sending sigterm.
750 */
2690262e 751int send_sigterm;
521fb7d0
AL		 752module_param(send_sigterm, int, 0444);
753MODULE_PARM_DESC(send_sigterm,
754 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
755
521fb7d0
AL		 756/**
757 * DOC: halt_if_hws_hang (int)
758 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
759 * Setting 1 enables halt on hang.
760 */
2690262e 761int halt_if_hws_hang;
521fb7d0
AL		 762module_param(halt_if_hws_hang, int, 0644);
763MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
29e76462
OZ		 764
765/**
766 * DOC: hws_gws_support(bool)
29633d0e
JG		 767 * Assume that HWS supports GWS barriers regardless of what firmware version
768 * check says. Default value: false (rely on MEC2 firmware version check).
29e76462
OZ		 769 */
770bool hws_gws_support;
771module_param(hws_gws_support, bool, 0444);
29633d0e 772MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
14328aa5
PC		 773
774/**
f9acfafc
SS		 775 * DOC: queue_preemption_timeout_ms (int)
776 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
777 */
f51af435 778int queue_preemption_timeout_ms = 9000;
14328aa5
PC		 779module_param(queue_preemption_timeout_ms, int, 0644);
780MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
b2057956
FK		 781
782/**
783 * DOC: debug_evictions(bool)
784 * Enable extra debug messages to help determine the cause of evictions
785 */
786bool debug_evictions;
787module_param(debug_evictions, bool, 0644);
788MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
b80f050f
PY		 789
790/**
791 * DOC: no_system_mem_limit(bool)
792 * Disable system memory limit, to support multiple process shared memory
793 */
794bool no_system_mem_limit;
795module_param(no_system_mem_limit, bool, 0644);
796MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
797
6d909c5d
OZ		 798/**
799 * DOC: no_queue_eviction_on_vm_fault (int)
800 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
801 */
120ceaf7 802int amdgpu_no_queue_eviction_on_vm_fault;
6d909c5d
OZ		 803MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
804module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
2690262e 805#endif
521fb7d0 806
895797d9 807/**
76eb9c95 808 * DOC: mtype_local (int)
895797d9 809 */
76eb9c95 810int amdgpu_mtype_local;
b9cbd510 811MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
76eb9c95 812module_param_named(mtype_local, amdgpu_mtype_local, int, 0444);
895797d9 813
08a2fd23
RE		 814/**
815 * DOC: pcie_p2p (bool)
816 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
817 */
818#ifdef CONFIG_HSA_AMD_P2P
819bool pcie_p2p = true;
820module_param(pcie_p2p, bool, 0444);
821MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
822#endif
823
7875a226
AD		 824/**
825 * DOC: dcfeaturemask (uint)
826 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
827 * The default is the current set of stable display features.
828 */
829MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
830module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
831
8a791dab
HW		 832/**
833 * DOC: dcdebugmask (uint)
834 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
835 */
836MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
837module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
838
792a0cdd
LL		 839MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
840module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
841
ad4de27f
NK		 842/**
843 * DOC: abmlevel (uint)
844 * Override the default ABM (Adaptive Backlight Management) level used for DC
845 * enabled hardware. Requires DMCU to be supported and loaded.
846 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
847 * default. Values 1-4 control the maximum allowable brightness reduction via
848 * the ABM algorithm, with 1 being the least reduction and 4 being the most
849 * reduction.
850 *
851 * Defaults to 0, or disabled. Userspace can still override this level later
852 * after boot.
853 */
87fb7833 854uint amdgpu_dm_abm_level;
ad4de27f
NK		 855MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
856module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
857
7a46f05e
TI		 858int amdgpu_backlight = -1;
859MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
860module_param_named(backlight, amdgpu_backlight, bint, 0444);
861
d7ccb38d
HR		 862/**
863 * DOC: tmz (int)
864 * Trusted Memory Zone (TMZ) is a method to protect data being written
865 * to or read from memory.
866 *
867 * The default value: 0 (off). TODO: change to auto till it is completed.
868 */
58aa7790 869MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
d7ccb38d
HR		 870module_param_named(tmz, amdgpu_tmz, int, 0444);
871
273da6ff
WS		 872/**
873 * DOC: reset_method (int)
2656fd23 874 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
273da6ff 875 */
2656fd23 876MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
273da6ff
WS		 877module_param_named(reset_method, amdgpu_reset_method, int, 0444);
878
acc0204c 879/**
e4e6a589
LT		 880 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
881 * threshold value of faulty pages detected by RAS ECC, which may
882 * result in the GPU entering bad status when the number of total
883 * faulty pages by ECC exceeds the threshold value.
acc0204c 884 */
f3cbe70e 885MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
acc0204c
GC		 886module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
887
a300de40
ML		 888MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
889module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
890
11eb648d
RD		 891/**
892 * DOC: vcnfw_log (int)
893 * Enable vcnfw log output for debugging, the default is disabled.
894 */
895MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
896module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
897
bf0207e1
AD		 898/**
899 * DOC: sg_display (int)
900 * Disable S/G (scatter/gather) display (i.e., display from system memory).
901 * This option is only relevant on APUs. Set this option to 0 to disable
902 * S/G display if you experience flickering or other issues under memory
903 * pressure and report the issue.
904 */
905MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
906module_param_named(sg_display, amdgpu_sg_display, int, 0444);
907
eebb06d1
LY		 908/**
909 * DOC: umsch_mm (int)
910 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
911 * (0 = disabled (default), 1 = enabled)
912 */
913MODULE_PARM_DESC(umsch_mm,
914 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
915module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
916
8738a82b
LL		 917/**
918 * DOC: smu_pptable_id (int)
919 * Used to override pptable id. id = 0 use VBIOS pptable.
920 * id > 0 use the soft pptable with specicfied id.
921 */
922MODULE_PARM_DESC(smu_pptable_id,
923 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
924module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
925
0fa49d10
SZ		 926/**
927 * DOC: partition_mode (int)
928 * Used to override the default SPX mode.
929 */
570de94b
LL		 930MODULE_PARM_DESC(
931 user_partt_mode,
932 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
933 0 = AMDGPU_SPX_PARTITION_MODE, \
0fa49d10
SZ		 934 1 = AMDGPU_DPX_PARTITION_MODE, \
935 2 = AMDGPU_TPX_PARTITION_MODE, \
936 3 = AMDGPU_QPX_PARTITION_MODE, \
937 4 = AMDGPU_CPX_PARTITION_MODE)");
938module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
939
80e709ee
CL		 940
941/**
942 * DOC: enforce_isolation (bool)
943 * enforce process isolation between graphics and compute via using the same reserved vmid.
944 */
945module_param(enforce_isolation, bool, 0444);
946MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on");
947
5dc270d3
ML		 948/**
949 * DOC: seamless (int)
950 * Seamless boot will keep the image on the screen during the boot process.
951 */
952MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
953module_param_named(seamless, amdgpu_seamless, int, 0444);
954
887db1e4
AA		 955/**
956 * DOC: debug_mask (uint)
957 * Debug options for amdgpu, work as a binary mask with the following options:
958 *
959 * - 0x1: Debug VM handling
960 * - 0x2: Enable simulating large-bar capability on non-large bar system. This
961 * limits the VRAM size reported to ROCm applications to the visible
962 * size, usually 256MB.
ffde7210 963 * - 0x4: Disable GPU soft recovery, always do a full reset
887db1e4
AA		 964 */
965MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
966module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
967
6ba5b613
AD		 968/**
969 * DOC: agp (int)
970 * Enable the AGP aperture. This provides an aperture in the GPU's internal
971 * address space for direct access to system memory. Note that these accesses
972 * are non-snooped, so they are only used for access to uncached memory.
973 */
974MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
975module_param_named(agp, amdgpu_agp, int, 0444);
976
b8b39de6
EQ		 977/**
978 * DOC: wbrf (int)
979 * Enable Wifi RFI interference mitigation feature.
980 * Due to electrical and mechanical constraints there may be likely interference of
981 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
982 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,
983 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
984 * on active list of frequencies in-use (to be avoided) as part of initial setting or
985 * P-state transition. However, there may be potential performance impact with this
986 * feature enabled.
987 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
988 */
989MODULE_PARM_DESC(wbrf,
990 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
991module_param_named(wbrf, amdgpu_wbrf, int, 0444);
992
bdbeb0dd
AD		 993/* These devices are not supported by amdgpu.
994 * They are supported by the mach64, r128, radeon drivers
995 */
996static const u16 amdgpu_unsupported_pciidlist[] = {
997 /* mach64 */
998 0x4354,
999 0x4358,
1000 0x4554,
1001 0x4742,
1002 0x4744,
1003 0x4749,
1004 0x474C,
1005 0x474D,
1006 0x474E,
1007 0x474F,
1008 0x4750,
1009 0x4751,
1010 0x4752,
1011 0x4753,
1012 0x4754,
1013 0x4755,
1014 0x4756,
1015 0x4757,
1016 0x4758,
1017 0x4759,
1018 0x475A,
1019 0x4C42,
1020 0x4C44,
1021 0x4C47,
1022 0x4C49,
1023 0x4C4D,
1024 0x4C4E,
1025 0x4C50,
1026 0x4C51,
1027 0x4C52,
1028 0x4C53,
1029 0x5654,
1030 0x5655,
1031 0x5656,
1032 /* r128 */
1033 0x4c45,
1034 0x4c46,
1035 0x4d46,
1036 0x4d4c,
1037 0x5041,
1038 0x5042,
1039 0x5043,
1040 0x5044,
1041 0x5045,
1042 0x5046,
1043 0x5047,
1044 0x5048,
1045 0x5049,
1046 0x504A,
1047 0x504B,
1048 0x504C,
1049 0x504D,
1050 0x504E,
1051 0x504F,
1052 0x5050,
1053 0x5051,
1054 0x5052,
1055 0x5053,
1056 0x5054,
1057 0x5055,
1058 0x5056,
1059 0x5057,
1060 0x5058,
1061 0x5245,
1062 0x5246,
1063 0x5247,
1064 0x524b,
1065 0x524c,
1066 0x534d,
1067 0x5446,
1068 0x544C,
1069 0x5452,
1070 /* radeon */
1071 0x3150,
1072 0x3151,
1073 0x3152,
1074 0x3154,
1075 0x3155,
1076 0x3E50,
1077 0x3E54,
1078 0x4136,
1079 0x4137,
1080 0x4144,
1081 0x4145,
1082 0x4146,
1083 0x4147,
1084 0x4148,
1085 0x4149,
1086 0x414A,
1087 0x414B,
1088 0x4150,
1089 0x4151,
1090 0x4152,
1091 0x4153,
1092 0x4154,
1093 0x4155,
1094 0x4156,
1095 0x4237,
1096 0x4242,
1097 0x4336,
1098 0x4337,
1099 0x4437,
1100 0x4966,
1101 0x4967,
1102 0x4A48,
1103 0x4A49,
1104 0x4A4A,
1105 0x4A4B,
1106 0x4A4C,
1107 0x4A4D,
1108 0x4A4E,
1109 0x4A4F,
1110 0x4A50,
1111 0x4A54,
1112 0x4B48,
1113 0x4B49,
1114 0x4B4A,
1115 0x4B4B,
1116 0x4B4C,
1117 0x4C57,
1118 0x4C58,
1119 0x4C59,
1120 0x4C5A,
1121 0x4C64,
1122 0x4C66,
1123 0x4C67,
1124 0x4E44,
1125 0x4E45,
1126 0x4E46,
1127 0x4E47,
1128 0x4E48,
1129 0x4E49,
1130 0x4E4A,
1131 0x4E4B,
1132 0x4E50,
1133 0x4E51,
1134 0x4E52,
1135 0x4E53,
1136 0x4E54,
1137 0x4E56,
1138 0x5144,
1139 0x5145,
1140 0x5146,
1141 0x5147,
1142 0x5148,
1143 0x514C,
1144 0x514D,
1145 0x5157,
1146 0x5158,
1147 0x5159,
1148 0x515A,
1149 0x515E,
1150 0x5460,
1151 0x5462,
1152 0x5464,
1153 0x5548,
1154 0x5549,
1155 0x554A,
1156 0x554B,
1157 0x554C,
1158 0x554D,
1159 0x554E,
1160 0x554F,
1161 0x5550,
1162 0x5551,
1163 0x5552,
1164 0x5554,
1165 0x564A,
1166 0x564B,
1167 0x564F,
1168 0x5652,
1169 0x5653,
1170 0x5657,
1171 0x5834,
1172 0x5835,
1173 0x5954,
1174 0x5955,
1175 0x5974,
1176 0x5975,
1177 0x5960,
1178 0x5961,
1179 0x5962,
1180 0x5964,
1181 0x5965,
1182 0x5969,
1183 0x5a41,
1184 0x5a42,
1185 0x5a61,
1186 0x5a62,
1187 0x5b60,
1188 0x5b62,
1189 0x5b63,
1190 0x5b64,
1191 0x5b65,
1192 0x5c61,
1193 0x5c63,
1194 0x5d48,
1195 0x5d49,
1196 0x5d4a,
1197 0x5d4c,
1198 0x5d4d,
1199 0x5d4e,
1200 0x5d4f,
1201 0x5d50,
1202 0x5d52,
1203 0x5d57,
1204 0x5e48,
1205 0x5e4a,
1206 0x5e4b,
1207 0x5e4c,
1208 0x5e4d,
1209 0x5e4f,
1210 0x6700,
1211 0x6701,
1212 0x6702,
1213 0x6703,
1214 0x6704,
1215 0x6705,
1216 0x6706,
1217 0x6707,
1218 0x6708,
1219 0x6709,
1220 0x6718,
1221 0x6719,
1222 0x671c,
1223 0x671d,
1224 0x671f,
1225 0x6720,
1226 0x6721,
1227 0x6722,
1228 0x6723,
1229 0x6724,
1230 0x6725,
1231 0x6726,
1232 0x6727,
1233 0x6728,
1234 0x6729,
1235 0x6738,
1236 0x6739,
1237 0x673e,
1238 0x6740,
1239 0x6741,
1240 0x6742,
1241 0x6743,
1242 0x6744,
1243 0x6745,
1244 0x6746,
1245 0x6747,
1246 0x6748,
1247 0x6749,
1248 0x674A,
1249 0x6750,
1250 0x6751,
1251 0x6758,
1252 0x6759,
1253 0x675B,
1254 0x675D,
1255 0x675F,
1256 0x6760,
1257 0x6761,
1258 0x6762,
1259 0x6763,
1260 0x6764,
1261 0x6765,
1262 0x6766,
1263 0x6767,
1264 0x6768,
1265 0x6770,
1266 0x6771,
1267 0x6772,
1268 0x6778,
1269 0x6779,
1270 0x677B,
1271 0x6840,
1272 0x6841,
1273 0x6842,
1274 0x6843,
1275 0x6849,
1276 0x684C,
1277 0x6850,
1278 0x6858,
1279 0x6859,
1280 0x6880,
1281 0x6888,
1282 0x6889,
1283 0x688A,
1284 0x688C,
1285 0x688D,
1286 0x6898,
1287 0x6899,
1288 0x689b,
1289 0x689c,
1290 0x689d,
1291 0x689e,
1292 0x68a0,
1293 0x68a1,
1294 0x68a8,
1295 0x68a9,
1296 0x68b0,
1297 0x68b8,
1298 0x68b9,
1299 0x68ba,
1300 0x68be,
1301 0x68bf,
1302 0x68c0,
1303 0x68c1,
1304 0x68c7,
1305 0x68c8,
1306 0x68c9,
1307 0x68d8,
1308 0x68d9,
1309 0x68da,
1310 0x68de,
1311 0x68e0,
1312 0x68e1,
1313 0x68e4,
1314 0x68e5,
1315 0x68e8,
1316 0x68e9,
1317 0x68f1,
1318 0x68f2,
1319 0x68f8,
1320 0x68f9,
1321 0x68fa,
1322 0x68fe,
1323 0x7100,
1324 0x7101,
1325 0x7102,
1326 0x7103,
1327 0x7104,
1328 0x7105,
1329 0x7106,
1330 0x7108,
1331 0x7109,
1332 0x710A,
1333 0x710B,
1334 0x710C,
1335 0x710E,
1336 0x710F,
1337 0x7140,
1338 0x7141,
1339 0x7142,
1340 0x7143,
1341 0x7144,
1342 0x7145,
1343 0x7146,
1344 0x7147,
1345 0x7149,
1346 0x714A,
1347 0x714B,
1348 0x714C,
1349 0x714D,
1350 0x714E,
1351 0x714F,
1352 0x7151,
1353 0x7152,
1354 0x7153,
1355 0x715E,
1356 0x715F,
1357 0x7180,
1358 0x7181,
1359 0x7183,
1360 0x7186,
1361 0x7187,
1362 0x7188,
1363 0x718A,
1364 0x718B,
1365 0x718C,
1366 0x718D,
1367 0x718F,
1368 0x7193,
1369 0x7196,
1370 0x719B,
1371 0x719F,
1372 0x71C0,
1373 0x71C1,
1374 0x71C2,
1375 0x71C3,
1376 0x71C4,
1377 0x71C5,
1378 0x71C6,
1379 0x71C7,
1380 0x71CD,
1381 0x71CE,
1382 0x71D2,
1383 0x71D4,
1384 0x71D5,
1385 0x71D6,
1386 0x71DA,
1387 0x71DE,
1388 0x7200,
1389 0x7210,
1390 0x7211,
1391 0x7240,
1392 0x7243,
1393 0x7244,
1394 0x7245,
1395 0x7246,
1396 0x7247,
1397 0x7248,
1398 0x7249,
1399 0x724A,
1400 0x724B,
1401 0x724C,
1402 0x724D,
1403 0x724E,
1404 0x724F,
1405 0x7280,
1406 0x7281,
1407 0x7283,
1408 0x7284,
1409 0x7287,
1410 0x7288,
1411 0x7289,
1412 0x728B,
1413 0x728C,
1414 0x7290,
1415 0x7291,
1416 0x7293,
1417 0x7297,
1418 0x7834,
1419 0x7835,
1420 0x791e,
1421 0x791f,
1422 0x793f,
1423 0x7941,
1424 0x7942,
1425 0x796c,
1426 0x796d,
1427 0x796e,
1428 0x796f,
1429 0x9400,
1430 0x9401,
1431 0x9402,
1432 0x9403,
1433 0x9405,
1434 0x940A,
1435 0x940B,
1436 0x940F,
1437 0x94A0,
1438 0x94A1,
1439 0x94A3,
1440 0x94B1,
1441 0x94B3,
1442 0x94B4,
1443 0x94B5,
1444 0x94B9,
1445 0x9440,
1446 0x9441,
1447 0x9442,
1448 0x9443,
1449 0x9444,
1450 0x9446,
1451 0x944A,
1452 0x944B,
1453 0x944C,
1454 0x944E,
1455 0x9450,
1456 0x9452,
1457 0x9456,
1458 0x945A,
1459 0x945B,
1460 0x945E,
1461 0x9460,
1462 0x9462,
1463 0x946A,
1464 0x946B,
1465 0x947A,
1466 0x947B,
1467 0x9480,
1468 0x9487,
1469 0x9488,
1470 0x9489,
1471 0x948A,
1472 0x948F,
1473 0x9490,
1474 0x9491,
1475 0x9495,
1476 0x9498,
1477 0x949C,
1478 0x949E,
1479 0x949F,
1480 0x94C0,
1481 0x94C1,
1482 0x94C3,
1483 0x94C4,
1484 0x94C5,
1485 0x94C6,
1486 0x94C7,
1487 0x94C8,
1488 0x94C9,
1489 0x94CB,
1490 0x94CC,
1491 0x94CD,
1492 0x9500,
1493 0x9501,
1494 0x9504,
1495 0x9505,
1496 0x9506,
1497 0x9507,
1498 0x9508,
1499 0x9509,
1500 0x950F,
1501 0x9511,
1502 0x9515,
1503 0x9517,
1504 0x9519,
1505 0x9540,
1506 0x9541,
1507 0x9542,
1508 0x954E,
1509 0x954F,
1510 0x9552,
1511 0x9553,
1512 0x9555,
1513 0x9557,
1514 0x955f,
1515 0x9580,
1516 0x9581,
1517 0x9583,
1518 0x9586,
1519 0x9587,
1520 0x9588,
1521 0x9589,
1522 0x958A,
1523 0x958B,
1524 0x958C,
1525 0x958D,
1526 0x958E,
1527 0x958F,
1528 0x9590,
1529 0x9591,
1530 0x9593,
1531 0x9595,
1532 0x9596,
1533 0x9597,
1534 0x9598,
1535 0x9599,
1536 0x959B,
1537 0x95C0,
1538 0x95C2,
1539 0x95C4,
1540 0x95C5,
1541 0x95C6,
1542 0x95C7,
1543 0x95C9,
1544 0x95CC,
1545 0x95CD,
1546 0x95CE,
1547 0x95CF,
1548 0x9610,
1549 0x9611,
1550 0x9612,
1551 0x9613,
1552 0x9614,
1553 0x9615,
1554 0x9616,
1555 0x9640,
1556 0x9641,
1557 0x9642,
1558 0x9643,
1559 0x9644,
1560 0x9645,
1561 0x9647,
1562 0x9648,
1563 0x9649,
1564 0x964a,
1565 0x964b,
1566 0x964c,
1567 0x964e,
1568 0x964f,
1569 0x9710,
1570 0x9711,
1571 0x9712,
1572 0x9713,
1573 0x9714,
1574 0x9715,
1575 0x9802,
1576 0x9803,
1577 0x9804,
1578 0x9805,
1579 0x9806,
1580 0x9807,
1581 0x9808,
1582 0x9809,
1583 0x980A,
1584 0x9900,
1585 0x9901,
1586 0x9903,
1587 0x9904,
1588 0x9905,
1589 0x9906,
1590 0x9907,
1591 0x9908,
1592 0x9909,
1593 0x990A,
1594 0x990B,
1595 0x990C,
1596 0x990D,
1597 0x990E,
1598 0x990F,
1599 0x9910,
1600 0x9913,
1601 0x9917,
1602 0x9918,
1603 0x9919,
1604 0x9990,
1605 0x9991,
1606 0x9992,
1607 0x9993,
1608 0x9994,
1609 0x9995,
1610 0x9996,
1611 0x9997,
1612 0x9998,
1613 0x9999,
1614 0x999A,
1615 0x999B,
1616 0x999C,
1617 0x999D,
1618 0x99A0,
1619 0x99A2,
1620 0x99A4,
9e5a14bc
AD		 1621 /* radeon secondary ids */
1622 0x3171,
1623 0x3e70,
1624 0x4164,
1625 0x4165,
1626 0x4166,
1627 0x4168,
1628 0x4170,
1629 0x4171,
1630 0x4172,
1631 0x4173,
1632 0x496e,
1633 0x4a69,
1634 0x4a6a,
1635 0x4a6b,
1636 0x4a70,
1637 0x4a74,
1638 0x4b69,
1639 0x4b6b,
1640 0x4b6c,
1641 0x4c6e,
1642 0x4e64,
1643 0x4e65,
1644 0x4e66,
1645 0x4e67,
1646 0x4e68,
1647 0x4e69,
1648 0x4e6a,
1649 0x4e71,
1650 0x4f73,
1651 0x5569,
1652 0x556b,
1653 0x556d,
1654 0x556f,
1655 0x5571,
1656 0x5854,
1657 0x5874,
1658 0x5940,
1659 0x5941,
c1ac2ea8 1660 0x5b70,
9e5a14bc
AD		 1661 0x5b72,
1662 0x5b73,
1663 0x5b74,
1664 0x5b75,
1665 0x5d44,
1666 0x5d45,
1667 0x5d6d,
1668 0x5d6f,
1669 0x5d72,
1670 0x5d77,
1671 0x5e6b,
1672 0x5e6d,
1673 0x7120,
1674 0x7124,
1675 0x7129,
1676 0x712e,
1677 0x712f,
1678 0x7162,
1679 0x7163,
1680 0x7166,
1681 0x7167,
1682 0x7172,
1683 0x7173,
1684 0x71a0,
1685 0x71a1,
1686 0x71a3,
1687 0x71a7,
1688 0x71bb,
1689 0x71e0,
1690 0x71e1,
1691 0x71e2,
1692 0x71e6,
1693 0x71e7,
1694 0x71f2,
1695 0x7269,
1696 0x726b,
1697 0x726e,
1698 0x72a0,
1699 0x72a8,
1700 0x72b1,
1701 0x72b3,
1702 0x793f,
bdbeb0dd
AD		 1703};
1704
f498d9ed 1705static const struct pci_device_id pciidlist[] = {
47fc644f 1706#ifdef CONFIG_DRM_AMDGPU_SI
78fbb685
KW		 1707 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1708 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1709 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1710 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1711 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1712 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1713 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1714 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1715 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1716 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1717 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1718 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1719 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1720 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1721 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1722 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1723 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1724 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1725 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1726 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1727 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1728 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1729 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1730 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1731 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1732 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1733 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1734 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1735 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1736 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1737 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1738 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1739 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1740 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1741 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1742 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1743 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1744 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1745 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1746 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1747 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1748 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1749 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1750 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1751 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1752 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1753 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1754 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1755 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1756 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1757 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1758 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1759 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1760 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1761 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1762 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1763 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1764 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1765 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1766 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1767 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1768 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1769 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1770 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1771 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1772 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1773 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1774 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1775 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1776 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1777 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1778 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1779#endif
89330c39
AD		 1780#ifdef CONFIG_DRM_AMDGPU_CIK
1781 /* Kaveri */
2f7d10b3
JZ		 1782 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1783 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1784 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1785 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1786 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1787 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1788 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1789 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1790 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1791 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1792 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1793 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1794 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1795 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1796 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1797 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1798 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1799 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1800 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1801 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1802 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1803 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 1804 /* Bonaire */
2f7d10b3
JZ		 1805 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1806 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1807 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1808 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 1809 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1810 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1811 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1812 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1813 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1814 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 1815 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 1816 /* Hawaii */
1817 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1818 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1819 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1820 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1821 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1822 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1823 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1824 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1825 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1826 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1827 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1828 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1829 /* Kabini */
2f7d10b3
JZ		 1830 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1831 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1832 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1833 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1834 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1835 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1836 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1837 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1838 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1839 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1840 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1841 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1842 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1843 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1844 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1845 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 1846 /* mullins */
2f7d10b3
JZ		 1847 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1848 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1849 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1850 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1851 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1852 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1853 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1854 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1855 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1856 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1857 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1858 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1859 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1860 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1861 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1862 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 1863#endif
1256a8b8 1864 /* topaz */
dba280b2
AD		 1865 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1866 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1867 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1868 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1869 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 1870 /* tonga */
1871 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1872 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1873 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1874 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1875 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1876 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1877 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1878 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1879 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 1880 /* fiji */
1881 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 1882 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 1883 /* carrizo */
2f7d10b3
JZ		 1884 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1885 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1886 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1887 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1888 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 1889 /* stoney */
1890 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 1891 /* Polaris11 */
1892 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1893 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1894 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1895 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1896 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1897 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 1898 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1899 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1900 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 1901 /* Polaris10 */
1902 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1903 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1904 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1905 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1906 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 1907 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 1908 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1909 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1910 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1911 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1912 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1913 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
30f3984e 1914 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 1915 /* Polaris12 */
1916 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1917 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1918 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1919 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1920 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 1921 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 1922 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 1923 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
e9307932
LL		 1924 /* VEGAM */
1925 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1926 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
f6653a0e 1927 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
ca2f1cca 1928 /* Vega 10 */
dfbf0c14
AD		 1929 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1930 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1931 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1932 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1933 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1934 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1935 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1936 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1937 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1938 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1939 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1940 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1941 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1942 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1943 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dc53d543
AD		 1944 /* Vega 12 */
1945 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1946 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1947 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1948 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1949 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1204a26e 1950 /* Vega 20 */
6dddaeef
AD		 1951 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1952 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1953 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1954 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
ec5b2020 1955 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
6dddaeef
AD		 1956 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1957 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
df515052 1958 /* Raven */
acc34503 1959 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
741deade 1960 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
48c69cda 1961 /* Arcturus */
12c5365e
AD		 1962 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1963 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1964 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1965 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
bd1c0fdf
AD		 1966 /* Navi10 */
1967 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1968 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1969 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1970 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1971 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1972 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
89428811 1973 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1974 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
26051720 1975 /* Navi14 */
b62d9554
AD		 1976 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1977 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1978 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1979 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
df515052 1980
61bdb39c 1981 /* Renoir */
775da830 1982 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
23fe1390 1983 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
8bf08351 1984 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
278cdb68 1985 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
61bdb39c 1986
10e85054 1987 /* Navi12 */
d34c7b7b
AD		 1988 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1989 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
10e85054 1990
61278d14
LG		 1991 /* Sienna_Cichlid */
1992 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
d26bbbcc 1993 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14
LG		 1994 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1995 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1996 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1997 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1998 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1999 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 2000 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2001 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 2002 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
ed098aa3 2003 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 2004 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
10e85054 2005
27f5355f
AL		 2006 /* Yellow Carp */
2007 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2008 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2009
2c1eaddd
TZ		 2010 /* Navy_Flounder */
2011 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2012 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2013 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
8f0c93f4
AD		 2014 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2015 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2016 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2017 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2018 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2c1eaddd
TZ		 2019 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2020
e7de4aee
TZ		 2021 /* DIMGREY_CAVEFISH */
2022 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2023 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2024 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
06ac9b6c 2025 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
8f0c93f4
AD		 2026 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2027 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2028 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2029 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2030 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2031 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2032 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
e7de4aee
TZ		 2033 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2034
4c2e5f51 2035 /* Aldebaran */
3786a9bc
AD		 2036 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2037 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2038 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2039 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
4c2e5f51 2040
a8f70696
TZ		 2041 /* CYAN_SKILLFISH */
2042 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
dfcc3e8c 2043 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
a8f70696 2044
a2e9b166
CG		 2045 /* BEIGE_GOBY */
2046 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2047 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2048 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2049 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
62e9bd20 2050 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
a2e9b166
CG		 2051 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2052
eb4fd29a
AD		 2053 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2054 .class = PCI_CLASS_DISPLAY_VGA << 8,
2055 .class_mask = 0xffffff,
d0761fd2 2056 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a
AD		 2057
2058 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2059 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2060 .class_mask = 0xffffff,
d0761fd2 2061 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a 2062
5d6cd200 2063 { PCI_DEVICE(0x1002, PCI_ANY_ID),
9d65b1b4 2064 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
5d6cd200
SZ		 2065 .class_mask = 0xffffff,
2066 .driver_data = CHIP_IP_DISCOVERY },
2067
d38ceaf9
AD		 2068 {0, 0, 0}
2069};
2070
2071MODULE_DEVICE_TABLE(pci, pciidlist);
2072
dbab6356
MJ		 2073static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
2074 /* differentiate between P10 and P11 asics with the same DID */
2075 {0x67FF, 0xE3, CHIP_POLARIS10},
2076 {0x67FF, 0xE7, CHIP_POLARIS10},
2077 {0x67FF, 0xF3, CHIP_POLARIS10},
2078 {0x67FF, 0xF7, CHIP_POLARIS10},
2079};
2080
5088d657 2081static const struct drm_driver amdgpu_kms_driver;
d38ceaf9 2082
243c719e 2083static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
d0d66b8c
AD		 2084{
2085 struct pci_dev *p = NULL;
243c719e 2086 int i;
d0d66b8c 2087
243c719e
AD		 2088 /* 0 - GPU
2089 * 1 - audio
2090 * 2 - USB
2091 * 3 - UCSI
2092 */
2093 for (i = 1; i < 4; i++) {
2094 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2095 adev->pdev->bus->number, i);
2096 if (p) {
2097 pm_runtime_get_sync(&p->dev);
2098 pm_runtime_mark_last_busy(&p->dev);
2099 pm_runtime_put_autosuspend(&p->dev);
2100 pci_dev_put(p);
2101 }
d0d66b8c
AD		 2102 }
2103}
2104
887db1e4
AA		 2105static void amdgpu_init_debug_options(struct amdgpu_device *adev)
2106{
2107 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {
2108 pr_info("debug: VM handling debug enabled\n");
2109 adev->debug_vm = true;
2110 }
2111
2112 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {
2113 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
2114 adev->debug_largebar = true;
2115 }
ffde7210
AA		 2116
2117 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {
2118 pr_info("debug: soft reset for GPU recovery disabled\n");
2119 adev->debug_disable_soft_recovery = true;
2120 }
d20e1aec
LM		 2121
2122 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {
2123 pr_info("debug: place fw in vram for frontdoor loading\n");
2124 adev->debug_use_vram_fw_buf = true;
2125 }
887db1e4
AA		 2126}
2127
dbab6356
MJ		 2128static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
2129{
2130 int i;
2131
2132 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
2133 if (pdev->device == asic_type_quirks[i].device &&
2134 pdev->revision == asic_type_quirks[i].revision) {
2135 flags &= ~AMD_ASIC_MASK;
2136 flags |= asic_type_quirks[i].type;
2137 break;
2138 }
2139 }
2140
2141 return flags;
2142}
2143
d38ceaf9
AD		 2144static int amdgpu_pci_probe(struct pci_dev *pdev,
2145 const struct pci_device_id *ent)
2146{
8aba21b7 2147 struct drm_device *ddev;
c6385e50 2148 struct amdgpu_device *adev;
d38ceaf9 2149 unsigned long flags = ent->driver_data;
bdbeb0dd 2150 int ret, retry = 0, i;
3fa203af
AD		 2151 bool supports_atomic = false;
2152
bdbeb0dd
AD		 2153 /* skip devices which are owned by radeon */
2154 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2155 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2156 return -ENODEV;
2157 }
2158
7294863a
ML		 2159 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2160 amdgpu_aspm = 0;
2161
84ec374b 2162 if (amdgpu_virtual_display ||
3fa203af
AD		 2163 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2164 supports_atomic = true;
d38ceaf9 2165
2f7d10b3 2166 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 2167 DRM_INFO("This hardware requires experimental hardware support.\n"
2168 "See modparam exp_hw_support\n");
2169 return -ENODEV;
2170 }
dbab6356
MJ		 2171
2172 flags = amdgpu_fix_asic_type(pdev, flags);
d38ceaf9 2173
ea68573d
AD		 2174 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2175 * however, SME requires an indirect IOMMU mapping because the encryption
2176 * bit is beyond the DMA mask of the chip.
2177 */
e9d1d2bb
TL		 2178 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2179 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
ea68573d
AD		 2180 dev_info(&pdev->dev,
2181 "SME is not compatible with RAVEN\n");
2182 return -ENOTSUPP;
2183 }
2184
984d7a92
HG		 2185#ifdef CONFIG_DRM_AMDGPU_SI
2186 if (!amdgpu_si_support) {
2187 switch (flags & AMD_ASIC_MASK) {
2188 case CHIP_TAHITI:
2189 case CHIP_PITCAIRN:
2190 case CHIP_VERDE:
2191 case CHIP_OLAND:
2192 case CHIP_HAINAN:
2193 dev_info(&pdev->dev,
2194 "SI support provided by radeon.\n");
2195 dev_info(&pdev->dev,
2196 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2197 );
2198 return -ENODEV;
2199 }
2200 }
2201#endif
2202#ifdef CONFIG_DRM_AMDGPU_CIK
2203 if (!amdgpu_cik_support) {
2204 switch (flags & AMD_ASIC_MASK) {
2205 case CHIP_KAVERI:
2206 case CHIP_BONAIRE:
2207 case CHIP_HAWAII:
2208 case CHIP_KABINI:
2209 case CHIP_MULLINS:
2210 dev_info(&pdev->dev,
2211 "CIK support provided by radeon.\n");
2212 dev_info(&pdev->dev,
2213 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2214 );
2215 return -ENODEV;
2216 }
2217 }
2218#endif
2219
5088d657 2220 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
df2ce459
LT		 2221 if (IS_ERR(adev))
2222 return PTR_ERR(adev);
8aba21b7
LT		 2223
2224 adev->dev = &pdev->dev;
2225 adev->pdev = pdev;
2226 ddev = adev_to_drm(adev);
b58c1131 2227
351c4dbe 2228 if (!supports_atomic)
8aba21b7 2229 ddev->driver_features &= ~DRIVER_ATOMIC;
351c4dbe 2230
b58c1131
AD		 2231 ret = pci_enable_device(pdev);
2232 if (ret)
df2ce459 2233 return ret;
b58c1131 2234
8aba21b7 2235 pci_set_drvdata(pdev, ddev);
b58c1131 2236
51258acd
LM		 2237 amdgpu_init_debug_options(adev);
2238
1d4624cd 2239 ret = amdgpu_driver_load_kms(adev, flags);
7504d3bb
LC		 2240 if (ret)
2241 goto err_pci;
c6385e50 2242
1daee8b4 2243retry_init:
1d4624cd 2244 ret = drm_dev_register(ddev, flags);
1daee8b4
PD		 2245 if (ret == -EAGAIN && ++retry <= 3) {
2246 DRM_INFO("retry init %d\n", retry);
2247 /* Don't request EX mode too frequently which is attacking */
2248 msleep(5000);
2249 goto retry_init;
8aba21b7 2250 } else if (ret) {
b58c1131 2251 goto err_pci;
8aba21b7 2252 }
b58c1131 2253
2c1c7ba4
JZ		 2254 ret = amdgpu_xcp_dev_register(adev, ent);
2255 if (ret)
2256 goto err_pci;
2257
087451f3
EQ		 2258 /*
2259 * 1. don't init fbdev on hw without DCE
2260 * 2. don't init fbdev if there are no connectors
2261 */
2262 if (adev->mode_info.mode_config_initialized &&
2263 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2264 /* select 8 bpp console on low vram cards */
2265 if (adev->gmc.real_vram_size <= (32*1024*1024))
2266 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2267 else
2268 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2269 }
2270
c6385e50
AD		 2271 ret = amdgpu_debugfs_init(adev);
2272 if (ret)
2273 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2274
9c913f38 2275 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
d0d66b8c
AD		 2276 /* only need to skip on ATPX */
2277 if (amdgpu_device_supports_px(ddev))
2278 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2279 /* we want direct complete for BOCO */
2280 if (amdgpu_device_supports_boco(ddev))
2281 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2282 DPM_FLAG_SMART_SUSPEND |
2283 DPM_FLAG_MAY_SKIP_RESUME);
2284 pm_runtime_use_autosuspend(ddev->dev);
2285 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2286
2287 pm_runtime_allow(ddev->dev);
2288
2289 pm_runtime_mark_last_busy(ddev->dev);
2290 pm_runtime_put_autosuspend(ddev->dev);
2291
bd1f6a31
ML		 2292 pci_wake_from_d3(pdev, TRUE);
2293
d0d66b8c
AD		 2294 /*
2295 * For runpm implemented via BACO, PMFW will handle the
2296 * timing for BACO in and out:
2297 * - put ASIC into BACO state only when both video and
2298 * audio functions are in D3 state.
2299 * - pull ASIC out of BACO state when either video or
2300 * audio function is in D0 state.
2301 * Also, at startup, PMFW assumes both functions are in
2302 * D0 state.
2303 *
2304 * So if snd driver was loaded prior to amdgpu driver
2305 * and audio function was put into D3 state, there will
2306 * be no PMFW-aware D-state transition(D0->D3) on runpm
2307 * suspend. Thus the BACO will be not correctly kicked in.
2308 *
243c719e 2309 * Via amdgpu_get_secondary_funcs(), the audio dev is put
d0d66b8c
AD		 2310 * into D0 state. Then there will be a PMFW-aware D-state
2311 * transition(D0->D3) on runpm suspend.
2312 */
2313 if (amdgpu_device_supports_baco(ddev) &&
2314 !(adev->flags & AMD_IS_APU) &&
2315 (adev->asic_type >= CHIP_NAVI10))
243c719e 2316 amdgpu_get_secondary_funcs(adev);
d0d66b8c
AD		 2317 }
2318
b58c1131
AD		 2319 return 0;
2320
2321err_pci:
2322 pci_disable_device(pdev);
b58c1131 2323 return ret;
d38ceaf9
AD		 2324}
2325
2326static void
2327amdgpu_pci_remove(struct pci_dev *pdev)
2328{
2329 struct drm_device *dev = pci_get_drvdata(pdev);
d0d66b8c 2330 struct amdgpu_device *adev = drm_to_adev(dev);
d38ceaf9 2331
2c1c7ba4 2332 amdgpu_xcp_dev_unplug(adev);
39934d3e
VP		 2333 drm_dev_unplug(dev);
2334
9c913f38 2335 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
d0d66b8c
AD		 2336 pm_runtime_get_sync(dev->dev);
2337 pm_runtime_forbid(dev->dev);
2338 }
2339
c6385e50 2340 amdgpu_driver_unload_kms(dev);
72c8c97b 2341
98c6e6a7
AG		 2342 /*
2343 * Flush any in flight DMA operations from device.
2344 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2345 * StatusTransactions Pending bit.
2346 */
fd4495e5 2347 pci_disable_device(pdev);
98c6e6a7 2348 pci_wait_for_pending_transaction(pdev);
d38ceaf9
AD		 2349}
2350
61e11306
AD		 2351static void
2352amdgpu_pci_shutdown(struct pci_dev *pdev)
2353{
faefba95 2354 struct drm_device *dev = pci_get_drvdata(pdev);
1348969a 2355 struct amdgpu_device *adev = drm_to_adev(dev);
faefba95 2356
7c6e68c7
AG		 2357 if (amdgpu_ras_intr_triggered())
2358 return;
2359
61e11306 2360 /* if we are running in a VM, make sure the device
00ea8cba
AD		 2361 * torn down properly on reboot/shutdown.
2362 * unfortunately we can't detect certain
2363 * hypervisors so just do this all the time.
61e11306 2364 */
05cac1ae
ND		 2365 if (!amdgpu_passthrough(adev))
2366 adev->mp1_state = PP_MP1_STATE_UNLOAD;
cdd61df6 2367 amdgpu_device_ip_suspend(adev);
a3a09142 2368 adev->mp1_state = PP_MP1_STATE_NONE;
61e11306
AD		 2369}
2370
e3c1b071 2371/**
2372 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2373 *
2374 * @work: work_struct.
2375 */
2376static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2377{
2378 struct list_head device_list;
2379 struct amdgpu_device *adev;
2380 int i, r;
04442bf7
LL		 2381 struct amdgpu_reset_context reset_context;
2382
2383 memset(&reset_context, 0, sizeof(reset_context));
e3c1b071 2384
2385 mutex_lock(&mgpu_info.mutex);
2386 if (mgpu_info.pending_reset == true) {
2387 mutex_unlock(&mgpu_info.mutex);
2388 return;
2389 }
2390 mgpu_info.pending_reset = true;
2391 mutex_unlock(&mgpu_info.mutex);
2392
04442bf7
LL		 2393 /* Use a common context, just need to make sure full reset is done */
2394 reset_context.method = AMD_RESET_METHOD_NONE;
2395 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2396
e3c1b071 2397 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2398 adev = mgpu_info.gpu_ins[i].adev;
04442bf7
LL		 2399 reset_context.reset_req_dev = adev;
2400 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
e3c1b071 2401 if (r) {
2402 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2403 r, adev_to_drm(adev)->unique);
2404 }
2405 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2406 r = -EALREADY;
2407 }
2408 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2409 adev = mgpu_info.gpu_ins[i].adev;
e3c1b071 2410 flush_work(&adev->xgmi_reset_work);
050743da 2411 adev->gmc.xgmi.pending_reset = false;
e3c1b071 2412 }
2413
2414 /* reset function will rebuild the xgmi hive info , clear it now */
2415 for (i = 0; i < mgpu_info.num_dgpu; i++)
2416 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2417
2418 INIT_LIST_HEAD(&device_list);
2419
2420 for (i = 0; i < mgpu_info.num_dgpu; i++)
2421 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2422
2423 /* unregister the GPU first, reset function will add them back */
2424 list_for_each_entry(adev, &device_list, reset_list)
2425 amdgpu_unregister_gpu_instance(adev);
2426
04442bf7
LL		 2427 /* Use a common context, just need to make sure full reset is done */
2428 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2429 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2430
e3c1b071 2431 if (r) {
2432 DRM_ERROR("reinit gpus failure");
2433 return;
2434 }
2435 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2436 adev = mgpu_info.gpu_ins[i].adev;
2437 if (!adev->kfd.init_complete)
2438 amdgpu_amdkfd_device_init(adev);
2439 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2440 }
e3c1b071 2441}
2442
e25443d2
AD		 2443static int amdgpu_pmops_prepare(struct device *dev)
2444{
2445 struct drm_device *drm_dev = dev_get_drvdata(dev);
d2a197a4 2446 struct amdgpu_device *adev = drm_to_adev(drm_dev);
e25443d2
AD		 2447
2448 /* Return a positive number here so
2449 * DPM_FLAG_SMART_SUSPEND works properly
2450 */
5095d541
ML		 2451 if (amdgpu_device_supports_boco(drm_dev) &&
2452 pm_runtime_suspended(dev))
2453 return 1;
e25443d2 2454
d2a197a4
ML		 2455 /* if we will not support s3 or s2i for the device
2456 * then skip suspend
2457 */
2458 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2459 !amdgpu_acpi_is_s3_active(adev))
2460 return 1;
e25443d2 2461
5095d541 2462 return amdgpu_device_prepare(drm_dev);
e25443d2
AD		 2463}
2464
2465static void amdgpu_pmops_complete(struct device *dev)
2466{
2467 /* nothing to do */
2468}
2469
d38ceaf9
AD		 2470static int amdgpu_pmops_suspend(struct device *dev)
2471{
911d8b30 2472 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733 2473 struct amdgpu_device *adev = drm_to_adev(drm_dev);
74b0b157 2474
d0260f62 2475 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2476 adev->in_s0ix = true;
ca475186 2477 else if (amdgpu_acpi_is_s3_active(adev))
eac4c54b 2478 adev->in_s3 = true;
ca475186
ML		 2479 if (!adev->in_s0ix && !adev->in_s3)
2480 return 0;
9e051720
KHF		 2481 return amdgpu_device_suspend(drm_dev, true);
2482}
2483
2484static int amdgpu_pmops_suspend_noirq(struct device *dev)
2485{
2486 struct drm_device *drm_dev = dev_get_drvdata(dev);
2487 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2488
0223e516 2489 if (amdgpu_acpi_should_gpu_reset(adev))
9e051720
KHF		 2490 return amdgpu_asic_reset(adev);
2491
2492 return 0;
d38ceaf9
AD		 2493}
2494
2495static int amdgpu_pmops_resume(struct device *dev)
2496{
911d8b30 2497 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2498 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2499 int r;
85e154c2 2500
ca475186
ML		 2501 if (!adev->in_s0ix && !adev->in_s3)
2502 return 0;
2503
ebe86a57
AG		 2504 /* Avoids registers access if device is physically gone */
2505 if (!pci_device_is_present(adev->pdev))
2506 adev->no_hw_access = true;
2507
62498733 2508 r = amdgpu_device_resume(drm_dev, true);
d0260f62 2509 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2510 adev->in_s0ix = false;
eac4c54b
ML		 2511 else
2512 adev->in_s3 = false;
62498733 2513 return r;
d38ceaf9
AD		 2514}
2515
2516static int amdgpu_pmops_freeze(struct device *dev)
2517{
911d8b30 2518 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2519 struct amdgpu_device *adev = drm_to_adev(drm_dev);
897483d8 2520 int r;
74b0b157 2521
62498733 2522 adev->in_s4 = true;
de185019 2523 r = amdgpu_device_suspend(drm_dev, true);
62498733 2524 adev->in_s4 = false;
897483d8
AD		 2525 if (r)
2526 return r;
af1f2985
TH		 2527
2528 if (amdgpu_acpi_should_gpu_reset(adev))
2529 return amdgpu_asic_reset(adev);
2530 return 0;
d38ceaf9
AD		 2531}
2532
2533static int amdgpu_pmops_thaw(struct device *dev)
2534{
911d8b30 2535 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2536
de185019 2537 return amdgpu_device_resume(drm_dev, true);
74b0b157 2538}
2539
2540static int amdgpu_pmops_poweroff(struct device *dev)
2541{
911d8b30 2542 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2543
62498733 2544 return amdgpu_device_suspend(drm_dev, true);
74b0b157 2545}
2546
2547static int amdgpu_pmops_restore(struct device *dev)
2548{
911d8b30 2549 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2550
de185019 2551 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 2552}
2553
4020c228
AD		 2554static int amdgpu_runtime_idle_check_display(struct device *dev)
2555{
2556 struct pci_dev *pdev = to_pci_dev(dev);
2557 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2558 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2559
2560 if (adev->mode_info.num_crtc) {
2561 struct drm_connector *list_connector;
2562 struct drm_connector_list_iter iter;
2563 int ret = 0;
2564
4d6fc55a
AD		 2565 if (amdgpu_runtime_pm != -2) {
2566 /* XXX: Return busy if any displays are connected to avoid
2567 * possible display wakeups after runtime resume due to
2568 * hotplug events in case any displays were connected while
2569 * the GPU was in suspend. Remove this once that is fixed.
2570 */
2571 mutex_lock(&drm_dev->mode_config.mutex);
2572 drm_connector_list_iter_begin(drm_dev, &iter);
2573 drm_for_each_connector_iter(list_connector, &iter) {
2574 if (list_connector->status == connector_status_connected) {
2575 ret = -EBUSY;
2576 break;
2577 }
4020c228 2578 }
4d6fc55a
AD		 2579 drm_connector_list_iter_end(&iter);
2580 mutex_unlock(&drm_dev->mode_config.mutex);
4020c228 2581
4d6fc55a
AD		 2582 if (ret)
2583 return ret;
2584 }
4020c228 2585
d09ef243 2586 if (adev->dc_enabled) {
4020c228
AD		 2587 struct drm_crtc *crtc;
2588
2589 drm_for_each_crtc(crtc, drm_dev) {
2590 drm_modeset_lock(&crtc->mutex, NULL);
2591 if (crtc->state->active)
2592 ret = -EBUSY;
2593 drm_modeset_unlock(&crtc->mutex);
2594 if (ret < 0)
2595 break;
2596 }
2597 } else {
2598 mutex_lock(&drm_dev->mode_config.mutex);
2599 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2600
2601 drm_connector_list_iter_begin(drm_dev, &iter);
2602 drm_for_each_connector_iter(list_connector, &iter) {
2603 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2604 ret = -EBUSY;
2605 break;
2606 }
2607 }
2608
2609 drm_connector_list_iter_end(&iter);
2610
2611 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2612 mutex_unlock(&drm_dev->mode_config.mutex);
2613 }
2614 if (ret)
2615 return ret;
2616 }
2617
2618 return 0;
2619}
2620
d38ceaf9
AD		 2621static int amdgpu_pmops_runtime_suspend(struct device *dev)
2622{
2623 struct pci_dev *pdev = to_pci_dev(dev);
2624 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2625 struct amdgpu_device *adev = drm_to_adev(drm_dev);
719423f6 2626 int ret, i;
d38ceaf9 2627
9c913f38 2628 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
d38ceaf9
AD		 2629 pm_runtime_forbid(dev);
2630 return -EBUSY;
2631 }
2632
4020c228
AD		 2633 ret = amdgpu_runtime_idle_check_display(dev);
2634 if (ret)
2635 return ret;
2636
719423f6
AD		 2637 /* wait for all rings to drain before suspending */
2638 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2639 struct amdgpu_ring *ring = adev->rings[i];
f9acfafc 2640
719423f6
AD		 2641 if (ring && ring->sched.ready) {
2642 ret = amdgpu_fence_wait_empty(ring);
2643 if (ret)
2644 return -EBUSY;
2645 }
2646 }
2647
f0f7ddfc 2648 adev->in_runpm = true;
b98c6299 2649 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2650 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
d38ceaf9 2651
7be3be2b
EQ		 2652 /*
2653 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2654 * proper cleanups and put itself into a state ready for PNP. That
2655 * can address some random resuming failure observed on BOCO capable
2656 * platforms.
2657 * TODO: this may be also needed for PX capable platform.
2658 */
2659 if (amdgpu_device_supports_boco(drm_dev))
2660 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2661
5095d541
ML		 2662 ret = amdgpu_device_prepare(drm_dev);
2663 if (ret)
2664 return ret;
de185019 2665 ret = amdgpu_device_suspend(drm_dev, false);
cef8b03b
AD		 2666 if (ret) {
2667 adev->in_runpm = false;
7be3be2b
EQ		 2668 if (amdgpu_device_supports_boco(drm_dev))
2669 adev->mp1_state = PP_MP1_STATE_NONE;
70bedd68 2670 return ret;
cef8b03b 2671 }
70bedd68 2672
7be3be2b
EQ		 2673 if (amdgpu_device_supports_boco(drm_dev))
2674 adev->mp1_state = PP_MP1_STATE_NONE;
2675
b98c6299 2676 if (amdgpu_device_supports_px(drm_dev)) {
562b49fc
AD		 2677 /* Only need to handle PCI state in the driver for ATPX
2678 * PCI core handles it for _PR3.
2679 */
b98c6299
AD		 2680 amdgpu_device_cache_pci_state(pdev);
2681 pci_disable_device(pdev);
2682 pci_ignore_hotplug(pdev);
2683 pci_set_power_state(pdev, PCI_D3cold);
b97e9d47 2684 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
11e612a0
AD		 2685 } else if (amdgpu_device_supports_boco(drm_dev)) {
2686 /* nothing to do */
19134317
AD		 2687 } else if (amdgpu_device_supports_baco(drm_dev)) {
2688 amdgpu_device_baco_enter(drm_dev);
b97e9d47 2689 }
d38ceaf9 2690
abcb2ace 2691 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
f4b09c29 2692
d38ceaf9
AD		 2693 return 0;
2694}
2695
2696static int amdgpu_pmops_runtime_resume(struct device *dev)
2697{
2698 struct pci_dev *pdev = to_pci_dev(dev);
2699 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2700 struct amdgpu_device *adev = drm_to_adev(drm_dev);
d38ceaf9
AD		 2701 int ret;
2702
9c913f38 2703 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
d38ceaf9
AD		 2704 return -EINVAL;
2705
e1543d83
AG		 2706 /* Avoids registers access if device is physically gone */
2707 if (!pci_device_is_present(adev->pdev))
2708 adev->no_hw_access = true;
2709
b98c6299 2710 if (amdgpu_device_supports_px(drm_dev)) {
b97e9d47
AD		 2711 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2712
562b49fc
AD		 2713 /* Only need to handle PCI state in the driver for ATPX
2714 * PCI core handles it for _PR3.
2715 */
b98c6299
AD		 2716 pci_set_power_state(pdev, PCI_D0);
2717 amdgpu_device_load_pci_state(pdev);
2718 ret = pci_enable_device(pdev);
2719 if (ret)
2720 return ret;
637bb036 2721 pci_set_master(pdev);
fd496ca8
AD		 2722 } else if (amdgpu_device_supports_boco(drm_dev)) {
2723 /* Only need to handle PCI state in the driver for ATPX
2724 * PCI core handles it for _PR3.
2725 */
2726 pci_set_master(pdev);
19134317
AD		 2727 } else if (amdgpu_device_supports_baco(drm_dev)) {
2728 amdgpu_device_baco_exit(drm_dev);
b97e9d47 2729 }
de185019 2730 ret = amdgpu_device_resume(drm_dev, false);
6b11af6d
YY		 2731 if (ret) {
2732 if (amdgpu_device_supports_px(drm_dev))
2733 pci_disable_device(pdev);
b45aeb2d 2734 return ret;
6b11af6d 2735 }
b45aeb2d 2736
b98c6299 2737 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2738 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
f0f7ddfc 2739 adev->in_runpm = false;
d38ceaf9
AD		 2740 return 0;
2741}
2742
2743static int amdgpu_pmops_runtime_idle(struct device *dev)
2744{
911d8b30 2745 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2746 struct amdgpu_device *adev = drm_to_adev(drm_dev);
97f6a21b
AG		 2747 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2748 int ret = 1;
d38ceaf9 2749
9c913f38 2750 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
d38ceaf9
AD		 2751 pm_runtime_forbid(dev);
2752 return -EBUSY;
2753 }
2754
4020c228 2755 ret = amdgpu_runtime_idle_check_display(dev);
97f6a21b 2756
d38ceaf9
AD		 2757 pm_runtime_mark_last_busy(dev);
2758 pm_runtime_autosuspend(dev);
97f6a21b 2759 return ret;
d38ceaf9
AD		 2760}
2761
2762long amdgpu_drm_ioctl(struct file *filp,
2763 unsigned int cmd, unsigned long arg)
2764{
2765 struct drm_file *file_priv = filp->private_data;
2766 struct drm_device *dev;
2767 long ret;
f9acfafc 2768
d38ceaf9
AD		 2769 dev = file_priv->minor->dev;
2770 ret = pm_runtime_get_sync(dev->dev);
2771 if (ret < 0)
5509ac65 2772 goto out;
d38ceaf9
AD		 2773
2774 ret = drm_ioctl(filp, cmd, arg);
2775
2776 pm_runtime_mark_last_busy(dev->dev);
5509ac65 2777out:
d38ceaf9
AD		 2778 pm_runtime_put_autosuspend(dev->dev);
2779 return ret;
2780}
2781
2782static const struct dev_pm_ops amdgpu_pm_ops = {
e25443d2
AD		 2783 .prepare = amdgpu_pmops_prepare,
2784 .complete = amdgpu_pmops_complete,
d38ceaf9 2785 .suspend = amdgpu_pmops_suspend,
9e051720 2786 .suspend_noirq = amdgpu_pmops_suspend_noirq,
d38ceaf9
AD		 2787 .resume = amdgpu_pmops_resume,
2788 .freeze = amdgpu_pmops_freeze,
2789 .thaw = amdgpu_pmops_thaw,
74b0b157 2790 .poweroff = amdgpu_pmops_poweroff,
2791 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 2792 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2793 .runtime_resume = amdgpu_pmops_runtime_resume,
2794 .runtime_idle = amdgpu_pmops_runtime_idle,
2795};
2796
48ad368a
AG		 2797static int amdgpu_flush(struct file *f, fl_owner_t id)
2798{
2799 struct drm_file *file_priv = f->private_data;
2800 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
56753e73 2801 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
48ad368a 2802
56753e73
CK		 2803 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2804 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
48ad368a 2805
56753e73 2806 return timeout >= 0 ? 0 : timeout;
48ad368a
AG		 2807}
2808
d38ceaf9
AD		 2809static const struct file_operations amdgpu_driver_kms_fops = {
2810 .owner = THIS_MODULE,
2811 .open = drm_open,
48ad368a 2812 .flush = amdgpu_flush,
d38ceaf9
AD		 2813 .release = drm_release,
2814 .unlocked_ioctl = amdgpu_drm_ioctl,
71df0368 2815 .mmap = drm_gem_mmap,
d38ceaf9
AD		 2816 .poll = drm_poll,
2817 .read = drm_read,
2818#ifdef CONFIG_COMPAT
2819 .compat_ioctl = amdgpu_kms_compat_ioctl,
2820#endif
87444254 2821#ifdef CONFIG_PROC_FS
376c25f8 2822 .show_fdinfo = drm_show_fdinfo,
87444254 2823#endif
d38ceaf9
AD		 2824};
2825
021830d2
BN		 2826int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2827{
f3729f7b 2828 struct drm_file *file;
021830d2
BN		 2829
2830 if (!filp)
2831 return -EINVAL;
2832
f9acfafc 2833 if (filp->f_op != &amdgpu_driver_kms_fops)
021830d2 2834 return -EINVAL;
021830d2
BN		 2835
2836 file = filp->private_data;
2837 *fpriv = file->driver_priv;
2838 return 0;
2839}
2840
5088d657
LT		 2841const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2842 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2843 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2844 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2845 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2846 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2847 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2848 /* KMS */
2849 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2850 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2851 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2852 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2853 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2854 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2855 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2856 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2857 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2858 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2859};
2860
2861static const struct drm_driver amdgpu_kms_driver = {
d38ceaf9 2862 .driver_features =
f3ed6739 2863 DRIVER_ATOMIC |
1ff49481 2864 DRIVER_GEM |
db4ff423
CZ		 2865 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2866 DRIVER_SYNCOBJ_TIMELINE,
d38ceaf9 2867 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 2868 .postclose = amdgpu_driver_postclose_kms,
2869 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9 2870 .ioctls = amdgpu_ioctls_kms,
5088d657 2871 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
d38ceaf9
AD		 2872 .dumb_create = amdgpu_mode_dumb_create,
2873 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9 2874 .fops = &amdgpu_driver_kms_fops,
72c8c97b 2875 .release = &amdgpu_driver_release_kms,
1a56fcf0 2876#ifdef CONFIG_PROC_FS
376c25f8 2877 .show_fdinfo = amdgpu_show_fdinfo,
1a56fcf0 2878#endif
d38ceaf9 2879
09052fc3 2880 .gem_prime_import = amdgpu_gem_prime_import,
d38ceaf9
AD		 2881
2882 .name = DRIVER_NAME,
2883 .desc = DRIVER_DESC,
2884 .date = DRIVER_DATE,
2885 .major = KMS_DRIVER_MAJOR,
2886 .minor = KMS_DRIVER_MINOR,
2887 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2888};
2889
2c1c7ba4
JZ		 2890const struct drm_driver amdgpu_partition_driver = {
2891 .driver_features =
2892 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
2893 DRIVER_SYNCOBJ_TIMELINE,
2894 .open = amdgpu_driver_open_kms,
2895 .postclose = amdgpu_driver_postclose_kms,
2896 .lastclose = amdgpu_driver_lastclose_kms,
2897 .ioctls = amdgpu_ioctls_kms,
2898 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2899 .dumb_create = amdgpu_mode_dumb_create,
2900 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2901 .fops = &amdgpu_driver_kms_fops,
2902 .release = &amdgpu_driver_release_kms,
2903
2c1c7ba4 2904 .gem_prime_import = amdgpu_gem_prime_import,
d38ceaf9
AD		 2905
2906 .name = DRIVER_NAME,
2907 .desc = DRIVER_DESC,
2908 .date = DRIVER_DATE,
2909 .major = KMS_DRIVER_MAJOR,
2910 .minor = KMS_DRIVER_MINOR,
2911 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2912};
2913
c9a6b82f
AG		 2914static struct pci_error_handlers amdgpu_pci_err_handler = {
2915 .error_detected = amdgpu_pci_error_detected,
2916 .mmio_enabled = amdgpu_pci_mmio_enabled,
2917 .slot_reset = amdgpu_pci_slot_reset,
2918 .resume = amdgpu_pci_resume,
2919};
2920
35bba831
AG		 2921static const struct attribute_group *amdgpu_sysfs_groups[] = {
2922 &amdgpu_vram_mgr_attr_group,
2923 &amdgpu_gtt_mgr_attr_group,
521289d2 2924 &amdgpu_flash_attr_group,
35bba831
AG		 2925 NULL,
2926};
2927
d38ceaf9
AD		 2928static struct pci_driver amdgpu_kms_pci_driver = {
2929 .name = DRIVER_NAME,
2930 .id_table = pciidlist,
2931 .probe = amdgpu_pci_probe,
2932 .remove = amdgpu_pci_remove,
61e11306 2933 .shutdown = amdgpu_pci_shutdown,
d38ceaf9 2934 .driver.pm = &amdgpu_pm_ops,
c9a6b82f 2935 .err_handler = &amdgpu_pci_err_handler,
35bba831 2936 .dev_groups = amdgpu_sysfs_groups,
d38ceaf9
AD		 2937};
2938
2939static int __init amdgpu_init(void)
2940{
245ae5e9
CK		 2941 int r;
2942
6a2d2ddf 2943 if (drm_firmware_drivers_only())
c60e22f7 2944 return -EINVAL;
c60e22f7 2945
245ae5e9
CK		 2946 r = amdgpu_sync_init();
2947 if (r)
2948 goto error_sync;
2949
2950 r = amdgpu_fence_slab_init();
2951 if (r)
2952 goto error_fence;
2953
d38ceaf9 2954 DRM_INFO("amdgpu kernel modesetting enabled.\n");
d38ceaf9 2955 amdgpu_register_atpx_handler();
f9b7f370 2956 amdgpu_acpi_detect();
03a1c08d
FK		 2957
2958 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2959 amdgpu_amdkfd_init();
2960
d38ceaf9 2961 /* let modprobe override vga console setting */
448d1051 2962 return pci_register_driver(&amdgpu_kms_pci_driver);
245ae5e9 2963
245ae5e9
CK		 2964error_fence:
2965 amdgpu_sync_fini();
2966
2967error_sync:
2968 return r;
d38ceaf9
AD		 2969}
2970
2971static void __exit amdgpu_exit(void)
2972{
130e0371 2973 amdgpu_amdkfd_fini();
448d1051 2974 pci_unregister_driver(&amdgpu_kms_pci_driver);
d38ceaf9 2975 amdgpu_unregister_atpx_handler();
4d5275ab 2976 amdgpu_acpi_release();
257bf15a 2977 amdgpu_sync_fini();
d573de2d 2978 amdgpu_fence_slab_fini();
c7d8b782 2979 mmu_notifier_synchronize();
9938333a 2980 amdgpu_xcp_drv_release();
d38ceaf9
AD		 2981}
2982
2983module_init(amdgpu_init);
2984module_exit(amdgpu_exit);
2985
2986MODULE_AUTHOR(DRIVER_AUTHOR);
2987MODULE_DESCRIPTION(DRIVER_DESC);
2988MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)