[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_dpm.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef __AMDGPU_DPM_H__
#define __AMDGPU_DPM_H__

enum amdgpu_int_thermal_type {
	THERMAL_TYPE_NONE,
	THERMAL_TYPE_EXTERNAL,
	THERMAL_TYPE_EXTERNAL_GPIO,
	THERMAL_TYPE_RV6XX,
	THERMAL_TYPE_RV770,
	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
	THERMAL_TYPE_EVERGREEN,
	THERMAL_TYPE_SUMO,
	THERMAL_TYPE_NI,
	THERMAL_TYPE_SI,
	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
	THERMAL_TYPE_CI,
	THERMAL_TYPE_KV,
};

enum amdgpu_dpm_auto_throttle_src {
	AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
	AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
};

enum amdgpu_dpm_event_src {
	AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
	AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
	AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
	AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
};

struct amdgpu_ps {
	u32 caps; /* vbios flags */
	u32 class; /* vbios flags */
	u32 class2; /* vbios flags */
	/* UVD clocks */
	u32 vclk;
	u32 dclk;
	/* VCE clocks */
	u32 evclk;
	u32 ecclk;
	bool vce_active;
	enum amd_vce_level vce_level;
	/* asic priv */
	void *ps_priv;
};

struct amdgpu_dpm_thermal {
	/* thermal interrupt work */
	struct work_struct work;
	/* low temperature threshold */
	int                min_temp;
	/* high temperature threshold */
	int                max_temp;
	/* was last interrupt low to high or high to low */
	bool               high_to_low;
	/* interrupt source */
	struct amdgpu_irq_src	irq;
};

enum amdgpu_clk_action
{
	AMDGPU_SCLK_UP = 1,
	AMDGPU_SCLK_DOWN
};

struct amdgpu_blacklist_clocks
{
	u32 sclk;
	u32 mclk;
	enum amdgpu_clk_action action;
};

struct amdgpu_clock_and_voltage_limits {
	u32 sclk;
	u32 mclk;
	u16 vddc;
	u16 vddci;
};

struct amdgpu_clock_array {
	u32 count;
	u32 *values;
};

struct amdgpu_clock_voltage_dependency_entry {
	u32 clk;
	u16 v;
};

struct amdgpu_clock_voltage_dependency_table {
	u32 count;
	struct amdgpu_clock_voltage_dependency_entry *entries;
};

union amdgpu_cac_leakage_entry {
	struct {
		u16 vddc;
		u32 leakage;
	};
	struct {
		u16 vddc1;
		u16 vddc2;
		u16 vddc3;
	};
};

struct amdgpu_cac_leakage_table {
	u32 count;
	union amdgpu_cac_leakage_entry *entries;
};

struct amdgpu_phase_shedding_limits_entry {
	u16 voltage;
	u32 sclk;
	u32 mclk;
};

struct amdgpu_phase_shedding_limits_table {
	u32 count;
	struct amdgpu_phase_shedding_limits_entry *entries;
};

struct amdgpu_uvd_clock_voltage_dependency_entry {
	u32 vclk;
	u32 dclk;
	u16 v;
};

struct amdgpu_uvd_clock_voltage_dependency_table {
	u8 count;
	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
};

struct amdgpu_vce_clock_voltage_dependency_entry {
	u32 ecclk;
	u32 evclk;
	u16 v;
};

struct amdgpu_vce_clock_voltage_dependency_table {
	u8 count;
	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
};

struct amdgpu_ppm_table {
	u8 ppm_design;
	u16 cpu_core_number;
	u32 platform_tdp;
	u32 small_ac_platform_tdp;
	u32 platform_tdc;
	u32 small_ac_platform_tdc;
	u32 apu_tdp;
	u32 dgpu_tdp;
	u32 dgpu_ulv_power;
	u32 tj_max;
};

struct amdgpu_cac_tdp_table {
	u16 tdp;
	u16 configurable_tdp;
	u16 tdc;
	u16 battery_power_limit;
	u16 small_power_limit;
	u16 low_cac_leakage;
	u16 high_cac_leakage;
	u16 maximum_power_delivery_limit;
};

struct amdgpu_dpm_dynamic_state {
	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
	struct amdgpu_clock_array valid_sclk_values;
	struct amdgpu_clock_array valid_mclk_values;
	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
	u32 mclk_sclk_ratio;
	u32 sclk_mclk_delta;
	u16 vddc_vddci_delta;
	u16 min_vddc_for_pcie_gen2;
	struct amdgpu_cac_leakage_table cac_leakage_table;
	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
	struct amdgpu_ppm_table *ppm_table;
	struct amdgpu_cac_tdp_table *cac_tdp_table;
};

struct amdgpu_dpm_fan {
	u16 t_min;
	u16 t_med;
	u16 t_high;
	u16 pwm_min;
	u16 pwm_med;
	u16 pwm_high;
	u8 t_hyst;
	u32 cycle_delay;
	u16 t_max;
	u8 control_mode;
	u16 default_max_fan_pwm;
	u16 default_fan_output_sensitivity;
	u16 fan_output_sensitivity;
	bool ucode_fan_control;
};

enum amdgpu_pcie_gen {
	AMDGPU_PCIE_GEN1 = 0,
	AMDGPU_PCIE_GEN2 = 1,
	AMDGPU_PCIE_GEN3 = 2,
	AMDGPU_PCIE_GEN_INVALID = 0xffff
};

#define amdgpu_dpm_pre_set_power_state(adev) \
		((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_power_state(adev) \
		((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))

#define amdgpu_dpm_post_set_power_state(adev) \
		((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))

#define amdgpu_dpm_display_configuration_changed(adev) \
		((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))

#define amdgpu_dpm_print_power_state(adev, ps) \
		((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))

#define amdgpu_dpm_vblank_too_short(adev) \
		((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))

#define amdgpu_dpm_enable_bapm(adev, e) \
		((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))

#define amdgpu_dpm_read_sensor(adev, idx, value, size) \
		((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))

#define amdgpu_dpm_set_fan_control_mode(adev, m) \
		((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))

#define amdgpu_dpm_get_fan_control_mode(adev) \
		((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
		((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))

#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
		((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))

#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
		((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))

#define amdgpu_dpm_set_fan_speed_rpm(adev, s) \
		((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))

#define amdgpu_dpm_get_sclk(adev, l) \
		((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))

#define amdgpu_dpm_get_mclk(adev, l)  \
		((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))

#define amdgpu_dpm_force_performance_level(adev, l) \
		((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))

#define amdgpu_dpm_get_current_power_state(adev) \
		((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))

#define amdgpu_dpm_get_pp_num_states(adev, data) \
		((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))

#define amdgpu_dpm_get_pp_table(adev, table) \
		((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))

#define amdgpu_dpm_set_pp_table(adev, buf, size) \
		((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))

#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
		((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))

#define amdgpu_dpm_force_clock_level(adev, type, level) \
		((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))

#define amdgpu_dpm_get_sclk_od(adev) \
		((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_sclk_od(adev, value) \
		((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))

#define amdgpu_dpm_get_mclk_od(adev) \
		((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_mclk_od(adev, value) \
		((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))

#define amdgpu_dpm_dispatch_task(adev, task_id, user_state)		\
		((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state))

#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
		((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))

#define amdgpu_dpm_get_vce_clock_state(adev, i)				\
		((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))

#define amdgpu_dpm_get_performance_level(adev)				\
		((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))

#define amdgpu_dpm_reset_power_profile_state(adev, request) \
		((adev)->powerplay.pp_funcs->reset_power_profile_state(\
			(adev)->powerplay.pp_handle, request))

#define amdgpu_dpm_switch_power_profile(adev, type, en) \
		((adev)->powerplay.pp_funcs->switch_power_profile(\
			(adev)->powerplay.pp_handle, type, en))

#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
			(adev)->powerplay.pp_handle, msg_id))

#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
		((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
			(adev)->powerplay.pp_handle, block_type, gate))

#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
		((adev)->powerplay.pp_funcs->get_power_profile_mode(\
			(adev)->powerplay.pp_handle, buf))

#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
		((adev)->powerplay.pp_funcs->set_power_profile_mode(\
			(adev)->powerplay.pp_handle, parameter, size))

#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
		((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
			(adev)->powerplay.pp_handle, type, parameter, size))

#define amdgpu_dpm_enable_mgpu_fan_boost(adev) \
		((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
			(adev)->powerplay.pp_handle))

#define amdgpu_dpm_get_ppfeature_status(adev, buf) \
		((adev)->powerplay.pp_funcs->get_ppfeature_status(\
			(adev)->powerplay.pp_handle, (buf)))

#define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \
		((adev)->powerplay.pp_funcs->set_ppfeature_status(\
			(adev)->powerplay.pp_handle, (ppfeatures)))

struct amdgpu_dpm {
	struct amdgpu_ps        *ps;
	/* number of valid power states */
	int                     num_ps;
	/* current power state that is active */
	struct amdgpu_ps        *current_ps;
	/* requested power state */
	struct amdgpu_ps        *requested_ps;
	/* boot up power state */
	struct amdgpu_ps        *boot_ps;
	/* default uvd power state */
	struct amdgpu_ps        *uvd_ps;
	/* vce requirements */
	u32                  num_of_vce_states;
	struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
	enum amd_vce_level vce_level;
	enum amd_pm_state_type state;
	enum amd_pm_state_type user_state;
	enum amd_pm_state_type last_state;
	enum amd_pm_state_type last_user_state;
	u32                     platform_caps;
	u32                     voltage_response_time;
	u32                     backbias_response_time;
	void                    *priv;
	u32			new_active_crtcs;
	int			new_active_crtc_count;
	u32			current_active_crtcs;
	int			current_active_crtc_count;
	struct amdgpu_dpm_dynamic_state dyn_state;
	struct amdgpu_dpm_fan fan;
	u32 tdp_limit;
	u32 near_tdp_limit;
	u32 near_tdp_limit_adjusted;
	u32 sq_ramping_threshold;
	u32 cac_leakage;
	u16 tdp_od_limit;
	u32 tdp_adjustment;
	u16 load_line_slope;
	bool power_control;
	/* special states active */
	bool                    thermal_active;
	bool                    uvd_active;
	bool                    vce_active;
	/* thermal handling */
	struct amdgpu_dpm_thermal thermal;
	/* forced levels */
	enum amd_dpm_forced_level forced_level;
};

struct amdgpu_pm {
	struct mutex		mutex;
	u32                     current_sclk;
	u32                     current_mclk;
	u32                     default_sclk;
	u32                     default_mclk;
	struct amdgpu_i2c_chan *i2c_bus;
	/* internal thermal controller on rv6xx+ */
	enum amdgpu_int_thermal_type int_thermal_type;
	struct device	        *int_hwmon_dev;
	/* fan control parameters */
	bool                    no_fan;
	u8                      fan_pulses_per_revolution;
	u8                      fan_min_rpm;
	u8                      fan_max_rpm;
	/* dpm */
	bool                    dpm_enabled;
	bool                    sysfs_initialized;
	struct amdgpu_dpm       dpm;
	const struct firmware	*fw;	/* SMC firmware */
	uint32_t                fw_version;
	uint32_t                pcie_gen_mask;
	uint32_t                pcie_mlw_mask;
	struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
	uint32_t                smu_prv_buffer_size;
	struct amdgpu_bo        *smu_prv_buffer;
	bool ac_power;
};

#define R600_SSTU_DFLT                               0
#define R600_SST_DFLT                                0x00C8

/* XXX are these ok? */
#define R600_TEMP_RANGE_MIN (90 * 1000)
#define R600_TEMP_RANGE_MAX (120 * 1000)

#define FDO_PWM_MODE_STATIC  1
#define FDO_PWM_MODE_STATIC_RPM 5

enum amdgpu_td {
	AMDGPU_TD_AUTO,
	AMDGPU_TD_UP,
	AMDGPU_TD_DOWN,
};

enum amdgpu_display_watermark {
	AMDGPU_DISPLAY_WATERMARK_LOW = 0,
	AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
};

enum amdgpu_display_gap
{
    AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
    AMDGPU_PM_DISPLAY_GAP_VBLANK       = 1,
    AMDGPU_PM_DISPLAY_GAP_WATERMARK    = 2,
    AMDGPU_PM_DISPLAY_GAP_IGNORE       = 3,
};

void amdgpu_dpm_print_class_info(u32 class, u32 class2);
void amdgpu_dpm_print_cap_info(u32 caps);
void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
				struct amdgpu_ps *rps);
u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);

bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);

int amdgpu_get_platform_caps(struct amdgpu_device *adev);

int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
void amdgpu_free_extended_power_table(struct amdgpu_device *adev);

void amdgpu_add_thermal_controller(struct amdgpu_device *adev);

enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
						 u32 sys_mask,
						 enum amdgpu_pcie_gen asic_gen,
						 enum amdgpu_pcie_gen default_gen);

struct amd_vce_state*
amdgpu_get_vce_clock_state(void *handle, u32 idx);

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef __AMDGPU_DPM_H__
	24	#define __AMDGPU_DPM_H__
	25
cf097881 AD	26	enum amdgpu_int_thermal_type {
	27	THERMAL_TYPE_NONE,
	28	THERMAL_TYPE_EXTERNAL,
	29	THERMAL_TYPE_EXTERNAL_GPIO,
	30	THERMAL_TYPE_RV6XX,
	31	THERMAL_TYPE_RV770,
	32	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
	33	THERMAL_TYPE_EVERGREEN,
	34	THERMAL_TYPE_SUMO,
	35	THERMAL_TYPE_NI,
	36	THERMAL_TYPE_SI,
	37	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
	38	THERMAL_TYPE_CI,
	39	THERMAL_TYPE_KV,
	40	};
	41
	42	enum amdgpu_dpm_auto_throttle_src {
	43	AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
	44	AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
	45	};
	46
	47	enum amdgpu_dpm_event_src {
	48	AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
	49	AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
	50	AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
	51	AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
	52	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
	53	};
	54
cf097881 AD	55	struct amdgpu_ps {
	56	u32 caps; /* vbios flags */
	57	u32 class; /* vbios flags */
	58	u32 class2; /* vbios flags */
	59	/* UVD clocks */
	60	u32 vclk;
	61	u32 dclk;
	62	/* VCE clocks */
	63	u32 evclk;
	64	u32 ecclk;
	65	bool vce_active;
0d8de7ca	66	enum amd_vce_level vce_level;
cf097881 AD	67	/* asic priv */
	68	void *ps_priv;
	69	};
	70
	71	struct amdgpu_dpm_thermal {
	72	/* thermal interrupt work */
	73	struct work_struct work;
	74	/* low temperature threshold */
	75	int min_temp;
	76	/* high temperature threshold */
	77	int max_temp;
	78	/* was last interrupt low to high or high to low */
	79	bool high_to_low;
	80	/* interrupt source */
	81	struct amdgpu_irq_src irq;
	82	};
	83
	84	enum amdgpu_clk_action
	85	{
	86	AMDGPU_SCLK_UP = 1,
	87	AMDGPU_SCLK_DOWN
	88	};
	89
	90	struct amdgpu_blacklist_clocks
	91	{
	92	u32 sclk;
	93	u32 mclk;
	94	enum amdgpu_clk_action action;
	95	};
	96
	97	struct amdgpu_clock_and_voltage_limits {
	98	u32 sclk;
	99	u32 mclk;
	100	u16 vddc;
	101	u16 vddci;
	102	};
	103
	104	struct amdgpu_clock_array {
	105	u32 count;
	106	u32 *values;
	107	};
	108
	109	struct amdgpu_clock_voltage_dependency_entry {
	110	u32 clk;
	111	u16 v;
	112	};
	113
	114	struct amdgpu_clock_voltage_dependency_table {
	115	u32 count;
	116	struct amdgpu_clock_voltage_dependency_entry *entries;
	117	};
	118
	119	union amdgpu_cac_leakage_entry {
	120	struct {
	121	u16 vddc;
	122	u32 leakage;
	123	};
	124	struct {
	125	u16 vddc1;
	126	u16 vddc2;
	127	u16 vddc3;
	128	};
	129	};
	130
131	struct amdgpu_cac_leakage_table {
132	u32 count;
133	union amdgpu_cac_leakage_entry *entries;
134	};
135
136	struct amdgpu_phase_shedding_limits_entry {
137	u16 voltage;
138	u32 sclk;
139	u32 mclk;
140	};
141
142	struct amdgpu_phase_shedding_limits_table {
143	u32 count;
144	struct amdgpu_phase_shedding_limits_entry *entries;
145	};
146
147	struct amdgpu_uvd_clock_voltage_dependency_entry {
148	u32 vclk;
149	u32 dclk;
150	u16 v;
151	};
152
153	struct amdgpu_uvd_clock_voltage_dependency_table {
154	u8 count;
155	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
156	};
157
158	struct amdgpu_vce_clock_voltage_dependency_entry {
159	u32 ecclk;
160	u32 evclk;
161	u16 v;
162	};
163
164	struct amdgpu_vce_clock_voltage_dependency_table {
165	u8 count;
166	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
167	};
168
169	struct amdgpu_ppm_table {
170	u8 ppm_design;
171	u16 cpu_core_number;
172	u32 platform_tdp;
173	u32 small_ac_platform_tdp;
174	u32 platform_tdc;
175	u32 small_ac_platform_tdc;
176	u32 apu_tdp;
177	u32 dgpu_tdp;
178	u32 dgpu_ulv_power;
179	u32 tj_max;
180	};
181
182	struct amdgpu_cac_tdp_table {
183	u16 tdp;
184	u16 configurable_tdp;
185	u16 tdc;
186	u16 battery_power_limit;
187	u16 small_power_limit;
188	u16 low_cac_leakage;
189	u16 high_cac_leakage;
190	u16 maximum_power_delivery_limit;
191	};
192
193	struct amdgpu_dpm_dynamic_state {
194	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
195	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
196	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
197	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
198	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
199	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
200	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
201	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
202	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
203	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
204	struct amdgpu_clock_array valid_sclk_values;
205	struct amdgpu_clock_array valid_mclk_values;
206	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
207	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
208	u32 mclk_sclk_ratio;
209	u32 sclk_mclk_delta;
210	u16 vddc_vddci_delta;
211	u16 min_vddc_for_pcie_gen2;
212	struct amdgpu_cac_leakage_table cac_leakage_table;
213	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
214	struct amdgpu_ppm_table *ppm_table;
215	struct amdgpu_cac_tdp_table *cac_tdp_table;
216	};
217
218	struct amdgpu_dpm_fan {
219	u16 t_min;
220	u16 t_med;
221	u16 t_high;
222	u16 pwm_min;
223	u16 pwm_med;
224	u16 pwm_high;
225	u8 t_hyst;
226	u32 cycle_delay;
227	u16 t_max;
228	u8 control_mode;
229	u16 default_max_fan_pwm;
230	u16 default_fan_output_sensitivity;
231	u16 fan_output_sensitivity;
232	bool ucode_fan_control;
233	};
234
235	enum amdgpu_pcie_gen {
236	AMDGPU_PCIE_GEN1 = 0,
237	AMDGPU_PCIE_GEN2 = 1,
238	AMDGPU_PCIE_GEN3 = 2,
239	AMDGPU_PCIE_GEN_INVALID = 0xffff
240	};
241
cd4d7464 RZ	242	#define amdgpu_dpm_pre_set_power_state(adev) \
	243	((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
	244
	245	#define amdgpu_dpm_set_power_state(adev) \
	246	((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
	247
	248	#define amdgpu_dpm_post_set_power_state(adev) \
	249	((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
	250
	251	#define amdgpu_dpm_display_configuration_changed(adev) \
	252	((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
	253
	254	#define amdgpu_dpm_print_power_state(adev, ps) \
	255	((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
	256
	257	#define amdgpu_dpm_vblank_too_short(adev) \
	258	((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
	259
	260	#define amdgpu_dpm_enable_bapm(adev, e) \
	261	((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
cf097881	262
9f8df7d7	263	#define amdgpu_dpm_read_sensor(adev, idx, value, size) \
cd4d7464	264	((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
cf097881	265
cf097881	266	#define amdgpu_dpm_set_fan_control_mode(adev, m) \
cd4d7464	267	((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
cf097881 AD	268
cf097881 AD	269	#define amdgpu_dpm_get_fan_control_mode(adev) \
cd4d7464	270	((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
cf097881 AD	271
cf097881 AD	272	#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
cd4d7464	273	((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
cf097881 AD	274
cf097881 AD	275	#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
cd4d7464	276	((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
cf097881	277
81c1514b	278	#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
cd4d7464	279	((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
81c1514b	280
c2870527 RZ	281	#define amdgpu_dpm_set_fan_speed_rpm(adev, s) \
	282	((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
	283
cf097881	284	#define amdgpu_dpm_get_sclk(adev, l) \
cd4d7464	285	((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
cf097881 AD	286
cf097881 AD	287	#define amdgpu_dpm_get_mclk(adev, l) \
cd4d7464	288	((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
cf097881 AD	289
cf097881 AD	290	#define amdgpu_dpm_force_performance_level(adev, l) \
cd4d7464	291	((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
cf097881	292
cf097881	293	#define amdgpu_dpm_get_current_power_state(adev) \
cd4d7464	294	((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
cf097881	295
cf097881	296	#define amdgpu_dpm_get_pp_num_states(adev, data) \
cd4d7464	297	((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
cf097881 AD	298
cf097881 AD	299	#define amdgpu_dpm_get_pp_table(adev, table) \
cd4d7464	300	((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
cf097881 AD	301
cf097881 AD	302	#define amdgpu_dpm_set_pp_table(adev, buf, size) \
cd4d7464	303	((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
cf097881 AD	304
cf097881 AD	305	#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
cd4d7464	306	((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
cf097881 AD	307
cf097881 AD	308	#define amdgpu_dpm_force_clock_level(adev, type, level) \
cd4d7464	309	((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
cf097881 AD	310
cf097881 AD	311	#define amdgpu_dpm_get_sclk_od(adev) \
cd4d7464	312	((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
cf097881 AD	313
cf097881 AD	314	#define amdgpu_dpm_set_sclk_od(adev, value) \
cd4d7464	315	((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
cf097881 AD	316
cf097881 AD	317	#define amdgpu_dpm_get_mclk_od(adev) \
cd4d7464	318	((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
cf097881 AD	319
cf097881 AD	320	#define amdgpu_dpm_set_mclk_od(adev, value) \
cd4d7464	321	((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
cf097881	322
39199b80 EQ	323	#define amdgpu_dpm_dispatch_task(adev, task_id, user_state) \
39199b80 EQ	324	((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state))
cf097881	325
cd4d7464 RZ	326	#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
cd4d7464 RZ	327	((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
fbebf2c6	328
230cf1ba	329	#define amdgpu_dpm_get_vce_clock_state(adev, i) \
cd4d7464	330	((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
cf097881	331
cd4d7464 RZ	332	#define amdgpu_dpm_get_performance_level(adev) \
cd4d7464 RZ	333	((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
e5d03ac2	334
34bb2734	335	#define amdgpu_dpm_reset_power_profile_state(adev, request) \
cd4d7464	336	((adev)->powerplay.pp_funcs->reset_power_profile_state(\
34bb2734 EH	337	(adev)->powerplay.pp_handle, request))
34bb2734 EH	338
052fe96d	339	#define amdgpu_dpm_switch_power_profile(adev, type, en) \
cd4d7464	340	((adev)->powerplay.pp_funcs->switch_power_profile(\
052fe96d	341	(adev)->powerplay.pp_handle, type, en))
34bb2734	342
3811f8f0 RZ	343	#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
	344	((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
	345	(adev)->powerplay.pp_handle, msg_id))
	346
b92c6287 RZ	347	#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
	348	((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
	349	(adev)->powerplay.pp_handle, block_type, gate))
	350
37c5c4db RZ	351	#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
	352	((adev)->powerplay.pp_funcs->get_power_profile_mode(\
	353	(adev)->powerplay.pp_handle, buf))
	354
	355	#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
	356	((adev)->powerplay.pp_funcs->set_power_profile_mode(\
	357	(adev)->powerplay.pp_handle, parameter, size))
	358
e3933f26 RZ	359	#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
	360	((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
	361	(adev)->powerplay.pp_handle, type, parameter, size))
	362
b55c9e7a EQ	363	#define amdgpu_dpm_enable_mgpu_fan_boost(adev) \
	364	((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
	365	(adev)->powerplay.pp_handle))
	366
7ca881a8 EQ	367	#define amdgpu_dpm_get_ppfeature_status(adev, buf) \
	368	((adev)->powerplay.pp_funcs->get_ppfeature_status(\
	369	(adev)->powerplay.pp_handle, (buf)))
	370
	371	#define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \
	372	((adev)->powerplay.pp_funcs->set_ppfeature_status(\
	373	(adev)->powerplay.pp_handle, (ppfeatures)))
	374
cf097881 AD	375	struct amdgpu_dpm {
	376	struct amdgpu_ps *ps;
	377	/* number of valid power states */
	378	int num_ps;
	379	/* current power state that is active */
	380	struct amdgpu_ps *current_ps;
	381	/* requested power state */
	382	struct amdgpu_ps *requested_ps;
	383	/* boot up power state */
	384	struct amdgpu_ps *boot_ps;
	385	/* default uvd power state */
	386	struct amdgpu_ps *uvd_ps;
	387	/* vce requirements */
66ba1afd	388	u32 num_of_vce_states;
0d8de7ca RZ	389	struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
0d8de7ca RZ	390	enum amd_vce_level vce_level;
cf097881 AD	391	enum amd_pm_state_type state;
cf097881 AD	392	enum amd_pm_state_type user_state;
86f8c599 RZ	393	enum amd_pm_state_type last_state;
86f8c599 RZ	394	enum amd_pm_state_type last_user_state;
cf097881 AD	395	u32 platform_caps;
	396	u32 voltage_response_time;
	397	u32 backbias_response_time;
	398	void *priv;
	399	u32 new_active_crtcs;
	400	int new_active_crtc_count;
	401	u32 current_active_crtcs;
	402	int current_active_crtc_count;
	403	struct amdgpu_dpm_dynamic_state dyn_state;
	404	struct amdgpu_dpm_fan fan;
	405	u32 tdp_limit;
	406	u32 near_tdp_limit;
	407	u32 near_tdp_limit_adjusted;
	408	u32 sq_ramping_threshold;
	409	u32 cac_leakage;
	410	u16 tdp_od_limit;
	411	u32 tdp_adjustment;
	412	u16 load_line_slope;
	413	bool power_control;
cf097881 AD	414	/* special states active */
	415	bool thermal_active;
	416	bool uvd_active;
	417	bool vce_active;
	418	/* thermal handling */
	419	struct amdgpu_dpm_thermal thermal;
	420	/* forced levels */
e5d03ac2	421	enum amd_dpm_forced_level forced_level;
cf097881 AD	422	};
	423
	424	struct amdgpu_pm {
	425	struct mutex mutex;
	426	u32 current_sclk;
	427	u32 current_mclk;
	428	u32 default_sclk;
	429	u32 default_mclk;
	430	struct amdgpu_i2c_chan *i2c_bus;
	431	/* internal thermal controller on rv6xx+ */
	432	enum amdgpu_int_thermal_type int_thermal_type;
	433	struct device *int_hwmon_dev;
	434	/* fan control parameters */
	435	bool no_fan;
	436	u8 fan_pulses_per_revolution;
	437	u8 fan_min_rpm;
	438	u8 fan_max_rpm;
	439	/* dpm */
	440	bool dpm_enabled;
	441	bool sysfs_initialized;
	442	struct amdgpu_dpm dpm;
	443	const struct firmware fw; / SMC firmware */
	444	uint32_t fw_version;
cf097881 AD	445	uint32_t pcie_gen_mask;
cf097881 AD	446	uint32_t pcie_mlw_mask;
4562236b	447	struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
7951e376 RZ	448	uint32_t smu_prv_buffer_size;
7951e376 RZ	449	struct amdgpu_bo *smu_prv_buffer;
600ae890	450	bool ac_power;
cf097881 AD	451	};
cf097881 AD	452
d38ceaf9 AD	453	#define R600_SSTU_DFLT 0
	454	#define R600_SST_DFLT 0x00C8
	455
	456	/* XXX are these ok? */
	457	#define R600_TEMP_RANGE_MIN (90 * 1000)
	458	#define R600_TEMP_RANGE_MAX (120 * 1000)
	459
	460	#define FDO_PWM_MODE_STATIC 1
	461	#define FDO_PWM_MODE_STATIC_RPM 5
	462
	463	enum amdgpu_td {
	464	AMDGPU_TD_AUTO,
	465	AMDGPU_TD_UP,
	466	AMDGPU_TD_DOWN,
	467	};
	468
	469	enum amdgpu_display_watermark {
	470	AMDGPU_DISPLAY_WATERMARK_LOW = 0,
	471	AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
	472	};
	473
	474	enum amdgpu_display_gap
	475	{
	476	AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
	477	AMDGPU_PM_DISPLAY_GAP_VBLANK = 1,
	478	AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2,
	479	AMDGPU_PM_DISPLAY_GAP_IGNORE = 3,
	480	};
	481
	482	void amdgpu_dpm_print_class_info(u32 class, u32 class2);
	483	void amdgpu_dpm_print_cap_info(u32 caps);
	484	void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
	485	struct amdgpu_ps *rps);
	486	u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
	487	u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
d91ea496	488	void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
d38ceaf9 AD	489
	490	bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
	491
	492	int amdgpu_get_platform_caps(struct amdgpu_device *adev);
	493
	494	int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
	495	void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
	496
	497	void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
	498
	499	enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
	500	u32 sys_mask,
	501	enum amdgpu_pcie_gen asic_gen,
	502	enum amdgpu_pcie_gen default_gen);
	503
825cc997	504	struct amd_vce_state*
cfa289fd	505	amdgpu_get_vce_clock_state(void *handle, u32 idx);
825cc997	506
d38ceaf9	507	#endif