[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_dpm.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef __AMDGPU_DPM_H__
#define __AMDGPU_DPM_H__

enum amdgpu_int_thermal_type {
	THERMAL_TYPE_NONE,
	THERMAL_TYPE_EXTERNAL,
	THERMAL_TYPE_EXTERNAL_GPIO,
	THERMAL_TYPE_RV6XX,
	THERMAL_TYPE_RV770,
	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
	THERMAL_TYPE_EVERGREEN,
	THERMAL_TYPE_SUMO,
	THERMAL_TYPE_NI,
	THERMAL_TYPE_SI,
	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
	THERMAL_TYPE_CI,
	THERMAL_TYPE_KV,
};

enum amdgpu_dpm_auto_throttle_src {
	AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
	AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
};

enum amdgpu_dpm_event_src {
	AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
	AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
	AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
	AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
};

struct amdgpu_ps {
	u32 caps; /* vbios flags */
	u32 class; /* vbios flags */
	u32 class2; /* vbios flags */
	/* UVD clocks */
	u32 vclk;
	u32 dclk;
	/* VCE clocks */
	u32 evclk;
	u32 ecclk;
	bool vce_active;
	enum amd_vce_level vce_level;
	/* asic priv */
	void *ps_priv;
};

struct amdgpu_dpm_thermal {
	/* thermal interrupt work */
	struct work_struct work;
	/* low temperature threshold */
	int                min_temp;
	/* high temperature threshold */
	int                max_temp;
	/* edge max emergency(shutdown) temp */
	int                max_edge_emergency_temp;
	/* hotspot low temperature threshold */
	int                min_hotspot_temp;
	/* hotspot high temperature critical threshold */
	int                max_hotspot_crit_temp;
	/* hotspot max emergency(shutdown) temp */
	int                max_hotspot_emergency_temp;
	/* memory low temperature threshold */
	int                min_mem_temp;
	/* memory high temperature critical threshold */
	int                max_mem_crit_temp;
	/* memory max emergency(shutdown) temp */
	int                max_mem_emergency_temp;
	/* was last interrupt low to high or high to low */
	bool               high_to_low;
	/* interrupt source */
	struct amdgpu_irq_src	irq;
};

enum amdgpu_clk_action
{
	AMDGPU_SCLK_UP = 1,
	AMDGPU_SCLK_DOWN
};

struct amdgpu_blacklist_clocks
{
	u32 sclk;
	u32 mclk;
	enum amdgpu_clk_action action;
};

struct amdgpu_clock_and_voltage_limits {
	u32 sclk;
	u32 mclk;
	u16 vddc;
	u16 vddci;
};

struct amdgpu_clock_array {
	u32 count;
	u32 *values;
};

struct amdgpu_clock_voltage_dependency_entry {
	u32 clk;
	u16 v;
};

struct amdgpu_clock_voltage_dependency_table {
	u32 count;
	struct amdgpu_clock_voltage_dependency_entry *entries;
};

union amdgpu_cac_leakage_entry {
	struct {
		u16 vddc;
		u32 leakage;
	};
	struct {
		u16 vddc1;
		u16 vddc2;
		u16 vddc3;
	};
};

struct amdgpu_cac_leakage_table {
	u32 count;
	union amdgpu_cac_leakage_entry *entries;
};

struct amdgpu_phase_shedding_limits_entry {
	u16 voltage;
	u32 sclk;
	u32 mclk;
};

struct amdgpu_phase_shedding_limits_table {
	u32 count;
	struct amdgpu_phase_shedding_limits_entry *entries;
};

struct amdgpu_uvd_clock_voltage_dependency_entry {
	u32 vclk;
	u32 dclk;
	u16 v;
};

struct amdgpu_uvd_clock_voltage_dependency_table {
	u8 count;
	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
};

struct amdgpu_vce_clock_voltage_dependency_entry {
	u32 ecclk;
	u32 evclk;
	u16 v;
};

struct amdgpu_vce_clock_voltage_dependency_table {
	u8 count;
	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
};

struct amdgpu_ppm_table {
	u8 ppm_design;
	u16 cpu_core_number;
	u32 platform_tdp;
	u32 small_ac_platform_tdp;
	u32 platform_tdc;
	u32 small_ac_platform_tdc;
	u32 apu_tdp;
	u32 dgpu_tdp;
	u32 dgpu_ulv_power;
	u32 tj_max;
};

struct amdgpu_cac_tdp_table {
	u16 tdp;
	u16 configurable_tdp;
	u16 tdc;
	u16 battery_power_limit;
	u16 small_power_limit;
	u16 low_cac_leakage;
	u16 high_cac_leakage;
	u16 maximum_power_delivery_limit;
};

struct amdgpu_dpm_dynamic_state {
	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
	struct amdgpu_clock_array valid_sclk_values;
	struct amdgpu_clock_array valid_mclk_values;
	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
	u32 mclk_sclk_ratio;
	u32 sclk_mclk_delta;
	u16 vddc_vddci_delta;
	u16 min_vddc_for_pcie_gen2;
	struct amdgpu_cac_leakage_table cac_leakage_table;
	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
	struct amdgpu_ppm_table *ppm_table;
	struct amdgpu_cac_tdp_table *cac_tdp_table;
};

struct amdgpu_dpm_fan {
	u16 t_min;
	u16 t_med;
	u16 t_high;
	u16 pwm_min;
	u16 pwm_med;
	u16 pwm_high;
	u8 t_hyst;
	u32 cycle_delay;
	u16 t_max;
	u8 control_mode;
	u16 default_max_fan_pwm;
	u16 default_fan_output_sensitivity;
	u16 fan_output_sensitivity;
	bool ucode_fan_control;
};

enum amdgpu_pcie_gen {
	AMDGPU_PCIE_GEN1 = 0,
	AMDGPU_PCIE_GEN2 = 1,
	AMDGPU_PCIE_GEN3 = 2,
	AMDGPU_PCIE_GEN_INVALID = 0xffff
};

#define amdgpu_dpm_pre_set_power_state(adev) \
		((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_power_state(adev) \
		((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))

#define amdgpu_dpm_post_set_power_state(adev) \
		((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))

#define amdgpu_dpm_display_configuration_changed(adev) \
		((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))

#define amdgpu_dpm_print_power_state(adev, ps) \
		((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))

#define amdgpu_dpm_vblank_too_short(adev) \
		((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))

#define amdgpu_dpm_enable_bapm(adev, e) \
		((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))

#define amdgpu_dpm_set_fan_control_mode(adev, m) \
		((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))

#define amdgpu_dpm_get_fan_control_mode(adev) \
		((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
		((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))

#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
		((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))

#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
		((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))

#define amdgpu_dpm_set_fan_speed_rpm(adev, s) \
		((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))

#define amdgpu_dpm_force_performance_level(adev, l) \
		((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))

#define amdgpu_dpm_get_current_power_state(adev) \
		((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))

#define amdgpu_smu_get_current_power_state(adev) \
		((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))

#define amdgpu_smu_set_power_state(adev) \
		((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))

#define amdgpu_dpm_get_pp_num_states(adev, data) \
		((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))

#define amdgpu_dpm_get_pp_table(adev, table) \
		((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))

#define amdgpu_dpm_set_pp_table(adev, buf, size) \
		((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))

#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
		((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))

#define amdgpu_dpm_force_clock_level(adev, type, level) \
		((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))

#define amdgpu_dpm_get_sclk_od(adev) \
		((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_sclk_od(adev, value) \
		((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))

#define amdgpu_dpm_get_mclk_od(adev) \
		((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))

#define amdgpu_dpm_set_mclk_od(adev, value) \
		((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))

#define amdgpu_dpm_dispatch_task(adev, task_id, user_state)		\
		((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state))

#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
		((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))

#define amdgpu_dpm_get_vce_clock_state(adev, i)				\
		((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))

#define amdgpu_dpm_get_performance_level(adev)				\
		((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))

#define amdgpu_dpm_reset_power_profile_state(adev, request) \
		((adev)->powerplay.pp_funcs->reset_power_profile_state(\
			(adev)->powerplay.pp_handle, request))

#define amdgpu_dpm_switch_power_profile(adev, type, en) \
		((adev)->powerplay.pp_funcs->switch_power_profile(\
			(adev)->powerplay.pp_handle, type, en))

#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
			(adev)->powerplay.pp_handle, msg_id))

#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
		((adev)->powerplay.pp_funcs->get_power_profile_mode(\
			(adev)->powerplay.pp_handle, buf))

#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
		((adev)->powerplay.pp_funcs->set_power_profile_mode(\
			(adev)->powerplay.pp_handle, parameter, size))

#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
		((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
			(adev)->powerplay.pp_handle, type, parameter, size))

#define amdgpu_dpm_enable_mgpu_fan_boost(adev) \
		((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
			(adev)->powerplay.pp_handle))

#define amdgpu_dpm_get_ppfeature_status(adev, buf) \
		((adev)->powerplay.pp_funcs->get_ppfeature_status(\
			(adev)->powerplay.pp_handle, (buf)))

#define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \
		((adev)->powerplay.pp_funcs->set_ppfeature_status(\
			(adev)->powerplay.pp_handle, (ppfeatures)))

struct amdgpu_dpm {
	struct amdgpu_ps        *ps;
	/* number of valid power states */
	int                     num_ps;
	/* current power state that is active */
	struct amdgpu_ps        *current_ps;
	/* requested power state */
	struct amdgpu_ps        *requested_ps;
	/* boot up power state */
	struct amdgpu_ps        *boot_ps;
	/* default uvd power state */
	struct amdgpu_ps        *uvd_ps;
	/* vce requirements */
	u32                  num_of_vce_states;
	struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
	enum amd_vce_level vce_level;
	enum amd_pm_state_type state;
	enum amd_pm_state_type user_state;
	enum amd_pm_state_type last_state;
	enum amd_pm_state_type last_user_state;
	u32                     platform_caps;
	u32                     voltage_response_time;
	u32                     backbias_response_time;
	void                    *priv;
	u32			new_active_crtcs;
	int			new_active_crtc_count;
	u32			current_active_crtcs;
	int			current_active_crtc_count;
	struct amdgpu_dpm_dynamic_state dyn_state;
	struct amdgpu_dpm_fan fan;
	u32 tdp_limit;
	u32 near_tdp_limit;
	u32 near_tdp_limit_adjusted;
	u32 sq_ramping_threshold;
	u32 cac_leakage;
	u16 tdp_od_limit;
	u32 tdp_adjustment;
	u16 load_line_slope;
	bool power_control;
	/* special states active */
	bool                    thermal_active;
	bool                    uvd_active;
	bool                    vce_active;
	/* thermal handling */
	struct amdgpu_dpm_thermal thermal;
	/* forced levels */
	enum amd_dpm_forced_level forced_level;
};

struct amdgpu_pm {
	struct mutex		mutex;
	u32                     current_sclk;
	u32                     current_mclk;
	u32                     default_sclk;
	u32                     default_mclk;
	struct amdgpu_i2c_chan *i2c_bus;
	/* internal thermal controller on rv6xx+ */
	enum amdgpu_int_thermal_type int_thermal_type;
	struct device	        *int_hwmon_dev;
	/* fan control parameters */
	bool                    no_fan;
	u8                      fan_pulses_per_revolution;
	u8                      fan_min_rpm;
	u8                      fan_max_rpm;
	/* dpm */
	bool                    dpm_enabled;
	bool                    sysfs_initialized;
	struct amdgpu_dpm       dpm;
	const struct firmware	*fw;	/* SMC firmware */
	uint32_t                fw_version;
	uint32_t                pcie_gen_mask;
	uint32_t                pcie_mlw_mask;
	struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
	uint32_t                smu_prv_buffer_size;
	struct amdgpu_bo        *smu_prv_buffer;
	bool ac_power;
	/* powerplay feature */
	uint32_t pp_feature;

};

#define R600_SSTU_DFLT                               0
#define R600_SST_DFLT                                0x00C8

/* XXX are these ok? */
#define R600_TEMP_RANGE_MIN (90 * 1000)
#define R600_TEMP_RANGE_MAX (120 * 1000)

#define FDO_PWM_MODE_STATIC  1
#define FDO_PWM_MODE_STATIC_RPM 5

enum amdgpu_td {
	AMDGPU_TD_AUTO,
	AMDGPU_TD_UP,
	AMDGPU_TD_DOWN,
};

enum amdgpu_display_watermark {
	AMDGPU_DISPLAY_WATERMARK_LOW = 0,
	AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
};

enum amdgpu_display_gap
{
    AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
    AMDGPU_PM_DISPLAY_GAP_VBLANK       = 1,
    AMDGPU_PM_DISPLAY_GAP_WATERMARK    = 2,
    AMDGPU_PM_DISPLAY_GAP_IGNORE       = 3,
};

void amdgpu_dpm_print_class_info(u32 class, u32 class2);
void amdgpu_dpm_print_cap_info(u32 caps);
void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
				struct amdgpu_ps *rps);
u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
			   void *data, uint32_t *size);

bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);

int amdgpu_get_platform_caps(struct amdgpu_device *adev);

int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
void amdgpu_free_extended_power_table(struct amdgpu_device *adev);

void amdgpu_add_thermal_controller(struct amdgpu_device *adev);

enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
						 u32 sys_mask,
						 enum amdgpu_pcie_gen asic_gen,
						 enum amdgpu_pcie_gen default_gen);

struct amd_vce_state*
amdgpu_get_vce_clock_state(void *handle, u32 idx);

int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
				      uint32_t block_type, bool gate);

extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);

extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef __AMDGPU_DPM_H__
	24	#define __AMDGPU_DPM_H__
	25
cf097881 AD	26	enum amdgpu_int_thermal_type {
	27	THERMAL_TYPE_NONE,
	28	THERMAL_TYPE_EXTERNAL,
	29	THERMAL_TYPE_EXTERNAL_GPIO,
	30	THERMAL_TYPE_RV6XX,
	31	THERMAL_TYPE_RV770,
	32	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
	33	THERMAL_TYPE_EVERGREEN,
	34	THERMAL_TYPE_SUMO,
	35	THERMAL_TYPE_NI,
	36	THERMAL_TYPE_SI,
	37	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
	38	THERMAL_TYPE_CI,
	39	THERMAL_TYPE_KV,
	40	};
	41
	42	enum amdgpu_dpm_auto_throttle_src {
	43	AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
	44	AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
	45	};
	46
	47	enum amdgpu_dpm_event_src {
	48	AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
	49	AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
	50	AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
	51	AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
	52	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
	53	};
	54
cf097881 AD	55	struct amdgpu_ps {
	56	u32 caps; /* vbios flags */
	57	u32 class; /* vbios flags */
	58	u32 class2; /* vbios flags */
	59	/* UVD clocks */
	60	u32 vclk;
	61	u32 dclk;
	62	/* VCE clocks */
	63	u32 evclk;
	64	u32 ecclk;
	65	bool vce_active;
0d8de7ca	66	enum amd_vce_level vce_level;
cf097881 AD	67	/* asic priv */
	68	void *ps_priv;
	69	};
	70
	71	struct amdgpu_dpm_thermal {
	72	/* thermal interrupt work */
	73	struct work_struct work;
	74	/* low temperature threshold */
	75	int min_temp;
	76	/* high temperature threshold */
	77	int max_temp;
901cb599 EQ	78	/* edge max emergency(shutdown) temp */
901cb599 EQ	79	int max_edge_emergency_temp;
437ccd17 EQ	80	/* hotspot low temperature threshold */
	81	int min_hotspot_temp;
	82	/* hotspot high temperature critical threshold */
	83	int max_hotspot_crit_temp;
901cb599 EQ	84	/* hotspot max emergency(shutdown) temp */
901cb599 EQ	85	int max_hotspot_emergency_temp;
437ccd17 EQ	86	/* memory low temperature threshold */
	87	int min_mem_temp;
	88	/* memory high temperature critical threshold */
	89	int max_mem_crit_temp;
901cb599 EQ	90	/* memory max emergency(shutdown) temp */
901cb599 EQ	91	int max_mem_emergency_temp;
cf097881 AD	92	/* was last interrupt low to high or high to low */
	93	bool high_to_low;
	94	/* interrupt source */
	95	struct amdgpu_irq_src irq;
	96	};
	97
	98	enum amdgpu_clk_action
	99	{
	100	AMDGPU_SCLK_UP = 1,
	101	AMDGPU_SCLK_DOWN
	102	};
	103
	104	struct amdgpu_blacklist_clocks
	105	{
	106	u32 sclk;
	107	u32 mclk;
	108	enum amdgpu_clk_action action;
	109	};
	110
	111	struct amdgpu_clock_and_voltage_limits {
	112	u32 sclk;
	113	u32 mclk;
	114	u16 vddc;
	115	u16 vddci;
	116	};
	117
	118	struct amdgpu_clock_array {
	119	u32 count;
	120	u32 *values;
	121	};
	122
	123	struct amdgpu_clock_voltage_dependency_entry {
	124	u32 clk;
	125	u16 v;
	126	};
	127
	128	struct amdgpu_clock_voltage_dependency_table {
	129	u32 count;
	130	struct amdgpu_clock_voltage_dependency_entry *entries;
	131	};
	132
	133	union amdgpu_cac_leakage_entry {
	134	struct {
	135	u16 vddc;
	136	u32 leakage;
	137	};
	138	struct {
	139	u16 vddc1;
	140	u16 vddc2;
	141	u16 vddc3;
	142	};
	143	};
	144
	145	struct amdgpu_cac_leakage_table {
	146	u32 count;
	147	union amdgpu_cac_leakage_entry *entries;
	148	};
	149
	150	struct amdgpu_phase_shedding_limits_entry {
	151	u16 voltage;
	152	u32 sclk;
	153	u32 mclk;
	154	};
	155
156	struct amdgpu_phase_shedding_limits_table {
157	u32 count;
158	struct amdgpu_phase_shedding_limits_entry *entries;
159	};
160
161	struct amdgpu_uvd_clock_voltage_dependency_entry {
162	u32 vclk;
163	u32 dclk;
164	u16 v;
165	};
166
167	struct amdgpu_uvd_clock_voltage_dependency_table {
168	u8 count;
169	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
170	};
171
172	struct amdgpu_vce_clock_voltage_dependency_entry {
173	u32 ecclk;
174	u32 evclk;
175	u16 v;
176	};
177
178	struct amdgpu_vce_clock_voltage_dependency_table {
179	u8 count;
180	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
181	};
182
183	struct amdgpu_ppm_table {
184	u8 ppm_design;
185	u16 cpu_core_number;
186	u32 platform_tdp;
187	u32 small_ac_platform_tdp;
188	u32 platform_tdc;
189	u32 small_ac_platform_tdc;
190	u32 apu_tdp;
191	u32 dgpu_tdp;
192	u32 dgpu_ulv_power;
193	u32 tj_max;
194	};
195
196	struct amdgpu_cac_tdp_table {
197	u16 tdp;
198	u16 configurable_tdp;
199	u16 tdc;
200	u16 battery_power_limit;
201	u16 small_power_limit;
202	u16 low_cac_leakage;
203	u16 high_cac_leakage;
204	u16 maximum_power_delivery_limit;
205	};
206
207	struct amdgpu_dpm_dynamic_state {
208	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
209	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
210	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
211	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
212	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
213	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
214	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
215	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
216	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
217	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
218	struct amdgpu_clock_array valid_sclk_values;
219	struct amdgpu_clock_array valid_mclk_values;
220	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
221	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
222	u32 mclk_sclk_ratio;
223	u32 sclk_mclk_delta;
224	u16 vddc_vddci_delta;
225	u16 min_vddc_for_pcie_gen2;
226	struct amdgpu_cac_leakage_table cac_leakage_table;
227	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
228	struct amdgpu_ppm_table *ppm_table;
229	struct amdgpu_cac_tdp_table *cac_tdp_table;
230	};
231
232	struct amdgpu_dpm_fan {
233	u16 t_min;
234	u16 t_med;
235	u16 t_high;
236	u16 pwm_min;
237	u16 pwm_med;
238	u16 pwm_high;
239	u8 t_hyst;
240	u32 cycle_delay;
241	u16 t_max;
242	u8 control_mode;
243	u16 default_max_fan_pwm;
244	u16 default_fan_output_sensitivity;
245	u16 fan_output_sensitivity;
246	bool ucode_fan_control;
247	};
248
249	enum amdgpu_pcie_gen {
250	AMDGPU_PCIE_GEN1 = 0,
251	AMDGPU_PCIE_GEN2 = 1,
252	AMDGPU_PCIE_GEN3 = 2,
253	AMDGPU_PCIE_GEN_INVALID = 0xffff
254	};
255
cd4d7464 RZ	256	#define amdgpu_dpm_pre_set_power_state(adev) \
	257	((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
	258
	259	#define amdgpu_dpm_set_power_state(adev) \
	260	((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
	261
	262	#define amdgpu_dpm_post_set_power_state(adev) \
	263	((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
	264
	265	#define amdgpu_dpm_display_configuration_changed(adev) \
	266	((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
	267
	268	#define amdgpu_dpm_print_power_state(adev, ps) \
	269	((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
	270
	271	#define amdgpu_dpm_vblank_too_short(adev) \
	272	((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
	273
	274	#define amdgpu_dpm_enable_bapm(adev, e) \
	275	((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
cf097881	276
cf097881	277	#define amdgpu_dpm_set_fan_control_mode(adev, m) \
cd4d7464	278	((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
cf097881 AD	279
cf097881 AD	280	#define amdgpu_dpm_get_fan_control_mode(adev) \
cd4d7464	281	((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
cf097881 AD	282
cf097881 AD	283	#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
cd4d7464	284	((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
cf097881 AD	285
cf097881 AD	286	#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
cd4d7464	287	((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
cf097881	288
81c1514b	289	#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
cd4d7464	290	((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
81c1514b	291
c2870527 RZ	292	#define amdgpu_dpm_set_fan_speed_rpm(adev, s) \
	293	((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
	294
cf097881	295	#define amdgpu_dpm_force_performance_level(adev, l) \
cd4d7464	296	((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
cf097881	297
cf097881	298	#define amdgpu_dpm_get_current_power_state(adev) \
cd4d7464	299	((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
cf097881	300
8554e67d CG	301	#define amdgpu_smu_get_current_power_state(adev) \
	302	((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
	303
	304	#define amdgpu_smu_set_power_state(adev) \
	305	((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
	306
cf097881	307	#define amdgpu_dpm_get_pp_num_states(adev, data) \
cd4d7464	308	((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
cf097881 AD	309
cf097881 AD	310	#define amdgpu_dpm_get_pp_table(adev, table) \
cd4d7464	311	((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
cf097881 AD	312
cf097881 AD	313	#define amdgpu_dpm_set_pp_table(adev, buf, size) \
cd4d7464	314	((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
cf097881 AD	315
cf097881 AD	316	#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
cd4d7464	317	((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
cf097881 AD	318
cf097881 AD	319	#define amdgpu_dpm_force_clock_level(adev, type, level) \
cd4d7464	320	((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
cf097881 AD	321
cf097881 AD	322	#define amdgpu_dpm_get_sclk_od(adev) \
cd4d7464	323	((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
cf097881 AD	324
cf097881 AD	325	#define amdgpu_dpm_set_sclk_od(adev, value) \
cd4d7464	326	((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
cf097881 AD	327
cf097881 AD	328	#define amdgpu_dpm_get_mclk_od(adev) \
cd4d7464	329	((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
cf097881 AD	330
cf097881 AD	331	#define amdgpu_dpm_set_mclk_od(adev, value) \
cd4d7464	332	((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
cf097881	333
39199b80 EQ	334	#define amdgpu_dpm_dispatch_task(adev, task_id, user_state) \
39199b80 EQ	335	((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state))
cf097881	336
cd4d7464 RZ	337	#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
cd4d7464 RZ	338	((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
fbebf2c6	339
230cf1ba	340	#define amdgpu_dpm_get_vce_clock_state(adev, i) \
cd4d7464	341	((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
cf097881	342
cd4d7464 RZ	343	#define amdgpu_dpm_get_performance_level(adev) \
cd4d7464 RZ	344	((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
e5d03ac2	345
34bb2734	346	#define amdgpu_dpm_reset_power_profile_state(adev, request) \
cd4d7464	347	((adev)->powerplay.pp_funcs->reset_power_profile_state(\
34bb2734 EH	348	(adev)->powerplay.pp_handle, request))
34bb2734 EH	349
052fe96d	350	#define amdgpu_dpm_switch_power_profile(adev, type, en) \
cd4d7464	351	((adev)->powerplay.pp_funcs->switch_power_profile(\
052fe96d	352	(adev)->powerplay.pp_handle, type, en))
34bb2734	353
3811f8f0 RZ	354	#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
	355	((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
	356	(adev)->powerplay.pp_handle, msg_id))
	357
37c5c4db RZ	358	#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
	359	((adev)->powerplay.pp_funcs->get_power_profile_mode(\
	360	(adev)->powerplay.pp_handle, buf))
	361
	362	#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
	363	((adev)->powerplay.pp_funcs->set_power_profile_mode(\
	364	(adev)->powerplay.pp_handle, parameter, size))
	365
e3933f26 RZ	366	#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
	367	((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
	368	(adev)->powerplay.pp_handle, type, parameter, size))
	369
b55c9e7a EQ	370	#define amdgpu_dpm_enable_mgpu_fan_boost(adev) \
	371	((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
	372	(adev)->powerplay.pp_handle))
	373
7ca881a8 EQ	374	#define amdgpu_dpm_get_ppfeature_status(adev, buf) \
	375	((adev)->powerplay.pp_funcs->get_ppfeature_status(\
	376	(adev)->powerplay.pp_handle, (buf)))
	377
	378	#define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \
	379	((adev)->powerplay.pp_funcs->set_ppfeature_status(\
	380	(adev)->powerplay.pp_handle, (ppfeatures)))
	381
cf097881 AD	382	struct amdgpu_dpm {
	383	struct amdgpu_ps *ps;
	384	/* number of valid power states */
	385	int num_ps;
	386	/* current power state that is active */
	387	struct amdgpu_ps *current_ps;
	388	/* requested power state */
	389	struct amdgpu_ps *requested_ps;
	390	/* boot up power state */
	391	struct amdgpu_ps *boot_ps;
	392	/* default uvd power state */
	393	struct amdgpu_ps *uvd_ps;
	394	/* vce requirements */
66ba1afd	395	u32 num_of_vce_states;
0d8de7ca RZ	396	struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
0d8de7ca RZ	397	enum amd_vce_level vce_level;
cf097881 AD	398	enum amd_pm_state_type state;
cf097881 AD	399	enum amd_pm_state_type user_state;
86f8c599 RZ	400	enum amd_pm_state_type last_state;
86f8c599 RZ	401	enum amd_pm_state_type last_user_state;
cf097881 AD	402	u32 platform_caps;
	403	u32 voltage_response_time;
	404	u32 backbias_response_time;
	405	void *priv;
	406	u32 new_active_crtcs;
	407	int new_active_crtc_count;
	408	u32 current_active_crtcs;
	409	int current_active_crtc_count;
	410	struct amdgpu_dpm_dynamic_state dyn_state;
	411	struct amdgpu_dpm_fan fan;
	412	u32 tdp_limit;
	413	u32 near_tdp_limit;
	414	u32 near_tdp_limit_adjusted;
	415	u32 sq_ramping_threshold;
	416	u32 cac_leakage;
	417	u16 tdp_od_limit;
	418	u32 tdp_adjustment;
	419	u16 load_line_slope;
	420	bool power_control;
cf097881 AD	421	/* special states active */
	422	bool thermal_active;
	423	bool uvd_active;
	424	bool vce_active;
	425	/* thermal handling */
	426	struct amdgpu_dpm_thermal thermal;
	427	/* forced levels */
e5d03ac2	428	enum amd_dpm_forced_level forced_level;
cf097881 AD	429	};
	430
	431	struct amdgpu_pm {
	432	struct mutex mutex;
	433	u32 current_sclk;
	434	u32 current_mclk;
	435	u32 default_sclk;
	436	u32 default_mclk;
	437	struct amdgpu_i2c_chan *i2c_bus;
	438	/* internal thermal controller on rv6xx+ */
	439	enum amdgpu_int_thermal_type int_thermal_type;
	440	struct device *int_hwmon_dev;
	441	/* fan control parameters */
	442	bool no_fan;
	443	u8 fan_pulses_per_revolution;
	444	u8 fan_min_rpm;
	445	u8 fan_max_rpm;
	446	/* dpm */
	447	bool dpm_enabled;
	448	bool sysfs_initialized;
	449	struct amdgpu_dpm dpm;
	450	const struct firmware fw; / SMC firmware */
	451	uint32_t fw_version;
cf097881 AD	452	uint32_t pcie_gen_mask;
cf097881 AD	453	uint32_t pcie_mlw_mask;
4562236b	454	struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
7951e376 RZ	455	uint32_t smu_prv_buffer_size;
7951e376 RZ	456	struct amdgpu_bo *smu_prv_buffer;
600ae890	457	bool ac_power;
3b94fb10 LG	458	/* powerplay feature */
	459	uint32_t pp_feature;
	460
cf097881 AD	461	};
cf097881 AD	462
d38ceaf9 AD	463	#define R600_SSTU_DFLT 0
	464	#define R600_SST_DFLT 0x00C8
	465
	466	/* XXX are these ok? */
	467	#define R600_TEMP_RANGE_MIN (90 * 1000)
	468	#define R600_TEMP_RANGE_MAX (120 * 1000)
	469
	470	#define FDO_PWM_MODE_STATIC 1
	471	#define FDO_PWM_MODE_STATIC_RPM 5
	472
	473	enum amdgpu_td {
	474	AMDGPU_TD_AUTO,
	475	AMDGPU_TD_UP,
	476	AMDGPU_TD_DOWN,
	477	};
	478
	479	enum amdgpu_display_watermark {
	480	AMDGPU_DISPLAY_WATERMARK_LOW = 0,
	481	AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
	482	};
	483
	484	enum amdgpu_display_gap
	485	{
	486	AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
	487	AMDGPU_PM_DISPLAY_GAP_VBLANK = 1,
	488	AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2,
	489	AMDGPU_PM_DISPLAY_GAP_IGNORE = 3,
	490	};
	491
	492	void amdgpu_dpm_print_class_info(u32 class, u32 class2);
	493	void amdgpu_dpm_print_cap_info(u32 caps);
	494	void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
	495	struct amdgpu_ps *rps);
	496	u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
	497	u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
d91ea496	498	void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
4a5a2de6 KW	499	int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
4a5a2de6 KW	500	void data, uint32_t size);
d38ceaf9 AD	501
	502	bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
	503
	504	int amdgpu_get_platform_caps(struct amdgpu_device *adev);
	505
	506	int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
	507	void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
	508
	509	void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
	510
	511	enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
	512	u32 sys_mask,
	513	enum amdgpu_pcie_gen asic_gen,
	514	enum amdgpu_pcie_gen default_gen);
	515
825cc997	516	struct amd_vce_state*
cfa289fd	517	amdgpu_get_vce_clock_state(void *handle, u32 idx);
825cc997	518
bca32528 KF	519	int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
	520	uint32_t block_type, bool gate);
	521
c5bee44b LG	522	extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
	523
	524	extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
	525
d38ceaf9	526	#endif