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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
d38ceaf9 AD |
30 | #include <linux/console.h> |
31 | #include <linux/slab.h> | |
d38ceaf9 AD |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
d38ceaf9 AD |
35 | #include <drm/amdgpu_drm.h> |
36 | #include <linux/vgaarb.h> | |
37 | #include <linux/vga_switcheroo.h> | |
38 | #include <linux/efi.h> | |
39 | #include "amdgpu.h" | |
f4b373f4 | 40 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
41 | #include "amdgpu_i2c.h" |
42 | #include "atom.h" | |
43 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 44 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 45 | #include "amd_pcie.h" |
33f34802 KW |
46 | #ifdef CONFIG_DRM_AMDGPU_SI |
47 | #include "si.h" | |
48 | #endif | |
a2e73f56 AD |
49 | #ifdef CONFIG_DRM_AMDGPU_CIK |
50 | #include "cik.h" | |
51 | #endif | |
aaa36a97 | 52 | #include "vi.h" |
460826e6 | 53 | #include "soc15.h" |
d38ceaf9 | 54 | #include "bif/bif_4_1_d.h" |
9accf2fd | 55 | #include <linux/pci.h> |
bec86378 | 56 | #include <linux/firmware.h> |
89041940 | 57 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 58 | |
ba997709 | 59 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 60 | #include "amdgpu_pm.h" |
d38ceaf9 | 61 | |
e2a75f88 | 62 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 63 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 64 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 65 | |
2dc80b00 S |
66 | #define AMDGPU_RESUME_MS 2000 |
67 | ||
d38ceaf9 | 68 | static const char *amdgpu_asic_name[] = { |
da69c161 KW |
69 | "TAHITI", |
70 | "PITCAIRN", | |
71 | "VERDE", | |
72 | "OLAND", | |
73 | "HAINAN", | |
d38ceaf9 AD |
74 | "BONAIRE", |
75 | "KAVERI", | |
76 | "KABINI", | |
77 | "HAWAII", | |
78 | "MULLINS", | |
79 | "TOPAZ", | |
80 | "TONGA", | |
48299f95 | 81 | "FIJI", |
d38ceaf9 | 82 | "CARRIZO", |
139f4917 | 83 | "STONEY", |
2cc0c0b5 FC |
84 | "POLARIS10", |
85 | "POLARIS11", | |
c4642a47 | 86 | "POLARIS12", |
48ff108d | 87 | "VEGAM", |
d4196f01 | 88 | "VEGA10", |
8fab806a | 89 | "VEGA12", |
956fcddc | 90 | "VEGA20", |
2ca8a5d2 | 91 | "RAVEN", |
d38ceaf9 AD |
92 | "LAST", |
93 | }; | |
94 | ||
5494d864 AD |
95 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
96 | ||
e3ecdffa AD |
97 | /** |
98 | * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control | |
99 | * | |
100 | * @dev: drm_device pointer | |
101 | * | |
102 | * Returns true if the device is a dGPU with HG/PX power control, | |
103 | * otherwise return false. | |
104 | */ | |
d38ceaf9 AD |
105 | bool amdgpu_device_is_px(struct drm_device *dev) |
106 | { | |
107 | struct amdgpu_device *adev = dev->dev_private; | |
108 | ||
2f7d10b3 | 109 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
110 | return true; |
111 | return false; | |
112 | } | |
113 | ||
114 | /* | |
115 | * MMIO register access helper functions. | |
116 | */ | |
e3ecdffa AD |
117 | /** |
118 | * amdgpu_mm_rreg - read a memory mapped IO register | |
119 | * | |
120 | * @adev: amdgpu_device pointer | |
121 | * @reg: dword aligned register offset | |
122 | * @acc_flags: access flags which require special behavior | |
123 | * | |
124 | * Returns the 32 bit value from the offset specified. | |
125 | */ | |
d38ceaf9 | 126 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
15d72fd7 | 127 | uint32_t acc_flags) |
d38ceaf9 | 128 | { |
f4b373f4 TSD |
129 | uint32_t ret; |
130 | ||
43ca8efa | 131 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 132 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 133 | |
15d72fd7 | 134 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 135 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
136 | else { |
137 | unsigned long flags; | |
d38ceaf9 AD |
138 | |
139 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
140 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
141 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
142 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 143 | } |
f4b373f4 TSD |
144 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
145 | return ret; | |
d38ceaf9 AD |
146 | } |
147 | ||
421a2a30 ML |
148 | /* |
149 | * MMIO register read with bytes helper functions | |
150 | * @offset:bytes offset from MMIO start | |
151 | * | |
152 | */ | |
153 | ||
e3ecdffa AD |
154 | /** |
155 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
156 | * | |
157 | * @adev: amdgpu_device pointer | |
158 | * @offset: byte aligned register offset | |
159 | * | |
160 | * Returns the 8 bit value from the offset specified. | |
161 | */ | |
421a2a30 ML |
162 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
163 | if (offset < adev->rmmio_size) | |
164 | return (readb(adev->rmmio + offset)); | |
165 | BUG(); | |
166 | } | |
167 | ||
168 | /* | |
169 | * MMIO register write with bytes helper functions | |
170 | * @offset:bytes offset from MMIO start | |
171 | * @value: the value want to be written to the register | |
172 | * | |
173 | */ | |
e3ecdffa AD |
174 | /** |
175 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
176 | * | |
177 | * @adev: amdgpu_device pointer | |
178 | * @offset: byte aligned register offset | |
179 | * @value: 8 bit value to write | |
180 | * | |
181 | * Writes the value specified to the offset specified. | |
182 | */ | |
421a2a30 ML |
183 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
184 | if (offset < adev->rmmio_size) | |
185 | writeb(value, adev->rmmio + offset); | |
186 | else | |
187 | BUG(); | |
188 | } | |
189 | ||
e3ecdffa AD |
190 | /** |
191 | * amdgpu_mm_wreg - write to a memory mapped IO register | |
192 | * | |
193 | * @adev: amdgpu_device pointer | |
194 | * @reg: dword aligned register offset | |
195 | * @v: 32 bit value to write to the register | |
196 | * @acc_flags: access flags which require special behavior | |
197 | * | |
198 | * Writes the value specified to the offset specified. | |
199 | */ | |
d38ceaf9 | 200 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 201 | uint32_t acc_flags) |
d38ceaf9 | 202 | { |
f4b373f4 | 203 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 204 | |
47ed4e1c KW |
205 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
206 | adev->last_mm_index = v; | |
207 | } | |
208 | ||
43ca8efa | 209 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 210 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 211 | |
15d72fd7 | 212 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
213 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
214 | else { | |
215 | unsigned long flags; | |
216 | ||
217 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
218 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
219 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
220 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
221 | } | |
47ed4e1c KW |
222 | |
223 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
224 | udelay(500); | |
225 | } | |
d38ceaf9 AD |
226 | } |
227 | ||
e3ecdffa AD |
228 | /** |
229 | * amdgpu_io_rreg - read an IO register | |
230 | * | |
231 | * @adev: amdgpu_device pointer | |
232 | * @reg: dword aligned register offset | |
233 | * | |
234 | * Returns the 32 bit value from the offset specified. | |
235 | */ | |
d38ceaf9 AD |
236 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
237 | { | |
238 | if ((reg * 4) < adev->rio_mem_size) | |
239 | return ioread32(adev->rio_mem + (reg * 4)); | |
240 | else { | |
241 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
242 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
243 | } | |
244 | } | |
245 | ||
e3ecdffa AD |
246 | /** |
247 | * amdgpu_io_wreg - write to an IO register | |
248 | * | |
249 | * @adev: amdgpu_device pointer | |
250 | * @reg: dword aligned register offset | |
251 | * @v: 32 bit value to write to the register | |
252 | * | |
253 | * Writes the value specified to the offset specified. | |
254 | */ | |
d38ceaf9 AD |
255 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
256 | { | |
47ed4e1c KW |
257 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
258 | adev->last_mm_index = v; | |
259 | } | |
d38ceaf9 AD |
260 | |
261 | if ((reg * 4) < adev->rio_mem_size) | |
262 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
263 | else { | |
264 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
265 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
266 | } | |
47ed4e1c KW |
267 | |
268 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
269 | udelay(500); | |
270 | } | |
d38ceaf9 AD |
271 | } |
272 | ||
273 | /** | |
274 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
275 | * | |
276 | * @adev: amdgpu_device pointer | |
277 | * @index: doorbell index | |
278 | * | |
279 | * Returns the value in the doorbell aperture at the | |
280 | * requested doorbell index (CIK). | |
281 | */ | |
282 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
283 | { | |
284 | if (index < adev->doorbell.num_doorbells) { | |
285 | return readl(adev->doorbell.ptr + index); | |
286 | } else { | |
287 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
288 | return 0; | |
289 | } | |
290 | } | |
291 | ||
292 | /** | |
293 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
294 | * | |
295 | * @adev: amdgpu_device pointer | |
296 | * @index: doorbell index | |
297 | * @v: value to write | |
298 | * | |
299 | * Writes @v to the doorbell aperture at the | |
300 | * requested doorbell index (CIK). | |
301 | */ | |
302 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
303 | { | |
304 | if (index < adev->doorbell.num_doorbells) { | |
305 | writel(v, adev->doorbell.ptr + index); | |
306 | } else { | |
307 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
308 | } | |
309 | } | |
310 | ||
832be404 KW |
311 | /** |
312 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
313 | * | |
314 | * @adev: amdgpu_device pointer | |
315 | * @index: doorbell index | |
316 | * | |
317 | * Returns the value in the doorbell aperture at the | |
318 | * requested doorbell index (VEGA10+). | |
319 | */ | |
320 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
321 | { | |
322 | if (index < adev->doorbell.num_doorbells) { | |
323 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
324 | } else { | |
325 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
326 | return 0; | |
327 | } | |
328 | } | |
329 | ||
330 | /** | |
331 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
332 | * | |
333 | * @adev: amdgpu_device pointer | |
334 | * @index: doorbell index | |
335 | * @v: value to write | |
336 | * | |
337 | * Writes @v to the doorbell aperture at the | |
338 | * requested doorbell index (VEGA10+). | |
339 | */ | |
340 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
341 | { | |
342 | if (index < adev->doorbell.num_doorbells) { | |
343 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
344 | } else { | |
345 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
346 | } | |
347 | } | |
348 | ||
d38ceaf9 AD |
349 | /** |
350 | * amdgpu_invalid_rreg - dummy reg read function | |
351 | * | |
352 | * @adev: amdgpu device pointer | |
353 | * @reg: offset of register | |
354 | * | |
355 | * Dummy register read function. Used for register blocks | |
356 | * that certain asics don't have (all asics). | |
357 | * Returns the value in the register. | |
358 | */ | |
359 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
360 | { | |
361 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
362 | BUG(); | |
363 | return 0; | |
364 | } | |
365 | ||
366 | /** | |
367 | * amdgpu_invalid_wreg - dummy reg write function | |
368 | * | |
369 | * @adev: amdgpu device pointer | |
370 | * @reg: offset of register | |
371 | * @v: value to write to the register | |
372 | * | |
373 | * Dummy register read function. Used for register blocks | |
374 | * that certain asics don't have (all asics). | |
375 | */ | |
376 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
377 | { | |
378 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
379 | reg, v); | |
380 | BUG(); | |
381 | } | |
382 | ||
383 | /** | |
384 | * amdgpu_block_invalid_rreg - dummy reg read function | |
385 | * | |
386 | * @adev: amdgpu device pointer | |
387 | * @block: offset of instance | |
388 | * @reg: offset of register | |
389 | * | |
390 | * Dummy register read function. Used for register blocks | |
391 | * that certain asics don't have (all asics). | |
392 | * Returns the value in the register. | |
393 | */ | |
394 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
395 | uint32_t block, uint32_t reg) | |
396 | { | |
397 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
398 | reg, block); | |
399 | BUG(); | |
400 | return 0; | |
401 | } | |
402 | ||
403 | /** | |
404 | * amdgpu_block_invalid_wreg - dummy reg write function | |
405 | * | |
406 | * @adev: amdgpu device pointer | |
407 | * @block: offset of instance | |
408 | * @reg: offset of register | |
409 | * @v: value to write to the register | |
410 | * | |
411 | * Dummy register read function. Used for register blocks | |
412 | * that certain asics don't have (all asics). | |
413 | */ | |
414 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
415 | uint32_t block, | |
416 | uint32_t reg, uint32_t v) | |
417 | { | |
418 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
419 | reg, block, v); | |
420 | BUG(); | |
421 | } | |
422 | ||
e3ecdffa AD |
423 | /** |
424 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
425 | * | |
426 | * @adev: amdgpu device pointer | |
427 | * | |
428 | * Allocates a scratch page of VRAM for use by various things in the | |
429 | * driver. | |
430 | */ | |
06ec9070 | 431 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 432 | { |
a4a02777 CK |
433 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
434 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
435 | &adev->vram_scratch.robj, | |
436 | &adev->vram_scratch.gpu_addr, | |
437 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
438 | } |
439 | ||
e3ecdffa AD |
440 | /** |
441 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
442 | * | |
443 | * @adev: amdgpu device pointer | |
444 | * | |
445 | * Frees the VRAM scratch page. | |
446 | */ | |
06ec9070 | 447 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 448 | { |
078af1a3 | 449 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
450 | } |
451 | ||
452 | /** | |
9c3f2b54 | 453 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
454 | * |
455 | * @adev: amdgpu_device pointer | |
456 | * @registers: pointer to the register array | |
457 | * @array_size: size of the register array | |
458 | * | |
459 | * Programs an array or registers with and and or masks. | |
460 | * This is a helper for setting golden registers. | |
461 | */ | |
9c3f2b54 AD |
462 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
463 | const u32 *registers, | |
464 | const u32 array_size) | |
d38ceaf9 AD |
465 | { |
466 | u32 tmp, reg, and_mask, or_mask; | |
467 | int i; | |
468 | ||
469 | if (array_size % 3) | |
470 | return; | |
471 | ||
472 | for (i = 0; i < array_size; i +=3) { | |
473 | reg = registers[i + 0]; | |
474 | and_mask = registers[i + 1]; | |
475 | or_mask = registers[i + 2]; | |
476 | ||
477 | if (and_mask == 0xffffffff) { | |
478 | tmp = or_mask; | |
479 | } else { | |
480 | tmp = RREG32(reg); | |
481 | tmp &= ~and_mask; | |
482 | tmp |= or_mask; | |
483 | } | |
484 | WREG32(reg, tmp); | |
485 | } | |
486 | } | |
487 | ||
e3ecdffa AD |
488 | /** |
489 | * amdgpu_device_pci_config_reset - reset the GPU | |
490 | * | |
491 | * @adev: amdgpu_device pointer | |
492 | * | |
493 | * Resets the GPU using the pci config reset sequence. | |
494 | * Only applicable to asics prior to vega10. | |
495 | */ | |
8111c387 | 496 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
497 | { |
498 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
499 | } | |
500 | ||
501 | /* | |
502 | * GPU doorbell aperture helpers function. | |
503 | */ | |
504 | /** | |
06ec9070 | 505 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
506 | * |
507 | * @adev: amdgpu_device pointer | |
508 | * | |
509 | * Init doorbell driver information (CIK) | |
510 | * Returns 0 on success, error on failure. | |
511 | */ | |
06ec9070 | 512 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 513 | { |
705e519e CK |
514 | /* No doorbell on SI hardware generation */ |
515 | if (adev->asic_type < CHIP_BONAIRE) { | |
516 | adev->doorbell.base = 0; | |
517 | adev->doorbell.size = 0; | |
518 | adev->doorbell.num_doorbells = 0; | |
519 | adev->doorbell.ptr = NULL; | |
520 | return 0; | |
521 | } | |
522 | ||
d6895ad3 CK |
523 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
524 | return -EINVAL; | |
525 | ||
d38ceaf9 AD |
526 | /* doorbell bar mapping */ |
527 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
528 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
529 | ||
edf600da | 530 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
531 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
532 | if (adev->doorbell.num_doorbells == 0) | |
533 | return -EINVAL; | |
534 | ||
8972e5d2 CK |
535 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
536 | adev->doorbell.num_doorbells * | |
537 | sizeof(u32)); | |
538 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 539 | return -ENOMEM; |
d38ceaf9 AD |
540 | |
541 | return 0; | |
542 | } | |
543 | ||
544 | /** | |
06ec9070 | 545 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
546 | * |
547 | * @adev: amdgpu_device pointer | |
548 | * | |
549 | * Tear down doorbell driver information (CIK) | |
550 | */ | |
06ec9070 | 551 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
552 | { |
553 | iounmap(adev->doorbell.ptr); | |
554 | adev->doorbell.ptr = NULL; | |
555 | } | |
556 | ||
22cb0164 | 557 | |
d38ceaf9 AD |
558 | |
559 | /* | |
06ec9070 | 560 | * amdgpu_device_wb_*() |
455a7bc2 | 561 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 562 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
563 | */ |
564 | ||
565 | /** | |
06ec9070 | 566 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
567 | * |
568 | * @adev: amdgpu_device pointer | |
569 | * | |
570 | * Disables Writeback and frees the Writeback memory (all asics). | |
571 | * Used at driver shutdown. | |
572 | */ | |
06ec9070 | 573 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
574 | { |
575 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
576 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
577 | &adev->wb.gpu_addr, | |
578 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
579 | adev->wb.wb_obj = NULL; |
580 | } | |
581 | } | |
582 | ||
583 | /** | |
06ec9070 | 584 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
585 | * |
586 | * @adev: amdgpu_device pointer | |
587 | * | |
455a7bc2 | 588 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
589 | * Used at driver startup. |
590 | * Returns 0 on success or an -error on failure. | |
591 | */ | |
06ec9070 | 592 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
593 | { |
594 | int r; | |
595 | ||
596 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
597 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
598 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
599 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
600 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
601 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
602 | if (r) { |
603 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
604 | return r; | |
605 | } | |
d38ceaf9 AD |
606 | |
607 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
608 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
609 | ||
610 | /* clear wb memory */ | |
73469585 | 611 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
612 | } |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | /** | |
131b4b36 | 618 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
619 | * |
620 | * @adev: amdgpu_device pointer | |
621 | * @wb: wb index | |
622 | * | |
623 | * Allocate a wb slot for use by the driver (all asics). | |
624 | * Returns 0 on success or -EINVAL on failure. | |
625 | */ | |
131b4b36 | 626 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
627 | { |
628 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 629 | |
97407b63 | 630 | if (offset < adev->wb.num_wb) { |
7014285a | 631 | __set_bit(offset, adev->wb.used); |
63ae07ca | 632 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
633 | return 0; |
634 | } else { | |
635 | return -EINVAL; | |
636 | } | |
637 | } | |
638 | ||
d38ceaf9 | 639 | /** |
131b4b36 | 640 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
641 | * |
642 | * @adev: amdgpu_device pointer | |
643 | * @wb: wb index | |
644 | * | |
645 | * Free a wb slot allocated for use by the driver (all asics) | |
646 | */ | |
131b4b36 | 647 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 648 | { |
73469585 | 649 | wb >>= 3; |
d38ceaf9 | 650 | if (wb < adev->wb.num_wb) |
73469585 | 651 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
652 | } |
653 | ||
d6895ad3 CK |
654 | /** |
655 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
656 | * | |
657 | * @adev: amdgpu_device pointer | |
658 | * | |
659 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
660 | * to fail, but if any of the BARs is not accessible after the size we abort | |
661 | * driver loading by returning -ENODEV. | |
662 | */ | |
663 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
664 | { | |
770d13b1 | 665 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 666 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
667 | struct pci_bus *root; |
668 | struct resource *res; | |
669 | unsigned i; | |
d6895ad3 CK |
670 | u16 cmd; |
671 | int r; | |
672 | ||
0c03b912 | 673 | /* Bypass for VF */ |
674 | if (amdgpu_sriov_vf(adev)) | |
675 | return 0; | |
676 | ||
31b8adab CK |
677 | /* Check if the root BUS has 64bit memory resources */ |
678 | root = adev->pdev->bus; | |
679 | while (root->parent) | |
680 | root = root->parent; | |
681 | ||
682 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 683 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
684 | res->start > 0x100000000ull) |
685 | break; | |
686 | } | |
687 | ||
688 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
689 | if (!res) | |
690 | return 0; | |
691 | ||
d6895ad3 CK |
692 | /* Disable memory decoding while we change the BAR addresses and size */ |
693 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
694 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
695 | cmd & ~PCI_COMMAND_MEMORY); | |
696 | ||
697 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 698 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
699 | if (adev->asic_type >= CHIP_BONAIRE) |
700 | pci_release_resource(adev->pdev, 2); | |
701 | ||
702 | pci_release_resource(adev->pdev, 0); | |
703 | ||
704 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
705 | if (r == -ENOSPC) | |
706 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
707 | else if (r && r != -ENOTSUPP) | |
708 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
709 | ||
710 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
711 | ||
712 | /* When the doorbell or fb BAR isn't available we have no chance of | |
713 | * using the device. | |
714 | */ | |
06ec9070 | 715 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
716 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
717 | return -ENODEV; | |
718 | ||
719 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
720 | ||
721 | return 0; | |
722 | } | |
a05502e5 | 723 | |
d38ceaf9 AD |
724 | /* |
725 | * GPU helpers function. | |
726 | */ | |
727 | /** | |
39c640c0 | 728 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
729 | * |
730 | * @adev: amdgpu_device pointer | |
731 | * | |
c836fec5 JQ |
732 | * Check if the asic has been initialized (all asics) at driver startup |
733 | * or post is needed if hw reset is performed. | |
734 | * Returns true if need or false if not. | |
d38ceaf9 | 735 | */ |
39c640c0 | 736 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
737 | { |
738 | uint32_t reg; | |
739 | ||
bec86378 ML |
740 | if (amdgpu_sriov_vf(adev)) |
741 | return false; | |
742 | ||
743 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
744 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
745 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
746 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
747 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
748 | */ |
749 | if (adev->asic_type == CHIP_FIJI) { | |
750 | int err; | |
751 | uint32_t fw_ver; | |
752 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
753 | /* force vPost if error occured */ | |
754 | if (err) | |
755 | return true; | |
756 | ||
757 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
758 | if (fw_ver < 0x00160e00) |
759 | return true; | |
bec86378 | 760 | } |
bec86378 | 761 | } |
91fe77eb | 762 | |
763 | if (adev->has_hw_reset) { | |
764 | adev->has_hw_reset = false; | |
765 | return true; | |
766 | } | |
767 | ||
768 | /* bios scratch used on CIK+ */ | |
769 | if (adev->asic_type >= CHIP_BONAIRE) | |
770 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
771 | ||
772 | /* check MEM_SIZE for older asics */ | |
773 | reg = amdgpu_asic_get_config_memsize(adev); | |
774 | ||
775 | if ((reg != 0) && (reg != 0xffffffff)) | |
776 | return false; | |
777 | ||
778 | return true; | |
bec86378 ML |
779 | } |
780 | ||
d38ceaf9 AD |
781 | /* if we get transitioned to only one device, take VGA back */ |
782 | /** | |
06ec9070 | 783 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
784 | * |
785 | * @cookie: amdgpu_device pointer | |
786 | * @state: enable/disable vga decode | |
787 | * | |
788 | * Enable/disable vga decode (all asics). | |
789 | * Returns VGA resource flags. | |
790 | */ | |
06ec9070 | 791 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
792 | { |
793 | struct amdgpu_device *adev = cookie; | |
794 | amdgpu_asic_set_vga_state(adev, state); | |
795 | if (state) | |
796 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
797 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
798 | else | |
799 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
800 | } | |
801 | ||
e3ecdffa AD |
802 | /** |
803 | * amdgpu_device_check_block_size - validate the vm block size | |
804 | * | |
805 | * @adev: amdgpu_device pointer | |
806 | * | |
807 | * Validates the vm block size specified via module parameter. | |
808 | * The vm block size defines number of bits in page table versus page directory, | |
809 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
810 | * page table and the remaining bits are in the page directory. | |
811 | */ | |
06ec9070 | 812 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
813 | { |
814 | /* defines number of bits in page table versus page directory, | |
815 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
816 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
817 | if (amdgpu_vm_block_size == -1) |
818 | return; | |
a1adf8be | 819 | |
bab4fee7 | 820 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
821 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
822 | amdgpu_vm_block_size); | |
97489129 | 823 | amdgpu_vm_block_size = -1; |
a1adf8be | 824 | } |
a1adf8be CZ |
825 | } |
826 | ||
e3ecdffa AD |
827 | /** |
828 | * amdgpu_device_check_vm_size - validate the vm size | |
829 | * | |
830 | * @adev: amdgpu_device pointer | |
831 | * | |
832 | * Validates the vm size in GB specified via module parameter. | |
833 | * The VM size is the size of the GPU virtual memory space in GB. | |
834 | */ | |
06ec9070 | 835 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 836 | { |
64dab074 AD |
837 | /* no need to check the default value */ |
838 | if (amdgpu_vm_size == -1) | |
839 | return; | |
840 | ||
83ca145d ZJ |
841 | if (amdgpu_vm_size < 1) { |
842 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
843 | amdgpu_vm_size); | |
f3368128 | 844 | amdgpu_vm_size = -1; |
83ca145d | 845 | } |
83ca145d ZJ |
846 | } |
847 | ||
7951e376 RZ |
848 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
849 | { | |
850 | struct sysinfo si; | |
851 | bool is_os_64 = (sizeof(void *) == 8) ? true : false; | |
852 | uint64_t total_memory; | |
853 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
854 | uint64_t dram_size_three_GB = 0xB8000000; | |
855 | ||
856 | if (amdgpu_smu_memory_pool_size == 0) | |
857 | return; | |
858 | ||
859 | if (!is_os_64) { | |
860 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
861 | goto def_value; | |
862 | } | |
863 | si_meminfo(&si); | |
864 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
865 | ||
866 | if ((amdgpu_smu_memory_pool_size == 1) || | |
867 | (amdgpu_smu_memory_pool_size == 2)) { | |
868 | if (total_memory < dram_size_three_GB) | |
869 | goto def_value1; | |
870 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
871 | (amdgpu_smu_memory_pool_size == 8)) { | |
872 | if (total_memory < dram_size_seven_GB) | |
873 | goto def_value1; | |
874 | } else { | |
875 | DRM_WARN("Smu memory pool size not supported\n"); | |
876 | goto def_value; | |
877 | } | |
878 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
879 | ||
880 | return; | |
881 | ||
882 | def_value1: | |
883 | DRM_WARN("No enough system memory\n"); | |
884 | def_value: | |
885 | adev->pm.smu_prv_buffer_size = 0; | |
886 | } | |
887 | ||
d38ceaf9 | 888 | /** |
06ec9070 | 889 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
890 | * |
891 | * @adev: amdgpu_device pointer | |
892 | * | |
893 | * Validates certain module parameters and updates | |
894 | * the associated values used by the driver (all asics). | |
895 | */ | |
06ec9070 | 896 | static void amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 897 | { |
5b011235 CZ |
898 | if (amdgpu_sched_jobs < 4) { |
899 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
900 | amdgpu_sched_jobs); | |
901 | amdgpu_sched_jobs = 4; | |
76117507 | 902 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
903 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
904 | amdgpu_sched_jobs); | |
905 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
906 | } | |
d38ceaf9 | 907 | |
83e74db6 | 908 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
909 | /* gart size must be greater or equal to 32M */ |
910 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
911 | amdgpu_gart_size); | |
83e74db6 | 912 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
913 | } |
914 | ||
36d38372 | 915 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 916 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
917 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
918 | amdgpu_gtt_size); | |
919 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
920 | } |
921 | ||
d07f14be RH |
922 | /* valid range is between 4 and 9 inclusive */ |
923 | if (amdgpu_vm_fragment_size != -1 && | |
924 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
925 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
926 | amdgpu_vm_fragment_size = -1; | |
927 | } | |
928 | ||
7951e376 RZ |
929 | amdgpu_device_check_smu_prv_buffer_size(adev); |
930 | ||
06ec9070 | 931 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 932 | |
06ec9070 | 933 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 934 | |
526bae37 | 935 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 936 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
937 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
938 | amdgpu_vram_page_split); | |
939 | amdgpu_vram_page_split = 1024; | |
940 | } | |
8854695a AG |
941 | |
942 | if (amdgpu_lockup_timeout == 0) { | |
943 | dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n"); | |
944 | amdgpu_lockup_timeout = 10000; | |
945 | } | |
19aede77 AD |
946 | |
947 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); | |
d38ceaf9 AD |
948 | } |
949 | ||
950 | /** | |
951 | * amdgpu_switcheroo_set_state - set switcheroo state | |
952 | * | |
953 | * @pdev: pci dev pointer | |
1694467b | 954 | * @state: vga_switcheroo state |
d38ceaf9 AD |
955 | * |
956 | * Callback for the switcheroo driver. Suspends or resumes the | |
957 | * the asics before or after it is powered up using ACPI methods. | |
958 | */ | |
959 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
960 | { | |
961 | struct drm_device *dev = pci_get_drvdata(pdev); | |
962 | ||
963 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
964 | return; | |
965 | ||
966 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 967 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
968 | /* don't suspend or resume card normally */ |
969 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
970 | ||
810ddc3a | 971 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 972 | |
d38ceaf9 AD |
973 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
974 | drm_kms_helper_poll_enable(dev); | |
975 | } else { | |
7ca85295 | 976 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
977 | drm_kms_helper_poll_disable(dev); |
978 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 979 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
980 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
981 | } | |
982 | } | |
983 | ||
984 | /** | |
985 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
986 | * | |
987 | * @pdev: pci dev pointer | |
988 | * | |
989 | * Callback for the switcheroo driver. Check of the switcheroo | |
990 | * state can be changed. | |
991 | * Returns true if the state can be changed, false if not. | |
992 | */ | |
993 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
994 | { | |
995 | struct drm_device *dev = pci_get_drvdata(pdev); | |
996 | ||
997 | /* | |
998 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
999 | * locking inversion with the driver load path. And the access here is | |
1000 | * completely racy anyway. So don't bother with locking for now. | |
1001 | */ | |
1002 | return dev->open_count == 0; | |
1003 | } | |
1004 | ||
1005 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1006 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1007 | .reprobe = NULL, | |
1008 | .can_switch = amdgpu_switcheroo_can_switch, | |
1009 | }; | |
1010 | ||
e3ecdffa AD |
1011 | /** |
1012 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1013 | * | |
87e3f136 | 1014 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1015 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1016 | * @state: clockgating state (gate or ungate) | |
1017 | * | |
1018 | * Sets the requested clockgating state for all instances of | |
1019 | * the hardware IP specified. | |
1020 | * Returns the error code from the last instance. | |
1021 | */ | |
43fa561f | 1022 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1023 | enum amd_ip_block_type block_type, |
1024 | enum amd_clockgating_state state) | |
d38ceaf9 | 1025 | { |
43fa561f | 1026 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1027 | int i, r = 0; |
1028 | ||
1029 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1030 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1031 | continue; |
c722865a RZ |
1032 | if (adev->ip_blocks[i].version->type != block_type) |
1033 | continue; | |
1034 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1035 | continue; | |
1036 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1037 | (void *)adev, state); | |
1038 | if (r) | |
1039 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1040 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1041 | } |
1042 | return r; | |
1043 | } | |
1044 | ||
e3ecdffa AD |
1045 | /** |
1046 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1047 | * | |
87e3f136 | 1048 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1049 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1050 | * @state: powergating state (gate or ungate) | |
1051 | * | |
1052 | * Sets the requested powergating state for all instances of | |
1053 | * the hardware IP specified. | |
1054 | * Returns the error code from the last instance. | |
1055 | */ | |
43fa561f | 1056 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1057 | enum amd_ip_block_type block_type, |
1058 | enum amd_powergating_state state) | |
d38ceaf9 | 1059 | { |
43fa561f | 1060 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1061 | int i, r = 0; |
1062 | ||
1063 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1064 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1065 | continue; |
c722865a RZ |
1066 | if (adev->ip_blocks[i].version->type != block_type) |
1067 | continue; | |
1068 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1069 | continue; | |
1070 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1071 | (void *)adev, state); | |
1072 | if (r) | |
1073 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1074 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1075 | } |
1076 | return r; | |
1077 | } | |
1078 | ||
e3ecdffa AD |
1079 | /** |
1080 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1081 | * | |
1082 | * @adev: amdgpu_device pointer | |
1083 | * @flags: clockgating feature flags | |
1084 | * | |
1085 | * Walks the list of IPs on the device and updates the clockgating | |
1086 | * flags for each IP. | |
1087 | * Updates @flags with the feature flags for each hardware IP where | |
1088 | * clockgating is enabled. | |
1089 | */ | |
2990a1fc AD |
1090 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1091 | u32 *flags) | |
6cb2d4e4 HR |
1092 | { |
1093 | int i; | |
1094 | ||
1095 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1096 | if (!adev->ip_blocks[i].status.valid) | |
1097 | continue; | |
1098 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1099 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1100 | } | |
1101 | } | |
1102 | ||
e3ecdffa AD |
1103 | /** |
1104 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1105 | * | |
1106 | * @adev: amdgpu_device pointer | |
1107 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1108 | * | |
1109 | * Waits for the request hardware IP to be idle. | |
1110 | * Returns 0 for success or a negative error code on failure. | |
1111 | */ | |
2990a1fc AD |
1112 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1113 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1114 | { |
1115 | int i, r; | |
1116 | ||
1117 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1118 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1119 | continue; |
a1255107 AD |
1120 | if (adev->ip_blocks[i].version->type == block_type) { |
1121 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1122 | if (r) |
1123 | return r; | |
1124 | break; | |
1125 | } | |
1126 | } | |
1127 | return 0; | |
1128 | ||
1129 | } | |
1130 | ||
e3ecdffa AD |
1131 | /** |
1132 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1133 | * | |
1134 | * @adev: amdgpu_device pointer | |
1135 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1136 | * | |
1137 | * Check if the hardware IP is idle or not. | |
1138 | * Returns true if it the IP is idle, false if not. | |
1139 | */ | |
2990a1fc AD |
1140 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1141 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1142 | { |
1143 | int i; | |
1144 | ||
1145 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1146 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1147 | continue; |
a1255107 AD |
1148 | if (adev->ip_blocks[i].version->type == block_type) |
1149 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1150 | } |
1151 | return true; | |
1152 | ||
1153 | } | |
1154 | ||
e3ecdffa AD |
1155 | /** |
1156 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1157 | * | |
1158 | * @adev: amdgpu_device pointer | |
87e3f136 | 1159 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1160 | * |
1161 | * Returns a pointer to the hardware IP block structure | |
1162 | * if it exists for the asic, otherwise NULL. | |
1163 | */ | |
2990a1fc AD |
1164 | struct amdgpu_ip_block * |
1165 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1166 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1167 | { |
1168 | int i; | |
1169 | ||
1170 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1171 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1172 | return &adev->ip_blocks[i]; |
1173 | ||
1174 | return NULL; | |
1175 | } | |
1176 | ||
1177 | /** | |
2990a1fc | 1178 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1179 | * |
1180 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1181 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1182 | * @major: major version |
1183 | * @minor: minor version | |
1184 | * | |
1185 | * return 0 if equal or greater | |
1186 | * return 1 if smaller or the ip_block doesn't exist | |
1187 | */ | |
2990a1fc AD |
1188 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1189 | enum amd_ip_block_type type, | |
1190 | u32 major, u32 minor) | |
d38ceaf9 | 1191 | { |
2990a1fc | 1192 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1193 | |
a1255107 AD |
1194 | if (ip_block && ((ip_block->version->major > major) || |
1195 | ((ip_block->version->major == major) && | |
1196 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1197 | return 0; |
1198 | ||
1199 | return 1; | |
1200 | } | |
1201 | ||
a1255107 | 1202 | /** |
2990a1fc | 1203 | * amdgpu_device_ip_block_add |
a1255107 AD |
1204 | * |
1205 | * @adev: amdgpu_device pointer | |
1206 | * @ip_block_version: pointer to the IP to add | |
1207 | * | |
1208 | * Adds the IP block driver information to the collection of IPs | |
1209 | * on the asic. | |
1210 | */ | |
2990a1fc AD |
1211 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1212 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1213 | { |
1214 | if (!ip_block_version) | |
1215 | return -EINVAL; | |
1216 | ||
e966a725 | 1217 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1218 | ip_block_version->funcs->name); |
1219 | ||
a1255107 AD |
1220 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
e3ecdffa AD |
1225 | /** |
1226 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1227 | * | |
1228 | * @adev: amdgpu_device pointer | |
1229 | * | |
1230 | * Enabled the virtual display feature if the user has enabled it via | |
1231 | * the module parameter virtual_display. This feature provides a virtual | |
1232 | * display hardware on headless boards or in virtualized environments. | |
1233 | * This function parses and validates the configuration string specified by | |
1234 | * the user and configues the virtual display configuration (number of | |
1235 | * virtual connectors, crtcs, etc.) specified. | |
1236 | */ | |
483ef985 | 1237 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1238 | { |
1239 | adev->enable_virtual_display = false; | |
1240 | ||
1241 | if (amdgpu_virtual_display) { | |
1242 | struct drm_device *ddev = adev->ddev; | |
1243 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1244 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1245 | |
1246 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1247 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1248 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1249 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1250 | if (!strcmp("all", pciaddname) |
1251 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1252 | long num_crtc; |
1253 | int res = -1; | |
1254 | ||
9accf2fd | 1255 | adev->enable_virtual_display = true; |
0f66356d ED |
1256 | |
1257 | if (pciaddname_tmp) | |
1258 | res = kstrtol(pciaddname_tmp, 10, | |
1259 | &num_crtc); | |
1260 | ||
1261 | if (!res) { | |
1262 | if (num_crtc < 1) | |
1263 | num_crtc = 1; | |
1264 | if (num_crtc > 6) | |
1265 | num_crtc = 6; | |
1266 | adev->mode_info.num_crtc = num_crtc; | |
1267 | } else { | |
1268 | adev->mode_info.num_crtc = 1; | |
1269 | } | |
9accf2fd ED |
1270 | break; |
1271 | } | |
1272 | } | |
1273 | ||
0f66356d ED |
1274 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1275 | amdgpu_virtual_display, pci_address_name, | |
1276 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1277 | |
1278 | kfree(pciaddstr); | |
1279 | } | |
1280 | } | |
1281 | ||
e3ecdffa AD |
1282 | /** |
1283 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1284 | * | |
1285 | * @adev: amdgpu_device pointer | |
1286 | * | |
1287 | * Parses the asic configuration parameters specified in the gpu info | |
1288 | * firmware and makes them availale to the driver for use in configuring | |
1289 | * the asic. | |
1290 | * Returns 0 on success, -EINVAL on failure. | |
1291 | */ | |
e2a75f88 AD |
1292 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1293 | { | |
e2a75f88 AD |
1294 | const char *chip_name; |
1295 | char fw_name[30]; | |
1296 | int err; | |
1297 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1298 | ||
ab4fe3e1 HR |
1299 | adev->firmware.gpu_info_fw = NULL; |
1300 | ||
e2a75f88 AD |
1301 | switch (adev->asic_type) { |
1302 | case CHIP_TOPAZ: | |
1303 | case CHIP_TONGA: | |
1304 | case CHIP_FIJI: | |
e2a75f88 | 1305 | case CHIP_POLARIS10: |
cc07f18d | 1306 | case CHIP_POLARIS11: |
e2a75f88 | 1307 | case CHIP_POLARIS12: |
cc07f18d | 1308 | case CHIP_VEGAM: |
e2a75f88 AD |
1309 | case CHIP_CARRIZO: |
1310 | case CHIP_STONEY: | |
1311 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1312 | case CHIP_VERDE: | |
1313 | case CHIP_TAHITI: | |
1314 | case CHIP_PITCAIRN: | |
1315 | case CHIP_OLAND: | |
1316 | case CHIP_HAINAN: | |
1317 | #endif | |
1318 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1319 | case CHIP_BONAIRE: | |
1320 | case CHIP_HAWAII: | |
1321 | case CHIP_KAVERI: | |
1322 | case CHIP_KABINI: | |
1323 | case CHIP_MULLINS: | |
1324 | #endif | |
27c0bc71 | 1325 | case CHIP_VEGA20: |
e2a75f88 AD |
1326 | default: |
1327 | return 0; | |
1328 | case CHIP_VEGA10: | |
1329 | chip_name = "vega10"; | |
1330 | break; | |
3f76dced AD |
1331 | case CHIP_VEGA12: |
1332 | chip_name = "vega12"; | |
1333 | break; | |
2d2e5e7e AD |
1334 | case CHIP_RAVEN: |
1335 | chip_name = "raven"; | |
1336 | break; | |
e2a75f88 AD |
1337 | } |
1338 | ||
1339 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1340 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1341 | if (err) { |
1342 | dev_err(adev->dev, | |
1343 | "Failed to load gpu_info firmware \"%s\"\n", | |
1344 | fw_name); | |
1345 | goto out; | |
1346 | } | |
ab4fe3e1 | 1347 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1348 | if (err) { |
1349 | dev_err(adev->dev, | |
1350 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1351 | fw_name); | |
1352 | goto out; | |
1353 | } | |
1354 | ||
ab4fe3e1 | 1355 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1356 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1357 | ||
1358 | switch (hdr->version_major) { | |
1359 | case 1: | |
1360 | { | |
1361 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1362 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1363 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1364 | ||
b5ab16bf AD |
1365 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1366 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1367 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1368 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1369 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1370 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1371 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1372 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1373 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1374 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1375 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1376 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1377 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1378 | adev->gfx.cu_info.max_waves_per_simd = |
1379 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1380 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1381 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1382 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1383 | break; |
1384 | } | |
1385 | default: | |
1386 | dev_err(adev->dev, | |
1387 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1388 | err = -EINVAL; | |
1389 | goto out; | |
1390 | } | |
1391 | out: | |
e2a75f88 AD |
1392 | return err; |
1393 | } | |
1394 | ||
e3ecdffa AD |
1395 | /** |
1396 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1397 | * | |
1398 | * @adev: amdgpu_device pointer | |
1399 | * | |
1400 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1401 | * up each asic are discovered each IP's early_init callback is run. This | |
1402 | * is the first stage in initializing the asic. | |
1403 | * Returns 0 on success, negative error code on failure. | |
1404 | */ | |
06ec9070 | 1405 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1406 | { |
aaa36a97 | 1407 | int i, r; |
d38ceaf9 | 1408 | |
483ef985 | 1409 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1410 | |
d38ceaf9 | 1411 | switch (adev->asic_type) { |
aaa36a97 AD |
1412 | case CHIP_TOPAZ: |
1413 | case CHIP_TONGA: | |
48299f95 | 1414 | case CHIP_FIJI: |
2cc0c0b5 | 1415 | case CHIP_POLARIS10: |
32cc7e53 | 1416 | case CHIP_POLARIS11: |
c4642a47 | 1417 | case CHIP_POLARIS12: |
32cc7e53 | 1418 | case CHIP_VEGAM: |
aaa36a97 | 1419 | case CHIP_CARRIZO: |
39bb0c92 SL |
1420 | case CHIP_STONEY: |
1421 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1422 | adev->family = AMDGPU_FAMILY_CZ; |
1423 | else | |
1424 | adev->family = AMDGPU_FAMILY_VI; | |
1425 | ||
1426 | r = vi_set_ip_blocks(adev); | |
1427 | if (r) | |
1428 | return r; | |
1429 | break; | |
33f34802 KW |
1430 | #ifdef CONFIG_DRM_AMDGPU_SI |
1431 | case CHIP_VERDE: | |
1432 | case CHIP_TAHITI: | |
1433 | case CHIP_PITCAIRN: | |
1434 | case CHIP_OLAND: | |
1435 | case CHIP_HAINAN: | |
295d0daf | 1436 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1437 | r = si_set_ip_blocks(adev); |
1438 | if (r) | |
1439 | return r; | |
1440 | break; | |
1441 | #endif | |
a2e73f56 AD |
1442 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1443 | case CHIP_BONAIRE: | |
1444 | case CHIP_HAWAII: | |
1445 | case CHIP_KAVERI: | |
1446 | case CHIP_KABINI: | |
1447 | case CHIP_MULLINS: | |
1448 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1449 | adev->family = AMDGPU_FAMILY_CI; | |
1450 | else | |
1451 | adev->family = AMDGPU_FAMILY_KV; | |
1452 | ||
1453 | r = cik_set_ip_blocks(adev); | |
1454 | if (r) | |
1455 | return r; | |
1456 | break; | |
1457 | #endif | |
e48a3cd9 AD |
1458 | case CHIP_VEGA10: |
1459 | case CHIP_VEGA12: | |
e4bd8170 | 1460 | case CHIP_VEGA20: |
e48a3cd9 | 1461 | case CHIP_RAVEN: |
2ca8a5d2 CZ |
1462 | if (adev->asic_type == CHIP_RAVEN) |
1463 | adev->family = AMDGPU_FAMILY_RV; | |
1464 | else | |
1465 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1466 | |
1467 | r = soc15_set_ip_blocks(adev); | |
1468 | if (r) | |
1469 | return r; | |
1470 | break; | |
d38ceaf9 AD |
1471 | default: |
1472 | /* FIXME: not supported yet */ | |
1473 | return -EINVAL; | |
1474 | } | |
1475 | ||
e2a75f88 AD |
1476 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1477 | if (r) | |
1478 | return r; | |
1479 | ||
1884734a | 1480 | amdgpu_amdkfd_device_probe(adev); |
1481 | ||
3149d9da XY |
1482 | if (amdgpu_sriov_vf(adev)) { |
1483 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1484 | if (r) | |
5ffa61c1 | 1485 | return -EAGAIN; |
3149d9da XY |
1486 | } |
1487 | ||
00f54b97 HR |
1488 | adev->powerplay.pp_feature = amdgpu_pp_feature_mask; |
1489 | ||
d38ceaf9 AD |
1490 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1491 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1492 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1493 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1494 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1495 | } else { |
a1255107 AD |
1496 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1497 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1498 | if (r == -ENOENT) { |
a1255107 | 1499 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1500 | } else if (r) { |
a1255107 AD |
1501 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1502 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1503 | return r; |
2c1a2784 | 1504 | } else { |
a1255107 | 1505 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1506 | } |
974e6b64 | 1507 | } else { |
a1255107 | 1508 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1509 | } |
d38ceaf9 AD |
1510 | } |
1511 | } | |
1512 | ||
395d1fb9 NH |
1513 | adev->cg_flags &= amdgpu_cg_mask; |
1514 | adev->pg_flags &= amdgpu_pg_mask; | |
1515 | ||
d38ceaf9 AD |
1516 | return 0; |
1517 | } | |
1518 | ||
e3ecdffa AD |
1519 | /** |
1520 | * amdgpu_device_ip_init - run init for hardware IPs | |
1521 | * | |
1522 | * @adev: amdgpu_device pointer | |
1523 | * | |
1524 | * Main initialization pass for hardware IPs. The list of all the hardware | |
1525 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
1526 | * are run. sw_init initializes the software state associated with each IP | |
1527 | * and hw_init initializes the hardware associated with each IP. | |
1528 | * Returns 0 on success, negative error code on failure. | |
1529 | */ | |
06ec9070 | 1530 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1531 | { |
1532 | int i, r; | |
1533 | ||
1534 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1535 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1536 | continue; |
a1255107 | 1537 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1538 | if (r) { |
a1255107 AD |
1539 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1540 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1541 | return r; |
2c1a2784 | 1542 | } |
a1255107 | 1543 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 1544 | |
d38ceaf9 | 1545 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1546 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 1547 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
1548 | if (r) { |
1549 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1550 | return r; |
2c1a2784 | 1551 | } |
a1255107 | 1552 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1553 | if (r) { |
1554 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1555 | return r; |
2c1a2784 | 1556 | } |
06ec9070 | 1557 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 1558 | if (r) { |
06ec9070 | 1559 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
d38ceaf9 | 1560 | return r; |
2c1a2784 | 1561 | } |
a1255107 | 1562 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1563 | |
1564 | /* right after GMC hw init, we create CSA */ | |
1565 | if (amdgpu_sriov_vf(adev)) { | |
1566 | r = amdgpu_allocate_static_csa(adev); | |
1567 | if (r) { | |
1568 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1569 | return r; | |
1570 | } | |
1571 | } | |
d38ceaf9 AD |
1572 | } |
1573 | } | |
1574 | ||
1575 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1576 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1577 | continue; |
bfca0289 | 1578 | if (adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1579 | continue; |
a1255107 | 1580 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1581 | if (r) { |
a1255107 AD |
1582 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1583 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1584 | return r; |
2c1a2784 | 1585 | } |
a1255107 | 1586 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1587 | } |
1588 | ||
1884734a | 1589 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1590 | |
1591 | if (amdgpu_sriov_vf(adev)) | |
1592 | amdgpu_virt_release_full_gpu(adev, true); | |
1593 | ||
d38ceaf9 AD |
1594 | return 0; |
1595 | } | |
1596 | ||
e3ecdffa AD |
1597 | /** |
1598 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
1599 | * | |
1600 | * @adev: amdgpu_device pointer | |
1601 | * | |
1602 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
1603 | * this function before a GPU reset. If the value is retained after a | |
1604 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
1605 | */ | |
06ec9070 | 1606 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1607 | { |
1608 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1609 | } | |
1610 | ||
e3ecdffa AD |
1611 | /** |
1612 | * amdgpu_device_check_vram_lost - check if vram is valid | |
1613 | * | |
1614 | * @adev: amdgpu_device pointer | |
1615 | * | |
1616 | * Checks the reset magic value written to the gart pointer in VRAM. | |
1617 | * The driver calls this after a GPU reset to see if the contents of | |
1618 | * VRAM is lost or now. | |
1619 | * returns true if vram is lost, false if not. | |
1620 | */ | |
06ec9070 | 1621 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1622 | { |
1623 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1624 | AMDGPU_RESET_MAGIC_NUM); | |
1625 | } | |
1626 | ||
e3ecdffa | 1627 | /** |
1112a46b | 1628 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
1629 | * |
1630 | * @adev: amdgpu_device pointer | |
1631 | * | |
e3ecdffa | 1632 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
1633 | * set_clockgating_state callbacks are run. |
1634 | * Late initialization pass enabling clockgating for hardware IPs. | |
1635 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
1636 | * Returns 0 on success, negative error code on failure. |
1637 | */ | |
fdd34271 | 1638 | |
1112a46b RZ |
1639 | static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
1640 | enum amd_clockgating_state state) | |
d38ceaf9 | 1641 | { |
1112a46b | 1642 | int i, j, r; |
d38ceaf9 | 1643 | |
4a2ba394 SL |
1644 | if (amdgpu_emu_mode == 1) |
1645 | return 0; | |
1646 | ||
1112a46b RZ |
1647 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1648 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a1255107 | 1649 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1650 | continue; |
4a446d55 | 1651 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 1652 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 1653 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 1654 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
57716327 | 1655 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 1656 | /* enable clockgating to save power */ |
a1255107 | 1657 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 1658 | state); |
4a446d55 AD |
1659 | if (r) { |
1660 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1661 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1662 | return r; |
1663 | } | |
b0b00ff1 | 1664 | } |
d38ceaf9 | 1665 | } |
06b18f61 | 1666 | |
c9f96fd5 RZ |
1667 | return 0; |
1668 | } | |
1669 | ||
1112a46b | 1670 | static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state) |
c9f96fd5 | 1671 | { |
1112a46b | 1672 | int i, j, r; |
06b18f61 | 1673 | |
c9f96fd5 RZ |
1674 | if (amdgpu_emu_mode == 1) |
1675 | return 0; | |
1676 | ||
1112a46b RZ |
1677 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1678 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
c9f96fd5 RZ |
1679 | if (!adev->ip_blocks[i].status.valid) |
1680 | continue; | |
1681 | /* skip CG for VCE/UVD, it's handled specially */ | |
1682 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1683 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
1684 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
1685 | adev->ip_blocks[i].version->funcs->set_powergating_state) { | |
1686 | /* enable powergating to save power */ | |
1687 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 1688 | state); |
c9f96fd5 RZ |
1689 | if (r) { |
1690 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
1691 | adev->ip_blocks[i].version->funcs->name, r); | |
1692 | return r; | |
1693 | } | |
1694 | } | |
1695 | } | |
2dc80b00 S |
1696 | return 0; |
1697 | } | |
1698 | ||
e3ecdffa AD |
1699 | /** |
1700 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
1701 | * | |
1702 | * @adev: amdgpu_device pointer | |
1703 | * | |
1704 | * Late initialization pass for hardware IPs. The list of all the hardware | |
1705 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
1706 | * late_init covers any special initialization that an IP requires | |
1707 | * after all of the have been initialized or something that needs to happen | |
1708 | * late in the init process. | |
1709 | * Returns 0 on success, negative error code on failure. | |
1710 | */ | |
06ec9070 | 1711 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 S |
1712 | { |
1713 | int i = 0, r; | |
1714 | ||
1715 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1716 | if (!adev->ip_blocks[i].status.valid) | |
1717 | continue; | |
1718 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1719 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1720 | if (r) { | |
1721 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1722 | adev->ip_blocks[i].version->funcs->name, r); | |
1723 | return r; | |
1724 | } | |
1725 | adev->ip_blocks[i].status.late_initialized = true; | |
1726 | } | |
1727 | } | |
1728 | ||
1112a46b RZ |
1729 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
1730 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 1731 | |
2c773de2 S |
1732 | queue_delayed_work(system_wq, &adev->late_init_work, |
1733 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1734 | |
06ec9070 | 1735 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 AD |
1736 | |
1737 | return 0; | |
1738 | } | |
1739 | ||
e3ecdffa AD |
1740 | /** |
1741 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
1742 | * | |
1743 | * @adev: amdgpu_device pointer | |
1744 | * | |
1745 | * Main teardown pass for hardware IPs. The list of all the hardware | |
1746 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
1747 | * are run. hw_fini tears down the hardware associated with each IP | |
1748 | * and sw_fini tears down any software state associated with each IP. | |
1749 | * Returns 0 on success, negative error code on failure. | |
1750 | */ | |
06ec9070 | 1751 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1752 | { |
1753 | int i, r; | |
1754 | ||
1884734a | 1755 | amdgpu_amdkfd_device_fini(adev); |
05df1f01 RZ |
1756 | |
1757 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); | |
fdd34271 RZ |
1758 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
1759 | ||
3e96dbfd AD |
1760 | /* need to disable SMC first */ |
1761 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1762 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1763 | continue; |
fdd34271 | 1764 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 1765 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1766 | /* XXX handle errors */ |
1767 | if (r) { | |
1768 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1769 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1770 | } |
a1255107 | 1771 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1772 | break; |
1773 | } | |
1774 | } | |
1775 | ||
d38ceaf9 | 1776 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1777 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1778 | continue; |
8201a67a | 1779 | |
a1255107 | 1780 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1781 | /* XXX handle errors */ |
2c1a2784 | 1782 | if (r) { |
a1255107 AD |
1783 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1784 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1785 | } |
8201a67a | 1786 | |
a1255107 | 1787 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1788 | } |
1789 | ||
9950cda2 | 1790 | |
d38ceaf9 | 1791 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1792 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1793 | continue; |
c12aba3a ML |
1794 | |
1795 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
1796 | amdgpu_free_static_csa(adev); | |
1797 | amdgpu_device_wb_fini(adev); | |
1798 | amdgpu_device_vram_scratch_fini(adev); | |
1799 | } | |
1800 | ||
a1255107 | 1801 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1802 | /* XXX handle errors */ |
2c1a2784 | 1803 | if (r) { |
a1255107 AD |
1804 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1805 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1806 | } |
a1255107 AD |
1807 | adev->ip_blocks[i].status.sw = false; |
1808 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1809 | } |
1810 | ||
a6dcfd9c | 1811 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1812 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1813 | continue; |
a1255107 AD |
1814 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1815 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1816 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1817 | } |
1818 | ||
030308fc | 1819 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
1820 | if (amdgpu_virt_release_full_gpu(adev, false)) |
1821 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 1822 | |
d38ceaf9 AD |
1823 | return 0; |
1824 | } | |
1825 | ||
e3ecdffa | 1826 | /** |
1112a46b | 1827 | * amdgpu_device_ip_late_init_func_handler - work handler for ib test |
e3ecdffa | 1828 | * |
1112a46b | 1829 | * @work: work_struct. |
e3ecdffa | 1830 | */ |
06ec9070 | 1831 | static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) |
2dc80b00 S |
1832 | { |
1833 | struct amdgpu_device *adev = | |
1834 | container_of(work, struct amdgpu_device, late_init_work.work); | |
916ac57f RZ |
1835 | int r; |
1836 | ||
1837 | r = amdgpu_ib_ring_tests(adev); | |
1838 | if (r) | |
1839 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
1840 | } |
1841 | ||
1e317b99 RZ |
1842 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
1843 | { | |
1844 | struct amdgpu_device *adev = | |
1845 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
1846 | ||
1847 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
1848 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
1849 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
1850 | adev->gfx.gfx_off_state = true; | |
1851 | } | |
1852 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
1853 | } | |
1854 | ||
e3ecdffa | 1855 | /** |
e7854a03 | 1856 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
1857 | * |
1858 | * @adev: amdgpu_device pointer | |
1859 | * | |
1860 | * Main suspend function for hardware IPs. The list of all the hardware | |
1861 | * IPs that make up the asic is walked, clockgating is disabled and the | |
1862 | * suspend callbacks are run. suspend puts the hardware and software state | |
1863 | * in each IP into a state suitable for suspend. | |
1864 | * Returns 0 on success, negative error code on failure. | |
1865 | */ | |
e7854a03 AD |
1866 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
1867 | { | |
1868 | int i, r; | |
1869 | ||
05df1f01 | 1870 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 | 1871 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
05df1f01 | 1872 | |
e7854a03 AD |
1873 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
1874 | if (!adev->ip_blocks[i].status.valid) | |
1875 | continue; | |
1876 | /* displays are handled separately */ | |
1877 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { | |
e7854a03 AD |
1878 | /* XXX handle errors */ |
1879 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
1880 | /* XXX handle errors */ | |
1881 | if (r) { | |
1882 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
1883 | adev->ip_blocks[i].version->funcs->name, r); | |
1884 | } | |
1885 | } | |
1886 | } | |
1887 | ||
e7854a03 AD |
1888 | return 0; |
1889 | } | |
1890 | ||
1891 | /** | |
1892 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
1893 | * | |
1894 | * @adev: amdgpu_device pointer | |
1895 | * | |
1896 | * Main suspend function for hardware IPs. The list of all the hardware | |
1897 | * IPs that make up the asic is walked, clockgating is disabled and the | |
1898 | * suspend callbacks are run. suspend puts the hardware and software state | |
1899 | * in each IP into a state suitable for suspend. | |
1900 | * Returns 0 on success, negative error code on failure. | |
1901 | */ | |
1902 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
1903 | { |
1904 | int i, r; | |
1905 | ||
1906 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1907 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1908 | continue; |
e7854a03 AD |
1909 | /* displays are handled in phase1 */ |
1910 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
1911 | continue; | |
d38ceaf9 | 1912 | /* XXX handle errors */ |
a1255107 | 1913 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1914 | /* XXX handle errors */ |
2c1a2784 | 1915 | if (r) { |
a1255107 AD |
1916 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1917 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1918 | } |
d38ceaf9 AD |
1919 | } |
1920 | ||
1921 | return 0; | |
1922 | } | |
1923 | ||
e7854a03 AD |
1924 | /** |
1925 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
1926 | * | |
1927 | * @adev: amdgpu_device pointer | |
1928 | * | |
1929 | * Main suspend function for hardware IPs. The list of all the hardware | |
1930 | * IPs that make up the asic is walked, clockgating is disabled and the | |
1931 | * suspend callbacks are run. suspend puts the hardware and software state | |
1932 | * in each IP into a state suitable for suspend. | |
1933 | * Returns 0 on success, negative error code on failure. | |
1934 | */ | |
1935 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
1936 | { | |
1937 | int r; | |
1938 | ||
e7819644 YT |
1939 | if (amdgpu_sriov_vf(adev)) |
1940 | amdgpu_virt_request_full_gpu(adev, false); | |
1941 | ||
e7854a03 AD |
1942 | r = amdgpu_device_ip_suspend_phase1(adev); |
1943 | if (r) | |
1944 | return r; | |
1945 | r = amdgpu_device_ip_suspend_phase2(adev); | |
1946 | ||
e7819644 YT |
1947 | if (amdgpu_sriov_vf(adev)) |
1948 | amdgpu_virt_release_full_gpu(adev, false); | |
1949 | ||
e7854a03 AD |
1950 | return r; |
1951 | } | |
1952 | ||
06ec9070 | 1953 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1954 | { |
1955 | int i, r; | |
1956 | ||
2cb681b6 ML |
1957 | static enum amd_ip_block_type ip_order[] = { |
1958 | AMD_IP_BLOCK_TYPE_GMC, | |
1959 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1960 | AMD_IP_BLOCK_TYPE_IH, |
1961 | }; | |
a90ad3c2 | 1962 | |
2cb681b6 ML |
1963 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1964 | int j; | |
1965 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1966 | |
2cb681b6 ML |
1967 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1968 | block = &adev->ip_blocks[j]; | |
1969 | ||
1970 | if (block->version->type != ip_order[i] || | |
1971 | !block->status.valid) | |
1972 | continue; | |
1973 | ||
1974 | r = block->version->funcs->hw_init(adev); | |
3f48c681 | 1975 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
1976 | if (r) |
1977 | return r; | |
a90ad3c2 ML |
1978 | } |
1979 | } | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
06ec9070 | 1984 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1985 | { |
1986 | int i, r; | |
1987 | ||
2cb681b6 ML |
1988 | static enum amd_ip_block_type ip_order[] = { |
1989 | AMD_IP_BLOCK_TYPE_SMC, | |
ef4c166d | 1990 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
1991 | AMD_IP_BLOCK_TYPE_DCE, |
1992 | AMD_IP_BLOCK_TYPE_GFX, | |
1993 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
1994 | AMD_IP_BLOCK_TYPE_UVD, |
1995 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 1996 | }; |
a90ad3c2 | 1997 | |
2cb681b6 ML |
1998 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1999 | int j; | |
2000 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2001 | |
2cb681b6 ML |
2002 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2003 | block = &adev->ip_blocks[j]; | |
2004 | ||
2005 | if (block->version->type != ip_order[i] || | |
2006 | !block->status.valid) | |
2007 | continue; | |
2008 | ||
2009 | r = block->version->funcs->hw_init(adev); | |
3f48c681 | 2010 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2011 | if (r) |
2012 | return r; | |
a90ad3c2 ML |
2013 | } |
2014 | } | |
2015 | ||
2016 | return 0; | |
2017 | } | |
2018 | ||
e3ecdffa AD |
2019 | /** |
2020 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2021 | * | |
2022 | * @adev: amdgpu_device pointer | |
2023 | * | |
2024 | * First resume function for hardware IPs. The list of all the hardware | |
2025 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2026 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2027 | * after a suspend and updates the software state as necessary. This | |
2028 | * function is also used for restoring the GPU after a GPU reset. | |
2029 | * Returns 0 on success, negative error code on failure. | |
2030 | */ | |
06ec9070 | 2031 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2032 | { |
2033 | int i, r; | |
2034 | ||
a90ad3c2 ML |
2035 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2036 | if (!adev->ip_blocks[i].status.valid) | |
2037 | continue; | |
a90ad3c2 | 2038 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2039 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2040 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
fcf0649f CZ |
2041 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2042 | if (r) { | |
2043 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2044 | adev->ip_blocks[i].version->funcs->name, r); | |
2045 | return r; | |
2046 | } | |
a90ad3c2 ML |
2047 | } |
2048 | } | |
2049 | ||
2050 | return 0; | |
2051 | } | |
2052 | ||
e3ecdffa AD |
2053 | /** |
2054 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2055 | * | |
2056 | * @adev: amdgpu_device pointer | |
2057 | * | |
2058 | * First resume function for hardware IPs. The list of all the hardware | |
2059 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2060 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2061 | * functional state after a suspend and updates the software state as | |
2062 | * necessary. This function is also used for restoring the GPU after a GPU | |
2063 | * reset. | |
2064 | * Returns 0 on success, negative error code on failure. | |
2065 | */ | |
06ec9070 | 2066 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2067 | { |
2068 | int i, r; | |
2069 | ||
2070 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2071 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2072 | continue; |
fcf0649f | 2073 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2074 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2075 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) | |
fcf0649f | 2076 | continue; |
a1255107 | 2077 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2078 | if (r) { |
a1255107 AD |
2079 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2080 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2081 | return r; |
2c1a2784 | 2082 | } |
d38ceaf9 AD |
2083 | } |
2084 | ||
2085 | return 0; | |
2086 | } | |
2087 | ||
e3ecdffa AD |
2088 | /** |
2089 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2090 | * | |
2091 | * @adev: amdgpu_device pointer | |
2092 | * | |
2093 | * Main resume function for hardware IPs. The hardware IPs | |
2094 | * are split into two resume functions because they are | |
2095 | * are also used in in recovering from a GPU reset and some additional | |
2096 | * steps need to be take between them. In this case (S3/S4) they are | |
2097 | * run sequentially. | |
2098 | * Returns 0 on success, negative error code on failure. | |
2099 | */ | |
06ec9070 | 2100 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2101 | { |
2102 | int r; | |
2103 | ||
06ec9070 | 2104 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2105 | if (r) |
2106 | return r; | |
06ec9070 | 2107 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2108 | |
2109 | return r; | |
2110 | } | |
2111 | ||
e3ecdffa AD |
2112 | /** |
2113 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2114 | * | |
2115 | * @adev: amdgpu_device pointer | |
2116 | * | |
2117 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2118 | */ | |
4e99a44e | 2119 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2120 | { |
6867e1b5 ML |
2121 | if (amdgpu_sriov_vf(adev)) { |
2122 | if (adev->is_atom_fw) { | |
2123 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2124 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2125 | } else { | |
2126 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2127 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2128 | } | |
2129 | ||
2130 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2131 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2132 | } |
048765ad AR |
2133 | } |
2134 | ||
e3ecdffa AD |
2135 | /** |
2136 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2137 | * | |
2138 | * @asic_type: AMD asic type | |
2139 | * | |
2140 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2141 | * returns true if DC has support, false if not. | |
2142 | */ | |
4562236b HW |
2143 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2144 | { | |
2145 | switch (asic_type) { | |
2146 | #if defined(CONFIG_DRM_AMD_DC) | |
2147 | case CHIP_BONAIRE: | |
0d6fbccb | 2148 | case CHIP_KAVERI: |
367e6687 AD |
2149 | case CHIP_KABINI: |
2150 | case CHIP_MULLINS: | |
d9fda248 HW |
2151 | /* |
2152 | * We have systems in the wild with these ASICs that require | |
2153 | * LVDS and VGA support which is not supported with DC. | |
2154 | * | |
2155 | * Fallback to the non-DC driver here by default so as not to | |
2156 | * cause regressions. | |
2157 | */ | |
2158 | return amdgpu_dc > 0; | |
2159 | case CHIP_HAWAII: | |
4562236b HW |
2160 | case CHIP_CARRIZO: |
2161 | case CHIP_STONEY: | |
4562236b | 2162 | case CHIP_POLARIS10: |
675fd32b | 2163 | case CHIP_POLARIS11: |
2c8ad2d5 | 2164 | case CHIP_POLARIS12: |
675fd32b | 2165 | case CHIP_VEGAM: |
4562236b HW |
2166 | case CHIP_TONGA: |
2167 | case CHIP_FIJI: | |
42f8ffa1 | 2168 | case CHIP_VEGA10: |
dca7b401 | 2169 | case CHIP_VEGA12: |
c6034aa2 | 2170 | case CHIP_VEGA20: |
dc37a9a0 | 2171 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
fd187853 | 2172 | case CHIP_RAVEN: |
42f8ffa1 | 2173 | #endif |
fd187853 | 2174 | return amdgpu_dc != 0; |
4562236b HW |
2175 | #endif |
2176 | default: | |
2177 | return false; | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | /** | |
2182 | * amdgpu_device_has_dc_support - check if dc is supported | |
2183 | * | |
2184 | * @adev: amdgpu_device_pointer | |
2185 | * | |
2186 | * Returns true for supported, false for not supported | |
2187 | */ | |
2188 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2189 | { | |
2555039d XY |
2190 | if (amdgpu_sriov_vf(adev)) |
2191 | return false; | |
2192 | ||
4562236b HW |
2193 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2194 | } | |
2195 | ||
d38ceaf9 AD |
2196 | /** |
2197 | * amdgpu_device_init - initialize the driver | |
2198 | * | |
2199 | * @adev: amdgpu_device pointer | |
87e3f136 | 2200 | * @ddev: drm dev pointer |
d38ceaf9 AD |
2201 | * @pdev: pci dev pointer |
2202 | * @flags: driver flags | |
2203 | * | |
2204 | * Initializes the driver info and hw (all asics). | |
2205 | * Returns 0 for success or an error on failure. | |
2206 | * Called at driver startup. | |
2207 | */ | |
2208 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2209 | struct drm_device *ddev, | |
2210 | struct pci_dev *pdev, | |
2211 | uint32_t flags) | |
2212 | { | |
2213 | int r, i; | |
2214 | bool runtime = false; | |
95844d20 | 2215 | u32 max_MBps; |
d38ceaf9 AD |
2216 | |
2217 | adev->shutdown = false; | |
2218 | adev->dev = &pdev->dev; | |
2219 | adev->ddev = ddev; | |
2220 | adev->pdev = pdev; | |
2221 | adev->flags = flags; | |
2f7d10b3 | 2222 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2223 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 SL |
2224 | if (amdgpu_emu_mode == 1) |
2225 | adev->usec_timeout *= 2; | |
770d13b1 | 2226 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2227 | adev->accel_working = false; |
2228 | adev->num_rings = 0; | |
2229 | adev->mman.buffer_funcs = NULL; | |
2230 | adev->mman.buffer_funcs_ring = NULL; | |
2231 | adev->vm_manager.vm_pte_funcs = NULL; | |
3798e9a6 | 2232 | adev->vm_manager.vm_pte_num_rqs = 0; |
132f34e4 | 2233 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 2234 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2235 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2236 | |
2237 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2238 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2239 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2240 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2241 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2242 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2243 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2244 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2245 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2246 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2247 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2248 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2249 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2250 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2251 | ||
3e39ab90 AD |
2252 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2253 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2254 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2255 | |
2256 | /* mutex initialization are all done here so we | |
2257 | * can recall function without having locking issues */ | |
d38ceaf9 | 2258 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2259 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2260 | mutex_init(&adev->pm.mutex); |
2261 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2262 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2263 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 2264 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 2265 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2266 | mutex_init(&adev->mn_lock); |
e23b74aa | 2267 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 2268 | hash_init(adev->mn_hash); |
13a752e3 | 2269 | mutex_init(&adev->lock_reset); |
d38ceaf9 | 2270 | |
06ec9070 | 2271 | amdgpu_device_check_arguments(adev); |
d38ceaf9 | 2272 | |
d38ceaf9 AD |
2273 | spin_lock_init(&adev->mmio_idx_lock); |
2274 | spin_lock_init(&adev->smc_idx_lock); | |
2275 | spin_lock_init(&adev->pcie_idx_lock); | |
2276 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2277 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2278 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2279 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2280 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2281 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2282 | |
0c4e7fa5 CZ |
2283 | INIT_LIST_HEAD(&adev->shadow_list); |
2284 | mutex_init(&adev->shadow_list_lock); | |
2285 | ||
795f2813 AR |
2286 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2287 | spin_lock_init(&adev->ring_lru_list_lock); | |
2288 | ||
06ec9070 AD |
2289 | INIT_DELAYED_WORK(&adev->late_init_work, |
2290 | amdgpu_device_ip_late_init_func_handler); | |
1e317b99 RZ |
2291 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
2292 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 2293 | |
d23ee13f | 2294 | adev->gfx.gfx_off_req_count = 1; |
b1ddf548 RZ |
2295 | adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false; |
2296 | ||
0fa49558 AX |
2297 | /* Registers mapping */ |
2298 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2299 | if (adev->asic_type >= CHIP_BONAIRE) { |
2300 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2301 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2302 | } else { | |
2303 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2304 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2305 | } | |
d38ceaf9 | 2306 | |
d38ceaf9 AD |
2307 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2308 | if (adev->rmmio == NULL) { | |
2309 | return -ENOMEM; | |
2310 | } | |
2311 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2312 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2313 | ||
705e519e | 2314 | /* doorbell bar mapping */ |
06ec9070 | 2315 | amdgpu_device_doorbell_init(adev); |
d38ceaf9 AD |
2316 | |
2317 | /* io port mapping */ | |
2318 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2319 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2320 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2321 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2322 | break; | |
2323 | } | |
2324 | } | |
2325 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2326 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 2327 | |
5494d864 AD |
2328 | amdgpu_device_get_pcie_info(adev); |
2329 | ||
d38ceaf9 | 2330 | /* early init functions */ |
06ec9070 | 2331 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
2332 | if (r) |
2333 | return r; | |
2334 | ||
2335 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2336 | /* this will fail for cards that aren't VGA class devices, just | |
2337 | * ignore it */ | |
06ec9070 | 2338 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 2339 | |
e9bef455 | 2340 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2341 | runtime = true; |
84c8b22e LW |
2342 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2343 | vga_switcheroo_register_client(adev->pdev, | |
2344 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2345 | if (runtime) |
2346 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2347 | ||
9475a943 SL |
2348 | if (amdgpu_emu_mode == 1) { |
2349 | /* post the asic on emulation mode */ | |
2350 | emu_soc_asic_init(adev); | |
bfca0289 | 2351 | goto fence_driver_init; |
9475a943 | 2352 | } |
bfca0289 | 2353 | |
d38ceaf9 | 2354 | /* Read BIOS */ |
83ba126a AD |
2355 | if (!amdgpu_get_bios(adev)) { |
2356 | r = -EINVAL; | |
2357 | goto failed; | |
2358 | } | |
f7e9e9fe | 2359 | |
d38ceaf9 | 2360 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2361 | if (r) { |
2362 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
e23b74aa | 2363 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2364 | goto failed; |
2c1a2784 | 2365 | } |
d38ceaf9 | 2366 | |
4e99a44e ML |
2367 | /* detect if we are with an SRIOV vbios */ |
2368 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2369 | |
d38ceaf9 | 2370 | /* Post card if necessary */ |
39c640c0 | 2371 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 2372 | if (!adev->bios) { |
bec86378 | 2373 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2374 | r = -EINVAL; |
2375 | goto failed; | |
d38ceaf9 | 2376 | } |
bec86378 | 2377 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2378 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2379 | if (r) { | |
2380 | dev_err(adev->dev, "gpu post error!\n"); | |
2381 | goto failed; | |
2382 | } | |
d38ceaf9 AD |
2383 | } |
2384 | ||
88b64e95 AD |
2385 | if (adev->is_atom_fw) { |
2386 | /* Initialize clocks */ | |
2387 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2388 | if (r) { | |
2389 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2390 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2391 | goto failed; |
2392 | } | |
2393 | } else { | |
a5bde2f9 AD |
2394 | /* Initialize clocks */ |
2395 | r = amdgpu_atombios_get_clock_info(adev); | |
2396 | if (r) { | |
2397 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2398 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2399 | goto failed; |
a5bde2f9 AD |
2400 | } |
2401 | /* init i2c buses */ | |
4562236b HW |
2402 | if (!amdgpu_device_has_dc_support(adev)) |
2403 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2404 | } |
d38ceaf9 | 2405 | |
bfca0289 | 2406 | fence_driver_init: |
d38ceaf9 AD |
2407 | /* Fence driver */ |
2408 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2409 | if (r) { |
2410 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2411 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2412 | goto failed; |
2c1a2784 | 2413 | } |
d38ceaf9 AD |
2414 | |
2415 | /* init the mode config */ | |
2416 | drm_mode_config_init(adev->ddev); | |
2417 | ||
06ec9070 | 2418 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 2419 | if (r) { |
8840a387 | 2420 | /* failed in exclusive mode due to timeout */ |
2421 | if (amdgpu_sriov_vf(adev) && | |
2422 | !amdgpu_sriov_runtime(adev) && | |
2423 | amdgpu_virt_mmio_blocked(adev) && | |
2424 | !amdgpu_virt_wait_reset(adev)) { | |
2425 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
2426 | /* Don't send request since VF is inactive. */ |
2427 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
2428 | adev->virt.ops = NULL; | |
8840a387 | 2429 | r = -EAGAIN; |
2430 | goto failed; | |
2431 | } | |
06ec9070 | 2432 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 2433 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
83ba126a | 2434 | goto failed; |
d38ceaf9 AD |
2435 | } |
2436 | ||
2437 | adev->accel_working = true; | |
2438 | ||
e59c0205 AX |
2439 | amdgpu_vm_check_compute_bug(adev); |
2440 | ||
95844d20 MO |
2441 | /* Initialize the buffer migration limit. */ |
2442 | if (amdgpu_moverate >= 0) | |
2443 | max_MBps = amdgpu_moverate; | |
2444 | else | |
2445 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2446 | /* Get a log2 for easy divisions. */ | |
2447 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2448 | ||
d38ceaf9 AD |
2449 | r = amdgpu_ib_pool_init(adev); |
2450 | if (r) { | |
2451 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
e23b74aa | 2452 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2453 | goto failed; |
d38ceaf9 AD |
2454 | } |
2455 | ||
2dc8f81e HC |
2456 | if (amdgpu_sriov_vf(adev)) |
2457 | amdgpu_virt_init_data_exchange(adev); | |
2458 | ||
9bc92b9c ML |
2459 | amdgpu_fbdev_init(adev); |
2460 | ||
d2f52ac8 RZ |
2461 | r = amdgpu_pm_sysfs_init(adev); |
2462 | if (r) | |
2463 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2464 | ||
75758255 | 2465 | r = amdgpu_debugfs_gem_init(adev); |
3f14e623 | 2466 | if (r) |
d38ceaf9 | 2467 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2468 | |
2469 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2470 | if (r) |
d38ceaf9 | 2471 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2472 | |
50ab2533 | 2473 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2474 | if (r) |
50ab2533 | 2475 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2476 | |
763efb6c | 2477 | r = amdgpu_debugfs_init(adev); |
db95e218 | 2478 | if (r) |
763efb6c | 2479 | DRM_ERROR("Creating debugfs files failed (%d).\n", r); |
db95e218 | 2480 | |
d38ceaf9 AD |
2481 | if ((amdgpu_testing & 1)) { |
2482 | if (adev->accel_working) | |
2483 | amdgpu_test_moves(adev); | |
2484 | else | |
2485 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2486 | } | |
d38ceaf9 AD |
2487 | if (amdgpu_benchmarking) { |
2488 | if (adev->accel_working) | |
2489 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2490 | else | |
2491 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2492 | } | |
2493 | ||
2494 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2495 | * explicit gating rather than handling it automatically. | |
2496 | */ | |
06ec9070 | 2497 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 2498 | if (r) { |
06ec9070 | 2499 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 2500 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2501 | goto failed; |
2c1a2784 | 2502 | } |
d38ceaf9 AD |
2503 | |
2504 | return 0; | |
83ba126a AD |
2505 | |
2506 | failed: | |
89041940 | 2507 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2508 | if (runtime) |
2509 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 2510 | |
83ba126a | 2511 | return r; |
d38ceaf9 AD |
2512 | } |
2513 | ||
d38ceaf9 AD |
2514 | /** |
2515 | * amdgpu_device_fini - tear down the driver | |
2516 | * | |
2517 | * @adev: amdgpu_device pointer | |
2518 | * | |
2519 | * Tear down the driver info (all asics). | |
2520 | * Called at driver shutdown. | |
2521 | */ | |
2522 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2523 | { | |
2524 | int r; | |
2525 | ||
2526 | DRM_INFO("amdgpu: finishing device.\n"); | |
2527 | adev->shutdown = true; | |
e5b03032 ML |
2528 | /* disable all interrupts */ |
2529 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
2530 | if (adev->mode_info.mode_config_initialized){ |
2531 | if (!amdgpu_device_has_dc_support(adev)) | |
2532 | drm_crtc_force_disable_all(adev->ddev); | |
2533 | else | |
2534 | drm_atomic_helper_shutdown(adev->ddev); | |
2535 | } | |
d38ceaf9 AD |
2536 | amdgpu_ib_pool_fini(adev); |
2537 | amdgpu_fence_driver_fini(adev); | |
58e955d9 | 2538 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2539 | amdgpu_fbdev_fini(adev); |
06ec9070 | 2540 | r = amdgpu_device_ip_fini(adev); |
ab4fe3e1 HR |
2541 | if (adev->firmware.gpu_info_fw) { |
2542 | release_firmware(adev->firmware.gpu_info_fw); | |
2543 | adev->firmware.gpu_info_fw = NULL; | |
2544 | } | |
d38ceaf9 | 2545 | adev->accel_working = false; |
2dc80b00 | 2546 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 | 2547 | /* free i2c buses */ |
4562236b HW |
2548 | if (!amdgpu_device_has_dc_support(adev)) |
2549 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
2550 | |
2551 | if (amdgpu_emu_mode != 1) | |
2552 | amdgpu_atombios_fini(adev); | |
2553 | ||
d38ceaf9 AD |
2554 | kfree(adev->bios); |
2555 | adev->bios = NULL; | |
84c8b22e LW |
2556 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2557 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2558 | if (adev->flags & AMD_IS_PX) |
2559 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2560 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2561 | if (adev->rio_mem) | |
2562 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2563 | adev->rio_mem = NULL; | |
2564 | iounmap(adev->rmmio); | |
2565 | adev->rmmio = NULL; | |
06ec9070 | 2566 | amdgpu_device_doorbell_fini(adev); |
d38ceaf9 | 2567 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2568 | } |
2569 | ||
2570 | ||
2571 | /* | |
2572 | * Suspend & resume. | |
2573 | */ | |
2574 | /** | |
810ddc3a | 2575 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 2576 | * |
87e3f136 DP |
2577 | * @dev: drm dev pointer |
2578 | * @suspend: suspend state | |
2579 | * @fbcon : notify the fbdev of suspend | |
d38ceaf9 AD |
2580 | * |
2581 | * Puts the hw in the suspend state (all asics). | |
2582 | * Returns 0 for success or an error on failure. | |
2583 | * Called at driver suspend. | |
2584 | */ | |
810ddc3a | 2585 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2586 | { |
2587 | struct amdgpu_device *adev; | |
2588 | struct drm_crtc *crtc; | |
2589 | struct drm_connector *connector; | |
5ceb54c6 | 2590 | int r; |
d38ceaf9 AD |
2591 | |
2592 | if (dev == NULL || dev->dev_private == NULL) { | |
2593 | return -ENODEV; | |
2594 | } | |
2595 | ||
2596 | adev = dev->dev_private; | |
2597 | ||
2598 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2599 | return 0; | |
2600 | ||
2601 | drm_kms_helper_poll_disable(dev); | |
2602 | ||
5f818173 S |
2603 | if (fbcon) |
2604 | amdgpu_fbdev_set_suspend(adev, 1); | |
2605 | ||
a5459475 RZ |
2606 | cancel_delayed_work_sync(&adev->late_init_work); |
2607 | ||
4562236b HW |
2608 | if (!amdgpu_device_has_dc_support(adev)) { |
2609 | /* turn off display hw */ | |
2610 | drm_modeset_lock_all(dev); | |
2611 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2612 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2613 | } | |
2614 | drm_modeset_unlock_all(dev); | |
fe1053b7 AD |
2615 | /* unpin the front buffers and cursors */ |
2616 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2617 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2618 | struct drm_framebuffer *fb = crtc->primary->fb; | |
2619 | struct amdgpu_bo *robj; | |
2620 | ||
2621 | if (amdgpu_crtc->cursor_bo) { | |
2622 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2623 | r = amdgpu_bo_reserve(aobj, true); | |
2624 | if (r == 0) { | |
2625 | amdgpu_bo_unpin(aobj); | |
2626 | amdgpu_bo_unreserve(aobj); | |
2627 | } | |
756e6880 | 2628 | } |
756e6880 | 2629 | |
fe1053b7 AD |
2630 | if (fb == NULL || fb->obj[0] == NULL) { |
2631 | continue; | |
2632 | } | |
2633 | robj = gem_to_amdgpu_bo(fb->obj[0]); | |
2634 | /* don't unpin kernel fb objects */ | |
2635 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
2636 | r = amdgpu_bo_reserve(robj, true); | |
2637 | if (r == 0) { | |
2638 | amdgpu_bo_unpin(robj); | |
2639 | amdgpu_bo_unreserve(robj); | |
2640 | } | |
d38ceaf9 AD |
2641 | } |
2642 | } | |
2643 | } | |
fe1053b7 AD |
2644 | |
2645 | amdgpu_amdkfd_suspend(adev); | |
2646 | ||
2647 | r = amdgpu_device_ip_suspend_phase1(adev); | |
2648 | ||
d38ceaf9 AD |
2649 | /* evict vram memory */ |
2650 | amdgpu_bo_evict_vram(adev); | |
2651 | ||
5ceb54c6 | 2652 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 2653 | |
fe1053b7 | 2654 | r = amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 2655 | |
a0a71e49 AD |
2656 | /* evict remaining vram memory |
2657 | * This second call to evict vram is to evict the gart page table | |
2658 | * using the CPU. | |
2659 | */ | |
d38ceaf9 AD |
2660 | amdgpu_bo_evict_vram(adev); |
2661 | ||
2662 | pci_save_state(dev->pdev); | |
2663 | if (suspend) { | |
2664 | /* Shut down the device */ | |
2665 | pci_disable_device(dev->pdev); | |
2666 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2667 | } else { |
2668 | r = amdgpu_asic_reset(adev); | |
2669 | if (r) | |
2670 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2671 | } |
2672 | ||
d38ceaf9 AD |
2673 | return 0; |
2674 | } | |
2675 | ||
2676 | /** | |
810ddc3a | 2677 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 2678 | * |
87e3f136 DP |
2679 | * @dev: drm dev pointer |
2680 | * @resume: resume state | |
2681 | * @fbcon : notify the fbdev of resume | |
d38ceaf9 AD |
2682 | * |
2683 | * Bring the hw back to operating state (all asics). | |
2684 | * Returns 0 for success or an error on failure. | |
2685 | * Called at driver resume. | |
2686 | */ | |
810ddc3a | 2687 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2688 | { |
2689 | struct drm_connector *connector; | |
2690 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2691 | struct drm_crtc *crtc; |
03161a6e | 2692 | int r = 0; |
d38ceaf9 AD |
2693 | |
2694 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2695 | return 0; | |
2696 | ||
d38ceaf9 AD |
2697 | if (resume) { |
2698 | pci_set_power_state(dev->pdev, PCI_D0); | |
2699 | pci_restore_state(dev->pdev); | |
74b0b157 | 2700 | r = pci_enable_device(dev->pdev); |
03161a6e | 2701 | if (r) |
4d3b9ae5 | 2702 | return r; |
d38ceaf9 AD |
2703 | } |
2704 | ||
2705 | /* post card */ | |
39c640c0 | 2706 | if (amdgpu_device_need_post(adev)) { |
74b0b157 | 2707 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2708 | if (r) | |
2709 | DRM_ERROR("amdgpu asic init failed\n"); | |
2710 | } | |
d38ceaf9 | 2711 | |
06ec9070 | 2712 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 2713 | if (r) { |
06ec9070 | 2714 | DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 2715 | return r; |
e6707218 | 2716 | } |
5ceb54c6 AD |
2717 | amdgpu_fence_driver_resume(adev); |
2718 | ||
d38ceaf9 | 2719 | |
06ec9070 | 2720 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 2721 | if (r) |
4d3b9ae5 | 2722 | return r; |
d38ceaf9 | 2723 | |
fe1053b7 AD |
2724 | if (!amdgpu_device_has_dc_support(adev)) { |
2725 | /* pin cursors */ | |
2726 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2727 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2728 | ||
2729 | if (amdgpu_crtc->cursor_bo) { | |
2730 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2731 | r = amdgpu_bo_reserve(aobj, true); | |
2732 | if (r == 0) { | |
2733 | r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); | |
2734 | if (r != 0) | |
2735 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2736 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); | |
2737 | amdgpu_bo_unreserve(aobj); | |
2738 | } | |
756e6880 AD |
2739 | } |
2740 | } | |
2741 | } | |
ba997709 YZ |
2742 | r = amdgpu_amdkfd_resume(adev); |
2743 | if (r) | |
2744 | return r; | |
756e6880 | 2745 | |
96a5d8d4 LL |
2746 | /* Make sure IB tests flushed */ |
2747 | flush_delayed_work(&adev->late_init_work); | |
2748 | ||
d38ceaf9 AD |
2749 | /* blat the mode back in */ |
2750 | if (fbcon) { | |
4562236b HW |
2751 | if (!amdgpu_device_has_dc_support(adev)) { |
2752 | /* pre DCE11 */ | |
2753 | drm_helper_resume_force_mode(dev); | |
2754 | ||
2755 | /* turn on display hw */ | |
2756 | drm_modeset_lock_all(dev); | |
2757 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2758 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2759 | } | |
2760 | drm_modeset_unlock_all(dev); | |
d38ceaf9 | 2761 | } |
4d3b9ae5 | 2762 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
2763 | } |
2764 | ||
2765 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2766 | |
2767 | /* | |
2768 | * Most of the connector probing functions try to acquire runtime pm | |
2769 | * refs to ensure that the GPU is powered on when connector polling is | |
2770 | * performed. Since we're calling this from a runtime PM callback, | |
2771 | * trying to acquire rpm refs will cause us to deadlock. | |
2772 | * | |
2773 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2774 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2775 | */ | |
2776 | #ifdef CONFIG_PM | |
2777 | dev->dev->power.disable_depth++; | |
2778 | #endif | |
4562236b HW |
2779 | if (!amdgpu_device_has_dc_support(adev)) |
2780 | drm_helper_hpd_irq_event(dev); | |
2781 | else | |
2782 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
2783 | #ifdef CONFIG_PM |
2784 | dev->dev->power.disable_depth--; | |
2785 | #endif | |
4d3b9ae5 | 2786 | return 0; |
d38ceaf9 AD |
2787 | } |
2788 | ||
e3ecdffa AD |
2789 | /** |
2790 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
2791 | * | |
2792 | * @adev: amdgpu_device pointer | |
2793 | * | |
2794 | * The list of all the hardware IPs that make up the asic is walked and | |
2795 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
2796 | * if the asic is still hung or not. | |
2797 | * Returns true if any of the IPs are still in a hung state, false if not. | |
2798 | */ | |
06ec9070 | 2799 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
2800 | { |
2801 | int i; | |
2802 | bool asic_hang = false; | |
2803 | ||
f993d628 ML |
2804 | if (amdgpu_sriov_vf(adev)) |
2805 | return true; | |
2806 | ||
8bc04c29 AD |
2807 | if (amdgpu_asic_need_full_reset(adev)) |
2808 | return true; | |
2809 | ||
63fbf42f | 2810 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2811 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2812 | continue; |
a1255107 AD |
2813 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2814 | adev->ip_blocks[i].status.hang = | |
2815 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2816 | if (adev->ip_blocks[i].status.hang) { | |
2817 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2818 | asic_hang = true; |
2819 | } | |
2820 | } | |
2821 | return asic_hang; | |
2822 | } | |
2823 | ||
e3ecdffa AD |
2824 | /** |
2825 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
2826 | * | |
2827 | * @adev: amdgpu_device pointer | |
2828 | * | |
2829 | * The list of all the hardware IPs that make up the asic is walked and the | |
2830 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
2831 | * handles any IP specific hardware or software state changes that are | |
2832 | * necessary for a soft reset to succeed. | |
2833 | * Returns 0 on success, negative error code on failure. | |
2834 | */ | |
06ec9070 | 2835 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2836 | { |
2837 | int i, r = 0; | |
2838 | ||
2839 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2840 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2841 | continue; |
a1255107 AD |
2842 | if (adev->ip_blocks[i].status.hang && |
2843 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2844 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2845 | if (r) |
2846 | return r; | |
2847 | } | |
2848 | } | |
2849 | ||
2850 | return 0; | |
2851 | } | |
2852 | ||
e3ecdffa AD |
2853 | /** |
2854 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
2855 | * | |
2856 | * @adev: amdgpu_device pointer | |
2857 | * | |
2858 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
2859 | * reset is necessary to recover. | |
2860 | * Returns true if a full asic reset is required, false if not. | |
2861 | */ | |
06ec9070 | 2862 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 2863 | { |
da146d3b AD |
2864 | int i; |
2865 | ||
8bc04c29 AD |
2866 | if (amdgpu_asic_need_full_reset(adev)) |
2867 | return true; | |
2868 | ||
da146d3b | 2869 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2870 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2871 | continue; |
a1255107 AD |
2872 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2873 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2874 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
2875 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
2876 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 2877 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
2878 | DRM_INFO("Some block need full reset!\n"); |
2879 | return true; | |
2880 | } | |
2881 | } | |
35d782fe CZ |
2882 | } |
2883 | return false; | |
2884 | } | |
2885 | ||
e3ecdffa AD |
2886 | /** |
2887 | * amdgpu_device_ip_soft_reset - do a soft reset | |
2888 | * | |
2889 | * @adev: amdgpu_device pointer | |
2890 | * | |
2891 | * The list of all the hardware IPs that make up the asic is walked and the | |
2892 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
2893 | * IP specific hardware or software state changes that are necessary to soft | |
2894 | * reset the IP. | |
2895 | * Returns 0 on success, negative error code on failure. | |
2896 | */ | |
06ec9070 | 2897 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2898 | { |
2899 | int i, r = 0; | |
2900 | ||
2901 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2902 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2903 | continue; |
a1255107 AD |
2904 | if (adev->ip_blocks[i].status.hang && |
2905 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2906 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2907 | if (r) |
2908 | return r; | |
2909 | } | |
2910 | } | |
2911 | ||
2912 | return 0; | |
2913 | } | |
2914 | ||
e3ecdffa AD |
2915 | /** |
2916 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
2917 | * | |
2918 | * @adev: amdgpu_device pointer | |
2919 | * | |
2920 | * The list of all the hardware IPs that make up the asic is walked and the | |
2921 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
2922 | * handles any IP specific hardware or software state changes that are | |
2923 | * necessary after the IP has been soft reset. | |
2924 | * Returns 0 on success, negative error code on failure. | |
2925 | */ | |
06ec9070 | 2926 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2927 | { |
2928 | int i, r = 0; | |
2929 | ||
2930 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2931 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2932 | continue; |
a1255107 AD |
2933 | if (adev->ip_blocks[i].status.hang && |
2934 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2935 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2936 | if (r) |
2937 | return r; | |
2938 | } | |
2939 | ||
2940 | return 0; | |
2941 | } | |
2942 | ||
e3ecdffa AD |
2943 | /** |
2944 | * amdgpu_device_recover_vram_from_shadow - restore shadowed VRAM buffers | |
2945 | * | |
2946 | * @adev: amdgpu_device pointer | |
2947 | * @ring: amdgpu_ring for the engine handling the buffer operations | |
2948 | * @bo: amdgpu_bo buffer whose shadow is being restored | |
2949 | * @fence: dma_fence associated with the operation | |
2950 | * | |
2951 | * Restores the VRAM buffer contents from the shadow in GTT. Used to | |
2952 | * restore things like GPUVM page tables after a GPU reset where | |
2953 | * the contents of VRAM might be lost. | |
2954 | * Returns 0 on success, negative error code on failure. | |
2955 | */ | |
06ec9070 AD |
2956 | static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev, |
2957 | struct amdgpu_ring *ring, | |
2958 | struct amdgpu_bo *bo, | |
2959 | struct dma_fence **fence) | |
53cdccd5 CZ |
2960 | { |
2961 | uint32_t domain; | |
2962 | int r; | |
2963 | ||
23d2e504 RH |
2964 | if (!bo->shadow) |
2965 | return 0; | |
2966 | ||
1d284797 | 2967 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2968 | if (r) |
2969 | return r; | |
2970 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2971 | /* if bo has been evicted, then no need to recover */ | |
2972 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2973 | r = amdgpu_bo_validate(bo->shadow); |
2974 | if (r) { | |
2975 | DRM_ERROR("bo validate failed!\n"); | |
2976 | goto err; | |
2977 | } | |
2978 | ||
23d2e504 | 2979 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2980 | NULL, fence, true); |
23d2e504 RH |
2981 | if (r) { |
2982 | DRM_ERROR("recover page table failed!\n"); | |
2983 | goto err; | |
2984 | } | |
2985 | } | |
53cdccd5 | 2986 | err: |
23d2e504 RH |
2987 | amdgpu_bo_unreserve(bo); |
2988 | return r; | |
53cdccd5 CZ |
2989 | } |
2990 | ||
e3ecdffa AD |
2991 | /** |
2992 | * amdgpu_device_handle_vram_lost - Handle the loss of VRAM contents | |
2993 | * | |
2994 | * @adev: amdgpu_device pointer | |
2995 | * | |
2996 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
2997 | * restore things like GPUVM page tables after a GPU reset where | |
2998 | * the contents of VRAM might be lost. | |
2999 | * Returns 0 on success, 1 on failure. | |
3000 | */ | |
c41d1cf6 ML |
3001 | static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev) |
3002 | { | |
3003 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
3004 | struct amdgpu_bo *bo, *tmp; | |
3005 | struct dma_fence *fence = NULL, *next = NULL; | |
3006 | long r = 1; | |
3007 | int i = 0; | |
3008 | long tmo; | |
3009 | ||
3010 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 3011 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
3012 | else |
3013 | tmo = msecs_to_jiffies(100); | |
3014 | ||
3015 | DRM_INFO("recover vram bo from shadow start\n"); | |
3016 | mutex_lock(&adev->shadow_list_lock); | |
3017 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
3018 | next = NULL; | |
3019 | amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next); | |
3020 | if (fence) { | |
3021 | r = dma_fence_wait_timeout(fence, false, tmo); | |
3022 | if (r == 0) | |
3023 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
3024 | else if (r < 0) | |
3025 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
3026 | if (r < 1) { | |
3027 | dma_fence_put(fence); | |
3028 | fence = next; | |
3029 | break; | |
3030 | } | |
3031 | i++; | |
3032 | } | |
3033 | ||
3034 | dma_fence_put(fence); | |
3035 | fence = next; | |
3036 | } | |
3037 | mutex_unlock(&adev->shadow_list_lock); | |
3038 | ||
3039 | if (fence) { | |
3040 | r = dma_fence_wait_timeout(fence, false, tmo); | |
3041 | if (r == 0) | |
3042 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
3043 | else if (r < 0) | |
3044 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
3045 | ||
3046 | } | |
3047 | dma_fence_put(fence); | |
3048 | ||
3049 | if (r > 0) | |
3050 | DRM_INFO("recover vram bo from shadow done\n"); | |
3051 | else | |
3052 | DRM_ERROR("recover vram bo from shadow failed\n"); | |
3053 | ||
e3ecdffa | 3054 | return (r > 0) ? 0 : 1; |
c41d1cf6 ML |
3055 | } |
3056 | ||
e3ecdffa | 3057 | /** |
06ec9070 | 3058 | * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough |
a90ad3c2 ML |
3059 | * |
3060 | * @adev: amdgpu device pointer | |
a90ad3c2 | 3061 | * |
5740682e | 3062 | * attempt to do soft-reset or full-reset and reinitialize Asic |
3f48c681 | 3063 | * return 0 means succeeded otherwise failed |
e3ecdffa | 3064 | */ |
c41d1cf6 | 3065 | static int amdgpu_device_reset(struct amdgpu_device *adev) |
a90ad3c2 | 3066 | { |
5740682e ML |
3067 | bool need_full_reset, vram_lost = 0; |
3068 | int r; | |
a90ad3c2 | 3069 | |
06ec9070 | 3070 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); |
a90ad3c2 | 3071 | |
5740682e | 3072 | if (!need_full_reset) { |
06ec9070 AD |
3073 | amdgpu_device_ip_pre_soft_reset(adev); |
3074 | r = amdgpu_device_ip_soft_reset(adev); | |
3075 | amdgpu_device_ip_post_soft_reset(adev); | |
3076 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
5740682e ML |
3077 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); |
3078 | need_full_reset = true; | |
3079 | } | |
5740682e | 3080 | } |
a90ad3c2 | 3081 | |
5740682e | 3082 | if (need_full_reset) { |
cdd61df6 | 3083 | r = amdgpu_device_ip_suspend(adev); |
a90ad3c2 | 3084 | |
5740682e | 3085 | retry: |
5740682e | 3086 | r = amdgpu_asic_reset(adev); |
5740682e ML |
3087 | /* post card */ |
3088 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
65781c78 | 3089 | |
5740682e ML |
3090 | if (!r) { |
3091 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
06ec9070 | 3092 | r = amdgpu_device_ip_resume_phase1(adev); |
5740682e ML |
3093 | if (r) |
3094 | goto out; | |
65781c78 | 3095 | |
06ec9070 | 3096 | vram_lost = amdgpu_device_check_vram_lost(adev); |
5740682e ML |
3097 | if (vram_lost) { |
3098 | DRM_ERROR("VRAM is lost!\n"); | |
3099 | atomic_inc(&adev->vram_lost_counter); | |
3100 | } | |
3101 | ||
c1c7ce8f CK |
3102 | r = amdgpu_gtt_mgr_recover( |
3103 | &adev->mman.bdev.man[TTM_PL_TT]); | |
5740682e ML |
3104 | if (r) |
3105 | goto out; | |
3106 | ||
06ec9070 | 3107 | r = amdgpu_device_ip_resume_phase2(adev); |
5740682e ML |
3108 | if (r) |
3109 | goto out; | |
3110 | ||
3111 | if (vram_lost) | |
06ec9070 | 3112 | amdgpu_device_fill_reset_magic(adev); |
65781c78 | 3113 | } |
5740682e | 3114 | } |
65781c78 | 3115 | |
5740682e ML |
3116 | out: |
3117 | if (!r) { | |
3118 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
3119 | r = amdgpu_ib_ring_tests(adev); | |
3120 | if (r) { | |
3121 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
cdd61df6 | 3122 | r = amdgpu_device_ip_suspend(adev); |
5740682e ML |
3123 | need_full_reset = true; |
3124 | goto retry; | |
3125 | } | |
3126 | } | |
65781c78 | 3127 | |
c41d1cf6 ML |
3128 | if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost)) |
3129 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 | 3130 | |
5740682e ML |
3131 | return r; |
3132 | } | |
a90ad3c2 | 3133 | |
e3ecdffa | 3134 | /** |
06ec9070 | 3135 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3136 | * |
3137 | * @adev: amdgpu device pointer | |
87e3f136 | 3138 | * @from_hypervisor: request from hypervisor |
5740682e ML |
3139 | * |
3140 | * do VF FLR and reinitialize Asic | |
3f48c681 | 3141 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
3142 | */ |
3143 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3144 | bool from_hypervisor) | |
5740682e ML |
3145 | { |
3146 | int r; | |
3147 | ||
3148 | if (from_hypervisor) | |
3149 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3150 | else | |
3151 | r = amdgpu_virt_reset_gpu(adev); | |
3152 | if (r) | |
3153 | return r; | |
a90ad3c2 ML |
3154 | |
3155 | /* Resume IP prior to SMC */ | |
06ec9070 | 3156 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3157 | if (r) |
3158 | goto error; | |
a90ad3c2 ML |
3159 | |
3160 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 3161 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 ML |
3162 | |
3163 | /* now we are okay to resume SMC/CP/SDMA */ | |
06ec9070 | 3164 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
3165 | if (r) |
3166 | goto error; | |
a90ad3c2 ML |
3167 | |
3168 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3169 | r = amdgpu_ib_ring_tests(adev); |
a90ad3c2 | 3170 | |
abc34253 ED |
3171 | error: |
3172 | amdgpu_virt_release_full_gpu(adev, true); | |
c41d1cf6 ML |
3173 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
3174 | atomic_inc(&adev->vram_lost_counter); | |
3175 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 ML |
3176 | } |
3177 | ||
3178 | return r; | |
3179 | } | |
3180 | ||
12938fad CK |
3181 | /** |
3182 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
3183 | * | |
3184 | * @adev: amdgpu device pointer | |
3185 | * | |
3186 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
3187 | * a hung GPU. | |
3188 | */ | |
3189 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
3190 | { | |
3191 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
3192 | DRM_INFO("Timeout, but no hardware hang detected.\n"); | |
3193 | return false; | |
3194 | } | |
3195 | ||
3196 | if (amdgpu_gpu_recovery == 0 || (amdgpu_gpu_recovery == -1 && | |
3197 | !amdgpu_sriov_vf(adev))) { | |
3198 | DRM_INFO("GPU recovery disabled.\n"); | |
3199 | return false; | |
3200 | } | |
3201 | ||
3202 | return true; | |
3203 | } | |
3204 | ||
d38ceaf9 | 3205 | /** |
5f152b5e | 3206 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler |
d38ceaf9 AD |
3207 | * |
3208 | * @adev: amdgpu device pointer | |
5740682e | 3209 | * @job: which job trigger hang |
d38ceaf9 | 3210 | * |
5740682e | 3211 | * Attempt to reset the GPU if it has hung (all asics). |
d38ceaf9 AD |
3212 | * Returns 0 for success or an error on failure. |
3213 | */ | |
5f152b5e | 3214 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
12938fad | 3215 | struct amdgpu_job *job) |
d38ceaf9 | 3216 | { |
5740682e | 3217 | int i, r, resched; |
fb140b29 | 3218 | |
5740682e ML |
3219 | dev_info(adev->dev, "GPU reset begin!\n"); |
3220 | ||
13a752e3 | 3221 | mutex_lock(&adev->lock_reset); |
d94aed5a | 3222 | atomic_inc(&adev->gpu_reset_counter); |
13a752e3 | 3223 | adev->in_gpu_reset = 1; |
d38ceaf9 | 3224 | |
5c6dd71e SL |
3225 | /* Block kfd */ |
3226 | amdgpu_amdkfd_pre_reset(adev); | |
3227 | ||
a3c47d6b CZ |
3228 | /* block TTM */ |
3229 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
71182665 | 3230 | |
71182665 | 3231 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
3232 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3233 | struct amdgpu_ring *ring = adev->rings[i]; | |
3234 | ||
51687759 | 3235 | if (!ring || !ring->sched.thread) |
0875dc9e | 3236 | continue; |
5740682e | 3237 | |
71182665 ML |
3238 | kthread_park(ring->sched.thread); |
3239 | ||
3320b8d2 | 3240 | if (job && job->base.sched == &ring->sched) |
5740682e ML |
3241 | continue; |
3242 | ||
67ccea60 | 3243 | drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL); |
5740682e | 3244 | |
2f9d4084 ML |
3245 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
3246 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 3247 | } |
d38ceaf9 | 3248 | |
5740682e | 3249 | if (amdgpu_sriov_vf(adev)) |
c41d1cf6 | 3250 | r = amdgpu_device_reset_sriov(adev, job ? false : true); |
5740682e | 3251 | else |
c41d1cf6 | 3252 | r = amdgpu_device_reset(adev); |
5740682e | 3253 | |
71182665 ML |
3254 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3255 | struct amdgpu_ring *ring = adev->rings[i]; | |
53cdccd5 | 3256 | |
71182665 ML |
3257 | if (!ring || !ring->sched.thread) |
3258 | continue; | |
5740682e | 3259 | |
71182665 ML |
3260 | /* only need recovery sched of the given job's ring |
3261 | * or all rings (in the case @job is NULL) | |
3262 | * after above amdgpu_reset accomplished | |
3263 | */ | |
3320b8d2 | 3264 | if ((!job || job->base.sched == &ring->sched) && !r) |
1b1f42d8 | 3265 | drm_sched_job_recovery(&ring->sched); |
5740682e | 3266 | |
71182665 | 3267 | kthread_unpark(ring->sched.thread); |
d38ceaf9 AD |
3268 | } |
3269 | ||
bf830604 | 3270 | if (!amdgpu_device_has_dc_support(adev)) { |
4562236b | 3271 | drm_helper_resume_force_mode(adev->ddev); |
5740682e | 3272 | } |
d38ceaf9 AD |
3273 | |
3274 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
5740682e | 3275 | |
89041940 | 3276 | if (r) { |
d38ceaf9 | 3277 | /* bad news, how to tell it to userspace ? */ |
5740682e ML |
3278 | dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); |
3279 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); | |
3280 | } else { | |
3f48c681 | 3281 | dev_info(adev->dev, "GPU reset(%d) succeeded!\n",atomic_read(&adev->gpu_reset_counter)); |
89041940 | 3282 | } |
d38ceaf9 | 3283 | |
5c6dd71e SL |
3284 | /*unlock kfd */ |
3285 | amdgpu_amdkfd_post_reset(adev); | |
89041940 | 3286 | amdgpu_vf_error_trans_all(adev); |
13a752e3 ML |
3287 | adev->in_gpu_reset = 0; |
3288 | mutex_unlock(&adev->lock_reset); | |
d38ceaf9 AD |
3289 | return r; |
3290 | } | |
3291 | ||
e3ecdffa AD |
3292 | /** |
3293 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
3294 | * | |
3295 | * @adev: amdgpu_device pointer | |
3296 | * | |
3297 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
3298 | * and lanes) of the slot the device is in. Handles APUs and | |
3299 | * virtualized environments where PCIE config space may not be available. | |
3300 | */ | |
5494d864 | 3301 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 3302 | { |
5d9a6330 AD |
3303 | struct pci_dev *pdev; |
3304 | enum pci_bus_speed speed_cap; | |
3305 | enum pcie_link_width link_width; | |
d0dd7f0c | 3306 | |
cd474ba0 AD |
3307 | if (amdgpu_pcie_gen_cap) |
3308 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3309 | |
cd474ba0 AD |
3310 | if (amdgpu_pcie_lane_cap) |
3311 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3312 | |
cd474ba0 AD |
3313 | /* covers APUs as well */ |
3314 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3315 | if (adev->pm.pcie_gen_mask == 0) | |
3316 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3317 | if (adev->pm.pcie_mlw_mask == 0) | |
3318 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3319 | return; |
cd474ba0 | 3320 | } |
d0dd7f0c | 3321 | |
cd474ba0 | 3322 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
3323 | /* asic caps */ |
3324 | pdev = adev->pdev; | |
3325 | speed_cap = pcie_get_speed_cap(pdev); | |
3326 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
3327 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
3328 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
3329 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 3330 | } else { |
5d9a6330 AD |
3331 | if (speed_cap == PCIE_SPEED_16_0GT) |
3332 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3333 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3334 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
3335 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
3336 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
3337 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3338 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3339 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3340 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
3341 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3342 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3343 | else | |
3344 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3345 | } | |
3346 | /* platform caps */ | |
3347 | pdev = adev->ddev->pdev->bus->self; | |
3348 | speed_cap = pcie_get_speed_cap(pdev); | |
3349 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
3350 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3351 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3352 | } else { | |
3353 | if (speed_cap == PCIE_SPEED_16_0GT) | |
3354 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3355 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3356 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
3357 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
3358 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
3359 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3360 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3361 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3362 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
3363 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3364 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3365 | else | |
3366 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3367 | ||
cd474ba0 AD |
3368 | } |
3369 | } | |
3370 | if (adev->pm.pcie_mlw_mask == 0) { | |
5d9a6330 AD |
3371 | pdev = adev->ddev->pdev->bus->self; |
3372 | link_width = pcie_get_width_cap(pdev); | |
3373 | if (link_width == PCIE_LNK_WIDTH_UNKNOWN) { | |
3374 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
3375 | } else { | |
3376 | switch (link_width) { | |
3377 | case PCIE_LNK_X32: | |
cd474ba0 AD |
3378 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
3379 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3380 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3381 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3382 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3383 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3384 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3385 | break; | |
5d9a6330 | 3386 | case PCIE_LNK_X16: |
cd474ba0 AD |
3387 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
3388 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3389 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3390 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3391 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3392 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3393 | break; | |
5d9a6330 | 3394 | case PCIE_LNK_X12: |
cd474ba0 AD |
3395 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
3396 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3397 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3398 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3399 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3400 | break; | |
5d9a6330 | 3401 | case PCIE_LNK_X8: |
cd474ba0 AD |
3402 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
3403 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3404 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3405 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3406 | break; | |
5d9a6330 | 3407 | case PCIE_LNK_X4: |
cd474ba0 AD |
3408 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
3409 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3410 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3411 | break; | |
5d9a6330 | 3412 | case PCIE_LNK_X2: |
cd474ba0 AD |
3413 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
3414 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3415 | break; | |
5d9a6330 | 3416 | case PCIE_LNK_X1: |
cd474ba0 AD |
3417 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
3418 | break; | |
3419 | default: | |
3420 | break; | |
3421 | } | |
d0dd7f0c AD |
3422 | } |
3423 | } | |
3424 | } | |
d38ceaf9 | 3425 |