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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
fdf2f6c5 | 33 | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 35 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
36 | #include <drm/amdgpu_drm.h> |
37 | #include <linux/vgaarb.h> | |
38 | #include <linux/vga_switcheroo.h> | |
39 | #include <linux/efi.h> | |
40 | #include "amdgpu.h" | |
f4b373f4 | 41 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
42 | #include "amdgpu_i2c.h" |
43 | #include "atom.h" | |
44 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 45 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 46 | #include "amd_pcie.h" |
33f34802 KW |
47 | #ifdef CONFIG_DRM_AMDGPU_SI |
48 | #include "si.h" | |
49 | #endif | |
a2e73f56 AD |
50 | #ifdef CONFIG_DRM_AMDGPU_CIK |
51 | #include "cik.h" | |
52 | #endif | |
aaa36a97 | 53 | #include "vi.h" |
460826e6 | 54 | #include "soc15.h" |
0a5b8c7b | 55 | #include "nv.h" |
d38ceaf9 | 56 | #include "bif/bif_4_1_d.h" |
9accf2fd | 57 | #include <linux/pci.h> |
bec86378 | 58 | #include <linux/firmware.h> |
89041940 | 59 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 60 | |
ba997709 | 61 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 62 | #include "amdgpu_pm.h" |
d38ceaf9 | 63 | |
5183411b | 64 | #include "amdgpu_xgmi.h" |
c030f2e4 | 65 | #include "amdgpu_ras.h" |
9c7c85f7 | 66 | #include "amdgpu_pmu.h" |
bd607166 | 67 | #include "amdgpu_fru_eeprom.h" |
5183411b | 68 | |
d5ea093e | 69 | #include <linux/suspend.h> |
c6a6e2db | 70 | #include <drm/task_barrier.h> |
3f12acc8 | 71 | #include <linux/pm_runtime.h> |
d5ea093e | 72 | |
e2a75f88 | 73 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 74 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 75 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 76 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 77 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 78 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 79 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 80 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 81 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 82 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
c0a43457 | 83 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_gpu_info.bin"); |
120eb833 | 84 | MODULE_FIRMWARE("amdgpu/navy_flounder_gpu_info.bin"); |
e2a75f88 | 85 | |
2dc80b00 S |
86 | #define AMDGPU_RESUME_MS 2000 |
87 | ||
050091ab | 88 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
89 | "TAHITI", |
90 | "PITCAIRN", | |
91 | "VERDE", | |
92 | "OLAND", | |
93 | "HAINAN", | |
d38ceaf9 AD |
94 | "BONAIRE", |
95 | "KAVERI", | |
96 | "KABINI", | |
97 | "HAWAII", | |
98 | "MULLINS", | |
99 | "TOPAZ", | |
100 | "TONGA", | |
48299f95 | 101 | "FIJI", |
d38ceaf9 | 102 | "CARRIZO", |
139f4917 | 103 | "STONEY", |
2cc0c0b5 FC |
104 | "POLARIS10", |
105 | "POLARIS11", | |
c4642a47 | 106 | "POLARIS12", |
48ff108d | 107 | "VEGAM", |
d4196f01 | 108 | "VEGA10", |
8fab806a | 109 | "VEGA12", |
956fcddc | 110 | "VEGA20", |
2ca8a5d2 | 111 | "RAVEN", |
d6c3b24e | 112 | "ARCTURUS", |
1eee4228 | 113 | "RENOIR", |
852a6626 | 114 | "NAVI10", |
87dbad02 | 115 | "NAVI14", |
9802f5d7 | 116 | "NAVI12", |
ccaf72d3 | 117 | "SIENNA_CICHLID", |
ddd8fbe7 | 118 | "NAVY_FLOUNDER", |
d38ceaf9 AD |
119 | "LAST", |
120 | }; | |
121 | ||
dcea6e65 KR |
122 | /** |
123 | * DOC: pcie_replay_count | |
124 | * | |
125 | * The amdgpu driver provides a sysfs API for reporting the total number | |
126 | * of PCIe replays (NAKs) | |
127 | * The file pcie_replay_count is used for this and returns the total | |
128 | * number of replays as a sum of the NAKs generated and NAKs received | |
129 | */ | |
130 | ||
131 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
132 | struct device_attribute *attr, char *buf) | |
133 | { | |
134 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 135 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
136 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
137 | ||
138 | return snprintf(buf, PAGE_SIZE, "%llu\n", cnt); | |
139 | } | |
140 | ||
141 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
142 | amdgpu_device_get_pcie_replay_count, NULL); | |
143 | ||
5494d864 AD |
144 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
145 | ||
bd607166 KR |
146 | /** |
147 | * DOC: product_name | |
148 | * | |
149 | * The amdgpu driver provides a sysfs API for reporting the product name | |
150 | * for the device | |
151 | * The file serial_number is used for this and returns the product name | |
152 | * as returned from the FRU. | |
153 | * NOTE: This is only available for certain server cards | |
154 | */ | |
155 | ||
156 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
157 | struct device_attribute *attr, char *buf) | |
158 | { | |
159 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 160 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
161 | |
162 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name); | |
163 | } | |
164 | ||
165 | static DEVICE_ATTR(product_name, S_IRUGO, | |
166 | amdgpu_device_get_product_name, NULL); | |
167 | ||
168 | /** | |
169 | * DOC: product_number | |
170 | * | |
171 | * The amdgpu driver provides a sysfs API for reporting the part number | |
172 | * for the device | |
173 | * The file serial_number is used for this and returns the part number | |
174 | * as returned from the FRU. | |
175 | * NOTE: This is only available for certain server cards | |
176 | */ | |
177 | ||
178 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
179 | struct device_attribute *attr, char *buf) | |
180 | { | |
181 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 182 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
183 | |
184 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number); | |
185 | } | |
186 | ||
187 | static DEVICE_ATTR(product_number, S_IRUGO, | |
188 | amdgpu_device_get_product_number, NULL); | |
189 | ||
190 | /** | |
191 | * DOC: serial_number | |
192 | * | |
193 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
194 | * for the device | |
195 | * The file serial_number is used for this and returns the serial number | |
196 | * as returned from the FRU. | |
197 | * NOTE: This is only available for certain server cards | |
198 | */ | |
199 | ||
200 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
201 | struct device_attribute *attr, char *buf) | |
202 | { | |
203 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 204 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
205 | |
206 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial); | |
207 | } | |
208 | ||
209 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
210 | amdgpu_device_get_serial_number, NULL); | |
211 | ||
e3ecdffa | 212 | /** |
31af062a | 213 | * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control |
e3ecdffa AD |
214 | * |
215 | * @dev: drm_device pointer | |
216 | * | |
217 | * Returns true if the device is a dGPU with HG/PX power control, | |
218 | * otherwise return false. | |
219 | */ | |
31af062a | 220 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 221 | { |
1348969a | 222 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 223 | |
2f7d10b3 | 224 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
225 | return true; |
226 | return false; | |
227 | } | |
228 | ||
a69cba42 AD |
229 | /** |
230 | * amdgpu_device_supports_baco - Does the device support BACO | |
231 | * | |
232 | * @dev: drm_device pointer | |
233 | * | |
234 | * Returns true if the device supporte BACO, | |
235 | * otherwise return false. | |
236 | */ | |
237 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
238 | { | |
1348969a | 239 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
240 | |
241 | return amdgpu_asic_supports_baco(adev); | |
242 | } | |
243 | ||
e35e2b11 TY |
244 | /** |
245 | * VRAM access helper functions. | |
246 | * | |
247 | * amdgpu_device_vram_access - read/write a buffer in vram | |
248 | * | |
249 | * @adev: amdgpu_device pointer | |
250 | * @pos: offset of the buffer in vram | |
251 | * @buf: virtual address of the buffer in system memory | |
252 | * @size: read/write size, sizeof(@buf) must > @size | |
253 | * @write: true - write to vram, otherwise - read from vram | |
254 | */ | |
255 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
256 | uint32_t *buf, size_t size, bool write) | |
257 | { | |
e35e2b11 | 258 | unsigned long flags; |
ce05ac56 CK |
259 | uint32_t hi = ~0; |
260 | uint64_t last; | |
261 | ||
9d11eb0d CK |
262 | |
263 | #ifdef CONFIG_64BIT | |
264 | last = min(pos + size, adev->gmc.visible_vram_size); | |
265 | if (last > pos) { | |
266 | void __iomem *addr = adev->mman.aper_base_kaddr + pos; | |
267 | size_t count = last - pos; | |
268 | ||
269 | if (write) { | |
270 | memcpy_toio(addr, buf, count); | |
271 | mb(); | |
272 | amdgpu_asic_flush_hdp(adev, NULL); | |
273 | } else { | |
274 | amdgpu_asic_invalidate_hdp(adev, NULL); | |
275 | mb(); | |
276 | memcpy_fromio(buf, addr, count); | |
277 | } | |
278 | ||
279 | if (count == size) | |
280 | return; | |
281 | ||
282 | pos += count; | |
283 | buf += count / 4; | |
284 | size -= count; | |
285 | } | |
286 | #endif | |
287 | ||
ce05ac56 CK |
288 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); |
289 | for (last = pos + size; pos < last; pos += 4) { | |
290 | uint32_t tmp = pos >> 31; | |
e35e2b11 | 291 | |
e35e2b11 | 292 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); |
ce05ac56 CK |
293 | if (tmp != hi) { |
294 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
295 | hi = tmp; | |
296 | } | |
e35e2b11 TY |
297 | if (write) |
298 | WREG32_NO_KIQ(mmMM_DATA, *buf++); | |
299 | else | |
300 | *buf++ = RREG32_NO_KIQ(mmMM_DATA); | |
e35e2b11 | 301 | } |
ce05ac56 | 302 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); |
e35e2b11 TY |
303 | } |
304 | ||
d38ceaf9 | 305 | /* |
e78b579d | 306 | * MMIO register access helper functions. |
d38ceaf9 | 307 | */ |
e3ecdffa | 308 | /** |
e78b579d | 309 | * amdgpu_mm_rreg - read a memory mapped IO register |
e3ecdffa AD |
310 | * |
311 | * @adev: amdgpu_device pointer | |
312 | * @reg: dword aligned register offset | |
313 | * @acc_flags: access flags which require special behavior | |
314 | * | |
315 | * Returns the 32 bit value from the offset specified. | |
316 | */ | |
e78b579d HZ |
317 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
318 | uint32_t acc_flags) | |
d38ceaf9 | 319 | { |
f4b373f4 TSD |
320 | uint32_t ret; |
321 | ||
f384ff95 | 322 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
d33a99c4 | 323 | return amdgpu_kiq_rreg(adev, reg); |
bc992ba5 | 324 | |
ec59847e | 325 | if ((reg * 4) < adev->rmmio_size) |
f4b373f4 | 326 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
e78b579d HZ |
327 | else { |
328 | unsigned long flags; | |
329 | ||
330 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
331 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
332 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
333 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
334 | } | |
335 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); | |
f4b373f4 | 336 | return ret; |
d38ceaf9 AD |
337 | } |
338 | ||
421a2a30 ML |
339 | /* |
340 | * MMIO register read with bytes helper functions | |
341 | * @offset:bytes offset from MMIO start | |
342 | * | |
343 | */ | |
344 | ||
e3ecdffa AD |
345 | /** |
346 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
347 | * | |
348 | * @adev: amdgpu_device pointer | |
349 | * @offset: byte aligned register offset | |
350 | * | |
351 | * Returns the 8 bit value from the offset specified. | |
352 | */ | |
421a2a30 ML |
353 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
354 | if (offset < adev->rmmio_size) | |
355 | return (readb(adev->rmmio + offset)); | |
356 | BUG(); | |
357 | } | |
358 | ||
359 | /* | |
360 | * MMIO register write with bytes helper functions | |
361 | * @offset:bytes offset from MMIO start | |
362 | * @value: the value want to be written to the register | |
363 | * | |
364 | */ | |
e3ecdffa AD |
365 | /** |
366 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
367 | * | |
368 | * @adev: amdgpu_device pointer | |
369 | * @offset: byte aligned register offset | |
370 | * @value: 8 bit value to write | |
371 | * | |
372 | * Writes the value specified to the offset specified. | |
373 | */ | |
421a2a30 ML |
374 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
375 | if (offset < adev->rmmio_size) | |
376 | writeb(value, adev->rmmio + offset); | |
377 | else | |
378 | BUG(); | |
379 | } | |
380 | ||
e230ac11 ND |
381 | static inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, |
382 | uint32_t reg, uint32_t v, | |
383 | uint32_t acc_flags) | |
2e0cc4d4 | 384 | { |
e78b579d | 385 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 386 | |
ec59847e | 387 | if ((reg * 4) < adev->rmmio_size) |
2e0cc4d4 | 388 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
e78b579d HZ |
389 | else { |
390 | unsigned long flags; | |
391 | ||
392 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
393 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
394 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
395 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
396 | } | |
2e0cc4d4 ML |
397 | } |
398 | ||
e3ecdffa | 399 | /** |
e78b579d | 400 | * amdgpu_mm_wreg - write to a memory mapped IO register |
e3ecdffa AD |
401 | * |
402 | * @adev: amdgpu_device pointer | |
403 | * @reg: dword aligned register offset | |
404 | * @v: 32 bit value to write to the register | |
405 | * @acc_flags: access flags which require special behavior | |
406 | * | |
407 | * Writes the value specified to the offset specified. | |
408 | */ | |
e78b579d HZ |
409 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
410 | uint32_t acc_flags) | |
d38ceaf9 | 411 | { |
f384ff95 | 412 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
d33a99c4 | 413 | return amdgpu_kiq_wreg(adev, reg, v); |
bc992ba5 | 414 | |
e78b579d | 415 | amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags); |
2e0cc4d4 | 416 | } |
d38ceaf9 | 417 | |
2e0cc4d4 ML |
418 | /* |
419 | * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range | |
420 | * | |
421 | * this function is invoked only the debugfs register access | |
422 | * */ | |
423 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
424 | uint32_t acc_flags) | |
425 | { | |
426 | if (amdgpu_sriov_fullaccess(adev) && | |
427 | adev->gfx.rlc.funcs && | |
428 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
47ed4e1c | 429 | |
2e0cc4d4 ML |
430 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
431 | return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v); | |
47ed4e1c | 432 | } |
2e0cc4d4 | 433 | |
e78b579d | 434 | amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags); |
d38ceaf9 AD |
435 | } |
436 | ||
e3ecdffa AD |
437 | /** |
438 | * amdgpu_io_rreg - read an IO register | |
439 | * | |
440 | * @adev: amdgpu_device pointer | |
441 | * @reg: dword aligned register offset | |
442 | * | |
443 | * Returns the 32 bit value from the offset specified. | |
444 | */ | |
d38ceaf9 AD |
445 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
446 | { | |
447 | if ((reg * 4) < adev->rio_mem_size) | |
448 | return ioread32(adev->rio_mem + (reg * 4)); | |
449 | else { | |
450 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
451 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
452 | } | |
453 | } | |
454 | ||
e3ecdffa AD |
455 | /** |
456 | * amdgpu_io_wreg - write to an IO register | |
457 | * | |
458 | * @adev: amdgpu_device pointer | |
459 | * @reg: dword aligned register offset | |
460 | * @v: 32 bit value to write to the register | |
461 | * | |
462 | * Writes the value specified to the offset specified. | |
463 | */ | |
d38ceaf9 AD |
464 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
465 | { | |
d38ceaf9 AD |
466 | if ((reg * 4) < adev->rio_mem_size) |
467 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
468 | else { | |
469 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
470 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
471 | } | |
472 | } | |
473 | ||
474 | /** | |
475 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
476 | * | |
477 | * @adev: amdgpu_device pointer | |
478 | * @index: doorbell index | |
479 | * | |
480 | * Returns the value in the doorbell aperture at the | |
481 | * requested doorbell index (CIK). | |
482 | */ | |
483 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
484 | { | |
485 | if (index < adev->doorbell.num_doorbells) { | |
486 | return readl(adev->doorbell.ptr + index); | |
487 | } else { | |
488 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
489 | return 0; | |
490 | } | |
491 | } | |
492 | ||
493 | /** | |
494 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
495 | * | |
496 | * @adev: amdgpu_device pointer | |
497 | * @index: doorbell index | |
498 | * @v: value to write | |
499 | * | |
500 | * Writes @v to the doorbell aperture at the | |
501 | * requested doorbell index (CIK). | |
502 | */ | |
503 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
504 | { | |
505 | if (index < adev->doorbell.num_doorbells) { | |
506 | writel(v, adev->doorbell.ptr + index); | |
507 | } else { | |
508 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
509 | } | |
510 | } | |
511 | ||
832be404 KW |
512 | /** |
513 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
514 | * | |
515 | * @adev: amdgpu_device pointer | |
516 | * @index: doorbell index | |
517 | * | |
518 | * Returns the value in the doorbell aperture at the | |
519 | * requested doorbell index (VEGA10+). | |
520 | */ | |
521 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
522 | { | |
523 | if (index < adev->doorbell.num_doorbells) { | |
524 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
525 | } else { | |
526 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
527 | return 0; | |
528 | } | |
529 | } | |
530 | ||
531 | /** | |
532 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
533 | * | |
534 | * @adev: amdgpu_device pointer | |
535 | * @index: doorbell index | |
536 | * @v: value to write | |
537 | * | |
538 | * Writes @v to the doorbell aperture at the | |
539 | * requested doorbell index (VEGA10+). | |
540 | */ | |
541 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
542 | { | |
543 | if (index < adev->doorbell.num_doorbells) { | |
544 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
545 | } else { | |
546 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
547 | } | |
548 | } | |
549 | ||
d38ceaf9 AD |
550 | /** |
551 | * amdgpu_invalid_rreg - dummy reg read function | |
552 | * | |
553 | * @adev: amdgpu device pointer | |
554 | * @reg: offset of register | |
555 | * | |
556 | * Dummy register read function. Used for register blocks | |
557 | * that certain asics don't have (all asics). | |
558 | * Returns the value in the register. | |
559 | */ | |
560 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
561 | { | |
562 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
563 | BUG(); | |
564 | return 0; | |
565 | } | |
566 | ||
567 | /** | |
568 | * amdgpu_invalid_wreg - dummy reg write function | |
569 | * | |
570 | * @adev: amdgpu device pointer | |
571 | * @reg: offset of register | |
572 | * @v: value to write to the register | |
573 | * | |
574 | * Dummy register read function. Used for register blocks | |
575 | * that certain asics don't have (all asics). | |
576 | */ | |
577 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
578 | { | |
579 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
580 | reg, v); | |
581 | BUG(); | |
582 | } | |
583 | ||
4fa1c6a6 TZ |
584 | /** |
585 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
586 | * | |
587 | * @adev: amdgpu device pointer | |
588 | * @reg: offset of register | |
589 | * | |
590 | * Dummy register read function. Used for register blocks | |
591 | * that certain asics don't have (all asics). | |
592 | * Returns the value in the register. | |
593 | */ | |
594 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
595 | { | |
596 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
597 | BUG(); | |
598 | return 0; | |
599 | } | |
600 | ||
601 | /** | |
602 | * amdgpu_invalid_wreg64 - dummy reg write function | |
603 | * | |
604 | * @adev: amdgpu device pointer | |
605 | * @reg: offset of register | |
606 | * @v: value to write to the register | |
607 | * | |
608 | * Dummy register read function. Used for register blocks | |
609 | * that certain asics don't have (all asics). | |
610 | */ | |
611 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
612 | { | |
613 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
614 | reg, v); | |
615 | BUG(); | |
616 | } | |
617 | ||
d38ceaf9 AD |
618 | /** |
619 | * amdgpu_block_invalid_rreg - dummy reg read function | |
620 | * | |
621 | * @adev: amdgpu device pointer | |
622 | * @block: offset of instance | |
623 | * @reg: offset of register | |
624 | * | |
625 | * Dummy register read function. Used for register blocks | |
626 | * that certain asics don't have (all asics). | |
627 | * Returns the value in the register. | |
628 | */ | |
629 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
630 | uint32_t block, uint32_t reg) | |
631 | { | |
632 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
633 | reg, block); | |
634 | BUG(); | |
635 | return 0; | |
636 | } | |
637 | ||
638 | /** | |
639 | * amdgpu_block_invalid_wreg - dummy reg write function | |
640 | * | |
641 | * @adev: amdgpu device pointer | |
642 | * @block: offset of instance | |
643 | * @reg: offset of register | |
644 | * @v: value to write to the register | |
645 | * | |
646 | * Dummy register read function. Used for register blocks | |
647 | * that certain asics don't have (all asics). | |
648 | */ | |
649 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
650 | uint32_t block, | |
651 | uint32_t reg, uint32_t v) | |
652 | { | |
653 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
654 | reg, block, v); | |
655 | BUG(); | |
656 | } | |
657 | ||
4d2997ab AD |
658 | /** |
659 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
660 | * | |
661 | * @dev: drm_device pointer | |
662 | * | |
663 | * Does any asic specific work and then calls atom asic init. | |
664 | */ | |
665 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
666 | { | |
667 | amdgpu_asic_pre_asic_init(adev); | |
668 | ||
669 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
670 | } | |
671 | ||
e3ecdffa AD |
672 | /** |
673 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
674 | * | |
675 | * @adev: amdgpu device pointer | |
676 | * | |
677 | * Allocates a scratch page of VRAM for use by various things in the | |
678 | * driver. | |
679 | */ | |
06ec9070 | 680 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 681 | { |
a4a02777 CK |
682 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
683 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
684 | &adev->vram_scratch.robj, | |
685 | &adev->vram_scratch.gpu_addr, | |
686 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
687 | } |
688 | ||
e3ecdffa AD |
689 | /** |
690 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
691 | * | |
692 | * @adev: amdgpu device pointer | |
693 | * | |
694 | * Frees the VRAM scratch page. | |
695 | */ | |
06ec9070 | 696 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 697 | { |
078af1a3 | 698 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
699 | } |
700 | ||
701 | /** | |
9c3f2b54 | 702 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
703 | * |
704 | * @adev: amdgpu_device pointer | |
705 | * @registers: pointer to the register array | |
706 | * @array_size: size of the register array | |
707 | * | |
708 | * Programs an array or registers with and and or masks. | |
709 | * This is a helper for setting golden registers. | |
710 | */ | |
9c3f2b54 AD |
711 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
712 | const u32 *registers, | |
713 | const u32 array_size) | |
d38ceaf9 AD |
714 | { |
715 | u32 tmp, reg, and_mask, or_mask; | |
716 | int i; | |
717 | ||
718 | if (array_size % 3) | |
719 | return; | |
720 | ||
721 | for (i = 0; i < array_size; i +=3) { | |
722 | reg = registers[i + 0]; | |
723 | and_mask = registers[i + 1]; | |
724 | or_mask = registers[i + 2]; | |
725 | ||
726 | if (and_mask == 0xffffffff) { | |
727 | tmp = or_mask; | |
728 | } else { | |
729 | tmp = RREG32(reg); | |
730 | tmp &= ~and_mask; | |
e0d07657 HZ |
731 | if (adev->family >= AMDGPU_FAMILY_AI) |
732 | tmp |= (or_mask & and_mask); | |
733 | else | |
734 | tmp |= or_mask; | |
d38ceaf9 AD |
735 | } |
736 | WREG32(reg, tmp); | |
737 | } | |
738 | } | |
739 | ||
e3ecdffa AD |
740 | /** |
741 | * amdgpu_device_pci_config_reset - reset the GPU | |
742 | * | |
743 | * @adev: amdgpu_device pointer | |
744 | * | |
745 | * Resets the GPU using the pci config reset sequence. | |
746 | * Only applicable to asics prior to vega10. | |
747 | */ | |
8111c387 | 748 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
749 | { |
750 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
751 | } | |
752 | ||
753 | /* | |
754 | * GPU doorbell aperture helpers function. | |
755 | */ | |
756 | /** | |
06ec9070 | 757 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
758 | * |
759 | * @adev: amdgpu_device pointer | |
760 | * | |
761 | * Init doorbell driver information (CIK) | |
762 | * Returns 0 on success, error on failure. | |
763 | */ | |
06ec9070 | 764 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 765 | { |
6585661d | 766 | |
705e519e CK |
767 | /* No doorbell on SI hardware generation */ |
768 | if (adev->asic_type < CHIP_BONAIRE) { | |
769 | adev->doorbell.base = 0; | |
770 | adev->doorbell.size = 0; | |
771 | adev->doorbell.num_doorbells = 0; | |
772 | adev->doorbell.ptr = NULL; | |
773 | return 0; | |
774 | } | |
775 | ||
d6895ad3 CK |
776 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
777 | return -EINVAL; | |
778 | ||
22357775 AD |
779 | amdgpu_asic_init_doorbell_index(adev); |
780 | ||
d38ceaf9 AD |
781 | /* doorbell bar mapping */ |
782 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
783 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
784 | ||
edf600da | 785 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 786 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
787 | if (adev->doorbell.num_doorbells == 0) |
788 | return -EINVAL; | |
789 | ||
ec3db8a6 | 790 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
791 | * paging queue doorbell use the second page. The |
792 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
793 | * doorbells are in the first page. So with paging queue enabled, | |
794 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
795 | */ |
796 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 797 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 798 | |
8972e5d2 CK |
799 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
800 | adev->doorbell.num_doorbells * | |
801 | sizeof(u32)); | |
802 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 803 | return -ENOMEM; |
d38ceaf9 AD |
804 | |
805 | return 0; | |
806 | } | |
807 | ||
808 | /** | |
06ec9070 | 809 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
810 | * |
811 | * @adev: amdgpu_device pointer | |
812 | * | |
813 | * Tear down doorbell driver information (CIK) | |
814 | */ | |
06ec9070 | 815 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
816 | { |
817 | iounmap(adev->doorbell.ptr); | |
818 | adev->doorbell.ptr = NULL; | |
819 | } | |
820 | ||
22cb0164 | 821 | |
d38ceaf9 AD |
822 | |
823 | /* | |
06ec9070 | 824 | * amdgpu_device_wb_*() |
455a7bc2 | 825 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 826 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
827 | */ |
828 | ||
829 | /** | |
06ec9070 | 830 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
831 | * |
832 | * @adev: amdgpu_device pointer | |
833 | * | |
834 | * Disables Writeback and frees the Writeback memory (all asics). | |
835 | * Used at driver shutdown. | |
836 | */ | |
06ec9070 | 837 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
838 | { |
839 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
840 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
841 | &adev->wb.gpu_addr, | |
842 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
843 | adev->wb.wb_obj = NULL; |
844 | } | |
845 | } | |
846 | ||
847 | /** | |
06ec9070 | 848 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
849 | * |
850 | * @adev: amdgpu_device pointer | |
851 | * | |
455a7bc2 | 852 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
853 | * Used at driver startup. |
854 | * Returns 0 on success or an -error on failure. | |
855 | */ | |
06ec9070 | 856 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
857 | { |
858 | int r; | |
859 | ||
860 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
861 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
862 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
863 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
864 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
865 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
866 | if (r) { |
867 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
868 | return r; | |
869 | } | |
d38ceaf9 AD |
870 | |
871 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
872 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
873 | ||
874 | /* clear wb memory */ | |
73469585 | 875 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
876 | } |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | /** | |
131b4b36 | 882 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
883 | * |
884 | * @adev: amdgpu_device pointer | |
885 | * @wb: wb index | |
886 | * | |
887 | * Allocate a wb slot for use by the driver (all asics). | |
888 | * Returns 0 on success or -EINVAL on failure. | |
889 | */ | |
131b4b36 | 890 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
891 | { |
892 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 893 | |
97407b63 | 894 | if (offset < adev->wb.num_wb) { |
7014285a | 895 | __set_bit(offset, adev->wb.used); |
63ae07ca | 896 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
897 | return 0; |
898 | } else { | |
899 | return -EINVAL; | |
900 | } | |
901 | } | |
902 | ||
d38ceaf9 | 903 | /** |
131b4b36 | 904 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
905 | * |
906 | * @adev: amdgpu_device pointer | |
907 | * @wb: wb index | |
908 | * | |
909 | * Free a wb slot allocated for use by the driver (all asics) | |
910 | */ | |
131b4b36 | 911 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 912 | { |
73469585 | 913 | wb >>= 3; |
d38ceaf9 | 914 | if (wb < adev->wb.num_wb) |
73469585 | 915 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
916 | } |
917 | ||
d6895ad3 CK |
918 | /** |
919 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
920 | * | |
921 | * @adev: amdgpu_device pointer | |
922 | * | |
923 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
924 | * to fail, but if any of the BARs is not accessible after the size we abort | |
925 | * driver loading by returning -ENODEV. | |
926 | */ | |
927 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
928 | { | |
770d13b1 | 929 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 930 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
931 | struct pci_bus *root; |
932 | struct resource *res; | |
933 | unsigned i; | |
d6895ad3 CK |
934 | u16 cmd; |
935 | int r; | |
936 | ||
0c03b912 | 937 | /* Bypass for VF */ |
938 | if (amdgpu_sriov_vf(adev)) | |
939 | return 0; | |
940 | ||
b7221f2b AD |
941 | /* skip if the bios has already enabled large BAR */ |
942 | if (adev->gmc.real_vram_size && | |
943 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
944 | return 0; | |
945 | ||
31b8adab CK |
946 | /* Check if the root BUS has 64bit memory resources */ |
947 | root = adev->pdev->bus; | |
948 | while (root->parent) | |
949 | root = root->parent; | |
950 | ||
951 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 952 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
953 | res->start > 0x100000000ull) |
954 | break; | |
955 | } | |
956 | ||
957 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
958 | if (!res) | |
959 | return 0; | |
960 | ||
d6895ad3 CK |
961 | /* Disable memory decoding while we change the BAR addresses and size */ |
962 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
963 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
964 | cmd & ~PCI_COMMAND_MEMORY); | |
965 | ||
966 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 967 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
968 | if (adev->asic_type >= CHIP_BONAIRE) |
969 | pci_release_resource(adev->pdev, 2); | |
970 | ||
971 | pci_release_resource(adev->pdev, 0); | |
972 | ||
973 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
974 | if (r == -ENOSPC) | |
975 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
976 | else if (r && r != -ENOTSUPP) | |
977 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
978 | ||
979 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
980 | ||
981 | /* When the doorbell or fb BAR isn't available we have no chance of | |
982 | * using the device. | |
983 | */ | |
06ec9070 | 984 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
985 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
986 | return -ENODEV; | |
987 | ||
988 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
989 | ||
990 | return 0; | |
991 | } | |
a05502e5 | 992 | |
d38ceaf9 AD |
993 | /* |
994 | * GPU helpers function. | |
995 | */ | |
996 | /** | |
39c640c0 | 997 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
998 | * |
999 | * @adev: amdgpu_device pointer | |
1000 | * | |
c836fec5 JQ |
1001 | * Check if the asic has been initialized (all asics) at driver startup |
1002 | * or post is needed if hw reset is performed. | |
1003 | * Returns true if need or false if not. | |
d38ceaf9 | 1004 | */ |
39c640c0 | 1005 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1006 | { |
1007 | uint32_t reg; | |
1008 | ||
bec86378 ML |
1009 | if (amdgpu_sriov_vf(adev)) |
1010 | return false; | |
1011 | ||
1012 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1013 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1014 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1015 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1016 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1017 | */ |
1018 | if (adev->asic_type == CHIP_FIJI) { | |
1019 | int err; | |
1020 | uint32_t fw_ver; | |
1021 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1022 | /* force vPost if error occured */ | |
1023 | if (err) | |
1024 | return true; | |
1025 | ||
1026 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1027 | if (fw_ver < 0x00160e00) |
1028 | return true; | |
bec86378 | 1029 | } |
bec86378 | 1030 | } |
91fe77eb | 1031 | |
1032 | if (adev->has_hw_reset) { | |
1033 | adev->has_hw_reset = false; | |
1034 | return true; | |
1035 | } | |
1036 | ||
1037 | /* bios scratch used on CIK+ */ | |
1038 | if (adev->asic_type >= CHIP_BONAIRE) | |
1039 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1040 | ||
1041 | /* check MEM_SIZE for older asics */ | |
1042 | reg = amdgpu_asic_get_config_memsize(adev); | |
1043 | ||
1044 | if ((reg != 0) && (reg != 0xffffffff)) | |
1045 | return false; | |
1046 | ||
1047 | return true; | |
bec86378 ML |
1048 | } |
1049 | ||
d38ceaf9 AD |
1050 | /* if we get transitioned to only one device, take VGA back */ |
1051 | /** | |
06ec9070 | 1052 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
1053 | * |
1054 | * @cookie: amdgpu_device pointer | |
1055 | * @state: enable/disable vga decode | |
1056 | * | |
1057 | * Enable/disable vga decode (all asics). | |
1058 | * Returns VGA resource flags. | |
1059 | */ | |
06ec9070 | 1060 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
1061 | { |
1062 | struct amdgpu_device *adev = cookie; | |
1063 | amdgpu_asic_set_vga_state(adev, state); | |
1064 | if (state) | |
1065 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1066 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1067 | else | |
1068 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1069 | } | |
1070 | ||
e3ecdffa AD |
1071 | /** |
1072 | * amdgpu_device_check_block_size - validate the vm block size | |
1073 | * | |
1074 | * @adev: amdgpu_device pointer | |
1075 | * | |
1076 | * Validates the vm block size specified via module parameter. | |
1077 | * The vm block size defines number of bits in page table versus page directory, | |
1078 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1079 | * page table and the remaining bits are in the page directory. | |
1080 | */ | |
06ec9070 | 1081 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1082 | { |
1083 | /* defines number of bits in page table versus page directory, | |
1084 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1085 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1086 | if (amdgpu_vm_block_size == -1) |
1087 | return; | |
a1adf8be | 1088 | |
bab4fee7 | 1089 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1090 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1091 | amdgpu_vm_block_size); | |
97489129 | 1092 | amdgpu_vm_block_size = -1; |
a1adf8be | 1093 | } |
a1adf8be CZ |
1094 | } |
1095 | ||
e3ecdffa AD |
1096 | /** |
1097 | * amdgpu_device_check_vm_size - validate the vm size | |
1098 | * | |
1099 | * @adev: amdgpu_device pointer | |
1100 | * | |
1101 | * Validates the vm size in GB specified via module parameter. | |
1102 | * The VM size is the size of the GPU virtual memory space in GB. | |
1103 | */ | |
06ec9070 | 1104 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1105 | { |
64dab074 AD |
1106 | /* no need to check the default value */ |
1107 | if (amdgpu_vm_size == -1) | |
1108 | return; | |
1109 | ||
83ca145d ZJ |
1110 | if (amdgpu_vm_size < 1) { |
1111 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1112 | amdgpu_vm_size); | |
f3368128 | 1113 | amdgpu_vm_size = -1; |
83ca145d | 1114 | } |
83ca145d ZJ |
1115 | } |
1116 | ||
7951e376 RZ |
1117 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1118 | { | |
1119 | struct sysinfo si; | |
a9d4fe2f | 1120 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1121 | uint64_t total_memory; |
1122 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1123 | uint64_t dram_size_three_GB = 0xB8000000; | |
1124 | ||
1125 | if (amdgpu_smu_memory_pool_size == 0) | |
1126 | return; | |
1127 | ||
1128 | if (!is_os_64) { | |
1129 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1130 | goto def_value; | |
1131 | } | |
1132 | si_meminfo(&si); | |
1133 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1134 | ||
1135 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1136 | (amdgpu_smu_memory_pool_size == 2)) { | |
1137 | if (total_memory < dram_size_three_GB) | |
1138 | goto def_value1; | |
1139 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1140 | (amdgpu_smu_memory_pool_size == 8)) { | |
1141 | if (total_memory < dram_size_seven_GB) | |
1142 | goto def_value1; | |
1143 | } else { | |
1144 | DRM_WARN("Smu memory pool size not supported\n"); | |
1145 | goto def_value; | |
1146 | } | |
1147 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1148 | ||
1149 | return; | |
1150 | ||
1151 | def_value1: | |
1152 | DRM_WARN("No enough system memory\n"); | |
1153 | def_value: | |
1154 | adev->pm.smu_prv_buffer_size = 0; | |
1155 | } | |
1156 | ||
d38ceaf9 | 1157 | /** |
06ec9070 | 1158 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1159 | * |
1160 | * @adev: amdgpu_device pointer | |
1161 | * | |
1162 | * Validates certain module parameters and updates | |
1163 | * the associated values used by the driver (all asics). | |
1164 | */ | |
912dfc84 | 1165 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1166 | { |
5b011235 CZ |
1167 | if (amdgpu_sched_jobs < 4) { |
1168 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1169 | amdgpu_sched_jobs); | |
1170 | amdgpu_sched_jobs = 4; | |
76117507 | 1171 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1172 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1173 | amdgpu_sched_jobs); | |
1174 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1175 | } | |
d38ceaf9 | 1176 | |
83e74db6 | 1177 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1178 | /* gart size must be greater or equal to 32M */ |
1179 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1180 | amdgpu_gart_size); | |
83e74db6 | 1181 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1182 | } |
1183 | ||
36d38372 | 1184 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1185 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1186 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1187 | amdgpu_gtt_size); | |
1188 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1189 | } |
1190 | ||
d07f14be RH |
1191 | /* valid range is between 4 and 9 inclusive */ |
1192 | if (amdgpu_vm_fragment_size != -1 && | |
1193 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1194 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1195 | amdgpu_vm_fragment_size = -1; | |
1196 | } | |
1197 | ||
5d5bd5e3 KW |
1198 | if (amdgpu_sched_hw_submission < 2) { |
1199 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1200 | amdgpu_sched_hw_submission); | |
1201 | amdgpu_sched_hw_submission = 2; | |
1202 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1203 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1204 | amdgpu_sched_hw_submission); | |
1205 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1206 | } | |
1207 | ||
7951e376 RZ |
1208 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1209 | ||
06ec9070 | 1210 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1211 | |
06ec9070 | 1212 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1213 | |
19aede77 | 1214 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1215 | |
c6252390 | 1216 | amdgpu_gmc_tmz_set(adev); |
01a8dcec | 1217 | |
a300de40 ML |
1218 | if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) { |
1219 | amdgpu_num_kcq = 8; | |
c16ce562 | 1220 | dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n"); |
a300de40 ML |
1221 | } |
1222 | ||
e3c00faa | 1223 | return 0; |
d38ceaf9 AD |
1224 | } |
1225 | ||
1226 | /** | |
1227 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1228 | * | |
1229 | * @pdev: pci dev pointer | |
1694467b | 1230 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1231 | * |
1232 | * Callback for the switcheroo driver. Suspends or resumes the | |
1233 | * the asics before or after it is powered up using ACPI methods. | |
1234 | */ | |
8aba21b7 LT |
1235 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1236 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1237 | { |
1238 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1239 | int r; |
d38ceaf9 | 1240 | |
31af062a | 1241 | if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1242 | return; |
1243 | ||
1244 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1245 | pr_info("switched on\n"); |
d38ceaf9 AD |
1246 | /* don't suspend or resume card normally */ |
1247 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1248 | ||
de185019 AD |
1249 | pci_set_power_state(dev->pdev, PCI_D0); |
1250 | pci_restore_state(dev->pdev); | |
1251 | r = pci_enable_device(dev->pdev); | |
1252 | if (r) | |
1253 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1254 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1255 | |
d38ceaf9 AD |
1256 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1257 | drm_kms_helper_poll_enable(dev); | |
1258 | } else { | |
dd4fa6c1 | 1259 | pr_info("switched off\n"); |
d38ceaf9 AD |
1260 | drm_kms_helper_poll_disable(dev); |
1261 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
de185019 AD |
1262 | amdgpu_device_suspend(dev, true); |
1263 | pci_save_state(dev->pdev); | |
1264 | /* Shut down the device */ | |
1265 | pci_disable_device(dev->pdev); | |
1266 | pci_set_power_state(dev->pdev, PCI_D3cold); | |
d38ceaf9 AD |
1267 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1268 | } | |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1273 | * | |
1274 | * @pdev: pci dev pointer | |
1275 | * | |
1276 | * Callback for the switcheroo driver. Check of the switcheroo | |
1277 | * state can be changed. | |
1278 | * Returns true if the state can be changed, false if not. | |
1279 | */ | |
1280 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1281 | { | |
1282 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1283 | ||
1284 | /* | |
1285 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1286 | * locking inversion with the driver load path. And the access here is | |
1287 | * completely racy anyway. So don't bother with locking for now. | |
1288 | */ | |
7e13ad89 | 1289 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1290 | } |
1291 | ||
1292 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1293 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1294 | .reprobe = NULL, | |
1295 | .can_switch = amdgpu_switcheroo_can_switch, | |
1296 | }; | |
1297 | ||
e3ecdffa AD |
1298 | /** |
1299 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1300 | * | |
87e3f136 | 1301 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1302 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1303 | * @state: clockgating state (gate or ungate) | |
1304 | * | |
1305 | * Sets the requested clockgating state for all instances of | |
1306 | * the hardware IP specified. | |
1307 | * Returns the error code from the last instance. | |
1308 | */ | |
43fa561f | 1309 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1310 | enum amd_ip_block_type block_type, |
1311 | enum amd_clockgating_state state) | |
d38ceaf9 | 1312 | { |
43fa561f | 1313 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1314 | int i, r = 0; |
1315 | ||
1316 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1317 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1318 | continue; |
c722865a RZ |
1319 | if (adev->ip_blocks[i].version->type != block_type) |
1320 | continue; | |
1321 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1322 | continue; | |
1323 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1324 | (void *)adev, state); | |
1325 | if (r) | |
1326 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1327 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1328 | } |
1329 | return r; | |
1330 | } | |
1331 | ||
e3ecdffa AD |
1332 | /** |
1333 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1334 | * | |
87e3f136 | 1335 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1336 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1337 | * @state: powergating state (gate or ungate) | |
1338 | * | |
1339 | * Sets the requested powergating state for all instances of | |
1340 | * the hardware IP specified. | |
1341 | * Returns the error code from the last instance. | |
1342 | */ | |
43fa561f | 1343 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1344 | enum amd_ip_block_type block_type, |
1345 | enum amd_powergating_state state) | |
d38ceaf9 | 1346 | { |
43fa561f | 1347 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1348 | int i, r = 0; |
1349 | ||
1350 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1351 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1352 | continue; |
c722865a RZ |
1353 | if (adev->ip_blocks[i].version->type != block_type) |
1354 | continue; | |
1355 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1356 | continue; | |
1357 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1358 | (void *)adev, state); | |
1359 | if (r) | |
1360 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1361 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1362 | } |
1363 | return r; | |
1364 | } | |
1365 | ||
e3ecdffa AD |
1366 | /** |
1367 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1368 | * | |
1369 | * @adev: amdgpu_device pointer | |
1370 | * @flags: clockgating feature flags | |
1371 | * | |
1372 | * Walks the list of IPs on the device and updates the clockgating | |
1373 | * flags for each IP. | |
1374 | * Updates @flags with the feature flags for each hardware IP where | |
1375 | * clockgating is enabled. | |
1376 | */ | |
2990a1fc AD |
1377 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1378 | u32 *flags) | |
6cb2d4e4 HR |
1379 | { |
1380 | int i; | |
1381 | ||
1382 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1383 | if (!adev->ip_blocks[i].status.valid) | |
1384 | continue; | |
1385 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1386 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1387 | } | |
1388 | } | |
1389 | ||
e3ecdffa AD |
1390 | /** |
1391 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1392 | * | |
1393 | * @adev: amdgpu_device pointer | |
1394 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1395 | * | |
1396 | * Waits for the request hardware IP to be idle. | |
1397 | * Returns 0 for success or a negative error code on failure. | |
1398 | */ | |
2990a1fc AD |
1399 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1400 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1401 | { |
1402 | int i, r; | |
1403 | ||
1404 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1405 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1406 | continue; |
a1255107 AD |
1407 | if (adev->ip_blocks[i].version->type == block_type) { |
1408 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1409 | if (r) |
1410 | return r; | |
1411 | break; | |
1412 | } | |
1413 | } | |
1414 | return 0; | |
1415 | ||
1416 | } | |
1417 | ||
e3ecdffa AD |
1418 | /** |
1419 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1420 | * | |
1421 | * @adev: amdgpu_device pointer | |
1422 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1423 | * | |
1424 | * Check if the hardware IP is idle or not. | |
1425 | * Returns true if it the IP is idle, false if not. | |
1426 | */ | |
2990a1fc AD |
1427 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1428 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1429 | { |
1430 | int i; | |
1431 | ||
1432 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1433 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1434 | continue; |
a1255107 AD |
1435 | if (adev->ip_blocks[i].version->type == block_type) |
1436 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1437 | } |
1438 | return true; | |
1439 | ||
1440 | } | |
1441 | ||
e3ecdffa AD |
1442 | /** |
1443 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1444 | * | |
1445 | * @adev: amdgpu_device pointer | |
87e3f136 | 1446 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1447 | * |
1448 | * Returns a pointer to the hardware IP block structure | |
1449 | * if it exists for the asic, otherwise NULL. | |
1450 | */ | |
2990a1fc AD |
1451 | struct amdgpu_ip_block * |
1452 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1453 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1454 | { |
1455 | int i; | |
1456 | ||
1457 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1458 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1459 | return &adev->ip_blocks[i]; |
1460 | ||
1461 | return NULL; | |
1462 | } | |
1463 | ||
1464 | /** | |
2990a1fc | 1465 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1466 | * |
1467 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1468 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1469 | * @major: major version |
1470 | * @minor: minor version | |
1471 | * | |
1472 | * return 0 if equal or greater | |
1473 | * return 1 if smaller or the ip_block doesn't exist | |
1474 | */ | |
2990a1fc AD |
1475 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1476 | enum amd_ip_block_type type, | |
1477 | u32 major, u32 minor) | |
d38ceaf9 | 1478 | { |
2990a1fc | 1479 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1480 | |
a1255107 AD |
1481 | if (ip_block && ((ip_block->version->major > major) || |
1482 | ((ip_block->version->major == major) && | |
1483 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1484 | return 0; |
1485 | ||
1486 | return 1; | |
1487 | } | |
1488 | ||
a1255107 | 1489 | /** |
2990a1fc | 1490 | * amdgpu_device_ip_block_add |
a1255107 AD |
1491 | * |
1492 | * @adev: amdgpu_device pointer | |
1493 | * @ip_block_version: pointer to the IP to add | |
1494 | * | |
1495 | * Adds the IP block driver information to the collection of IPs | |
1496 | * on the asic. | |
1497 | */ | |
2990a1fc AD |
1498 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1499 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1500 | { |
1501 | if (!ip_block_version) | |
1502 | return -EINVAL; | |
1503 | ||
e966a725 | 1504 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1505 | ip_block_version->funcs->name); |
1506 | ||
a1255107 AD |
1507 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
e3ecdffa AD |
1512 | /** |
1513 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1514 | * | |
1515 | * @adev: amdgpu_device pointer | |
1516 | * | |
1517 | * Enabled the virtual display feature if the user has enabled it via | |
1518 | * the module parameter virtual_display. This feature provides a virtual | |
1519 | * display hardware on headless boards or in virtualized environments. | |
1520 | * This function parses and validates the configuration string specified by | |
1521 | * the user and configues the virtual display configuration (number of | |
1522 | * virtual connectors, crtcs, etc.) specified. | |
1523 | */ | |
483ef985 | 1524 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1525 | { |
1526 | adev->enable_virtual_display = false; | |
1527 | ||
1528 | if (amdgpu_virtual_display) { | |
4a580877 | 1529 | struct drm_device *ddev = adev_to_drm(adev); |
9accf2fd | 1530 | const char *pci_address_name = pci_name(ddev->pdev); |
0f66356d | 1531 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1532 | |
1533 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1534 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1535 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1536 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1537 | if (!strcmp("all", pciaddname) |
1538 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1539 | long num_crtc; |
1540 | int res = -1; | |
1541 | ||
9accf2fd | 1542 | adev->enable_virtual_display = true; |
0f66356d ED |
1543 | |
1544 | if (pciaddname_tmp) | |
1545 | res = kstrtol(pciaddname_tmp, 10, | |
1546 | &num_crtc); | |
1547 | ||
1548 | if (!res) { | |
1549 | if (num_crtc < 1) | |
1550 | num_crtc = 1; | |
1551 | if (num_crtc > 6) | |
1552 | num_crtc = 6; | |
1553 | adev->mode_info.num_crtc = num_crtc; | |
1554 | } else { | |
1555 | adev->mode_info.num_crtc = 1; | |
1556 | } | |
9accf2fd ED |
1557 | break; |
1558 | } | |
1559 | } | |
1560 | ||
0f66356d ED |
1561 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1562 | amdgpu_virtual_display, pci_address_name, | |
1563 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1564 | |
1565 | kfree(pciaddstr); | |
1566 | } | |
1567 | } | |
1568 | ||
e3ecdffa AD |
1569 | /** |
1570 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1571 | * | |
1572 | * @adev: amdgpu_device pointer | |
1573 | * | |
1574 | * Parses the asic configuration parameters specified in the gpu info | |
1575 | * firmware and makes them availale to the driver for use in configuring | |
1576 | * the asic. | |
1577 | * Returns 0 on success, -EINVAL on failure. | |
1578 | */ | |
e2a75f88 AD |
1579 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1580 | { | |
e2a75f88 | 1581 | const char *chip_name; |
c0a43457 | 1582 | char fw_name[40]; |
e2a75f88 AD |
1583 | int err; |
1584 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1585 | ||
ab4fe3e1 HR |
1586 | adev->firmware.gpu_info_fw = NULL; |
1587 | ||
72de33f8 | 1588 | if (adev->mman.discovery_bin) { |
258620d0 | 1589 | amdgpu_discovery_get_gfx_info(adev); |
cc375d8c TY |
1590 | |
1591 | /* | |
1592 | * FIXME: The bounding box is still needed by Navi12, so | |
1593 | * temporarily read it from gpu_info firmware. Should be droped | |
1594 | * when DAL no longer needs it. | |
1595 | */ | |
1596 | if (adev->asic_type != CHIP_NAVI12) | |
1597 | return 0; | |
258620d0 AD |
1598 | } |
1599 | ||
e2a75f88 | 1600 | switch (adev->asic_type) { |
e2a75f88 AD |
1601 | #ifdef CONFIG_DRM_AMDGPU_SI |
1602 | case CHIP_VERDE: | |
1603 | case CHIP_TAHITI: | |
1604 | case CHIP_PITCAIRN: | |
1605 | case CHIP_OLAND: | |
1606 | case CHIP_HAINAN: | |
1607 | #endif | |
1608 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1609 | case CHIP_BONAIRE: | |
1610 | case CHIP_HAWAII: | |
1611 | case CHIP_KAVERI: | |
1612 | case CHIP_KABINI: | |
1613 | case CHIP_MULLINS: | |
1614 | #endif | |
da87c30b AD |
1615 | case CHIP_TOPAZ: |
1616 | case CHIP_TONGA: | |
1617 | case CHIP_FIJI: | |
1618 | case CHIP_POLARIS10: | |
1619 | case CHIP_POLARIS11: | |
1620 | case CHIP_POLARIS12: | |
1621 | case CHIP_VEGAM: | |
1622 | case CHIP_CARRIZO: | |
1623 | case CHIP_STONEY: | |
27c0bc71 | 1624 | case CHIP_VEGA20: |
e2a75f88 AD |
1625 | default: |
1626 | return 0; | |
1627 | case CHIP_VEGA10: | |
1628 | chip_name = "vega10"; | |
1629 | break; | |
3f76dced AD |
1630 | case CHIP_VEGA12: |
1631 | chip_name = "vega12"; | |
1632 | break; | |
2d2e5e7e | 1633 | case CHIP_RAVEN: |
54f78a76 | 1634 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1635 | chip_name = "raven2"; |
54f78a76 | 1636 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1637 | chip_name = "picasso"; |
54c4d17e FX |
1638 | else |
1639 | chip_name = "raven"; | |
2d2e5e7e | 1640 | break; |
65e60f6e LM |
1641 | case CHIP_ARCTURUS: |
1642 | chip_name = "arcturus"; | |
1643 | break; | |
b51a26a0 HR |
1644 | case CHIP_RENOIR: |
1645 | chip_name = "renoir"; | |
1646 | break; | |
23c6268e HR |
1647 | case CHIP_NAVI10: |
1648 | chip_name = "navi10"; | |
1649 | break; | |
ed42cfe1 XY |
1650 | case CHIP_NAVI14: |
1651 | chip_name = "navi14"; | |
1652 | break; | |
42b325e5 XY |
1653 | case CHIP_NAVI12: |
1654 | chip_name = "navi12"; | |
1655 | break; | |
c0a43457 LG |
1656 | case CHIP_SIENNA_CICHLID: |
1657 | chip_name = "sienna_cichlid"; | |
1658 | break; | |
120eb833 JC |
1659 | case CHIP_NAVY_FLOUNDER: |
1660 | chip_name = "navy_flounder"; | |
1661 | break; | |
e2a75f88 AD |
1662 | } |
1663 | ||
1664 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1665 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1666 | if (err) { |
1667 | dev_err(adev->dev, | |
1668 | "Failed to load gpu_info firmware \"%s\"\n", | |
1669 | fw_name); | |
1670 | goto out; | |
1671 | } | |
ab4fe3e1 | 1672 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1673 | if (err) { |
1674 | dev_err(adev->dev, | |
1675 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1676 | fw_name); | |
1677 | goto out; | |
1678 | } | |
1679 | ||
ab4fe3e1 | 1680 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1681 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1682 | ||
1683 | switch (hdr->version_major) { | |
1684 | case 1: | |
1685 | { | |
1686 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1687 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1688 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1689 | ||
cc375d8c TY |
1690 | /* |
1691 | * Should be droped when DAL no longer needs it. | |
1692 | */ | |
1693 | if (adev->asic_type == CHIP_NAVI12) | |
1694 | goto parse_soc_bounding_box; | |
1695 | ||
b5ab16bf AD |
1696 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1697 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1698 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1699 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1700 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1701 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1702 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1703 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1704 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1705 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1706 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1707 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1708 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1709 | adev->gfx.cu_info.max_waves_per_simd = |
1710 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1711 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1712 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1713 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 1714 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
1715 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
1716 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
1717 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1718 | adev->gfx.config.num_sc_per_sh = | |
1719 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
1720 | adev->gfx.config.num_packer_per_sc = | |
1721 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
1722 | } | |
ec51d3fa | 1723 | |
cc375d8c | 1724 | parse_soc_bounding_box: |
ec51d3fa XY |
1725 | /* |
1726 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 1727 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 1728 | */ |
48321c3d HW |
1729 | if (hdr->version_minor == 2) { |
1730 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
1731 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
1732 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1733 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
1734 | } | |
e2a75f88 AD |
1735 | break; |
1736 | } | |
1737 | default: | |
1738 | dev_err(adev->dev, | |
1739 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1740 | err = -EINVAL; | |
1741 | goto out; | |
1742 | } | |
1743 | out: | |
e2a75f88 AD |
1744 | return err; |
1745 | } | |
1746 | ||
e3ecdffa AD |
1747 | /** |
1748 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1749 | * | |
1750 | * @adev: amdgpu_device pointer | |
1751 | * | |
1752 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1753 | * up each asic are discovered each IP's early_init callback is run. This | |
1754 | * is the first stage in initializing the asic. | |
1755 | * Returns 0 on success, negative error code on failure. | |
1756 | */ | |
06ec9070 | 1757 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1758 | { |
aaa36a97 | 1759 | int i, r; |
d38ceaf9 | 1760 | |
483ef985 | 1761 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1762 | |
00a979f3 | 1763 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 1764 | r = amdgpu_virt_request_full_gpu(adev, true); |
e3a4d51c | 1765 | if (r) |
00a979f3 | 1766 | return r; |
00a979f3 WS |
1767 | } |
1768 | ||
d38ceaf9 | 1769 | switch (adev->asic_type) { |
33f34802 KW |
1770 | #ifdef CONFIG_DRM_AMDGPU_SI |
1771 | case CHIP_VERDE: | |
1772 | case CHIP_TAHITI: | |
1773 | case CHIP_PITCAIRN: | |
1774 | case CHIP_OLAND: | |
1775 | case CHIP_HAINAN: | |
295d0daf | 1776 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1777 | r = si_set_ip_blocks(adev); |
1778 | if (r) | |
1779 | return r; | |
1780 | break; | |
1781 | #endif | |
a2e73f56 AD |
1782 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1783 | case CHIP_BONAIRE: | |
1784 | case CHIP_HAWAII: | |
1785 | case CHIP_KAVERI: | |
1786 | case CHIP_KABINI: | |
1787 | case CHIP_MULLINS: | |
e1ad2d53 | 1788 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 1789 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
1790 | else |
1791 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
1792 | |
1793 | r = cik_set_ip_blocks(adev); | |
1794 | if (r) | |
1795 | return r; | |
1796 | break; | |
1797 | #endif | |
da87c30b AD |
1798 | case CHIP_TOPAZ: |
1799 | case CHIP_TONGA: | |
1800 | case CHIP_FIJI: | |
1801 | case CHIP_POLARIS10: | |
1802 | case CHIP_POLARIS11: | |
1803 | case CHIP_POLARIS12: | |
1804 | case CHIP_VEGAM: | |
1805 | case CHIP_CARRIZO: | |
1806 | case CHIP_STONEY: | |
1807 | if (adev->flags & AMD_IS_APU) | |
1808 | adev->family = AMDGPU_FAMILY_CZ; | |
1809 | else | |
1810 | adev->family = AMDGPU_FAMILY_VI; | |
1811 | ||
1812 | r = vi_set_ip_blocks(adev); | |
1813 | if (r) | |
1814 | return r; | |
1815 | break; | |
e48a3cd9 AD |
1816 | case CHIP_VEGA10: |
1817 | case CHIP_VEGA12: | |
e4bd8170 | 1818 | case CHIP_VEGA20: |
e48a3cd9 | 1819 | case CHIP_RAVEN: |
61cf44c1 | 1820 | case CHIP_ARCTURUS: |
b51a26a0 | 1821 | case CHIP_RENOIR: |
70534d1e | 1822 | if (adev->flags & AMD_IS_APU) |
2ca8a5d2 CZ |
1823 | adev->family = AMDGPU_FAMILY_RV; |
1824 | else | |
1825 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1826 | |
1827 | r = soc15_set_ip_blocks(adev); | |
1828 | if (r) | |
1829 | return r; | |
1830 | break; | |
0a5b8c7b | 1831 | case CHIP_NAVI10: |
7ecb5cd4 | 1832 | case CHIP_NAVI14: |
4808cf9c | 1833 | case CHIP_NAVI12: |
11e8aef5 | 1834 | case CHIP_SIENNA_CICHLID: |
41f446bf | 1835 | case CHIP_NAVY_FLOUNDER: |
0a5b8c7b HR |
1836 | adev->family = AMDGPU_FAMILY_NV; |
1837 | ||
1838 | r = nv_set_ip_blocks(adev); | |
1839 | if (r) | |
1840 | return r; | |
1841 | break; | |
d38ceaf9 AD |
1842 | default: |
1843 | /* FIXME: not supported yet */ | |
1844 | return -EINVAL; | |
1845 | } | |
1846 | ||
1884734a | 1847 | amdgpu_amdkfd_device_probe(adev); |
1848 | ||
3b94fb10 | 1849 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 1850 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 1851 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
00f54b97 | 1852 | |
d38ceaf9 AD |
1853 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1854 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1855 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1856 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1857 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1858 | } else { |
a1255107 AD |
1859 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1860 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1861 | if (r == -ENOENT) { |
a1255107 | 1862 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1863 | } else if (r) { |
a1255107 AD |
1864 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1865 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1866 | return r; |
2c1a2784 | 1867 | } else { |
a1255107 | 1868 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1869 | } |
974e6b64 | 1870 | } else { |
a1255107 | 1871 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1872 | } |
d38ceaf9 | 1873 | } |
21a249ca AD |
1874 | /* get the vbios after the asic_funcs are set up */ |
1875 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
1876 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1877 | if (r) | |
1878 | return r; | |
1879 | ||
21a249ca AD |
1880 | /* Read BIOS */ |
1881 | if (!amdgpu_get_bios(adev)) | |
1882 | return -EINVAL; | |
1883 | ||
1884 | r = amdgpu_atombios_init(adev); | |
1885 | if (r) { | |
1886 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
1887 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
1888 | return r; | |
1889 | } | |
1890 | } | |
d38ceaf9 AD |
1891 | } |
1892 | ||
395d1fb9 NH |
1893 | adev->cg_flags &= amdgpu_cg_mask; |
1894 | adev->pg_flags &= amdgpu_pg_mask; | |
1895 | ||
d38ceaf9 AD |
1896 | return 0; |
1897 | } | |
1898 | ||
0a4f2520 RZ |
1899 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
1900 | { | |
1901 | int i, r; | |
1902 | ||
1903 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1904 | if (!adev->ip_blocks[i].status.sw) | |
1905 | continue; | |
1906 | if (adev->ip_blocks[i].status.hw) | |
1907 | continue; | |
1908 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 1909 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
1910 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
1911 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1912 | if (r) { | |
1913 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1914 | adev->ip_blocks[i].version->funcs->name, r); | |
1915 | return r; | |
1916 | } | |
1917 | adev->ip_blocks[i].status.hw = true; | |
1918 | } | |
1919 | } | |
1920 | ||
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
1925 | { | |
1926 | int i, r; | |
1927 | ||
1928 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1929 | if (!adev->ip_blocks[i].status.sw) | |
1930 | continue; | |
1931 | if (adev->ip_blocks[i].status.hw) | |
1932 | continue; | |
1933 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1934 | if (r) { | |
1935 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1936 | adev->ip_blocks[i].version->funcs->name, r); | |
1937 | return r; | |
1938 | } | |
1939 | adev->ip_blocks[i].status.hw = true; | |
1940 | } | |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | ||
7a3e0bb2 RZ |
1945 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
1946 | { | |
1947 | int r = 0; | |
1948 | int i; | |
80f41f84 | 1949 | uint32_t smu_version; |
7a3e0bb2 RZ |
1950 | |
1951 | if (adev->asic_type >= CHIP_VEGA10) { | |
1952 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
1953 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
1954 | continue; | |
1955 | ||
1956 | /* no need to do the fw loading again if already done*/ | |
1957 | if (adev->ip_blocks[i].status.hw == true) | |
1958 | break; | |
1959 | ||
53b3f8f4 | 1960 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
1961 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
1962 | if (r) { | |
1963 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 1964 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
1965 | return r; |
1966 | } | |
1967 | } else { | |
1968 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1969 | if (r) { | |
1970 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1971 | adev->ip_blocks[i].version->funcs->name, r); | |
1972 | return r; | |
7a3e0bb2 | 1973 | } |
7a3e0bb2 | 1974 | } |
482f0e53 ML |
1975 | |
1976 | adev->ip_blocks[i].status.hw = true; | |
1977 | break; | |
7a3e0bb2 RZ |
1978 | } |
1979 | } | |
482f0e53 | 1980 | |
8973d9ec ED |
1981 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
1982 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 1983 | |
80f41f84 | 1984 | return r; |
7a3e0bb2 RZ |
1985 | } |
1986 | ||
e3ecdffa AD |
1987 | /** |
1988 | * amdgpu_device_ip_init - run init for hardware IPs | |
1989 | * | |
1990 | * @adev: amdgpu_device pointer | |
1991 | * | |
1992 | * Main initialization pass for hardware IPs. The list of all the hardware | |
1993 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
1994 | * are run. sw_init initializes the software state associated with each IP | |
1995 | * and hw_init initializes the hardware associated with each IP. | |
1996 | * Returns 0 on success, negative error code on failure. | |
1997 | */ | |
06ec9070 | 1998 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1999 | { |
2000 | int i, r; | |
2001 | ||
c030f2e4 | 2002 | r = amdgpu_ras_init(adev); |
2003 | if (r) | |
2004 | return r; | |
2005 | ||
d38ceaf9 | 2006 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2007 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2008 | continue; |
a1255107 | 2009 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2010 | if (r) { |
a1255107 AD |
2011 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2012 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2013 | goto init_failed; |
2c1a2784 | 2014 | } |
a1255107 | 2015 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2016 | |
d38ceaf9 | 2017 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2018 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 2019 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2020 | if (r) { |
2021 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2022 | goto init_failed; |
2c1a2784 | 2023 | } |
a1255107 | 2024 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2025 | if (r) { |
2026 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2027 | goto init_failed; |
2c1a2784 | 2028 | } |
06ec9070 | 2029 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2030 | if (r) { |
06ec9070 | 2031 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2032 | goto init_failed; |
2c1a2784 | 2033 | } |
a1255107 | 2034 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2035 | |
2036 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2037 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2038 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2039 | AMDGPU_GEM_DOMAIN_VRAM, | |
2040 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2041 | if (r) { |
2042 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2043 | goto init_failed; |
2493664f ML |
2044 | } |
2045 | } | |
d38ceaf9 AD |
2046 | } |
2047 | } | |
2048 | ||
c9ffa427 YT |
2049 | if (amdgpu_sriov_vf(adev)) |
2050 | amdgpu_virt_init_data_exchange(adev); | |
2051 | ||
533aed27 AG |
2052 | r = amdgpu_ib_pool_init(adev); |
2053 | if (r) { | |
2054 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2055 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2056 | goto init_failed; | |
2057 | } | |
2058 | ||
c8963ea4 RZ |
2059 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2060 | if (r) | |
72d3f592 | 2061 | goto init_failed; |
0a4f2520 RZ |
2062 | |
2063 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2064 | if (r) | |
72d3f592 | 2065 | goto init_failed; |
0a4f2520 | 2066 | |
7a3e0bb2 RZ |
2067 | r = amdgpu_device_fw_loading(adev); |
2068 | if (r) | |
72d3f592 | 2069 | goto init_failed; |
7a3e0bb2 | 2070 | |
0a4f2520 RZ |
2071 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2072 | if (r) | |
72d3f592 | 2073 | goto init_failed; |
d38ceaf9 | 2074 | |
121a2bc6 AG |
2075 | /* |
2076 | * retired pages will be loaded from eeprom and reserved here, | |
2077 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2078 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2079 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2080 | * |
2081 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2082 | * failure from bad gpu situation and stop amdgpu init process | |
2083 | * accordingly. For other failed cases, it will still release all | |
2084 | * the resource and print error message, rather than returning one | |
2085 | * negative value to upper level. | |
121a2bc6 AG |
2086 | * |
2087 | * Note: theoretically, this should be called before all vram allocations | |
2088 | * to protect retired page from abusing | |
2089 | */ | |
b82e65a9 GC |
2090 | r = amdgpu_ras_recovery_init(adev); |
2091 | if (r) | |
2092 | goto init_failed; | |
121a2bc6 | 2093 | |
3e2e2ab5 HZ |
2094 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2095 | amdgpu_xgmi_add_device(adev); | |
1884734a | 2096 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 2097 | |
bd607166 KR |
2098 | amdgpu_fru_get_product_info(adev); |
2099 | ||
72d3f592 | 2100 | init_failed: |
c9ffa427 | 2101 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2102 | amdgpu_virt_release_full_gpu(adev, true); |
2103 | ||
72d3f592 | 2104 | return r; |
d38ceaf9 AD |
2105 | } |
2106 | ||
e3ecdffa AD |
2107 | /** |
2108 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2109 | * | |
2110 | * @adev: amdgpu_device pointer | |
2111 | * | |
2112 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2113 | * this function before a GPU reset. If the value is retained after a | |
2114 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2115 | */ | |
06ec9070 | 2116 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2117 | { |
2118 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2119 | } | |
2120 | ||
e3ecdffa AD |
2121 | /** |
2122 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2123 | * | |
2124 | * @adev: amdgpu_device pointer | |
2125 | * | |
2126 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2127 | * The driver calls this after a GPU reset to see if the contents of | |
2128 | * VRAM is lost or now. | |
2129 | * returns true if vram is lost, false if not. | |
2130 | */ | |
06ec9070 | 2131 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2132 | { |
dadce777 EQ |
2133 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2134 | AMDGPU_RESET_MAGIC_NUM)) | |
2135 | return true; | |
2136 | ||
53b3f8f4 | 2137 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2138 | return false; |
2139 | ||
2140 | /* | |
2141 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2142 | * always assumed to be lost. | |
2143 | */ | |
2144 | switch (amdgpu_asic_reset_method(adev)) { | |
2145 | case AMD_RESET_METHOD_BACO: | |
2146 | case AMD_RESET_METHOD_MODE1: | |
2147 | return true; | |
2148 | default: | |
2149 | return false; | |
2150 | } | |
0c49e0b8 CZ |
2151 | } |
2152 | ||
e3ecdffa | 2153 | /** |
1112a46b | 2154 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2155 | * |
2156 | * @adev: amdgpu_device pointer | |
b8b72130 | 2157 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2158 | * |
e3ecdffa | 2159 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2160 | * set_clockgating_state callbacks are run. |
2161 | * Late initialization pass enabling clockgating for hardware IPs. | |
2162 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2163 | * Returns 0 on success, negative error code on failure. |
2164 | */ | |
fdd34271 | 2165 | |
1112a46b RZ |
2166 | static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2167 | enum amd_clockgating_state state) | |
d38ceaf9 | 2168 | { |
1112a46b | 2169 | int i, j, r; |
d38ceaf9 | 2170 | |
4a2ba394 SL |
2171 | if (amdgpu_emu_mode == 1) |
2172 | return 0; | |
2173 | ||
1112a46b RZ |
2174 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2175 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2176 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2177 | continue; |
4a446d55 | 2178 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2179 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2180 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2181 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2182 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2183 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2184 | /* enable clockgating to save power */ |
a1255107 | 2185 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2186 | state); |
4a446d55 AD |
2187 | if (r) { |
2188 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2189 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2190 | return r; |
2191 | } | |
b0b00ff1 | 2192 | } |
d38ceaf9 | 2193 | } |
06b18f61 | 2194 | |
c9f96fd5 RZ |
2195 | return 0; |
2196 | } | |
2197 | ||
1112a46b | 2198 | static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state) |
c9f96fd5 | 2199 | { |
1112a46b | 2200 | int i, j, r; |
06b18f61 | 2201 | |
c9f96fd5 RZ |
2202 | if (amdgpu_emu_mode == 1) |
2203 | return 0; | |
2204 | ||
1112a46b RZ |
2205 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2206 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2207 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 RZ |
2208 | continue; |
2209 | /* skip CG for VCE/UVD, it's handled specially */ | |
2210 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2211 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2212 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2213 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2214 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2215 | /* enable powergating to save power */ | |
2216 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2217 | state); |
c9f96fd5 RZ |
2218 | if (r) { |
2219 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2220 | adev->ip_blocks[i].version->funcs->name, r); | |
2221 | return r; | |
2222 | } | |
2223 | } | |
2224 | } | |
2dc80b00 S |
2225 | return 0; |
2226 | } | |
2227 | ||
beff74bc AD |
2228 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2229 | { | |
2230 | struct amdgpu_gpu_instance *gpu_ins; | |
2231 | struct amdgpu_device *adev; | |
2232 | int i, ret = 0; | |
2233 | ||
2234 | mutex_lock(&mgpu_info.mutex); | |
2235 | ||
2236 | /* | |
2237 | * MGPU fan boost feature should be enabled | |
2238 | * only when there are two or more dGPUs in | |
2239 | * the system | |
2240 | */ | |
2241 | if (mgpu_info.num_dgpu < 2) | |
2242 | goto out; | |
2243 | ||
2244 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2245 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2246 | adev = gpu_ins->adev; | |
2247 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2248 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2249 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2250 | if (ret) | |
2251 | break; | |
2252 | ||
2253 | gpu_ins->mgpu_fan_enabled = 1; | |
2254 | } | |
2255 | } | |
2256 | ||
2257 | out: | |
2258 | mutex_unlock(&mgpu_info.mutex); | |
2259 | ||
2260 | return ret; | |
2261 | } | |
2262 | ||
e3ecdffa AD |
2263 | /** |
2264 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2265 | * | |
2266 | * @adev: amdgpu_device pointer | |
2267 | * | |
2268 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2269 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2270 | * late_init covers any special initialization that an IP requires | |
2271 | * after all of the have been initialized or something that needs to happen | |
2272 | * late in the init process. | |
2273 | * Returns 0 on success, negative error code on failure. | |
2274 | */ | |
06ec9070 | 2275 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2276 | { |
60599a03 | 2277 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2278 | int i = 0, r; |
2279 | ||
2280 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2281 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2282 | continue; |
2283 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2284 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2285 | if (r) { | |
2286 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2287 | adev->ip_blocks[i].version->funcs->name, r); | |
2288 | return r; | |
2289 | } | |
2dc80b00 | 2290 | } |
73f847db | 2291 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2292 | } |
2293 | ||
a891d239 DL |
2294 | amdgpu_ras_set_error_query_ready(adev, true); |
2295 | ||
1112a46b RZ |
2296 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2297 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2298 | |
06ec9070 | 2299 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2300 | |
beff74bc AD |
2301 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2302 | if (r) | |
2303 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2304 | ||
60599a03 EQ |
2305 | |
2306 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2307 | mutex_lock(&mgpu_info.mutex); | |
2308 | ||
2309 | /* | |
2310 | * Reset device p-state to low as this was booted with high. | |
2311 | * | |
2312 | * This should be performed only after all devices from the same | |
2313 | * hive get initialized. | |
2314 | * | |
2315 | * However, it's unknown how many device in the hive in advance. | |
2316 | * As this is counted one by one during devices initializations. | |
2317 | * | |
2318 | * So, we wait for all XGMI interlinked devices initialized. | |
2319 | * This may bring some delays as those devices may come from | |
2320 | * different hives. But that should be OK. | |
2321 | */ | |
2322 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2323 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2324 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2325 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2326 | continue; | |
2327 | ||
d84a430d JK |
2328 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2329 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2330 | if (r) { |
2331 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2332 | break; | |
2333 | } | |
2334 | } | |
2335 | } | |
2336 | ||
2337 | mutex_unlock(&mgpu_info.mutex); | |
2338 | } | |
2339 | ||
d38ceaf9 AD |
2340 | return 0; |
2341 | } | |
2342 | ||
e3ecdffa AD |
2343 | /** |
2344 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2345 | * | |
2346 | * @adev: amdgpu_device pointer | |
2347 | * | |
2348 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2349 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2350 | * are run. hw_fini tears down the hardware associated with each IP | |
2351 | * and sw_fini tears down any software state associated with each IP. | |
2352 | * Returns 0 on success, negative error code on failure. | |
2353 | */ | |
06ec9070 | 2354 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
2355 | { |
2356 | int i, r; | |
2357 | ||
5278a159 SY |
2358 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) |
2359 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2360 | ||
c030f2e4 | 2361 | amdgpu_ras_pre_fini(adev); |
2362 | ||
a82400b5 AG |
2363 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2364 | amdgpu_xgmi_remove_device(adev); | |
2365 | ||
1884734a | 2366 | amdgpu_amdkfd_device_fini(adev); |
05df1f01 RZ |
2367 | |
2368 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); | |
fdd34271 RZ |
2369 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2370 | ||
3e96dbfd AD |
2371 | /* need to disable SMC first */ |
2372 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2373 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 2374 | continue; |
fdd34271 | 2375 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 2376 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
2377 | /* XXX handle errors */ |
2378 | if (r) { | |
2379 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 2380 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 2381 | } |
a1255107 | 2382 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
2383 | break; |
2384 | } | |
2385 | } | |
2386 | ||
d38ceaf9 | 2387 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2388 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2389 | continue; |
8201a67a | 2390 | |
a1255107 | 2391 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2392 | /* XXX handle errors */ |
2c1a2784 | 2393 | if (r) { |
a1255107 AD |
2394 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2395 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2396 | } |
8201a67a | 2397 | |
a1255107 | 2398 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2399 | } |
2400 | ||
9950cda2 | 2401 | |
d38ceaf9 | 2402 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2403 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2404 | continue; |
c12aba3a ML |
2405 | |
2406 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2407 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2408 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2409 | amdgpu_device_wb_fini(adev); |
2410 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2411 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2412 | } |
2413 | ||
a1255107 | 2414 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2415 | /* XXX handle errors */ |
2c1a2784 | 2416 | if (r) { |
a1255107 AD |
2417 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2418 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2419 | } |
a1255107 AD |
2420 | adev->ip_blocks[i].status.sw = false; |
2421 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2422 | } |
2423 | ||
a6dcfd9c | 2424 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2425 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2426 | continue; |
a1255107 AD |
2427 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2428 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2429 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2430 | } |
2431 | ||
c030f2e4 | 2432 | amdgpu_ras_fini(adev); |
2433 | ||
030308fc | 2434 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
2435 | if (amdgpu_virt_release_full_gpu(adev, false)) |
2436 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 2437 | |
d38ceaf9 AD |
2438 | return 0; |
2439 | } | |
2440 | ||
e3ecdffa | 2441 | /** |
beff74bc | 2442 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2443 | * |
1112a46b | 2444 | * @work: work_struct. |
e3ecdffa | 2445 | */ |
beff74bc | 2446 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2447 | { |
2448 | struct amdgpu_device *adev = | |
beff74bc | 2449 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2450 | int r; |
2451 | ||
2452 | r = amdgpu_ib_ring_tests(adev); | |
2453 | if (r) | |
2454 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2455 | } |
2456 | ||
1e317b99 RZ |
2457 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2458 | { | |
2459 | struct amdgpu_device *adev = | |
2460 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2461 | ||
2462 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
2463 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
2464 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2465 | adev->gfx.gfx_off_state = true; | |
2466 | } | |
2467 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
2468 | } | |
2469 | ||
e3ecdffa | 2470 | /** |
e7854a03 | 2471 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2472 | * |
2473 | * @adev: amdgpu_device pointer | |
2474 | * | |
2475 | * Main suspend function for hardware IPs. The list of all the hardware | |
2476 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2477 | * suspend callbacks are run. suspend puts the hardware and software state | |
2478 | * in each IP into a state suitable for suspend. | |
2479 | * Returns 0 on success, negative error code on failure. | |
2480 | */ | |
e7854a03 AD |
2481 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2482 | { | |
2483 | int i, r; | |
2484 | ||
ced1ba97 PL |
2485 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2486 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2487 | |
e7854a03 AD |
2488 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2489 | if (!adev->ip_blocks[i].status.valid) | |
2490 | continue; | |
2b9f7848 | 2491 | |
e7854a03 | 2492 | /* displays are handled separately */ |
2b9f7848 ND |
2493 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2494 | continue; | |
2495 | ||
2496 | /* XXX handle errors */ | |
2497 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2498 | /* XXX handle errors */ | |
2499 | if (r) { | |
2500 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2501 | adev->ip_blocks[i].version->funcs->name, r); | |
2502 | return r; | |
e7854a03 | 2503 | } |
2b9f7848 ND |
2504 | |
2505 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2506 | } |
2507 | ||
e7854a03 AD |
2508 | return 0; |
2509 | } | |
2510 | ||
2511 | /** | |
2512 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2513 | * | |
2514 | * @adev: amdgpu_device pointer | |
2515 | * | |
2516 | * Main suspend function for hardware IPs. The list of all the hardware | |
2517 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2518 | * suspend callbacks are run. suspend puts the hardware and software state | |
2519 | * in each IP into a state suitable for suspend. | |
2520 | * Returns 0 on success, negative error code on failure. | |
2521 | */ | |
2522 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2523 | { |
2524 | int i, r; | |
2525 | ||
2526 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 2527 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2528 | continue; |
e7854a03 AD |
2529 | /* displays are handled in phase1 */ |
2530 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2531 | continue; | |
bff77e86 LM |
2532 | /* PSP lost connection when err_event_athub occurs */ |
2533 | if (amdgpu_ras_intr_triggered() && | |
2534 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2535 | adev->ip_blocks[i].status.hw = false; | |
2536 | continue; | |
2537 | } | |
d38ceaf9 | 2538 | /* XXX handle errors */ |
a1255107 | 2539 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2540 | /* XXX handle errors */ |
2c1a2784 | 2541 | if (r) { |
a1255107 AD |
2542 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2543 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2544 | } |
876923fb | 2545 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 2546 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
2547 | if(!amdgpu_sriov_vf(adev)){ |
2548 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2549 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
2550 | if (r) { | |
2551 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2552 | adev->mp1_state, r); | |
2553 | return r; | |
2554 | } | |
a3a09142 AD |
2555 | } |
2556 | } | |
b5507c7e | 2557 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2558 | } |
2559 | ||
2560 | return 0; | |
2561 | } | |
2562 | ||
e7854a03 AD |
2563 | /** |
2564 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2565 | * | |
2566 | * @adev: amdgpu_device pointer | |
2567 | * | |
2568 | * Main suspend function for hardware IPs. The list of all the hardware | |
2569 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2570 | * suspend callbacks are run. suspend puts the hardware and software state | |
2571 | * in each IP into a state suitable for suspend. | |
2572 | * Returns 0 on success, negative error code on failure. | |
2573 | */ | |
2574 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2575 | { | |
2576 | int r; | |
2577 | ||
e7819644 YT |
2578 | if (amdgpu_sriov_vf(adev)) |
2579 | amdgpu_virt_request_full_gpu(adev, false); | |
2580 | ||
e7854a03 AD |
2581 | r = amdgpu_device_ip_suspend_phase1(adev); |
2582 | if (r) | |
2583 | return r; | |
2584 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2585 | ||
e7819644 YT |
2586 | if (amdgpu_sriov_vf(adev)) |
2587 | amdgpu_virt_release_full_gpu(adev, false); | |
2588 | ||
e7854a03 AD |
2589 | return r; |
2590 | } | |
2591 | ||
06ec9070 | 2592 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2593 | { |
2594 | int i, r; | |
2595 | ||
2cb681b6 ML |
2596 | static enum amd_ip_block_type ip_order[] = { |
2597 | AMD_IP_BLOCK_TYPE_GMC, | |
2598 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2599 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2600 | AMD_IP_BLOCK_TYPE_IH, |
2601 | }; | |
a90ad3c2 | 2602 | |
4cd2a96d | 2603 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2cb681b6 ML |
2604 | int j; |
2605 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2606 | |
4cd2a96d J |
2607 | block = &adev->ip_blocks[i]; |
2608 | block->status.hw = false; | |
2609 | ||
2610 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { | |
2cb681b6 | 2611 | |
4cd2a96d | 2612 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
2613 | !block->status.valid) |
2614 | continue; | |
2615 | ||
2616 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2617 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2618 | if (r) |
2619 | return r; | |
482f0e53 | 2620 | block->status.hw = true; |
a90ad3c2 ML |
2621 | } |
2622 | } | |
2623 | ||
2624 | return 0; | |
2625 | } | |
2626 | ||
06ec9070 | 2627 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2628 | { |
2629 | int i, r; | |
2630 | ||
2cb681b6 ML |
2631 | static enum amd_ip_block_type ip_order[] = { |
2632 | AMD_IP_BLOCK_TYPE_SMC, | |
2633 | AMD_IP_BLOCK_TYPE_DCE, | |
2634 | AMD_IP_BLOCK_TYPE_GFX, | |
2635 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 2636 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
2637 | AMD_IP_BLOCK_TYPE_VCE, |
2638 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 2639 | }; |
a90ad3c2 | 2640 | |
2cb681b6 ML |
2641 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2642 | int j; | |
2643 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2644 | |
2cb681b6 ML |
2645 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2646 | block = &adev->ip_blocks[j]; | |
2647 | ||
2648 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
2649 | !block->status.valid || |
2650 | block->status.hw) | |
2cb681b6 ML |
2651 | continue; |
2652 | ||
895bd048 JZ |
2653 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
2654 | r = block->version->funcs->resume(adev); | |
2655 | else | |
2656 | r = block->version->funcs->hw_init(adev); | |
2657 | ||
0aaeefcc | 2658 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2659 | if (r) |
2660 | return r; | |
482f0e53 | 2661 | block->status.hw = true; |
a90ad3c2 ML |
2662 | } |
2663 | } | |
2664 | ||
2665 | return 0; | |
2666 | } | |
2667 | ||
e3ecdffa AD |
2668 | /** |
2669 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2670 | * | |
2671 | * @adev: amdgpu_device pointer | |
2672 | * | |
2673 | * First resume function for hardware IPs. The list of all the hardware | |
2674 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2675 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2676 | * after a suspend and updates the software state as necessary. This | |
2677 | * function is also used for restoring the GPU after a GPU reset. | |
2678 | * Returns 0 on success, negative error code on failure. | |
2679 | */ | |
06ec9070 | 2680 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2681 | { |
2682 | int i, r; | |
2683 | ||
a90ad3c2 | 2684 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 2685 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 2686 | continue; |
a90ad3c2 | 2687 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2688 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2689 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 2690 | |
fcf0649f CZ |
2691 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2692 | if (r) { | |
2693 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2694 | adev->ip_blocks[i].version->funcs->name, r); | |
2695 | return r; | |
2696 | } | |
482f0e53 | 2697 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
2698 | } |
2699 | } | |
2700 | ||
2701 | return 0; | |
2702 | } | |
2703 | ||
e3ecdffa AD |
2704 | /** |
2705 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2706 | * | |
2707 | * @adev: amdgpu_device pointer | |
2708 | * | |
2709 | * First resume function for hardware IPs. The list of all the hardware | |
2710 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2711 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2712 | * functional state after a suspend and updates the software state as | |
2713 | * necessary. This function is also used for restoring the GPU after a GPU | |
2714 | * reset. | |
2715 | * Returns 0 on success, negative error code on failure. | |
2716 | */ | |
06ec9070 | 2717 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2718 | { |
2719 | int i, r; | |
2720 | ||
2721 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 2722 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2723 | continue; |
fcf0649f | 2724 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 2725 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
2726 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
2727 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 2728 | continue; |
a1255107 | 2729 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2730 | if (r) { |
a1255107 AD |
2731 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2732 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2733 | return r; |
2c1a2784 | 2734 | } |
482f0e53 | 2735 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
2736 | } |
2737 | ||
2738 | return 0; | |
2739 | } | |
2740 | ||
e3ecdffa AD |
2741 | /** |
2742 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2743 | * | |
2744 | * @adev: amdgpu_device pointer | |
2745 | * | |
2746 | * Main resume function for hardware IPs. The hardware IPs | |
2747 | * are split into two resume functions because they are | |
2748 | * are also used in in recovering from a GPU reset and some additional | |
2749 | * steps need to be take between them. In this case (S3/S4) they are | |
2750 | * run sequentially. | |
2751 | * Returns 0 on success, negative error code on failure. | |
2752 | */ | |
06ec9070 | 2753 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2754 | { |
2755 | int r; | |
2756 | ||
06ec9070 | 2757 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2758 | if (r) |
2759 | return r; | |
7a3e0bb2 RZ |
2760 | |
2761 | r = amdgpu_device_fw_loading(adev); | |
2762 | if (r) | |
2763 | return r; | |
2764 | ||
06ec9070 | 2765 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2766 | |
2767 | return r; | |
2768 | } | |
2769 | ||
e3ecdffa AD |
2770 | /** |
2771 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2772 | * | |
2773 | * @adev: amdgpu_device pointer | |
2774 | * | |
2775 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2776 | */ | |
4e99a44e | 2777 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2778 | { |
6867e1b5 ML |
2779 | if (amdgpu_sriov_vf(adev)) { |
2780 | if (adev->is_atom_fw) { | |
2781 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2782 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2783 | } else { | |
2784 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2785 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2786 | } | |
2787 | ||
2788 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2789 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2790 | } |
048765ad AR |
2791 | } |
2792 | ||
e3ecdffa AD |
2793 | /** |
2794 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2795 | * | |
2796 | * @asic_type: AMD asic type | |
2797 | * | |
2798 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2799 | * returns true if DC has support, false if not. | |
2800 | */ | |
4562236b HW |
2801 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2802 | { | |
2803 | switch (asic_type) { | |
2804 | #if defined(CONFIG_DRM_AMD_DC) | |
64200c46 MR |
2805 | #if defined(CONFIG_DRM_AMD_DC_SI) |
2806 | case CHIP_TAHITI: | |
2807 | case CHIP_PITCAIRN: | |
2808 | case CHIP_VERDE: | |
2809 | case CHIP_OLAND: | |
2810 | #endif | |
4562236b | 2811 | case CHIP_BONAIRE: |
0d6fbccb | 2812 | case CHIP_KAVERI: |
367e6687 AD |
2813 | case CHIP_KABINI: |
2814 | case CHIP_MULLINS: | |
d9fda248 HW |
2815 | /* |
2816 | * We have systems in the wild with these ASICs that require | |
2817 | * LVDS and VGA support which is not supported with DC. | |
2818 | * | |
2819 | * Fallback to the non-DC driver here by default so as not to | |
2820 | * cause regressions. | |
2821 | */ | |
2822 | return amdgpu_dc > 0; | |
2823 | case CHIP_HAWAII: | |
4562236b HW |
2824 | case CHIP_CARRIZO: |
2825 | case CHIP_STONEY: | |
4562236b | 2826 | case CHIP_POLARIS10: |
675fd32b | 2827 | case CHIP_POLARIS11: |
2c8ad2d5 | 2828 | case CHIP_POLARIS12: |
675fd32b | 2829 | case CHIP_VEGAM: |
4562236b HW |
2830 | case CHIP_TONGA: |
2831 | case CHIP_FIJI: | |
42f8ffa1 | 2832 | case CHIP_VEGA10: |
dca7b401 | 2833 | case CHIP_VEGA12: |
c6034aa2 | 2834 | case CHIP_VEGA20: |
b86a1aa3 | 2835 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
fd187853 | 2836 | case CHIP_RAVEN: |
b4f199c7 | 2837 | case CHIP_NAVI10: |
8fceceb6 | 2838 | case CHIP_NAVI14: |
078655d9 | 2839 | case CHIP_NAVI12: |
e1c14c43 | 2840 | case CHIP_RENOIR: |
81d9bfb8 JFZ |
2841 | #endif |
2842 | #if defined(CONFIG_DRM_AMD_DC_DCN3_0) | |
2843 | case CHIP_SIENNA_CICHLID: | |
a6c5308f | 2844 | case CHIP_NAVY_FLOUNDER: |
42f8ffa1 | 2845 | #endif |
fd187853 | 2846 | return amdgpu_dc != 0; |
4562236b HW |
2847 | #endif |
2848 | default: | |
93b09a9a SS |
2849 | if (amdgpu_dc > 0) |
2850 | DRM_INFO("Display Core has been requested via kernel parameter " | |
2851 | "but isn't supported by ASIC, ignoring\n"); | |
4562236b HW |
2852 | return false; |
2853 | } | |
2854 | } | |
2855 | ||
2856 | /** | |
2857 | * amdgpu_device_has_dc_support - check if dc is supported | |
2858 | * | |
2859 | * @adev: amdgpu_device_pointer | |
2860 | * | |
2861 | * Returns true for supported, false for not supported | |
2862 | */ | |
2863 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2864 | { | |
c997e8e2 | 2865 | if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display) |
2555039d XY |
2866 | return false; |
2867 | ||
4562236b HW |
2868 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2869 | } | |
2870 | ||
d4535e2c AG |
2871 | |
2872 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) | |
2873 | { | |
2874 | struct amdgpu_device *adev = | |
2875 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 2876 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 2877 | |
c6a6e2db AG |
2878 | /* It's a bug to not have a hive within this function */ |
2879 | if (WARN_ON(!hive)) | |
2880 | return; | |
2881 | ||
2882 | /* | |
2883 | * Use task barrier to synchronize all xgmi reset works across the | |
2884 | * hive. task_barrier_enter and task_barrier_exit will block | |
2885 | * until all the threads running the xgmi reset works reach | |
2886 | * those points. task_barrier_full will do both blocks. | |
2887 | */ | |
2888 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
2889 | ||
2890 | task_barrier_enter(&hive->tb); | |
4a580877 | 2891 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
2892 | |
2893 | if (adev->asic_reset_res) | |
2894 | goto fail; | |
2895 | ||
2896 | task_barrier_exit(&hive->tb); | |
4a580877 | 2897 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
2898 | |
2899 | if (adev->asic_reset_res) | |
2900 | goto fail; | |
43c4d576 JC |
2901 | |
2902 | if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count) | |
2903 | adev->mmhub.funcs->reset_ras_error_count(adev); | |
c6a6e2db AG |
2904 | } else { |
2905 | ||
2906 | task_barrier_full(&hive->tb); | |
2907 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
2908 | } | |
ce316fa5 | 2909 | |
c6a6e2db | 2910 | fail: |
d4535e2c | 2911 | if (adev->asic_reset_res) |
fed184e9 | 2912 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 2913 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 2914 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
2915 | } |
2916 | ||
71f98027 AD |
2917 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
2918 | { | |
2919 | char *input = amdgpu_lockup_timeout; | |
2920 | char *timeout_setting = NULL; | |
2921 | int index = 0; | |
2922 | long timeout; | |
2923 | int ret = 0; | |
2924 | ||
2925 | /* | |
2926 | * By default timeout for non compute jobs is 10000. | |
2927 | * And there is no timeout enforced on compute jobs. | |
2928 | * In SR-IOV or passthrough mode, timeout for compute | |
b7b2a316 | 2929 | * jobs are 60000 by default. |
71f98027 AD |
2930 | */ |
2931 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
2932 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
2933 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) | |
b7b2a316 | 2934 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 AD |
2935 | else |
2936 | adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; | |
2937 | ||
f440ff44 | 2938 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 2939 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 2940 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
2941 | ret = kstrtol(timeout_setting, 0, &timeout); |
2942 | if (ret) | |
2943 | return ret; | |
2944 | ||
2945 | if (timeout == 0) { | |
2946 | index++; | |
2947 | continue; | |
2948 | } else if (timeout < 0) { | |
2949 | timeout = MAX_SCHEDULE_TIMEOUT; | |
2950 | } else { | |
2951 | timeout = msecs_to_jiffies(timeout); | |
2952 | } | |
2953 | ||
2954 | switch (index++) { | |
2955 | case 0: | |
2956 | adev->gfx_timeout = timeout; | |
2957 | break; | |
2958 | case 1: | |
2959 | adev->compute_timeout = timeout; | |
2960 | break; | |
2961 | case 2: | |
2962 | adev->sdma_timeout = timeout; | |
2963 | break; | |
2964 | case 3: | |
2965 | adev->video_timeout = timeout; | |
2966 | break; | |
2967 | default: | |
2968 | break; | |
2969 | } | |
2970 | } | |
2971 | /* | |
2972 | * There is only one value specified and | |
2973 | * it should apply to all non-compute jobs. | |
2974 | */ | |
bcccee89 | 2975 | if (index == 1) { |
71f98027 | 2976 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
2977 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
2978 | adev->compute_timeout = adev->gfx_timeout; | |
2979 | } | |
71f98027 AD |
2980 | } |
2981 | ||
2982 | return ret; | |
2983 | } | |
d4535e2c | 2984 | |
77f3a5cd ND |
2985 | static const struct attribute *amdgpu_dev_attributes[] = { |
2986 | &dev_attr_product_name.attr, | |
2987 | &dev_attr_product_number.attr, | |
2988 | &dev_attr_serial_number.attr, | |
2989 | &dev_attr_pcie_replay_count.attr, | |
2990 | NULL | |
2991 | }; | |
2992 | ||
d38ceaf9 AD |
2993 | /** |
2994 | * amdgpu_device_init - initialize the driver | |
2995 | * | |
2996 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
2997 | * @flags: driver flags |
2998 | * | |
2999 | * Initializes the driver info and hw (all asics). | |
3000 | * Returns 0 for success or an error on failure. | |
3001 | * Called at driver startup. | |
3002 | */ | |
3003 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3004 | uint32_t flags) |
3005 | { | |
8aba21b7 LT |
3006 | struct drm_device *ddev = adev_to_drm(adev); |
3007 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3008 | int r, i; |
3840c5bc | 3009 | bool boco = false; |
95844d20 | 3010 | u32 max_MBps; |
d38ceaf9 AD |
3011 | |
3012 | adev->shutdown = false; | |
d38ceaf9 | 3013 | adev->flags = flags; |
4e66d7d2 YZ |
3014 | |
3015 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3016 | adev->asic_type = amdgpu_force_asic_type; | |
3017 | else | |
3018 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3019 | ||
d38ceaf9 | 3020 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3021 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3022 | adev->usec_timeout *= 10; |
770d13b1 | 3023 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3024 | adev->accel_working = false; |
3025 | adev->num_rings = 0; | |
3026 | adev->mman.buffer_funcs = NULL; | |
3027 | adev->mman.buffer_funcs_ring = NULL; | |
3028 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3029 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3030 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 3031 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3032 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3033 | |
3034 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3035 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3036 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3037 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3038 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3039 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3040 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3041 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3042 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3043 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3044 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3045 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3046 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3047 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3048 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3049 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3050 | ||
3e39ab90 AD |
3051 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3052 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3053 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3054 | |
3055 | /* mutex initialization are all done here so we | |
3056 | * can recall function without having locking issues */ | |
d38ceaf9 | 3057 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 3058 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3059 | mutex_init(&adev->pm.mutex); |
3060 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3061 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3062 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3063 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3064 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3065 | mutex_init(&adev->mn_lock); |
e23b74aa | 3066 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3067 | hash_init(adev->mn_hash); |
53b3f8f4 | 3068 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 3069 | init_rwsem(&adev->reset_sem); |
32eaeae0 | 3070 | mutex_init(&adev->psp.mutex); |
bd052211 | 3071 | mutex_init(&adev->notifier_lock); |
d38ceaf9 | 3072 | |
912dfc84 EQ |
3073 | r = amdgpu_device_check_arguments(adev); |
3074 | if (r) | |
3075 | return r; | |
d38ceaf9 | 3076 | |
d38ceaf9 AD |
3077 | spin_lock_init(&adev->mmio_idx_lock); |
3078 | spin_lock_init(&adev->smc_idx_lock); | |
3079 | spin_lock_init(&adev->pcie_idx_lock); | |
3080 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3081 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3082 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3083 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3084 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3085 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3086 | |
0c4e7fa5 CZ |
3087 | INIT_LIST_HEAD(&adev->shadow_list); |
3088 | mutex_init(&adev->shadow_list_lock); | |
3089 | ||
beff74bc AD |
3090 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3091 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3092 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3093 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3094 | |
d4535e2c AG |
3095 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3096 | ||
d23ee13f | 3097 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3098 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3099 | |
b265bdbd EQ |
3100 | atomic_set(&adev->throttling_logging_enabled, 1); |
3101 | /* | |
3102 | * If throttling continues, logging will be performed every minute | |
3103 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3104 | * throttling interrupt comes every second. Thus, the total logging | |
3105 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3106 | * for throttling interrupt) = 60 seconds. | |
3107 | */ | |
3108 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3109 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3110 | ||
0fa49558 AX |
3111 | /* Registers mapping */ |
3112 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3113 | if (adev->asic_type >= CHIP_BONAIRE) { |
3114 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3115 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3116 | } else { | |
3117 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3118 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3119 | } | |
d38ceaf9 | 3120 | |
d38ceaf9 AD |
3121 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3122 | if (adev->rmmio == NULL) { | |
3123 | return -ENOMEM; | |
3124 | } | |
3125 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3126 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3127 | ||
d38ceaf9 AD |
3128 | /* io port mapping */ |
3129 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
3130 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
3131 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
3132 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
3133 | break; | |
3134 | } | |
3135 | } | |
3136 | if (adev->rio_mem == NULL) | |
b64a18c5 | 3137 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 3138 | |
b2109d8e JX |
3139 | /* enable PCIE atomic ops */ |
3140 | r = pci_enable_atomic_ops_to_root(adev->pdev, | |
3141 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3142 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3143 | if (r) { | |
3144 | adev->have_atomics_support = false; | |
3145 | DRM_INFO("PCIE atomic ops is not supported\n"); | |
3146 | } else { | |
3147 | adev->have_atomics_support = true; | |
3148 | } | |
3149 | ||
5494d864 AD |
3150 | amdgpu_device_get_pcie_info(adev); |
3151 | ||
b239c017 JX |
3152 | if (amdgpu_mcbp) |
3153 | DRM_INFO("MCBP is enabled\n"); | |
3154 | ||
5f84cc63 JX |
3155 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
3156 | adev->enable_mes = true; | |
3157 | ||
3aa0115d ML |
3158 | /* detect hw virtualization here */ |
3159 | amdgpu_detect_virtualization(adev); | |
3160 | ||
dffa11b4 ML |
3161 | r = amdgpu_device_get_job_timeout_settings(adev); |
3162 | if (r) { | |
3163 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
3164 | return r; | |
a190d1c7 XY |
3165 | } |
3166 | ||
d38ceaf9 | 3167 | /* early init functions */ |
06ec9070 | 3168 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
3169 | if (r) |
3170 | return r; | |
3171 | ||
6585661d OZ |
3172 | /* doorbell bar mapping and doorbell index init*/ |
3173 | amdgpu_device_doorbell_init(adev); | |
3174 | ||
d38ceaf9 AD |
3175 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3176 | /* this will fail for cards that aren't VGA class devices, just | |
3177 | * ignore it */ | |
06ec9070 | 3178 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 3179 | |
31af062a | 3180 | if (amdgpu_device_supports_boco(ddev)) |
3840c5bc AD |
3181 | boco = true; |
3182 | if (amdgpu_has_atpx() && | |
3183 | (amdgpu_is_atpx_hybrid() || | |
3184 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
3185 | !pci_is_thunderbolt_attached(adev->pdev)) | |
84c8b22e | 3186 | vga_switcheroo_register_client(adev->pdev, |
3840c5bc AD |
3187 | &amdgpu_switcheroo_ops, boco); |
3188 | if (boco) | |
d38ceaf9 AD |
3189 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); |
3190 | ||
9475a943 SL |
3191 | if (amdgpu_emu_mode == 1) { |
3192 | /* post the asic on emulation mode */ | |
3193 | emu_soc_asic_init(adev); | |
bfca0289 | 3194 | goto fence_driver_init; |
9475a943 | 3195 | } |
bfca0289 | 3196 | |
4e99a44e ML |
3197 | /* detect if we are with an SRIOV vbios */ |
3198 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3199 | |
95e8e59e AD |
3200 | /* check if we need to reset the asic |
3201 | * E.g., driver was not cleanly unloaded previously, etc. | |
3202 | */ | |
f14899fd | 3203 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
95e8e59e AD |
3204 | r = amdgpu_asic_reset(adev); |
3205 | if (r) { | |
3206 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3207 | goto failed; | |
3208 | } | |
3209 | } | |
3210 | ||
d38ceaf9 | 3211 | /* Post card if necessary */ |
39c640c0 | 3212 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3213 | if (!adev->bios) { |
bec86378 | 3214 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3215 | r = -EINVAL; |
3216 | goto failed; | |
d38ceaf9 | 3217 | } |
bec86378 | 3218 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3219 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3220 | if (r) { |
3221 | dev_err(adev->dev, "gpu post error!\n"); | |
3222 | goto failed; | |
3223 | } | |
d38ceaf9 AD |
3224 | } |
3225 | ||
88b64e95 AD |
3226 | if (adev->is_atom_fw) { |
3227 | /* Initialize clocks */ | |
3228 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3229 | if (r) { | |
3230 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3231 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3232 | goto failed; |
3233 | } | |
3234 | } else { | |
a5bde2f9 AD |
3235 | /* Initialize clocks */ |
3236 | r = amdgpu_atombios_get_clock_info(adev); | |
3237 | if (r) { | |
3238 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3239 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3240 | goto failed; |
a5bde2f9 AD |
3241 | } |
3242 | /* init i2c buses */ | |
4562236b HW |
3243 | if (!amdgpu_device_has_dc_support(adev)) |
3244 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3245 | } |
d38ceaf9 | 3246 | |
bfca0289 | 3247 | fence_driver_init: |
d38ceaf9 AD |
3248 | /* Fence driver */ |
3249 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
3250 | if (r) { |
3251 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 3252 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3253 | goto failed; |
2c1a2784 | 3254 | } |
d38ceaf9 AD |
3255 | |
3256 | /* init the mode config */ | |
4a580877 | 3257 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3258 | |
06ec9070 | 3259 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3260 | if (r) { |
8840a387 | 3261 | /* failed in exclusive mode due to timeout */ |
3262 | if (amdgpu_sriov_vf(adev) && | |
3263 | !amdgpu_sriov_runtime(adev) && | |
3264 | amdgpu_virt_mmio_blocked(adev) && | |
3265 | !amdgpu_virt_wait_reset(adev)) { | |
3266 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3267 | /* Don't send request since VF is inactive. */ |
3268 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3269 | adev->virt.ops = NULL; | |
8840a387 | 3270 | r = -EAGAIN; |
3271 | goto failed; | |
3272 | } | |
06ec9070 | 3273 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3274 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
83ba126a | 3275 | goto failed; |
d38ceaf9 AD |
3276 | } |
3277 | ||
d69b8971 YZ |
3278 | dev_info(adev->dev, |
3279 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3280 | adev->gfx.config.max_shader_engines, |
3281 | adev->gfx.config.max_sh_per_se, | |
3282 | adev->gfx.config.max_cu_per_sh, | |
3283 | adev->gfx.cu_info.number); | |
3284 | ||
d38ceaf9 AD |
3285 | adev->accel_working = true; |
3286 | ||
e59c0205 AX |
3287 | amdgpu_vm_check_compute_bug(adev); |
3288 | ||
95844d20 MO |
3289 | /* Initialize the buffer migration limit. */ |
3290 | if (amdgpu_moverate >= 0) | |
3291 | max_MBps = amdgpu_moverate; | |
3292 | else | |
3293 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3294 | /* Get a log2 for easy divisions. */ | |
3295 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3296 | ||
9bc92b9c ML |
3297 | amdgpu_fbdev_init(adev); |
3298 | ||
d2f52ac8 | 3299 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3300 | if (r) { |
3301 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3302 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3303 | } else |
3304 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3305 | |
5bb23532 | 3306 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3307 | if (r) { |
3308 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3309 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3310 | } else |
3311 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3312 | |
d38ceaf9 AD |
3313 | if ((amdgpu_testing & 1)) { |
3314 | if (adev->accel_working) | |
3315 | amdgpu_test_moves(adev); | |
3316 | else | |
3317 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
3318 | } | |
d38ceaf9 AD |
3319 | if (amdgpu_benchmarking) { |
3320 | if (adev->accel_working) | |
3321 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
3322 | else | |
3323 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
3324 | } | |
3325 | ||
b0adca4d EQ |
3326 | /* |
3327 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3328 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3329 | * gpu instance is counted less. | |
3330 | */ | |
3331 | amdgpu_register_gpu_instance(adev); | |
3332 | ||
d38ceaf9 AD |
3333 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3334 | * explicit gating rather than handling it automatically. | |
3335 | */ | |
06ec9070 | 3336 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 3337 | if (r) { |
06ec9070 | 3338 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 3339 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 3340 | goto failed; |
2c1a2784 | 3341 | } |
d38ceaf9 | 3342 | |
108c6a63 | 3343 | /* must succeed. */ |
511fdbc3 | 3344 | amdgpu_ras_resume(adev); |
108c6a63 | 3345 | |
beff74bc AD |
3346 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3347 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3348 | ||
2c738637 ML |
3349 | if (amdgpu_sriov_vf(adev)) |
3350 | flush_delayed_work(&adev->delayed_init_work); | |
3351 | ||
77f3a5cd | 3352 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
bd607166 | 3353 | if (r) { |
77f3a5cd | 3354 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 KR |
3355 | return r; |
3356 | } | |
3357 | ||
d155bef0 AB |
3358 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3359 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3360 | if (r) |
3361 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3362 | ||
d38ceaf9 | 3363 | return 0; |
83ba126a AD |
3364 | |
3365 | failed: | |
89041940 | 3366 | amdgpu_vf_error_trans_all(adev); |
3840c5bc | 3367 | if (boco) |
83ba126a | 3368 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
8840a387 | 3369 | |
83ba126a | 3370 | return r; |
d38ceaf9 AD |
3371 | } |
3372 | ||
d38ceaf9 AD |
3373 | /** |
3374 | * amdgpu_device_fini - tear down the driver | |
3375 | * | |
3376 | * @adev: amdgpu_device pointer | |
3377 | * | |
3378 | * Tear down the driver info (all asics). | |
3379 | * Called at driver shutdown. | |
3380 | */ | |
3381 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
3382 | { | |
aac89168 | 3383 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3384 | flush_delayed_work(&adev->delayed_init_work); |
d0d13fe8 | 3385 | adev->shutdown = true; |
9f875167 | 3386 | |
752c683d ML |
3387 | /* make sure IB test finished before entering exclusive mode |
3388 | * to avoid preemption on IB test | |
3389 | * */ | |
3390 | if (amdgpu_sriov_vf(adev)) | |
3391 | amdgpu_virt_request_full_gpu(adev, false); | |
3392 | ||
e5b03032 ML |
3393 | /* disable all interrupts */ |
3394 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
3395 | if (adev->mode_info.mode_config_initialized){ |
3396 | if (!amdgpu_device_has_dc_support(adev)) | |
4a580877 | 3397 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3398 | else |
4a580877 | 3399 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3400 | } |
d38ceaf9 | 3401 | amdgpu_fence_driver_fini(adev); |
7c868b59 YT |
3402 | if (adev->pm_sysfs_en) |
3403 | amdgpu_pm_sysfs_fini(adev); | |
d38ceaf9 | 3404 | amdgpu_fbdev_fini(adev); |
e230ac11 | 3405 | amdgpu_device_ip_fini(adev); |
75e1658e ND |
3406 | release_firmware(adev->firmware.gpu_info_fw); |
3407 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 AD |
3408 | adev->accel_working = false; |
3409 | /* free i2c buses */ | |
4562236b HW |
3410 | if (!amdgpu_device_has_dc_support(adev)) |
3411 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3412 | |
3413 | if (amdgpu_emu_mode != 1) | |
3414 | amdgpu_atombios_fini(adev); | |
3415 | ||
d38ceaf9 AD |
3416 | kfree(adev->bios); |
3417 | adev->bios = NULL; | |
3840c5bc AD |
3418 | if (amdgpu_has_atpx() && |
3419 | (amdgpu_is_atpx_hybrid() || | |
3420 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
3421 | !pci_is_thunderbolt_attached(adev->pdev)) | |
84c8b22e | 3422 | vga_switcheroo_unregister_client(adev->pdev); |
4a580877 | 3423 | if (amdgpu_device_supports_boco(adev_to_drm(adev))) |
83ba126a | 3424 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
d38ceaf9 AD |
3425 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
3426 | if (adev->rio_mem) | |
3427 | pci_iounmap(adev->pdev, adev->rio_mem); | |
3428 | adev->rio_mem = NULL; | |
3429 | iounmap(adev->rmmio); | |
3430 | adev->rmmio = NULL; | |
06ec9070 | 3431 | amdgpu_device_doorbell_fini(adev); |
e9bc1bf7 | 3432 | |
7c868b59 YT |
3433 | if (adev->ucode_sysfs_en) |
3434 | amdgpu_ucode_sysfs_fini(adev); | |
77f3a5cd ND |
3435 | |
3436 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
d155bef0 AB |
3437 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3438 | amdgpu_pmu_fini(adev); | |
72de33f8 | 3439 | if (adev->mman.discovery_bin) |
a190d1c7 | 3440 | amdgpu_discovery_fini(adev); |
d38ceaf9 AD |
3441 | } |
3442 | ||
3443 | ||
3444 | /* | |
3445 | * Suspend & resume. | |
3446 | */ | |
3447 | /** | |
810ddc3a | 3448 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3449 | * |
87e3f136 | 3450 | * @dev: drm dev pointer |
87e3f136 | 3451 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
3452 | * |
3453 | * Puts the hw in the suspend state (all asics). | |
3454 | * Returns 0 for success or an error on failure. | |
3455 | * Called at driver suspend. | |
3456 | */ | |
de185019 | 3457 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 AD |
3458 | { |
3459 | struct amdgpu_device *adev; | |
3460 | struct drm_crtc *crtc; | |
3461 | struct drm_connector *connector; | |
f8d2d39e | 3462 | struct drm_connector_list_iter iter; |
5ceb54c6 | 3463 | int r; |
d38ceaf9 | 3464 | |
8aba21b7 | 3465 | if (!dev) |
d38ceaf9 | 3466 | return -ENODEV; |
d38ceaf9 | 3467 | |
1348969a | 3468 | adev = drm_to_adev(dev); |
d38ceaf9 AD |
3469 | |
3470 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3471 | return 0; | |
3472 | ||
44779b43 | 3473 | adev->in_suspend = true; |
d38ceaf9 AD |
3474 | drm_kms_helper_poll_disable(dev); |
3475 | ||
5f818173 S |
3476 | if (fbcon) |
3477 | amdgpu_fbdev_set_suspend(adev, 1); | |
3478 | ||
beff74bc | 3479 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3480 | |
4562236b HW |
3481 | if (!amdgpu_device_has_dc_support(adev)) { |
3482 | /* turn off display hw */ | |
3483 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3484 | drm_connector_list_iter_begin(dev, &iter); |
3485 | drm_for_each_connector_iter(connector, &iter) | |
3486 | drm_helper_connector_dpms(connector, | |
3487 | DRM_MODE_DPMS_OFF); | |
3488 | drm_connector_list_iter_end(&iter); | |
4562236b | 3489 | drm_modeset_unlock_all(dev); |
fe1053b7 AD |
3490 | /* unpin the front buffers and cursors */ |
3491 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3492 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3493 | struct drm_framebuffer *fb = crtc->primary->fb; | |
3494 | struct amdgpu_bo *robj; | |
3495 | ||
91334223 | 3496 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3497 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3498 | r = amdgpu_bo_reserve(aobj, true); | |
3499 | if (r == 0) { | |
3500 | amdgpu_bo_unpin(aobj); | |
3501 | amdgpu_bo_unreserve(aobj); | |
3502 | } | |
756e6880 | 3503 | } |
756e6880 | 3504 | |
fe1053b7 AD |
3505 | if (fb == NULL || fb->obj[0] == NULL) { |
3506 | continue; | |
3507 | } | |
3508 | robj = gem_to_amdgpu_bo(fb->obj[0]); | |
3509 | /* don't unpin kernel fb objects */ | |
3510 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
3511 | r = amdgpu_bo_reserve(robj, true); | |
3512 | if (r == 0) { | |
3513 | amdgpu_bo_unpin(robj); | |
3514 | amdgpu_bo_unreserve(robj); | |
3515 | } | |
d38ceaf9 AD |
3516 | } |
3517 | } | |
3518 | } | |
fe1053b7 | 3519 | |
5e6932fe | 3520 | amdgpu_ras_suspend(adev); |
3521 | ||
fe1053b7 AD |
3522 | r = amdgpu_device_ip_suspend_phase1(adev); |
3523 | ||
94fa5660 EQ |
3524 | amdgpu_amdkfd_suspend(adev, !fbcon); |
3525 | ||
d38ceaf9 AD |
3526 | /* evict vram memory */ |
3527 | amdgpu_bo_evict_vram(adev); | |
3528 | ||
5ceb54c6 | 3529 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 3530 | |
fe1053b7 | 3531 | r = amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 3532 | |
a0a71e49 AD |
3533 | /* evict remaining vram memory |
3534 | * This second call to evict vram is to evict the gart page table | |
3535 | * using the CPU. | |
3536 | */ | |
d38ceaf9 AD |
3537 | amdgpu_bo_evict_vram(adev); |
3538 | ||
d38ceaf9 AD |
3539 | return 0; |
3540 | } | |
3541 | ||
3542 | /** | |
810ddc3a | 3543 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 3544 | * |
87e3f136 | 3545 | * @dev: drm dev pointer |
87e3f136 | 3546 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
3547 | * |
3548 | * Bring the hw back to operating state (all asics). | |
3549 | * Returns 0 for success or an error on failure. | |
3550 | * Called at driver resume. | |
3551 | */ | |
de185019 | 3552 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 AD |
3553 | { |
3554 | struct drm_connector *connector; | |
f8d2d39e | 3555 | struct drm_connector_list_iter iter; |
1348969a | 3556 | struct amdgpu_device *adev = drm_to_adev(dev); |
756e6880 | 3557 | struct drm_crtc *crtc; |
03161a6e | 3558 | int r = 0; |
d38ceaf9 AD |
3559 | |
3560 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3561 | return 0; | |
3562 | ||
d38ceaf9 | 3563 | /* post card */ |
39c640c0 | 3564 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 3565 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 3566 | if (r) |
aac89168 | 3567 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 3568 | } |
d38ceaf9 | 3569 | |
06ec9070 | 3570 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 3571 | if (r) { |
aac89168 | 3572 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 3573 | return r; |
e6707218 | 3574 | } |
5ceb54c6 AD |
3575 | amdgpu_fence_driver_resume(adev); |
3576 | ||
d38ceaf9 | 3577 | |
06ec9070 | 3578 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 3579 | if (r) |
4d3b9ae5 | 3580 | return r; |
d38ceaf9 | 3581 | |
beff74bc AD |
3582 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3583 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3584 | ||
fe1053b7 AD |
3585 | if (!amdgpu_device_has_dc_support(adev)) { |
3586 | /* pin cursors */ | |
3587 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3588 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3589 | ||
91334223 | 3590 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3591 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3592 | r = amdgpu_bo_reserve(aobj, true); | |
3593 | if (r == 0) { | |
3594 | r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); | |
3595 | if (r != 0) | |
aac89168 | 3596 | dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); |
fe1053b7 AD |
3597 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); |
3598 | amdgpu_bo_unreserve(aobj); | |
3599 | } | |
756e6880 AD |
3600 | } |
3601 | } | |
3602 | } | |
9593f4d6 | 3603 | r = amdgpu_amdkfd_resume(adev, !fbcon); |
ba997709 YZ |
3604 | if (r) |
3605 | return r; | |
756e6880 | 3606 | |
96a5d8d4 | 3607 | /* Make sure IB tests flushed */ |
beff74bc | 3608 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 3609 | |
d38ceaf9 AD |
3610 | /* blat the mode back in */ |
3611 | if (fbcon) { | |
4562236b HW |
3612 | if (!amdgpu_device_has_dc_support(adev)) { |
3613 | /* pre DCE11 */ | |
3614 | drm_helper_resume_force_mode(dev); | |
3615 | ||
3616 | /* turn on display hw */ | |
3617 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3618 | |
3619 | drm_connector_list_iter_begin(dev, &iter); | |
3620 | drm_for_each_connector_iter(connector, &iter) | |
3621 | drm_helper_connector_dpms(connector, | |
3622 | DRM_MODE_DPMS_ON); | |
3623 | drm_connector_list_iter_end(&iter); | |
3624 | ||
4562236b | 3625 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 3626 | } |
4d3b9ae5 | 3627 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
3628 | } |
3629 | ||
3630 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 3631 | |
5e6932fe | 3632 | amdgpu_ras_resume(adev); |
3633 | ||
23a1a9e5 L |
3634 | /* |
3635 | * Most of the connector probing functions try to acquire runtime pm | |
3636 | * refs to ensure that the GPU is powered on when connector polling is | |
3637 | * performed. Since we're calling this from a runtime PM callback, | |
3638 | * trying to acquire rpm refs will cause us to deadlock. | |
3639 | * | |
3640 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
3641 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
3642 | */ | |
3643 | #ifdef CONFIG_PM | |
3644 | dev->dev->power.disable_depth++; | |
3645 | #endif | |
4562236b HW |
3646 | if (!amdgpu_device_has_dc_support(adev)) |
3647 | drm_helper_hpd_irq_event(dev); | |
3648 | else | |
3649 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
3650 | #ifdef CONFIG_PM |
3651 | dev->dev->power.disable_depth--; | |
3652 | #endif | |
44779b43 RZ |
3653 | adev->in_suspend = false; |
3654 | ||
4d3b9ae5 | 3655 | return 0; |
d38ceaf9 AD |
3656 | } |
3657 | ||
e3ecdffa AD |
3658 | /** |
3659 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
3660 | * | |
3661 | * @adev: amdgpu_device pointer | |
3662 | * | |
3663 | * The list of all the hardware IPs that make up the asic is walked and | |
3664 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
3665 | * if the asic is still hung or not. | |
3666 | * Returns true if any of the IPs are still in a hung state, false if not. | |
3667 | */ | |
06ec9070 | 3668 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
3669 | { |
3670 | int i; | |
3671 | bool asic_hang = false; | |
3672 | ||
f993d628 ML |
3673 | if (amdgpu_sriov_vf(adev)) |
3674 | return true; | |
3675 | ||
8bc04c29 AD |
3676 | if (amdgpu_asic_need_full_reset(adev)) |
3677 | return true; | |
3678 | ||
63fbf42f | 3679 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3680 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 3681 | continue; |
a1255107 AD |
3682 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
3683 | adev->ip_blocks[i].status.hang = | |
3684 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
3685 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 3686 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
3687 | asic_hang = true; |
3688 | } | |
3689 | } | |
3690 | return asic_hang; | |
3691 | } | |
3692 | ||
e3ecdffa AD |
3693 | /** |
3694 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
3695 | * | |
3696 | * @adev: amdgpu_device pointer | |
3697 | * | |
3698 | * The list of all the hardware IPs that make up the asic is walked and the | |
3699 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
3700 | * handles any IP specific hardware or software state changes that are | |
3701 | * necessary for a soft reset to succeed. | |
3702 | * Returns 0 on success, negative error code on failure. | |
3703 | */ | |
06ec9070 | 3704 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
3705 | { |
3706 | int i, r = 0; | |
3707 | ||
3708 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3709 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 3710 | continue; |
a1255107 AD |
3711 | if (adev->ip_blocks[i].status.hang && |
3712 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
3713 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
3714 | if (r) |
3715 | return r; | |
3716 | } | |
3717 | } | |
3718 | ||
3719 | return 0; | |
3720 | } | |
3721 | ||
e3ecdffa AD |
3722 | /** |
3723 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
3724 | * | |
3725 | * @adev: amdgpu_device pointer | |
3726 | * | |
3727 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
3728 | * reset is necessary to recover. | |
3729 | * Returns true if a full asic reset is required, false if not. | |
3730 | */ | |
06ec9070 | 3731 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 3732 | { |
da146d3b AD |
3733 | int i; |
3734 | ||
8bc04c29 AD |
3735 | if (amdgpu_asic_need_full_reset(adev)) |
3736 | return true; | |
3737 | ||
da146d3b | 3738 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3739 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 3740 | continue; |
a1255107 AD |
3741 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
3742 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
3743 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
3744 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
3745 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 3746 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 3747 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
3748 | return true; |
3749 | } | |
3750 | } | |
35d782fe CZ |
3751 | } |
3752 | return false; | |
3753 | } | |
3754 | ||
e3ecdffa AD |
3755 | /** |
3756 | * amdgpu_device_ip_soft_reset - do a soft reset | |
3757 | * | |
3758 | * @adev: amdgpu_device pointer | |
3759 | * | |
3760 | * The list of all the hardware IPs that make up the asic is walked and the | |
3761 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
3762 | * IP specific hardware or software state changes that are necessary to soft | |
3763 | * reset the IP. | |
3764 | * Returns 0 on success, negative error code on failure. | |
3765 | */ | |
06ec9070 | 3766 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3767 | { |
3768 | int i, r = 0; | |
3769 | ||
3770 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3771 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3772 | continue; |
a1255107 AD |
3773 | if (adev->ip_blocks[i].status.hang && |
3774 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
3775 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
3776 | if (r) |
3777 | return r; | |
3778 | } | |
3779 | } | |
3780 | ||
3781 | return 0; | |
3782 | } | |
3783 | ||
e3ecdffa AD |
3784 | /** |
3785 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
3786 | * | |
3787 | * @adev: amdgpu_device pointer | |
3788 | * | |
3789 | * The list of all the hardware IPs that make up the asic is walked and the | |
3790 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
3791 | * handles any IP specific hardware or software state changes that are | |
3792 | * necessary after the IP has been soft reset. | |
3793 | * Returns 0 on success, negative error code on failure. | |
3794 | */ | |
06ec9070 | 3795 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3796 | { |
3797 | int i, r = 0; | |
3798 | ||
3799 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3800 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3801 | continue; |
a1255107 AD |
3802 | if (adev->ip_blocks[i].status.hang && |
3803 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
3804 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
3805 | if (r) |
3806 | return r; | |
3807 | } | |
3808 | ||
3809 | return 0; | |
3810 | } | |
3811 | ||
e3ecdffa | 3812 | /** |
c33adbc7 | 3813 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
3814 | * |
3815 | * @adev: amdgpu_device pointer | |
3816 | * | |
3817 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
3818 | * restore things like GPUVM page tables after a GPU reset where | |
3819 | * the contents of VRAM might be lost. | |
403009bf CK |
3820 | * |
3821 | * Returns: | |
3822 | * 0 on success, negative error code on failure. | |
e3ecdffa | 3823 | */ |
c33adbc7 | 3824 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 3825 | { |
c41d1cf6 | 3826 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf CK |
3827 | struct amdgpu_bo *shadow; |
3828 | long r = 1, tmo; | |
c41d1cf6 ML |
3829 | |
3830 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 3831 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
3832 | else |
3833 | tmo = msecs_to_jiffies(100); | |
3834 | ||
aac89168 | 3835 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 3836 | mutex_lock(&adev->shadow_list_lock); |
403009bf CK |
3837 | list_for_each_entry(shadow, &adev->shadow_list, shadow_list) { |
3838 | ||
3839 | /* No need to recover an evicted BO */ | |
3840 | if (shadow->tbo.mem.mem_type != TTM_PL_TT || | |
b575f10d | 3841 | shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET || |
403009bf CK |
3842 | shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM) |
3843 | continue; | |
3844 | ||
3845 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
3846 | if (r) | |
3847 | break; | |
3848 | ||
c41d1cf6 | 3849 | if (fence) { |
1712fb1a | 3850 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
3851 | dma_fence_put(fence); |
3852 | fence = next; | |
1712fb1a | 3853 | if (tmo == 0) { |
3854 | r = -ETIMEDOUT; | |
c41d1cf6 | 3855 | break; |
1712fb1a | 3856 | } else if (tmo < 0) { |
3857 | r = tmo; | |
3858 | break; | |
3859 | } | |
403009bf CK |
3860 | } else { |
3861 | fence = next; | |
c41d1cf6 | 3862 | } |
c41d1cf6 ML |
3863 | } |
3864 | mutex_unlock(&adev->shadow_list_lock); | |
3865 | ||
403009bf CK |
3866 | if (fence) |
3867 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
3868 | dma_fence_put(fence); |
3869 | ||
1712fb1a | 3870 | if (r < 0 || tmo <= 0) { |
aac89168 | 3871 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
3872 | return -EIO; |
3873 | } | |
c41d1cf6 | 3874 | |
aac89168 | 3875 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 3876 | return 0; |
c41d1cf6 ML |
3877 | } |
3878 | ||
a90ad3c2 | 3879 | |
e3ecdffa | 3880 | /** |
06ec9070 | 3881 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3882 | * |
3883 | * @adev: amdgpu device pointer | |
87e3f136 | 3884 | * @from_hypervisor: request from hypervisor |
5740682e ML |
3885 | * |
3886 | * do VF FLR and reinitialize Asic | |
3f48c681 | 3887 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
3888 | */ |
3889 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3890 | bool from_hypervisor) | |
5740682e ML |
3891 | { |
3892 | int r; | |
3893 | ||
3894 | if (from_hypervisor) | |
3895 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3896 | else | |
3897 | r = amdgpu_virt_reset_gpu(adev); | |
3898 | if (r) | |
3899 | return r; | |
a90ad3c2 | 3900 | |
b639c22c JZ |
3901 | amdgpu_amdkfd_pre_reset(adev); |
3902 | ||
a90ad3c2 | 3903 | /* Resume IP prior to SMC */ |
06ec9070 | 3904 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3905 | if (r) |
3906 | goto error; | |
a90ad3c2 | 3907 | |
c9ffa427 | 3908 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 3909 | /* we need recover gart prior to run SMC/CP/SDMA resume */ |
c1c7ce8f | 3910 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 | 3911 | |
7a3e0bb2 RZ |
3912 | r = amdgpu_device_fw_loading(adev); |
3913 | if (r) | |
3914 | return r; | |
3915 | ||
a90ad3c2 | 3916 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 3917 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
3918 | if (r) |
3919 | goto error; | |
a90ad3c2 ML |
3920 | |
3921 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3922 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 3923 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 3924 | |
abc34253 ED |
3925 | error: |
3926 | amdgpu_virt_release_full_gpu(adev, true); | |
c41d1cf6 | 3927 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 3928 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 3929 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 ML |
3930 | } |
3931 | ||
3932 | return r; | |
3933 | } | |
3934 | ||
9a1cddd6 | 3935 | /** |
3936 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
3937 | * | |
3938 | * @adev: amdgpu device pointer | |
3939 | * | |
3940 | * check if there is any job in mirror list | |
3941 | */ | |
3942 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
3943 | { | |
3944 | int i; | |
3945 | struct drm_sched_job *job; | |
3946 | ||
3947 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
3948 | struct amdgpu_ring *ring = adev->rings[i]; | |
3949 | ||
3950 | if (!ring || !ring->sched.thread) | |
3951 | continue; | |
3952 | ||
3953 | spin_lock(&ring->sched.job_list_lock); | |
3954 | job = list_first_entry_or_null(&ring->sched.ring_mirror_list, | |
3955 | struct drm_sched_job, node); | |
3956 | spin_unlock(&ring->sched.job_list_lock); | |
3957 | if (job) | |
3958 | return true; | |
3959 | } | |
3960 | return false; | |
3961 | } | |
3962 | ||
12938fad CK |
3963 | /** |
3964 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
3965 | * | |
3966 | * @adev: amdgpu device pointer | |
3967 | * | |
3968 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
3969 | * a hung GPU. | |
3970 | */ | |
3971 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
3972 | { | |
3973 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 3974 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
3975 | return false; |
3976 | } | |
3977 | ||
3ba7b418 AG |
3978 | if (amdgpu_gpu_recovery == 0) |
3979 | goto disabled; | |
3980 | ||
3981 | if (amdgpu_sriov_vf(adev)) | |
3982 | return true; | |
3983 | ||
3984 | if (amdgpu_gpu_recovery == -1) { | |
3985 | switch (adev->asic_type) { | |
fc42d47c AG |
3986 | case CHIP_BONAIRE: |
3987 | case CHIP_HAWAII: | |
3ba7b418 AG |
3988 | case CHIP_TOPAZ: |
3989 | case CHIP_TONGA: | |
3990 | case CHIP_FIJI: | |
3991 | case CHIP_POLARIS10: | |
3992 | case CHIP_POLARIS11: | |
3993 | case CHIP_POLARIS12: | |
3994 | case CHIP_VEGAM: | |
3995 | case CHIP_VEGA20: | |
3996 | case CHIP_VEGA10: | |
3997 | case CHIP_VEGA12: | |
c43b849f | 3998 | case CHIP_RAVEN: |
e9d4cf91 | 3999 | case CHIP_ARCTURUS: |
2cb44fb0 | 4000 | case CHIP_RENOIR: |
658c6639 AD |
4001 | case CHIP_NAVI10: |
4002 | case CHIP_NAVI14: | |
4003 | case CHIP_NAVI12: | |
131a3c74 | 4004 | case CHIP_SIENNA_CICHLID: |
3ba7b418 AG |
4005 | break; |
4006 | default: | |
4007 | goto disabled; | |
4008 | } | |
12938fad CK |
4009 | } |
4010 | ||
4011 | return true; | |
3ba7b418 AG |
4012 | |
4013 | disabled: | |
aac89168 | 4014 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4015 | return false; |
12938fad CK |
4016 | } |
4017 | ||
5c6dd71e | 4018 | |
26bc5340 AG |
4019 | static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
4020 | struct amdgpu_job *job, | |
4021 | bool *need_full_reset_arg) | |
4022 | { | |
4023 | int i, r = 0; | |
4024 | bool need_full_reset = *need_full_reset_arg; | |
71182665 | 4025 | |
728e7e0c JZ |
4026 | amdgpu_debugfs_wait_dump(adev); |
4027 | ||
71182665 | 4028 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4029 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4030 | struct amdgpu_ring *ring = adev->rings[i]; | |
4031 | ||
51687759 | 4032 | if (!ring || !ring->sched.thread) |
0875dc9e | 4033 | continue; |
5740682e | 4034 | |
2f9d4084 ML |
4035 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4036 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4037 | } |
d38ceaf9 | 4038 | |
222b5f04 AG |
4039 | if(job) |
4040 | drm_sched_increase_karma(&job->base); | |
4041 | ||
1d721ed6 | 4042 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4043 | if (!amdgpu_sriov_vf(adev)) { |
4044 | ||
4045 | if (!need_full_reset) | |
4046 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4047 | ||
4048 | if (!need_full_reset) { | |
4049 | amdgpu_device_ip_pre_soft_reset(adev); | |
4050 | r = amdgpu_device_ip_soft_reset(adev); | |
4051 | amdgpu_device_ip_post_soft_reset(adev); | |
4052 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4053 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4054 | need_full_reset = true; |
4055 | } | |
4056 | } | |
4057 | ||
4058 | if (need_full_reset) | |
4059 | r = amdgpu_device_ip_suspend(adev); | |
4060 | ||
4061 | *need_full_reset_arg = need_full_reset; | |
4062 | } | |
4063 | ||
4064 | return r; | |
4065 | } | |
4066 | ||
041a62bc | 4067 | static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, |
26bc5340 AG |
4068 | struct list_head *device_list_handle, |
4069 | bool *need_full_reset_arg) | |
4070 | { | |
4071 | struct amdgpu_device *tmp_adev = NULL; | |
4072 | bool need_full_reset = *need_full_reset_arg, vram_lost = false; | |
4073 | int r = 0; | |
4074 | ||
4075 | /* | |
4076 | * ASIC reset has to be done on all HGMI hive nodes ASAP | |
4077 | * to allow proper links negotiation in FW (within 1 sec) | |
4078 | */ | |
4079 | if (need_full_reset) { | |
4080 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
041a62bc | 4081 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4082 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
c96cf282 | 4083 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4084 | r = -EALREADY; |
4085 | } else | |
4086 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4087 | |
041a62bc | 4088 | if (r) { |
aac89168 | 4089 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4090 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4091 | break; |
ce316fa5 LM |
4092 | } |
4093 | } | |
4094 | ||
041a62bc AG |
4095 | /* For XGMI wait for all resets to complete before proceed */ |
4096 | if (!r) { | |
ce316fa5 LM |
4097 | list_for_each_entry(tmp_adev, device_list_handle, |
4098 | gmc.xgmi.head) { | |
4099 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { | |
4100 | flush_work(&tmp_adev->xgmi_reset_work); | |
4101 | r = tmp_adev->asic_reset_res; | |
4102 | if (r) | |
4103 | break; | |
ce316fa5 LM |
4104 | } |
4105 | } | |
4106 | } | |
ce316fa5 | 4107 | } |
26bc5340 | 4108 | |
43c4d576 JC |
4109 | if (!r && amdgpu_ras_intr_triggered()) { |
4110 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
4111 | if (tmp_adev->mmhub.funcs && | |
4112 | tmp_adev->mmhub.funcs->reset_ras_error_count) | |
4113 | tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev); | |
4114 | } | |
4115 | ||
00eaa571 | 4116 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4117 | } |
00eaa571 | 4118 | |
26bc5340 AG |
4119 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { |
4120 | if (need_full_reset) { | |
4121 | /* post card */ | |
4d2997ab | 4122 | if (amdgpu_device_asic_init(tmp_adev)) |
aac89168 | 4123 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
26bc5340 AG |
4124 | |
4125 | if (!r) { | |
4126 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); | |
4127 | r = amdgpu_device_ip_resume_phase1(tmp_adev); | |
4128 | if (r) | |
4129 | goto out; | |
4130 | ||
4131 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
4132 | if (vram_lost) { | |
77e7f829 | 4133 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4134 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4135 | } |
4136 | ||
4137 | r = amdgpu_gtt_mgr_recover( | |
4138 | &tmp_adev->mman.bdev.man[TTM_PL_TT]); | |
4139 | if (r) | |
4140 | goto out; | |
4141 | ||
4142 | r = amdgpu_device_fw_loading(tmp_adev); | |
4143 | if (r) | |
4144 | return r; | |
4145 | ||
4146 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4147 | if (r) | |
4148 | goto out; | |
4149 | ||
4150 | if (vram_lost) | |
4151 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4152 | ||
fdafb359 EQ |
4153 | /* |
4154 | * Add this ASIC as tracked as reset was already | |
4155 | * complete successfully. | |
4156 | */ | |
4157 | amdgpu_register_gpu_instance(tmp_adev); | |
4158 | ||
7c04ca50 | 4159 | r = amdgpu_device_ip_late_init(tmp_adev); |
4160 | if (r) | |
4161 | goto out; | |
4162 | ||
565d1941 EQ |
4163 | amdgpu_fbdev_set_suspend(tmp_adev, 0); |
4164 | ||
e8fbaf03 GC |
4165 | /* |
4166 | * The GPU enters bad state once faulty pages | |
4167 | * by ECC has reached the threshold, and ras | |
4168 | * recovery is scheduled next. So add one check | |
4169 | * here to break recovery if it indeed exceeds | |
4170 | * bad page threshold, and remind user to | |
4171 | * retire this GPU or setting one bigger | |
4172 | * bad_page_threshold value to fix this once | |
4173 | * probing driver again. | |
4174 | */ | |
4175 | if (!amdgpu_ras_check_err_threshold(tmp_adev)) { | |
4176 | /* must succeed. */ | |
4177 | amdgpu_ras_resume(tmp_adev); | |
4178 | } else { | |
4179 | r = -EINVAL; | |
4180 | goto out; | |
4181 | } | |
e79a04d5 | 4182 | |
26bc5340 AG |
4183 | /* Update PSP FW topology after reset */ |
4184 | if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4185 | r = amdgpu_xgmi_update_topology(hive, tmp_adev); | |
4186 | } | |
4187 | } | |
4188 | ||
26bc5340 AG |
4189 | out: |
4190 | if (!r) { | |
4191 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4192 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4193 | if (r) { | |
4194 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
4195 | r = amdgpu_device_ip_suspend(tmp_adev); | |
4196 | need_full_reset = true; | |
4197 | r = -EAGAIN; | |
4198 | goto end; | |
4199 | } | |
4200 | } | |
4201 | ||
4202 | if (!r) | |
4203 | r = amdgpu_device_recover_vram(tmp_adev); | |
4204 | else | |
4205 | tmp_adev->asic_reset_res = r; | |
4206 | } | |
4207 | ||
4208 | end: | |
4209 | *need_full_reset_arg = need_full_reset; | |
4210 | return r; | |
4211 | } | |
4212 | ||
08ebb485 DL |
4213 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, |
4214 | struct amdgpu_hive_info *hive) | |
26bc5340 | 4215 | { |
53b3f8f4 DL |
4216 | if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0) |
4217 | return false; | |
4218 | ||
08ebb485 DL |
4219 | if (hive) { |
4220 | down_write_nest_lock(&adev->reset_sem, &hive->hive_lock); | |
4221 | } else { | |
4222 | down_write(&adev->reset_sem); | |
4223 | } | |
5740682e | 4224 | |
26bc5340 | 4225 | atomic_inc(&adev->gpu_reset_counter); |
a3a09142 AD |
4226 | switch (amdgpu_asic_reset_method(adev)) { |
4227 | case AMD_RESET_METHOD_MODE1: | |
4228 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4229 | break; | |
4230 | case AMD_RESET_METHOD_MODE2: | |
4231 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4232 | break; | |
4233 | default: | |
4234 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4235 | break; | |
4236 | } | |
1d721ed6 AG |
4237 | |
4238 | return true; | |
26bc5340 | 4239 | } |
d38ceaf9 | 4240 | |
26bc5340 AG |
4241 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
4242 | { | |
89041940 | 4243 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4244 | adev->mp1_state = PP_MP1_STATE_NONE; |
53b3f8f4 | 4245 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 4246 | up_write(&adev->reset_sem); |
26bc5340 AG |
4247 | } |
4248 | ||
3f12acc8 EQ |
4249 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4250 | { | |
4251 | struct pci_dev *p = NULL; | |
4252 | ||
4253 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4254 | adev->pdev->bus->number, 1); | |
4255 | if (p) { | |
4256 | pm_runtime_enable(&(p->dev)); | |
4257 | pm_runtime_resume(&(p->dev)); | |
4258 | } | |
4259 | } | |
4260 | ||
4261 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4262 | { | |
4263 | enum amd_reset_method reset_method; | |
4264 | struct pci_dev *p = NULL; | |
4265 | u64 expires; | |
4266 | ||
4267 | /* | |
4268 | * For now, only BACO and mode1 reset are confirmed | |
4269 | * to suffer the audio issue without proper suspended. | |
4270 | */ | |
4271 | reset_method = amdgpu_asic_reset_method(adev); | |
4272 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4273 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4274 | return -EINVAL; | |
4275 | ||
4276 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4277 | adev->pdev->bus->number, 1); | |
4278 | if (!p) | |
4279 | return -ENODEV; | |
4280 | ||
4281 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4282 | if (!expires) | |
4283 | /* | |
4284 | * If we cannot get the audio device autosuspend delay, | |
4285 | * a fixed 4S interval will be used. Considering 3S is | |
4286 | * the audio controller default autosuspend delay setting. | |
4287 | * 4S used here is guaranteed to cover that. | |
4288 | */ | |
54b7feb9 | 4289 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4290 | |
4291 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4292 | if (!pm_runtime_suspend(&(p->dev))) | |
4293 | break; | |
4294 | ||
4295 | if (expires < ktime_get_mono_fast_ns()) { | |
4296 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4297 | /* TODO: abort the succeeding gpu reset? */ | |
4298 | return -ETIMEDOUT; | |
4299 | } | |
4300 | } | |
4301 | ||
4302 | pm_runtime_disable(&(p->dev)); | |
4303 | ||
4304 | return 0; | |
4305 | } | |
4306 | ||
26bc5340 AG |
4307 | /** |
4308 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
4309 | * | |
4310 | * @adev: amdgpu device pointer | |
4311 | * @job: which job trigger hang | |
4312 | * | |
4313 | * Attempt to reset the GPU if it has hung (all asics). | |
4314 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
4315 | * Returns 0 for success or an error on failure. | |
4316 | */ | |
4317 | ||
4318 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
4319 | struct amdgpu_job *job) | |
4320 | { | |
1d721ed6 | 4321 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 EQ |
4322 | bool need_full_reset = false; |
4323 | bool job_signaled = false; | |
26bc5340 | 4324 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 4325 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 4326 | int i, r = 0; |
bb5c7235 | 4327 | bool need_emergency_restart = false; |
3f12acc8 | 4328 | bool audio_suspended = false; |
26bc5340 | 4329 | |
bb5c7235 WS |
4330 | /** |
4331 | * Special case: RAS triggered and full reset isn't supported | |
4332 | */ | |
4333 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
4334 | ||
d5ea093e AG |
4335 | /* |
4336 | * Flush RAM to disk so that after reboot | |
4337 | * the user can read log and see why the system rebooted. | |
4338 | */ | |
bb5c7235 | 4339 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
4340 | DRM_WARN("Emergency reboot."); |
4341 | ||
4342 | ksys_sync_helper(); | |
4343 | emergency_restart(); | |
4344 | } | |
4345 | ||
b823821f | 4346 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 4347 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 AG |
4348 | |
4349 | /* | |
1d721ed6 AG |
4350 | * Here we trylock to avoid chain of resets executing from |
4351 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
4352 | * different schedulers for same device while this TO handler is running. | |
4353 | * We always reset all schedulers for device and all devices for XGMI | |
4354 | * hive so that should take care of them too. | |
26bc5340 | 4355 | */ |
d95e8e97 | 4356 | hive = amdgpu_get_xgmi_hive(adev); |
53b3f8f4 DL |
4357 | if (hive) { |
4358 | if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) { | |
4359 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
4360 | job ? job->base.id : -1, hive->hive_id); | |
d95e8e97 | 4361 | amdgpu_put_xgmi_hive(hive); |
53b3f8f4 DL |
4362 | return 0; |
4363 | } | |
4364 | mutex_lock(&hive->hive_lock); | |
1d721ed6 | 4365 | } |
26bc5340 | 4366 | |
9e94d22c EQ |
4367 | /* |
4368 | * Build list of devices to reset. | |
4369 | * In case we are in XGMI hive mode, resort the device list | |
4370 | * to put adev in the 1st position. | |
4371 | */ | |
4372 | INIT_LIST_HEAD(&device_list); | |
4373 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
4374 | if (!hive) | |
26bc5340 | 4375 | return -ENODEV; |
9e94d22c EQ |
4376 | if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list)) |
4377 | list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list); | |
26bc5340 AG |
4378 | device_list_handle = &hive->device_list; |
4379 | } else { | |
4380 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
4381 | device_list_handle = &device_list; | |
4382 | } | |
4383 | ||
1d721ed6 AG |
4384 | /* block all schedulers and reset given job's ring */ |
4385 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
08ebb485 | 4386 | if (!amdgpu_device_lock_adev(tmp_adev, hive)) { |
aac89168 | 4387 | dev_info(tmp_adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress", |
9e94d22c | 4388 | job ? job->base.id : -1); |
cbfd17f7 DL |
4389 | r = 0; |
4390 | goto skip_recovery; | |
7c6e68c7 AG |
4391 | } |
4392 | ||
3f12acc8 EQ |
4393 | /* |
4394 | * Try to put the audio codec into suspend state | |
4395 | * before gpu reset started. | |
4396 | * | |
4397 | * Due to the power domain of the graphics device | |
4398 | * is shared with AZ power domain. Without this, | |
4399 | * we may change the audio hardware from behind | |
4400 | * the audio driver's back. That will trigger | |
4401 | * some audio codec errors. | |
4402 | */ | |
4403 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
4404 | audio_suspended = true; | |
4405 | ||
9e94d22c EQ |
4406 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
4407 | ||
52fb44cf EQ |
4408 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
4409 | ||
9e94d22c EQ |
4410 | if (!amdgpu_sriov_vf(tmp_adev)) |
4411 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
4412 | ||
12ffa55d AG |
4413 | /* |
4414 | * Mark these ASICs to be reseted as untracked first | |
4415 | * And add them back after reset completed | |
4416 | */ | |
4417 | amdgpu_unregister_gpu_instance(tmp_adev); | |
4418 | ||
a2f63ee8 | 4419 | amdgpu_fbdev_set_suspend(tmp_adev, 1); |
565d1941 | 4420 | |
f1c1314b | 4421 | /* disable ras on ALL IPs */ |
bb5c7235 | 4422 | if (!need_emergency_restart && |
b823821f | 4423 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 4424 | amdgpu_ras_suspend(tmp_adev); |
4425 | ||
1d721ed6 AG |
4426 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4427 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4428 | ||
4429 | if (!ring || !ring->sched.thread) | |
4430 | continue; | |
4431 | ||
0b2d2c2e | 4432 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 4433 | |
bb5c7235 | 4434 | if (need_emergency_restart) |
7c6e68c7 | 4435 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 AG |
4436 | } |
4437 | } | |
4438 | ||
bb5c7235 | 4439 | if (need_emergency_restart) |
7c6e68c7 AG |
4440 | goto skip_sched_resume; |
4441 | ||
1d721ed6 AG |
4442 | /* |
4443 | * Must check guilty signal here since after this point all old | |
4444 | * HW fences are force signaled. | |
4445 | * | |
4446 | * job->base holds a reference to parent fence | |
4447 | */ | |
4448 | if (job && job->base.s_fence->parent && | |
7dd8c205 | 4449 | dma_fence_is_signaled(job->base.s_fence->parent)) { |
1d721ed6 | 4450 | job_signaled = true; |
1d721ed6 AG |
4451 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
4452 | goto skip_hw_reset; | |
4453 | } | |
4454 | ||
26bc5340 AG |
4455 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
4456 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
26bc5340 AG |
4457 | r = amdgpu_device_pre_asic_reset(tmp_adev, |
4458 | NULL, | |
4459 | &need_full_reset); | |
4460 | /*TODO Should we stop ?*/ | |
4461 | if (r) { | |
aac89168 | 4462 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 4463 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
4464 | tmp_adev->asic_reset_res = r; |
4465 | } | |
4466 | } | |
4467 | ||
4468 | /* Actual ASIC resets if needed.*/ | |
4469 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
4470 | if (amdgpu_sriov_vf(adev)) { | |
4471 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
4472 | if (r) | |
4473 | adev->asic_reset_res = r; | |
4474 | } else { | |
041a62bc | 4475 | r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset); |
26bc5340 AG |
4476 | if (r && r == -EAGAIN) |
4477 | goto retry; | |
4478 | } | |
4479 | ||
1d721ed6 AG |
4480 | skip_hw_reset: |
4481 | ||
26bc5340 AG |
4482 | /* Post ASIC reset for all devs .*/ |
4483 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
7c6e68c7 | 4484 | |
1d721ed6 AG |
4485 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4486 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4487 | ||
4488 | if (!ring || !ring->sched.thread) | |
4489 | continue; | |
4490 | ||
4491 | /* No point to resubmit jobs if we didn't HW reset*/ | |
4492 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
4493 | drm_sched_resubmit_jobs(&ring->sched); | |
4494 | ||
4495 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
4496 | } | |
4497 | ||
4498 | if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) { | |
4a580877 | 4499 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
4500 | } |
4501 | ||
4502 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
4503 | |
4504 | if (r) { | |
4505 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 4506 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
4507 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
4508 | } else { | |
12ffa55d | 4509 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 | 4510 | } |
7c6e68c7 | 4511 | } |
26bc5340 | 4512 | |
7c6e68c7 AG |
4513 | skip_sched_resume: |
4514 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
4515 | /*unlock kfd: SRIOV would do it separately */ | |
bb5c7235 | 4516 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
7c6e68c7 | 4517 | amdgpu_amdkfd_post_reset(tmp_adev); |
3f12acc8 EQ |
4518 | if (audio_suspended) |
4519 | amdgpu_device_resume_display_audio(tmp_adev); | |
26bc5340 AG |
4520 | amdgpu_device_unlock_adev(tmp_adev); |
4521 | } | |
4522 | ||
cbfd17f7 | 4523 | skip_recovery: |
9e94d22c | 4524 | if (hive) { |
53b3f8f4 | 4525 | atomic_set(&hive->in_reset, 0); |
9e94d22c | 4526 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 4527 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 4528 | } |
26bc5340 AG |
4529 | |
4530 | if (r) | |
4531 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); | |
d38ceaf9 AD |
4532 | return r; |
4533 | } | |
4534 | ||
e3ecdffa AD |
4535 | /** |
4536 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
4537 | * | |
4538 | * @adev: amdgpu_device pointer | |
4539 | * | |
4540 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
4541 | * and lanes) of the slot the device is in. Handles APUs and | |
4542 | * virtualized environments where PCIE config space may not be available. | |
4543 | */ | |
5494d864 | 4544 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 4545 | { |
5d9a6330 | 4546 | struct pci_dev *pdev; |
c5313457 HK |
4547 | enum pci_bus_speed speed_cap, platform_speed_cap; |
4548 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 4549 | |
cd474ba0 AD |
4550 | if (amdgpu_pcie_gen_cap) |
4551 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 4552 | |
cd474ba0 AD |
4553 | if (amdgpu_pcie_lane_cap) |
4554 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 4555 | |
cd474ba0 AD |
4556 | /* covers APUs as well */ |
4557 | if (pci_is_root_bus(adev->pdev->bus)) { | |
4558 | if (adev->pm.pcie_gen_mask == 0) | |
4559 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
4560 | if (adev->pm.pcie_mlw_mask == 0) | |
4561 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 4562 | return; |
cd474ba0 | 4563 | } |
d0dd7f0c | 4564 | |
c5313457 HK |
4565 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
4566 | return; | |
4567 | ||
dbaa922b AD |
4568 | pcie_bandwidth_available(adev->pdev, NULL, |
4569 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 4570 | |
cd474ba0 | 4571 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
4572 | /* asic caps */ |
4573 | pdev = adev->pdev; | |
4574 | speed_cap = pcie_get_speed_cap(pdev); | |
4575 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
4576 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
4577 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
4578 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 4579 | } else { |
5d9a6330 AD |
4580 | if (speed_cap == PCIE_SPEED_16_0GT) |
4581 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4582 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4583 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4584 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
4585 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
4586 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4587 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4588 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
4589 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
4590 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4591 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4592 | else | |
4593 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4594 | } | |
4595 | /* platform caps */ | |
c5313457 | 4596 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
4597 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4598 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4599 | } else { | |
c5313457 | 4600 | if (platform_speed_cap == PCIE_SPEED_16_0GT) |
5d9a6330 AD |
4601 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4602 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4603 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4604 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 4605 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
4606 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4607 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4608 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 4609 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
4610 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4611 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4612 | else | |
4613 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4614 | ||
cd474ba0 AD |
4615 | } |
4616 | } | |
4617 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 4618 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
4619 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
4620 | } else { | |
c5313457 | 4621 | switch (platform_link_width) { |
5d9a6330 | 4622 | case PCIE_LNK_X32: |
cd474ba0 AD |
4623 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
4624 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
4625 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
4626 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4627 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4628 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4629 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4630 | break; | |
5d9a6330 | 4631 | case PCIE_LNK_X16: |
cd474ba0 AD |
4632 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
4633 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
4634 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4635 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4636 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4637 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4638 | break; | |
5d9a6330 | 4639 | case PCIE_LNK_X12: |
cd474ba0 AD |
4640 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
4641 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4642 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4643 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4644 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4645 | break; | |
5d9a6330 | 4646 | case PCIE_LNK_X8: |
cd474ba0 AD |
4647 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
4648 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4649 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4650 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4651 | break; | |
5d9a6330 | 4652 | case PCIE_LNK_X4: |
cd474ba0 AD |
4653 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
4654 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4655 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4656 | break; | |
5d9a6330 | 4657 | case PCIE_LNK_X2: |
cd474ba0 AD |
4658 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
4659 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4660 | break; | |
5d9a6330 | 4661 | case PCIE_LNK_X1: |
cd474ba0 AD |
4662 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
4663 | break; | |
4664 | default: | |
4665 | break; | |
4666 | } | |
d0dd7f0c AD |
4667 | } |
4668 | } | |
4669 | } | |
d38ceaf9 | 4670 | |
361dbd01 AD |
4671 | int amdgpu_device_baco_enter(struct drm_device *dev) |
4672 | { | |
1348969a | 4673 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 4674 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 4675 | |
4a580877 | 4676 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
4677 | return -ENOTSUPP; |
4678 | ||
7a22677b LM |
4679 | if (ras && ras->supported) |
4680 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); | |
4681 | ||
9530273e | 4682 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
4683 | } |
4684 | ||
4685 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
4686 | { | |
1348969a | 4687 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 4688 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 4689 | int ret = 0; |
361dbd01 | 4690 | |
4a580877 | 4691 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
4692 | return -ENOTSUPP; |
4693 | ||
9530273e EQ |
4694 | ret = amdgpu_dpm_baco_exit(adev); |
4695 | if (ret) | |
4696 | return ret; | |
7a22677b LM |
4697 | |
4698 | if (ras && ras->supported) | |
4699 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); | |
4700 | ||
4701 | return 0; | |
361dbd01 | 4702 | } |