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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
d38ceaf9 | 56 | |
e2a75f88 | 57 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 58 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 59 | |
2dc80b00 S |
60 | #define AMDGPU_RESUME_MS 2000 |
61 | ||
d38ceaf9 AD |
62 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
63 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
64 | ||
65 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
66 | "TAHITI", |
67 | "PITCAIRN", | |
68 | "VERDE", | |
69 | "OLAND", | |
70 | "HAINAN", | |
d38ceaf9 AD |
71 | "BONAIRE", |
72 | "KAVERI", | |
73 | "KABINI", | |
74 | "HAWAII", | |
75 | "MULLINS", | |
76 | "TOPAZ", | |
77 | "TONGA", | |
48299f95 | 78 | "FIJI", |
d38ceaf9 | 79 | "CARRIZO", |
139f4917 | 80 | "STONEY", |
2cc0c0b5 FC |
81 | "POLARIS10", |
82 | "POLARIS11", | |
c4642a47 | 83 | "POLARIS12", |
d4196f01 | 84 | "VEGA10", |
2ca8a5d2 | 85 | "RAVEN", |
d38ceaf9 AD |
86 | "LAST", |
87 | }; | |
88 | ||
89 | bool amdgpu_device_is_px(struct drm_device *dev) | |
90 | { | |
91 | struct amdgpu_device *adev = dev->dev_private; | |
92 | ||
2f7d10b3 | 93 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
94 | return true; |
95 | return false; | |
96 | } | |
97 | ||
98 | /* | |
99 | * MMIO register access helper functions. | |
100 | */ | |
101 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 102 | uint32_t acc_flags) |
d38ceaf9 | 103 | { |
f4b373f4 TSD |
104 | uint32_t ret; |
105 | ||
15d72fd7 | 106 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
107 | BUG_ON(in_interrupt()); |
108 | return amdgpu_virt_kiq_rreg(adev, reg); | |
109 | } | |
110 | ||
15d72fd7 | 111 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 112 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
113 | else { |
114 | unsigned long flags; | |
d38ceaf9 AD |
115 | |
116 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
117 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
118 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
119 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 120 | } |
f4b373f4 TSD |
121 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
122 | return ret; | |
d38ceaf9 AD |
123 | } |
124 | ||
125 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 126 | uint32_t acc_flags) |
d38ceaf9 | 127 | { |
f4b373f4 | 128 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 129 | |
15d72fd7 | 130 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
131 | BUG_ON(in_interrupt()); |
132 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
133 | } | |
134 | ||
15d72fd7 | 135 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
136 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
137 | else { | |
138 | unsigned long flags; | |
139 | ||
140 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
141 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
142 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
143 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
144 | } | |
145 | } | |
146 | ||
147 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
148 | { | |
149 | if ((reg * 4) < adev->rio_mem_size) | |
150 | return ioread32(adev->rio_mem + (reg * 4)); | |
151 | else { | |
152 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
153 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
154 | } | |
155 | } | |
156 | ||
157 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
158 | { | |
159 | ||
160 | if ((reg * 4) < adev->rio_mem_size) | |
161 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
162 | else { | |
163 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
164 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
165 | } | |
166 | } | |
167 | ||
168 | /** | |
169 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
170 | * | |
171 | * @adev: amdgpu_device pointer | |
172 | * @index: doorbell index | |
173 | * | |
174 | * Returns the value in the doorbell aperture at the | |
175 | * requested doorbell index (CIK). | |
176 | */ | |
177 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
178 | { | |
179 | if (index < adev->doorbell.num_doorbells) { | |
180 | return readl(adev->doorbell.ptr + index); | |
181 | } else { | |
182 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
183 | return 0; | |
184 | } | |
185 | } | |
186 | ||
187 | /** | |
188 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
189 | * | |
190 | * @adev: amdgpu_device pointer | |
191 | * @index: doorbell index | |
192 | * @v: value to write | |
193 | * | |
194 | * Writes @v to the doorbell aperture at the | |
195 | * requested doorbell index (CIK). | |
196 | */ | |
197 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
198 | { | |
199 | if (index < adev->doorbell.num_doorbells) { | |
200 | writel(v, adev->doorbell.ptr + index); | |
201 | } else { | |
202 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
203 | } | |
204 | } | |
205 | ||
832be404 KW |
206 | /** |
207 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
208 | * | |
209 | * @adev: amdgpu_device pointer | |
210 | * @index: doorbell index | |
211 | * | |
212 | * Returns the value in the doorbell aperture at the | |
213 | * requested doorbell index (VEGA10+). | |
214 | */ | |
215 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
216 | { | |
217 | if (index < adev->doorbell.num_doorbells) { | |
218 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
219 | } else { | |
220 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
221 | return 0; | |
222 | } | |
223 | } | |
224 | ||
225 | /** | |
226 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
227 | * | |
228 | * @adev: amdgpu_device pointer | |
229 | * @index: doorbell index | |
230 | * @v: value to write | |
231 | * | |
232 | * Writes @v to the doorbell aperture at the | |
233 | * requested doorbell index (VEGA10+). | |
234 | */ | |
235 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
236 | { | |
237 | if (index < adev->doorbell.num_doorbells) { | |
238 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
239 | } else { | |
240 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
241 | } | |
242 | } | |
243 | ||
d38ceaf9 AD |
244 | /** |
245 | * amdgpu_invalid_rreg - dummy reg read function | |
246 | * | |
247 | * @adev: amdgpu device pointer | |
248 | * @reg: offset of register | |
249 | * | |
250 | * Dummy register read function. Used for register blocks | |
251 | * that certain asics don't have (all asics). | |
252 | * Returns the value in the register. | |
253 | */ | |
254 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
255 | { | |
256 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
257 | BUG(); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | /** | |
262 | * amdgpu_invalid_wreg - dummy reg write function | |
263 | * | |
264 | * @adev: amdgpu device pointer | |
265 | * @reg: offset of register | |
266 | * @v: value to write to the register | |
267 | * | |
268 | * Dummy register read function. Used for register blocks | |
269 | * that certain asics don't have (all asics). | |
270 | */ | |
271 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
272 | { | |
273 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
274 | reg, v); | |
275 | BUG(); | |
276 | } | |
277 | ||
278 | /** | |
279 | * amdgpu_block_invalid_rreg - dummy reg read function | |
280 | * | |
281 | * @adev: amdgpu device pointer | |
282 | * @block: offset of instance | |
283 | * @reg: offset of register | |
284 | * | |
285 | * Dummy register read function. Used for register blocks | |
286 | * that certain asics don't have (all asics). | |
287 | * Returns the value in the register. | |
288 | */ | |
289 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
290 | uint32_t block, uint32_t reg) | |
291 | { | |
292 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
293 | reg, block); | |
294 | BUG(); | |
295 | return 0; | |
296 | } | |
297 | ||
298 | /** | |
299 | * amdgpu_block_invalid_wreg - dummy reg write function | |
300 | * | |
301 | * @adev: amdgpu device pointer | |
302 | * @block: offset of instance | |
303 | * @reg: offset of register | |
304 | * @v: value to write to the register | |
305 | * | |
306 | * Dummy register read function. Used for register blocks | |
307 | * that certain asics don't have (all asics). | |
308 | */ | |
309 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
310 | uint32_t block, | |
311 | uint32_t reg, uint32_t v) | |
312 | { | |
313 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
314 | reg, block, v); | |
315 | BUG(); | |
316 | } | |
317 | ||
318 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
319 | { | |
320 | int r; | |
321 | ||
322 | if (adev->vram_scratch.robj == NULL) { | |
323 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 324 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
325 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
326 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 327 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
328 | if (r) { |
329 | return r; | |
330 | } | |
331 | } | |
332 | ||
333 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
334 | if (unlikely(r != 0)) | |
335 | return r; | |
336 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
337 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
338 | if (r) { | |
339 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
340 | return r; | |
341 | } | |
342 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
343 | (void **)&adev->vram_scratch.ptr); | |
344 | if (r) | |
345 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
346 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
347 | ||
348 | return r; | |
349 | } | |
350 | ||
351 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
352 | { | |
353 | int r; | |
354 | ||
355 | if (adev->vram_scratch.robj == NULL) { | |
356 | return; | |
357 | } | |
8ab25b4f | 358 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, true); |
d38ceaf9 AD |
359 | if (likely(r == 0)) { |
360 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
361 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
362 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
363 | } | |
364 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
365 | } | |
366 | ||
367 | /** | |
368 | * amdgpu_program_register_sequence - program an array of registers. | |
369 | * | |
370 | * @adev: amdgpu_device pointer | |
371 | * @registers: pointer to the register array | |
372 | * @array_size: size of the register array | |
373 | * | |
374 | * Programs an array or registers with and and or masks. | |
375 | * This is a helper for setting golden registers. | |
376 | */ | |
377 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
378 | const u32 *registers, | |
379 | const u32 array_size) | |
380 | { | |
381 | u32 tmp, reg, and_mask, or_mask; | |
382 | int i; | |
383 | ||
384 | if (array_size % 3) | |
385 | return; | |
386 | ||
387 | for (i = 0; i < array_size; i +=3) { | |
388 | reg = registers[i + 0]; | |
389 | and_mask = registers[i + 1]; | |
390 | or_mask = registers[i + 2]; | |
391 | ||
392 | if (and_mask == 0xffffffff) { | |
393 | tmp = or_mask; | |
394 | } else { | |
395 | tmp = RREG32(reg); | |
396 | tmp &= ~and_mask; | |
397 | tmp |= or_mask; | |
398 | } | |
399 | WREG32(reg, tmp); | |
400 | } | |
401 | } | |
402 | ||
403 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
404 | { | |
405 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
406 | } | |
407 | ||
408 | /* | |
409 | * GPU doorbell aperture helpers function. | |
410 | */ | |
411 | /** | |
412 | * amdgpu_doorbell_init - Init doorbell driver information. | |
413 | * | |
414 | * @adev: amdgpu_device pointer | |
415 | * | |
416 | * Init doorbell driver information (CIK) | |
417 | * Returns 0 on success, error on failure. | |
418 | */ | |
419 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
420 | { | |
421 | /* doorbell bar mapping */ | |
422 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
423 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
424 | ||
edf600da | 425 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
426 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
427 | if (adev->doorbell.num_doorbells == 0) | |
428 | return -EINVAL; | |
429 | ||
8972e5d2 CK |
430 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
431 | adev->doorbell.num_doorbells * | |
432 | sizeof(u32)); | |
433 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 434 | return -ENOMEM; |
d38ceaf9 AD |
435 | |
436 | return 0; | |
437 | } | |
438 | ||
439 | /** | |
440 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
441 | * | |
442 | * @adev: amdgpu_device pointer | |
443 | * | |
444 | * Tear down doorbell driver information (CIK) | |
445 | */ | |
446 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
447 | { | |
448 | iounmap(adev->doorbell.ptr); | |
449 | adev->doorbell.ptr = NULL; | |
450 | } | |
451 | ||
452 | /** | |
453 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
454 | * setup amdkfd | |
455 | * | |
456 | * @adev: amdgpu_device pointer | |
457 | * @aperture_base: output returning doorbell aperture base physical address | |
458 | * @aperture_size: output returning doorbell aperture size in bytes | |
459 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
460 | * | |
461 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
462 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
463 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
464 | */ | |
465 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
466 | phys_addr_t *aperture_base, | |
467 | size_t *aperture_size, | |
468 | size_t *start_offset) | |
469 | { | |
470 | /* | |
471 | * The first num_doorbells are used by amdgpu. | |
472 | * amdkfd takes whatever's left in the aperture. | |
473 | */ | |
474 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
475 | *aperture_base = adev->doorbell.base; | |
476 | *aperture_size = adev->doorbell.size; | |
477 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
478 | } else { | |
479 | *aperture_base = 0; | |
480 | *aperture_size = 0; | |
481 | *start_offset = 0; | |
482 | } | |
483 | } | |
484 | ||
485 | /* | |
486 | * amdgpu_wb_*() | |
455a7bc2 | 487 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 488 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
489 | */ |
490 | ||
491 | /** | |
492 | * amdgpu_wb_fini - Disable Writeback and free memory | |
493 | * | |
494 | * @adev: amdgpu_device pointer | |
495 | * | |
496 | * Disables Writeback and frees the Writeback memory (all asics). | |
497 | * Used at driver shutdown. | |
498 | */ | |
499 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
500 | { | |
501 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
502 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
503 | &adev->wb.gpu_addr, | |
504 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
505 | adev->wb.wb_obj = NULL; |
506 | } | |
507 | } | |
508 | ||
509 | /** | |
510 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
511 | * | |
512 | * @adev: amdgpu_device pointer | |
513 | * | |
455a7bc2 | 514 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
515 | * Used at driver startup. |
516 | * Returns 0 on success or an -error on failure. | |
517 | */ | |
518 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
519 | { | |
520 | int r; | |
521 | ||
522 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 523 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
524 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
525 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
526 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
527 | if (r) { |
528 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
529 | return r; | |
530 | } | |
d38ceaf9 AD |
531 | |
532 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
533 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
534 | ||
535 | /* clear wb memory */ | |
60a970a6 | 536 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
537 | } |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | /** | |
543 | * amdgpu_wb_get - Allocate a wb entry | |
544 | * | |
545 | * @adev: amdgpu_device pointer | |
546 | * @wb: wb index | |
547 | * | |
548 | * Allocate a wb slot for use by the driver (all asics). | |
549 | * Returns 0 on success or -EINVAL on failure. | |
550 | */ | |
551 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
552 | { | |
553 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
554 | if (offset < adev->wb.num_wb) { | |
555 | __set_bit(offset, adev->wb.used); | |
556 | *wb = offset; | |
557 | return 0; | |
558 | } else { | |
559 | return -EINVAL; | |
560 | } | |
561 | } | |
562 | ||
7014285a KW |
563 | /** |
564 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
565 | * | |
566 | * @adev: amdgpu_device pointer | |
567 | * @wb: wb index | |
568 | * | |
569 | * Allocate a wb slot for use by the driver (all asics). | |
570 | * Returns 0 on success or -EINVAL on failure. | |
571 | */ | |
572 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
573 | { | |
574 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
575 | adev->wb.num_wb, 0, 2, 7, 0); | |
576 | if ((offset + 1) < adev->wb.num_wb) { | |
577 | __set_bit(offset, adev->wb.used); | |
578 | __set_bit(offset + 1, adev->wb.used); | |
579 | *wb = offset; | |
580 | return 0; | |
581 | } else { | |
582 | return -EINVAL; | |
583 | } | |
584 | } | |
585 | ||
d38ceaf9 AD |
586 | /** |
587 | * amdgpu_wb_free - Free a wb entry | |
588 | * | |
589 | * @adev: amdgpu_device pointer | |
590 | * @wb: wb index | |
591 | * | |
592 | * Free a wb slot allocated for use by the driver (all asics) | |
593 | */ | |
594 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
595 | { | |
596 | if (wb < adev->wb.num_wb) | |
597 | __clear_bit(wb, adev->wb.used); | |
598 | } | |
599 | ||
7014285a KW |
600 | /** |
601 | * amdgpu_wb_free_64bit - Free a wb entry | |
602 | * | |
603 | * @adev: amdgpu_device pointer | |
604 | * @wb: wb index | |
605 | * | |
606 | * Free a wb slot allocated for use by the driver (all asics) | |
607 | */ | |
608 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
609 | { | |
610 | if ((wb + 1) < adev->wb.num_wb) { | |
611 | __clear_bit(wb, adev->wb.used); | |
612 | __clear_bit(wb + 1, adev->wb.used); | |
613 | } | |
614 | } | |
615 | ||
d38ceaf9 AD |
616 | /** |
617 | * amdgpu_vram_location - try to find VRAM location | |
618 | * @adev: amdgpu device structure holding all necessary informations | |
619 | * @mc: memory controller structure holding memory informations | |
620 | * @base: base address at which to put VRAM | |
621 | * | |
455a7bc2 | 622 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
623 | * as parameter (which is so far either PCI aperture address or |
624 | * for IGP TOM base address). | |
625 | * | |
626 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
627 | * address space then we limit the VRAM size to the aperture. | |
628 | * | |
629 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
630 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
631 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
632 | * not IGP. | |
633 | * | |
634 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
635 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
636 | * Novell bug 204882 + along with lots of ubuntu ones | |
637 | * | |
638 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
639 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
640 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
641 | * ones) | |
642 | * | |
643 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 644 | * explicitly check for that though. |
d38ceaf9 AD |
645 | * |
646 | * FIXME: when reducing VRAM size align new size on power of 2. | |
647 | */ | |
648 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
649 | { | |
650 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
651 | ||
652 | mc->vram_start = base; | |
653 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
654 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
655 | mc->real_vram_size = mc->aper_size; | |
656 | mc->mc_vram_size = mc->aper_size; | |
657 | } | |
658 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
659 | if (limit && limit < mc->real_vram_size) | |
660 | mc->real_vram_size = limit; | |
661 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
662 | mc->mc_vram_size >> 20, mc->vram_start, | |
663 | mc->vram_end, mc->real_vram_size >> 20); | |
664 | } | |
665 | ||
666 | /** | |
667 | * amdgpu_gtt_location - try to find GTT location | |
668 | * @adev: amdgpu device structure holding all necessary informations | |
669 | * @mc: memory controller structure holding memory informations | |
670 | * | |
671 | * Function will place try to place GTT before or after VRAM. | |
672 | * | |
673 | * If GTT size is bigger than space left then we ajust GTT size. | |
674 | * Thus function will never fails. | |
675 | * | |
676 | * FIXME: when reducing GTT size align new size on power of 2. | |
677 | */ | |
678 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
679 | { | |
680 | u64 size_af, size_bf; | |
681 | ||
682 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
683 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
684 | if (size_bf > size_af) { | |
685 | if (mc->gtt_size > size_bf) { | |
686 | dev_warn(adev->dev, "limiting GTT\n"); | |
687 | mc->gtt_size = size_bf; | |
688 | } | |
9dc5a91e | 689 | mc->gtt_start = 0; |
d38ceaf9 AD |
690 | } else { |
691 | if (mc->gtt_size > size_af) { | |
692 | dev_warn(adev->dev, "limiting GTT\n"); | |
693 | mc->gtt_size = size_af; | |
694 | } | |
695 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
696 | } | |
697 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
698 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
699 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
700 | } | |
701 | ||
702 | /* | |
703 | * GPU helpers function. | |
704 | */ | |
705 | /** | |
c836fec5 | 706 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
707 | * |
708 | * @adev: amdgpu_device pointer | |
709 | * | |
c836fec5 JQ |
710 | * Check if the asic has been initialized (all asics) at driver startup |
711 | * or post is needed if hw reset is performed. | |
712 | * Returns true if need or false if not. | |
d38ceaf9 | 713 | */ |
c836fec5 | 714 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
715 | { |
716 | uint32_t reg; | |
717 | ||
c836fec5 JQ |
718 | if (adev->has_hw_reset) { |
719 | adev->has_hw_reset = false; | |
720 | return true; | |
721 | } | |
d38ceaf9 | 722 | /* then check MEM_SIZE, in case the crtcs are off */ |
bbf282d8 | 723 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 | 724 | |
f2713e8c | 725 | if ((reg != 0) && (reg != 0xffffffff)) |
c836fec5 | 726 | return false; |
d38ceaf9 | 727 | |
c836fec5 | 728 | return true; |
d38ceaf9 AD |
729 | |
730 | } | |
731 | ||
bec86378 ML |
732 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
733 | { | |
734 | if (amdgpu_sriov_vf(adev)) | |
735 | return false; | |
736 | ||
737 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
738 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
739 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
740 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
741 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
742 | */ |
743 | if (adev->asic_type == CHIP_FIJI) { | |
744 | int err; | |
745 | uint32_t fw_ver; | |
746 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
747 | /* force vPost if error occured */ | |
748 | if (err) | |
749 | return true; | |
750 | ||
751 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
752 | if (fw_ver < 0x00160e00) |
753 | return true; | |
bec86378 | 754 | } |
bec86378 | 755 | } |
c836fec5 | 756 | return amdgpu_need_post(adev); |
bec86378 ML |
757 | } |
758 | ||
d38ceaf9 AD |
759 | /** |
760 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
761 | * | |
762 | * @adev: amdgpu_device pointer | |
763 | * | |
764 | * Allocate the dummy page used by the driver (all asics). | |
765 | * This dummy page is used by the driver as a filler for gart entries | |
766 | * when pages are taken out of the GART | |
767 | * Returns 0 on sucess, -ENOMEM on failure. | |
768 | */ | |
769 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
770 | { | |
771 | if (adev->dummy_page.page) | |
772 | return 0; | |
773 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
774 | if (adev->dummy_page.page == NULL) | |
775 | return -ENOMEM; | |
776 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
777 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
778 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
779 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
780 | __free_page(adev->dummy_page.page); | |
781 | adev->dummy_page.page = NULL; | |
782 | return -ENOMEM; | |
783 | } | |
784 | return 0; | |
785 | } | |
786 | ||
787 | /** | |
788 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
789 | * | |
790 | * @adev: amdgpu_device pointer | |
791 | * | |
792 | * Frees the dummy page used by the driver (all asics). | |
793 | */ | |
794 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
795 | { | |
796 | if (adev->dummy_page.page == NULL) | |
797 | return; | |
798 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
799 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
800 | __free_page(adev->dummy_page.page); | |
801 | adev->dummy_page.page = NULL; | |
802 | } | |
803 | ||
804 | ||
805 | /* ATOM accessor methods */ | |
806 | /* | |
807 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
808 | * driver registers callbacks to access registers and the interpreter | |
809 | * in the driver parses the tables and executes then to program specific | |
810 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
811 | * atombios.h, and atom.c | |
812 | */ | |
813 | ||
814 | /** | |
815 | * cail_pll_read - read PLL register | |
816 | * | |
817 | * @info: atom card_info pointer | |
818 | * @reg: PLL register offset | |
819 | * | |
820 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
821 | * Returns the value of the PLL register. | |
822 | */ | |
823 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
824 | { | |
825 | return 0; | |
826 | } | |
827 | ||
828 | /** | |
829 | * cail_pll_write - write PLL register | |
830 | * | |
831 | * @info: atom card_info pointer | |
832 | * @reg: PLL register offset | |
833 | * @val: value to write to the pll register | |
834 | * | |
835 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
836 | */ | |
837 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
838 | { | |
839 | ||
840 | } | |
841 | ||
842 | /** | |
843 | * cail_mc_read - read MC (Memory Controller) register | |
844 | * | |
845 | * @info: atom card_info pointer | |
846 | * @reg: MC register offset | |
847 | * | |
848 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
849 | * Returns the value of the MC register. | |
850 | */ | |
851 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
852 | { | |
853 | return 0; | |
854 | } | |
855 | ||
856 | /** | |
857 | * cail_mc_write - write MC (Memory Controller) register | |
858 | * | |
859 | * @info: atom card_info pointer | |
860 | * @reg: MC register offset | |
861 | * @val: value to write to the pll register | |
862 | * | |
863 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
864 | */ | |
865 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
866 | { | |
867 | ||
868 | } | |
869 | ||
870 | /** | |
871 | * cail_reg_write - write MMIO register | |
872 | * | |
873 | * @info: atom card_info pointer | |
874 | * @reg: MMIO register offset | |
875 | * @val: value to write to the pll register | |
876 | * | |
877 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
878 | */ | |
879 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
880 | { | |
881 | struct amdgpu_device *adev = info->dev->dev_private; | |
882 | ||
883 | WREG32(reg, val); | |
884 | } | |
885 | ||
886 | /** | |
887 | * cail_reg_read - read MMIO register | |
888 | * | |
889 | * @info: atom card_info pointer | |
890 | * @reg: MMIO register offset | |
891 | * | |
892 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
893 | * Returns the value of the MMIO register. | |
894 | */ | |
895 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
896 | { | |
897 | struct amdgpu_device *adev = info->dev->dev_private; | |
898 | uint32_t r; | |
899 | ||
900 | r = RREG32(reg); | |
901 | return r; | |
902 | } | |
903 | ||
904 | /** | |
905 | * cail_ioreg_write - write IO register | |
906 | * | |
907 | * @info: atom card_info pointer | |
908 | * @reg: IO register offset | |
909 | * @val: value to write to the pll register | |
910 | * | |
911 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
912 | */ | |
913 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
914 | { | |
915 | struct amdgpu_device *adev = info->dev->dev_private; | |
916 | ||
917 | WREG32_IO(reg, val); | |
918 | } | |
919 | ||
920 | /** | |
921 | * cail_ioreg_read - read IO register | |
922 | * | |
923 | * @info: atom card_info pointer | |
924 | * @reg: IO register offset | |
925 | * | |
926 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
927 | * Returns the value of the IO register. | |
928 | */ | |
929 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
930 | { | |
931 | struct amdgpu_device *adev = info->dev->dev_private; | |
932 | uint32_t r; | |
933 | ||
934 | r = RREG32_IO(reg); | |
935 | return r; | |
936 | } | |
937 | ||
938 | /** | |
939 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
940 | * | |
941 | * @adev: amdgpu_device pointer | |
942 | * | |
943 | * Frees the driver info and register access callbacks for the ATOM | |
944 | * interpreter (r4xx+). | |
945 | * Called at driver shutdown. | |
946 | */ | |
947 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
948 | { | |
89e0ec9f | 949 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 950 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
951 | kfree(adev->mode_info.atom_context->iio); |
952 | } | |
d38ceaf9 AD |
953 | kfree(adev->mode_info.atom_context); |
954 | adev->mode_info.atom_context = NULL; | |
955 | kfree(adev->mode_info.atom_card_info); | |
956 | adev->mode_info.atom_card_info = NULL; | |
957 | } | |
958 | ||
959 | /** | |
960 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
961 | * | |
962 | * @adev: amdgpu_device pointer | |
963 | * | |
964 | * Initializes the driver info and register access callbacks for the | |
965 | * ATOM interpreter (r4xx+). | |
966 | * Returns 0 on sucess, -ENOMEM on failure. | |
967 | * Called at driver startup. | |
968 | */ | |
969 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
970 | { | |
971 | struct card_info *atom_card_info = | |
972 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
973 | ||
974 | if (!atom_card_info) | |
975 | return -ENOMEM; | |
976 | ||
977 | adev->mode_info.atom_card_info = atom_card_info; | |
978 | atom_card_info->dev = adev->ddev; | |
979 | atom_card_info->reg_read = cail_reg_read; | |
980 | atom_card_info->reg_write = cail_reg_write; | |
981 | /* needed for iio ops */ | |
982 | if (adev->rio_mem) { | |
983 | atom_card_info->ioreg_read = cail_ioreg_read; | |
984 | atom_card_info->ioreg_write = cail_ioreg_write; | |
985 | } else { | |
b64a18c5 | 986 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
987 | atom_card_info->ioreg_read = cail_reg_read; |
988 | atom_card_info->ioreg_write = cail_reg_write; | |
989 | } | |
990 | atom_card_info->mc_read = cail_mc_read; | |
991 | atom_card_info->mc_write = cail_mc_write; | |
992 | atom_card_info->pll_read = cail_pll_read; | |
993 | atom_card_info->pll_write = cail_pll_write; | |
994 | ||
995 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
996 | if (!adev->mode_info.atom_context) { | |
997 | amdgpu_atombios_fini(adev); | |
998 | return -ENOMEM; | |
999 | } | |
1000 | ||
1001 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1002 | if (adev->is_atom_fw) { |
1003 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1004 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1005 | } else { | |
1006 | amdgpu_atombios_scratch_regs_init(adev); | |
1007 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1008 | } | |
d38ceaf9 AD |
1009 | return 0; |
1010 | } | |
1011 | ||
1012 | /* if we get transitioned to only one device, take VGA back */ | |
1013 | /** | |
1014 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1015 | * | |
1016 | * @cookie: amdgpu_device pointer | |
1017 | * @state: enable/disable vga decode | |
1018 | * | |
1019 | * Enable/disable vga decode (all asics). | |
1020 | * Returns VGA resource flags. | |
1021 | */ | |
1022 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1023 | { | |
1024 | struct amdgpu_device *adev = cookie; | |
1025 | amdgpu_asic_set_vga_state(adev, state); | |
1026 | if (state) | |
1027 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1028 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1029 | else | |
1030 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1031 | } | |
1032 | ||
1033 | /** | |
1034 | * amdgpu_check_pot_argument - check that argument is a power of two | |
1035 | * | |
1036 | * @arg: value to check | |
1037 | * | |
1038 | * Validates that a certain argument is a power of two (all asics). | |
1039 | * Returns true if argument is valid. | |
1040 | */ | |
1041 | static bool amdgpu_check_pot_argument(int arg) | |
1042 | { | |
1043 | return (arg & (arg - 1)) == 0; | |
1044 | } | |
1045 | ||
bab4fee7 | 1046 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1047 | { |
1048 | /* defines number of bits in page table versus page directory, | |
1049 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1050 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1051 | if (amdgpu_vm_block_size == -1) |
1052 | return; | |
a1adf8be | 1053 | |
bab4fee7 | 1054 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1055 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1056 | amdgpu_vm_block_size); | |
bab4fee7 | 1057 | goto def_value; |
a1adf8be CZ |
1058 | } |
1059 | ||
1060 | if (amdgpu_vm_block_size > 24 || | |
1061 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1062 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1063 | amdgpu_vm_block_size); | |
bab4fee7 | 1064 | goto def_value; |
a1adf8be | 1065 | } |
bab4fee7 JZ |
1066 | |
1067 | return; | |
1068 | ||
1069 | def_value: | |
1070 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1071 | } |
1072 | ||
83ca145d ZJ |
1073 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1074 | { | |
1075 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
1076 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
1077 | amdgpu_vm_size); | |
1078 | goto def_value; | |
1079 | } | |
1080 | ||
1081 | if (amdgpu_vm_size < 1) { | |
1082 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1083 | amdgpu_vm_size); | |
1084 | goto def_value; | |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1089 | */ | |
1090 | if (amdgpu_vm_size > 1024) { | |
1091 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1092 | amdgpu_vm_size); | |
1093 | goto def_value; | |
1094 | } | |
1095 | ||
1096 | return; | |
1097 | ||
1098 | def_value: | |
bab4fee7 | 1099 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1100 | } |
1101 | ||
d38ceaf9 AD |
1102 | /** |
1103 | * amdgpu_check_arguments - validate module params | |
1104 | * | |
1105 | * @adev: amdgpu_device pointer | |
1106 | * | |
1107 | * Validates certain module parameters and updates | |
1108 | * the associated values used by the driver (all asics). | |
1109 | */ | |
1110 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1111 | { | |
5b011235 CZ |
1112 | if (amdgpu_sched_jobs < 4) { |
1113 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1114 | amdgpu_sched_jobs); | |
1115 | amdgpu_sched_jobs = 4; | |
1116 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
1117 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
1118 | amdgpu_sched_jobs); | |
1119 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1120 | } | |
d38ceaf9 AD |
1121 | |
1122 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 1123 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
1124 | if (amdgpu_gart_size < 32) { |
1125 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1126 | amdgpu_gart_size); | |
1127 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
1128 | } |
1129 | } | |
1130 | ||
83ca145d | 1131 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1132 | |
bab4fee7 | 1133 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1134 | |
526bae37 | 1135 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
1136 | !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { | |
6a7f76e7 CK |
1137 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1138 | amdgpu_vram_page_split); | |
1139 | amdgpu_vram_page_split = 1024; | |
1140 | } | |
d38ceaf9 AD |
1141 | } |
1142 | ||
1143 | /** | |
1144 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1145 | * | |
1146 | * @pdev: pci dev pointer | |
1694467b | 1147 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1148 | * |
1149 | * Callback for the switcheroo driver. Suspends or resumes the | |
1150 | * the asics before or after it is powered up using ACPI methods. | |
1151 | */ | |
1152 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1153 | { | |
1154 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1155 | ||
1156 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1157 | return; | |
1158 | ||
1159 | if (state == VGA_SWITCHEROO_ON) { | |
1160 | unsigned d3_delay = dev->pdev->d3_delay; | |
1161 | ||
7ca85295 | 1162 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1163 | /* don't suspend or resume card normally */ |
1164 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1165 | ||
810ddc3a | 1166 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1167 | |
1168 | dev->pdev->d3_delay = d3_delay; | |
1169 | ||
1170 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1171 | drm_kms_helper_poll_enable(dev); | |
1172 | } else { | |
7ca85295 | 1173 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1174 | drm_kms_helper_poll_disable(dev); |
1175 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1176 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1177 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1178 | } | |
1179 | } | |
1180 | ||
1181 | /** | |
1182 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1183 | * | |
1184 | * @pdev: pci dev pointer | |
1185 | * | |
1186 | * Callback for the switcheroo driver. Check of the switcheroo | |
1187 | * state can be changed. | |
1188 | * Returns true if the state can be changed, false if not. | |
1189 | */ | |
1190 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1191 | { | |
1192 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1193 | ||
1194 | /* | |
1195 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1196 | * locking inversion with the driver load path. And the access here is | |
1197 | * completely racy anyway. So don't bother with locking for now. | |
1198 | */ | |
1199 | return dev->open_count == 0; | |
1200 | } | |
1201 | ||
1202 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1203 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1204 | .reprobe = NULL, | |
1205 | .can_switch = amdgpu_switcheroo_can_switch, | |
1206 | }; | |
1207 | ||
1208 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1209 | enum amd_ip_block_type block_type, |
1210 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1211 | { |
1212 | int i, r = 0; | |
1213 | ||
1214 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1215 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1216 | continue; |
c722865a RZ |
1217 | if (adev->ip_blocks[i].version->type != block_type) |
1218 | continue; | |
1219 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1220 | continue; | |
1221 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1222 | (void *)adev, state); | |
1223 | if (r) | |
1224 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1225 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1226 | } |
1227 | return r; | |
1228 | } | |
1229 | ||
1230 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1231 | enum amd_ip_block_type block_type, |
1232 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1233 | { |
1234 | int i, r = 0; | |
1235 | ||
1236 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1237 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1238 | continue; |
c722865a RZ |
1239 | if (adev->ip_blocks[i].version->type != block_type) |
1240 | continue; | |
1241 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1242 | continue; | |
1243 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1244 | (void *)adev, state); | |
1245 | if (r) | |
1246 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1247 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1248 | } |
1249 | return r; | |
1250 | } | |
1251 | ||
6cb2d4e4 HR |
1252 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1253 | { | |
1254 | int i; | |
1255 | ||
1256 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1257 | if (!adev->ip_blocks[i].status.valid) | |
1258 | continue; | |
1259 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1260 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1261 | } | |
1262 | } | |
1263 | ||
5dbbb60b AD |
1264 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1265 | enum amd_ip_block_type block_type) | |
1266 | { | |
1267 | int i, r; | |
1268 | ||
1269 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1270 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1271 | continue; |
a1255107 AD |
1272 | if (adev->ip_blocks[i].version->type == block_type) { |
1273 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1274 | if (r) |
1275 | return r; | |
1276 | break; | |
1277 | } | |
1278 | } | |
1279 | return 0; | |
1280 | ||
1281 | } | |
1282 | ||
1283 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1284 | enum amd_ip_block_type block_type) | |
1285 | { | |
1286 | int i; | |
1287 | ||
1288 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1289 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1290 | continue; |
a1255107 AD |
1291 | if (adev->ip_blocks[i].version->type == block_type) |
1292 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1293 | } |
1294 | return true; | |
1295 | ||
1296 | } | |
1297 | ||
a1255107 AD |
1298 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1299 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1300 | { |
1301 | int i; | |
1302 | ||
1303 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1304 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1305 | return &adev->ip_blocks[i]; |
1306 | ||
1307 | return NULL; | |
1308 | } | |
1309 | ||
1310 | /** | |
1311 | * amdgpu_ip_block_version_cmp | |
1312 | * | |
1313 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1314 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1315 | * @major: major version |
1316 | * @minor: minor version | |
1317 | * | |
1318 | * return 0 if equal or greater | |
1319 | * return 1 if smaller or the ip_block doesn't exist | |
1320 | */ | |
1321 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1322 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1323 | u32 major, u32 minor) |
1324 | { | |
a1255107 | 1325 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1326 | |
a1255107 AD |
1327 | if (ip_block && ((ip_block->version->major > major) || |
1328 | ((ip_block->version->major == major) && | |
1329 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1330 | return 0; |
1331 | ||
1332 | return 1; | |
1333 | } | |
1334 | ||
a1255107 AD |
1335 | /** |
1336 | * amdgpu_ip_block_add | |
1337 | * | |
1338 | * @adev: amdgpu_device pointer | |
1339 | * @ip_block_version: pointer to the IP to add | |
1340 | * | |
1341 | * Adds the IP block driver information to the collection of IPs | |
1342 | * on the asic. | |
1343 | */ | |
1344 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1345 | const struct amdgpu_ip_block_version *ip_block_version) | |
1346 | { | |
1347 | if (!ip_block_version) | |
1348 | return -EINVAL; | |
1349 | ||
a0bae357 HR |
1350 | DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, |
1351 | ip_block_version->funcs->name); | |
1352 | ||
a1255107 AD |
1353 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
483ef985 | 1358 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1359 | { |
1360 | adev->enable_virtual_display = false; | |
1361 | ||
1362 | if (amdgpu_virtual_display) { | |
1363 | struct drm_device *ddev = adev->ddev; | |
1364 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1365 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1366 | |
1367 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1368 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1369 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1370 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1371 | if (!strcmp("all", pciaddname) |
1372 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1373 | long num_crtc; |
1374 | int res = -1; | |
1375 | ||
9accf2fd | 1376 | adev->enable_virtual_display = true; |
0f66356d ED |
1377 | |
1378 | if (pciaddname_tmp) | |
1379 | res = kstrtol(pciaddname_tmp, 10, | |
1380 | &num_crtc); | |
1381 | ||
1382 | if (!res) { | |
1383 | if (num_crtc < 1) | |
1384 | num_crtc = 1; | |
1385 | if (num_crtc > 6) | |
1386 | num_crtc = 6; | |
1387 | adev->mode_info.num_crtc = num_crtc; | |
1388 | } else { | |
1389 | adev->mode_info.num_crtc = 1; | |
1390 | } | |
9accf2fd ED |
1391 | break; |
1392 | } | |
1393 | } | |
1394 | ||
0f66356d ED |
1395 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1396 | amdgpu_virtual_display, pci_address_name, | |
1397 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1398 | |
1399 | kfree(pciaddstr); | |
1400 | } | |
1401 | } | |
1402 | ||
e2a75f88 AD |
1403 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1404 | { | |
1405 | const struct firmware *fw; | |
1406 | const char *chip_name; | |
1407 | char fw_name[30]; | |
1408 | int err; | |
1409 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1410 | ||
1411 | switch (adev->asic_type) { | |
1412 | case CHIP_TOPAZ: | |
1413 | case CHIP_TONGA: | |
1414 | case CHIP_FIJI: | |
1415 | case CHIP_POLARIS11: | |
1416 | case CHIP_POLARIS10: | |
1417 | case CHIP_POLARIS12: | |
1418 | case CHIP_CARRIZO: | |
1419 | case CHIP_STONEY: | |
1420 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1421 | case CHIP_VERDE: | |
1422 | case CHIP_TAHITI: | |
1423 | case CHIP_PITCAIRN: | |
1424 | case CHIP_OLAND: | |
1425 | case CHIP_HAINAN: | |
1426 | #endif | |
1427 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1428 | case CHIP_BONAIRE: | |
1429 | case CHIP_HAWAII: | |
1430 | case CHIP_KAVERI: | |
1431 | case CHIP_KABINI: | |
1432 | case CHIP_MULLINS: | |
1433 | #endif | |
1434 | default: | |
1435 | return 0; | |
1436 | case CHIP_VEGA10: | |
1437 | chip_name = "vega10"; | |
1438 | break; | |
2d2e5e7e AD |
1439 | case CHIP_RAVEN: |
1440 | chip_name = "raven"; | |
1441 | break; | |
e2a75f88 AD |
1442 | } |
1443 | ||
1444 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
1445 | err = request_firmware(&fw, fw_name, adev->dev); | |
1446 | if (err) { | |
1447 | dev_err(adev->dev, | |
1448 | "Failed to load gpu_info firmware \"%s\"\n", | |
1449 | fw_name); | |
1450 | goto out; | |
1451 | } | |
1452 | err = amdgpu_ucode_validate(fw); | |
1453 | if (err) { | |
1454 | dev_err(adev->dev, | |
1455 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1456 | fw_name); | |
1457 | goto out; | |
1458 | } | |
1459 | ||
1460 | hdr = (const struct gpu_info_firmware_header_v1_0 *)fw->data; | |
1461 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); | |
1462 | ||
1463 | switch (hdr->version_major) { | |
1464 | case 1: | |
1465 | { | |
1466 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
1467 | (const struct gpu_info_firmware_v1_0 *)(fw->data + | |
1468 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1469 | ||
b5ab16bf AD |
1470 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1471 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1472 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1473 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1474 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1475 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1476 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1477 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1478 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1479 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1480 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1481 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1482 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
e2a75f88 AD |
1483 | break; |
1484 | } | |
1485 | default: | |
1486 | dev_err(adev->dev, | |
1487 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1488 | err = -EINVAL; | |
1489 | goto out; | |
1490 | } | |
1491 | out: | |
1492 | release_firmware(fw); | |
1493 | fw = NULL; | |
1494 | ||
1495 | return err; | |
1496 | } | |
1497 | ||
d38ceaf9 AD |
1498 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1499 | { | |
aaa36a97 | 1500 | int i, r; |
d38ceaf9 | 1501 | |
483ef985 | 1502 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1503 | |
d38ceaf9 | 1504 | switch (adev->asic_type) { |
aaa36a97 AD |
1505 | case CHIP_TOPAZ: |
1506 | case CHIP_TONGA: | |
48299f95 | 1507 | case CHIP_FIJI: |
2cc0c0b5 FC |
1508 | case CHIP_POLARIS11: |
1509 | case CHIP_POLARIS10: | |
c4642a47 | 1510 | case CHIP_POLARIS12: |
aaa36a97 | 1511 | case CHIP_CARRIZO: |
39bb0c92 SL |
1512 | case CHIP_STONEY: |
1513 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1514 | adev->family = AMDGPU_FAMILY_CZ; |
1515 | else | |
1516 | adev->family = AMDGPU_FAMILY_VI; | |
1517 | ||
1518 | r = vi_set_ip_blocks(adev); | |
1519 | if (r) | |
1520 | return r; | |
1521 | break; | |
33f34802 KW |
1522 | #ifdef CONFIG_DRM_AMDGPU_SI |
1523 | case CHIP_VERDE: | |
1524 | case CHIP_TAHITI: | |
1525 | case CHIP_PITCAIRN: | |
1526 | case CHIP_OLAND: | |
1527 | case CHIP_HAINAN: | |
295d0daf | 1528 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1529 | r = si_set_ip_blocks(adev); |
1530 | if (r) | |
1531 | return r; | |
1532 | break; | |
1533 | #endif | |
a2e73f56 AD |
1534 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1535 | case CHIP_BONAIRE: | |
1536 | case CHIP_HAWAII: | |
1537 | case CHIP_KAVERI: | |
1538 | case CHIP_KABINI: | |
1539 | case CHIP_MULLINS: | |
1540 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1541 | adev->family = AMDGPU_FAMILY_CI; | |
1542 | else | |
1543 | adev->family = AMDGPU_FAMILY_KV; | |
1544 | ||
1545 | r = cik_set_ip_blocks(adev); | |
1546 | if (r) | |
1547 | return r; | |
1548 | break; | |
1549 | #endif | |
2ca8a5d2 CZ |
1550 | case CHIP_VEGA10: |
1551 | case CHIP_RAVEN: | |
1552 | if (adev->asic_type == CHIP_RAVEN) | |
1553 | adev->family = AMDGPU_FAMILY_RV; | |
1554 | else | |
1555 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1556 | |
1557 | r = soc15_set_ip_blocks(adev); | |
1558 | if (r) | |
1559 | return r; | |
1560 | break; | |
d38ceaf9 AD |
1561 | default: |
1562 | /* FIXME: not supported yet */ | |
1563 | return -EINVAL; | |
1564 | } | |
1565 | ||
e2a75f88 AD |
1566 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1567 | if (r) | |
1568 | return r; | |
1569 | ||
3149d9da XY |
1570 | if (amdgpu_sriov_vf(adev)) { |
1571 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1572 | if (r) | |
1573 | return r; | |
1574 | } | |
1575 | ||
d38ceaf9 AD |
1576 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1577 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1578 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1579 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1580 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1581 | } else { |
a1255107 AD |
1582 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1583 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1584 | if (r == -ENOENT) { |
a1255107 | 1585 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1586 | } else if (r) { |
a1255107 AD |
1587 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1588 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1589 | return r; |
2c1a2784 | 1590 | } else { |
a1255107 | 1591 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1592 | } |
974e6b64 | 1593 | } else { |
a1255107 | 1594 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1595 | } |
d38ceaf9 AD |
1596 | } |
1597 | } | |
1598 | ||
395d1fb9 NH |
1599 | adev->cg_flags &= amdgpu_cg_mask; |
1600 | adev->pg_flags &= amdgpu_pg_mask; | |
1601 | ||
d38ceaf9 AD |
1602 | return 0; |
1603 | } | |
1604 | ||
1605 | static int amdgpu_init(struct amdgpu_device *adev) | |
1606 | { | |
1607 | int i, r; | |
1608 | ||
1609 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1610 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1611 | continue; |
a1255107 | 1612 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1613 | if (r) { |
a1255107 AD |
1614 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1615 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1616 | return r; |
2c1a2784 | 1617 | } |
a1255107 | 1618 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1619 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1620 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1621 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1622 | if (r) { |
1623 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1624 | return r; |
2c1a2784 | 1625 | } |
a1255107 | 1626 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1627 | if (r) { |
1628 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1629 | return r; |
2c1a2784 | 1630 | } |
d38ceaf9 | 1631 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1632 | if (r) { |
1633 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1634 | return r; |
2c1a2784 | 1635 | } |
a1255107 | 1636 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1637 | |
1638 | /* right after GMC hw init, we create CSA */ | |
1639 | if (amdgpu_sriov_vf(adev)) { | |
1640 | r = amdgpu_allocate_static_csa(adev); | |
1641 | if (r) { | |
1642 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1643 | return r; | |
1644 | } | |
1645 | } | |
d38ceaf9 AD |
1646 | } |
1647 | } | |
1648 | ||
1649 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1650 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1651 | continue; |
1652 | /* gmc hw init is done early */ | |
a1255107 | 1653 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1654 | continue; |
a1255107 | 1655 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1656 | if (r) { |
a1255107 AD |
1657 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1658 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1659 | return r; |
2c1a2784 | 1660 | } |
a1255107 | 1661 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1662 | } |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
0c49e0b8 CZ |
1667 | static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) |
1668 | { | |
1669 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1670 | } | |
1671 | ||
1672 | static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) | |
1673 | { | |
1674 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1675 | AMDGPU_RESET_MAGIC_NUM); | |
1676 | } | |
1677 | ||
2dc80b00 | 1678 | static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1679 | { |
1680 | int i = 0, r; | |
1681 | ||
1682 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1683 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1684 | continue; |
4a446d55 | 1685 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1686 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1687 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1688 | /* enable clockgating to save power */ |
a1255107 AD |
1689 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1690 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1691 | if (r) { |
1692 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1693 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1694 | return r; |
1695 | } | |
b0b00ff1 | 1696 | } |
d38ceaf9 | 1697 | } |
2dc80b00 S |
1698 | return 0; |
1699 | } | |
1700 | ||
1701 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1702 | { | |
1703 | int i = 0, r; | |
1704 | ||
1705 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1706 | if (!adev->ip_blocks[i].status.valid) | |
1707 | continue; | |
1708 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1709 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1710 | if (r) { | |
1711 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1712 | adev->ip_blocks[i].version->funcs->name, r); | |
1713 | return r; | |
1714 | } | |
1715 | adev->ip_blocks[i].status.late_initialized = true; | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1720 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1721 | |
0c49e0b8 CZ |
1722 | amdgpu_fill_reset_magic(adev); |
1723 | ||
d38ceaf9 AD |
1724 | return 0; |
1725 | } | |
1726 | ||
1727 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1728 | { | |
1729 | int i, r; | |
1730 | ||
3e96dbfd AD |
1731 | /* need to disable SMC first */ |
1732 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1733 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1734 | continue; |
a1255107 | 1735 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1736 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1737 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1738 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1739 | if (r) { |
1740 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1741 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1742 | return r; |
1743 | } | |
a1255107 | 1744 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1745 | /* XXX handle errors */ |
1746 | if (r) { | |
1747 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1748 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1749 | } |
a1255107 | 1750 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1751 | break; |
1752 | } | |
1753 | } | |
1754 | ||
d38ceaf9 | 1755 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1756 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1757 | continue; |
a1255107 | 1758 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1759 | amdgpu_wb_fini(adev); |
1760 | amdgpu_vram_scratch_fini(adev); | |
1761 | } | |
8201a67a RZ |
1762 | |
1763 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1764 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1765 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1766 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1767 | AMD_CG_STATE_UNGATE); | |
1768 | if (r) { | |
1769 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1770 | adev->ip_blocks[i].version->funcs->name, r); | |
1771 | return r; | |
1772 | } | |
2c1a2784 | 1773 | } |
8201a67a | 1774 | |
a1255107 | 1775 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1776 | /* XXX handle errors */ |
2c1a2784 | 1777 | if (r) { |
a1255107 AD |
1778 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1779 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1780 | } |
8201a67a | 1781 | |
a1255107 | 1782 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1783 | } |
1784 | ||
1785 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1786 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1787 | continue; |
a1255107 | 1788 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1789 | /* XXX handle errors */ |
2c1a2784 | 1790 | if (r) { |
a1255107 AD |
1791 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1792 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1793 | } |
a1255107 AD |
1794 | adev->ip_blocks[i].status.sw = false; |
1795 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1796 | } |
1797 | ||
a6dcfd9c | 1798 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1799 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1800 | continue; |
a1255107 AD |
1801 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1802 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1803 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1804 | } |
1805 | ||
3149d9da | 1806 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1807 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1808 | amdgpu_virt_release_full_gpu(adev, false); |
1809 | } | |
2493664f | 1810 | |
d38ceaf9 AD |
1811 | return 0; |
1812 | } | |
1813 | ||
2dc80b00 S |
1814 | static void amdgpu_late_init_func_handler(struct work_struct *work) |
1815 | { | |
1816 | struct amdgpu_device *adev = | |
1817 | container_of(work, struct amdgpu_device, late_init_work.work); | |
1818 | amdgpu_late_set_cg_state(adev); | |
1819 | } | |
1820 | ||
faefba95 | 1821 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1822 | { |
1823 | int i, r; | |
1824 | ||
e941ea99 XY |
1825 | if (amdgpu_sriov_vf(adev)) |
1826 | amdgpu_virt_request_full_gpu(adev, false); | |
1827 | ||
c5a93a28 FC |
1828 | /* ungate SMC block first */ |
1829 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1830 | AMD_CG_STATE_UNGATE); | |
1831 | if (r) { | |
1832 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1833 | } | |
1834 | ||
d38ceaf9 | 1835 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1836 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1837 | continue; |
1838 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1839 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1840 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1841 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1842 | if (r) { |
a1255107 AD |
1843 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1844 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1845 | } |
2c1a2784 | 1846 | } |
d38ceaf9 | 1847 | /* XXX handle errors */ |
a1255107 | 1848 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1849 | /* XXX handle errors */ |
2c1a2784 | 1850 | if (r) { |
a1255107 AD |
1851 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1852 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1853 | } |
d38ceaf9 AD |
1854 | } |
1855 | ||
e941ea99 XY |
1856 | if (amdgpu_sriov_vf(adev)) |
1857 | amdgpu_virt_release_full_gpu(adev, false); | |
1858 | ||
d38ceaf9 AD |
1859 | return 0; |
1860 | } | |
1861 | ||
e4f0fdcc | 1862 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1863 | { |
1864 | int i, r; | |
1865 | ||
2cb681b6 ML |
1866 | static enum amd_ip_block_type ip_order[] = { |
1867 | AMD_IP_BLOCK_TYPE_GMC, | |
1868 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1869 | AMD_IP_BLOCK_TYPE_IH, |
1870 | }; | |
1871 | ||
1872 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { | |
1873 | int j; | |
1874 | struct amdgpu_ip_block *block; | |
1875 | ||
1876 | for (j = 0; j < adev->num_ip_blocks; j++) { | |
1877 | block = &adev->ip_blocks[j]; | |
1878 | ||
1879 | if (block->version->type != ip_order[i] || | |
1880 | !block->status.valid) | |
1881 | continue; | |
1882 | ||
1883 | r = block->version->funcs->hw_init(adev); | |
1884 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1885 | } |
1886 | } | |
1887 | ||
1888 | return 0; | |
1889 | } | |
1890 | ||
e4f0fdcc | 1891 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1892 | { |
1893 | int i, r; | |
1894 | ||
2cb681b6 ML |
1895 | static enum amd_ip_block_type ip_order[] = { |
1896 | AMD_IP_BLOCK_TYPE_SMC, | |
1897 | AMD_IP_BLOCK_TYPE_DCE, | |
1898 | AMD_IP_BLOCK_TYPE_GFX, | |
1899 | AMD_IP_BLOCK_TYPE_SDMA, | |
1900 | AMD_IP_BLOCK_TYPE_VCE, | |
1901 | }; | |
a90ad3c2 | 1902 | |
2cb681b6 ML |
1903 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1904 | int j; | |
1905 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1906 | |
2cb681b6 ML |
1907 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1908 | block = &adev->ip_blocks[j]; | |
1909 | ||
1910 | if (block->version->type != ip_order[i] || | |
1911 | !block->status.valid) | |
1912 | continue; | |
1913 | ||
1914 | r = block->version->funcs->hw_init(adev); | |
1915 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1916 | } |
1917 | } | |
1918 | ||
1919 | return 0; | |
1920 | } | |
1921 | ||
fcf0649f | 1922 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1923 | { |
1924 | int i, r; | |
1925 | ||
1926 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1927 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1928 | continue; |
fcf0649f CZ |
1929 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1930 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1931 | adev->ip_blocks[i].version->type == | |
1932 | AMD_IP_BLOCK_TYPE_IH) { | |
1933 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1934 | if (r) { | |
1935 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1936 | adev->ip_blocks[i].version->funcs->name, r); | |
1937 | return r; | |
1938 | } | |
1939 | } | |
1940 | } | |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | ||
1945 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) | |
1946 | { | |
1947 | int i, r; | |
1948 | ||
1949 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1950 | if (!adev->ip_blocks[i].status.valid) | |
1951 | continue; | |
1952 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1953 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1954 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1955 | continue; | |
a1255107 | 1956 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1957 | if (r) { |
a1255107 AD |
1958 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1959 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1960 | return r; |
2c1a2784 | 1961 | } |
d38ceaf9 AD |
1962 | } |
1963 | ||
1964 | return 0; | |
1965 | } | |
1966 | ||
fcf0649f CZ |
1967 | static int amdgpu_resume(struct amdgpu_device *adev) |
1968 | { | |
1969 | int r; | |
1970 | ||
1971 | r = amdgpu_resume_phase1(adev); | |
1972 | if (r) | |
1973 | return r; | |
1974 | r = amdgpu_resume_phase2(adev); | |
1975 | ||
1976 | return r; | |
1977 | } | |
1978 | ||
4e99a44e | 1979 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1980 | { |
a5bde2f9 AD |
1981 | if (adev->is_atom_fw) { |
1982 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
1983 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1984 | } else { | |
1985 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
1986 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1987 | } | |
048765ad AR |
1988 | } |
1989 | ||
d38ceaf9 AD |
1990 | /** |
1991 | * amdgpu_device_init - initialize the driver | |
1992 | * | |
1993 | * @adev: amdgpu_device pointer | |
1994 | * @pdev: drm dev pointer | |
1995 | * @pdev: pci dev pointer | |
1996 | * @flags: driver flags | |
1997 | * | |
1998 | * Initializes the driver info and hw (all asics). | |
1999 | * Returns 0 for success or an error on failure. | |
2000 | * Called at driver startup. | |
2001 | */ | |
2002 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2003 | struct drm_device *ddev, | |
2004 | struct pci_dev *pdev, | |
2005 | uint32_t flags) | |
2006 | { | |
2007 | int r, i; | |
2008 | bool runtime = false; | |
95844d20 | 2009 | u32 max_MBps; |
d38ceaf9 AD |
2010 | |
2011 | adev->shutdown = false; | |
2012 | adev->dev = &pdev->dev; | |
2013 | adev->ddev = ddev; | |
2014 | adev->pdev = pdev; | |
2015 | adev->flags = flags; | |
2f7d10b3 | 2016 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
2017 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
2018 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
2019 | adev->accel_working = false; | |
2020 | adev->num_rings = 0; | |
2021 | adev->mman.buffer_funcs = NULL; | |
2022 | adev->mman.buffer_funcs_ring = NULL; | |
2023 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2024 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 2025 | adev->gart.gart_funcs = NULL; |
f54d1867 | 2026 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
2027 | |
2028 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2029 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2030 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2031 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2032 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2033 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2034 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2035 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2036 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2037 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2038 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2039 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2040 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2041 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2042 | ||
ccdbb20a | 2043 | |
3e39ab90 AD |
2044 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2045 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2046 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2047 | |
2048 | /* mutex initialization are all done here so we | |
2049 | * can recall function without having locking issues */ | |
d38ceaf9 | 2050 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2051 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2052 | mutex_init(&adev->pm.mutex); |
2053 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2054 | mutex_init(&adev->srbm_mutex); | |
2055 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
2056 | mutex_init(&adev->mn_lock); |
2057 | hash_init(adev->mn_hash); | |
2058 | ||
2059 | amdgpu_check_arguments(adev); | |
2060 | ||
2061 | /* Registers mapping */ | |
2062 | /* TODO: block userspace mapping of io register */ | |
2063 | spin_lock_init(&adev->mmio_idx_lock); | |
2064 | spin_lock_init(&adev->smc_idx_lock); | |
2065 | spin_lock_init(&adev->pcie_idx_lock); | |
2066 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2067 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2068 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 2069 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2070 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2071 | |
0c4e7fa5 CZ |
2072 | INIT_LIST_HEAD(&adev->shadow_list); |
2073 | mutex_init(&adev->shadow_list_lock); | |
2074 | ||
5c1354bd CZ |
2075 | INIT_LIST_HEAD(&adev->gtt_list); |
2076 | spin_lock_init(&adev->gtt_list_lock); | |
2077 | ||
795f2813 AR |
2078 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2079 | spin_lock_init(&adev->ring_lru_list_lock); | |
2080 | ||
2dc80b00 S |
2081 | INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); |
2082 | ||
da69c161 KW |
2083 | if (adev->asic_type >= CHIP_BONAIRE) { |
2084 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2085 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2086 | } else { | |
2087 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2088 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2089 | } | |
d38ceaf9 | 2090 | |
d38ceaf9 AD |
2091 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2092 | if (adev->rmmio == NULL) { | |
2093 | return -ENOMEM; | |
2094 | } | |
2095 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2096 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2097 | ||
da69c161 KW |
2098 | if (adev->asic_type >= CHIP_BONAIRE) |
2099 | /* doorbell bar mapping */ | |
2100 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2101 | |
2102 | /* io port mapping */ | |
2103 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2104 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2105 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2106 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2107 | break; | |
2108 | } | |
2109 | } | |
2110 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2111 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2112 | |
2113 | /* early init functions */ | |
2114 | r = amdgpu_early_init(adev); | |
2115 | if (r) | |
2116 | return r; | |
2117 | ||
2118 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2119 | /* this will fail for cards that aren't VGA class devices, just | |
2120 | * ignore it */ | |
2121 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2122 | ||
2123 | if (amdgpu_runtime_pm == 1) | |
2124 | runtime = true; | |
e9bef455 | 2125 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2126 | runtime = true; |
84c8b22e LW |
2127 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2128 | vga_switcheroo_register_client(adev->pdev, | |
2129 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2130 | if (runtime) |
2131 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2132 | ||
2133 | /* Read BIOS */ | |
83ba126a AD |
2134 | if (!amdgpu_get_bios(adev)) { |
2135 | r = -EINVAL; | |
2136 | goto failed; | |
2137 | } | |
f7e9e9fe | 2138 | |
d38ceaf9 | 2139 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2140 | if (r) { |
2141 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 2142 | goto failed; |
2c1a2784 | 2143 | } |
d38ceaf9 | 2144 | |
4e99a44e ML |
2145 | /* detect if we are with an SRIOV vbios */ |
2146 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2147 | |
d38ceaf9 | 2148 | /* Post card if necessary */ |
bec86378 | 2149 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 2150 | if (!adev->bios) { |
bec86378 | 2151 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2152 | r = -EINVAL; |
2153 | goto failed; | |
d38ceaf9 | 2154 | } |
bec86378 | 2155 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2156 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2157 | if (r) { | |
2158 | dev_err(adev->dev, "gpu post error!\n"); | |
2159 | goto failed; | |
2160 | } | |
2161 | } else { | |
2162 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
2163 | } |
2164 | ||
a5bde2f9 AD |
2165 | if (!adev->is_atom_fw) { |
2166 | /* Initialize clocks */ | |
2167 | r = amdgpu_atombios_get_clock_info(adev); | |
2168 | if (r) { | |
2169 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
2170 | return r; | |
2171 | } | |
2172 | /* init i2c buses */ | |
2173 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2174 | } |
d38ceaf9 AD |
2175 | |
2176 | /* Fence driver */ | |
2177 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2178 | if (r) { |
2179 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 2180 | goto failed; |
2c1a2784 | 2181 | } |
d38ceaf9 AD |
2182 | |
2183 | /* init the mode config */ | |
2184 | drm_mode_config_init(adev->ddev); | |
2185 | ||
2186 | r = amdgpu_init(adev); | |
2187 | if (r) { | |
2c1a2784 | 2188 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 2189 | amdgpu_fini(adev); |
83ba126a | 2190 | goto failed; |
d38ceaf9 AD |
2191 | } |
2192 | ||
2193 | adev->accel_working = true; | |
2194 | ||
e59c0205 AX |
2195 | amdgpu_vm_check_compute_bug(adev); |
2196 | ||
95844d20 MO |
2197 | /* Initialize the buffer migration limit. */ |
2198 | if (amdgpu_moverate >= 0) | |
2199 | max_MBps = amdgpu_moverate; | |
2200 | else | |
2201 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2202 | /* Get a log2 for easy divisions. */ | |
2203 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2204 | ||
d38ceaf9 AD |
2205 | r = amdgpu_ib_pool_init(adev); |
2206 | if (r) { | |
2207 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 2208 | goto failed; |
d38ceaf9 AD |
2209 | } |
2210 | ||
2211 | r = amdgpu_ib_ring_tests(adev); | |
2212 | if (r) | |
2213 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2214 | ||
9bc92b9c ML |
2215 | amdgpu_fbdev_init(adev); |
2216 | ||
d38ceaf9 | 2217 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2218 | if (r) |
d38ceaf9 | 2219 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2220 | |
2221 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2222 | if (r) |
d38ceaf9 | 2223 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2224 | |
50ab2533 | 2225 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2226 | if (r) |
50ab2533 | 2227 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2228 | |
d38ceaf9 AD |
2229 | if ((amdgpu_testing & 1)) { |
2230 | if (adev->accel_working) | |
2231 | amdgpu_test_moves(adev); | |
2232 | else | |
2233 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2234 | } | |
d38ceaf9 AD |
2235 | if (amdgpu_benchmarking) { |
2236 | if (adev->accel_working) | |
2237 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2238 | else | |
2239 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2240 | } | |
2241 | ||
2242 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2243 | * explicit gating rather than handling it automatically. | |
2244 | */ | |
2245 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2246 | if (r) { |
2247 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 2248 | goto failed; |
2c1a2784 | 2249 | } |
d38ceaf9 AD |
2250 | |
2251 | return 0; | |
83ba126a AD |
2252 | |
2253 | failed: | |
2254 | if (runtime) | |
2255 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2256 | return r; | |
d38ceaf9 AD |
2257 | } |
2258 | ||
d38ceaf9 AD |
2259 | /** |
2260 | * amdgpu_device_fini - tear down the driver | |
2261 | * | |
2262 | * @adev: amdgpu_device pointer | |
2263 | * | |
2264 | * Tear down the driver info (all asics). | |
2265 | * Called at driver shutdown. | |
2266 | */ | |
2267 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2268 | { | |
2269 | int r; | |
2270 | ||
2271 | DRM_INFO("amdgpu: finishing device.\n"); | |
2272 | adev->shutdown = true; | |
db2c2a97 PD |
2273 | if (adev->mode_info.mode_config_initialized) |
2274 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2275 | /* evict vram memory */ |
2276 | amdgpu_bo_evict_vram(adev); | |
2277 | amdgpu_ib_pool_fini(adev); | |
2278 | amdgpu_fence_driver_fini(adev); | |
2279 | amdgpu_fbdev_fini(adev); | |
2280 | r = amdgpu_fini(adev); | |
d38ceaf9 | 2281 | adev->accel_working = false; |
2dc80b00 | 2282 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 AD |
2283 | /* free i2c buses */ |
2284 | amdgpu_i2c_fini(adev); | |
2285 | amdgpu_atombios_fini(adev); | |
2286 | kfree(adev->bios); | |
2287 | adev->bios = NULL; | |
84c8b22e LW |
2288 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2289 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2290 | if (adev->flags & AMD_IS_PX) |
2291 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2292 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2293 | if (adev->rio_mem) | |
2294 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2295 | adev->rio_mem = NULL; | |
2296 | iounmap(adev->rmmio); | |
2297 | adev->rmmio = NULL; | |
da69c161 KW |
2298 | if (adev->asic_type >= CHIP_BONAIRE) |
2299 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2300 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2301 | } |
2302 | ||
2303 | ||
2304 | /* | |
2305 | * Suspend & resume. | |
2306 | */ | |
2307 | /** | |
810ddc3a | 2308 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2309 | * |
2310 | * @pdev: drm dev pointer | |
2311 | * @state: suspend state | |
2312 | * | |
2313 | * Puts the hw in the suspend state (all asics). | |
2314 | * Returns 0 for success or an error on failure. | |
2315 | * Called at driver suspend. | |
2316 | */ | |
810ddc3a | 2317 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2318 | { |
2319 | struct amdgpu_device *adev; | |
2320 | struct drm_crtc *crtc; | |
2321 | struct drm_connector *connector; | |
5ceb54c6 | 2322 | int r; |
d38ceaf9 AD |
2323 | |
2324 | if (dev == NULL || dev->dev_private == NULL) { | |
2325 | return -ENODEV; | |
2326 | } | |
2327 | ||
2328 | adev = dev->dev_private; | |
2329 | ||
2330 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2331 | return 0; | |
2332 | ||
2333 | drm_kms_helper_poll_disable(dev); | |
2334 | ||
2335 | /* turn off display hw */ | |
4c7fbc39 | 2336 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2337 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2338 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2339 | } | |
4c7fbc39 | 2340 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2341 | |
756e6880 | 2342 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2343 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2344 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2345 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2346 | struct amdgpu_bo *robj; | |
2347 | ||
756e6880 AD |
2348 | if (amdgpu_crtc->cursor_bo) { |
2349 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2350 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2351 | if (r == 0) { |
2352 | amdgpu_bo_unpin(aobj); | |
2353 | amdgpu_bo_unreserve(aobj); | |
2354 | } | |
2355 | } | |
2356 | ||
d38ceaf9 AD |
2357 | if (rfb == NULL || rfb->obj == NULL) { |
2358 | continue; | |
2359 | } | |
2360 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2361 | /* don't unpin kernel fb objects */ | |
2362 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2363 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2364 | if (r == 0) { |
2365 | amdgpu_bo_unpin(robj); | |
2366 | amdgpu_bo_unreserve(robj); | |
2367 | } | |
2368 | } | |
2369 | } | |
2370 | /* evict vram memory */ | |
2371 | amdgpu_bo_evict_vram(adev); | |
2372 | ||
5ceb54c6 | 2373 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2374 | |
2375 | r = amdgpu_suspend(adev); | |
2376 | ||
a0a71e49 AD |
2377 | /* evict remaining vram memory |
2378 | * This second call to evict vram is to evict the gart page table | |
2379 | * using the CPU. | |
2380 | */ | |
d38ceaf9 AD |
2381 | amdgpu_bo_evict_vram(adev); |
2382 | ||
be34d3bf AD |
2383 | if (adev->is_atom_fw) |
2384 | amdgpu_atomfirmware_scratch_regs_save(adev); | |
2385 | else | |
2386 | amdgpu_atombios_scratch_regs_save(adev); | |
d38ceaf9 AD |
2387 | pci_save_state(dev->pdev); |
2388 | if (suspend) { | |
2389 | /* Shut down the device */ | |
2390 | pci_disable_device(dev->pdev); | |
2391 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2392 | } else { |
2393 | r = amdgpu_asic_reset(adev); | |
2394 | if (r) | |
2395 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2396 | } |
2397 | ||
2398 | if (fbcon) { | |
2399 | console_lock(); | |
2400 | amdgpu_fbdev_set_suspend(adev, 1); | |
2401 | console_unlock(); | |
2402 | } | |
2403 | return 0; | |
2404 | } | |
2405 | ||
2406 | /** | |
810ddc3a | 2407 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2408 | * |
2409 | * @pdev: drm dev pointer | |
2410 | * | |
2411 | * Bring the hw back to operating state (all asics). | |
2412 | * Returns 0 for success or an error on failure. | |
2413 | * Called at driver resume. | |
2414 | */ | |
810ddc3a | 2415 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2416 | { |
2417 | struct drm_connector *connector; | |
2418 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2419 | struct drm_crtc *crtc; |
03161a6e | 2420 | int r = 0; |
d38ceaf9 AD |
2421 | |
2422 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2423 | return 0; | |
2424 | ||
74b0b157 | 2425 | if (fbcon) |
d38ceaf9 | 2426 | console_lock(); |
74b0b157 | 2427 | |
d38ceaf9 AD |
2428 | if (resume) { |
2429 | pci_set_power_state(dev->pdev, PCI_D0); | |
2430 | pci_restore_state(dev->pdev); | |
74b0b157 | 2431 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2432 | if (r) |
2433 | goto unlock; | |
d38ceaf9 | 2434 | } |
be34d3bf AD |
2435 | if (adev->is_atom_fw) |
2436 | amdgpu_atomfirmware_scratch_regs_restore(adev); | |
2437 | else | |
2438 | amdgpu_atombios_scratch_regs_restore(adev); | |
d38ceaf9 AD |
2439 | |
2440 | /* post card */ | |
c836fec5 | 2441 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2442 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2443 | if (r) | |
2444 | DRM_ERROR("amdgpu asic init failed\n"); | |
2445 | } | |
d38ceaf9 AD |
2446 | |
2447 | r = amdgpu_resume(adev); | |
e6707218 | 2448 | if (r) { |
ca198528 | 2449 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2450 | goto unlock; |
e6707218 | 2451 | } |
5ceb54c6 AD |
2452 | amdgpu_fence_driver_resume(adev); |
2453 | ||
ca198528 FC |
2454 | if (resume) { |
2455 | r = amdgpu_ib_ring_tests(adev); | |
2456 | if (r) | |
2457 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2458 | } | |
d38ceaf9 AD |
2459 | |
2460 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2461 | if (r) |
2462 | goto unlock; | |
d38ceaf9 | 2463 | |
756e6880 AD |
2464 | /* pin cursors */ |
2465 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2466 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2467 | ||
2468 | if (amdgpu_crtc->cursor_bo) { | |
2469 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2470 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2471 | if (r == 0) { |
2472 | r = amdgpu_bo_pin(aobj, | |
2473 | AMDGPU_GEM_DOMAIN_VRAM, | |
2474 | &amdgpu_crtc->cursor_addr); | |
2475 | if (r != 0) | |
2476 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2477 | amdgpu_bo_unreserve(aobj); | |
2478 | } | |
2479 | } | |
2480 | } | |
2481 | ||
d38ceaf9 AD |
2482 | /* blat the mode back in */ |
2483 | if (fbcon) { | |
2484 | drm_helper_resume_force_mode(dev); | |
2485 | /* turn on display hw */ | |
4c7fbc39 | 2486 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2487 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2488 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2489 | } | |
4c7fbc39 | 2490 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2491 | } |
2492 | ||
2493 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2494 | |
2495 | /* | |
2496 | * Most of the connector probing functions try to acquire runtime pm | |
2497 | * refs to ensure that the GPU is powered on when connector polling is | |
2498 | * performed. Since we're calling this from a runtime PM callback, | |
2499 | * trying to acquire rpm refs will cause us to deadlock. | |
2500 | * | |
2501 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2502 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2503 | */ | |
2504 | #ifdef CONFIG_PM | |
2505 | dev->dev->power.disable_depth++; | |
2506 | #endif | |
54fb2a5c | 2507 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2508 | #ifdef CONFIG_PM |
2509 | dev->dev->power.disable_depth--; | |
2510 | #endif | |
d38ceaf9 | 2511 | |
03161a6e | 2512 | if (fbcon) |
d38ceaf9 | 2513 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2514 | |
2515 | unlock: | |
2516 | if (fbcon) | |
d38ceaf9 | 2517 | console_unlock(); |
d38ceaf9 | 2518 | |
03161a6e | 2519 | return r; |
d38ceaf9 AD |
2520 | } |
2521 | ||
63fbf42f CZ |
2522 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2523 | { | |
2524 | int i; | |
2525 | bool asic_hang = false; | |
2526 | ||
2527 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2528 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2529 | continue; |
a1255107 AD |
2530 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2531 | adev->ip_blocks[i].status.hang = | |
2532 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2533 | if (adev->ip_blocks[i].status.hang) { | |
2534 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2535 | asic_hang = true; |
2536 | } | |
2537 | } | |
2538 | return asic_hang; | |
2539 | } | |
2540 | ||
4d446656 | 2541 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2542 | { |
2543 | int i, r = 0; | |
2544 | ||
2545 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2546 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2547 | continue; |
a1255107 AD |
2548 | if (adev->ip_blocks[i].status.hang && |
2549 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2550 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2551 | if (r) |
2552 | return r; | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | return 0; | |
2557 | } | |
2558 | ||
35d782fe CZ |
2559 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2560 | { | |
da146d3b AD |
2561 | int i; |
2562 | ||
2563 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2564 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2565 | continue; |
a1255107 AD |
2566 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2567 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2568 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2569 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2570 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2571 | DRM_INFO("Some block need full reset!\n"); |
2572 | return true; | |
2573 | } | |
2574 | } | |
35d782fe CZ |
2575 | } |
2576 | return false; | |
2577 | } | |
2578 | ||
2579 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2580 | { | |
2581 | int i, r = 0; | |
2582 | ||
2583 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2584 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2585 | continue; |
a1255107 AD |
2586 | if (adev->ip_blocks[i].status.hang && |
2587 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2588 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2589 | if (r) |
2590 | return r; | |
2591 | } | |
2592 | } | |
2593 | ||
2594 | return 0; | |
2595 | } | |
2596 | ||
2597 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2598 | { | |
2599 | int i, r = 0; | |
2600 | ||
2601 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2602 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2603 | continue; |
a1255107 AD |
2604 | if (adev->ip_blocks[i].status.hang && |
2605 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2606 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2607 | if (r) |
2608 | return r; | |
2609 | } | |
2610 | ||
2611 | return 0; | |
2612 | } | |
2613 | ||
3ad81f16 CZ |
2614 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2615 | { | |
2616 | if (adev->flags & AMD_IS_APU) | |
2617 | return false; | |
2618 | ||
2619 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2620 | } | |
2621 | ||
53cdccd5 CZ |
2622 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2623 | struct amdgpu_ring *ring, | |
2624 | struct amdgpu_bo *bo, | |
f54d1867 | 2625 | struct dma_fence **fence) |
53cdccd5 CZ |
2626 | { |
2627 | uint32_t domain; | |
2628 | int r; | |
2629 | ||
23d2e504 RH |
2630 | if (!bo->shadow) |
2631 | return 0; | |
2632 | ||
1d284797 | 2633 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2634 | if (r) |
2635 | return r; | |
2636 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2637 | /* if bo has been evicted, then no need to recover */ | |
2638 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2639 | r = amdgpu_bo_validate(bo->shadow); |
2640 | if (r) { | |
2641 | DRM_ERROR("bo validate failed!\n"); | |
2642 | goto err; | |
2643 | } | |
2644 | ||
2645 | r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem); | |
2646 | if (r) { | |
2647 | DRM_ERROR("%p bind failed\n", bo->shadow); | |
2648 | goto err; | |
2649 | } | |
2650 | ||
23d2e504 | 2651 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2652 | NULL, fence, true); |
23d2e504 RH |
2653 | if (r) { |
2654 | DRM_ERROR("recover page table failed!\n"); | |
2655 | goto err; | |
2656 | } | |
2657 | } | |
53cdccd5 | 2658 | err: |
23d2e504 RH |
2659 | amdgpu_bo_unreserve(bo); |
2660 | return r; | |
53cdccd5 CZ |
2661 | } |
2662 | ||
a90ad3c2 ML |
2663 | /** |
2664 | * amdgpu_sriov_gpu_reset - reset the asic | |
2665 | * | |
2666 | * @adev: amdgpu device pointer | |
7225f873 | 2667 | * @job: which job trigger hang |
a90ad3c2 ML |
2668 | * |
2669 | * Attempt the reset the GPU if it has hung (all asics). | |
2670 | * for SRIOV case. | |
2671 | * Returns 0 for success or an error on failure. | |
2672 | */ | |
7225f873 | 2673 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) |
a90ad3c2 | 2674 | { |
65781c78 | 2675 | int i, j, r = 0; |
a90ad3c2 ML |
2676 | int resched; |
2677 | struct amdgpu_bo *bo, *tmp; | |
2678 | struct amdgpu_ring *ring; | |
2679 | struct dma_fence *fence = NULL, *next = NULL; | |
2680 | ||
147b5983 | 2681 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2682 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2683 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2684 | |
2685 | /* block TTM */ | |
2686 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2687 | ||
65781c78 ML |
2688 | /* we start from the ring trigger GPU hang */ |
2689 | j = job ? job->ring->idx : 0; | |
a90ad3c2 | 2690 | |
65781c78 ML |
2691 | /* block scheduler */ |
2692 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { | |
2693 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2694 | if (!ring || !ring->sched.thread) |
2695 | continue; | |
2696 | ||
2697 | kthread_park(ring->sched.thread); | |
65781c78 ML |
2698 | |
2699 | if (job && j != i) | |
2700 | continue; | |
2701 | ||
4f059ecd | 2702 | /* here give the last chance to check if job removed from mirror-list |
65781c78 | 2703 | * since we already pay some time on kthread_park */ |
4f059ecd | 2704 | if (job && list_empty(&job->base.node)) { |
65781c78 ML |
2705 | kthread_unpark(ring->sched.thread); |
2706 | goto give_up_reset; | |
2707 | } | |
2708 | ||
2709 | if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) | |
2710 | amd_sched_job_kickout(&job->base); | |
2711 | ||
2712 | /* only do job_reset on the hang ring if @job not NULL */ | |
a90ad3c2 | 2713 | amd_sched_hw_job_reset(&ring->sched); |
a90ad3c2 | 2714 | |
65781c78 ML |
2715 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2716 | amdgpu_fence_driver_force_completion_ring(ring); | |
2717 | } | |
a90ad3c2 ML |
2718 | |
2719 | /* request to take full control of GPU before re-initialization */ | |
7225f873 | 2720 | if (job) |
a90ad3c2 ML |
2721 | amdgpu_virt_reset_gpu(adev); |
2722 | else | |
2723 | amdgpu_virt_request_full_gpu(adev, true); | |
2724 | ||
2725 | ||
2726 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2727 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2728 | |
2729 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2730 | amdgpu_ttm_recover_gart(adev); | |
2731 | ||
2732 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2733 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2734 | |
2735 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2736 | ||
2737 | if (amdgpu_ib_ring_tests(adev)) | |
2738 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2739 | ||
2740 | /* release full control of GPU after ib test */ | |
2741 | amdgpu_virt_release_full_gpu(adev, true); | |
2742 | ||
2743 | DRM_INFO("recover vram bo from shadow\n"); | |
2744 | ||
2745 | ring = adev->mman.buffer_funcs_ring; | |
2746 | mutex_lock(&adev->shadow_list_lock); | |
2747 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2748 | next = NULL; |
a90ad3c2 ML |
2749 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2750 | if (fence) { | |
2751 | r = dma_fence_wait(fence, false); | |
2752 | if (r) { | |
2753 | WARN(r, "recovery from shadow isn't completed\n"); | |
2754 | break; | |
2755 | } | |
2756 | } | |
2757 | ||
2758 | dma_fence_put(fence); | |
2759 | fence = next; | |
2760 | } | |
2761 | mutex_unlock(&adev->shadow_list_lock); | |
2762 | ||
2763 | if (fence) { | |
2764 | r = dma_fence_wait(fence, false); | |
2765 | if (r) | |
2766 | WARN(r, "recovery from shadow isn't completed\n"); | |
2767 | } | |
2768 | dma_fence_put(fence); | |
2769 | ||
65781c78 ML |
2770 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { |
2771 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2772 | if (!ring || !ring->sched.thread) |
2773 | continue; | |
2774 | ||
65781c78 ML |
2775 | if (job && j != i) { |
2776 | kthread_unpark(ring->sched.thread); | |
2777 | continue; | |
2778 | } | |
2779 | ||
a90ad3c2 ML |
2780 | amd_sched_job_recovery(&ring->sched); |
2781 | kthread_unpark(ring->sched.thread); | |
2782 | } | |
2783 | ||
2784 | drm_helper_resume_force_mode(adev->ddev); | |
65781c78 | 2785 | give_up_reset: |
a90ad3c2 ML |
2786 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); |
2787 | if (r) { | |
2788 | /* bad news, how to tell it to userspace ? */ | |
2789 | dev_info(adev->dev, "GPU reset failed\n"); | |
65781c78 ML |
2790 | } else { |
2791 | dev_info(adev->dev, "GPU reset successed!\n"); | |
a90ad3c2 ML |
2792 | } |
2793 | ||
1fb37a3d | 2794 | adev->gfx.in_reset = false; |
147b5983 | 2795 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2796 | return r; |
2797 | } | |
2798 | ||
d38ceaf9 AD |
2799 | /** |
2800 | * amdgpu_gpu_reset - reset the asic | |
2801 | * | |
2802 | * @adev: amdgpu device pointer | |
2803 | * | |
2804 | * Attempt the reset the GPU if it has hung (all asics). | |
2805 | * Returns 0 for success or an error on failure. | |
2806 | */ | |
2807 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2808 | { | |
d38ceaf9 AD |
2809 | int i, r; |
2810 | int resched; | |
0c49e0b8 | 2811 | bool need_full_reset, vram_lost = false; |
d38ceaf9 | 2812 | |
63fbf42f CZ |
2813 | if (!amdgpu_check_soft_reset(adev)) { |
2814 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2815 | return 0; | |
2816 | } | |
d38ceaf9 | 2817 | |
d94aed5a | 2818 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2819 | |
a3c47d6b CZ |
2820 | /* block TTM */ |
2821 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2822 | ||
0875dc9e CZ |
2823 | /* block scheduler */ |
2824 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2825 | struct amdgpu_ring *ring = adev->rings[i]; | |
2826 | ||
51687759 | 2827 | if (!ring || !ring->sched.thread) |
0875dc9e CZ |
2828 | continue; |
2829 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2830 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2831 | } |
2200edac CZ |
2832 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2833 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2834 | |
35d782fe | 2835 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2836 | |
35d782fe CZ |
2837 | if (!need_full_reset) { |
2838 | amdgpu_pre_soft_reset(adev); | |
2839 | r = amdgpu_soft_reset(adev); | |
2840 | amdgpu_post_soft_reset(adev); | |
2841 | if (r || amdgpu_check_soft_reset(adev)) { | |
2842 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2843 | need_full_reset = true; | |
2844 | } | |
f1aa7e08 CZ |
2845 | } |
2846 | ||
35d782fe | 2847 | if (need_full_reset) { |
35d782fe | 2848 | r = amdgpu_suspend(adev); |
bfa99269 | 2849 | |
35d782fe CZ |
2850 | retry: |
2851 | /* Disable fb access */ | |
2852 | if (adev->mode_info.num_crtc) { | |
2853 | struct amdgpu_mode_mc_save save; | |
2854 | amdgpu_display_stop_mc_access(adev, &save); | |
2855 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
2856 | } | |
be34d3bf AD |
2857 | if (adev->is_atom_fw) |
2858 | amdgpu_atomfirmware_scratch_regs_save(adev); | |
2859 | else | |
2860 | amdgpu_atombios_scratch_regs_save(adev); | |
35d782fe | 2861 | r = amdgpu_asic_reset(adev); |
be34d3bf AD |
2862 | if (adev->is_atom_fw) |
2863 | amdgpu_atomfirmware_scratch_regs_restore(adev); | |
2864 | else | |
2865 | amdgpu_atombios_scratch_regs_restore(adev); | |
35d782fe CZ |
2866 | /* post card */ |
2867 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2868 | ||
2869 | if (!r) { | |
2870 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
fcf0649f CZ |
2871 | r = amdgpu_resume_phase1(adev); |
2872 | if (r) | |
2873 | goto out; | |
0c49e0b8 | 2874 | vram_lost = amdgpu_check_vram_lost(adev); |
f1892138 | 2875 | if (vram_lost) { |
0c49e0b8 | 2876 | DRM_ERROR("VRAM is lost!\n"); |
f1892138 CZ |
2877 | atomic_inc(&adev->vram_lost_counter); |
2878 | } | |
fcf0649f CZ |
2879 | r = amdgpu_ttm_recover_gart(adev); |
2880 | if (r) | |
2881 | goto out; | |
2882 | r = amdgpu_resume_phase2(adev); | |
2883 | if (r) | |
2884 | goto out; | |
0c49e0b8 CZ |
2885 | if (vram_lost) |
2886 | amdgpu_fill_reset_magic(adev); | |
35d782fe | 2887 | } |
d38ceaf9 | 2888 | } |
fcf0649f | 2889 | out: |
d38ceaf9 | 2890 | if (!r) { |
e72cfd58 | 2891 | amdgpu_irq_gpu_reset_resume_helper(adev); |
1f465087 CZ |
2892 | r = amdgpu_ib_ring_tests(adev); |
2893 | if (r) { | |
2894 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2895 | r = amdgpu_suspend(adev); |
53cdccd5 | 2896 | need_full_reset = true; |
40019dc4 | 2897 | goto retry; |
1f465087 | 2898 | } |
53cdccd5 CZ |
2899 | /** |
2900 | * recovery vm page tables, since we cannot depend on VRAM is | |
2901 | * consistent after gpu full reset. | |
2902 | */ | |
2903 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2904 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2905 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2906 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2907 | |
2908 | DRM_INFO("recover vram bo from shadow\n"); | |
2909 | mutex_lock(&adev->shadow_list_lock); | |
2910 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2911 | next = NULL; |
53cdccd5 CZ |
2912 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2913 | if (fence) { | |
f54d1867 | 2914 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2915 | if (r) { |
1d7b17b0 | 2916 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2917 | break; |
2918 | } | |
2919 | } | |
1f465087 | 2920 | |
f54d1867 | 2921 | dma_fence_put(fence); |
53cdccd5 CZ |
2922 | fence = next; |
2923 | } | |
2924 | mutex_unlock(&adev->shadow_list_lock); | |
2925 | if (fence) { | |
f54d1867 | 2926 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2927 | if (r) |
1d7b17b0 | 2928 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2929 | } |
f54d1867 | 2930 | dma_fence_put(fence); |
53cdccd5 | 2931 | } |
d38ceaf9 AD |
2932 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2933 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
2934 | |
2935 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 2936 | continue; |
53cdccd5 | 2937 | |
aa1c8900 | 2938 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2939 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2940 | } |
d38ceaf9 | 2941 | } else { |
2200edac | 2942 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2943 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
51687759 | 2944 | if (adev->rings[i] && adev->rings[i]->sched.thread) { |
0875dc9e | 2945 | kthread_unpark(adev->rings[i]->sched.thread); |
0875dc9e | 2946 | } |
d38ceaf9 AD |
2947 | } |
2948 | } | |
2949 | ||
2950 | drm_helper_resume_force_mode(adev->ddev); | |
2951 | ||
2952 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
6643be65 | 2953 | if (r) |
d38ceaf9 AD |
2954 | /* bad news, how to tell it to userspace ? */ |
2955 | dev_info(adev->dev, "GPU reset failed\n"); | |
6643be65 CZ |
2956 | else |
2957 | dev_info(adev->dev, "GPU reset successed!\n"); | |
d38ceaf9 | 2958 | |
d38ceaf9 AD |
2959 | return r; |
2960 | } | |
2961 | ||
d0dd7f0c AD |
2962 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2963 | { | |
2964 | u32 mask; | |
2965 | int ret; | |
2966 | ||
cd474ba0 AD |
2967 | if (amdgpu_pcie_gen_cap) |
2968 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2969 | |
cd474ba0 AD |
2970 | if (amdgpu_pcie_lane_cap) |
2971 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2972 | |
cd474ba0 AD |
2973 | /* covers APUs as well */ |
2974 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2975 | if (adev->pm.pcie_gen_mask == 0) | |
2976 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2977 | if (adev->pm.pcie_mlw_mask == 0) | |
2978 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2979 | return; |
cd474ba0 | 2980 | } |
d0dd7f0c | 2981 | |
cd474ba0 AD |
2982 | if (adev->pm.pcie_gen_mask == 0) { |
2983 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2984 | if (!ret) { | |
2985 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2986 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2987 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2988 | ||
2989 | if (mask & DRM_PCIE_SPEED_25) | |
2990 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2991 | if (mask & DRM_PCIE_SPEED_50) | |
2992 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2993 | if (mask & DRM_PCIE_SPEED_80) | |
2994 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2995 | } else { | |
2996 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2997 | } | |
2998 | } | |
2999 | if (adev->pm.pcie_mlw_mask == 0) { | |
3000 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3001 | if (!ret) { | |
3002 | switch (mask) { | |
3003 | case 32: | |
3004 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3005 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3006 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3007 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3008 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3009 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3010 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3011 | break; | |
3012 | case 16: | |
3013 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3014 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3015 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3016 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3017 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3018 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3019 | break; | |
3020 | case 12: | |
3021 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3022 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3023 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3024 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3025 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3026 | break; | |
3027 | case 8: | |
3028 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3029 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3030 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3031 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3032 | break; | |
3033 | case 4: | |
3034 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3035 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3036 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3037 | break; | |
3038 | case 2: | |
3039 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3040 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3041 | break; | |
3042 | case 1: | |
3043 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3044 | break; | |
3045 | default: | |
3046 | break; | |
3047 | } | |
3048 | } else { | |
3049 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3050 | } |
3051 | } | |
3052 | } | |
d38ceaf9 AD |
3053 | |
3054 | /* | |
3055 | * Debugfs | |
3056 | */ | |
3057 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3058 | const struct drm_info_list *files, |
d38ceaf9 AD |
3059 | unsigned nfiles) |
3060 | { | |
3061 | unsigned i; | |
3062 | ||
3063 | for (i = 0; i < adev->debugfs_count; i++) { | |
3064 | if (adev->debugfs[i].files == files) { | |
3065 | /* Already registered */ | |
3066 | return 0; | |
3067 | } | |
3068 | } | |
3069 | ||
3070 | i = adev->debugfs_count + 1; | |
3071 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3072 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3073 | DRM_ERROR("Report so we increase " | |
3074 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3075 | return -EINVAL; | |
3076 | } | |
3077 | adev->debugfs[adev->debugfs_count].files = files; | |
3078 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3079 | adev->debugfs_count = i; | |
3080 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3081 | drm_debugfs_create_files(files, nfiles, |
3082 | adev->ddev->primary->debugfs_root, | |
3083 | adev->ddev->primary); | |
3084 | #endif | |
3085 | return 0; | |
3086 | } | |
3087 | ||
d38ceaf9 AD |
3088 | #if defined(CONFIG_DEBUG_FS) |
3089 | ||
3090 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3091 | size_t size, loff_t *pos) | |
3092 | { | |
45063097 | 3093 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3094 | ssize_t result = 0; |
3095 | int r; | |
bd12267d | 3096 | bool pm_pg_lock, use_bank; |
56628159 | 3097 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3098 | |
3099 | if (size & 0x3 || *pos & 0x3) | |
3100 | return -EINVAL; | |
3101 | ||
bd12267d TSD |
3102 | /* are we reading registers for which a PG lock is necessary? */ |
3103 | pm_pg_lock = (*pos >> 23) & 1; | |
3104 | ||
56628159 TSD |
3105 | if (*pos & (1ULL << 62)) { |
3106 | se_bank = (*pos >> 24) & 0x3FF; | |
3107 | sh_bank = (*pos >> 34) & 0x3FF; | |
3108 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
3109 | |
3110 | if (se_bank == 0x3FF) | |
3111 | se_bank = 0xFFFFFFFF; | |
3112 | if (sh_bank == 0x3FF) | |
3113 | sh_bank = 0xFFFFFFFF; | |
3114 | if (instance_bank == 0x3FF) | |
3115 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3116 | use_bank = 1; |
56628159 TSD |
3117 | } else { |
3118 | use_bank = 0; | |
3119 | } | |
3120 | ||
801a6aa9 | 3121 | *pos &= (1UL << 22) - 1; |
bd12267d | 3122 | |
56628159 | 3123 | if (use_bank) { |
32977f93 TSD |
3124 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3125 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3126 | return -EINVAL; |
3127 | mutex_lock(&adev->grbm_idx_mutex); | |
3128 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3129 | sh_bank, instance_bank); | |
3130 | } | |
3131 | ||
bd12267d TSD |
3132 | if (pm_pg_lock) |
3133 | mutex_lock(&adev->pm.mutex); | |
3134 | ||
d38ceaf9 AD |
3135 | while (size) { |
3136 | uint32_t value; | |
3137 | ||
3138 | if (*pos > adev->rmmio_size) | |
56628159 | 3139 | goto end; |
d38ceaf9 AD |
3140 | |
3141 | value = RREG32(*pos >> 2); | |
3142 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3143 | if (r) { |
3144 | result = r; | |
3145 | goto end; | |
3146 | } | |
d38ceaf9 AD |
3147 | |
3148 | result += 4; | |
3149 | buf += 4; | |
3150 | *pos += 4; | |
3151 | size -= 4; | |
3152 | } | |
3153 | ||
56628159 TSD |
3154 | end: |
3155 | if (use_bank) { | |
3156 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3157 | mutex_unlock(&adev->grbm_idx_mutex); | |
3158 | } | |
3159 | ||
bd12267d TSD |
3160 | if (pm_pg_lock) |
3161 | mutex_unlock(&adev->pm.mutex); | |
3162 | ||
d38ceaf9 AD |
3163 | return result; |
3164 | } | |
3165 | ||
3166 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3167 | size_t size, loff_t *pos) | |
3168 | { | |
45063097 | 3169 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3170 | ssize_t result = 0; |
3171 | int r; | |
394fdde2 TSD |
3172 | bool pm_pg_lock, use_bank; |
3173 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3174 | |
3175 | if (size & 0x3 || *pos & 0x3) | |
3176 | return -EINVAL; | |
3177 | ||
394fdde2 TSD |
3178 | /* are we reading registers for which a PG lock is necessary? */ |
3179 | pm_pg_lock = (*pos >> 23) & 1; | |
3180 | ||
3181 | if (*pos & (1ULL << 62)) { | |
3182 | se_bank = (*pos >> 24) & 0x3FF; | |
3183 | sh_bank = (*pos >> 34) & 0x3FF; | |
3184 | instance_bank = (*pos >> 44) & 0x3FF; | |
3185 | ||
3186 | if (se_bank == 0x3FF) | |
3187 | se_bank = 0xFFFFFFFF; | |
3188 | if (sh_bank == 0x3FF) | |
3189 | sh_bank = 0xFFFFFFFF; | |
3190 | if (instance_bank == 0x3FF) | |
3191 | instance_bank = 0xFFFFFFFF; | |
3192 | use_bank = 1; | |
3193 | } else { | |
3194 | use_bank = 0; | |
3195 | } | |
3196 | ||
801a6aa9 | 3197 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3198 | |
3199 | if (use_bank) { | |
3200 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3201 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3202 | return -EINVAL; | |
3203 | mutex_lock(&adev->grbm_idx_mutex); | |
3204 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3205 | sh_bank, instance_bank); | |
3206 | } | |
3207 | ||
3208 | if (pm_pg_lock) | |
3209 | mutex_lock(&adev->pm.mutex); | |
3210 | ||
d38ceaf9 AD |
3211 | while (size) { |
3212 | uint32_t value; | |
3213 | ||
3214 | if (*pos > adev->rmmio_size) | |
3215 | return result; | |
3216 | ||
3217 | r = get_user(value, (uint32_t *)buf); | |
3218 | if (r) | |
3219 | return r; | |
3220 | ||
3221 | WREG32(*pos >> 2, value); | |
3222 | ||
3223 | result += 4; | |
3224 | buf += 4; | |
3225 | *pos += 4; | |
3226 | size -= 4; | |
3227 | } | |
3228 | ||
394fdde2 TSD |
3229 | if (use_bank) { |
3230 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3231 | mutex_unlock(&adev->grbm_idx_mutex); | |
3232 | } | |
3233 | ||
3234 | if (pm_pg_lock) | |
3235 | mutex_unlock(&adev->pm.mutex); | |
3236 | ||
d38ceaf9 AD |
3237 | return result; |
3238 | } | |
3239 | ||
adcec288 TSD |
3240 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3241 | size_t size, loff_t *pos) | |
3242 | { | |
45063097 | 3243 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3244 | ssize_t result = 0; |
3245 | int r; | |
3246 | ||
3247 | if (size & 0x3 || *pos & 0x3) | |
3248 | return -EINVAL; | |
3249 | ||
3250 | while (size) { | |
3251 | uint32_t value; | |
3252 | ||
3253 | value = RREG32_PCIE(*pos >> 2); | |
3254 | r = put_user(value, (uint32_t *)buf); | |
3255 | if (r) | |
3256 | return r; | |
3257 | ||
3258 | result += 4; | |
3259 | buf += 4; | |
3260 | *pos += 4; | |
3261 | size -= 4; | |
3262 | } | |
3263 | ||
3264 | return result; | |
3265 | } | |
3266 | ||
3267 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3268 | size_t size, loff_t *pos) | |
3269 | { | |
45063097 | 3270 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3271 | ssize_t result = 0; |
3272 | int r; | |
3273 | ||
3274 | if (size & 0x3 || *pos & 0x3) | |
3275 | return -EINVAL; | |
3276 | ||
3277 | while (size) { | |
3278 | uint32_t value; | |
3279 | ||
3280 | r = get_user(value, (uint32_t *)buf); | |
3281 | if (r) | |
3282 | return r; | |
3283 | ||
3284 | WREG32_PCIE(*pos >> 2, value); | |
3285 | ||
3286 | result += 4; | |
3287 | buf += 4; | |
3288 | *pos += 4; | |
3289 | size -= 4; | |
3290 | } | |
3291 | ||
3292 | return result; | |
3293 | } | |
3294 | ||
3295 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3296 | size_t size, loff_t *pos) | |
3297 | { | |
45063097 | 3298 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3299 | ssize_t result = 0; |
3300 | int r; | |
3301 | ||
3302 | if (size & 0x3 || *pos & 0x3) | |
3303 | return -EINVAL; | |
3304 | ||
3305 | while (size) { | |
3306 | uint32_t value; | |
3307 | ||
3308 | value = RREG32_DIDT(*pos >> 2); | |
3309 | r = put_user(value, (uint32_t *)buf); | |
3310 | if (r) | |
3311 | return r; | |
3312 | ||
3313 | result += 4; | |
3314 | buf += 4; | |
3315 | *pos += 4; | |
3316 | size -= 4; | |
3317 | } | |
3318 | ||
3319 | return result; | |
3320 | } | |
3321 | ||
3322 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3323 | size_t size, loff_t *pos) | |
3324 | { | |
45063097 | 3325 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3326 | ssize_t result = 0; |
3327 | int r; | |
3328 | ||
3329 | if (size & 0x3 || *pos & 0x3) | |
3330 | return -EINVAL; | |
3331 | ||
3332 | while (size) { | |
3333 | uint32_t value; | |
3334 | ||
3335 | r = get_user(value, (uint32_t *)buf); | |
3336 | if (r) | |
3337 | return r; | |
3338 | ||
3339 | WREG32_DIDT(*pos >> 2, value); | |
3340 | ||
3341 | result += 4; | |
3342 | buf += 4; | |
3343 | *pos += 4; | |
3344 | size -= 4; | |
3345 | } | |
3346 | ||
3347 | return result; | |
3348 | } | |
3349 | ||
3350 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3351 | size_t size, loff_t *pos) | |
3352 | { | |
45063097 | 3353 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3354 | ssize_t result = 0; |
3355 | int r; | |
3356 | ||
3357 | if (size & 0x3 || *pos & 0x3) | |
3358 | return -EINVAL; | |
3359 | ||
3360 | while (size) { | |
3361 | uint32_t value; | |
3362 | ||
6fc0deaf | 3363 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3364 | r = put_user(value, (uint32_t *)buf); |
3365 | if (r) | |
3366 | return r; | |
3367 | ||
3368 | result += 4; | |
3369 | buf += 4; | |
3370 | *pos += 4; | |
3371 | size -= 4; | |
3372 | } | |
3373 | ||
3374 | return result; | |
3375 | } | |
3376 | ||
3377 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3378 | size_t size, loff_t *pos) | |
3379 | { | |
45063097 | 3380 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3381 | ssize_t result = 0; |
3382 | int r; | |
3383 | ||
3384 | if (size & 0x3 || *pos & 0x3) | |
3385 | return -EINVAL; | |
3386 | ||
3387 | while (size) { | |
3388 | uint32_t value; | |
3389 | ||
3390 | r = get_user(value, (uint32_t *)buf); | |
3391 | if (r) | |
3392 | return r; | |
3393 | ||
6fc0deaf | 3394 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3395 | |
3396 | result += 4; | |
3397 | buf += 4; | |
3398 | *pos += 4; | |
3399 | size -= 4; | |
3400 | } | |
3401 | ||
3402 | return result; | |
3403 | } | |
3404 | ||
1e051413 TSD |
3405 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3406 | size_t size, loff_t *pos) | |
3407 | { | |
45063097 | 3408 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3409 | ssize_t result = 0; |
3410 | int r; | |
3411 | uint32_t *config, no_regs = 0; | |
3412 | ||
3413 | if (size & 0x3 || *pos & 0x3) | |
3414 | return -EINVAL; | |
3415 | ||
ecab7668 | 3416 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3417 | if (!config) |
3418 | return -ENOMEM; | |
3419 | ||
3420 | /* version, increment each time something is added */ | |
9a999359 | 3421 | config[no_regs++] = 3; |
1e051413 TSD |
3422 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3423 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3424 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3425 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3426 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3427 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3428 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3429 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3430 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3431 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3432 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3433 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3434 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3435 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3436 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3437 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3438 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3439 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3440 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3441 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3442 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3443 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3444 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3445 | ||
89a8f309 TSD |
3446 | /* rev==1 */ |
3447 | config[no_regs++] = adev->rev_id; | |
3448 | config[no_regs++] = adev->pg_flags; | |
3449 | config[no_regs++] = adev->cg_flags; | |
3450 | ||
e9f11dc8 TSD |
3451 | /* rev==2 */ |
3452 | config[no_regs++] = adev->family; | |
3453 | config[no_regs++] = adev->external_rev_id; | |
3454 | ||
9a999359 TSD |
3455 | /* rev==3 */ |
3456 | config[no_regs++] = adev->pdev->device; | |
3457 | config[no_regs++] = adev->pdev->revision; | |
3458 | config[no_regs++] = adev->pdev->subsystem_device; | |
3459 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3460 | ||
1e051413 TSD |
3461 | while (size && (*pos < no_regs * 4)) { |
3462 | uint32_t value; | |
3463 | ||
3464 | value = config[*pos >> 2]; | |
3465 | r = put_user(value, (uint32_t *)buf); | |
3466 | if (r) { | |
3467 | kfree(config); | |
3468 | return r; | |
3469 | } | |
3470 | ||
3471 | result += 4; | |
3472 | buf += 4; | |
3473 | *pos += 4; | |
3474 | size -= 4; | |
3475 | } | |
3476 | ||
3477 | kfree(config); | |
3478 | return result; | |
3479 | } | |
3480 | ||
f2cdaf20 TSD |
3481 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3482 | size_t size, loff_t *pos) | |
3483 | { | |
45063097 | 3484 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3485 | int idx, x, outsize, r, valuesize; |
3486 | uint32_t values[16]; | |
f2cdaf20 | 3487 | |
9f8df7d7 | 3488 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3489 | return -EINVAL; |
3490 | ||
3cbc614f SP |
3491 | if (amdgpu_dpm == 0) |
3492 | return -EINVAL; | |
3493 | ||
f2cdaf20 TSD |
3494 | /* convert offset to sensor number */ |
3495 | idx = *pos >> 2; | |
3496 | ||
9f8df7d7 | 3497 | valuesize = sizeof(values); |
f2cdaf20 | 3498 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3499 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3500 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3501 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3502 | &valuesize); | |
f2cdaf20 TSD |
3503 | else |
3504 | return -EINVAL; | |
3505 | ||
9f8df7d7 TSD |
3506 | if (size > valuesize) |
3507 | return -EINVAL; | |
3508 | ||
3509 | outsize = 0; | |
3510 | x = 0; | |
3511 | if (!r) { | |
3512 | while (size) { | |
3513 | r = put_user(values[x++], (int32_t *)buf); | |
3514 | buf += 4; | |
3515 | size -= 4; | |
3516 | outsize += 4; | |
3517 | } | |
3518 | } | |
f2cdaf20 | 3519 | |
9f8df7d7 | 3520 | return !r ? outsize : r; |
f2cdaf20 | 3521 | } |
1e051413 | 3522 | |
273d7aa1 TSD |
3523 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3524 | size_t size, loff_t *pos) | |
3525 | { | |
3526 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3527 | int r, x; | |
3528 | ssize_t result=0; | |
472259f0 | 3529 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3530 | |
3531 | if (size & 3 || *pos & 3) | |
3532 | return -EINVAL; | |
3533 | ||
3534 | /* decode offset */ | |
3535 | offset = (*pos & 0x7F); | |
3536 | se = ((*pos >> 7) & 0xFF); | |
3537 | sh = ((*pos >> 15) & 0xFF); | |
3538 | cu = ((*pos >> 23) & 0xFF); | |
3539 | wave = ((*pos >> 31) & 0xFF); | |
3540 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3541 | |
3542 | /* switch to the specific se/sh/cu */ | |
3543 | mutex_lock(&adev->grbm_idx_mutex); | |
3544 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3545 | ||
3546 | x = 0; | |
472259f0 TSD |
3547 | if (adev->gfx.funcs->read_wave_data) |
3548 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3549 | |
3550 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3551 | mutex_unlock(&adev->grbm_idx_mutex); | |
3552 | ||
5ecfb3b8 TSD |
3553 | if (!x) |
3554 | return -EINVAL; | |
3555 | ||
472259f0 | 3556 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3557 | uint32_t value; |
3558 | ||
472259f0 | 3559 | value = data[offset >> 2]; |
273d7aa1 TSD |
3560 | r = put_user(value, (uint32_t *)buf); |
3561 | if (r) | |
3562 | return r; | |
3563 | ||
3564 | result += 4; | |
3565 | buf += 4; | |
472259f0 | 3566 | offset += 4; |
273d7aa1 TSD |
3567 | size -= 4; |
3568 | } | |
3569 | ||
3570 | return result; | |
3571 | } | |
3572 | ||
c5a60ce8 TSD |
3573 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3574 | size_t size, loff_t *pos) | |
3575 | { | |
3576 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3577 | int r; | |
3578 | ssize_t result = 0; | |
3579 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3580 | ||
3581 | if (size & 3 || *pos & 3) | |
3582 | return -EINVAL; | |
3583 | ||
3584 | /* decode offset */ | |
3585 | offset = (*pos & 0xFFF); /* in dwords */ | |
3586 | se = ((*pos >> 12) & 0xFF); | |
3587 | sh = ((*pos >> 20) & 0xFF); | |
3588 | cu = ((*pos >> 28) & 0xFF); | |
3589 | wave = ((*pos >> 36) & 0xFF); | |
3590 | simd = ((*pos >> 44) & 0xFF); | |
3591 | thread = ((*pos >> 52) & 0xFF); | |
3592 | bank = ((*pos >> 60) & 1); | |
3593 | ||
3594 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3595 | if (!data) | |
3596 | return -ENOMEM; | |
3597 | ||
3598 | /* switch to the specific se/sh/cu */ | |
3599 | mutex_lock(&adev->grbm_idx_mutex); | |
3600 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3601 | ||
3602 | if (bank == 0) { | |
3603 | if (adev->gfx.funcs->read_wave_vgprs) | |
3604 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3605 | } else { | |
3606 | if (adev->gfx.funcs->read_wave_sgprs) | |
3607 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3608 | } | |
3609 | ||
3610 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3611 | mutex_unlock(&adev->grbm_idx_mutex); | |
3612 | ||
3613 | while (size) { | |
3614 | uint32_t value; | |
3615 | ||
3616 | value = data[offset++]; | |
3617 | r = put_user(value, (uint32_t *)buf); | |
3618 | if (r) { | |
3619 | result = r; | |
3620 | goto err; | |
3621 | } | |
3622 | ||
3623 | result += 4; | |
3624 | buf += 4; | |
3625 | size -= 4; | |
3626 | } | |
3627 | ||
3628 | err: | |
3629 | kfree(data); | |
3630 | return result; | |
3631 | } | |
3632 | ||
d38ceaf9 AD |
3633 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3634 | .owner = THIS_MODULE, | |
3635 | .read = amdgpu_debugfs_regs_read, | |
3636 | .write = amdgpu_debugfs_regs_write, | |
3637 | .llseek = default_llseek | |
3638 | }; | |
adcec288 TSD |
3639 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3640 | .owner = THIS_MODULE, | |
3641 | .read = amdgpu_debugfs_regs_didt_read, | |
3642 | .write = amdgpu_debugfs_regs_didt_write, | |
3643 | .llseek = default_llseek | |
3644 | }; | |
3645 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3646 | .owner = THIS_MODULE, | |
3647 | .read = amdgpu_debugfs_regs_pcie_read, | |
3648 | .write = amdgpu_debugfs_regs_pcie_write, | |
3649 | .llseek = default_llseek | |
3650 | }; | |
3651 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3652 | .owner = THIS_MODULE, | |
3653 | .read = amdgpu_debugfs_regs_smc_read, | |
3654 | .write = amdgpu_debugfs_regs_smc_write, | |
3655 | .llseek = default_llseek | |
3656 | }; | |
3657 | ||
1e051413 TSD |
3658 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3659 | .owner = THIS_MODULE, | |
3660 | .read = amdgpu_debugfs_gca_config_read, | |
3661 | .llseek = default_llseek | |
3662 | }; | |
3663 | ||
f2cdaf20 TSD |
3664 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3665 | .owner = THIS_MODULE, | |
3666 | .read = amdgpu_debugfs_sensor_read, | |
3667 | .llseek = default_llseek | |
3668 | }; | |
3669 | ||
273d7aa1 TSD |
3670 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3671 | .owner = THIS_MODULE, | |
3672 | .read = amdgpu_debugfs_wave_read, | |
3673 | .llseek = default_llseek | |
3674 | }; | |
c5a60ce8 TSD |
3675 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3676 | .owner = THIS_MODULE, | |
3677 | .read = amdgpu_debugfs_gpr_read, | |
3678 | .llseek = default_llseek | |
3679 | }; | |
273d7aa1 | 3680 | |
adcec288 TSD |
3681 | static const struct file_operations *debugfs_regs[] = { |
3682 | &amdgpu_debugfs_regs_fops, | |
3683 | &amdgpu_debugfs_regs_didt_fops, | |
3684 | &amdgpu_debugfs_regs_pcie_fops, | |
3685 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3686 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3687 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3688 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3689 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3690 | }; |
3691 | ||
3692 | static const char *debugfs_regs_names[] = { | |
3693 | "amdgpu_regs", | |
3694 | "amdgpu_regs_didt", | |
3695 | "amdgpu_regs_pcie", | |
3696 | "amdgpu_regs_smc", | |
1e051413 | 3697 | "amdgpu_gca_config", |
f2cdaf20 | 3698 | "amdgpu_sensors", |
273d7aa1 | 3699 | "amdgpu_wave", |
c5a60ce8 | 3700 | "amdgpu_gpr", |
adcec288 | 3701 | }; |
d38ceaf9 AD |
3702 | |
3703 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3704 | { | |
3705 | struct drm_minor *minor = adev->ddev->primary; | |
3706 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3707 | unsigned i, j; |
3708 | ||
3709 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3710 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3711 | S_IFREG | S_IRUGO, root, | |
3712 | adev, debugfs_regs[i]); | |
3713 | if (IS_ERR(ent)) { | |
3714 | for (j = 0; j < i; j++) { | |
3715 | debugfs_remove(adev->debugfs_regs[i]); | |
3716 | adev->debugfs_regs[i] = NULL; | |
3717 | } | |
3718 | return PTR_ERR(ent); | |
3719 | } | |
d38ceaf9 | 3720 | |
adcec288 TSD |
3721 | if (!i) |
3722 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3723 | adev->debugfs_regs[i] = ent; | |
3724 | } | |
d38ceaf9 AD |
3725 | |
3726 | return 0; | |
3727 | } | |
3728 | ||
3729 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3730 | { | |
adcec288 TSD |
3731 | unsigned i; |
3732 | ||
3733 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3734 | if (adev->debugfs_regs[i]) { | |
3735 | debugfs_remove(adev->debugfs_regs[i]); | |
3736 | adev->debugfs_regs[i] = NULL; | |
3737 | } | |
3738 | } | |
d38ceaf9 AD |
3739 | } |
3740 | ||
3741 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
3742 | { | |
3743 | return 0; | |
3744 | } | |
7cebc728 AK |
3745 | #else |
3746 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3747 | { | |
3748 | return 0; | |
3749 | } | |
3750 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3751 | #endif |