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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
d38ceaf9 | 56 | |
e2a75f88 | 57 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 58 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 59 | |
d38ceaf9 AD |
60 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
61 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
62 | ||
63 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
64 | "TAHITI", |
65 | "PITCAIRN", | |
66 | "VERDE", | |
67 | "OLAND", | |
68 | "HAINAN", | |
d38ceaf9 AD |
69 | "BONAIRE", |
70 | "KAVERI", | |
71 | "KABINI", | |
72 | "HAWAII", | |
73 | "MULLINS", | |
74 | "TOPAZ", | |
75 | "TONGA", | |
48299f95 | 76 | "FIJI", |
d38ceaf9 | 77 | "CARRIZO", |
139f4917 | 78 | "STONEY", |
2cc0c0b5 FC |
79 | "POLARIS10", |
80 | "POLARIS11", | |
c4642a47 | 81 | "POLARIS12", |
d4196f01 | 82 | "VEGA10", |
2ca8a5d2 | 83 | "RAVEN", |
d38ceaf9 AD |
84 | "LAST", |
85 | }; | |
86 | ||
87 | bool amdgpu_device_is_px(struct drm_device *dev) | |
88 | { | |
89 | struct amdgpu_device *adev = dev->dev_private; | |
90 | ||
2f7d10b3 | 91 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
92 | return true; |
93 | return false; | |
94 | } | |
95 | ||
96 | /* | |
97 | * MMIO register access helper functions. | |
98 | */ | |
99 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 100 | uint32_t acc_flags) |
d38ceaf9 | 101 | { |
f4b373f4 TSD |
102 | uint32_t ret; |
103 | ||
15d72fd7 | 104 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
105 | BUG_ON(in_interrupt()); |
106 | return amdgpu_virt_kiq_rreg(adev, reg); | |
107 | } | |
108 | ||
15d72fd7 | 109 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 110 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
111 | else { |
112 | unsigned long flags; | |
d38ceaf9 AD |
113 | |
114 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
115 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
116 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
117 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 118 | } |
f4b373f4 TSD |
119 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
120 | return ret; | |
d38ceaf9 AD |
121 | } |
122 | ||
123 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 124 | uint32_t acc_flags) |
d38ceaf9 | 125 | { |
f4b373f4 | 126 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 127 | |
15d72fd7 | 128 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
129 | BUG_ON(in_interrupt()); |
130 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
131 | } | |
132 | ||
15d72fd7 | 133 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
134 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
135 | else { | |
136 | unsigned long flags; | |
137 | ||
138 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
139 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
140 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
141 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
142 | } | |
143 | } | |
144 | ||
145 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
146 | { | |
147 | if ((reg * 4) < adev->rio_mem_size) | |
148 | return ioread32(adev->rio_mem + (reg * 4)); | |
149 | else { | |
150 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
151 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
152 | } | |
153 | } | |
154 | ||
155 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
156 | { | |
157 | ||
158 | if ((reg * 4) < adev->rio_mem_size) | |
159 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
160 | else { | |
161 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
162 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
163 | } | |
164 | } | |
165 | ||
166 | /** | |
167 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
168 | * | |
169 | * @adev: amdgpu_device pointer | |
170 | * @index: doorbell index | |
171 | * | |
172 | * Returns the value in the doorbell aperture at the | |
173 | * requested doorbell index (CIK). | |
174 | */ | |
175 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
176 | { | |
177 | if (index < adev->doorbell.num_doorbells) { | |
178 | return readl(adev->doorbell.ptr + index); | |
179 | } else { | |
180 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
181 | return 0; | |
182 | } | |
183 | } | |
184 | ||
185 | /** | |
186 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
187 | * | |
188 | * @adev: amdgpu_device pointer | |
189 | * @index: doorbell index | |
190 | * @v: value to write | |
191 | * | |
192 | * Writes @v to the doorbell aperture at the | |
193 | * requested doorbell index (CIK). | |
194 | */ | |
195 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
196 | { | |
197 | if (index < adev->doorbell.num_doorbells) { | |
198 | writel(v, adev->doorbell.ptr + index); | |
199 | } else { | |
200 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
201 | } | |
202 | } | |
203 | ||
832be404 KW |
204 | /** |
205 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
206 | * | |
207 | * @adev: amdgpu_device pointer | |
208 | * @index: doorbell index | |
209 | * | |
210 | * Returns the value in the doorbell aperture at the | |
211 | * requested doorbell index (VEGA10+). | |
212 | */ | |
213 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
214 | { | |
215 | if (index < adev->doorbell.num_doorbells) { | |
216 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
217 | } else { | |
218 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
219 | return 0; | |
220 | } | |
221 | } | |
222 | ||
223 | /** | |
224 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
225 | * | |
226 | * @adev: amdgpu_device pointer | |
227 | * @index: doorbell index | |
228 | * @v: value to write | |
229 | * | |
230 | * Writes @v to the doorbell aperture at the | |
231 | * requested doorbell index (VEGA10+). | |
232 | */ | |
233 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
234 | { | |
235 | if (index < adev->doorbell.num_doorbells) { | |
236 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
237 | } else { | |
238 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
239 | } | |
240 | } | |
241 | ||
d38ceaf9 AD |
242 | /** |
243 | * amdgpu_invalid_rreg - dummy reg read function | |
244 | * | |
245 | * @adev: amdgpu device pointer | |
246 | * @reg: offset of register | |
247 | * | |
248 | * Dummy register read function. Used for register blocks | |
249 | * that certain asics don't have (all asics). | |
250 | * Returns the value in the register. | |
251 | */ | |
252 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
253 | { | |
254 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
255 | BUG(); | |
256 | return 0; | |
257 | } | |
258 | ||
259 | /** | |
260 | * amdgpu_invalid_wreg - dummy reg write function | |
261 | * | |
262 | * @adev: amdgpu device pointer | |
263 | * @reg: offset of register | |
264 | * @v: value to write to the register | |
265 | * | |
266 | * Dummy register read function. Used for register blocks | |
267 | * that certain asics don't have (all asics). | |
268 | */ | |
269 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
270 | { | |
271 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
272 | reg, v); | |
273 | BUG(); | |
274 | } | |
275 | ||
276 | /** | |
277 | * amdgpu_block_invalid_rreg - dummy reg read function | |
278 | * | |
279 | * @adev: amdgpu device pointer | |
280 | * @block: offset of instance | |
281 | * @reg: offset of register | |
282 | * | |
283 | * Dummy register read function. Used for register blocks | |
284 | * that certain asics don't have (all asics). | |
285 | * Returns the value in the register. | |
286 | */ | |
287 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
288 | uint32_t block, uint32_t reg) | |
289 | { | |
290 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
291 | reg, block); | |
292 | BUG(); | |
293 | return 0; | |
294 | } | |
295 | ||
296 | /** | |
297 | * amdgpu_block_invalid_wreg - dummy reg write function | |
298 | * | |
299 | * @adev: amdgpu device pointer | |
300 | * @block: offset of instance | |
301 | * @reg: offset of register | |
302 | * @v: value to write to the register | |
303 | * | |
304 | * Dummy register read function. Used for register blocks | |
305 | * that certain asics don't have (all asics). | |
306 | */ | |
307 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
308 | uint32_t block, | |
309 | uint32_t reg, uint32_t v) | |
310 | { | |
311 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
312 | reg, block, v); | |
313 | BUG(); | |
314 | } | |
315 | ||
316 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
317 | { | |
318 | int r; | |
319 | ||
320 | if (adev->vram_scratch.robj == NULL) { | |
321 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 322 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
323 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
324 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 325 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
326 | if (r) { |
327 | return r; | |
328 | } | |
329 | } | |
330 | ||
331 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
332 | if (unlikely(r != 0)) | |
333 | return r; | |
334 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
335 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
336 | if (r) { | |
337 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
338 | return r; | |
339 | } | |
340 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
341 | (void **)&adev->vram_scratch.ptr); | |
342 | if (r) | |
343 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
344 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
345 | ||
346 | return r; | |
347 | } | |
348 | ||
349 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
350 | { | |
351 | int r; | |
352 | ||
353 | if (adev->vram_scratch.robj == NULL) { | |
354 | return; | |
355 | } | |
8ab25b4f | 356 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, true); |
d38ceaf9 AD |
357 | if (likely(r == 0)) { |
358 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
359 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
360 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
361 | } | |
362 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
363 | } | |
364 | ||
365 | /** | |
366 | * amdgpu_program_register_sequence - program an array of registers. | |
367 | * | |
368 | * @adev: amdgpu_device pointer | |
369 | * @registers: pointer to the register array | |
370 | * @array_size: size of the register array | |
371 | * | |
372 | * Programs an array or registers with and and or masks. | |
373 | * This is a helper for setting golden registers. | |
374 | */ | |
375 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
376 | const u32 *registers, | |
377 | const u32 array_size) | |
378 | { | |
379 | u32 tmp, reg, and_mask, or_mask; | |
380 | int i; | |
381 | ||
382 | if (array_size % 3) | |
383 | return; | |
384 | ||
385 | for (i = 0; i < array_size; i +=3) { | |
386 | reg = registers[i + 0]; | |
387 | and_mask = registers[i + 1]; | |
388 | or_mask = registers[i + 2]; | |
389 | ||
390 | if (and_mask == 0xffffffff) { | |
391 | tmp = or_mask; | |
392 | } else { | |
393 | tmp = RREG32(reg); | |
394 | tmp &= ~and_mask; | |
395 | tmp |= or_mask; | |
396 | } | |
397 | WREG32(reg, tmp); | |
398 | } | |
399 | } | |
400 | ||
401 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
402 | { | |
403 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
404 | } | |
405 | ||
406 | /* | |
407 | * GPU doorbell aperture helpers function. | |
408 | */ | |
409 | /** | |
410 | * amdgpu_doorbell_init - Init doorbell driver information. | |
411 | * | |
412 | * @adev: amdgpu_device pointer | |
413 | * | |
414 | * Init doorbell driver information (CIK) | |
415 | * Returns 0 on success, error on failure. | |
416 | */ | |
417 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
418 | { | |
419 | /* doorbell bar mapping */ | |
420 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
421 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
422 | ||
edf600da | 423 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
424 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
425 | if (adev->doorbell.num_doorbells == 0) | |
426 | return -EINVAL; | |
427 | ||
8972e5d2 CK |
428 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
429 | adev->doorbell.num_doorbells * | |
430 | sizeof(u32)); | |
431 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 432 | return -ENOMEM; |
d38ceaf9 AD |
433 | |
434 | return 0; | |
435 | } | |
436 | ||
437 | /** | |
438 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
439 | * | |
440 | * @adev: amdgpu_device pointer | |
441 | * | |
442 | * Tear down doorbell driver information (CIK) | |
443 | */ | |
444 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
445 | { | |
446 | iounmap(adev->doorbell.ptr); | |
447 | adev->doorbell.ptr = NULL; | |
448 | } | |
449 | ||
450 | /** | |
451 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
452 | * setup amdkfd | |
453 | * | |
454 | * @adev: amdgpu_device pointer | |
455 | * @aperture_base: output returning doorbell aperture base physical address | |
456 | * @aperture_size: output returning doorbell aperture size in bytes | |
457 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
458 | * | |
459 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
460 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
461 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
462 | */ | |
463 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
464 | phys_addr_t *aperture_base, | |
465 | size_t *aperture_size, | |
466 | size_t *start_offset) | |
467 | { | |
468 | /* | |
469 | * The first num_doorbells are used by amdgpu. | |
470 | * amdkfd takes whatever's left in the aperture. | |
471 | */ | |
472 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
473 | *aperture_base = adev->doorbell.base; | |
474 | *aperture_size = adev->doorbell.size; | |
475 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
476 | } else { | |
477 | *aperture_base = 0; | |
478 | *aperture_size = 0; | |
479 | *start_offset = 0; | |
480 | } | |
481 | } | |
482 | ||
483 | /* | |
484 | * amdgpu_wb_*() | |
455a7bc2 | 485 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 486 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
487 | */ |
488 | ||
489 | /** | |
490 | * amdgpu_wb_fini - Disable Writeback and free memory | |
491 | * | |
492 | * @adev: amdgpu_device pointer | |
493 | * | |
494 | * Disables Writeback and frees the Writeback memory (all asics). | |
495 | * Used at driver shutdown. | |
496 | */ | |
497 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
498 | { | |
499 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
500 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
501 | &adev->wb.gpu_addr, | |
502 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
503 | adev->wb.wb_obj = NULL; |
504 | } | |
505 | } | |
506 | ||
507 | /** | |
508 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
509 | * | |
510 | * @adev: amdgpu_device pointer | |
511 | * | |
455a7bc2 | 512 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
513 | * Used at driver startup. |
514 | * Returns 0 on success or an -error on failure. | |
515 | */ | |
516 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
517 | { | |
518 | int r; | |
519 | ||
520 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 521 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
522 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
523 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
524 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
525 | if (r) { |
526 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
527 | return r; | |
528 | } | |
d38ceaf9 AD |
529 | |
530 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
531 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
532 | ||
533 | /* clear wb memory */ | |
60a970a6 | 534 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
535 | } |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
540 | /** | |
541 | * amdgpu_wb_get - Allocate a wb entry | |
542 | * | |
543 | * @adev: amdgpu_device pointer | |
544 | * @wb: wb index | |
545 | * | |
546 | * Allocate a wb slot for use by the driver (all asics). | |
547 | * Returns 0 on success or -EINVAL on failure. | |
548 | */ | |
549 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
550 | { | |
551 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
552 | if (offset < adev->wb.num_wb) { | |
553 | __set_bit(offset, adev->wb.used); | |
554 | *wb = offset; | |
555 | return 0; | |
556 | } else { | |
557 | return -EINVAL; | |
558 | } | |
559 | } | |
560 | ||
7014285a KW |
561 | /** |
562 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
563 | * | |
564 | * @adev: amdgpu_device pointer | |
565 | * @wb: wb index | |
566 | * | |
567 | * Allocate a wb slot for use by the driver (all asics). | |
568 | * Returns 0 on success or -EINVAL on failure. | |
569 | */ | |
570 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
571 | { | |
572 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
573 | adev->wb.num_wb, 0, 2, 7, 0); | |
574 | if ((offset + 1) < adev->wb.num_wb) { | |
575 | __set_bit(offset, adev->wb.used); | |
576 | __set_bit(offset + 1, adev->wb.used); | |
577 | *wb = offset; | |
578 | return 0; | |
579 | } else { | |
580 | return -EINVAL; | |
581 | } | |
582 | } | |
583 | ||
d38ceaf9 AD |
584 | /** |
585 | * amdgpu_wb_free - Free a wb entry | |
586 | * | |
587 | * @adev: amdgpu_device pointer | |
588 | * @wb: wb index | |
589 | * | |
590 | * Free a wb slot allocated for use by the driver (all asics) | |
591 | */ | |
592 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
593 | { | |
594 | if (wb < adev->wb.num_wb) | |
595 | __clear_bit(wb, adev->wb.used); | |
596 | } | |
597 | ||
7014285a KW |
598 | /** |
599 | * amdgpu_wb_free_64bit - Free a wb entry | |
600 | * | |
601 | * @adev: amdgpu_device pointer | |
602 | * @wb: wb index | |
603 | * | |
604 | * Free a wb slot allocated for use by the driver (all asics) | |
605 | */ | |
606 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
607 | { | |
608 | if ((wb + 1) < adev->wb.num_wb) { | |
609 | __clear_bit(wb, adev->wb.used); | |
610 | __clear_bit(wb + 1, adev->wb.used); | |
611 | } | |
612 | } | |
613 | ||
d38ceaf9 AD |
614 | /** |
615 | * amdgpu_vram_location - try to find VRAM location | |
616 | * @adev: amdgpu device structure holding all necessary informations | |
617 | * @mc: memory controller structure holding memory informations | |
618 | * @base: base address at which to put VRAM | |
619 | * | |
455a7bc2 | 620 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
621 | * as parameter (which is so far either PCI aperture address or |
622 | * for IGP TOM base address). | |
623 | * | |
624 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
625 | * address space then we limit the VRAM size to the aperture. | |
626 | * | |
627 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
628 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
629 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
630 | * not IGP. | |
631 | * | |
632 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
633 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
634 | * Novell bug 204882 + along with lots of ubuntu ones | |
635 | * | |
636 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
637 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
638 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
639 | * ones) | |
640 | * | |
641 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 642 | * explicitly check for that though. |
d38ceaf9 AD |
643 | * |
644 | * FIXME: when reducing VRAM size align new size on power of 2. | |
645 | */ | |
646 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
647 | { | |
648 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
649 | ||
650 | mc->vram_start = base; | |
651 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
652 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
653 | mc->real_vram_size = mc->aper_size; | |
654 | mc->mc_vram_size = mc->aper_size; | |
655 | } | |
656 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
657 | if (limit && limit < mc->real_vram_size) | |
658 | mc->real_vram_size = limit; | |
659 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
660 | mc->mc_vram_size >> 20, mc->vram_start, | |
661 | mc->vram_end, mc->real_vram_size >> 20); | |
662 | } | |
663 | ||
664 | /** | |
665 | * amdgpu_gtt_location - try to find GTT location | |
666 | * @adev: amdgpu device structure holding all necessary informations | |
667 | * @mc: memory controller structure holding memory informations | |
668 | * | |
669 | * Function will place try to place GTT before or after VRAM. | |
670 | * | |
671 | * If GTT size is bigger than space left then we ajust GTT size. | |
672 | * Thus function will never fails. | |
673 | * | |
674 | * FIXME: when reducing GTT size align new size on power of 2. | |
675 | */ | |
676 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
677 | { | |
678 | u64 size_af, size_bf; | |
679 | ||
680 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
681 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
682 | if (size_bf > size_af) { | |
683 | if (mc->gtt_size > size_bf) { | |
684 | dev_warn(adev->dev, "limiting GTT\n"); | |
685 | mc->gtt_size = size_bf; | |
686 | } | |
9dc5a91e | 687 | mc->gtt_start = 0; |
d38ceaf9 AD |
688 | } else { |
689 | if (mc->gtt_size > size_af) { | |
690 | dev_warn(adev->dev, "limiting GTT\n"); | |
691 | mc->gtt_size = size_af; | |
692 | } | |
693 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
694 | } | |
695 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
696 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
697 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
698 | } | |
699 | ||
700 | /* | |
701 | * GPU helpers function. | |
702 | */ | |
703 | /** | |
c836fec5 | 704 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
705 | * |
706 | * @adev: amdgpu_device pointer | |
707 | * | |
c836fec5 JQ |
708 | * Check if the asic has been initialized (all asics) at driver startup |
709 | * or post is needed if hw reset is performed. | |
710 | * Returns true if need or false if not. | |
d38ceaf9 | 711 | */ |
c836fec5 | 712 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
713 | { |
714 | uint32_t reg; | |
715 | ||
c836fec5 JQ |
716 | if (adev->has_hw_reset) { |
717 | adev->has_hw_reset = false; | |
718 | return true; | |
719 | } | |
d38ceaf9 | 720 | /* then check MEM_SIZE, in case the crtcs are off */ |
bbf282d8 | 721 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 | 722 | |
f2713e8c | 723 | if ((reg != 0) && (reg != 0xffffffff)) |
c836fec5 | 724 | return false; |
d38ceaf9 | 725 | |
c836fec5 | 726 | return true; |
d38ceaf9 AD |
727 | |
728 | } | |
729 | ||
bec86378 ML |
730 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
731 | { | |
732 | if (amdgpu_sriov_vf(adev)) | |
733 | return false; | |
734 | ||
735 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
736 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
737 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
738 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
739 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
740 | */ |
741 | if (adev->asic_type == CHIP_FIJI) { | |
742 | int err; | |
743 | uint32_t fw_ver; | |
744 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
745 | /* force vPost if error occured */ | |
746 | if (err) | |
747 | return true; | |
748 | ||
749 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
750 | if (fw_ver < 0x00160e00) |
751 | return true; | |
bec86378 | 752 | } |
bec86378 | 753 | } |
c836fec5 | 754 | return amdgpu_need_post(adev); |
bec86378 ML |
755 | } |
756 | ||
d38ceaf9 AD |
757 | /** |
758 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
759 | * | |
760 | * @adev: amdgpu_device pointer | |
761 | * | |
762 | * Allocate the dummy page used by the driver (all asics). | |
763 | * This dummy page is used by the driver as a filler for gart entries | |
764 | * when pages are taken out of the GART | |
765 | * Returns 0 on sucess, -ENOMEM on failure. | |
766 | */ | |
767 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
768 | { | |
769 | if (adev->dummy_page.page) | |
770 | return 0; | |
771 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
772 | if (adev->dummy_page.page == NULL) | |
773 | return -ENOMEM; | |
774 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
775 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
776 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
777 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
778 | __free_page(adev->dummy_page.page); | |
779 | adev->dummy_page.page = NULL; | |
780 | return -ENOMEM; | |
781 | } | |
782 | return 0; | |
783 | } | |
784 | ||
785 | /** | |
786 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
787 | * | |
788 | * @adev: amdgpu_device pointer | |
789 | * | |
790 | * Frees the dummy page used by the driver (all asics). | |
791 | */ | |
792 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
793 | { | |
794 | if (adev->dummy_page.page == NULL) | |
795 | return; | |
796 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
797 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
798 | __free_page(adev->dummy_page.page); | |
799 | adev->dummy_page.page = NULL; | |
800 | } | |
801 | ||
802 | ||
803 | /* ATOM accessor methods */ | |
804 | /* | |
805 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
806 | * driver registers callbacks to access registers and the interpreter | |
807 | * in the driver parses the tables and executes then to program specific | |
808 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
809 | * atombios.h, and atom.c | |
810 | */ | |
811 | ||
812 | /** | |
813 | * cail_pll_read - read PLL register | |
814 | * | |
815 | * @info: atom card_info pointer | |
816 | * @reg: PLL register offset | |
817 | * | |
818 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
819 | * Returns the value of the PLL register. | |
820 | */ | |
821 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
822 | { | |
823 | return 0; | |
824 | } | |
825 | ||
826 | /** | |
827 | * cail_pll_write - write PLL register | |
828 | * | |
829 | * @info: atom card_info pointer | |
830 | * @reg: PLL register offset | |
831 | * @val: value to write to the pll register | |
832 | * | |
833 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
834 | */ | |
835 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
836 | { | |
837 | ||
838 | } | |
839 | ||
840 | /** | |
841 | * cail_mc_read - read MC (Memory Controller) register | |
842 | * | |
843 | * @info: atom card_info pointer | |
844 | * @reg: MC register offset | |
845 | * | |
846 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
847 | * Returns the value of the MC register. | |
848 | */ | |
849 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
850 | { | |
851 | return 0; | |
852 | } | |
853 | ||
854 | /** | |
855 | * cail_mc_write - write MC (Memory Controller) register | |
856 | * | |
857 | * @info: atom card_info pointer | |
858 | * @reg: MC register offset | |
859 | * @val: value to write to the pll register | |
860 | * | |
861 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
862 | */ | |
863 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
864 | { | |
865 | ||
866 | } | |
867 | ||
868 | /** | |
869 | * cail_reg_write - write MMIO register | |
870 | * | |
871 | * @info: atom card_info pointer | |
872 | * @reg: MMIO register offset | |
873 | * @val: value to write to the pll register | |
874 | * | |
875 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
876 | */ | |
877 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
878 | { | |
879 | struct amdgpu_device *adev = info->dev->dev_private; | |
880 | ||
881 | WREG32(reg, val); | |
882 | } | |
883 | ||
884 | /** | |
885 | * cail_reg_read - read MMIO register | |
886 | * | |
887 | * @info: atom card_info pointer | |
888 | * @reg: MMIO register offset | |
889 | * | |
890 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
891 | * Returns the value of the MMIO register. | |
892 | */ | |
893 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
894 | { | |
895 | struct amdgpu_device *adev = info->dev->dev_private; | |
896 | uint32_t r; | |
897 | ||
898 | r = RREG32(reg); | |
899 | return r; | |
900 | } | |
901 | ||
902 | /** | |
903 | * cail_ioreg_write - write IO register | |
904 | * | |
905 | * @info: atom card_info pointer | |
906 | * @reg: IO register offset | |
907 | * @val: value to write to the pll register | |
908 | * | |
909 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
910 | */ | |
911 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
912 | { | |
913 | struct amdgpu_device *adev = info->dev->dev_private; | |
914 | ||
915 | WREG32_IO(reg, val); | |
916 | } | |
917 | ||
918 | /** | |
919 | * cail_ioreg_read - read IO register | |
920 | * | |
921 | * @info: atom card_info pointer | |
922 | * @reg: IO register offset | |
923 | * | |
924 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
925 | * Returns the value of the IO register. | |
926 | */ | |
927 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
928 | { | |
929 | struct amdgpu_device *adev = info->dev->dev_private; | |
930 | uint32_t r; | |
931 | ||
932 | r = RREG32_IO(reg); | |
933 | return r; | |
934 | } | |
935 | ||
936 | /** | |
937 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
938 | * | |
939 | * @adev: amdgpu_device pointer | |
940 | * | |
941 | * Frees the driver info and register access callbacks for the ATOM | |
942 | * interpreter (r4xx+). | |
943 | * Called at driver shutdown. | |
944 | */ | |
945 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
946 | { | |
89e0ec9f | 947 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 948 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
949 | kfree(adev->mode_info.atom_context->iio); |
950 | } | |
d38ceaf9 AD |
951 | kfree(adev->mode_info.atom_context); |
952 | adev->mode_info.atom_context = NULL; | |
953 | kfree(adev->mode_info.atom_card_info); | |
954 | adev->mode_info.atom_card_info = NULL; | |
955 | } | |
956 | ||
957 | /** | |
958 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
959 | * | |
960 | * @adev: amdgpu_device pointer | |
961 | * | |
962 | * Initializes the driver info and register access callbacks for the | |
963 | * ATOM interpreter (r4xx+). | |
964 | * Returns 0 on sucess, -ENOMEM on failure. | |
965 | * Called at driver startup. | |
966 | */ | |
967 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
968 | { | |
969 | struct card_info *atom_card_info = | |
970 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
971 | ||
972 | if (!atom_card_info) | |
973 | return -ENOMEM; | |
974 | ||
975 | adev->mode_info.atom_card_info = atom_card_info; | |
976 | atom_card_info->dev = adev->ddev; | |
977 | atom_card_info->reg_read = cail_reg_read; | |
978 | atom_card_info->reg_write = cail_reg_write; | |
979 | /* needed for iio ops */ | |
980 | if (adev->rio_mem) { | |
981 | atom_card_info->ioreg_read = cail_ioreg_read; | |
982 | atom_card_info->ioreg_write = cail_ioreg_write; | |
983 | } else { | |
b64a18c5 | 984 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
985 | atom_card_info->ioreg_read = cail_reg_read; |
986 | atom_card_info->ioreg_write = cail_reg_write; | |
987 | } | |
988 | atom_card_info->mc_read = cail_mc_read; | |
989 | atom_card_info->mc_write = cail_mc_write; | |
990 | atom_card_info->pll_read = cail_pll_read; | |
991 | atom_card_info->pll_write = cail_pll_write; | |
992 | ||
993 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
994 | if (!adev->mode_info.atom_context) { | |
995 | amdgpu_atombios_fini(adev); | |
996 | return -ENOMEM; | |
997 | } | |
998 | ||
999 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1000 | if (adev->is_atom_fw) { |
1001 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1002 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1003 | } else { | |
1004 | amdgpu_atombios_scratch_regs_init(adev); | |
1005 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1006 | } | |
d38ceaf9 AD |
1007 | return 0; |
1008 | } | |
1009 | ||
1010 | /* if we get transitioned to only one device, take VGA back */ | |
1011 | /** | |
1012 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1013 | * | |
1014 | * @cookie: amdgpu_device pointer | |
1015 | * @state: enable/disable vga decode | |
1016 | * | |
1017 | * Enable/disable vga decode (all asics). | |
1018 | * Returns VGA resource flags. | |
1019 | */ | |
1020 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1021 | { | |
1022 | struct amdgpu_device *adev = cookie; | |
1023 | amdgpu_asic_set_vga_state(adev, state); | |
1024 | if (state) | |
1025 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1026 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1027 | else | |
1028 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1029 | } | |
1030 | ||
1031 | /** | |
1032 | * amdgpu_check_pot_argument - check that argument is a power of two | |
1033 | * | |
1034 | * @arg: value to check | |
1035 | * | |
1036 | * Validates that a certain argument is a power of two (all asics). | |
1037 | * Returns true if argument is valid. | |
1038 | */ | |
1039 | static bool amdgpu_check_pot_argument(int arg) | |
1040 | { | |
1041 | return (arg & (arg - 1)) == 0; | |
1042 | } | |
1043 | ||
bab4fee7 | 1044 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1045 | { |
1046 | /* defines number of bits in page table versus page directory, | |
1047 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1048 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1049 | if (amdgpu_vm_block_size == -1) |
1050 | return; | |
a1adf8be | 1051 | |
bab4fee7 | 1052 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1053 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1054 | amdgpu_vm_block_size); | |
bab4fee7 | 1055 | goto def_value; |
a1adf8be CZ |
1056 | } |
1057 | ||
1058 | if (amdgpu_vm_block_size > 24 || | |
1059 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1060 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1061 | amdgpu_vm_block_size); | |
bab4fee7 | 1062 | goto def_value; |
a1adf8be | 1063 | } |
bab4fee7 JZ |
1064 | |
1065 | return; | |
1066 | ||
1067 | def_value: | |
1068 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1069 | } |
1070 | ||
83ca145d ZJ |
1071 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1072 | { | |
1073 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
1074 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
1075 | amdgpu_vm_size); | |
1076 | goto def_value; | |
1077 | } | |
1078 | ||
1079 | if (amdgpu_vm_size < 1) { | |
1080 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1081 | amdgpu_vm_size); | |
1082 | goto def_value; | |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1087 | */ | |
1088 | if (amdgpu_vm_size > 1024) { | |
1089 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1090 | amdgpu_vm_size); | |
1091 | goto def_value; | |
1092 | } | |
1093 | ||
1094 | return; | |
1095 | ||
1096 | def_value: | |
bab4fee7 | 1097 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1098 | } |
1099 | ||
d38ceaf9 AD |
1100 | /** |
1101 | * amdgpu_check_arguments - validate module params | |
1102 | * | |
1103 | * @adev: amdgpu_device pointer | |
1104 | * | |
1105 | * Validates certain module parameters and updates | |
1106 | * the associated values used by the driver (all asics). | |
1107 | */ | |
1108 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1109 | { | |
5b011235 CZ |
1110 | if (amdgpu_sched_jobs < 4) { |
1111 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1112 | amdgpu_sched_jobs); | |
1113 | amdgpu_sched_jobs = 4; | |
1114 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
1115 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
1116 | amdgpu_sched_jobs); | |
1117 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1118 | } | |
d38ceaf9 AD |
1119 | |
1120 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 1121 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
1122 | if (amdgpu_gart_size < 32) { |
1123 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1124 | amdgpu_gart_size); | |
1125 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
1126 | } |
1127 | } | |
1128 | ||
83ca145d | 1129 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1130 | |
bab4fee7 | 1131 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1132 | |
526bae37 | 1133 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
1134 | !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { | |
6a7f76e7 CK |
1135 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1136 | amdgpu_vram_page_split); | |
1137 | amdgpu_vram_page_split = 1024; | |
1138 | } | |
d38ceaf9 AD |
1139 | } |
1140 | ||
1141 | /** | |
1142 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1143 | * | |
1144 | * @pdev: pci dev pointer | |
1694467b | 1145 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1146 | * |
1147 | * Callback for the switcheroo driver. Suspends or resumes the | |
1148 | * the asics before or after it is powered up using ACPI methods. | |
1149 | */ | |
1150 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1151 | { | |
1152 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1153 | ||
1154 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1155 | return; | |
1156 | ||
1157 | if (state == VGA_SWITCHEROO_ON) { | |
1158 | unsigned d3_delay = dev->pdev->d3_delay; | |
1159 | ||
7ca85295 | 1160 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1161 | /* don't suspend or resume card normally */ |
1162 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1163 | ||
810ddc3a | 1164 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1165 | |
1166 | dev->pdev->d3_delay = d3_delay; | |
1167 | ||
1168 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1169 | drm_kms_helper_poll_enable(dev); | |
1170 | } else { | |
7ca85295 | 1171 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1172 | drm_kms_helper_poll_disable(dev); |
1173 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1174 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1175 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1176 | } | |
1177 | } | |
1178 | ||
1179 | /** | |
1180 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1181 | * | |
1182 | * @pdev: pci dev pointer | |
1183 | * | |
1184 | * Callback for the switcheroo driver. Check of the switcheroo | |
1185 | * state can be changed. | |
1186 | * Returns true if the state can be changed, false if not. | |
1187 | */ | |
1188 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1189 | { | |
1190 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1191 | ||
1192 | /* | |
1193 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1194 | * locking inversion with the driver load path. And the access here is | |
1195 | * completely racy anyway. So don't bother with locking for now. | |
1196 | */ | |
1197 | return dev->open_count == 0; | |
1198 | } | |
1199 | ||
1200 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1201 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1202 | .reprobe = NULL, | |
1203 | .can_switch = amdgpu_switcheroo_can_switch, | |
1204 | }; | |
1205 | ||
1206 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1207 | enum amd_ip_block_type block_type, |
1208 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1209 | { |
1210 | int i, r = 0; | |
1211 | ||
1212 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1213 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1214 | continue; |
c722865a RZ |
1215 | if (adev->ip_blocks[i].version->type != block_type) |
1216 | continue; | |
1217 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1218 | continue; | |
1219 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1220 | (void *)adev, state); | |
1221 | if (r) | |
1222 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1223 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1224 | } |
1225 | return r; | |
1226 | } | |
1227 | ||
1228 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1229 | enum amd_ip_block_type block_type, |
1230 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1231 | { |
1232 | int i, r = 0; | |
1233 | ||
1234 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1235 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1236 | continue; |
c722865a RZ |
1237 | if (adev->ip_blocks[i].version->type != block_type) |
1238 | continue; | |
1239 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1240 | continue; | |
1241 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1242 | (void *)adev, state); | |
1243 | if (r) | |
1244 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1245 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1246 | } |
1247 | return r; | |
1248 | } | |
1249 | ||
6cb2d4e4 HR |
1250 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1251 | { | |
1252 | int i; | |
1253 | ||
1254 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1255 | if (!adev->ip_blocks[i].status.valid) | |
1256 | continue; | |
1257 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1258 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1259 | } | |
1260 | } | |
1261 | ||
5dbbb60b AD |
1262 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1263 | enum amd_ip_block_type block_type) | |
1264 | { | |
1265 | int i, r; | |
1266 | ||
1267 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1268 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1269 | continue; |
a1255107 AD |
1270 | if (adev->ip_blocks[i].version->type == block_type) { |
1271 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1272 | if (r) |
1273 | return r; | |
1274 | break; | |
1275 | } | |
1276 | } | |
1277 | return 0; | |
1278 | ||
1279 | } | |
1280 | ||
1281 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1282 | enum amd_ip_block_type block_type) | |
1283 | { | |
1284 | int i; | |
1285 | ||
1286 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1287 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1288 | continue; |
a1255107 AD |
1289 | if (adev->ip_blocks[i].version->type == block_type) |
1290 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1291 | } |
1292 | return true; | |
1293 | ||
1294 | } | |
1295 | ||
a1255107 AD |
1296 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1297 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1298 | { |
1299 | int i; | |
1300 | ||
1301 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1302 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1303 | return &adev->ip_blocks[i]; |
1304 | ||
1305 | return NULL; | |
1306 | } | |
1307 | ||
1308 | /** | |
1309 | * amdgpu_ip_block_version_cmp | |
1310 | * | |
1311 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1312 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1313 | * @major: major version |
1314 | * @minor: minor version | |
1315 | * | |
1316 | * return 0 if equal or greater | |
1317 | * return 1 if smaller or the ip_block doesn't exist | |
1318 | */ | |
1319 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1320 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1321 | u32 major, u32 minor) |
1322 | { | |
a1255107 | 1323 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1324 | |
a1255107 AD |
1325 | if (ip_block && ((ip_block->version->major > major) || |
1326 | ((ip_block->version->major == major) && | |
1327 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1328 | return 0; |
1329 | ||
1330 | return 1; | |
1331 | } | |
1332 | ||
a1255107 AD |
1333 | /** |
1334 | * amdgpu_ip_block_add | |
1335 | * | |
1336 | * @adev: amdgpu_device pointer | |
1337 | * @ip_block_version: pointer to the IP to add | |
1338 | * | |
1339 | * Adds the IP block driver information to the collection of IPs | |
1340 | * on the asic. | |
1341 | */ | |
1342 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1343 | const struct amdgpu_ip_block_version *ip_block_version) | |
1344 | { | |
1345 | if (!ip_block_version) | |
1346 | return -EINVAL; | |
1347 | ||
1348 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; | |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
483ef985 | 1353 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1354 | { |
1355 | adev->enable_virtual_display = false; | |
1356 | ||
1357 | if (amdgpu_virtual_display) { | |
1358 | struct drm_device *ddev = adev->ddev; | |
1359 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1360 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1361 | |
1362 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1363 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1364 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1365 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1366 | if (!strcmp("all", pciaddname) |
1367 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1368 | long num_crtc; |
1369 | int res = -1; | |
1370 | ||
9accf2fd | 1371 | adev->enable_virtual_display = true; |
0f66356d ED |
1372 | |
1373 | if (pciaddname_tmp) | |
1374 | res = kstrtol(pciaddname_tmp, 10, | |
1375 | &num_crtc); | |
1376 | ||
1377 | if (!res) { | |
1378 | if (num_crtc < 1) | |
1379 | num_crtc = 1; | |
1380 | if (num_crtc > 6) | |
1381 | num_crtc = 6; | |
1382 | adev->mode_info.num_crtc = num_crtc; | |
1383 | } else { | |
1384 | adev->mode_info.num_crtc = 1; | |
1385 | } | |
9accf2fd ED |
1386 | break; |
1387 | } | |
1388 | } | |
1389 | ||
0f66356d ED |
1390 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1391 | amdgpu_virtual_display, pci_address_name, | |
1392 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1393 | |
1394 | kfree(pciaddstr); | |
1395 | } | |
1396 | } | |
1397 | ||
e2a75f88 AD |
1398 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1399 | { | |
1400 | const struct firmware *fw; | |
1401 | const char *chip_name; | |
1402 | char fw_name[30]; | |
1403 | int err; | |
1404 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1405 | ||
1406 | switch (adev->asic_type) { | |
1407 | case CHIP_TOPAZ: | |
1408 | case CHIP_TONGA: | |
1409 | case CHIP_FIJI: | |
1410 | case CHIP_POLARIS11: | |
1411 | case CHIP_POLARIS10: | |
1412 | case CHIP_POLARIS12: | |
1413 | case CHIP_CARRIZO: | |
1414 | case CHIP_STONEY: | |
1415 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1416 | case CHIP_VERDE: | |
1417 | case CHIP_TAHITI: | |
1418 | case CHIP_PITCAIRN: | |
1419 | case CHIP_OLAND: | |
1420 | case CHIP_HAINAN: | |
1421 | #endif | |
1422 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1423 | case CHIP_BONAIRE: | |
1424 | case CHIP_HAWAII: | |
1425 | case CHIP_KAVERI: | |
1426 | case CHIP_KABINI: | |
1427 | case CHIP_MULLINS: | |
1428 | #endif | |
1429 | default: | |
1430 | return 0; | |
1431 | case CHIP_VEGA10: | |
1432 | chip_name = "vega10"; | |
1433 | break; | |
2d2e5e7e AD |
1434 | case CHIP_RAVEN: |
1435 | chip_name = "raven"; | |
1436 | break; | |
e2a75f88 AD |
1437 | } |
1438 | ||
1439 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
1440 | err = request_firmware(&fw, fw_name, adev->dev); | |
1441 | if (err) { | |
1442 | dev_err(adev->dev, | |
1443 | "Failed to load gpu_info firmware \"%s\"\n", | |
1444 | fw_name); | |
1445 | goto out; | |
1446 | } | |
1447 | err = amdgpu_ucode_validate(fw); | |
1448 | if (err) { | |
1449 | dev_err(adev->dev, | |
1450 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1451 | fw_name); | |
1452 | goto out; | |
1453 | } | |
1454 | ||
1455 | hdr = (const struct gpu_info_firmware_header_v1_0 *)fw->data; | |
1456 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); | |
1457 | ||
1458 | switch (hdr->version_major) { | |
1459 | case 1: | |
1460 | { | |
1461 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
1462 | (const struct gpu_info_firmware_v1_0 *)(fw->data + | |
1463 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1464 | ||
1465 | adev->gfx.config.max_shader_engines = gpu_info_fw->gc_num_se; | |
1466 | adev->gfx.config.max_cu_per_sh = gpu_info_fw->gc_num_cu_per_sh; | |
1467 | adev->gfx.config.max_sh_per_se = gpu_info_fw->gc_num_sh_per_se; | |
1468 | adev->gfx.config.max_backends_per_se = gpu_info_fw->gc_num_rb_per_se; | |
1469 | adev->gfx.config.max_texture_channel_caches = | |
1470 | gpu_info_fw->gc_num_tccs; | |
1471 | adev->gfx.config.max_gprs = gpu_info_fw->gc_num_gprs; | |
1472 | adev->gfx.config.max_gs_threads = gpu_info_fw->gc_num_max_gs_thds; | |
1473 | adev->gfx.config.gs_vgt_table_depth = gpu_info_fw->gc_gs_table_depth; | |
1474 | adev->gfx.config.gs_prim_buffer_depth = gpu_info_fw->gc_gsprim_buff_depth; | |
1475 | adev->gfx.config.double_offchip_lds_buf = | |
1476 | gpu_info_fw->gc_double_offchip_lds_buffer; | |
1477 | adev->gfx.cu_info.wave_front_size = gpu_info_fw->gc_wave_size; | |
1478 | break; | |
1479 | } | |
1480 | default: | |
1481 | dev_err(adev->dev, | |
1482 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1483 | err = -EINVAL; | |
1484 | goto out; | |
1485 | } | |
1486 | out: | |
1487 | release_firmware(fw); | |
1488 | fw = NULL; | |
1489 | ||
1490 | return err; | |
1491 | } | |
1492 | ||
d38ceaf9 AD |
1493 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1494 | { | |
aaa36a97 | 1495 | int i, r; |
d38ceaf9 | 1496 | |
483ef985 | 1497 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1498 | |
d38ceaf9 | 1499 | switch (adev->asic_type) { |
aaa36a97 AD |
1500 | case CHIP_TOPAZ: |
1501 | case CHIP_TONGA: | |
48299f95 | 1502 | case CHIP_FIJI: |
2cc0c0b5 FC |
1503 | case CHIP_POLARIS11: |
1504 | case CHIP_POLARIS10: | |
c4642a47 | 1505 | case CHIP_POLARIS12: |
aaa36a97 | 1506 | case CHIP_CARRIZO: |
39bb0c92 SL |
1507 | case CHIP_STONEY: |
1508 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1509 | adev->family = AMDGPU_FAMILY_CZ; |
1510 | else | |
1511 | adev->family = AMDGPU_FAMILY_VI; | |
1512 | ||
1513 | r = vi_set_ip_blocks(adev); | |
1514 | if (r) | |
1515 | return r; | |
1516 | break; | |
33f34802 KW |
1517 | #ifdef CONFIG_DRM_AMDGPU_SI |
1518 | case CHIP_VERDE: | |
1519 | case CHIP_TAHITI: | |
1520 | case CHIP_PITCAIRN: | |
1521 | case CHIP_OLAND: | |
1522 | case CHIP_HAINAN: | |
295d0daf | 1523 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1524 | r = si_set_ip_blocks(adev); |
1525 | if (r) | |
1526 | return r; | |
1527 | break; | |
1528 | #endif | |
a2e73f56 AD |
1529 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1530 | case CHIP_BONAIRE: | |
1531 | case CHIP_HAWAII: | |
1532 | case CHIP_KAVERI: | |
1533 | case CHIP_KABINI: | |
1534 | case CHIP_MULLINS: | |
1535 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1536 | adev->family = AMDGPU_FAMILY_CI; | |
1537 | else | |
1538 | adev->family = AMDGPU_FAMILY_KV; | |
1539 | ||
1540 | r = cik_set_ip_blocks(adev); | |
1541 | if (r) | |
1542 | return r; | |
1543 | break; | |
1544 | #endif | |
2ca8a5d2 CZ |
1545 | case CHIP_VEGA10: |
1546 | case CHIP_RAVEN: | |
1547 | if (adev->asic_type == CHIP_RAVEN) | |
1548 | adev->family = AMDGPU_FAMILY_RV; | |
1549 | else | |
1550 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1551 | |
1552 | r = soc15_set_ip_blocks(adev); | |
1553 | if (r) | |
1554 | return r; | |
1555 | break; | |
d38ceaf9 AD |
1556 | default: |
1557 | /* FIXME: not supported yet */ | |
1558 | return -EINVAL; | |
1559 | } | |
1560 | ||
e2a75f88 AD |
1561 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1562 | if (r) | |
1563 | return r; | |
1564 | ||
3149d9da XY |
1565 | if (amdgpu_sriov_vf(adev)) { |
1566 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1567 | if (r) | |
1568 | return r; | |
1569 | } | |
1570 | ||
d38ceaf9 AD |
1571 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1572 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1573 | DRM_ERROR("disabled ip block: %d\n", i); | |
a1255107 | 1574 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1575 | } else { |
a1255107 AD |
1576 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1577 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1578 | if (r == -ENOENT) { |
a1255107 | 1579 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1580 | } else if (r) { |
a1255107 AD |
1581 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1582 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1583 | return r; |
2c1a2784 | 1584 | } else { |
a1255107 | 1585 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1586 | } |
974e6b64 | 1587 | } else { |
a1255107 | 1588 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1589 | } |
d38ceaf9 AD |
1590 | } |
1591 | } | |
1592 | ||
395d1fb9 NH |
1593 | adev->cg_flags &= amdgpu_cg_mask; |
1594 | adev->pg_flags &= amdgpu_pg_mask; | |
1595 | ||
d38ceaf9 AD |
1596 | return 0; |
1597 | } | |
1598 | ||
1599 | static int amdgpu_init(struct amdgpu_device *adev) | |
1600 | { | |
1601 | int i, r; | |
1602 | ||
1603 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1604 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1605 | continue; |
a1255107 | 1606 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1607 | if (r) { |
a1255107 AD |
1608 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1609 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1610 | return r; |
2c1a2784 | 1611 | } |
a1255107 | 1612 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1613 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1614 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1615 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1616 | if (r) { |
1617 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1618 | return r; |
2c1a2784 | 1619 | } |
a1255107 | 1620 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1621 | if (r) { |
1622 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1623 | return r; |
2c1a2784 | 1624 | } |
d38ceaf9 | 1625 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1626 | if (r) { |
1627 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1628 | return r; |
2c1a2784 | 1629 | } |
a1255107 | 1630 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1631 | |
1632 | /* right after GMC hw init, we create CSA */ | |
1633 | if (amdgpu_sriov_vf(adev)) { | |
1634 | r = amdgpu_allocate_static_csa(adev); | |
1635 | if (r) { | |
1636 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1637 | return r; | |
1638 | } | |
1639 | } | |
d38ceaf9 AD |
1640 | } |
1641 | } | |
1642 | ||
1643 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1644 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1645 | continue; |
1646 | /* gmc hw init is done early */ | |
a1255107 | 1647 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1648 | continue; |
a1255107 | 1649 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1650 | if (r) { |
a1255107 AD |
1651 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1652 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1653 | return r; |
2c1a2784 | 1654 | } |
a1255107 | 1655 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1656 | } |
1657 | ||
1658 | return 0; | |
1659 | } | |
1660 | ||
1661 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1662 | { | |
1663 | int i = 0, r; | |
1664 | ||
1665 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1666 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1667 | continue; |
a1255107 AD |
1668 | if (adev->ip_blocks[i].version->funcs->late_init) { |
1669 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2c1a2784 | 1670 | if (r) { |
a1255107 AD |
1671 | DRM_ERROR("late_init of IP block <%s> failed %d\n", |
1672 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1673 | return r; |
2c1a2784 | 1674 | } |
a1255107 | 1675 | adev->ip_blocks[i].status.late_initialized = true; |
d38ceaf9 | 1676 | } |
4a446d55 | 1677 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1678 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1679 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1680 | /* enable clockgating to save power */ |
a1255107 AD |
1681 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1682 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1683 | if (r) { |
1684 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1685 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1686 | return r; |
1687 | } | |
b0b00ff1 | 1688 | } |
d38ceaf9 AD |
1689 | } |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1695 | { | |
1696 | int i, r; | |
1697 | ||
3e96dbfd AD |
1698 | /* need to disable SMC first */ |
1699 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1700 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1701 | continue; |
a1255107 | 1702 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1703 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1704 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1705 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1706 | if (r) { |
1707 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1708 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1709 | return r; |
1710 | } | |
a1255107 | 1711 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1712 | /* XXX handle errors */ |
1713 | if (r) { | |
1714 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1715 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1716 | } |
a1255107 | 1717 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1718 | break; |
1719 | } | |
1720 | } | |
1721 | ||
d38ceaf9 | 1722 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1723 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1724 | continue; |
a1255107 | 1725 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1726 | amdgpu_wb_fini(adev); |
1727 | amdgpu_vram_scratch_fini(adev); | |
1728 | } | |
8201a67a RZ |
1729 | |
1730 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1731 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1732 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1733 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1734 | AMD_CG_STATE_UNGATE); | |
1735 | if (r) { | |
1736 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1737 | adev->ip_blocks[i].version->funcs->name, r); | |
1738 | return r; | |
1739 | } | |
2c1a2784 | 1740 | } |
8201a67a | 1741 | |
a1255107 | 1742 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1743 | /* XXX handle errors */ |
2c1a2784 | 1744 | if (r) { |
a1255107 AD |
1745 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1746 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1747 | } |
8201a67a | 1748 | |
a1255107 | 1749 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1750 | } |
1751 | ||
1752 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1753 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1754 | continue; |
a1255107 | 1755 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1756 | /* XXX handle errors */ |
2c1a2784 | 1757 | if (r) { |
a1255107 AD |
1758 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1759 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1760 | } |
a1255107 AD |
1761 | adev->ip_blocks[i].status.sw = false; |
1762 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1763 | } |
1764 | ||
a6dcfd9c | 1765 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1766 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1767 | continue; |
a1255107 AD |
1768 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1769 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1770 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1771 | } |
1772 | ||
3149d9da | 1773 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1774 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1775 | amdgpu_virt_release_full_gpu(adev, false); |
1776 | } | |
2493664f | 1777 | |
d38ceaf9 AD |
1778 | return 0; |
1779 | } | |
1780 | ||
faefba95 | 1781 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1782 | { |
1783 | int i, r; | |
1784 | ||
e941ea99 XY |
1785 | if (amdgpu_sriov_vf(adev)) |
1786 | amdgpu_virt_request_full_gpu(adev, false); | |
1787 | ||
c5a93a28 FC |
1788 | /* ungate SMC block first */ |
1789 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1790 | AMD_CG_STATE_UNGATE); | |
1791 | if (r) { | |
1792 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1793 | } | |
1794 | ||
d38ceaf9 | 1795 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1796 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1797 | continue; |
1798 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1799 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1800 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1801 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1802 | if (r) { |
a1255107 AD |
1803 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1804 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1805 | } |
2c1a2784 | 1806 | } |
d38ceaf9 | 1807 | /* XXX handle errors */ |
a1255107 | 1808 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1809 | /* XXX handle errors */ |
2c1a2784 | 1810 | if (r) { |
a1255107 AD |
1811 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1812 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1813 | } |
d38ceaf9 AD |
1814 | } |
1815 | ||
e941ea99 XY |
1816 | if (amdgpu_sriov_vf(adev)) |
1817 | amdgpu_virt_release_full_gpu(adev, false); | |
1818 | ||
d38ceaf9 AD |
1819 | return 0; |
1820 | } | |
1821 | ||
e4f0fdcc | 1822 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1823 | { |
1824 | int i, r; | |
1825 | ||
2cb681b6 ML |
1826 | static enum amd_ip_block_type ip_order[] = { |
1827 | AMD_IP_BLOCK_TYPE_GMC, | |
1828 | AMD_IP_BLOCK_TYPE_COMMON, | |
1829 | AMD_IP_BLOCK_TYPE_GFXHUB, | |
1830 | AMD_IP_BLOCK_TYPE_MMHUB, | |
1831 | AMD_IP_BLOCK_TYPE_IH, | |
1832 | }; | |
1833 | ||
1834 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { | |
1835 | int j; | |
1836 | struct amdgpu_ip_block *block; | |
1837 | ||
1838 | for (j = 0; j < adev->num_ip_blocks; j++) { | |
1839 | block = &adev->ip_blocks[j]; | |
1840 | ||
1841 | if (block->version->type != ip_order[i] || | |
1842 | !block->status.valid) | |
1843 | continue; | |
1844 | ||
1845 | r = block->version->funcs->hw_init(adev); | |
1846 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1847 | } |
1848 | } | |
1849 | ||
1850 | return 0; | |
1851 | } | |
1852 | ||
e4f0fdcc | 1853 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1854 | { |
1855 | int i, r; | |
1856 | ||
2cb681b6 ML |
1857 | static enum amd_ip_block_type ip_order[] = { |
1858 | AMD_IP_BLOCK_TYPE_SMC, | |
1859 | AMD_IP_BLOCK_TYPE_DCE, | |
1860 | AMD_IP_BLOCK_TYPE_GFX, | |
1861 | AMD_IP_BLOCK_TYPE_SDMA, | |
1862 | AMD_IP_BLOCK_TYPE_VCE, | |
1863 | }; | |
a90ad3c2 | 1864 | |
2cb681b6 ML |
1865 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1866 | int j; | |
1867 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1868 | |
2cb681b6 ML |
1869 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1870 | block = &adev->ip_blocks[j]; | |
1871 | ||
1872 | if (block->version->type != ip_order[i] || | |
1873 | !block->status.valid) | |
1874 | continue; | |
1875 | ||
1876 | r = block->version->funcs->hw_init(adev); | |
1877 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1878 | } |
1879 | } | |
1880 | ||
1881 | return 0; | |
1882 | } | |
1883 | ||
fcf0649f | 1884 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1885 | { |
1886 | int i, r; | |
1887 | ||
1888 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1889 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1890 | continue; |
fcf0649f CZ |
1891 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1892 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1893 | adev->ip_blocks[i].version->type == | |
1894 | AMD_IP_BLOCK_TYPE_IH) { | |
1895 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1896 | if (r) { | |
1897 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1898 | adev->ip_blocks[i].version->funcs->name, r); | |
1899 | return r; | |
1900 | } | |
1901 | } | |
1902 | } | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) | |
1908 | { | |
1909 | int i, r; | |
1910 | ||
1911 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1912 | if (!adev->ip_blocks[i].status.valid) | |
1913 | continue; | |
1914 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1915 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1916 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1917 | continue; | |
a1255107 | 1918 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1919 | if (r) { |
a1255107 AD |
1920 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1921 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1922 | return r; |
2c1a2784 | 1923 | } |
d38ceaf9 AD |
1924 | } |
1925 | ||
1926 | return 0; | |
1927 | } | |
1928 | ||
fcf0649f CZ |
1929 | static int amdgpu_resume(struct amdgpu_device *adev) |
1930 | { | |
1931 | int r; | |
1932 | ||
1933 | r = amdgpu_resume_phase1(adev); | |
1934 | if (r) | |
1935 | return r; | |
1936 | r = amdgpu_resume_phase2(adev); | |
1937 | ||
1938 | return r; | |
1939 | } | |
1940 | ||
4e99a44e | 1941 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1942 | { |
a5bde2f9 AD |
1943 | if (adev->is_atom_fw) { |
1944 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
1945 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1946 | } else { | |
1947 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
1948 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1949 | } | |
048765ad AR |
1950 | } |
1951 | ||
d38ceaf9 AD |
1952 | /** |
1953 | * amdgpu_device_init - initialize the driver | |
1954 | * | |
1955 | * @adev: amdgpu_device pointer | |
1956 | * @pdev: drm dev pointer | |
1957 | * @pdev: pci dev pointer | |
1958 | * @flags: driver flags | |
1959 | * | |
1960 | * Initializes the driver info and hw (all asics). | |
1961 | * Returns 0 for success or an error on failure. | |
1962 | * Called at driver startup. | |
1963 | */ | |
1964 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1965 | struct drm_device *ddev, | |
1966 | struct pci_dev *pdev, | |
1967 | uint32_t flags) | |
1968 | { | |
1969 | int r, i; | |
1970 | bool runtime = false; | |
95844d20 | 1971 | u32 max_MBps; |
d38ceaf9 AD |
1972 | |
1973 | adev->shutdown = false; | |
1974 | adev->dev = &pdev->dev; | |
1975 | adev->ddev = ddev; | |
1976 | adev->pdev = pdev; | |
1977 | adev->flags = flags; | |
2f7d10b3 | 1978 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1979 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
1980 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1981 | adev->accel_working = false; | |
1982 | adev->num_rings = 0; | |
1983 | adev->mman.buffer_funcs = NULL; | |
1984 | adev->mman.buffer_funcs_ring = NULL; | |
1985 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1986 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 1987 | adev->gart.gart_funcs = NULL; |
f54d1867 | 1988 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
1989 | |
1990 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1991 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1992 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1993 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
1994 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
1995 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1996 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
1997 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1998 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1999 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2000 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2001 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2002 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2003 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2004 | ||
ccdbb20a | 2005 | |
3e39ab90 AD |
2006 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2007 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2008 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2009 | |
2010 | /* mutex initialization are all done here so we | |
2011 | * can recall function without having locking issues */ | |
d38ceaf9 | 2012 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2013 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2014 | mutex_init(&adev->pm.mutex); |
2015 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2016 | mutex_init(&adev->srbm_mutex); | |
2017 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
2018 | mutex_init(&adev->mn_lock); |
2019 | hash_init(adev->mn_hash); | |
2020 | ||
2021 | amdgpu_check_arguments(adev); | |
2022 | ||
2023 | /* Registers mapping */ | |
2024 | /* TODO: block userspace mapping of io register */ | |
2025 | spin_lock_init(&adev->mmio_idx_lock); | |
2026 | spin_lock_init(&adev->smc_idx_lock); | |
2027 | spin_lock_init(&adev->pcie_idx_lock); | |
2028 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2029 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2030 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 2031 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2032 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2033 | |
0c4e7fa5 CZ |
2034 | INIT_LIST_HEAD(&adev->shadow_list); |
2035 | mutex_init(&adev->shadow_list_lock); | |
2036 | ||
5c1354bd CZ |
2037 | INIT_LIST_HEAD(&adev->gtt_list); |
2038 | spin_lock_init(&adev->gtt_list_lock); | |
2039 | ||
da69c161 KW |
2040 | if (adev->asic_type >= CHIP_BONAIRE) { |
2041 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2042 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2043 | } else { | |
2044 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2045 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2046 | } | |
d38ceaf9 | 2047 | |
d38ceaf9 AD |
2048 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2049 | if (adev->rmmio == NULL) { | |
2050 | return -ENOMEM; | |
2051 | } | |
2052 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2053 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2054 | ||
da69c161 KW |
2055 | if (adev->asic_type >= CHIP_BONAIRE) |
2056 | /* doorbell bar mapping */ | |
2057 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2058 | |
2059 | /* io port mapping */ | |
2060 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2061 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2062 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2063 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2064 | break; | |
2065 | } | |
2066 | } | |
2067 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2068 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2069 | |
2070 | /* early init functions */ | |
2071 | r = amdgpu_early_init(adev); | |
2072 | if (r) | |
2073 | return r; | |
2074 | ||
2075 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2076 | /* this will fail for cards that aren't VGA class devices, just | |
2077 | * ignore it */ | |
2078 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2079 | ||
2080 | if (amdgpu_runtime_pm == 1) | |
2081 | runtime = true; | |
e9bef455 | 2082 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2083 | runtime = true; |
84c8b22e LW |
2084 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2085 | vga_switcheroo_register_client(adev->pdev, | |
2086 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2087 | if (runtime) |
2088 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2089 | ||
2090 | /* Read BIOS */ | |
83ba126a AD |
2091 | if (!amdgpu_get_bios(adev)) { |
2092 | r = -EINVAL; | |
2093 | goto failed; | |
2094 | } | |
f7e9e9fe | 2095 | |
d38ceaf9 | 2096 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2097 | if (r) { |
2098 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 2099 | goto failed; |
2c1a2784 | 2100 | } |
d38ceaf9 | 2101 | |
4e99a44e ML |
2102 | /* detect if we are with an SRIOV vbios */ |
2103 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2104 | |
d38ceaf9 | 2105 | /* Post card if necessary */ |
bec86378 | 2106 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 2107 | if (!adev->bios) { |
bec86378 | 2108 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2109 | r = -EINVAL; |
2110 | goto failed; | |
d38ceaf9 | 2111 | } |
bec86378 | 2112 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2113 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2114 | if (r) { | |
2115 | dev_err(adev->dev, "gpu post error!\n"); | |
2116 | goto failed; | |
2117 | } | |
2118 | } else { | |
2119 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
2120 | } |
2121 | ||
a5bde2f9 AD |
2122 | if (!adev->is_atom_fw) { |
2123 | /* Initialize clocks */ | |
2124 | r = amdgpu_atombios_get_clock_info(adev); | |
2125 | if (r) { | |
2126 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
2127 | return r; | |
2128 | } | |
2129 | /* init i2c buses */ | |
2130 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2131 | } |
d38ceaf9 AD |
2132 | |
2133 | /* Fence driver */ | |
2134 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2135 | if (r) { |
2136 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 2137 | goto failed; |
2c1a2784 | 2138 | } |
d38ceaf9 AD |
2139 | |
2140 | /* init the mode config */ | |
2141 | drm_mode_config_init(adev->ddev); | |
2142 | ||
2143 | r = amdgpu_init(adev); | |
2144 | if (r) { | |
2c1a2784 | 2145 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 2146 | amdgpu_fini(adev); |
83ba126a | 2147 | goto failed; |
d38ceaf9 AD |
2148 | } |
2149 | ||
2150 | adev->accel_working = true; | |
2151 | ||
95844d20 MO |
2152 | /* Initialize the buffer migration limit. */ |
2153 | if (amdgpu_moverate >= 0) | |
2154 | max_MBps = amdgpu_moverate; | |
2155 | else | |
2156 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2157 | /* Get a log2 for easy divisions. */ | |
2158 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2159 | ||
d38ceaf9 AD |
2160 | r = amdgpu_ib_pool_init(adev); |
2161 | if (r) { | |
2162 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 2163 | goto failed; |
d38ceaf9 AD |
2164 | } |
2165 | ||
2166 | r = amdgpu_ib_ring_tests(adev); | |
2167 | if (r) | |
2168 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2169 | ||
9bc92b9c ML |
2170 | amdgpu_fbdev_init(adev); |
2171 | ||
d38ceaf9 | 2172 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2173 | if (r) |
d38ceaf9 | 2174 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2175 | |
2176 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2177 | if (r) |
d38ceaf9 | 2178 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2179 | |
50ab2533 | 2180 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2181 | if (r) |
50ab2533 | 2182 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2183 | |
d38ceaf9 AD |
2184 | if ((amdgpu_testing & 1)) { |
2185 | if (adev->accel_working) | |
2186 | amdgpu_test_moves(adev); | |
2187 | else | |
2188 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2189 | } | |
d38ceaf9 AD |
2190 | if (amdgpu_benchmarking) { |
2191 | if (adev->accel_working) | |
2192 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2193 | else | |
2194 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2195 | } | |
2196 | ||
2197 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2198 | * explicit gating rather than handling it automatically. | |
2199 | */ | |
2200 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2201 | if (r) { |
2202 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 2203 | goto failed; |
2c1a2784 | 2204 | } |
d38ceaf9 AD |
2205 | |
2206 | return 0; | |
83ba126a AD |
2207 | |
2208 | failed: | |
2209 | if (runtime) | |
2210 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2211 | return r; | |
d38ceaf9 AD |
2212 | } |
2213 | ||
d38ceaf9 AD |
2214 | /** |
2215 | * amdgpu_device_fini - tear down the driver | |
2216 | * | |
2217 | * @adev: amdgpu_device pointer | |
2218 | * | |
2219 | * Tear down the driver info (all asics). | |
2220 | * Called at driver shutdown. | |
2221 | */ | |
2222 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2223 | { | |
2224 | int r; | |
2225 | ||
2226 | DRM_INFO("amdgpu: finishing device.\n"); | |
2227 | adev->shutdown = true; | |
db2c2a97 PD |
2228 | if (adev->mode_info.mode_config_initialized) |
2229 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2230 | /* evict vram memory */ |
2231 | amdgpu_bo_evict_vram(adev); | |
2232 | amdgpu_ib_pool_fini(adev); | |
2233 | amdgpu_fence_driver_fini(adev); | |
2234 | amdgpu_fbdev_fini(adev); | |
2235 | r = amdgpu_fini(adev); | |
d38ceaf9 AD |
2236 | adev->accel_working = false; |
2237 | /* free i2c buses */ | |
2238 | amdgpu_i2c_fini(adev); | |
2239 | amdgpu_atombios_fini(adev); | |
2240 | kfree(adev->bios); | |
2241 | adev->bios = NULL; | |
84c8b22e LW |
2242 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2243 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2244 | if (adev->flags & AMD_IS_PX) |
2245 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2246 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2247 | if (adev->rio_mem) | |
2248 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2249 | adev->rio_mem = NULL; | |
2250 | iounmap(adev->rmmio); | |
2251 | adev->rmmio = NULL; | |
da69c161 KW |
2252 | if (adev->asic_type >= CHIP_BONAIRE) |
2253 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2254 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2255 | } |
2256 | ||
2257 | ||
2258 | /* | |
2259 | * Suspend & resume. | |
2260 | */ | |
2261 | /** | |
810ddc3a | 2262 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2263 | * |
2264 | * @pdev: drm dev pointer | |
2265 | * @state: suspend state | |
2266 | * | |
2267 | * Puts the hw in the suspend state (all asics). | |
2268 | * Returns 0 for success or an error on failure. | |
2269 | * Called at driver suspend. | |
2270 | */ | |
810ddc3a | 2271 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2272 | { |
2273 | struct amdgpu_device *adev; | |
2274 | struct drm_crtc *crtc; | |
2275 | struct drm_connector *connector; | |
5ceb54c6 | 2276 | int r; |
d38ceaf9 AD |
2277 | |
2278 | if (dev == NULL || dev->dev_private == NULL) { | |
2279 | return -ENODEV; | |
2280 | } | |
2281 | ||
2282 | adev = dev->dev_private; | |
2283 | ||
2284 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2285 | return 0; | |
2286 | ||
2287 | drm_kms_helper_poll_disable(dev); | |
2288 | ||
2289 | /* turn off display hw */ | |
4c7fbc39 | 2290 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2291 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2292 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2293 | } | |
4c7fbc39 | 2294 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2295 | |
756e6880 | 2296 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2297 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2298 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2299 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2300 | struct amdgpu_bo *robj; | |
2301 | ||
756e6880 AD |
2302 | if (amdgpu_crtc->cursor_bo) { |
2303 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2304 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2305 | if (r == 0) { |
2306 | amdgpu_bo_unpin(aobj); | |
2307 | amdgpu_bo_unreserve(aobj); | |
2308 | } | |
2309 | } | |
2310 | ||
d38ceaf9 AD |
2311 | if (rfb == NULL || rfb->obj == NULL) { |
2312 | continue; | |
2313 | } | |
2314 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2315 | /* don't unpin kernel fb objects */ | |
2316 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2317 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2318 | if (r == 0) { |
2319 | amdgpu_bo_unpin(robj); | |
2320 | amdgpu_bo_unreserve(robj); | |
2321 | } | |
2322 | } | |
2323 | } | |
2324 | /* evict vram memory */ | |
2325 | amdgpu_bo_evict_vram(adev); | |
2326 | ||
5ceb54c6 | 2327 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2328 | |
2329 | r = amdgpu_suspend(adev); | |
2330 | ||
a0a71e49 AD |
2331 | /* evict remaining vram memory |
2332 | * This second call to evict vram is to evict the gart page table | |
2333 | * using the CPU. | |
2334 | */ | |
d38ceaf9 AD |
2335 | amdgpu_bo_evict_vram(adev); |
2336 | ||
be34d3bf AD |
2337 | if (adev->is_atom_fw) |
2338 | amdgpu_atomfirmware_scratch_regs_save(adev); | |
2339 | else | |
2340 | amdgpu_atombios_scratch_regs_save(adev); | |
d38ceaf9 AD |
2341 | pci_save_state(dev->pdev); |
2342 | if (suspend) { | |
2343 | /* Shut down the device */ | |
2344 | pci_disable_device(dev->pdev); | |
2345 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2346 | } else { |
2347 | r = amdgpu_asic_reset(adev); | |
2348 | if (r) | |
2349 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2350 | } |
2351 | ||
2352 | if (fbcon) { | |
2353 | console_lock(); | |
2354 | amdgpu_fbdev_set_suspend(adev, 1); | |
2355 | console_unlock(); | |
2356 | } | |
2357 | return 0; | |
2358 | } | |
2359 | ||
2360 | /** | |
810ddc3a | 2361 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2362 | * |
2363 | * @pdev: drm dev pointer | |
2364 | * | |
2365 | * Bring the hw back to operating state (all asics). | |
2366 | * Returns 0 for success or an error on failure. | |
2367 | * Called at driver resume. | |
2368 | */ | |
810ddc3a | 2369 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2370 | { |
2371 | struct drm_connector *connector; | |
2372 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2373 | struct drm_crtc *crtc; |
03161a6e | 2374 | int r = 0; |
d38ceaf9 AD |
2375 | |
2376 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2377 | return 0; | |
2378 | ||
74b0b157 | 2379 | if (fbcon) |
d38ceaf9 | 2380 | console_lock(); |
74b0b157 | 2381 | |
d38ceaf9 AD |
2382 | if (resume) { |
2383 | pci_set_power_state(dev->pdev, PCI_D0); | |
2384 | pci_restore_state(dev->pdev); | |
74b0b157 | 2385 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2386 | if (r) |
2387 | goto unlock; | |
d38ceaf9 | 2388 | } |
be34d3bf AD |
2389 | if (adev->is_atom_fw) |
2390 | amdgpu_atomfirmware_scratch_regs_restore(adev); | |
2391 | else | |
2392 | amdgpu_atombios_scratch_regs_restore(adev); | |
d38ceaf9 AD |
2393 | |
2394 | /* post card */ | |
c836fec5 | 2395 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2396 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2397 | if (r) | |
2398 | DRM_ERROR("amdgpu asic init failed\n"); | |
2399 | } | |
d38ceaf9 AD |
2400 | |
2401 | r = amdgpu_resume(adev); | |
e6707218 | 2402 | if (r) { |
ca198528 | 2403 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2404 | goto unlock; |
e6707218 | 2405 | } |
5ceb54c6 AD |
2406 | amdgpu_fence_driver_resume(adev); |
2407 | ||
ca198528 FC |
2408 | if (resume) { |
2409 | r = amdgpu_ib_ring_tests(adev); | |
2410 | if (r) | |
2411 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2412 | } | |
d38ceaf9 AD |
2413 | |
2414 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2415 | if (r) |
2416 | goto unlock; | |
d38ceaf9 | 2417 | |
756e6880 AD |
2418 | /* pin cursors */ |
2419 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2420 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2421 | ||
2422 | if (amdgpu_crtc->cursor_bo) { | |
2423 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2424 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2425 | if (r == 0) { |
2426 | r = amdgpu_bo_pin(aobj, | |
2427 | AMDGPU_GEM_DOMAIN_VRAM, | |
2428 | &amdgpu_crtc->cursor_addr); | |
2429 | if (r != 0) | |
2430 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2431 | amdgpu_bo_unreserve(aobj); | |
2432 | } | |
2433 | } | |
2434 | } | |
2435 | ||
d38ceaf9 AD |
2436 | /* blat the mode back in */ |
2437 | if (fbcon) { | |
2438 | drm_helper_resume_force_mode(dev); | |
2439 | /* turn on display hw */ | |
4c7fbc39 | 2440 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2441 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2442 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2443 | } | |
4c7fbc39 | 2444 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2445 | } |
2446 | ||
2447 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2448 | |
2449 | /* | |
2450 | * Most of the connector probing functions try to acquire runtime pm | |
2451 | * refs to ensure that the GPU is powered on when connector polling is | |
2452 | * performed. Since we're calling this from a runtime PM callback, | |
2453 | * trying to acquire rpm refs will cause us to deadlock. | |
2454 | * | |
2455 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2456 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2457 | */ | |
2458 | #ifdef CONFIG_PM | |
2459 | dev->dev->power.disable_depth++; | |
2460 | #endif | |
54fb2a5c | 2461 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2462 | #ifdef CONFIG_PM |
2463 | dev->dev->power.disable_depth--; | |
2464 | #endif | |
d38ceaf9 | 2465 | |
03161a6e | 2466 | if (fbcon) |
d38ceaf9 | 2467 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2468 | |
2469 | unlock: | |
2470 | if (fbcon) | |
d38ceaf9 | 2471 | console_unlock(); |
d38ceaf9 | 2472 | |
03161a6e | 2473 | return r; |
d38ceaf9 AD |
2474 | } |
2475 | ||
63fbf42f CZ |
2476 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2477 | { | |
2478 | int i; | |
2479 | bool asic_hang = false; | |
2480 | ||
2481 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2482 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2483 | continue; |
a1255107 AD |
2484 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2485 | adev->ip_blocks[i].status.hang = | |
2486 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2487 | if (adev->ip_blocks[i].status.hang) { | |
2488 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2489 | asic_hang = true; |
2490 | } | |
2491 | } | |
2492 | return asic_hang; | |
2493 | } | |
2494 | ||
4d446656 | 2495 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2496 | { |
2497 | int i, r = 0; | |
2498 | ||
2499 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2500 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2501 | continue; |
a1255107 AD |
2502 | if (adev->ip_blocks[i].status.hang && |
2503 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2504 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2505 | if (r) |
2506 | return r; | |
2507 | } | |
2508 | } | |
2509 | ||
2510 | return 0; | |
2511 | } | |
2512 | ||
35d782fe CZ |
2513 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2514 | { | |
da146d3b AD |
2515 | int i; |
2516 | ||
2517 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2518 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2519 | continue; |
a1255107 AD |
2520 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2521 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2522 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2523 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2524 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2525 | DRM_INFO("Some block need full reset!\n"); |
2526 | return true; | |
2527 | } | |
2528 | } | |
35d782fe CZ |
2529 | } |
2530 | return false; | |
2531 | } | |
2532 | ||
2533 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2534 | { | |
2535 | int i, r = 0; | |
2536 | ||
2537 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2538 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2539 | continue; |
a1255107 AD |
2540 | if (adev->ip_blocks[i].status.hang && |
2541 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2542 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2543 | if (r) |
2544 | return r; | |
2545 | } | |
2546 | } | |
2547 | ||
2548 | return 0; | |
2549 | } | |
2550 | ||
2551 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2552 | { | |
2553 | int i, r = 0; | |
2554 | ||
2555 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2556 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2557 | continue; |
a1255107 AD |
2558 | if (adev->ip_blocks[i].status.hang && |
2559 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2560 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2561 | if (r) |
2562 | return r; | |
2563 | } | |
2564 | ||
2565 | return 0; | |
2566 | } | |
2567 | ||
3ad81f16 CZ |
2568 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2569 | { | |
2570 | if (adev->flags & AMD_IS_APU) | |
2571 | return false; | |
2572 | ||
2573 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2574 | } | |
2575 | ||
53cdccd5 CZ |
2576 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2577 | struct amdgpu_ring *ring, | |
2578 | struct amdgpu_bo *bo, | |
f54d1867 | 2579 | struct dma_fence **fence) |
53cdccd5 CZ |
2580 | { |
2581 | uint32_t domain; | |
2582 | int r; | |
2583 | ||
23d2e504 RH |
2584 | if (!bo->shadow) |
2585 | return 0; | |
2586 | ||
1d284797 | 2587 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2588 | if (r) |
2589 | return r; | |
2590 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2591 | /* if bo has been evicted, then no need to recover */ | |
2592 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2593 | r = amdgpu_bo_validate(bo->shadow); |
2594 | if (r) { | |
2595 | DRM_ERROR("bo validate failed!\n"); | |
2596 | goto err; | |
2597 | } | |
2598 | ||
2599 | r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem); | |
2600 | if (r) { | |
2601 | DRM_ERROR("%p bind failed\n", bo->shadow); | |
2602 | goto err; | |
2603 | } | |
2604 | ||
23d2e504 | 2605 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2606 | NULL, fence, true); |
23d2e504 RH |
2607 | if (r) { |
2608 | DRM_ERROR("recover page table failed!\n"); | |
2609 | goto err; | |
2610 | } | |
2611 | } | |
53cdccd5 | 2612 | err: |
23d2e504 RH |
2613 | amdgpu_bo_unreserve(bo); |
2614 | return r; | |
53cdccd5 CZ |
2615 | } |
2616 | ||
a90ad3c2 ML |
2617 | /** |
2618 | * amdgpu_sriov_gpu_reset - reset the asic | |
2619 | * | |
2620 | * @adev: amdgpu device pointer | |
7225f873 | 2621 | * @job: which job trigger hang |
a90ad3c2 ML |
2622 | * |
2623 | * Attempt the reset the GPU if it has hung (all asics). | |
2624 | * for SRIOV case. | |
2625 | * Returns 0 for success or an error on failure. | |
2626 | */ | |
7225f873 | 2627 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) |
a90ad3c2 | 2628 | { |
65781c78 | 2629 | int i, j, r = 0; |
a90ad3c2 ML |
2630 | int resched; |
2631 | struct amdgpu_bo *bo, *tmp; | |
2632 | struct amdgpu_ring *ring; | |
2633 | struct dma_fence *fence = NULL, *next = NULL; | |
2634 | ||
147b5983 | 2635 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2636 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2637 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2638 | |
2639 | /* block TTM */ | |
2640 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2641 | ||
65781c78 ML |
2642 | /* we start from the ring trigger GPU hang */ |
2643 | j = job ? job->ring->idx : 0; | |
a90ad3c2 | 2644 | |
65781c78 ML |
2645 | /* block scheduler */ |
2646 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { | |
2647 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2648 | if (!ring || !ring->sched.thread) |
2649 | continue; | |
2650 | ||
2651 | kthread_park(ring->sched.thread); | |
65781c78 ML |
2652 | |
2653 | if (job && j != i) | |
2654 | continue; | |
2655 | ||
4f059ecd | 2656 | /* here give the last chance to check if job removed from mirror-list |
65781c78 | 2657 | * since we already pay some time on kthread_park */ |
4f059ecd | 2658 | if (job && list_empty(&job->base.node)) { |
65781c78 ML |
2659 | kthread_unpark(ring->sched.thread); |
2660 | goto give_up_reset; | |
2661 | } | |
2662 | ||
2663 | if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) | |
2664 | amd_sched_job_kickout(&job->base); | |
2665 | ||
2666 | /* only do job_reset on the hang ring if @job not NULL */ | |
a90ad3c2 | 2667 | amd_sched_hw_job_reset(&ring->sched); |
a90ad3c2 | 2668 | |
65781c78 ML |
2669 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2670 | amdgpu_fence_driver_force_completion_ring(ring); | |
2671 | } | |
a90ad3c2 ML |
2672 | |
2673 | /* request to take full control of GPU before re-initialization */ | |
7225f873 | 2674 | if (job) |
a90ad3c2 ML |
2675 | amdgpu_virt_reset_gpu(adev); |
2676 | else | |
2677 | amdgpu_virt_request_full_gpu(adev, true); | |
2678 | ||
2679 | ||
2680 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2681 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2682 | |
2683 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2684 | amdgpu_ttm_recover_gart(adev); | |
2685 | ||
2686 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2687 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2688 | |
2689 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2690 | ||
2691 | if (amdgpu_ib_ring_tests(adev)) | |
2692 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2693 | ||
2694 | /* release full control of GPU after ib test */ | |
2695 | amdgpu_virt_release_full_gpu(adev, true); | |
2696 | ||
2697 | DRM_INFO("recover vram bo from shadow\n"); | |
2698 | ||
2699 | ring = adev->mman.buffer_funcs_ring; | |
2700 | mutex_lock(&adev->shadow_list_lock); | |
2701 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2702 | next = NULL; |
a90ad3c2 ML |
2703 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2704 | if (fence) { | |
2705 | r = dma_fence_wait(fence, false); | |
2706 | if (r) { | |
2707 | WARN(r, "recovery from shadow isn't completed\n"); | |
2708 | break; | |
2709 | } | |
2710 | } | |
2711 | ||
2712 | dma_fence_put(fence); | |
2713 | fence = next; | |
2714 | } | |
2715 | mutex_unlock(&adev->shadow_list_lock); | |
2716 | ||
2717 | if (fence) { | |
2718 | r = dma_fence_wait(fence, false); | |
2719 | if (r) | |
2720 | WARN(r, "recovery from shadow isn't completed\n"); | |
2721 | } | |
2722 | dma_fence_put(fence); | |
2723 | ||
65781c78 ML |
2724 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { |
2725 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2726 | if (!ring || !ring->sched.thread) |
2727 | continue; | |
2728 | ||
65781c78 ML |
2729 | if (job && j != i) { |
2730 | kthread_unpark(ring->sched.thread); | |
2731 | continue; | |
2732 | } | |
2733 | ||
a90ad3c2 ML |
2734 | amd_sched_job_recovery(&ring->sched); |
2735 | kthread_unpark(ring->sched.thread); | |
2736 | } | |
2737 | ||
2738 | drm_helper_resume_force_mode(adev->ddev); | |
65781c78 | 2739 | give_up_reset: |
a90ad3c2 ML |
2740 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); |
2741 | if (r) { | |
2742 | /* bad news, how to tell it to userspace ? */ | |
2743 | dev_info(adev->dev, "GPU reset failed\n"); | |
65781c78 ML |
2744 | } else { |
2745 | dev_info(adev->dev, "GPU reset successed!\n"); | |
a90ad3c2 ML |
2746 | } |
2747 | ||
1fb37a3d | 2748 | adev->gfx.in_reset = false; |
147b5983 | 2749 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2750 | return r; |
2751 | } | |
2752 | ||
d38ceaf9 AD |
2753 | /** |
2754 | * amdgpu_gpu_reset - reset the asic | |
2755 | * | |
2756 | * @adev: amdgpu device pointer | |
2757 | * | |
2758 | * Attempt the reset the GPU if it has hung (all asics). | |
2759 | * Returns 0 for success or an error on failure. | |
2760 | */ | |
2761 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2762 | { | |
d38ceaf9 AD |
2763 | int i, r; |
2764 | int resched; | |
35d782fe | 2765 | bool need_full_reset; |
d38ceaf9 | 2766 | |
63fbf42f CZ |
2767 | if (!amdgpu_check_soft_reset(adev)) { |
2768 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2769 | return 0; | |
2770 | } | |
d38ceaf9 | 2771 | |
d94aed5a | 2772 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2773 | |
a3c47d6b CZ |
2774 | /* block TTM */ |
2775 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2776 | ||
0875dc9e CZ |
2777 | /* block scheduler */ |
2778 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2779 | struct amdgpu_ring *ring = adev->rings[i]; | |
2780 | ||
51687759 | 2781 | if (!ring || !ring->sched.thread) |
0875dc9e CZ |
2782 | continue; |
2783 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2784 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2785 | } |
2200edac CZ |
2786 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2787 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2788 | |
35d782fe | 2789 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2790 | |
35d782fe CZ |
2791 | if (!need_full_reset) { |
2792 | amdgpu_pre_soft_reset(adev); | |
2793 | r = amdgpu_soft_reset(adev); | |
2794 | amdgpu_post_soft_reset(adev); | |
2795 | if (r || amdgpu_check_soft_reset(adev)) { | |
2796 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2797 | need_full_reset = true; | |
2798 | } | |
f1aa7e08 CZ |
2799 | } |
2800 | ||
35d782fe | 2801 | if (need_full_reset) { |
35d782fe | 2802 | r = amdgpu_suspend(adev); |
bfa99269 | 2803 | |
35d782fe CZ |
2804 | retry: |
2805 | /* Disable fb access */ | |
2806 | if (adev->mode_info.num_crtc) { | |
2807 | struct amdgpu_mode_mc_save save; | |
2808 | amdgpu_display_stop_mc_access(adev, &save); | |
2809 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
2810 | } | |
be34d3bf AD |
2811 | if (adev->is_atom_fw) |
2812 | amdgpu_atomfirmware_scratch_regs_save(adev); | |
2813 | else | |
2814 | amdgpu_atombios_scratch_regs_save(adev); | |
35d782fe | 2815 | r = amdgpu_asic_reset(adev); |
be34d3bf AD |
2816 | if (adev->is_atom_fw) |
2817 | amdgpu_atomfirmware_scratch_regs_restore(adev); | |
2818 | else | |
2819 | amdgpu_atombios_scratch_regs_restore(adev); | |
35d782fe CZ |
2820 | /* post card */ |
2821 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2822 | ||
2823 | if (!r) { | |
2824 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
fcf0649f CZ |
2825 | r = amdgpu_resume_phase1(adev); |
2826 | if (r) | |
2827 | goto out; | |
2828 | r = amdgpu_ttm_recover_gart(adev); | |
2829 | if (r) | |
2830 | goto out; | |
2831 | r = amdgpu_resume_phase2(adev); | |
2832 | if (r) | |
2833 | goto out; | |
35d782fe | 2834 | } |
d38ceaf9 | 2835 | } |
fcf0649f | 2836 | out: |
d38ceaf9 | 2837 | if (!r) { |
e72cfd58 | 2838 | amdgpu_irq_gpu_reset_resume_helper(adev); |
1f465087 CZ |
2839 | r = amdgpu_ib_ring_tests(adev); |
2840 | if (r) { | |
2841 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2842 | r = amdgpu_suspend(adev); |
53cdccd5 | 2843 | need_full_reset = true; |
40019dc4 | 2844 | goto retry; |
1f465087 | 2845 | } |
53cdccd5 CZ |
2846 | /** |
2847 | * recovery vm page tables, since we cannot depend on VRAM is | |
2848 | * consistent after gpu full reset. | |
2849 | */ | |
2850 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2851 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2852 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2853 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2854 | |
2855 | DRM_INFO("recover vram bo from shadow\n"); | |
2856 | mutex_lock(&adev->shadow_list_lock); | |
2857 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2858 | next = NULL; |
53cdccd5 CZ |
2859 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2860 | if (fence) { | |
f54d1867 | 2861 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2862 | if (r) { |
1d7b17b0 | 2863 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2864 | break; |
2865 | } | |
2866 | } | |
1f465087 | 2867 | |
f54d1867 | 2868 | dma_fence_put(fence); |
53cdccd5 CZ |
2869 | fence = next; |
2870 | } | |
2871 | mutex_unlock(&adev->shadow_list_lock); | |
2872 | if (fence) { | |
f54d1867 | 2873 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2874 | if (r) |
1d7b17b0 | 2875 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2876 | } |
f54d1867 | 2877 | dma_fence_put(fence); |
53cdccd5 | 2878 | } |
d38ceaf9 AD |
2879 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2880 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
2881 | |
2882 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 2883 | continue; |
53cdccd5 | 2884 | |
aa1c8900 | 2885 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2886 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2887 | } |
d38ceaf9 | 2888 | } else { |
2200edac | 2889 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2890 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
51687759 | 2891 | if (adev->rings[i] && adev->rings[i]->sched.thread) { |
0875dc9e | 2892 | kthread_unpark(adev->rings[i]->sched.thread); |
0875dc9e | 2893 | } |
d38ceaf9 AD |
2894 | } |
2895 | } | |
2896 | ||
2897 | drm_helper_resume_force_mode(adev->ddev); | |
2898 | ||
2899 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
6643be65 | 2900 | if (r) |
d38ceaf9 AD |
2901 | /* bad news, how to tell it to userspace ? */ |
2902 | dev_info(adev->dev, "GPU reset failed\n"); | |
6643be65 CZ |
2903 | else |
2904 | dev_info(adev->dev, "GPU reset successed!\n"); | |
d38ceaf9 | 2905 | |
d38ceaf9 AD |
2906 | return r; |
2907 | } | |
2908 | ||
d0dd7f0c AD |
2909 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2910 | { | |
2911 | u32 mask; | |
2912 | int ret; | |
2913 | ||
cd474ba0 AD |
2914 | if (amdgpu_pcie_gen_cap) |
2915 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2916 | |
cd474ba0 AD |
2917 | if (amdgpu_pcie_lane_cap) |
2918 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2919 | |
cd474ba0 AD |
2920 | /* covers APUs as well */ |
2921 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2922 | if (adev->pm.pcie_gen_mask == 0) | |
2923 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2924 | if (adev->pm.pcie_mlw_mask == 0) | |
2925 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2926 | return; |
cd474ba0 | 2927 | } |
d0dd7f0c | 2928 | |
cd474ba0 AD |
2929 | if (adev->pm.pcie_gen_mask == 0) { |
2930 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2931 | if (!ret) { | |
2932 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2933 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2934 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2935 | ||
2936 | if (mask & DRM_PCIE_SPEED_25) | |
2937 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2938 | if (mask & DRM_PCIE_SPEED_50) | |
2939 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2940 | if (mask & DRM_PCIE_SPEED_80) | |
2941 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2942 | } else { | |
2943 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2944 | } | |
2945 | } | |
2946 | if (adev->pm.pcie_mlw_mask == 0) { | |
2947 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2948 | if (!ret) { | |
2949 | switch (mask) { | |
2950 | case 32: | |
2951 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2952 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2953 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2954 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2955 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2956 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2957 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2958 | break; | |
2959 | case 16: | |
2960 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2961 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2962 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2963 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2964 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2965 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2966 | break; | |
2967 | case 12: | |
2968 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2969 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2970 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2971 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2972 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2973 | break; | |
2974 | case 8: | |
2975 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2976 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2977 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2978 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2979 | break; | |
2980 | case 4: | |
2981 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2982 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2983 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2984 | break; | |
2985 | case 2: | |
2986 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2987 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2988 | break; | |
2989 | case 1: | |
2990 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2991 | break; | |
2992 | default: | |
2993 | break; | |
2994 | } | |
2995 | } else { | |
2996 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2997 | } |
2998 | } | |
2999 | } | |
d38ceaf9 AD |
3000 | |
3001 | /* | |
3002 | * Debugfs | |
3003 | */ | |
3004 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3005 | const struct drm_info_list *files, |
d38ceaf9 AD |
3006 | unsigned nfiles) |
3007 | { | |
3008 | unsigned i; | |
3009 | ||
3010 | for (i = 0; i < adev->debugfs_count; i++) { | |
3011 | if (adev->debugfs[i].files == files) { | |
3012 | /* Already registered */ | |
3013 | return 0; | |
3014 | } | |
3015 | } | |
3016 | ||
3017 | i = adev->debugfs_count + 1; | |
3018 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3019 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3020 | DRM_ERROR("Report so we increase " | |
3021 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3022 | return -EINVAL; | |
3023 | } | |
3024 | adev->debugfs[adev->debugfs_count].files = files; | |
3025 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3026 | adev->debugfs_count = i; | |
3027 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3028 | drm_debugfs_create_files(files, nfiles, |
3029 | adev->ddev->primary->debugfs_root, | |
3030 | adev->ddev->primary); | |
3031 | #endif | |
3032 | return 0; | |
3033 | } | |
3034 | ||
d38ceaf9 AD |
3035 | #if defined(CONFIG_DEBUG_FS) |
3036 | ||
3037 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3038 | size_t size, loff_t *pos) | |
3039 | { | |
45063097 | 3040 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3041 | ssize_t result = 0; |
3042 | int r; | |
bd12267d | 3043 | bool pm_pg_lock, use_bank; |
56628159 | 3044 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3045 | |
3046 | if (size & 0x3 || *pos & 0x3) | |
3047 | return -EINVAL; | |
3048 | ||
bd12267d TSD |
3049 | /* are we reading registers for which a PG lock is necessary? */ |
3050 | pm_pg_lock = (*pos >> 23) & 1; | |
3051 | ||
56628159 TSD |
3052 | if (*pos & (1ULL << 62)) { |
3053 | se_bank = (*pos >> 24) & 0x3FF; | |
3054 | sh_bank = (*pos >> 34) & 0x3FF; | |
3055 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
3056 | |
3057 | if (se_bank == 0x3FF) | |
3058 | se_bank = 0xFFFFFFFF; | |
3059 | if (sh_bank == 0x3FF) | |
3060 | sh_bank = 0xFFFFFFFF; | |
3061 | if (instance_bank == 0x3FF) | |
3062 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3063 | use_bank = 1; |
56628159 TSD |
3064 | } else { |
3065 | use_bank = 0; | |
3066 | } | |
3067 | ||
801a6aa9 | 3068 | *pos &= (1UL << 22) - 1; |
bd12267d | 3069 | |
56628159 | 3070 | if (use_bank) { |
32977f93 TSD |
3071 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3072 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3073 | return -EINVAL; |
3074 | mutex_lock(&adev->grbm_idx_mutex); | |
3075 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3076 | sh_bank, instance_bank); | |
3077 | } | |
3078 | ||
bd12267d TSD |
3079 | if (pm_pg_lock) |
3080 | mutex_lock(&adev->pm.mutex); | |
3081 | ||
d38ceaf9 AD |
3082 | while (size) { |
3083 | uint32_t value; | |
3084 | ||
3085 | if (*pos > adev->rmmio_size) | |
56628159 | 3086 | goto end; |
d38ceaf9 AD |
3087 | |
3088 | value = RREG32(*pos >> 2); | |
3089 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3090 | if (r) { |
3091 | result = r; | |
3092 | goto end; | |
3093 | } | |
d38ceaf9 AD |
3094 | |
3095 | result += 4; | |
3096 | buf += 4; | |
3097 | *pos += 4; | |
3098 | size -= 4; | |
3099 | } | |
3100 | ||
56628159 TSD |
3101 | end: |
3102 | if (use_bank) { | |
3103 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3104 | mutex_unlock(&adev->grbm_idx_mutex); | |
3105 | } | |
3106 | ||
bd12267d TSD |
3107 | if (pm_pg_lock) |
3108 | mutex_unlock(&adev->pm.mutex); | |
3109 | ||
d38ceaf9 AD |
3110 | return result; |
3111 | } | |
3112 | ||
3113 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3114 | size_t size, loff_t *pos) | |
3115 | { | |
45063097 | 3116 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3117 | ssize_t result = 0; |
3118 | int r; | |
394fdde2 TSD |
3119 | bool pm_pg_lock, use_bank; |
3120 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3121 | |
3122 | if (size & 0x3 || *pos & 0x3) | |
3123 | return -EINVAL; | |
3124 | ||
394fdde2 TSD |
3125 | /* are we reading registers for which a PG lock is necessary? */ |
3126 | pm_pg_lock = (*pos >> 23) & 1; | |
3127 | ||
3128 | if (*pos & (1ULL << 62)) { | |
3129 | se_bank = (*pos >> 24) & 0x3FF; | |
3130 | sh_bank = (*pos >> 34) & 0x3FF; | |
3131 | instance_bank = (*pos >> 44) & 0x3FF; | |
3132 | ||
3133 | if (se_bank == 0x3FF) | |
3134 | se_bank = 0xFFFFFFFF; | |
3135 | if (sh_bank == 0x3FF) | |
3136 | sh_bank = 0xFFFFFFFF; | |
3137 | if (instance_bank == 0x3FF) | |
3138 | instance_bank = 0xFFFFFFFF; | |
3139 | use_bank = 1; | |
3140 | } else { | |
3141 | use_bank = 0; | |
3142 | } | |
3143 | ||
801a6aa9 | 3144 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3145 | |
3146 | if (use_bank) { | |
3147 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3148 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3149 | return -EINVAL; | |
3150 | mutex_lock(&adev->grbm_idx_mutex); | |
3151 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3152 | sh_bank, instance_bank); | |
3153 | } | |
3154 | ||
3155 | if (pm_pg_lock) | |
3156 | mutex_lock(&adev->pm.mutex); | |
3157 | ||
d38ceaf9 AD |
3158 | while (size) { |
3159 | uint32_t value; | |
3160 | ||
3161 | if (*pos > adev->rmmio_size) | |
3162 | return result; | |
3163 | ||
3164 | r = get_user(value, (uint32_t *)buf); | |
3165 | if (r) | |
3166 | return r; | |
3167 | ||
3168 | WREG32(*pos >> 2, value); | |
3169 | ||
3170 | result += 4; | |
3171 | buf += 4; | |
3172 | *pos += 4; | |
3173 | size -= 4; | |
3174 | } | |
3175 | ||
394fdde2 TSD |
3176 | if (use_bank) { |
3177 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3178 | mutex_unlock(&adev->grbm_idx_mutex); | |
3179 | } | |
3180 | ||
3181 | if (pm_pg_lock) | |
3182 | mutex_unlock(&adev->pm.mutex); | |
3183 | ||
d38ceaf9 AD |
3184 | return result; |
3185 | } | |
3186 | ||
adcec288 TSD |
3187 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3188 | size_t size, loff_t *pos) | |
3189 | { | |
45063097 | 3190 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3191 | ssize_t result = 0; |
3192 | int r; | |
3193 | ||
3194 | if (size & 0x3 || *pos & 0x3) | |
3195 | return -EINVAL; | |
3196 | ||
3197 | while (size) { | |
3198 | uint32_t value; | |
3199 | ||
3200 | value = RREG32_PCIE(*pos >> 2); | |
3201 | r = put_user(value, (uint32_t *)buf); | |
3202 | if (r) | |
3203 | return r; | |
3204 | ||
3205 | result += 4; | |
3206 | buf += 4; | |
3207 | *pos += 4; | |
3208 | size -= 4; | |
3209 | } | |
3210 | ||
3211 | return result; | |
3212 | } | |
3213 | ||
3214 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3215 | size_t size, loff_t *pos) | |
3216 | { | |
45063097 | 3217 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3218 | ssize_t result = 0; |
3219 | int r; | |
3220 | ||
3221 | if (size & 0x3 || *pos & 0x3) | |
3222 | return -EINVAL; | |
3223 | ||
3224 | while (size) { | |
3225 | uint32_t value; | |
3226 | ||
3227 | r = get_user(value, (uint32_t *)buf); | |
3228 | if (r) | |
3229 | return r; | |
3230 | ||
3231 | WREG32_PCIE(*pos >> 2, value); | |
3232 | ||
3233 | result += 4; | |
3234 | buf += 4; | |
3235 | *pos += 4; | |
3236 | size -= 4; | |
3237 | } | |
3238 | ||
3239 | return result; | |
3240 | } | |
3241 | ||
3242 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3243 | size_t size, loff_t *pos) | |
3244 | { | |
45063097 | 3245 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3246 | ssize_t result = 0; |
3247 | int r; | |
3248 | ||
3249 | if (size & 0x3 || *pos & 0x3) | |
3250 | return -EINVAL; | |
3251 | ||
3252 | while (size) { | |
3253 | uint32_t value; | |
3254 | ||
3255 | value = RREG32_DIDT(*pos >> 2); | |
3256 | r = put_user(value, (uint32_t *)buf); | |
3257 | if (r) | |
3258 | return r; | |
3259 | ||
3260 | result += 4; | |
3261 | buf += 4; | |
3262 | *pos += 4; | |
3263 | size -= 4; | |
3264 | } | |
3265 | ||
3266 | return result; | |
3267 | } | |
3268 | ||
3269 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3270 | size_t size, loff_t *pos) | |
3271 | { | |
45063097 | 3272 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3273 | ssize_t result = 0; |
3274 | int r; | |
3275 | ||
3276 | if (size & 0x3 || *pos & 0x3) | |
3277 | return -EINVAL; | |
3278 | ||
3279 | while (size) { | |
3280 | uint32_t value; | |
3281 | ||
3282 | r = get_user(value, (uint32_t *)buf); | |
3283 | if (r) | |
3284 | return r; | |
3285 | ||
3286 | WREG32_DIDT(*pos >> 2, value); | |
3287 | ||
3288 | result += 4; | |
3289 | buf += 4; | |
3290 | *pos += 4; | |
3291 | size -= 4; | |
3292 | } | |
3293 | ||
3294 | return result; | |
3295 | } | |
3296 | ||
3297 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3298 | size_t size, loff_t *pos) | |
3299 | { | |
45063097 | 3300 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3301 | ssize_t result = 0; |
3302 | int r; | |
3303 | ||
3304 | if (size & 0x3 || *pos & 0x3) | |
3305 | return -EINVAL; | |
3306 | ||
3307 | while (size) { | |
3308 | uint32_t value; | |
3309 | ||
6fc0deaf | 3310 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3311 | r = put_user(value, (uint32_t *)buf); |
3312 | if (r) | |
3313 | return r; | |
3314 | ||
3315 | result += 4; | |
3316 | buf += 4; | |
3317 | *pos += 4; | |
3318 | size -= 4; | |
3319 | } | |
3320 | ||
3321 | return result; | |
3322 | } | |
3323 | ||
3324 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3325 | size_t size, loff_t *pos) | |
3326 | { | |
45063097 | 3327 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3328 | ssize_t result = 0; |
3329 | int r; | |
3330 | ||
3331 | if (size & 0x3 || *pos & 0x3) | |
3332 | return -EINVAL; | |
3333 | ||
3334 | while (size) { | |
3335 | uint32_t value; | |
3336 | ||
3337 | r = get_user(value, (uint32_t *)buf); | |
3338 | if (r) | |
3339 | return r; | |
3340 | ||
6fc0deaf | 3341 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3342 | |
3343 | result += 4; | |
3344 | buf += 4; | |
3345 | *pos += 4; | |
3346 | size -= 4; | |
3347 | } | |
3348 | ||
3349 | return result; | |
3350 | } | |
3351 | ||
1e051413 TSD |
3352 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3353 | size_t size, loff_t *pos) | |
3354 | { | |
45063097 | 3355 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3356 | ssize_t result = 0; |
3357 | int r; | |
3358 | uint32_t *config, no_regs = 0; | |
3359 | ||
3360 | if (size & 0x3 || *pos & 0x3) | |
3361 | return -EINVAL; | |
3362 | ||
ecab7668 | 3363 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3364 | if (!config) |
3365 | return -ENOMEM; | |
3366 | ||
3367 | /* version, increment each time something is added */ | |
9a999359 | 3368 | config[no_regs++] = 3; |
1e051413 TSD |
3369 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3370 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3371 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3372 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3373 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3374 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3375 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3376 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3377 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3378 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3379 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3380 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3381 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3382 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3383 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3384 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3385 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3386 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3387 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3388 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3389 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3390 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3391 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3392 | ||
89a8f309 TSD |
3393 | /* rev==1 */ |
3394 | config[no_regs++] = adev->rev_id; | |
3395 | config[no_regs++] = adev->pg_flags; | |
3396 | config[no_regs++] = adev->cg_flags; | |
3397 | ||
e9f11dc8 TSD |
3398 | /* rev==2 */ |
3399 | config[no_regs++] = adev->family; | |
3400 | config[no_regs++] = adev->external_rev_id; | |
3401 | ||
9a999359 TSD |
3402 | /* rev==3 */ |
3403 | config[no_regs++] = adev->pdev->device; | |
3404 | config[no_regs++] = adev->pdev->revision; | |
3405 | config[no_regs++] = adev->pdev->subsystem_device; | |
3406 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3407 | ||
1e051413 TSD |
3408 | while (size && (*pos < no_regs * 4)) { |
3409 | uint32_t value; | |
3410 | ||
3411 | value = config[*pos >> 2]; | |
3412 | r = put_user(value, (uint32_t *)buf); | |
3413 | if (r) { | |
3414 | kfree(config); | |
3415 | return r; | |
3416 | } | |
3417 | ||
3418 | result += 4; | |
3419 | buf += 4; | |
3420 | *pos += 4; | |
3421 | size -= 4; | |
3422 | } | |
3423 | ||
3424 | kfree(config); | |
3425 | return result; | |
3426 | } | |
3427 | ||
f2cdaf20 TSD |
3428 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3429 | size_t size, loff_t *pos) | |
3430 | { | |
45063097 | 3431 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3432 | int idx, x, outsize, r, valuesize; |
3433 | uint32_t values[16]; | |
f2cdaf20 | 3434 | |
9f8df7d7 | 3435 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3436 | return -EINVAL; |
3437 | ||
3cbc614f SP |
3438 | if (amdgpu_dpm == 0) |
3439 | return -EINVAL; | |
3440 | ||
f2cdaf20 TSD |
3441 | /* convert offset to sensor number */ |
3442 | idx = *pos >> 2; | |
3443 | ||
9f8df7d7 | 3444 | valuesize = sizeof(values); |
f2cdaf20 | 3445 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3446 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3447 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3448 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3449 | &valuesize); | |
f2cdaf20 TSD |
3450 | else |
3451 | return -EINVAL; | |
3452 | ||
9f8df7d7 TSD |
3453 | if (size > valuesize) |
3454 | return -EINVAL; | |
3455 | ||
3456 | outsize = 0; | |
3457 | x = 0; | |
3458 | if (!r) { | |
3459 | while (size) { | |
3460 | r = put_user(values[x++], (int32_t *)buf); | |
3461 | buf += 4; | |
3462 | size -= 4; | |
3463 | outsize += 4; | |
3464 | } | |
3465 | } | |
f2cdaf20 | 3466 | |
9f8df7d7 | 3467 | return !r ? outsize : r; |
f2cdaf20 | 3468 | } |
1e051413 | 3469 | |
273d7aa1 TSD |
3470 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3471 | size_t size, loff_t *pos) | |
3472 | { | |
3473 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3474 | int r, x; | |
3475 | ssize_t result=0; | |
472259f0 | 3476 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3477 | |
3478 | if (size & 3 || *pos & 3) | |
3479 | return -EINVAL; | |
3480 | ||
3481 | /* decode offset */ | |
3482 | offset = (*pos & 0x7F); | |
3483 | se = ((*pos >> 7) & 0xFF); | |
3484 | sh = ((*pos >> 15) & 0xFF); | |
3485 | cu = ((*pos >> 23) & 0xFF); | |
3486 | wave = ((*pos >> 31) & 0xFF); | |
3487 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3488 | |
3489 | /* switch to the specific se/sh/cu */ | |
3490 | mutex_lock(&adev->grbm_idx_mutex); | |
3491 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3492 | ||
3493 | x = 0; | |
472259f0 TSD |
3494 | if (adev->gfx.funcs->read_wave_data) |
3495 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3496 | |
3497 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3498 | mutex_unlock(&adev->grbm_idx_mutex); | |
3499 | ||
5ecfb3b8 TSD |
3500 | if (!x) |
3501 | return -EINVAL; | |
3502 | ||
472259f0 | 3503 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3504 | uint32_t value; |
3505 | ||
472259f0 | 3506 | value = data[offset >> 2]; |
273d7aa1 TSD |
3507 | r = put_user(value, (uint32_t *)buf); |
3508 | if (r) | |
3509 | return r; | |
3510 | ||
3511 | result += 4; | |
3512 | buf += 4; | |
472259f0 | 3513 | offset += 4; |
273d7aa1 TSD |
3514 | size -= 4; |
3515 | } | |
3516 | ||
3517 | return result; | |
3518 | } | |
3519 | ||
c5a60ce8 TSD |
3520 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3521 | size_t size, loff_t *pos) | |
3522 | { | |
3523 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3524 | int r; | |
3525 | ssize_t result = 0; | |
3526 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3527 | ||
3528 | if (size & 3 || *pos & 3) | |
3529 | return -EINVAL; | |
3530 | ||
3531 | /* decode offset */ | |
3532 | offset = (*pos & 0xFFF); /* in dwords */ | |
3533 | se = ((*pos >> 12) & 0xFF); | |
3534 | sh = ((*pos >> 20) & 0xFF); | |
3535 | cu = ((*pos >> 28) & 0xFF); | |
3536 | wave = ((*pos >> 36) & 0xFF); | |
3537 | simd = ((*pos >> 44) & 0xFF); | |
3538 | thread = ((*pos >> 52) & 0xFF); | |
3539 | bank = ((*pos >> 60) & 1); | |
3540 | ||
3541 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3542 | if (!data) | |
3543 | return -ENOMEM; | |
3544 | ||
3545 | /* switch to the specific se/sh/cu */ | |
3546 | mutex_lock(&adev->grbm_idx_mutex); | |
3547 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3548 | ||
3549 | if (bank == 0) { | |
3550 | if (adev->gfx.funcs->read_wave_vgprs) | |
3551 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3552 | } else { | |
3553 | if (adev->gfx.funcs->read_wave_sgprs) | |
3554 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3555 | } | |
3556 | ||
3557 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3558 | mutex_unlock(&adev->grbm_idx_mutex); | |
3559 | ||
3560 | while (size) { | |
3561 | uint32_t value; | |
3562 | ||
3563 | value = data[offset++]; | |
3564 | r = put_user(value, (uint32_t *)buf); | |
3565 | if (r) { | |
3566 | result = r; | |
3567 | goto err; | |
3568 | } | |
3569 | ||
3570 | result += 4; | |
3571 | buf += 4; | |
3572 | size -= 4; | |
3573 | } | |
3574 | ||
3575 | err: | |
3576 | kfree(data); | |
3577 | return result; | |
3578 | } | |
3579 | ||
d38ceaf9 AD |
3580 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3581 | .owner = THIS_MODULE, | |
3582 | .read = amdgpu_debugfs_regs_read, | |
3583 | .write = amdgpu_debugfs_regs_write, | |
3584 | .llseek = default_llseek | |
3585 | }; | |
adcec288 TSD |
3586 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3587 | .owner = THIS_MODULE, | |
3588 | .read = amdgpu_debugfs_regs_didt_read, | |
3589 | .write = amdgpu_debugfs_regs_didt_write, | |
3590 | .llseek = default_llseek | |
3591 | }; | |
3592 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3593 | .owner = THIS_MODULE, | |
3594 | .read = amdgpu_debugfs_regs_pcie_read, | |
3595 | .write = amdgpu_debugfs_regs_pcie_write, | |
3596 | .llseek = default_llseek | |
3597 | }; | |
3598 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3599 | .owner = THIS_MODULE, | |
3600 | .read = amdgpu_debugfs_regs_smc_read, | |
3601 | .write = amdgpu_debugfs_regs_smc_write, | |
3602 | .llseek = default_llseek | |
3603 | }; | |
3604 | ||
1e051413 TSD |
3605 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3606 | .owner = THIS_MODULE, | |
3607 | .read = amdgpu_debugfs_gca_config_read, | |
3608 | .llseek = default_llseek | |
3609 | }; | |
3610 | ||
f2cdaf20 TSD |
3611 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3612 | .owner = THIS_MODULE, | |
3613 | .read = amdgpu_debugfs_sensor_read, | |
3614 | .llseek = default_llseek | |
3615 | }; | |
3616 | ||
273d7aa1 TSD |
3617 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3618 | .owner = THIS_MODULE, | |
3619 | .read = amdgpu_debugfs_wave_read, | |
3620 | .llseek = default_llseek | |
3621 | }; | |
c5a60ce8 TSD |
3622 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3623 | .owner = THIS_MODULE, | |
3624 | .read = amdgpu_debugfs_gpr_read, | |
3625 | .llseek = default_llseek | |
3626 | }; | |
273d7aa1 | 3627 | |
adcec288 TSD |
3628 | static const struct file_operations *debugfs_regs[] = { |
3629 | &amdgpu_debugfs_regs_fops, | |
3630 | &amdgpu_debugfs_regs_didt_fops, | |
3631 | &amdgpu_debugfs_regs_pcie_fops, | |
3632 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3633 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3634 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3635 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3636 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3637 | }; |
3638 | ||
3639 | static const char *debugfs_regs_names[] = { | |
3640 | "amdgpu_regs", | |
3641 | "amdgpu_regs_didt", | |
3642 | "amdgpu_regs_pcie", | |
3643 | "amdgpu_regs_smc", | |
1e051413 | 3644 | "amdgpu_gca_config", |
f2cdaf20 | 3645 | "amdgpu_sensors", |
273d7aa1 | 3646 | "amdgpu_wave", |
c5a60ce8 | 3647 | "amdgpu_gpr", |
adcec288 | 3648 | }; |
d38ceaf9 AD |
3649 | |
3650 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3651 | { | |
3652 | struct drm_minor *minor = adev->ddev->primary; | |
3653 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3654 | unsigned i, j; |
3655 | ||
3656 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3657 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3658 | S_IFREG | S_IRUGO, root, | |
3659 | adev, debugfs_regs[i]); | |
3660 | if (IS_ERR(ent)) { | |
3661 | for (j = 0; j < i; j++) { | |
3662 | debugfs_remove(adev->debugfs_regs[i]); | |
3663 | adev->debugfs_regs[i] = NULL; | |
3664 | } | |
3665 | return PTR_ERR(ent); | |
3666 | } | |
d38ceaf9 | 3667 | |
adcec288 TSD |
3668 | if (!i) |
3669 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3670 | adev->debugfs_regs[i] = ent; | |
3671 | } | |
d38ceaf9 AD |
3672 | |
3673 | return 0; | |
3674 | } | |
3675 | ||
3676 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3677 | { | |
adcec288 TSD |
3678 | unsigned i; |
3679 | ||
3680 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3681 | if (adev->debugfs_regs[i]) { | |
3682 | debugfs_remove(adev->debugfs_regs[i]); | |
3683 | adev->debugfs_regs[i] = NULL; | |
3684 | } | |
3685 | } | |
d38ceaf9 AD |
3686 | } |
3687 | ||
3688 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
3689 | { | |
3690 | return 0; | |
3691 | } | |
7cebc728 AK |
3692 | #else |
3693 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3694 | { | |
3695 | return 0; | |
3696 | } | |
3697 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3698 | #endif |