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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
fdf2f6c5 | 33 | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 35 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
36 | #include <drm/amdgpu_drm.h> |
37 | #include <linux/vgaarb.h> | |
38 | #include <linux/vga_switcheroo.h> | |
39 | #include <linux/efi.h> | |
40 | #include "amdgpu.h" | |
f4b373f4 | 41 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
42 | #include "amdgpu_i2c.h" |
43 | #include "atom.h" | |
44 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 45 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 46 | #include "amd_pcie.h" |
33f34802 KW |
47 | #ifdef CONFIG_DRM_AMDGPU_SI |
48 | #include "si.h" | |
49 | #endif | |
a2e73f56 AD |
50 | #ifdef CONFIG_DRM_AMDGPU_CIK |
51 | #include "cik.h" | |
52 | #endif | |
aaa36a97 | 53 | #include "vi.h" |
460826e6 | 54 | #include "soc15.h" |
0a5b8c7b | 55 | #include "nv.h" |
d38ceaf9 | 56 | #include "bif/bif_4_1_d.h" |
9accf2fd | 57 | #include <linux/pci.h> |
bec86378 | 58 | #include <linux/firmware.h> |
89041940 | 59 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 60 | |
ba997709 | 61 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 62 | #include "amdgpu_pm.h" |
d38ceaf9 | 63 | |
5183411b | 64 | #include "amdgpu_xgmi.h" |
c030f2e4 | 65 | #include "amdgpu_ras.h" |
9c7c85f7 | 66 | #include "amdgpu_pmu.h" |
bd607166 | 67 | #include "amdgpu_fru_eeprom.h" |
5183411b | 68 | |
d5ea093e | 69 | #include <linux/suspend.h> |
c6a6e2db | 70 | #include <drm/task_barrier.h> |
3f12acc8 | 71 | #include <linux/pm_runtime.h> |
d5ea093e | 72 | |
e2a75f88 | 73 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 74 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 75 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 76 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 77 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 78 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 79 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 80 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 81 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 82 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
c0a43457 | 83 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_gpu_info.bin"); |
120eb833 | 84 | MODULE_FIRMWARE("amdgpu/navy_flounder_gpu_info.bin"); |
e2a75f88 | 85 | |
2dc80b00 S |
86 | #define AMDGPU_RESUME_MS 2000 |
87 | ||
050091ab | 88 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
89 | "TAHITI", |
90 | "PITCAIRN", | |
91 | "VERDE", | |
92 | "OLAND", | |
93 | "HAINAN", | |
d38ceaf9 AD |
94 | "BONAIRE", |
95 | "KAVERI", | |
96 | "KABINI", | |
97 | "HAWAII", | |
98 | "MULLINS", | |
99 | "TOPAZ", | |
100 | "TONGA", | |
48299f95 | 101 | "FIJI", |
d38ceaf9 | 102 | "CARRIZO", |
139f4917 | 103 | "STONEY", |
2cc0c0b5 FC |
104 | "POLARIS10", |
105 | "POLARIS11", | |
c4642a47 | 106 | "POLARIS12", |
48ff108d | 107 | "VEGAM", |
d4196f01 | 108 | "VEGA10", |
8fab806a | 109 | "VEGA12", |
956fcddc | 110 | "VEGA20", |
2ca8a5d2 | 111 | "RAVEN", |
d6c3b24e | 112 | "ARCTURUS", |
1eee4228 | 113 | "RENOIR", |
852a6626 | 114 | "NAVI10", |
87dbad02 | 115 | "NAVI14", |
9802f5d7 | 116 | "NAVI12", |
ccaf72d3 | 117 | "SIENNA_CICHLID", |
ddd8fbe7 | 118 | "NAVY_FLOUNDER", |
d38ceaf9 AD |
119 | "LAST", |
120 | }; | |
121 | ||
dcea6e65 KR |
122 | /** |
123 | * DOC: pcie_replay_count | |
124 | * | |
125 | * The amdgpu driver provides a sysfs API for reporting the total number | |
126 | * of PCIe replays (NAKs) | |
127 | * The file pcie_replay_count is used for this and returns the total | |
128 | * number of replays as a sum of the NAKs generated and NAKs received | |
129 | */ | |
130 | ||
131 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
132 | struct device_attribute *attr, char *buf) | |
133 | { | |
134 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 135 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
136 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
137 | ||
138 | return snprintf(buf, PAGE_SIZE, "%llu\n", cnt); | |
139 | } | |
140 | ||
141 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
142 | amdgpu_device_get_pcie_replay_count, NULL); | |
143 | ||
5494d864 AD |
144 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
145 | ||
bd607166 KR |
146 | /** |
147 | * DOC: product_name | |
148 | * | |
149 | * The amdgpu driver provides a sysfs API for reporting the product name | |
150 | * for the device | |
151 | * The file serial_number is used for this and returns the product name | |
152 | * as returned from the FRU. | |
153 | * NOTE: This is only available for certain server cards | |
154 | */ | |
155 | ||
156 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
157 | struct device_attribute *attr, char *buf) | |
158 | { | |
159 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 160 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
161 | |
162 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name); | |
163 | } | |
164 | ||
165 | static DEVICE_ATTR(product_name, S_IRUGO, | |
166 | amdgpu_device_get_product_name, NULL); | |
167 | ||
168 | /** | |
169 | * DOC: product_number | |
170 | * | |
171 | * The amdgpu driver provides a sysfs API for reporting the part number | |
172 | * for the device | |
173 | * The file serial_number is used for this and returns the part number | |
174 | * as returned from the FRU. | |
175 | * NOTE: This is only available for certain server cards | |
176 | */ | |
177 | ||
178 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
179 | struct device_attribute *attr, char *buf) | |
180 | { | |
181 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 182 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
183 | |
184 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number); | |
185 | } | |
186 | ||
187 | static DEVICE_ATTR(product_number, S_IRUGO, | |
188 | amdgpu_device_get_product_number, NULL); | |
189 | ||
190 | /** | |
191 | * DOC: serial_number | |
192 | * | |
193 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
194 | * for the device | |
195 | * The file serial_number is used for this and returns the serial number | |
196 | * as returned from the FRU. | |
197 | * NOTE: This is only available for certain server cards | |
198 | */ | |
199 | ||
200 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
201 | struct device_attribute *attr, char *buf) | |
202 | { | |
203 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 204 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
205 | |
206 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial); | |
207 | } | |
208 | ||
209 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
210 | amdgpu_device_get_serial_number, NULL); | |
211 | ||
e3ecdffa | 212 | /** |
31af062a | 213 | * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control |
e3ecdffa AD |
214 | * |
215 | * @dev: drm_device pointer | |
216 | * | |
217 | * Returns true if the device is a dGPU with HG/PX power control, | |
218 | * otherwise return false. | |
219 | */ | |
31af062a | 220 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 221 | { |
1348969a | 222 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 223 | |
2f7d10b3 | 224 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
225 | return true; |
226 | return false; | |
227 | } | |
228 | ||
a69cba42 AD |
229 | /** |
230 | * amdgpu_device_supports_baco - Does the device support BACO | |
231 | * | |
232 | * @dev: drm_device pointer | |
233 | * | |
234 | * Returns true if the device supporte BACO, | |
235 | * otherwise return false. | |
236 | */ | |
237 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
238 | { | |
1348969a | 239 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
240 | |
241 | return amdgpu_asic_supports_baco(adev); | |
242 | } | |
243 | ||
e35e2b11 TY |
244 | /** |
245 | * VRAM access helper functions. | |
246 | * | |
247 | * amdgpu_device_vram_access - read/write a buffer in vram | |
248 | * | |
249 | * @adev: amdgpu_device pointer | |
250 | * @pos: offset of the buffer in vram | |
251 | * @buf: virtual address of the buffer in system memory | |
252 | * @size: read/write size, sizeof(@buf) must > @size | |
253 | * @write: true - write to vram, otherwise - read from vram | |
254 | */ | |
255 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
256 | uint32_t *buf, size_t size, bool write) | |
257 | { | |
e35e2b11 | 258 | unsigned long flags; |
ce05ac56 CK |
259 | uint32_t hi = ~0; |
260 | uint64_t last; | |
261 | ||
9d11eb0d CK |
262 | |
263 | #ifdef CONFIG_64BIT | |
264 | last = min(pos + size, adev->gmc.visible_vram_size); | |
265 | if (last > pos) { | |
266 | void __iomem *addr = adev->mman.aper_base_kaddr + pos; | |
267 | size_t count = last - pos; | |
268 | ||
269 | if (write) { | |
270 | memcpy_toio(addr, buf, count); | |
271 | mb(); | |
272 | amdgpu_asic_flush_hdp(adev, NULL); | |
273 | } else { | |
274 | amdgpu_asic_invalidate_hdp(adev, NULL); | |
275 | mb(); | |
276 | memcpy_fromio(buf, addr, count); | |
277 | } | |
278 | ||
279 | if (count == size) | |
280 | return; | |
281 | ||
282 | pos += count; | |
283 | buf += count / 4; | |
284 | size -= count; | |
285 | } | |
286 | #endif | |
287 | ||
ce05ac56 CK |
288 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); |
289 | for (last = pos + size; pos < last; pos += 4) { | |
290 | uint32_t tmp = pos >> 31; | |
e35e2b11 | 291 | |
e35e2b11 | 292 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); |
ce05ac56 CK |
293 | if (tmp != hi) { |
294 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
295 | hi = tmp; | |
296 | } | |
e35e2b11 TY |
297 | if (write) |
298 | WREG32_NO_KIQ(mmMM_DATA, *buf++); | |
299 | else | |
300 | *buf++ = RREG32_NO_KIQ(mmMM_DATA); | |
e35e2b11 | 301 | } |
ce05ac56 | 302 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); |
e35e2b11 TY |
303 | } |
304 | ||
d38ceaf9 | 305 | /* |
e78b579d | 306 | * MMIO register access helper functions. |
d38ceaf9 | 307 | */ |
e3ecdffa | 308 | /** |
e78b579d | 309 | * amdgpu_mm_rreg - read a memory mapped IO register |
e3ecdffa AD |
310 | * |
311 | * @adev: amdgpu_device pointer | |
312 | * @reg: dword aligned register offset | |
313 | * @acc_flags: access flags which require special behavior | |
314 | * | |
315 | * Returns the 32 bit value from the offset specified. | |
316 | */ | |
e78b579d HZ |
317 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
318 | uint32_t acc_flags) | |
d38ceaf9 | 319 | { |
f4b373f4 TSD |
320 | uint32_t ret; |
321 | ||
81202807 DL |
322 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev) && |
323 | down_read_trylock(&adev->reset_sem)) { | |
324 | ret = amdgpu_kiq_rreg(adev, reg); | |
325 | up_read(&adev->reset_sem); | |
326 | return ret; | |
327 | } | |
bc992ba5 | 328 | |
ec59847e | 329 | if ((reg * 4) < adev->rmmio_size) |
f4b373f4 | 330 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
e78b579d HZ |
331 | else { |
332 | unsigned long flags; | |
333 | ||
334 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
335 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
336 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
337 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
338 | } | |
81202807 | 339 | |
e78b579d | 340 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
f4b373f4 | 341 | return ret; |
d38ceaf9 AD |
342 | } |
343 | ||
421a2a30 ML |
344 | /* |
345 | * MMIO register read with bytes helper functions | |
346 | * @offset:bytes offset from MMIO start | |
347 | * | |
348 | */ | |
349 | ||
e3ecdffa AD |
350 | /** |
351 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
352 | * | |
353 | * @adev: amdgpu_device pointer | |
354 | * @offset: byte aligned register offset | |
355 | * | |
356 | * Returns the 8 bit value from the offset specified. | |
357 | */ | |
421a2a30 ML |
358 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
359 | if (offset < adev->rmmio_size) | |
360 | return (readb(adev->rmmio + offset)); | |
361 | BUG(); | |
362 | } | |
363 | ||
364 | /* | |
365 | * MMIO register write with bytes helper functions | |
366 | * @offset:bytes offset from MMIO start | |
367 | * @value: the value want to be written to the register | |
368 | * | |
369 | */ | |
e3ecdffa AD |
370 | /** |
371 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
372 | * | |
373 | * @adev: amdgpu_device pointer | |
374 | * @offset: byte aligned register offset | |
375 | * @value: 8 bit value to write | |
376 | * | |
377 | * Writes the value specified to the offset specified. | |
378 | */ | |
421a2a30 ML |
379 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
380 | if (offset < adev->rmmio_size) | |
381 | writeb(value, adev->rmmio + offset); | |
382 | else | |
383 | BUG(); | |
384 | } | |
385 | ||
e230ac11 ND |
386 | static inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, |
387 | uint32_t reg, uint32_t v, | |
388 | uint32_t acc_flags) | |
2e0cc4d4 | 389 | { |
e78b579d | 390 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 391 | |
ec59847e | 392 | if ((reg * 4) < adev->rmmio_size) |
2e0cc4d4 | 393 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
e78b579d HZ |
394 | else { |
395 | unsigned long flags; | |
396 | ||
397 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
398 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
399 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
400 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
401 | } | |
2e0cc4d4 ML |
402 | } |
403 | ||
e3ecdffa | 404 | /** |
e78b579d | 405 | * amdgpu_mm_wreg - write to a memory mapped IO register |
e3ecdffa AD |
406 | * |
407 | * @adev: amdgpu_device pointer | |
408 | * @reg: dword aligned register offset | |
409 | * @v: 32 bit value to write to the register | |
410 | * @acc_flags: access flags which require special behavior | |
411 | * | |
412 | * Writes the value specified to the offset specified. | |
413 | */ | |
e78b579d HZ |
414 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
415 | uint32_t acc_flags) | |
d38ceaf9 | 416 | { |
81202807 DL |
417 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev) && |
418 | down_read_trylock(&adev->reset_sem)) { | |
419 | amdgpu_kiq_wreg(adev, reg, v); | |
420 | up_read(&adev->reset_sem); | |
421 | return; | |
422 | } | |
bc992ba5 | 423 | |
e78b579d | 424 | amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags); |
2e0cc4d4 | 425 | } |
d38ceaf9 | 426 | |
2e0cc4d4 ML |
427 | /* |
428 | * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range | |
429 | * | |
430 | * this function is invoked only the debugfs register access | |
431 | * */ | |
432 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
433 | uint32_t acc_flags) | |
434 | { | |
435 | if (amdgpu_sriov_fullaccess(adev) && | |
436 | adev->gfx.rlc.funcs && | |
437 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
47ed4e1c | 438 | |
2e0cc4d4 ML |
439 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
440 | return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v); | |
47ed4e1c | 441 | } |
2e0cc4d4 | 442 | |
e78b579d | 443 | amdgpu_mm_wreg_mmio(adev, reg, v, acc_flags); |
d38ceaf9 AD |
444 | } |
445 | ||
e3ecdffa AD |
446 | /** |
447 | * amdgpu_io_rreg - read an IO register | |
448 | * | |
449 | * @adev: amdgpu_device pointer | |
450 | * @reg: dword aligned register offset | |
451 | * | |
452 | * Returns the 32 bit value from the offset specified. | |
453 | */ | |
d38ceaf9 AD |
454 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
455 | { | |
456 | if ((reg * 4) < adev->rio_mem_size) | |
457 | return ioread32(adev->rio_mem + (reg * 4)); | |
458 | else { | |
459 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
460 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
461 | } | |
462 | } | |
463 | ||
e3ecdffa AD |
464 | /** |
465 | * amdgpu_io_wreg - write to an IO register | |
466 | * | |
467 | * @adev: amdgpu_device pointer | |
468 | * @reg: dword aligned register offset | |
469 | * @v: 32 bit value to write to the register | |
470 | * | |
471 | * Writes the value specified to the offset specified. | |
472 | */ | |
d38ceaf9 AD |
473 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
474 | { | |
d38ceaf9 AD |
475 | if ((reg * 4) < adev->rio_mem_size) |
476 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
477 | else { | |
478 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
479 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
480 | } | |
481 | } | |
482 | ||
483 | /** | |
484 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
485 | * | |
486 | * @adev: amdgpu_device pointer | |
487 | * @index: doorbell index | |
488 | * | |
489 | * Returns the value in the doorbell aperture at the | |
490 | * requested doorbell index (CIK). | |
491 | */ | |
492 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
493 | { | |
494 | if (index < adev->doorbell.num_doorbells) { | |
495 | return readl(adev->doorbell.ptr + index); | |
496 | } else { | |
497 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
498 | return 0; | |
499 | } | |
500 | } | |
501 | ||
502 | /** | |
503 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
504 | * | |
505 | * @adev: amdgpu_device pointer | |
506 | * @index: doorbell index | |
507 | * @v: value to write | |
508 | * | |
509 | * Writes @v to the doorbell aperture at the | |
510 | * requested doorbell index (CIK). | |
511 | */ | |
512 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
513 | { | |
514 | if (index < adev->doorbell.num_doorbells) { | |
515 | writel(v, adev->doorbell.ptr + index); | |
516 | } else { | |
517 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
518 | } | |
519 | } | |
520 | ||
832be404 KW |
521 | /** |
522 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
523 | * | |
524 | * @adev: amdgpu_device pointer | |
525 | * @index: doorbell index | |
526 | * | |
527 | * Returns the value in the doorbell aperture at the | |
528 | * requested doorbell index (VEGA10+). | |
529 | */ | |
530 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
531 | { | |
532 | if (index < adev->doorbell.num_doorbells) { | |
533 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
534 | } else { | |
535 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
536 | return 0; | |
537 | } | |
538 | } | |
539 | ||
540 | /** | |
541 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
542 | * | |
543 | * @adev: amdgpu_device pointer | |
544 | * @index: doorbell index | |
545 | * @v: value to write | |
546 | * | |
547 | * Writes @v to the doorbell aperture at the | |
548 | * requested doorbell index (VEGA10+). | |
549 | */ | |
550 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
551 | { | |
552 | if (index < adev->doorbell.num_doorbells) { | |
553 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
554 | } else { | |
555 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
556 | } | |
557 | } | |
558 | ||
d38ceaf9 AD |
559 | /** |
560 | * amdgpu_invalid_rreg - dummy reg read function | |
561 | * | |
562 | * @adev: amdgpu device pointer | |
563 | * @reg: offset of register | |
564 | * | |
565 | * Dummy register read function. Used for register blocks | |
566 | * that certain asics don't have (all asics). | |
567 | * Returns the value in the register. | |
568 | */ | |
569 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
570 | { | |
571 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
572 | BUG(); | |
573 | return 0; | |
574 | } | |
575 | ||
576 | /** | |
577 | * amdgpu_invalid_wreg - dummy reg write function | |
578 | * | |
579 | * @adev: amdgpu device pointer | |
580 | * @reg: offset of register | |
581 | * @v: value to write to the register | |
582 | * | |
583 | * Dummy register read function. Used for register blocks | |
584 | * that certain asics don't have (all asics). | |
585 | */ | |
586 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
587 | { | |
588 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
589 | reg, v); | |
590 | BUG(); | |
591 | } | |
592 | ||
4fa1c6a6 TZ |
593 | /** |
594 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
595 | * | |
596 | * @adev: amdgpu device pointer | |
597 | * @reg: offset of register | |
598 | * | |
599 | * Dummy register read function. Used for register blocks | |
600 | * that certain asics don't have (all asics). | |
601 | * Returns the value in the register. | |
602 | */ | |
603 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
604 | { | |
605 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
606 | BUG(); | |
607 | return 0; | |
608 | } | |
609 | ||
610 | /** | |
611 | * amdgpu_invalid_wreg64 - dummy reg write function | |
612 | * | |
613 | * @adev: amdgpu device pointer | |
614 | * @reg: offset of register | |
615 | * @v: value to write to the register | |
616 | * | |
617 | * Dummy register read function. Used for register blocks | |
618 | * that certain asics don't have (all asics). | |
619 | */ | |
620 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
621 | { | |
622 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
623 | reg, v); | |
624 | BUG(); | |
625 | } | |
626 | ||
d38ceaf9 AD |
627 | /** |
628 | * amdgpu_block_invalid_rreg - dummy reg read function | |
629 | * | |
630 | * @adev: amdgpu device pointer | |
631 | * @block: offset of instance | |
632 | * @reg: offset of register | |
633 | * | |
634 | * Dummy register read function. Used for register blocks | |
635 | * that certain asics don't have (all asics). | |
636 | * Returns the value in the register. | |
637 | */ | |
638 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
639 | uint32_t block, uint32_t reg) | |
640 | { | |
641 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
642 | reg, block); | |
643 | BUG(); | |
644 | return 0; | |
645 | } | |
646 | ||
647 | /** | |
648 | * amdgpu_block_invalid_wreg - dummy reg write function | |
649 | * | |
650 | * @adev: amdgpu device pointer | |
651 | * @block: offset of instance | |
652 | * @reg: offset of register | |
653 | * @v: value to write to the register | |
654 | * | |
655 | * Dummy register read function. Used for register blocks | |
656 | * that certain asics don't have (all asics). | |
657 | */ | |
658 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
659 | uint32_t block, | |
660 | uint32_t reg, uint32_t v) | |
661 | { | |
662 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
663 | reg, block, v); | |
664 | BUG(); | |
665 | } | |
666 | ||
4d2997ab AD |
667 | /** |
668 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
669 | * | |
670 | * @dev: drm_device pointer | |
671 | * | |
672 | * Does any asic specific work and then calls atom asic init. | |
673 | */ | |
674 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
675 | { | |
676 | amdgpu_asic_pre_asic_init(adev); | |
677 | ||
678 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
679 | } | |
680 | ||
e3ecdffa AD |
681 | /** |
682 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
683 | * | |
684 | * @adev: amdgpu device pointer | |
685 | * | |
686 | * Allocates a scratch page of VRAM for use by various things in the | |
687 | * driver. | |
688 | */ | |
06ec9070 | 689 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 690 | { |
a4a02777 CK |
691 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
692 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
693 | &adev->vram_scratch.robj, | |
694 | &adev->vram_scratch.gpu_addr, | |
695 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
696 | } |
697 | ||
e3ecdffa AD |
698 | /** |
699 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
700 | * | |
701 | * @adev: amdgpu device pointer | |
702 | * | |
703 | * Frees the VRAM scratch page. | |
704 | */ | |
06ec9070 | 705 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 706 | { |
078af1a3 | 707 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
708 | } |
709 | ||
710 | /** | |
9c3f2b54 | 711 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
712 | * |
713 | * @adev: amdgpu_device pointer | |
714 | * @registers: pointer to the register array | |
715 | * @array_size: size of the register array | |
716 | * | |
717 | * Programs an array or registers with and and or masks. | |
718 | * This is a helper for setting golden registers. | |
719 | */ | |
9c3f2b54 AD |
720 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
721 | const u32 *registers, | |
722 | const u32 array_size) | |
d38ceaf9 AD |
723 | { |
724 | u32 tmp, reg, and_mask, or_mask; | |
725 | int i; | |
726 | ||
727 | if (array_size % 3) | |
728 | return; | |
729 | ||
730 | for (i = 0; i < array_size; i +=3) { | |
731 | reg = registers[i + 0]; | |
732 | and_mask = registers[i + 1]; | |
733 | or_mask = registers[i + 2]; | |
734 | ||
735 | if (and_mask == 0xffffffff) { | |
736 | tmp = or_mask; | |
737 | } else { | |
738 | tmp = RREG32(reg); | |
739 | tmp &= ~and_mask; | |
e0d07657 HZ |
740 | if (adev->family >= AMDGPU_FAMILY_AI) |
741 | tmp |= (or_mask & and_mask); | |
742 | else | |
743 | tmp |= or_mask; | |
d38ceaf9 AD |
744 | } |
745 | WREG32(reg, tmp); | |
746 | } | |
747 | } | |
748 | ||
e3ecdffa AD |
749 | /** |
750 | * amdgpu_device_pci_config_reset - reset the GPU | |
751 | * | |
752 | * @adev: amdgpu_device pointer | |
753 | * | |
754 | * Resets the GPU using the pci config reset sequence. | |
755 | * Only applicable to asics prior to vega10. | |
756 | */ | |
8111c387 | 757 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
758 | { |
759 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
760 | } | |
761 | ||
762 | /* | |
763 | * GPU doorbell aperture helpers function. | |
764 | */ | |
765 | /** | |
06ec9070 | 766 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
767 | * |
768 | * @adev: amdgpu_device pointer | |
769 | * | |
770 | * Init doorbell driver information (CIK) | |
771 | * Returns 0 on success, error on failure. | |
772 | */ | |
06ec9070 | 773 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 774 | { |
6585661d | 775 | |
705e519e CK |
776 | /* No doorbell on SI hardware generation */ |
777 | if (adev->asic_type < CHIP_BONAIRE) { | |
778 | adev->doorbell.base = 0; | |
779 | adev->doorbell.size = 0; | |
780 | adev->doorbell.num_doorbells = 0; | |
781 | adev->doorbell.ptr = NULL; | |
782 | return 0; | |
783 | } | |
784 | ||
d6895ad3 CK |
785 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
786 | return -EINVAL; | |
787 | ||
22357775 AD |
788 | amdgpu_asic_init_doorbell_index(adev); |
789 | ||
d38ceaf9 AD |
790 | /* doorbell bar mapping */ |
791 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
792 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
793 | ||
edf600da | 794 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 795 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
796 | if (adev->doorbell.num_doorbells == 0) |
797 | return -EINVAL; | |
798 | ||
ec3db8a6 | 799 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
800 | * paging queue doorbell use the second page. The |
801 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
802 | * doorbells are in the first page. So with paging queue enabled, | |
803 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
804 | */ |
805 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 806 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 807 | |
8972e5d2 CK |
808 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
809 | adev->doorbell.num_doorbells * | |
810 | sizeof(u32)); | |
811 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 812 | return -ENOMEM; |
d38ceaf9 AD |
813 | |
814 | return 0; | |
815 | } | |
816 | ||
817 | /** | |
06ec9070 | 818 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
819 | * |
820 | * @adev: amdgpu_device pointer | |
821 | * | |
822 | * Tear down doorbell driver information (CIK) | |
823 | */ | |
06ec9070 | 824 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
825 | { |
826 | iounmap(adev->doorbell.ptr); | |
827 | adev->doorbell.ptr = NULL; | |
828 | } | |
829 | ||
22cb0164 | 830 | |
d38ceaf9 AD |
831 | |
832 | /* | |
06ec9070 | 833 | * amdgpu_device_wb_*() |
455a7bc2 | 834 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 835 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
836 | */ |
837 | ||
838 | /** | |
06ec9070 | 839 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
840 | * |
841 | * @adev: amdgpu_device pointer | |
842 | * | |
843 | * Disables Writeback and frees the Writeback memory (all asics). | |
844 | * Used at driver shutdown. | |
845 | */ | |
06ec9070 | 846 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
847 | { |
848 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
849 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
850 | &adev->wb.gpu_addr, | |
851 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
852 | adev->wb.wb_obj = NULL; |
853 | } | |
854 | } | |
855 | ||
856 | /** | |
06ec9070 | 857 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
858 | * |
859 | * @adev: amdgpu_device pointer | |
860 | * | |
455a7bc2 | 861 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
862 | * Used at driver startup. |
863 | * Returns 0 on success or an -error on failure. | |
864 | */ | |
06ec9070 | 865 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
866 | { |
867 | int r; | |
868 | ||
869 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
870 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
871 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
872 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
873 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
874 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
875 | if (r) { |
876 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
877 | return r; | |
878 | } | |
d38ceaf9 AD |
879 | |
880 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
881 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
882 | ||
883 | /* clear wb memory */ | |
73469585 | 884 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
885 | } |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | /** | |
131b4b36 | 891 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
892 | * |
893 | * @adev: amdgpu_device pointer | |
894 | * @wb: wb index | |
895 | * | |
896 | * Allocate a wb slot for use by the driver (all asics). | |
897 | * Returns 0 on success or -EINVAL on failure. | |
898 | */ | |
131b4b36 | 899 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
900 | { |
901 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 902 | |
97407b63 | 903 | if (offset < adev->wb.num_wb) { |
7014285a | 904 | __set_bit(offset, adev->wb.used); |
63ae07ca | 905 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
906 | return 0; |
907 | } else { | |
908 | return -EINVAL; | |
909 | } | |
910 | } | |
911 | ||
d38ceaf9 | 912 | /** |
131b4b36 | 913 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
914 | * |
915 | * @adev: amdgpu_device pointer | |
916 | * @wb: wb index | |
917 | * | |
918 | * Free a wb slot allocated for use by the driver (all asics) | |
919 | */ | |
131b4b36 | 920 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 921 | { |
73469585 | 922 | wb >>= 3; |
d38ceaf9 | 923 | if (wb < adev->wb.num_wb) |
73469585 | 924 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
925 | } |
926 | ||
d6895ad3 CK |
927 | /** |
928 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
929 | * | |
930 | * @adev: amdgpu_device pointer | |
931 | * | |
932 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
933 | * to fail, but if any of the BARs is not accessible after the size we abort | |
934 | * driver loading by returning -ENODEV. | |
935 | */ | |
936 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
937 | { | |
770d13b1 | 938 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 939 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
940 | struct pci_bus *root; |
941 | struct resource *res; | |
942 | unsigned i; | |
d6895ad3 CK |
943 | u16 cmd; |
944 | int r; | |
945 | ||
0c03b912 | 946 | /* Bypass for VF */ |
947 | if (amdgpu_sriov_vf(adev)) | |
948 | return 0; | |
949 | ||
b7221f2b AD |
950 | /* skip if the bios has already enabled large BAR */ |
951 | if (adev->gmc.real_vram_size && | |
952 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
953 | return 0; | |
954 | ||
31b8adab CK |
955 | /* Check if the root BUS has 64bit memory resources */ |
956 | root = adev->pdev->bus; | |
957 | while (root->parent) | |
958 | root = root->parent; | |
959 | ||
960 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 961 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
962 | res->start > 0x100000000ull) |
963 | break; | |
964 | } | |
965 | ||
966 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
967 | if (!res) | |
968 | return 0; | |
969 | ||
d6895ad3 CK |
970 | /* Disable memory decoding while we change the BAR addresses and size */ |
971 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
972 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
973 | cmd & ~PCI_COMMAND_MEMORY); | |
974 | ||
975 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 976 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
977 | if (adev->asic_type >= CHIP_BONAIRE) |
978 | pci_release_resource(adev->pdev, 2); | |
979 | ||
980 | pci_release_resource(adev->pdev, 0); | |
981 | ||
982 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
983 | if (r == -ENOSPC) | |
984 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
985 | else if (r && r != -ENOTSUPP) | |
986 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
987 | ||
988 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
989 | ||
990 | /* When the doorbell or fb BAR isn't available we have no chance of | |
991 | * using the device. | |
992 | */ | |
06ec9070 | 993 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
994 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
995 | return -ENODEV; | |
996 | ||
997 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
998 | ||
999 | return 0; | |
1000 | } | |
a05502e5 | 1001 | |
d38ceaf9 AD |
1002 | /* |
1003 | * GPU helpers function. | |
1004 | */ | |
1005 | /** | |
39c640c0 | 1006 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1007 | * |
1008 | * @adev: amdgpu_device pointer | |
1009 | * | |
c836fec5 JQ |
1010 | * Check if the asic has been initialized (all asics) at driver startup |
1011 | * or post is needed if hw reset is performed. | |
1012 | * Returns true if need or false if not. | |
d38ceaf9 | 1013 | */ |
39c640c0 | 1014 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1015 | { |
1016 | uint32_t reg; | |
1017 | ||
bec86378 ML |
1018 | if (amdgpu_sriov_vf(adev)) |
1019 | return false; | |
1020 | ||
1021 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1022 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1023 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1024 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1025 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1026 | */ |
1027 | if (adev->asic_type == CHIP_FIJI) { | |
1028 | int err; | |
1029 | uint32_t fw_ver; | |
1030 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1031 | /* force vPost if error occured */ | |
1032 | if (err) | |
1033 | return true; | |
1034 | ||
1035 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1036 | if (fw_ver < 0x00160e00) |
1037 | return true; | |
bec86378 | 1038 | } |
bec86378 | 1039 | } |
91fe77eb | 1040 | |
1041 | if (adev->has_hw_reset) { | |
1042 | adev->has_hw_reset = false; | |
1043 | return true; | |
1044 | } | |
1045 | ||
1046 | /* bios scratch used on CIK+ */ | |
1047 | if (adev->asic_type >= CHIP_BONAIRE) | |
1048 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1049 | ||
1050 | /* check MEM_SIZE for older asics */ | |
1051 | reg = amdgpu_asic_get_config_memsize(adev); | |
1052 | ||
1053 | if ((reg != 0) && (reg != 0xffffffff)) | |
1054 | return false; | |
1055 | ||
1056 | return true; | |
bec86378 ML |
1057 | } |
1058 | ||
d38ceaf9 AD |
1059 | /* if we get transitioned to only one device, take VGA back */ |
1060 | /** | |
06ec9070 | 1061 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
1062 | * |
1063 | * @cookie: amdgpu_device pointer | |
1064 | * @state: enable/disable vga decode | |
1065 | * | |
1066 | * Enable/disable vga decode (all asics). | |
1067 | * Returns VGA resource flags. | |
1068 | */ | |
06ec9070 | 1069 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
1070 | { |
1071 | struct amdgpu_device *adev = cookie; | |
1072 | amdgpu_asic_set_vga_state(adev, state); | |
1073 | if (state) | |
1074 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1075 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1076 | else | |
1077 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1078 | } | |
1079 | ||
e3ecdffa AD |
1080 | /** |
1081 | * amdgpu_device_check_block_size - validate the vm block size | |
1082 | * | |
1083 | * @adev: amdgpu_device pointer | |
1084 | * | |
1085 | * Validates the vm block size specified via module parameter. | |
1086 | * The vm block size defines number of bits in page table versus page directory, | |
1087 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1088 | * page table and the remaining bits are in the page directory. | |
1089 | */ | |
06ec9070 | 1090 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1091 | { |
1092 | /* defines number of bits in page table versus page directory, | |
1093 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1094 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1095 | if (amdgpu_vm_block_size == -1) |
1096 | return; | |
a1adf8be | 1097 | |
bab4fee7 | 1098 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1099 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1100 | amdgpu_vm_block_size); | |
97489129 | 1101 | amdgpu_vm_block_size = -1; |
a1adf8be | 1102 | } |
a1adf8be CZ |
1103 | } |
1104 | ||
e3ecdffa AD |
1105 | /** |
1106 | * amdgpu_device_check_vm_size - validate the vm size | |
1107 | * | |
1108 | * @adev: amdgpu_device pointer | |
1109 | * | |
1110 | * Validates the vm size in GB specified via module parameter. | |
1111 | * The VM size is the size of the GPU virtual memory space in GB. | |
1112 | */ | |
06ec9070 | 1113 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1114 | { |
64dab074 AD |
1115 | /* no need to check the default value */ |
1116 | if (amdgpu_vm_size == -1) | |
1117 | return; | |
1118 | ||
83ca145d ZJ |
1119 | if (amdgpu_vm_size < 1) { |
1120 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1121 | amdgpu_vm_size); | |
f3368128 | 1122 | amdgpu_vm_size = -1; |
83ca145d | 1123 | } |
83ca145d ZJ |
1124 | } |
1125 | ||
7951e376 RZ |
1126 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1127 | { | |
1128 | struct sysinfo si; | |
a9d4fe2f | 1129 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1130 | uint64_t total_memory; |
1131 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1132 | uint64_t dram_size_three_GB = 0xB8000000; | |
1133 | ||
1134 | if (amdgpu_smu_memory_pool_size == 0) | |
1135 | return; | |
1136 | ||
1137 | if (!is_os_64) { | |
1138 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1139 | goto def_value; | |
1140 | } | |
1141 | si_meminfo(&si); | |
1142 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1143 | ||
1144 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1145 | (amdgpu_smu_memory_pool_size == 2)) { | |
1146 | if (total_memory < dram_size_three_GB) | |
1147 | goto def_value1; | |
1148 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1149 | (amdgpu_smu_memory_pool_size == 8)) { | |
1150 | if (total_memory < dram_size_seven_GB) | |
1151 | goto def_value1; | |
1152 | } else { | |
1153 | DRM_WARN("Smu memory pool size not supported\n"); | |
1154 | goto def_value; | |
1155 | } | |
1156 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1157 | ||
1158 | return; | |
1159 | ||
1160 | def_value1: | |
1161 | DRM_WARN("No enough system memory\n"); | |
1162 | def_value: | |
1163 | adev->pm.smu_prv_buffer_size = 0; | |
1164 | } | |
1165 | ||
d38ceaf9 | 1166 | /** |
06ec9070 | 1167 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1168 | * |
1169 | * @adev: amdgpu_device pointer | |
1170 | * | |
1171 | * Validates certain module parameters and updates | |
1172 | * the associated values used by the driver (all asics). | |
1173 | */ | |
912dfc84 | 1174 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1175 | { |
5b011235 CZ |
1176 | if (amdgpu_sched_jobs < 4) { |
1177 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1178 | amdgpu_sched_jobs); | |
1179 | amdgpu_sched_jobs = 4; | |
76117507 | 1180 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1181 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1182 | amdgpu_sched_jobs); | |
1183 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1184 | } | |
d38ceaf9 | 1185 | |
83e74db6 | 1186 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1187 | /* gart size must be greater or equal to 32M */ |
1188 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1189 | amdgpu_gart_size); | |
83e74db6 | 1190 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1191 | } |
1192 | ||
36d38372 | 1193 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1194 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1195 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1196 | amdgpu_gtt_size); | |
1197 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1198 | } |
1199 | ||
d07f14be RH |
1200 | /* valid range is between 4 and 9 inclusive */ |
1201 | if (amdgpu_vm_fragment_size != -1 && | |
1202 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1203 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1204 | amdgpu_vm_fragment_size = -1; | |
1205 | } | |
1206 | ||
5d5bd5e3 KW |
1207 | if (amdgpu_sched_hw_submission < 2) { |
1208 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1209 | amdgpu_sched_hw_submission); | |
1210 | amdgpu_sched_hw_submission = 2; | |
1211 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1212 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1213 | amdgpu_sched_hw_submission); | |
1214 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1215 | } | |
1216 | ||
7951e376 RZ |
1217 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1218 | ||
06ec9070 | 1219 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1220 | |
06ec9070 | 1221 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1222 | |
19aede77 | 1223 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1224 | |
c6252390 | 1225 | amdgpu_gmc_tmz_set(adev); |
01a8dcec | 1226 | |
a300de40 ML |
1227 | if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) { |
1228 | amdgpu_num_kcq = 8; | |
c16ce562 | 1229 | dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n"); |
a300de40 ML |
1230 | } |
1231 | ||
e3c00faa | 1232 | return 0; |
d38ceaf9 AD |
1233 | } |
1234 | ||
1235 | /** | |
1236 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1237 | * | |
1238 | * @pdev: pci dev pointer | |
1694467b | 1239 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1240 | * |
1241 | * Callback for the switcheroo driver. Suspends or resumes the | |
1242 | * the asics before or after it is powered up using ACPI methods. | |
1243 | */ | |
8aba21b7 LT |
1244 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1245 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1246 | { |
1247 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1248 | int r; |
d38ceaf9 | 1249 | |
31af062a | 1250 | if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1251 | return; |
1252 | ||
1253 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1254 | pr_info("switched on\n"); |
d38ceaf9 AD |
1255 | /* don't suspend or resume card normally */ |
1256 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1257 | ||
de185019 AD |
1258 | pci_set_power_state(dev->pdev, PCI_D0); |
1259 | pci_restore_state(dev->pdev); | |
1260 | r = pci_enable_device(dev->pdev); | |
1261 | if (r) | |
1262 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1263 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1264 | |
d38ceaf9 AD |
1265 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1266 | drm_kms_helper_poll_enable(dev); | |
1267 | } else { | |
dd4fa6c1 | 1268 | pr_info("switched off\n"); |
d38ceaf9 AD |
1269 | drm_kms_helper_poll_disable(dev); |
1270 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
de185019 AD |
1271 | amdgpu_device_suspend(dev, true); |
1272 | pci_save_state(dev->pdev); | |
1273 | /* Shut down the device */ | |
1274 | pci_disable_device(dev->pdev); | |
1275 | pci_set_power_state(dev->pdev, PCI_D3cold); | |
d38ceaf9 AD |
1276 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1277 | } | |
1278 | } | |
1279 | ||
1280 | /** | |
1281 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1282 | * | |
1283 | * @pdev: pci dev pointer | |
1284 | * | |
1285 | * Callback for the switcheroo driver. Check of the switcheroo | |
1286 | * state can be changed. | |
1287 | * Returns true if the state can be changed, false if not. | |
1288 | */ | |
1289 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1290 | { | |
1291 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1292 | ||
1293 | /* | |
1294 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1295 | * locking inversion with the driver load path. And the access here is | |
1296 | * completely racy anyway. So don't bother with locking for now. | |
1297 | */ | |
7e13ad89 | 1298 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1299 | } |
1300 | ||
1301 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1302 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1303 | .reprobe = NULL, | |
1304 | .can_switch = amdgpu_switcheroo_can_switch, | |
1305 | }; | |
1306 | ||
e3ecdffa AD |
1307 | /** |
1308 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1309 | * | |
87e3f136 | 1310 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1311 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1312 | * @state: clockgating state (gate or ungate) | |
1313 | * | |
1314 | * Sets the requested clockgating state for all instances of | |
1315 | * the hardware IP specified. | |
1316 | * Returns the error code from the last instance. | |
1317 | */ | |
43fa561f | 1318 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1319 | enum amd_ip_block_type block_type, |
1320 | enum amd_clockgating_state state) | |
d38ceaf9 | 1321 | { |
43fa561f | 1322 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1323 | int i, r = 0; |
1324 | ||
1325 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1326 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1327 | continue; |
c722865a RZ |
1328 | if (adev->ip_blocks[i].version->type != block_type) |
1329 | continue; | |
1330 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1331 | continue; | |
1332 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1333 | (void *)adev, state); | |
1334 | if (r) | |
1335 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1336 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1337 | } |
1338 | return r; | |
1339 | } | |
1340 | ||
e3ecdffa AD |
1341 | /** |
1342 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1343 | * | |
87e3f136 | 1344 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1345 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1346 | * @state: powergating state (gate or ungate) | |
1347 | * | |
1348 | * Sets the requested powergating state for all instances of | |
1349 | * the hardware IP specified. | |
1350 | * Returns the error code from the last instance. | |
1351 | */ | |
43fa561f | 1352 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1353 | enum amd_ip_block_type block_type, |
1354 | enum amd_powergating_state state) | |
d38ceaf9 | 1355 | { |
43fa561f | 1356 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1357 | int i, r = 0; |
1358 | ||
1359 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1360 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1361 | continue; |
c722865a RZ |
1362 | if (adev->ip_blocks[i].version->type != block_type) |
1363 | continue; | |
1364 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1365 | continue; | |
1366 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1367 | (void *)adev, state); | |
1368 | if (r) | |
1369 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1370 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1371 | } |
1372 | return r; | |
1373 | } | |
1374 | ||
e3ecdffa AD |
1375 | /** |
1376 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1377 | * | |
1378 | * @adev: amdgpu_device pointer | |
1379 | * @flags: clockgating feature flags | |
1380 | * | |
1381 | * Walks the list of IPs on the device and updates the clockgating | |
1382 | * flags for each IP. | |
1383 | * Updates @flags with the feature flags for each hardware IP where | |
1384 | * clockgating is enabled. | |
1385 | */ | |
2990a1fc AD |
1386 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1387 | u32 *flags) | |
6cb2d4e4 HR |
1388 | { |
1389 | int i; | |
1390 | ||
1391 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1392 | if (!adev->ip_blocks[i].status.valid) | |
1393 | continue; | |
1394 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1395 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1396 | } | |
1397 | } | |
1398 | ||
e3ecdffa AD |
1399 | /** |
1400 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1401 | * | |
1402 | * @adev: amdgpu_device pointer | |
1403 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1404 | * | |
1405 | * Waits for the request hardware IP to be idle. | |
1406 | * Returns 0 for success or a negative error code on failure. | |
1407 | */ | |
2990a1fc AD |
1408 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1409 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1410 | { |
1411 | int i, r; | |
1412 | ||
1413 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1414 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1415 | continue; |
a1255107 AD |
1416 | if (adev->ip_blocks[i].version->type == block_type) { |
1417 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1418 | if (r) |
1419 | return r; | |
1420 | break; | |
1421 | } | |
1422 | } | |
1423 | return 0; | |
1424 | ||
1425 | } | |
1426 | ||
e3ecdffa AD |
1427 | /** |
1428 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1429 | * | |
1430 | * @adev: amdgpu_device pointer | |
1431 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1432 | * | |
1433 | * Check if the hardware IP is idle or not. | |
1434 | * Returns true if it the IP is idle, false if not. | |
1435 | */ | |
2990a1fc AD |
1436 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1437 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1438 | { |
1439 | int i; | |
1440 | ||
1441 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1442 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1443 | continue; |
a1255107 AD |
1444 | if (adev->ip_blocks[i].version->type == block_type) |
1445 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1446 | } |
1447 | return true; | |
1448 | ||
1449 | } | |
1450 | ||
e3ecdffa AD |
1451 | /** |
1452 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1453 | * | |
1454 | * @adev: amdgpu_device pointer | |
87e3f136 | 1455 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1456 | * |
1457 | * Returns a pointer to the hardware IP block structure | |
1458 | * if it exists for the asic, otherwise NULL. | |
1459 | */ | |
2990a1fc AD |
1460 | struct amdgpu_ip_block * |
1461 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1462 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1463 | { |
1464 | int i; | |
1465 | ||
1466 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1467 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1468 | return &adev->ip_blocks[i]; |
1469 | ||
1470 | return NULL; | |
1471 | } | |
1472 | ||
1473 | /** | |
2990a1fc | 1474 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1475 | * |
1476 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1477 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1478 | * @major: major version |
1479 | * @minor: minor version | |
1480 | * | |
1481 | * return 0 if equal or greater | |
1482 | * return 1 if smaller or the ip_block doesn't exist | |
1483 | */ | |
2990a1fc AD |
1484 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1485 | enum amd_ip_block_type type, | |
1486 | u32 major, u32 minor) | |
d38ceaf9 | 1487 | { |
2990a1fc | 1488 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1489 | |
a1255107 AD |
1490 | if (ip_block && ((ip_block->version->major > major) || |
1491 | ((ip_block->version->major == major) && | |
1492 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1493 | return 0; |
1494 | ||
1495 | return 1; | |
1496 | } | |
1497 | ||
a1255107 | 1498 | /** |
2990a1fc | 1499 | * amdgpu_device_ip_block_add |
a1255107 AD |
1500 | * |
1501 | * @adev: amdgpu_device pointer | |
1502 | * @ip_block_version: pointer to the IP to add | |
1503 | * | |
1504 | * Adds the IP block driver information to the collection of IPs | |
1505 | * on the asic. | |
1506 | */ | |
2990a1fc AD |
1507 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1508 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1509 | { |
1510 | if (!ip_block_version) | |
1511 | return -EINVAL; | |
1512 | ||
e966a725 | 1513 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1514 | ip_block_version->funcs->name); |
1515 | ||
a1255107 AD |
1516 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
e3ecdffa AD |
1521 | /** |
1522 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1523 | * | |
1524 | * @adev: amdgpu_device pointer | |
1525 | * | |
1526 | * Enabled the virtual display feature if the user has enabled it via | |
1527 | * the module parameter virtual_display. This feature provides a virtual | |
1528 | * display hardware on headless boards or in virtualized environments. | |
1529 | * This function parses and validates the configuration string specified by | |
1530 | * the user and configues the virtual display configuration (number of | |
1531 | * virtual connectors, crtcs, etc.) specified. | |
1532 | */ | |
483ef985 | 1533 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1534 | { |
1535 | adev->enable_virtual_display = false; | |
1536 | ||
1537 | if (amdgpu_virtual_display) { | |
4a580877 | 1538 | struct drm_device *ddev = adev_to_drm(adev); |
9accf2fd | 1539 | const char *pci_address_name = pci_name(ddev->pdev); |
0f66356d | 1540 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1541 | |
1542 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1543 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1544 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1545 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1546 | if (!strcmp("all", pciaddname) |
1547 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1548 | long num_crtc; |
1549 | int res = -1; | |
1550 | ||
9accf2fd | 1551 | adev->enable_virtual_display = true; |
0f66356d ED |
1552 | |
1553 | if (pciaddname_tmp) | |
1554 | res = kstrtol(pciaddname_tmp, 10, | |
1555 | &num_crtc); | |
1556 | ||
1557 | if (!res) { | |
1558 | if (num_crtc < 1) | |
1559 | num_crtc = 1; | |
1560 | if (num_crtc > 6) | |
1561 | num_crtc = 6; | |
1562 | adev->mode_info.num_crtc = num_crtc; | |
1563 | } else { | |
1564 | adev->mode_info.num_crtc = 1; | |
1565 | } | |
9accf2fd ED |
1566 | break; |
1567 | } | |
1568 | } | |
1569 | ||
0f66356d ED |
1570 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1571 | amdgpu_virtual_display, pci_address_name, | |
1572 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1573 | |
1574 | kfree(pciaddstr); | |
1575 | } | |
1576 | } | |
1577 | ||
e3ecdffa AD |
1578 | /** |
1579 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1580 | * | |
1581 | * @adev: amdgpu_device pointer | |
1582 | * | |
1583 | * Parses the asic configuration parameters specified in the gpu info | |
1584 | * firmware and makes them availale to the driver for use in configuring | |
1585 | * the asic. | |
1586 | * Returns 0 on success, -EINVAL on failure. | |
1587 | */ | |
e2a75f88 AD |
1588 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1589 | { | |
e2a75f88 | 1590 | const char *chip_name; |
c0a43457 | 1591 | char fw_name[40]; |
e2a75f88 AD |
1592 | int err; |
1593 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1594 | ||
ab4fe3e1 HR |
1595 | adev->firmware.gpu_info_fw = NULL; |
1596 | ||
72de33f8 | 1597 | if (adev->mman.discovery_bin) { |
258620d0 | 1598 | amdgpu_discovery_get_gfx_info(adev); |
cc375d8c TY |
1599 | |
1600 | /* | |
1601 | * FIXME: The bounding box is still needed by Navi12, so | |
1602 | * temporarily read it from gpu_info firmware. Should be droped | |
1603 | * when DAL no longer needs it. | |
1604 | */ | |
1605 | if (adev->asic_type != CHIP_NAVI12) | |
1606 | return 0; | |
258620d0 AD |
1607 | } |
1608 | ||
e2a75f88 | 1609 | switch (adev->asic_type) { |
e2a75f88 AD |
1610 | #ifdef CONFIG_DRM_AMDGPU_SI |
1611 | case CHIP_VERDE: | |
1612 | case CHIP_TAHITI: | |
1613 | case CHIP_PITCAIRN: | |
1614 | case CHIP_OLAND: | |
1615 | case CHIP_HAINAN: | |
1616 | #endif | |
1617 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1618 | case CHIP_BONAIRE: | |
1619 | case CHIP_HAWAII: | |
1620 | case CHIP_KAVERI: | |
1621 | case CHIP_KABINI: | |
1622 | case CHIP_MULLINS: | |
1623 | #endif | |
da87c30b AD |
1624 | case CHIP_TOPAZ: |
1625 | case CHIP_TONGA: | |
1626 | case CHIP_FIJI: | |
1627 | case CHIP_POLARIS10: | |
1628 | case CHIP_POLARIS11: | |
1629 | case CHIP_POLARIS12: | |
1630 | case CHIP_VEGAM: | |
1631 | case CHIP_CARRIZO: | |
1632 | case CHIP_STONEY: | |
27c0bc71 | 1633 | case CHIP_VEGA20: |
e2a75f88 AD |
1634 | default: |
1635 | return 0; | |
1636 | case CHIP_VEGA10: | |
1637 | chip_name = "vega10"; | |
1638 | break; | |
3f76dced AD |
1639 | case CHIP_VEGA12: |
1640 | chip_name = "vega12"; | |
1641 | break; | |
2d2e5e7e | 1642 | case CHIP_RAVEN: |
54f78a76 | 1643 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1644 | chip_name = "raven2"; |
54f78a76 | 1645 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1646 | chip_name = "picasso"; |
54c4d17e FX |
1647 | else |
1648 | chip_name = "raven"; | |
2d2e5e7e | 1649 | break; |
65e60f6e LM |
1650 | case CHIP_ARCTURUS: |
1651 | chip_name = "arcturus"; | |
1652 | break; | |
b51a26a0 HR |
1653 | case CHIP_RENOIR: |
1654 | chip_name = "renoir"; | |
1655 | break; | |
23c6268e HR |
1656 | case CHIP_NAVI10: |
1657 | chip_name = "navi10"; | |
1658 | break; | |
ed42cfe1 XY |
1659 | case CHIP_NAVI14: |
1660 | chip_name = "navi14"; | |
1661 | break; | |
42b325e5 XY |
1662 | case CHIP_NAVI12: |
1663 | chip_name = "navi12"; | |
1664 | break; | |
c0a43457 LG |
1665 | case CHIP_SIENNA_CICHLID: |
1666 | chip_name = "sienna_cichlid"; | |
1667 | break; | |
120eb833 JC |
1668 | case CHIP_NAVY_FLOUNDER: |
1669 | chip_name = "navy_flounder"; | |
1670 | break; | |
e2a75f88 AD |
1671 | } |
1672 | ||
1673 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1674 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1675 | if (err) { |
1676 | dev_err(adev->dev, | |
1677 | "Failed to load gpu_info firmware \"%s\"\n", | |
1678 | fw_name); | |
1679 | goto out; | |
1680 | } | |
ab4fe3e1 | 1681 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1682 | if (err) { |
1683 | dev_err(adev->dev, | |
1684 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1685 | fw_name); | |
1686 | goto out; | |
1687 | } | |
1688 | ||
ab4fe3e1 | 1689 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1690 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1691 | ||
1692 | switch (hdr->version_major) { | |
1693 | case 1: | |
1694 | { | |
1695 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1696 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1697 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1698 | ||
cc375d8c TY |
1699 | /* |
1700 | * Should be droped when DAL no longer needs it. | |
1701 | */ | |
1702 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
1703 | goto parse_soc_bounding_box; |
1704 | ||
b5ab16bf AD |
1705 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1706 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1707 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1708 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1709 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1710 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1711 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1712 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1713 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1714 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1715 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1716 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1717 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1718 | adev->gfx.cu_info.max_waves_per_simd = |
1719 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1720 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1721 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1722 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 1723 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
1724 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
1725 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
1726 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1727 | adev->gfx.config.num_sc_per_sh = | |
1728 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
1729 | adev->gfx.config.num_packer_per_sc = | |
1730 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
1731 | } | |
ec51d3fa XY |
1732 | |
1733 | parse_soc_bounding_box: | |
ec51d3fa XY |
1734 | /* |
1735 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 1736 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 1737 | */ |
48321c3d HW |
1738 | if (hdr->version_minor == 2) { |
1739 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
1740 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
1741 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1742 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
1743 | } | |
e2a75f88 AD |
1744 | break; |
1745 | } | |
1746 | default: | |
1747 | dev_err(adev->dev, | |
1748 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1749 | err = -EINVAL; | |
1750 | goto out; | |
1751 | } | |
1752 | out: | |
e2a75f88 AD |
1753 | return err; |
1754 | } | |
1755 | ||
e3ecdffa AD |
1756 | /** |
1757 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1758 | * | |
1759 | * @adev: amdgpu_device pointer | |
1760 | * | |
1761 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1762 | * up each asic are discovered each IP's early_init callback is run. This | |
1763 | * is the first stage in initializing the asic. | |
1764 | * Returns 0 on success, negative error code on failure. | |
1765 | */ | |
06ec9070 | 1766 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1767 | { |
aaa36a97 | 1768 | int i, r; |
d38ceaf9 | 1769 | |
483ef985 | 1770 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1771 | |
00a979f3 | 1772 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 1773 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
1774 | if (r) |
1775 | return r; | |
00a979f3 WS |
1776 | } |
1777 | ||
d38ceaf9 | 1778 | switch (adev->asic_type) { |
33f34802 KW |
1779 | #ifdef CONFIG_DRM_AMDGPU_SI |
1780 | case CHIP_VERDE: | |
1781 | case CHIP_TAHITI: | |
1782 | case CHIP_PITCAIRN: | |
1783 | case CHIP_OLAND: | |
1784 | case CHIP_HAINAN: | |
295d0daf | 1785 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1786 | r = si_set_ip_blocks(adev); |
1787 | if (r) | |
1788 | return r; | |
1789 | break; | |
1790 | #endif | |
a2e73f56 AD |
1791 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1792 | case CHIP_BONAIRE: | |
1793 | case CHIP_HAWAII: | |
1794 | case CHIP_KAVERI: | |
1795 | case CHIP_KABINI: | |
1796 | case CHIP_MULLINS: | |
e1ad2d53 | 1797 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 1798 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
1799 | else |
1800 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
1801 | |
1802 | r = cik_set_ip_blocks(adev); | |
1803 | if (r) | |
1804 | return r; | |
1805 | break; | |
1806 | #endif | |
da87c30b AD |
1807 | case CHIP_TOPAZ: |
1808 | case CHIP_TONGA: | |
1809 | case CHIP_FIJI: | |
1810 | case CHIP_POLARIS10: | |
1811 | case CHIP_POLARIS11: | |
1812 | case CHIP_POLARIS12: | |
1813 | case CHIP_VEGAM: | |
1814 | case CHIP_CARRIZO: | |
1815 | case CHIP_STONEY: | |
1816 | if (adev->flags & AMD_IS_APU) | |
1817 | adev->family = AMDGPU_FAMILY_CZ; | |
1818 | else | |
1819 | adev->family = AMDGPU_FAMILY_VI; | |
1820 | ||
1821 | r = vi_set_ip_blocks(adev); | |
1822 | if (r) | |
1823 | return r; | |
1824 | break; | |
e48a3cd9 AD |
1825 | case CHIP_VEGA10: |
1826 | case CHIP_VEGA12: | |
e4bd8170 | 1827 | case CHIP_VEGA20: |
e48a3cd9 | 1828 | case CHIP_RAVEN: |
61cf44c1 | 1829 | case CHIP_ARCTURUS: |
b51a26a0 | 1830 | case CHIP_RENOIR: |
70534d1e | 1831 | if (adev->flags & AMD_IS_APU) |
2ca8a5d2 CZ |
1832 | adev->family = AMDGPU_FAMILY_RV; |
1833 | else | |
1834 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1835 | |
1836 | r = soc15_set_ip_blocks(adev); | |
1837 | if (r) | |
1838 | return r; | |
1839 | break; | |
0a5b8c7b | 1840 | case CHIP_NAVI10: |
7ecb5cd4 | 1841 | case CHIP_NAVI14: |
4808cf9c | 1842 | case CHIP_NAVI12: |
11e8aef5 | 1843 | case CHIP_SIENNA_CICHLID: |
41f446bf | 1844 | case CHIP_NAVY_FLOUNDER: |
0a5b8c7b HR |
1845 | adev->family = AMDGPU_FAMILY_NV; |
1846 | ||
1847 | r = nv_set_ip_blocks(adev); | |
1848 | if (r) | |
1849 | return r; | |
1850 | break; | |
d38ceaf9 AD |
1851 | default: |
1852 | /* FIXME: not supported yet */ | |
1853 | return -EINVAL; | |
1854 | } | |
1855 | ||
1884734a | 1856 | amdgpu_amdkfd_device_probe(adev); |
1857 | ||
3b94fb10 | 1858 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 1859 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 1860 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
00f54b97 | 1861 | |
d38ceaf9 AD |
1862 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1863 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1864 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1865 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1866 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1867 | } else { |
a1255107 AD |
1868 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1869 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1870 | if (r == -ENOENT) { |
a1255107 | 1871 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1872 | } else if (r) { |
a1255107 AD |
1873 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1874 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1875 | return r; |
2c1a2784 | 1876 | } else { |
a1255107 | 1877 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1878 | } |
974e6b64 | 1879 | } else { |
a1255107 | 1880 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1881 | } |
d38ceaf9 | 1882 | } |
21a249ca AD |
1883 | /* get the vbios after the asic_funcs are set up */ |
1884 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
1885 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1886 | if (r) | |
1887 | return r; | |
1888 | ||
21a249ca AD |
1889 | /* Read BIOS */ |
1890 | if (!amdgpu_get_bios(adev)) | |
1891 | return -EINVAL; | |
1892 | ||
1893 | r = amdgpu_atombios_init(adev); | |
1894 | if (r) { | |
1895 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
1896 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
1897 | return r; | |
1898 | } | |
1899 | } | |
d38ceaf9 AD |
1900 | } |
1901 | ||
395d1fb9 NH |
1902 | adev->cg_flags &= amdgpu_cg_mask; |
1903 | adev->pg_flags &= amdgpu_pg_mask; | |
1904 | ||
d38ceaf9 AD |
1905 | return 0; |
1906 | } | |
1907 | ||
0a4f2520 RZ |
1908 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
1909 | { | |
1910 | int i, r; | |
1911 | ||
1912 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1913 | if (!adev->ip_blocks[i].status.sw) | |
1914 | continue; | |
1915 | if (adev->ip_blocks[i].status.hw) | |
1916 | continue; | |
1917 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 1918 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
1919 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
1920 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1921 | if (r) { | |
1922 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1923 | adev->ip_blocks[i].version->funcs->name, r); | |
1924 | return r; | |
1925 | } | |
1926 | adev->ip_blocks[i].status.hw = true; | |
1927 | } | |
1928 | } | |
1929 | ||
1930 | return 0; | |
1931 | } | |
1932 | ||
1933 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
1934 | { | |
1935 | int i, r; | |
1936 | ||
1937 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1938 | if (!adev->ip_blocks[i].status.sw) | |
1939 | continue; | |
1940 | if (adev->ip_blocks[i].status.hw) | |
1941 | continue; | |
1942 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1943 | if (r) { | |
1944 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1945 | adev->ip_blocks[i].version->funcs->name, r); | |
1946 | return r; | |
1947 | } | |
1948 | adev->ip_blocks[i].status.hw = true; | |
1949 | } | |
1950 | ||
1951 | return 0; | |
1952 | } | |
1953 | ||
7a3e0bb2 RZ |
1954 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
1955 | { | |
1956 | int r = 0; | |
1957 | int i; | |
80f41f84 | 1958 | uint32_t smu_version; |
7a3e0bb2 RZ |
1959 | |
1960 | if (adev->asic_type >= CHIP_VEGA10) { | |
1961 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
1962 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
1963 | continue; | |
1964 | ||
1965 | /* no need to do the fw loading again if already done*/ | |
1966 | if (adev->ip_blocks[i].status.hw == true) | |
1967 | break; | |
1968 | ||
53b3f8f4 | 1969 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
1970 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
1971 | if (r) { | |
1972 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 1973 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
1974 | return r; |
1975 | } | |
1976 | } else { | |
1977 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1978 | if (r) { | |
1979 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1980 | adev->ip_blocks[i].version->funcs->name, r); | |
1981 | return r; | |
7a3e0bb2 | 1982 | } |
7a3e0bb2 | 1983 | } |
482f0e53 ML |
1984 | |
1985 | adev->ip_blocks[i].status.hw = true; | |
1986 | break; | |
7a3e0bb2 RZ |
1987 | } |
1988 | } | |
482f0e53 | 1989 | |
8973d9ec ED |
1990 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
1991 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 1992 | |
80f41f84 | 1993 | return r; |
7a3e0bb2 RZ |
1994 | } |
1995 | ||
e3ecdffa AD |
1996 | /** |
1997 | * amdgpu_device_ip_init - run init for hardware IPs | |
1998 | * | |
1999 | * @adev: amdgpu_device pointer | |
2000 | * | |
2001 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2002 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2003 | * are run. sw_init initializes the software state associated with each IP | |
2004 | * and hw_init initializes the hardware associated with each IP. | |
2005 | * Returns 0 on success, negative error code on failure. | |
2006 | */ | |
06ec9070 | 2007 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2008 | { |
2009 | int i, r; | |
2010 | ||
c030f2e4 | 2011 | r = amdgpu_ras_init(adev); |
2012 | if (r) | |
2013 | return r; | |
2014 | ||
d38ceaf9 | 2015 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2016 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2017 | continue; |
a1255107 | 2018 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2019 | if (r) { |
a1255107 AD |
2020 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2021 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2022 | goto init_failed; |
2c1a2784 | 2023 | } |
a1255107 | 2024 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2025 | |
d38ceaf9 | 2026 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2027 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 2028 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2029 | if (r) { |
2030 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2031 | goto init_failed; |
2c1a2784 | 2032 | } |
a1255107 | 2033 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2034 | if (r) { |
2035 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2036 | goto init_failed; |
2c1a2784 | 2037 | } |
06ec9070 | 2038 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2039 | if (r) { |
06ec9070 | 2040 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2041 | goto init_failed; |
2c1a2784 | 2042 | } |
a1255107 | 2043 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2044 | |
2045 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2046 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2047 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2048 | AMDGPU_GEM_DOMAIN_VRAM, | |
2049 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2050 | if (r) { |
2051 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2052 | goto init_failed; |
2493664f ML |
2053 | } |
2054 | } | |
d38ceaf9 AD |
2055 | } |
2056 | } | |
2057 | ||
c9ffa427 YT |
2058 | if (amdgpu_sriov_vf(adev)) |
2059 | amdgpu_virt_init_data_exchange(adev); | |
2060 | ||
533aed27 AG |
2061 | r = amdgpu_ib_pool_init(adev); |
2062 | if (r) { | |
2063 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2064 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2065 | goto init_failed; | |
2066 | } | |
2067 | ||
c8963ea4 RZ |
2068 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2069 | if (r) | |
72d3f592 | 2070 | goto init_failed; |
0a4f2520 RZ |
2071 | |
2072 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2073 | if (r) | |
72d3f592 | 2074 | goto init_failed; |
0a4f2520 | 2075 | |
7a3e0bb2 RZ |
2076 | r = amdgpu_device_fw_loading(adev); |
2077 | if (r) | |
72d3f592 | 2078 | goto init_failed; |
7a3e0bb2 | 2079 | |
0a4f2520 RZ |
2080 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2081 | if (r) | |
72d3f592 | 2082 | goto init_failed; |
d38ceaf9 | 2083 | |
121a2bc6 AG |
2084 | /* |
2085 | * retired pages will be loaded from eeprom and reserved here, | |
2086 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2087 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2088 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2089 | * |
2090 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2091 | * failure from bad gpu situation and stop amdgpu init process | |
2092 | * accordingly. For other failed cases, it will still release all | |
2093 | * the resource and print error message, rather than returning one | |
2094 | * negative value to upper level. | |
121a2bc6 AG |
2095 | * |
2096 | * Note: theoretically, this should be called before all vram allocations | |
2097 | * to protect retired page from abusing | |
2098 | */ | |
b82e65a9 GC |
2099 | r = amdgpu_ras_recovery_init(adev); |
2100 | if (r) | |
2101 | goto init_failed; | |
121a2bc6 | 2102 | |
3e2e2ab5 HZ |
2103 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2104 | amdgpu_xgmi_add_device(adev); | |
1884734a | 2105 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 2106 | |
bd607166 KR |
2107 | amdgpu_fru_get_product_info(adev); |
2108 | ||
72d3f592 | 2109 | init_failed: |
c9ffa427 | 2110 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2111 | amdgpu_virt_release_full_gpu(adev, true); |
2112 | ||
72d3f592 | 2113 | return r; |
d38ceaf9 AD |
2114 | } |
2115 | ||
e3ecdffa AD |
2116 | /** |
2117 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2118 | * | |
2119 | * @adev: amdgpu_device pointer | |
2120 | * | |
2121 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2122 | * this function before a GPU reset. If the value is retained after a | |
2123 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2124 | */ | |
06ec9070 | 2125 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2126 | { |
2127 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2128 | } | |
2129 | ||
e3ecdffa AD |
2130 | /** |
2131 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2132 | * | |
2133 | * @adev: amdgpu_device pointer | |
2134 | * | |
2135 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2136 | * The driver calls this after a GPU reset to see if the contents of | |
2137 | * VRAM is lost or now. | |
2138 | * returns true if vram is lost, false if not. | |
2139 | */ | |
06ec9070 | 2140 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2141 | { |
dadce777 EQ |
2142 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2143 | AMDGPU_RESET_MAGIC_NUM)) | |
2144 | return true; | |
2145 | ||
53b3f8f4 | 2146 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2147 | return false; |
2148 | ||
2149 | /* | |
2150 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2151 | * always assumed to be lost. | |
2152 | */ | |
2153 | switch (amdgpu_asic_reset_method(adev)) { | |
2154 | case AMD_RESET_METHOD_BACO: | |
2155 | case AMD_RESET_METHOD_MODE1: | |
2156 | return true; | |
2157 | default: | |
2158 | return false; | |
2159 | } | |
0c49e0b8 CZ |
2160 | } |
2161 | ||
e3ecdffa | 2162 | /** |
1112a46b | 2163 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2164 | * |
2165 | * @adev: amdgpu_device pointer | |
b8b72130 | 2166 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2167 | * |
e3ecdffa | 2168 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2169 | * set_clockgating_state callbacks are run. |
2170 | * Late initialization pass enabling clockgating for hardware IPs. | |
2171 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2172 | * Returns 0 on success, negative error code on failure. |
2173 | */ | |
fdd34271 | 2174 | |
1112a46b RZ |
2175 | static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2176 | enum amd_clockgating_state state) | |
d38ceaf9 | 2177 | { |
1112a46b | 2178 | int i, j, r; |
d38ceaf9 | 2179 | |
4a2ba394 SL |
2180 | if (amdgpu_emu_mode == 1) |
2181 | return 0; | |
2182 | ||
1112a46b RZ |
2183 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2184 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2185 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2186 | continue; |
4a446d55 | 2187 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2188 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2189 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2190 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2191 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2192 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2193 | /* enable clockgating to save power */ |
a1255107 | 2194 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2195 | state); |
4a446d55 AD |
2196 | if (r) { |
2197 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2198 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2199 | return r; |
2200 | } | |
b0b00ff1 | 2201 | } |
d38ceaf9 | 2202 | } |
06b18f61 | 2203 | |
c9f96fd5 RZ |
2204 | return 0; |
2205 | } | |
2206 | ||
1112a46b | 2207 | static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state) |
c9f96fd5 | 2208 | { |
1112a46b | 2209 | int i, j, r; |
06b18f61 | 2210 | |
c9f96fd5 RZ |
2211 | if (amdgpu_emu_mode == 1) |
2212 | return 0; | |
2213 | ||
1112a46b RZ |
2214 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2215 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2216 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 RZ |
2217 | continue; |
2218 | /* skip CG for VCE/UVD, it's handled specially */ | |
2219 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2220 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2221 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2222 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2223 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2224 | /* enable powergating to save power */ | |
2225 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2226 | state); |
c9f96fd5 RZ |
2227 | if (r) { |
2228 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2229 | adev->ip_blocks[i].version->funcs->name, r); | |
2230 | return r; | |
2231 | } | |
2232 | } | |
2233 | } | |
2dc80b00 S |
2234 | return 0; |
2235 | } | |
2236 | ||
beff74bc AD |
2237 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2238 | { | |
2239 | struct amdgpu_gpu_instance *gpu_ins; | |
2240 | struct amdgpu_device *adev; | |
2241 | int i, ret = 0; | |
2242 | ||
2243 | mutex_lock(&mgpu_info.mutex); | |
2244 | ||
2245 | /* | |
2246 | * MGPU fan boost feature should be enabled | |
2247 | * only when there are two or more dGPUs in | |
2248 | * the system | |
2249 | */ | |
2250 | if (mgpu_info.num_dgpu < 2) | |
2251 | goto out; | |
2252 | ||
2253 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2254 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2255 | adev = gpu_ins->adev; | |
2256 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2257 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2258 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2259 | if (ret) | |
2260 | break; | |
2261 | ||
2262 | gpu_ins->mgpu_fan_enabled = 1; | |
2263 | } | |
2264 | } | |
2265 | ||
2266 | out: | |
2267 | mutex_unlock(&mgpu_info.mutex); | |
2268 | ||
2269 | return ret; | |
2270 | } | |
2271 | ||
e3ecdffa AD |
2272 | /** |
2273 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2274 | * | |
2275 | * @adev: amdgpu_device pointer | |
2276 | * | |
2277 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2278 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2279 | * late_init covers any special initialization that an IP requires | |
2280 | * after all of the have been initialized or something that needs to happen | |
2281 | * late in the init process. | |
2282 | * Returns 0 on success, negative error code on failure. | |
2283 | */ | |
06ec9070 | 2284 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2285 | { |
60599a03 | 2286 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2287 | int i = 0, r; |
2288 | ||
2289 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2290 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2291 | continue; |
2292 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2293 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2294 | if (r) { | |
2295 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2296 | adev->ip_blocks[i].version->funcs->name, r); | |
2297 | return r; | |
2298 | } | |
2dc80b00 | 2299 | } |
73f847db | 2300 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2301 | } |
2302 | ||
a891d239 DL |
2303 | amdgpu_ras_set_error_query_ready(adev, true); |
2304 | ||
1112a46b RZ |
2305 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2306 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2307 | |
06ec9070 | 2308 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2309 | |
beff74bc AD |
2310 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2311 | if (r) | |
2312 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2313 | ||
60599a03 EQ |
2314 | |
2315 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2316 | mutex_lock(&mgpu_info.mutex); | |
2317 | ||
2318 | /* | |
2319 | * Reset device p-state to low as this was booted with high. | |
2320 | * | |
2321 | * This should be performed only after all devices from the same | |
2322 | * hive get initialized. | |
2323 | * | |
2324 | * However, it's unknown how many device in the hive in advance. | |
2325 | * As this is counted one by one during devices initializations. | |
2326 | * | |
2327 | * So, we wait for all XGMI interlinked devices initialized. | |
2328 | * This may bring some delays as those devices may come from | |
2329 | * different hives. But that should be OK. | |
2330 | */ | |
2331 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2332 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2333 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2334 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2335 | continue; | |
2336 | ||
d84a430d JK |
2337 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2338 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2339 | if (r) { |
2340 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2341 | break; | |
2342 | } | |
2343 | } | |
2344 | } | |
2345 | ||
2346 | mutex_unlock(&mgpu_info.mutex); | |
2347 | } | |
2348 | ||
d38ceaf9 AD |
2349 | return 0; |
2350 | } | |
2351 | ||
e3ecdffa AD |
2352 | /** |
2353 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2354 | * | |
2355 | * @adev: amdgpu_device pointer | |
2356 | * | |
2357 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2358 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2359 | * are run. hw_fini tears down the hardware associated with each IP | |
2360 | * and sw_fini tears down any software state associated with each IP. | |
2361 | * Returns 0 on success, negative error code on failure. | |
2362 | */ | |
06ec9070 | 2363 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
2364 | { |
2365 | int i, r; | |
2366 | ||
5278a159 SY |
2367 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) |
2368 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2369 | ||
c030f2e4 | 2370 | amdgpu_ras_pre_fini(adev); |
2371 | ||
a82400b5 AG |
2372 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2373 | amdgpu_xgmi_remove_device(adev); | |
2374 | ||
1884734a | 2375 | amdgpu_amdkfd_device_fini(adev); |
05df1f01 RZ |
2376 | |
2377 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); | |
fdd34271 RZ |
2378 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2379 | ||
3e96dbfd AD |
2380 | /* need to disable SMC first */ |
2381 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2382 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 2383 | continue; |
fdd34271 | 2384 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 2385 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
2386 | /* XXX handle errors */ |
2387 | if (r) { | |
2388 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 2389 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 2390 | } |
a1255107 | 2391 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
2392 | break; |
2393 | } | |
2394 | } | |
2395 | ||
d38ceaf9 | 2396 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2397 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2398 | continue; |
8201a67a | 2399 | |
a1255107 | 2400 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2401 | /* XXX handle errors */ |
2c1a2784 | 2402 | if (r) { |
a1255107 AD |
2403 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2404 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2405 | } |
8201a67a | 2406 | |
a1255107 | 2407 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2408 | } |
2409 | ||
9950cda2 | 2410 | |
d38ceaf9 | 2411 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2412 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2413 | continue; |
c12aba3a ML |
2414 | |
2415 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2416 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2417 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2418 | amdgpu_device_wb_fini(adev); |
2419 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2420 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2421 | } |
2422 | ||
a1255107 | 2423 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2424 | /* XXX handle errors */ |
2c1a2784 | 2425 | if (r) { |
a1255107 AD |
2426 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2427 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2428 | } |
a1255107 AD |
2429 | adev->ip_blocks[i].status.sw = false; |
2430 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2431 | } |
2432 | ||
a6dcfd9c | 2433 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2434 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2435 | continue; |
a1255107 AD |
2436 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2437 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2438 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2439 | } |
2440 | ||
c030f2e4 | 2441 | amdgpu_ras_fini(adev); |
2442 | ||
030308fc | 2443 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
2444 | if (amdgpu_virt_release_full_gpu(adev, false)) |
2445 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 2446 | |
d38ceaf9 AD |
2447 | return 0; |
2448 | } | |
2449 | ||
e3ecdffa | 2450 | /** |
beff74bc | 2451 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2452 | * |
1112a46b | 2453 | * @work: work_struct. |
e3ecdffa | 2454 | */ |
beff74bc | 2455 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2456 | { |
2457 | struct amdgpu_device *adev = | |
beff74bc | 2458 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2459 | int r; |
2460 | ||
2461 | r = amdgpu_ib_ring_tests(adev); | |
2462 | if (r) | |
2463 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2464 | } |
2465 | ||
1e317b99 RZ |
2466 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2467 | { | |
2468 | struct amdgpu_device *adev = | |
2469 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2470 | ||
2471 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
2472 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
2473 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2474 | adev->gfx.gfx_off_state = true; | |
2475 | } | |
2476 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
2477 | } | |
2478 | ||
e3ecdffa | 2479 | /** |
e7854a03 | 2480 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2481 | * |
2482 | * @adev: amdgpu_device pointer | |
2483 | * | |
2484 | * Main suspend function for hardware IPs. The list of all the hardware | |
2485 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2486 | * suspend callbacks are run. suspend puts the hardware and software state | |
2487 | * in each IP into a state suitable for suspend. | |
2488 | * Returns 0 on success, negative error code on failure. | |
2489 | */ | |
e7854a03 AD |
2490 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2491 | { | |
2492 | int i, r; | |
2493 | ||
ced1ba97 PL |
2494 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2495 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2496 | |
e7854a03 AD |
2497 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2498 | if (!adev->ip_blocks[i].status.valid) | |
2499 | continue; | |
2b9f7848 | 2500 | |
e7854a03 | 2501 | /* displays are handled separately */ |
2b9f7848 ND |
2502 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2503 | continue; | |
2504 | ||
2505 | /* XXX handle errors */ | |
2506 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2507 | /* XXX handle errors */ | |
2508 | if (r) { | |
2509 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2510 | adev->ip_blocks[i].version->funcs->name, r); | |
2511 | return r; | |
e7854a03 | 2512 | } |
2b9f7848 ND |
2513 | |
2514 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2515 | } |
2516 | ||
e7854a03 AD |
2517 | return 0; |
2518 | } | |
2519 | ||
2520 | /** | |
2521 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2522 | * | |
2523 | * @adev: amdgpu_device pointer | |
2524 | * | |
2525 | * Main suspend function for hardware IPs. The list of all the hardware | |
2526 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2527 | * suspend callbacks are run. suspend puts the hardware and software state | |
2528 | * in each IP into a state suitable for suspend. | |
2529 | * Returns 0 on success, negative error code on failure. | |
2530 | */ | |
2531 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2532 | { |
2533 | int i, r; | |
2534 | ||
2535 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 2536 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2537 | continue; |
e7854a03 AD |
2538 | /* displays are handled in phase1 */ |
2539 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2540 | continue; | |
bff77e86 LM |
2541 | /* PSP lost connection when err_event_athub occurs */ |
2542 | if (amdgpu_ras_intr_triggered() && | |
2543 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2544 | adev->ip_blocks[i].status.hw = false; | |
2545 | continue; | |
2546 | } | |
d38ceaf9 | 2547 | /* XXX handle errors */ |
a1255107 | 2548 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2549 | /* XXX handle errors */ |
2c1a2784 | 2550 | if (r) { |
a1255107 AD |
2551 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2552 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2553 | } |
876923fb | 2554 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 2555 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
2556 | if(!amdgpu_sriov_vf(adev)){ |
2557 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2558 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
2559 | if (r) { | |
2560 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2561 | adev->mp1_state, r); | |
2562 | return r; | |
2563 | } | |
a3a09142 AD |
2564 | } |
2565 | } | |
b5507c7e | 2566 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2567 | } |
2568 | ||
2569 | return 0; | |
2570 | } | |
2571 | ||
e7854a03 AD |
2572 | /** |
2573 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2574 | * | |
2575 | * @adev: amdgpu_device pointer | |
2576 | * | |
2577 | * Main suspend function for hardware IPs. The list of all the hardware | |
2578 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2579 | * suspend callbacks are run. suspend puts the hardware and software state | |
2580 | * in each IP into a state suitable for suspend. | |
2581 | * Returns 0 on success, negative error code on failure. | |
2582 | */ | |
2583 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2584 | { | |
2585 | int r; | |
2586 | ||
e7819644 YT |
2587 | if (amdgpu_sriov_vf(adev)) |
2588 | amdgpu_virt_request_full_gpu(adev, false); | |
2589 | ||
e7854a03 AD |
2590 | r = amdgpu_device_ip_suspend_phase1(adev); |
2591 | if (r) | |
2592 | return r; | |
2593 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2594 | ||
e7819644 YT |
2595 | if (amdgpu_sriov_vf(adev)) |
2596 | amdgpu_virt_release_full_gpu(adev, false); | |
2597 | ||
e7854a03 AD |
2598 | return r; |
2599 | } | |
2600 | ||
06ec9070 | 2601 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2602 | { |
2603 | int i, r; | |
2604 | ||
2cb681b6 ML |
2605 | static enum amd_ip_block_type ip_order[] = { |
2606 | AMD_IP_BLOCK_TYPE_GMC, | |
2607 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2608 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2609 | AMD_IP_BLOCK_TYPE_IH, |
2610 | }; | |
a90ad3c2 | 2611 | |
2cb681b6 ML |
2612 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2613 | int j; | |
2614 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2615 | |
4cd2a96d J |
2616 | block = &adev->ip_blocks[i]; |
2617 | block->status.hw = false; | |
2cb681b6 | 2618 | |
4cd2a96d | 2619 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 2620 | |
4cd2a96d | 2621 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
2622 | !block->status.valid) |
2623 | continue; | |
2624 | ||
2625 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2626 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2627 | if (r) |
2628 | return r; | |
482f0e53 | 2629 | block->status.hw = true; |
a90ad3c2 ML |
2630 | } |
2631 | } | |
2632 | ||
2633 | return 0; | |
2634 | } | |
2635 | ||
06ec9070 | 2636 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2637 | { |
2638 | int i, r; | |
2639 | ||
2cb681b6 ML |
2640 | static enum amd_ip_block_type ip_order[] = { |
2641 | AMD_IP_BLOCK_TYPE_SMC, | |
2642 | AMD_IP_BLOCK_TYPE_DCE, | |
2643 | AMD_IP_BLOCK_TYPE_GFX, | |
2644 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 2645 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
2646 | AMD_IP_BLOCK_TYPE_VCE, |
2647 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 2648 | }; |
a90ad3c2 | 2649 | |
2cb681b6 ML |
2650 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2651 | int j; | |
2652 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2653 | |
2cb681b6 ML |
2654 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2655 | block = &adev->ip_blocks[j]; | |
2656 | ||
2657 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
2658 | !block->status.valid || |
2659 | block->status.hw) | |
2cb681b6 ML |
2660 | continue; |
2661 | ||
895bd048 JZ |
2662 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
2663 | r = block->version->funcs->resume(adev); | |
2664 | else | |
2665 | r = block->version->funcs->hw_init(adev); | |
2666 | ||
0aaeefcc | 2667 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2668 | if (r) |
2669 | return r; | |
482f0e53 | 2670 | block->status.hw = true; |
a90ad3c2 ML |
2671 | } |
2672 | } | |
2673 | ||
2674 | return 0; | |
2675 | } | |
2676 | ||
e3ecdffa AD |
2677 | /** |
2678 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2679 | * | |
2680 | * @adev: amdgpu_device pointer | |
2681 | * | |
2682 | * First resume function for hardware IPs. The list of all the hardware | |
2683 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2684 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2685 | * after a suspend and updates the software state as necessary. This | |
2686 | * function is also used for restoring the GPU after a GPU reset. | |
2687 | * Returns 0 on success, negative error code on failure. | |
2688 | */ | |
06ec9070 | 2689 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2690 | { |
2691 | int i, r; | |
2692 | ||
a90ad3c2 | 2693 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 2694 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 2695 | continue; |
a90ad3c2 | 2696 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2697 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2698 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 2699 | |
fcf0649f CZ |
2700 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2701 | if (r) { | |
2702 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2703 | adev->ip_blocks[i].version->funcs->name, r); | |
2704 | return r; | |
2705 | } | |
482f0e53 | 2706 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
2707 | } |
2708 | } | |
2709 | ||
2710 | return 0; | |
2711 | } | |
2712 | ||
e3ecdffa AD |
2713 | /** |
2714 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2715 | * | |
2716 | * @adev: amdgpu_device pointer | |
2717 | * | |
2718 | * First resume function for hardware IPs. The list of all the hardware | |
2719 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2720 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2721 | * functional state after a suspend and updates the software state as | |
2722 | * necessary. This function is also used for restoring the GPU after a GPU | |
2723 | * reset. | |
2724 | * Returns 0 on success, negative error code on failure. | |
2725 | */ | |
06ec9070 | 2726 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2727 | { |
2728 | int i, r; | |
2729 | ||
2730 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 2731 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2732 | continue; |
fcf0649f | 2733 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 2734 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
2735 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
2736 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 2737 | continue; |
a1255107 | 2738 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2739 | if (r) { |
a1255107 AD |
2740 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2741 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2742 | return r; |
2c1a2784 | 2743 | } |
482f0e53 | 2744 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
2745 | } |
2746 | ||
2747 | return 0; | |
2748 | } | |
2749 | ||
e3ecdffa AD |
2750 | /** |
2751 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2752 | * | |
2753 | * @adev: amdgpu_device pointer | |
2754 | * | |
2755 | * Main resume function for hardware IPs. The hardware IPs | |
2756 | * are split into two resume functions because they are | |
2757 | * are also used in in recovering from a GPU reset and some additional | |
2758 | * steps need to be take between them. In this case (S3/S4) they are | |
2759 | * run sequentially. | |
2760 | * Returns 0 on success, negative error code on failure. | |
2761 | */ | |
06ec9070 | 2762 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2763 | { |
2764 | int r; | |
2765 | ||
06ec9070 | 2766 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2767 | if (r) |
2768 | return r; | |
7a3e0bb2 RZ |
2769 | |
2770 | r = amdgpu_device_fw_loading(adev); | |
2771 | if (r) | |
2772 | return r; | |
2773 | ||
06ec9070 | 2774 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2775 | |
2776 | return r; | |
2777 | } | |
2778 | ||
e3ecdffa AD |
2779 | /** |
2780 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2781 | * | |
2782 | * @adev: amdgpu_device pointer | |
2783 | * | |
2784 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2785 | */ | |
4e99a44e | 2786 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2787 | { |
6867e1b5 ML |
2788 | if (amdgpu_sriov_vf(adev)) { |
2789 | if (adev->is_atom_fw) { | |
2790 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2791 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2792 | } else { | |
2793 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2794 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2795 | } | |
2796 | ||
2797 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2798 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2799 | } |
048765ad AR |
2800 | } |
2801 | ||
e3ecdffa AD |
2802 | /** |
2803 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2804 | * | |
2805 | * @asic_type: AMD asic type | |
2806 | * | |
2807 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2808 | * returns true if DC has support, false if not. | |
2809 | */ | |
4562236b HW |
2810 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2811 | { | |
2812 | switch (asic_type) { | |
2813 | #if defined(CONFIG_DRM_AMD_DC) | |
64200c46 MR |
2814 | #if defined(CONFIG_DRM_AMD_DC_SI) |
2815 | case CHIP_TAHITI: | |
2816 | case CHIP_PITCAIRN: | |
2817 | case CHIP_VERDE: | |
2818 | case CHIP_OLAND: | |
2819 | #endif | |
4562236b | 2820 | case CHIP_BONAIRE: |
0d6fbccb | 2821 | case CHIP_KAVERI: |
367e6687 AD |
2822 | case CHIP_KABINI: |
2823 | case CHIP_MULLINS: | |
d9fda248 HW |
2824 | /* |
2825 | * We have systems in the wild with these ASICs that require | |
2826 | * LVDS and VGA support which is not supported with DC. | |
2827 | * | |
2828 | * Fallback to the non-DC driver here by default so as not to | |
2829 | * cause regressions. | |
2830 | */ | |
2831 | return amdgpu_dc > 0; | |
2832 | case CHIP_HAWAII: | |
4562236b HW |
2833 | case CHIP_CARRIZO: |
2834 | case CHIP_STONEY: | |
4562236b | 2835 | case CHIP_POLARIS10: |
675fd32b | 2836 | case CHIP_POLARIS11: |
2c8ad2d5 | 2837 | case CHIP_POLARIS12: |
675fd32b | 2838 | case CHIP_VEGAM: |
4562236b HW |
2839 | case CHIP_TONGA: |
2840 | case CHIP_FIJI: | |
42f8ffa1 | 2841 | case CHIP_VEGA10: |
dca7b401 | 2842 | case CHIP_VEGA12: |
c6034aa2 | 2843 | case CHIP_VEGA20: |
b86a1aa3 | 2844 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
fd187853 | 2845 | case CHIP_RAVEN: |
b4f199c7 | 2846 | case CHIP_NAVI10: |
8fceceb6 | 2847 | case CHIP_NAVI14: |
078655d9 | 2848 | case CHIP_NAVI12: |
e1c14c43 | 2849 | case CHIP_RENOIR: |
81d9bfb8 JFZ |
2850 | #endif |
2851 | #if defined(CONFIG_DRM_AMD_DC_DCN3_0) | |
2852 | case CHIP_SIENNA_CICHLID: | |
a6c5308f | 2853 | case CHIP_NAVY_FLOUNDER: |
42f8ffa1 | 2854 | #endif |
fd187853 | 2855 | return amdgpu_dc != 0; |
4562236b HW |
2856 | #endif |
2857 | default: | |
93b09a9a SS |
2858 | if (amdgpu_dc > 0) |
2859 | DRM_INFO("Display Core has been requested via kernel parameter " | |
2860 | "but isn't supported by ASIC, ignoring\n"); | |
4562236b HW |
2861 | return false; |
2862 | } | |
2863 | } | |
2864 | ||
2865 | /** | |
2866 | * amdgpu_device_has_dc_support - check if dc is supported | |
2867 | * | |
2868 | * @adev: amdgpu_device_pointer | |
2869 | * | |
2870 | * Returns true for supported, false for not supported | |
2871 | */ | |
2872 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2873 | { | |
c997e8e2 | 2874 | if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display) |
2555039d XY |
2875 | return false; |
2876 | ||
4562236b HW |
2877 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2878 | } | |
2879 | ||
d4535e2c AG |
2880 | |
2881 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) | |
2882 | { | |
2883 | struct amdgpu_device *adev = | |
2884 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 2885 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 2886 | |
c6a6e2db AG |
2887 | /* It's a bug to not have a hive within this function */ |
2888 | if (WARN_ON(!hive)) | |
2889 | return; | |
2890 | ||
2891 | /* | |
2892 | * Use task barrier to synchronize all xgmi reset works across the | |
2893 | * hive. task_barrier_enter and task_barrier_exit will block | |
2894 | * until all the threads running the xgmi reset works reach | |
2895 | * those points. task_barrier_full will do both blocks. | |
2896 | */ | |
2897 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
2898 | ||
2899 | task_barrier_enter(&hive->tb); | |
4a580877 | 2900 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
2901 | |
2902 | if (adev->asic_reset_res) | |
2903 | goto fail; | |
2904 | ||
2905 | task_barrier_exit(&hive->tb); | |
4a580877 | 2906 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
2907 | |
2908 | if (adev->asic_reset_res) | |
2909 | goto fail; | |
43c4d576 JC |
2910 | |
2911 | if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count) | |
2912 | adev->mmhub.funcs->reset_ras_error_count(adev); | |
c6a6e2db AG |
2913 | } else { |
2914 | ||
2915 | task_barrier_full(&hive->tb); | |
2916 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
2917 | } | |
ce316fa5 | 2918 | |
c6a6e2db | 2919 | fail: |
d4535e2c | 2920 | if (adev->asic_reset_res) |
fed184e9 | 2921 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 2922 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 2923 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
2924 | } |
2925 | ||
71f98027 AD |
2926 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
2927 | { | |
2928 | char *input = amdgpu_lockup_timeout; | |
2929 | char *timeout_setting = NULL; | |
2930 | int index = 0; | |
2931 | long timeout; | |
2932 | int ret = 0; | |
2933 | ||
2934 | /* | |
2935 | * By default timeout for non compute jobs is 10000. | |
2936 | * And there is no timeout enforced on compute jobs. | |
2937 | * In SR-IOV or passthrough mode, timeout for compute | |
b7b2a316 | 2938 | * jobs are 60000 by default. |
71f98027 AD |
2939 | */ |
2940 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
2941 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
2942 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) | |
b7b2a316 | 2943 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 AD |
2944 | else |
2945 | adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; | |
2946 | ||
f440ff44 | 2947 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 2948 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 2949 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
2950 | ret = kstrtol(timeout_setting, 0, &timeout); |
2951 | if (ret) | |
2952 | return ret; | |
2953 | ||
2954 | if (timeout == 0) { | |
2955 | index++; | |
2956 | continue; | |
2957 | } else if (timeout < 0) { | |
2958 | timeout = MAX_SCHEDULE_TIMEOUT; | |
2959 | } else { | |
2960 | timeout = msecs_to_jiffies(timeout); | |
2961 | } | |
2962 | ||
2963 | switch (index++) { | |
2964 | case 0: | |
2965 | adev->gfx_timeout = timeout; | |
2966 | break; | |
2967 | case 1: | |
2968 | adev->compute_timeout = timeout; | |
2969 | break; | |
2970 | case 2: | |
2971 | adev->sdma_timeout = timeout; | |
2972 | break; | |
2973 | case 3: | |
2974 | adev->video_timeout = timeout; | |
2975 | break; | |
2976 | default: | |
2977 | break; | |
2978 | } | |
2979 | } | |
2980 | /* | |
2981 | * There is only one value specified and | |
2982 | * it should apply to all non-compute jobs. | |
2983 | */ | |
bcccee89 | 2984 | if (index == 1) { |
71f98027 | 2985 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
2986 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
2987 | adev->compute_timeout = adev->gfx_timeout; | |
2988 | } | |
71f98027 AD |
2989 | } |
2990 | ||
2991 | return ret; | |
2992 | } | |
d4535e2c | 2993 | |
77f3a5cd ND |
2994 | static const struct attribute *amdgpu_dev_attributes[] = { |
2995 | &dev_attr_product_name.attr, | |
2996 | &dev_attr_product_number.attr, | |
2997 | &dev_attr_serial_number.attr, | |
2998 | &dev_attr_pcie_replay_count.attr, | |
2999 | NULL | |
3000 | }; | |
3001 | ||
c9a6b82f | 3002 | |
d38ceaf9 AD |
3003 | /** |
3004 | * amdgpu_device_init - initialize the driver | |
3005 | * | |
3006 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3007 | * @flags: driver flags |
3008 | * | |
3009 | * Initializes the driver info and hw (all asics). | |
3010 | * Returns 0 for success or an error on failure. | |
3011 | * Called at driver startup. | |
3012 | */ | |
3013 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3014 | uint32_t flags) |
3015 | { | |
8aba21b7 LT |
3016 | struct drm_device *ddev = adev_to_drm(adev); |
3017 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3018 | int r, i; |
3840c5bc | 3019 | bool boco = false; |
95844d20 | 3020 | u32 max_MBps; |
d38ceaf9 AD |
3021 | |
3022 | adev->shutdown = false; | |
d38ceaf9 | 3023 | adev->flags = flags; |
4e66d7d2 YZ |
3024 | |
3025 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3026 | adev->asic_type = amdgpu_force_asic_type; | |
3027 | else | |
3028 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3029 | ||
d38ceaf9 | 3030 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3031 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3032 | adev->usec_timeout *= 10; |
770d13b1 | 3033 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3034 | adev->accel_working = false; |
3035 | adev->num_rings = 0; | |
3036 | adev->mman.buffer_funcs = NULL; | |
3037 | adev->mman.buffer_funcs_ring = NULL; | |
3038 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3039 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3040 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 3041 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3042 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3043 | |
3044 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3045 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3046 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3047 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3048 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3049 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3050 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3051 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3052 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3053 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3054 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3055 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3056 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3057 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3058 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3059 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3060 | ||
3e39ab90 AD |
3061 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3062 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3063 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3064 | |
3065 | /* mutex initialization are all done here so we | |
3066 | * can recall function without having locking issues */ | |
d38ceaf9 | 3067 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 3068 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3069 | mutex_init(&adev->pm.mutex); |
3070 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3071 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3072 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3073 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3074 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3075 | mutex_init(&adev->mn_lock); |
e23b74aa | 3076 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3077 | hash_init(adev->mn_hash); |
53b3f8f4 | 3078 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 3079 | init_rwsem(&adev->reset_sem); |
32eaeae0 | 3080 | mutex_init(&adev->psp.mutex); |
bd052211 | 3081 | mutex_init(&adev->notifier_lock); |
d38ceaf9 | 3082 | |
912dfc84 EQ |
3083 | r = amdgpu_device_check_arguments(adev); |
3084 | if (r) | |
3085 | return r; | |
d38ceaf9 | 3086 | |
d38ceaf9 AD |
3087 | spin_lock_init(&adev->mmio_idx_lock); |
3088 | spin_lock_init(&adev->smc_idx_lock); | |
3089 | spin_lock_init(&adev->pcie_idx_lock); | |
3090 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3091 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3092 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3093 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3094 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3095 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3096 | |
0c4e7fa5 CZ |
3097 | INIT_LIST_HEAD(&adev->shadow_list); |
3098 | mutex_init(&adev->shadow_list_lock); | |
3099 | ||
beff74bc AD |
3100 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3101 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3102 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3103 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3104 | |
d4535e2c AG |
3105 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3106 | ||
d23ee13f | 3107 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3108 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3109 | |
b265bdbd EQ |
3110 | atomic_set(&adev->throttling_logging_enabled, 1); |
3111 | /* | |
3112 | * If throttling continues, logging will be performed every minute | |
3113 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3114 | * throttling interrupt comes every second. Thus, the total logging | |
3115 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3116 | * for throttling interrupt) = 60 seconds. | |
3117 | */ | |
3118 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3119 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3120 | ||
0fa49558 AX |
3121 | /* Registers mapping */ |
3122 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3123 | if (adev->asic_type >= CHIP_BONAIRE) { |
3124 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3125 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3126 | } else { | |
3127 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3128 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3129 | } | |
d38ceaf9 | 3130 | |
d38ceaf9 AD |
3131 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3132 | if (adev->rmmio == NULL) { | |
3133 | return -ENOMEM; | |
3134 | } | |
3135 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3136 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3137 | ||
d38ceaf9 AD |
3138 | /* io port mapping */ |
3139 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
3140 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
3141 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
3142 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
3143 | break; | |
3144 | } | |
3145 | } | |
3146 | if (adev->rio_mem == NULL) | |
b64a18c5 | 3147 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 3148 | |
b2109d8e JX |
3149 | /* enable PCIE atomic ops */ |
3150 | r = pci_enable_atomic_ops_to_root(adev->pdev, | |
3151 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3152 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3153 | if (r) { | |
3154 | adev->have_atomics_support = false; | |
3155 | DRM_INFO("PCIE atomic ops is not supported\n"); | |
3156 | } else { | |
3157 | adev->have_atomics_support = true; | |
3158 | } | |
3159 | ||
5494d864 AD |
3160 | amdgpu_device_get_pcie_info(adev); |
3161 | ||
b239c017 JX |
3162 | if (amdgpu_mcbp) |
3163 | DRM_INFO("MCBP is enabled\n"); | |
3164 | ||
5f84cc63 JX |
3165 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
3166 | adev->enable_mes = true; | |
3167 | ||
3aa0115d ML |
3168 | /* detect hw virtualization here */ |
3169 | amdgpu_detect_virtualization(adev); | |
3170 | ||
dffa11b4 ML |
3171 | r = amdgpu_device_get_job_timeout_settings(adev); |
3172 | if (r) { | |
3173 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
3174 | return r; | |
a190d1c7 XY |
3175 | } |
3176 | ||
d38ceaf9 | 3177 | /* early init functions */ |
06ec9070 | 3178 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
3179 | if (r) |
3180 | return r; | |
3181 | ||
6585661d OZ |
3182 | /* doorbell bar mapping and doorbell index init*/ |
3183 | amdgpu_device_doorbell_init(adev); | |
3184 | ||
d38ceaf9 AD |
3185 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3186 | /* this will fail for cards that aren't VGA class devices, just | |
3187 | * ignore it */ | |
06ec9070 | 3188 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 3189 | |
31af062a | 3190 | if (amdgpu_device_supports_boco(ddev)) |
3840c5bc AD |
3191 | boco = true; |
3192 | if (amdgpu_has_atpx() && | |
3193 | (amdgpu_is_atpx_hybrid() || | |
3194 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
3195 | !pci_is_thunderbolt_attached(adev->pdev)) | |
84c8b22e | 3196 | vga_switcheroo_register_client(adev->pdev, |
3840c5bc AD |
3197 | &amdgpu_switcheroo_ops, boco); |
3198 | if (boco) | |
d38ceaf9 AD |
3199 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); |
3200 | ||
9475a943 SL |
3201 | if (amdgpu_emu_mode == 1) { |
3202 | /* post the asic on emulation mode */ | |
3203 | emu_soc_asic_init(adev); | |
bfca0289 | 3204 | goto fence_driver_init; |
9475a943 | 3205 | } |
bfca0289 | 3206 | |
4e99a44e ML |
3207 | /* detect if we are with an SRIOV vbios */ |
3208 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3209 | |
95e8e59e AD |
3210 | /* check if we need to reset the asic |
3211 | * E.g., driver was not cleanly unloaded previously, etc. | |
3212 | */ | |
f14899fd | 3213 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
95e8e59e AD |
3214 | r = amdgpu_asic_reset(adev); |
3215 | if (r) { | |
3216 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3217 | goto failed; | |
3218 | } | |
3219 | } | |
3220 | ||
c9a6b82f AG |
3221 | pci_enable_pcie_error_reporting(adev->ddev.pdev); |
3222 | ||
d38ceaf9 | 3223 | /* Post card if necessary */ |
39c640c0 | 3224 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3225 | if (!adev->bios) { |
bec86378 | 3226 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3227 | r = -EINVAL; |
3228 | goto failed; | |
d38ceaf9 | 3229 | } |
bec86378 | 3230 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3231 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3232 | if (r) { |
3233 | dev_err(adev->dev, "gpu post error!\n"); | |
3234 | goto failed; | |
3235 | } | |
d38ceaf9 AD |
3236 | } |
3237 | ||
88b64e95 AD |
3238 | if (adev->is_atom_fw) { |
3239 | /* Initialize clocks */ | |
3240 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3241 | if (r) { | |
3242 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3243 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3244 | goto failed; |
3245 | } | |
3246 | } else { | |
a5bde2f9 AD |
3247 | /* Initialize clocks */ |
3248 | r = amdgpu_atombios_get_clock_info(adev); | |
3249 | if (r) { | |
3250 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3251 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3252 | goto failed; |
a5bde2f9 AD |
3253 | } |
3254 | /* init i2c buses */ | |
4562236b HW |
3255 | if (!amdgpu_device_has_dc_support(adev)) |
3256 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3257 | } |
d38ceaf9 | 3258 | |
bfca0289 | 3259 | fence_driver_init: |
d38ceaf9 AD |
3260 | /* Fence driver */ |
3261 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
3262 | if (r) { |
3263 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 3264 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3265 | goto failed; |
2c1a2784 | 3266 | } |
d38ceaf9 AD |
3267 | |
3268 | /* init the mode config */ | |
4a580877 | 3269 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3270 | |
06ec9070 | 3271 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3272 | if (r) { |
8840a387 | 3273 | /* failed in exclusive mode due to timeout */ |
3274 | if (amdgpu_sriov_vf(adev) && | |
3275 | !amdgpu_sriov_runtime(adev) && | |
3276 | amdgpu_virt_mmio_blocked(adev) && | |
3277 | !amdgpu_virt_wait_reset(adev)) { | |
3278 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3279 | /* Don't send request since VF is inactive. */ |
3280 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3281 | adev->virt.ops = NULL; | |
8840a387 | 3282 | r = -EAGAIN; |
3283 | goto failed; | |
3284 | } | |
06ec9070 | 3285 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3286 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
83ba126a | 3287 | goto failed; |
d38ceaf9 AD |
3288 | } |
3289 | ||
d69b8971 YZ |
3290 | dev_info(adev->dev, |
3291 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3292 | adev->gfx.config.max_shader_engines, |
3293 | adev->gfx.config.max_sh_per_se, | |
3294 | adev->gfx.config.max_cu_per_sh, | |
3295 | adev->gfx.cu_info.number); | |
3296 | ||
d38ceaf9 AD |
3297 | adev->accel_working = true; |
3298 | ||
e59c0205 AX |
3299 | amdgpu_vm_check_compute_bug(adev); |
3300 | ||
95844d20 MO |
3301 | /* Initialize the buffer migration limit. */ |
3302 | if (amdgpu_moverate >= 0) | |
3303 | max_MBps = amdgpu_moverate; | |
3304 | else | |
3305 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3306 | /* Get a log2 for easy divisions. */ | |
3307 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3308 | ||
9bc92b9c ML |
3309 | amdgpu_fbdev_init(adev); |
3310 | ||
d2f52ac8 | 3311 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3312 | if (r) { |
3313 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3314 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3315 | } else |
3316 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3317 | |
5bb23532 | 3318 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3319 | if (r) { |
3320 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3321 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3322 | } else |
3323 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3324 | |
d38ceaf9 AD |
3325 | if ((amdgpu_testing & 1)) { |
3326 | if (adev->accel_working) | |
3327 | amdgpu_test_moves(adev); | |
3328 | else | |
3329 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
3330 | } | |
d38ceaf9 AD |
3331 | if (amdgpu_benchmarking) { |
3332 | if (adev->accel_working) | |
3333 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
3334 | else | |
3335 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
3336 | } | |
3337 | ||
b0adca4d EQ |
3338 | /* |
3339 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3340 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3341 | * gpu instance is counted less. | |
3342 | */ | |
3343 | amdgpu_register_gpu_instance(adev); | |
3344 | ||
d38ceaf9 AD |
3345 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3346 | * explicit gating rather than handling it automatically. | |
3347 | */ | |
06ec9070 | 3348 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 3349 | if (r) { |
06ec9070 | 3350 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 3351 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 3352 | goto failed; |
2c1a2784 | 3353 | } |
d38ceaf9 | 3354 | |
108c6a63 | 3355 | /* must succeed. */ |
511fdbc3 | 3356 | amdgpu_ras_resume(adev); |
108c6a63 | 3357 | |
beff74bc AD |
3358 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3359 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3360 | ||
2c738637 ML |
3361 | if (amdgpu_sriov_vf(adev)) |
3362 | flush_delayed_work(&adev->delayed_init_work); | |
3363 | ||
77f3a5cd | 3364 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
bd607166 | 3365 | if (r) { |
77f3a5cd | 3366 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 KR |
3367 | return r; |
3368 | } | |
3369 | ||
d155bef0 AB |
3370 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3371 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3372 | if (r) |
3373 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3374 | ||
d38ceaf9 | 3375 | return 0; |
83ba126a AD |
3376 | |
3377 | failed: | |
89041940 | 3378 | amdgpu_vf_error_trans_all(adev); |
3840c5bc | 3379 | if (boco) |
83ba126a | 3380 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
8840a387 | 3381 | |
83ba126a | 3382 | return r; |
d38ceaf9 AD |
3383 | } |
3384 | ||
d38ceaf9 AD |
3385 | /** |
3386 | * amdgpu_device_fini - tear down the driver | |
3387 | * | |
3388 | * @adev: amdgpu_device pointer | |
3389 | * | |
3390 | * Tear down the driver info (all asics). | |
3391 | * Called at driver shutdown. | |
3392 | */ | |
3393 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
3394 | { | |
aac89168 | 3395 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3396 | flush_delayed_work(&adev->delayed_init_work); |
d0d13fe8 | 3397 | adev->shutdown = true; |
9f875167 | 3398 | |
752c683d ML |
3399 | /* make sure IB test finished before entering exclusive mode |
3400 | * to avoid preemption on IB test | |
3401 | * */ | |
3402 | if (amdgpu_sriov_vf(adev)) | |
3403 | amdgpu_virt_request_full_gpu(adev, false); | |
3404 | ||
e5b03032 ML |
3405 | /* disable all interrupts */ |
3406 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
3407 | if (adev->mode_info.mode_config_initialized){ |
3408 | if (!amdgpu_device_has_dc_support(adev)) | |
4a580877 | 3409 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3410 | else |
4a580877 | 3411 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3412 | } |
d38ceaf9 | 3413 | amdgpu_fence_driver_fini(adev); |
7c868b59 YT |
3414 | if (adev->pm_sysfs_en) |
3415 | amdgpu_pm_sysfs_fini(adev); | |
d38ceaf9 | 3416 | amdgpu_fbdev_fini(adev); |
e230ac11 | 3417 | amdgpu_device_ip_fini(adev); |
75e1658e ND |
3418 | release_firmware(adev->firmware.gpu_info_fw); |
3419 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 AD |
3420 | adev->accel_working = false; |
3421 | /* free i2c buses */ | |
4562236b HW |
3422 | if (!amdgpu_device_has_dc_support(adev)) |
3423 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3424 | |
3425 | if (amdgpu_emu_mode != 1) | |
3426 | amdgpu_atombios_fini(adev); | |
3427 | ||
d38ceaf9 AD |
3428 | kfree(adev->bios); |
3429 | adev->bios = NULL; | |
3840c5bc AD |
3430 | if (amdgpu_has_atpx() && |
3431 | (amdgpu_is_atpx_hybrid() || | |
3432 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
3433 | !pci_is_thunderbolt_attached(adev->pdev)) | |
84c8b22e | 3434 | vga_switcheroo_unregister_client(adev->pdev); |
4a580877 | 3435 | if (amdgpu_device_supports_boco(adev_to_drm(adev))) |
83ba126a | 3436 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
d38ceaf9 AD |
3437 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
3438 | if (adev->rio_mem) | |
3439 | pci_iounmap(adev->pdev, adev->rio_mem); | |
3440 | adev->rio_mem = NULL; | |
3441 | iounmap(adev->rmmio); | |
3442 | adev->rmmio = NULL; | |
06ec9070 | 3443 | amdgpu_device_doorbell_fini(adev); |
e9bc1bf7 | 3444 | |
7c868b59 YT |
3445 | if (adev->ucode_sysfs_en) |
3446 | amdgpu_ucode_sysfs_fini(adev); | |
77f3a5cd ND |
3447 | |
3448 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
d155bef0 AB |
3449 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3450 | amdgpu_pmu_fini(adev); | |
72de33f8 | 3451 | if (adev->mman.discovery_bin) |
a190d1c7 | 3452 | amdgpu_discovery_fini(adev); |
d38ceaf9 AD |
3453 | } |
3454 | ||
3455 | ||
3456 | /* | |
3457 | * Suspend & resume. | |
3458 | */ | |
3459 | /** | |
810ddc3a | 3460 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3461 | * |
87e3f136 | 3462 | * @dev: drm dev pointer |
87e3f136 | 3463 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
3464 | * |
3465 | * Puts the hw in the suspend state (all asics). | |
3466 | * Returns 0 for success or an error on failure. | |
3467 | * Called at driver suspend. | |
3468 | */ | |
de185019 | 3469 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 AD |
3470 | { |
3471 | struct amdgpu_device *adev; | |
3472 | struct drm_crtc *crtc; | |
3473 | struct drm_connector *connector; | |
f8d2d39e | 3474 | struct drm_connector_list_iter iter; |
5ceb54c6 | 3475 | int r; |
d38ceaf9 | 3476 | |
1348969a | 3477 | adev = drm_to_adev(dev); |
d38ceaf9 AD |
3478 | |
3479 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3480 | return 0; | |
3481 | ||
44779b43 | 3482 | adev->in_suspend = true; |
d38ceaf9 AD |
3483 | drm_kms_helper_poll_disable(dev); |
3484 | ||
5f818173 S |
3485 | if (fbcon) |
3486 | amdgpu_fbdev_set_suspend(adev, 1); | |
3487 | ||
beff74bc | 3488 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3489 | |
4562236b HW |
3490 | if (!amdgpu_device_has_dc_support(adev)) { |
3491 | /* turn off display hw */ | |
3492 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3493 | drm_connector_list_iter_begin(dev, &iter); |
3494 | drm_for_each_connector_iter(connector, &iter) | |
3495 | drm_helper_connector_dpms(connector, | |
3496 | DRM_MODE_DPMS_OFF); | |
3497 | drm_connector_list_iter_end(&iter); | |
4562236b | 3498 | drm_modeset_unlock_all(dev); |
fe1053b7 AD |
3499 | /* unpin the front buffers and cursors */ |
3500 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3501 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3502 | struct drm_framebuffer *fb = crtc->primary->fb; | |
3503 | struct amdgpu_bo *robj; | |
3504 | ||
91334223 | 3505 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3506 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3507 | r = amdgpu_bo_reserve(aobj, true); | |
3508 | if (r == 0) { | |
3509 | amdgpu_bo_unpin(aobj); | |
3510 | amdgpu_bo_unreserve(aobj); | |
3511 | } | |
756e6880 | 3512 | } |
756e6880 | 3513 | |
fe1053b7 AD |
3514 | if (fb == NULL || fb->obj[0] == NULL) { |
3515 | continue; | |
3516 | } | |
3517 | robj = gem_to_amdgpu_bo(fb->obj[0]); | |
3518 | /* don't unpin kernel fb objects */ | |
3519 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
3520 | r = amdgpu_bo_reserve(robj, true); | |
3521 | if (r == 0) { | |
3522 | amdgpu_bo_unpin(robj); | |
3523 | amdgpu_bo_unreserve(robj); | |
3524 | } | |
d38ceaf9 AD |
3525 | } |
3526 | } | |
3527 | } | |
fe1053b7 | 3528 | |
5e6932fe | 3529 | amdgpu_ras_suspend(adev); |
3530 | ||
fe1053b7 AD |
3531 | r = amdgpu_device_ip_suspend_phase1(adev); |
3532 | ||
94fa5660 EQ |
3533 | amdgpu_amdkfd_suspend(adev, !fbcon); |
3534 | ||
d38ceaf9 AD |
3535 | /* evict vram memory */ |
3536 | amdgpu_bo_evict_vram(adev); | |
3537 | ||
5ceb54c6 | 3538 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 3539 | |
fe1053b7 | 3540 | r = amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 3541 | |
a0a71e49 AD |
3542 | /* evict remaining vram memory |
3543 | * This second call to evict vram is to evict the gart page table | |
3544 | * using the CPU. | |
3545 | */ | |
d38ceaf9 AD |
3546 | amdgpu_bo_evict_vram(adev); |
3547 | ||
d38ceaf9 AD |
3548 | return 0; |
3549 | } | |
3550 | ||
3551 | /** | |
810ddc3a | 3552 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 3553 | * |
87e3f136 | 3554 | * @dev: drm dev pointer |
87e3f136 | 3555 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
3556 | * |
3557 | * Bring the hw back to operating state (all asics). | |
3558 | * Returns 0 for success or an error on failure. | |
3559 | * Called at driver resume. | |
3560 | */ | |
de185019 | 3561 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 AD |
3562 | { |
3563 | struct drm_connector *connector; | |
f8d2d39e | 3564 | struct drm_connector_list_iter iter; |
1348969a | 3565 | struct amdgpu_device *adev = drm_to_adev(dev); |
756e6880 | 3566 | struct drm_crtc *crtc; |
03161a6e | 3567 | int r = 0; |
d38ceaf9 AD |
3568 | |
3569 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3570 | return 0; | |
3571 | ||
d38ceaf9 | 3572 | /* post card */ |
39c640c0 | 3573 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 3574 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 3575 | if (r) |
aac89168 | 3576 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 3577 | } |
d38ceaf9 | 3578 | |
06ec9070 | 3579 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 3580 | if (r) { |
aac89168 | 3581 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 3582 | return r; |
e6707218 | 3583 | } |
5ceb54c6 AD |
3584 | amdgpu_fence_driver_resume(adev); |
3585 | ||
d38ceaf9 | 3586 | |
06ec9070 | 3587 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 3588 | if (r) |
4d3b9ae5 | 3589 | return r; |
d38ceaf9 | 3590 | |
beff74bc AD |
3591 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3592 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3593 | ||
fe1053b7 AD |
3594 | if (!amdgpu_device_has_dc_support(adev)) { |
3595 | /* pin cursors */ | |
3596 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3597 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3598 | ||
91334223 | 3599 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3600 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3601 | r = amdgpu_bo_reserve(aobj, true); | |
3602 | if (r == 0) { | |
3603 | r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); | |
3604 | if (r != 0) | |
aac89168 | 3605 | dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); |
fe1053b7 AD |
3606 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); |
3607 | amdgpu_bo_unreserve(aobj); | |
3608 | } | |
756e6880 AD |
3609 | } |
3610 | } | |
3611 | } | |
9593f4d6 | 3612 | r = amdgpu_amdkfd_resume(adev, !fbcon); |
ba997709 YZ |
3613 | if (r) |
3614 | return r; | |
756e6880 | 3615 | |
96a5d8d4 | 3616 | /* Make sure IB tests flushed */ |
beff74bc | 3617 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 3618 | |
d38ceaf9 AD |
3619 | /* blat the mode back in */ |
3620 | if (fbcon) { | |
4562236b HW |
3621 | if (!amdgpu_device_has_dc_support(adev)) { |
3622 | /* pre DCE11 */ | |
3623 | drm_helper_resume_force_mode(dev); | |
3624 | ||
3625 | /* turn on display hw */ | |
3626 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3627 | |
3628 | drm_connector_list_iter_begin(dev, &iter); | |
3629 | drm_for_each_connector_iter(connector, &iter) | |
3630 | drm_helper_connector_dpms(connector, | |
3631 | DRM_MODE_DPMS_ON); | |
3632 | drm_connector_list_iter_end(&iter); | |
3633 | ||
4562236b | 3634 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 3635 | } |
4d3b9ae5 | 3636 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
3637 | } |
3638 | ||
3639 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 3640 | |
5e6932fe | 3641 | amdgpu_ras_resume(adev); |
3642 | ||
23a1a9e5 L |
3643 | /* |
3644 | * Most of the connector probing functions try to acquire runtime pm | |
3645 | * refs to ensure that the GPU is powered on when connector polling is | |
3646 | * performed. Since we're calling this from a runtime PM callback, | |
3647 | * trying to acquire rpm refs will cause us to deadlock. | |
3648 | * | |
3649 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
3650 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
3651 | */ | |
3652 | #ifdef CONFIG_PM | |
3653 | dev->dev->power.disable_depth++; | |
3654 | #endif | |
4562236b HW |
3655 | if (!amdgpu_device_has_dc_support(adev)) |
3656 | drm_helper_hpd_irq_event(dev); | |
3657 | else | |
3658 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
3659 | #ifdef CONFIG_PM |
3660 | dev->dev->power.disable_depth--; | |
3661 | #endif | |
44779b43 RZ |
3662 | adev->in_suspend = false; |
3663 | ||
4d3b9ae5 | 3664 | return 0; |
d38ceaf9 AD |
3665 | } |
3666 | ||
e3ecdffa AD |
3667 | /** |
3668 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
3669 | * | |
3670 | * @adev: amdgpu_device pointer | |
3671 | * | |
3672 | * The list of all the hardware IPs that make up the asic is walked and | |
3673 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
3674 | * if the asic is still hung or not. | |
3675 | * Returns true if any of the IPs are still in a hung state, false if not. | |
3676 | */ | |
06ec9070 | 3677 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
3678 | { |
3679 | int i; | |
3680 | bool asic_hang = false; | |
3681 | ||
f993d628 ML |
3682 | if (amdgpu_sriov_vf(adev)) |
3683 | return true; | |
3684 | ||
8bc04c29 AD |
3685 | if (amdgpu_asic_need_full_reset(adev)) |
3686 | return true; | |
3687 | ||
63fbf42f | 3688 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3689 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 3690 | continue; |
a1255107 AD |
3691 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
3692 | adev->ip_blocks[i].status.hang = | |
3693 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
3694 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 3695 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
3696 | asic_hang = true; |
3697 | } | |
3698 | } | |
3699 | return asic_hang; | |
3700 | } | |
3701 | ||
e3ecdffa AD |
3702 | /** |
3703 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
3704 | * | |
3705 | * @adev: amdgpu_device pointer | |
3706 | * | |
3707 | * The list of all the hardware IPs that make up the asic is walked and the | |
3708 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
3709 | * handles any IP specific hardware or software state changes that are | |
3710 | * necessary for a soft reset to succeed. | |
3711 | * Returns 0 on success, negative error code on failure. | |
3712 | */ | |
06ec9070 | 3713 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
3714 | { |
3715 | int i, r = 0; | |
3716 | ||
3717 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3718 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 3719 | continue; |
a1255107 AD |
3720 | if (adev->ip_blocks[i].status.hang && |
3721 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
3722 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
3723 | if (r) |
3724 | return r; | |
3725 | } | |
3726 | } | |
3727 | ||
3728 | return 0; | |
3729 | } | |
3730 | ||
e3ecdffa AD |
3731 | /** |
3732 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
3733 | * | |
3734 | * @adev: amdgpu_device pointer | |
3735 | * | |
3736 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
3737 | * reset is necessary to recover. | |
3738 | * Returns true if a full asic reset is required, false if not. | |
3739 | */ | |
06ec9070 | 3740 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 3741 | { |
da146d3b AD |
3742 | int i; |
3743 | ||
8bc04c29 AD |
3744 | if (amdgpu_asic_need_full_reset(adev)) |
3745 | return true; | |
3746 | ||
da146d3b | 3747 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3748 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 3749 | continue; |
a1255107 AD |
3750 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
3751 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
3752 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
3753 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
3754 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 3755 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 3756 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
3757 | return true; |
3758 | } | |
3759 | } | |
35d782fe CZ |
3760 | } |
3761 | return false; | |
3762 | } | |
3763 | ||
e3ecdffa AD |
3764 | /** |
3765 | * amdgpu_device_ip_soft_reset - do a soft reset | |
3766 | * | |
3767 | * @adev: amdgpu_device pointer | |
3768 | * | |
3769 | * The list of all the hardware IPs that make up the asic is walked and the | |
3770 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
3771 | * IP specific hardware or software state changes that are necessary to soft | |
3772 | * reset the IP. | |
3773 | * Returns 0 on success, negative error code on failure. | |
3774 | */ | |
06ec9070 | 3775 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3776 | { |
3777 | int i, r = 0; | |
3778 | ||
3779 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3780 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3781 | continue; |
a1255107 AD |
3782 | if (adev->ip_blocks[i].status.hang && |
3783 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
3784 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
3785 | if (r) |
3786 | return r; | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | return 0; | |
3791 | } | |
3792 | ||
e3ecdffa AD |
3793 | /** |
3794 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
3795 | * | |
3796 | * @adev: amdgpu_device pointer | |
3797 | * | |
3798 | * The list of all the hardware IPs that make up the asic is walked and the | |
3799 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
3800 | * handles any IP specific hardware or software state changes that are | |
3801 | * necessary after the IP has been soft reset. | |
3802 | * Returns 0 on success, negative error code on failure. | |
3803 | */ | |
06ec9070 | 3804 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3805 | { |
3806 | int i, r = 0; | |
3807 | ||
3808 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3809 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3810 | continue; |
a1255107 AD |
3811 | if (adev->ip_blocks[i].status.hang && |
3812 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
3813 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
3814 | if (r) |
3815 | return r; | |
3816 | } | |
3817 | ||
3818 | return 0; | |
3819 | } | |
3820 | ||
e3ecdffa | 3821 | /** |
c33adbc7 | 3822 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
3823 | * |
3824 | * @adev: amdgpu_device pointer | |
3825 | * | |
3826 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
3827 | * restore things like GPUVM page tables after a GPU reset where | |
3828 | * the contents of VRAM might be lost. | |
403009bf CK |
3829 | * |
3830 | * Returns: | |
3831 | * 0 on success, negative error code on failure. | |
e3ecdffa | 3832 | */ |
c33adbc7 | 3833 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 3834 | { |
c41d1cf6 | 3835 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf CK |
3836 | struct amdgpu_bo *shadow; |
3837 | long r = 1, tmo; | |
c41d1cf6 ML |
3838 | |
3839 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 3840 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
3841 | else |
3842 | tmo = msecs_to_jiffies(100); | |
3843 | ||
aac89168 | 3844 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 3845 | mutex_lock(&adev->shadow_list_lock); |
403009bf CK |
3846 | list_for_each_entry(shadow, &adev->shadow_list, shadow_list) { |
3847 | ||
3848 | /* No need to recover an evicted BO */ | |
3849 | if (shadow->tbo.mem.mem_type != TTM_PL_TT || | |
b575f10d | 3850 | shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET || |
403009bf CK |
3851 | shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM) |
3852 | continue; | |
3853 | ||
3854 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
3855 | if (r) | |
3856 | break; | |
3857 | ||
c41d1cf6 | 3858 | if (fence) { |
1712fb1a | 3859 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
3860 | dma_fence_put(fence); |
3861 | fence = next; | |
1712fb1a | 3862 | if (tmo == 0) { |
3863 | r = -ETIMEDOUT; | |
c41d1cf6 | 3864 | break; |
1712fb1a | 3865 | } else if (tmo < 0) { |
3866 | r = tmo; | |
3867 | break; | |
3868 | } | |
403009bf CK |
3869 | } else { |
3870 | fence = next; | |
c41d1cf6 | 3871 | } |
c41d1cf6 ML |
3872 | } |
3873 | mutex_unlock(&adev->shadow_list_lock); | |
3874 | ||
403009bf CK |
3875 | if (fence) |
3876 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
3877 | dma_fence_put(fence); |
3878 | ||
1712fb1a | 3879 | if (r < 0 || tmo <= 0) { |
aac89168 | 3880 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
3881 | return -EIO; |
3882 | } | |
c41d1cf6 | 3883 | |
aac89168 | 3884 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 3885 | return 0; |
c41d1cf6 ML |
3886 | } |
3887 | ||
a90ad3c2 | 3888 | |
e3ecdffa | 3889 | /** |
06ec9070 | 3890 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3891 | * |
3892 | * @adev: amdgpu device pointer | |
87e3f136 | 3893 | * @from_hypervisor: request from hypervisor |
5740682e ML |
3894 | * |
3895 | * do VF FLR and reinitialize Asic | |
3f48c681 | 3896 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
3897 | */ |
3898 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3899 | bool from_hypervisor) | |
5740682e ML |
3900 | { |
3901 | int r; | |
3902 | ||
3903 | if (from_hypervisor) | |
3904 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3905 | else | |
3906 | r = amdgpu_virt_reset_gpu(adev); | |
3907 | if (r) | |
3908 | return r; | |
a90ad3c2 | 3909 | |
b639c22c JZ |
3910 | amdgpu_amdkfd_pre_reset(adev); |
3911 | ||
a90ad3c2 | 3912 | /* Resume IP prior to SMC */ |
06ec9070 | 3913 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3914 | if (r) |
3915 | goto error; | |
a90ad3c2 | 3916 | |
c9ffa427 | 3917 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 3918 | /* we need recover gart prior to run SMC/CP/SDMA resume */ |
6c28aed6 | 3919 | amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); |
a90ad3c2 | 3920 | |
7a3e0bb2 RZ |
3921 | r = amdgpu_device_fw_loading(adev); |
3922 | if (r) | |
3923 | return r; | |
3924 | ||
a90ad3c2 | 3925 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 3926 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
3927 | if (r) |
3928 | goto error; | |
a90ad3c2 ML |
3929 | |
3930 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3931 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 3932 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 3933 | |
abc34253 ED |
3934 | error: |
3935 | amdgpu_virt_release_full_gpu(adev, true); | |
c41d1cf6 | 3936 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 3937 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 3938 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 ML |
3939 | } |
3940 | ||
3941 | return r; | |
3942 | } | |
3943 | ||
9a1cddd6 | 3944 | /** |
3945 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
3946 | * | |
3947 | * @adev: amdgpu device pointer | |
3948 | * | |
3949 | * check if there is any job in mirror list | |
3950 | */ | |
3951 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
3952 | { | |
3953 | int i; | |
3954 | struct drm_sched_job *job; | |
3955 | ||
3956 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
3957 | struct amdgpu_ring *ring = adev->rings[i]; | |
3958 | ||
3959 | if (!ring || !ring->sched.thread) | |
3960 | continue; | |
3961 | ||
3962 | spin_lock(&ring->sched.job_list_lock); | |
3963 | job = list_first_entry_or_null(&ring->sched.ring_mirror_list, | |
3964 | struct drm_sched_job, node); | |
3965 | spin_unlock(&ring->sched.job_list_lock); | |
3966 | if (job) | |
3967 | return true; | |
3968 | } | |
3969 | return false; | |
3970 | } | |
3971 | ||
12938fad CK |
3972 | /** |
3973 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
3974 | * | |
3975 | * @adev: amdgpu device pointer | |
3976 | * | |
3977 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
3978 | * a hung GPU. | |
3979 | */ | |
3980 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
3981 | { | |
3982 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 3983 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
3984 | return false; |
3985 | } | |
3986 | ||
3ba7b418 AG |
3987 | if (amdgpu_gpu_recovery == 0) |
3988 | goto disabled; | |
3989 | ||
3990 | if (amdgpu_sriov_vf(adev)) | |
3991 | return true; | |
3992 | ||
3993 | if (amdgpu_gpu_recovery == -1) { | |
3994 | switch (adev->asic_type) { | |
fc42d47c AG |
3995 | case CHIP_BONAIRE: |
3996 | case CHIP_HAWAII: | |
3ba7b418 AG |
3997 | case CHIP_TOPAZ: |
3998 | case CHIP_TONGA: | |
3999 | case CHIP_FIJI: | |
4000 | case CHIP_POLARIS10: | |
4001 | case CHIP_POLARIS11: | |
4002 | case CHIP_POLARIS12: | |
4003 | case CHIP_VEGAM: | |
4004 | case CHIP_VEGA20: | |
4005 | case CHIP_VEGA10: | |
4006 | case CHIP_VEGA12: | |
c43b849f | 4007 | case CHIP_RAVEN: |
e9d4cf91 | 4008 | case CHIP_ARCTURUS: |
2cb44fb0 | 4009 | case CHIP_RENOIR: |
658c6639 AD |
4010 | case CHIP_NAVI10: |
4011 | case CHIP_NAVI14: | |
4012 | case CHIP_NAVI12: | |
131a3c74 | 4013 | case CHIP_SIENNA_CICHLID: |
3ba7b418 AG |
4014 | break; |
4015 | default: | |
4016 | goto disabled; | |
4017 | } | |
12938fad CK |
4018 | } |
4019 | ||
4020 | return true; | |
3ba7b418 AG |
4021 | |
4022 | disabled: | |
aac89168 | 4023 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4024 | return false; |
12938fad CK |
4025 | } |
4026 | ||
5c6dd71e | 4027 | |
26bc5340 AG |
4028 | static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
4029 | struct amdgpu_job *job, | |
4030 | bool *need_full_reset_arg) | |
4031 | { | |
4032 | int i, r = 0; | |
4033 | bool need_full_reset = *need_full_reset_arg; | |
71182665 | 4034 | |
728e7e0c JZ |
4035 | amdgpu_debugfs_wait_dump(adev); |
4036 | ||
71182665 | 4037 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4038 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4039 | struct amdgpu_ring *ring = adev->rings[i]; | |
4040 | ||
51687759 | 4041 | if (!ring || !ring->sched.thread) |
0875dc9e | 4042 | continue; |
5740682e | 4043 | |
2f9d4084 ML |
4044 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4045 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4046 | } |
d38ceaf9 | 4047 | |
222b5f04 AG |
4048 | if(job) |
4049 | drm_sched_increase_karma(&job->base); | |
4050 | ||
1d721ed6 | 4051 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4052 | if (!amdgpu_sriov_vf(adev)) { |
4053 | ||
4054 | if (!need_full_reset) | |
4055 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4056 | ||
4057 | if (!need_full_reset) { | |
4058 | amdgpu_device_ip_pre_soft_reset(adev); | |
4059 | r = amdgpu_device_ip_soft_reset(adev); | |
4060 | amdgpu_device_ip_post_soft_reset(adev); | |
4061 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4062 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4063 | need_full_reset = true; |
4064 | } | |
4065 | } | |
4066 | ||
4067 | if (need_full_reset) | |
4068 | r = amdgpu_device_ip_suspend(adev); | |
4069 | ||
4070 | *need_full_reset_arg = need_full_reset; | |
4071 | } | |
4072 | ||
4073 | return r; | |
4074 | } | |
4075 | ||
041a62bc | 4076 | static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, |
26bc5340 AG |
4077 | struct list_head *device_list_handle, |
4078 | bool *need_full_reset_arg) | |
4079 | { | |
4080 | struct amdgpu_device *tmp_adev = NULL; | |
4081 | bool need_full_reset = *need_full_reset_arg, vram_lost = false; | |
4082 | int r = 0; | |
4083 | ||
4084 | /* | |
4085 | * ASIC reset has to be done on all HGMI hive nodes ASAP | |
4086 | * to allow proper links negotiation in FW (within 1 sec) | |
4087 | */ | |
4088 | if (need_full_reset) { | |
4089 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
041a62bc | 4090 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4091 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
c96cf282 | 4092 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4093 | r = -EALREADY; |
4094 | } else | |
4095 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4096 | |
041a62bc | 4097 | if (r) { |
aac89168 | 4098 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4099 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4100 | break; |
ce316fa5 LM |
4101 | } |
4102 | } | |
4103 | ||
041a62bc AG |
4104 | /* For XGMI wait for all resets to complete before proceed */ |
4105 | if (!r) { | |
ce316fa5 LM |
4106 | list_for_each_entry(tmp_adev, device_list_handle, |
4107 | gmc.xgmi.head) { | |
4108 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { | |
4109 | flush_work(&tmp_adev->xgmi_reset_work); | |
4110 | r = tmp_adev->asic_reset_res; | |
4111 | if (r) | |
4112 | break; | |
ce316fa5 LM |
4113 | } |
4114 | } | |
4115 | } | |
ce316fa5 | 4116 | } |
26bc5340 | 4117 | |
43c4d576 JC |
4118 | if (!r && amdgpu_ras_intr_triggered()) { |
4119 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
4120 | if (tmp_adev->mmhub.funcs && | |
4121 | tmp_adev->mmhub.funcs->reset_ras_error_count) | |
4122 | tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev); | |
4123 | } | |
4124 | ||
00eaa571 | 4125 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4126 | } |
00eaa571 | 4127 | |
26bc5340 AG |
4128 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { |
4129 | if (need_full_reset) { | |
4130 | /* post card */ | |
4d2997ab | 4131 | if (amdgpu_device_asic_init(tmp_adev)) |
aac89168 | 4132 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
26bc5340 AG |
4133 | |
4134 | if (!r) { | |
4135 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); | |
4136 | r = amdgpu_device_ip_resume_phase1(tmp_adev); | |
4137 | if (r) | |
4138 | goto out; | |
4139 | ||
4140 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
4141 | if (vram_lost) { | |
77e7f829 | 4142 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4143 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4144 | } |
4145 | ||
6c28aed6 | 4146 | r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT)); |
26bc5340 AG |
4147 | if (r) |
4148 | goto out; | |
4149 | ||
4150 | r = amdgpu_device_fw_loading(tmp_adev); | |
4151 | if (r) | |
4152 | return r; | |
4153 | ||
4154 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4155 | if (r) | |
4156 | goto out; | |
4157 | ||
4158 | if (vram_lost) | |
4159 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4160 | ||
fdafb359 EQ |
4161 | /* |
4162 | * Add this ASIC as tracked as reset was already | |
4163 | * complete successfully. | |
4164 | */ | |
4165 | amdgpu_register_gpu_instance(tmp_adev); | |
4166 | ||
7c04ca50 | 4167 | r = amdgpu_device_ip_late_init(tmp_adev); |
4168 | if (r) | |
4169 | goto out; | |
4170 | ||
565d1941 EQ |
4171 | amdgpu_fbdev_set_suspend(tmp_adev, 0); |
4172 | ||
e8fbaf03 GC |
4173 | /* |
4174 | * The GPU enters bad state once faulty pages | |
4175 | * by ECC has reached the threshold, and ras | |
4176 | * recovery is scheduled next. So add one check | |
4177 | * here to break recovery if it indeed exceeds | |
4178 | * bad page threshold, and remind user to | |
4179 | * retire this GPU or setting one bigger | |
4180 | * bad_page_threshold value to fix this once | |
4181 | * probing driver again. | |
4182 | */ | |
4183 | if (!amdgpu_ras_check_err_threshold(tmp_adev)) { | |
4184 | /* must succeed. */ | |
4185 | amdgpu_ras_resume(tmp_adev); | |
4186 | } else { | |
4187 | r = -EINVAL; | |
4188 | goto out; | |
4189 | } | |
e79a04d5 | 4190 | |
26bc5340 AG |
4191 | /* Update PSP FW topology after reset */ |
4192 | if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4193 | r = amdgpu_xgmi_update_topology(hive, tmp_adev); | |
4194 | } | |
4195 | } | |
4196 | ||
26bc5340 AG |
4197 | out: |
4198 | if (!r) { | |
4199 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4200 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4201 | if (r) { | |
4202 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
4203 | r = amdgpu_device_ip_suspend(tmp_adev); | |
4204 | need_full_reset = true; | |
4205 | r = -EAGAIN; | |
4206 | goto end; | |
4207 | } | |
4208 | } | |
4209 | ||
4210 | if (!r) | |
4211 | r = amdgpu_device_recover_vram(tmp_adev); | |
4212 | else | |
4213 | tmp_adev->asic_reset_res = r; | |
4214 | } | |
4215 | ||
4216 | end: | |
4217 | *need_full_reset_arg = need_full_reset; | |
4218 | return r; | |
4219 | } | |
4220 | ||
08ebb485 DL |
4221 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, |
4222 | struct amdgpu_hive_info *hive) | |
26bc5340 | 4223 | { |
53b3f8f4 DL |
4224 | if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0) |
4225 | return false; | |
4226 | ||
08ebb485 DL |
4227 | if (hive) { |
4228 | down_write_nest_lock(&adev->reset_sem, &hive->hive_lock); | |
4229 | } else { | |
4230 | down_write(&adev->reset_sem); | |
4231 | } | |
5740682e | 4232 | |
26bc5340 | 4233 | atomic_inc(&adev->gpu_reset_counter); |
a3a09142 AD |
4234 | switch (amdgpu_asic_reset_method(adev)) { |
4235 | case AMD_RESET_METHOD_MODE1: | |
4236 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4237 | break; | |
4238 | case AMD_RESET_METHOD_MODE2: | |
4239 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4240 | break; | |
4241 | default: | |
4242 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4243 | break; | |
4244 | } | |
1d721ed6 AG |
4245 | |
4246 | return true; | |
26bc5340 | 4247 | } |
d38ceaf9 | 4248 | |
26bc5340 AG |
4249 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
4250 | { | |
89041940 | 4251 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4252 | adev->mp1_state = PP_MP1_STATE_NONE; |
53b3f8f4 | 4253 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 4254 | up_write(&adev->reset_sem); |
26bc5340 AG |
4255 | } |
4256 | ||
3f12acc8 EQ |
4257 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4258 | { | |
4259 | struct pci_dev *p = NULL; | |
4260 | ||
4261 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4262 | adev->pdev->bus->number, 1); | |
4263 | if (p) { | |
4264 | pm_runtime_enable(&(p->dev)); | |
4265 | pm_runtime_resume(&(p->dev)); | |
4266 | } | |
4267 | } | |
4268 | ||
4269 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4270 | { | |
4271 | enum amd_reset_method reset_method; | |
4272 | struct pci_dev *p = NULL; | |
4273 | u64 expires; | |
4274 | ||
4275 | /* | |
4276 | * For now, only BACO and mode1 reset are confirmed | |
4277 | * to suffer the audio issue without proper suspended. | |
4278 | */ | |
4279 | reset_method = amdgpu_asic_reset_method(adev); | |
4280 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4281 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4282 | return -EINVAL; | |
4283 | ||
4284 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4285 | adev->pdev->bus->number, 1); | |
4286 | if (!p) | |
4287 | return -ENODEV; | |
4288 | ||
4289 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4290 | if (!expires) | |
4291 | /* | |
4292 | * If we cannot get the audio device autosuspend delay, | |
4293 | * a fixed 4S interval will be used. Considering 3S is | |
4294 | * the audio controller default autosuspend delay setting. | |
4295 | * 4S used here is guaranteed to cover that. | |
4296 | */ | |
54b7feb9 | 4297 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4298 | |
4299 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4300 | if (!pm_runtime_suspend(&(p->dev))) | |
4301 | break; | |
4302 | ||
4303 | if (expires < ktime_get_mono_fast_ns()) { | |
4304 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4305 | /* TODO: abort the succeeding gpu reset? */ | |
4306 | return -ETIMEDOUT; | |
4307 | } | |
4308 | } | |
4309 | ||
4310 | pm_runtime_disable(&(p->dev)); | |
4311 | ||
4312 | return 0; | |
4313 | } | |
4314 | ||
26bc5340 AG |
4315 | /** |
4316 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
4317 | * | |
4318 | * @adev: amdgpu device pointer | |
4319 | * @job: which job trigger hang | |
4320 | * | |
4321 | * Attempt to reset the GPU if it has hung (all asics). | |
4322 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
4323 | * Returns 0 for success or an error on failure. | |
4324 | */ | |
4325 | ||
4326 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
4327 | struct amdgpu_job *job) | |
4328 | { | |
1d721ed6 | 4329 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 EQ |
4330 | bool need_full_reset = false; |
4331 | bool job_signaled = false; | |
26bc5340 | 4332 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 4333 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 4334 | int i, r = 0; |
bb5c7235 | 4335 | bool need_emergency_restart = false; |
3f12acc8 | 4336 | bool audio_suspended = false; |
26bc5340 | 4337 | |
bb5c7235 WS |
4338 | /** |
4339 | * Special case: RAS triggered and full reset isn't supported | |
4340 | */ | |
4341 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
4342 | ||
d5ea093e AG |
4343 | /* |
4344 | * Flush RAM to disk so that after reboot | |
4345 | * the user can read log and see why the system rebooted. | |
4346 | */ | |
bb5c7235 | 4347 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
4348 | DRM_WARN("Emergency reboot."); |
4349 | ||
4350 | ksys_sync_helper(); | |
4351 | emergency_restart(); | |
4352 | } | |
4353 | ||
b823821f | 4354 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 4355 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 AG |
4356 | |
4357 | /* | |
1d721ed6 AG |
4358 | * Here we trylock to avoid chain of resets executing from |
4359 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
4360 | * different schedulers for same device while this TO handler is running. | |
4361 | * We always reset all schedulers for device and all devices for XGMI | |
4362 | * hive so that should take care of them too. | |
26bc5340 | 4363 | */ |
d95e8e97 | 4364 | hive = amdgpu_get_xgmi_hive(adev); |
53b3f8f4 DL |
4365 | if (hive) { |
4366 | if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) { | |
4367 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
4368 | job ? job->base.id : -1, hive->hive_id); | |
d95e8e97 | 4369 | amdgpu_put_xgmi_hive(hive); |
53b3f8f4 DL |
4370 | return 0; |
4371 | } | |
4372 | mutex_lock(&hive->hive_lock); | |
1d721ed6 | 4373 | } |
26bc5340 | 4374 | |
9e94d22c EQ |
4375 | /* |
4376 | * Build list of devices to reset. | |
4377 | * In case we are in XGMI hive mode, resort the device list | |
4378 | * to put adev in the 1st position. | |
4379 | */ | |
4380 | INIT_LIST_HEAD(&device_list); | |
4381 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
4382 | if (!hive) | |
26bc5340 | 4383 | return -ENODEV; |
9e94d22c EQ |
4384 | if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list)) |
4385 | list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list); | |
26bc5340 AG |
4386 | device_list_handle = &hive->device_list; |
4387 | } else { | |
4388 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
4389 | device_list_handle = &device_list; | |
4390 | } | |
4391 | ||
1d721ed6 AG |
4392 | /* block all schedulers and reset given job's ring */ |
4393 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
08ebb485 | 4394 | if (!amdgpu_device_lock_adev(tmp_adev, hive)) { |
aac89168 | 4395 | dev_info(tmp_adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress", |
9e94d22c | 4396 | job ? job->base.id : -1); |
cbfd17f7 DL |
4397 | r = 0; |
4398 | goto skip_recovery; | |
7c6e68c7 AG |
4399 | } |
4400 | ||
3f12acc8 EQ |
4401 | /* |
4402 | * Try to put the audio codec into suspend state | |
4403 | * before gpu reset started. | |
4404 | * | |
4405 | * Due to the power domain of the graphics device | |
4406 | * is shared with AZ power domain. Without this, | |
4407 | * we may change the audio hardware from behind | |
4408 | * the audio driver's back. That will trigger | |
4409 | * some audio codec errors. | |
4410 | */ | |
4411 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
4412 | audio_suspended = true; | |
4413 | ||
9e94d22c EQ |
4414 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
4415 | ||
52fb44cf EQ |
4416 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
4417 | ||
9e94d22c EQ |
4418 | if (!amdgpu_sriov_vf(tmp_adev)) |
4419 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
4420 | ||
12ffa55d AG |
4421 | /* |
4422 | * Mark these ASICs to be reseted as untracked first | |
4423 | * And add them back after reset completed | |
4424 | */ | |
4425 | amdgpu_unregister_gpu_instance(tmp_adev); | |
4426 | ||
a2f63ee8 | 4427 | amdgpu_fbdev_set_suspend(tmp_adev, 1); |
565d1941 | 4428 | |
f1c1314b | 4429 | /* disable ras on ALL IPs */ |
bb5c7235 | 4430 | if (!need_emergency_restart && |
b823821f | 4431 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 4432 | amdgpu_ras_suspend(tmp_adev); |
4433 | ||
1d721ed6 AG |
4434 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4435 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4436 | ||
4437 | if (!ring || !ring->sched.thread) | |
4438 | continue; | |
4439 | ||
0b2d2c2e | 4440 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 4441 | |
bb5c7235 | 4442 | if (need_emergency_restart) |
7c6e68c7 | 4443 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 AG |
4444 | } |
4445 | } | |
4446 | ||
bb5c7235 | 4447 | if (need_emergency_restart) |
7c6e68c7 AG |
4448 | goto skip_sched_resume; |
4449 | ||
1d721ed6 AG |
4450 | /* |
4451 | * Must check guilty signal here since after this point all old | |
4452 | * HW fences are force signaled. | |
4453 | * | |
4454 | * job->base holds a reference to parent fence | |
4455 | */ | |
4456 | if (job && job->base.s_fence->parent && | |
7dd8c205 | 4457 | dma_fence_is_signaled(job->base.s_fence->parent)) { |
1d721ed6 | 4458 | job_signaled = true; |
1d721ed6 AG |
4459 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
4460 | goto skip_hw_reset; | |
4461 | } | |
4462 | ||
26bc5340 AG |
4463 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
4464 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
26bc5340 AG |
4465 | r = amdgpu_device_pre_asic_reset(tmp_adev, |
4466 | NULL, | |
4467 | &need_full_reset); | |
4468 | /*TODO Should we stop ?*/ | |
4469 | if (r) { | |
aac89168 | 4470 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 4471 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
4472 | tmp_adev->asic_reset_res = r; |
4473 | } | |
4474 | } | |
4475 | ||
4476 | /* Actual ASIC resets if needed.*/ | |
4477 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
4478 | if (amdgpu_sriov_vf(adev)) { | |
4479 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
4480 | if (r) | |
4481 | adev->asic_reset_res = r; | |
4482 | } else { | |
041a62bc | 4483 | r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset); |
26bc5340 AG |
4484 | if (r && r == -EAGAIN) |
4485 | goto retry; | |
4486 | } | |
4487 | ||
1d721ed6 AG |
4488 | skip_hw_reset: |
4489 | ||
26bc5340 AG |
4490 | /* Post ASIC reset for all devs .*/ |
4491 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
7c6e68c7 | 4492 | |
1d721ed6 AG |
4493 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4494 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4495 | ||
4496 | if (!ring || !ring->sched.thread) | |
4497 | continue; | |
4498 | ||
4499 | /* No point to resubmit jobs if we didn't HW reset*/ | |
4500 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
4501 | drm_sched_resubmit_jobs(&ring->sched); | |
4502 | ||
4503 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
4504 | } | |
4505 | ||
4506 | if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) { | |
4a580877 | 4507 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
4508 | } |
4509 | ||
4510 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
4511 | |
4512 | if (r) { | |
4513 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 4514 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
4515 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
4516 | } else { | |
12ffa55d | 4517 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 | 4518 | } |
7c6e68c7 | 4519 | } |
26bc5340 | 4520 | |
7c6e68c7 AG |
4521 | skip_sched_resume: |
4522 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
4523 | /*unlock kfd: SRIOV would do it separately */ | |
bb5c7235 | 4524 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
7c6e68c7 | 4525 | amdgpu_amdkfd_post_reset(tmp_adev); |
3f12acc8 EQ |
4526 | if (audio_suspended) |
4527 | amdgpu_device_resume_display_audio(tmp_adev); | |
26bc5340 AG |
4528 | amdgpu_device_unlock_adev(tmp_adev); |
4529 | } | |
4530 | ||
cbfd17f7 | 4531 | skip_recovery: |
9e94d22c | 4532 | if (hive) { |
53b3f8f4 | 4533 | atomic_set(&hive->in_reset, 0); |
9e94d22c | 4534 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 4535 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 4536 | } |
26bc5340 AG |
4537 | |
4538 | if (r) | |
4539 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); | |
d38ceaf9 AD |
4540 | return r; |
4541 | } | |
4542 | ||
e3ecdffa AD |
4543 | /** |
4544 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
4545 | * | |
4546 | * @adev: amdgpu_device pointer | |
4547 | * | |
4548 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
4549 | * and lanes) of the slot the device is in. Handles APUs and | |
4550 | * virtualized environments where PCIE config space may not be available. | |
4551 | */ | |
5494d864 | 4552 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 4553 | { |
5d9a6330 | 4554 | struct pci_dev *pdev; |
c5313457 HK |
4555 | enum pci_bus_speed speed_cap, platform_speed_cap; |
4556 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 4557 | |
cd474ba0 AD |
4558 | if (amdgpu_pcie_gen_cap) |
4559 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 4560 | |
cd474ba0 AD |
4561 | if (amdgpu_pcie_lane_cap) |
4562 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 4563 | |
cd474ba0 AD |
4564 | /* covers APUs as well */ |
4565 | if (pci_is_root_bus(adev->pdev->bus)) { | |
4566 | if (adev->pm.pcie_gen_mask == 0) | |
4567 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
4568 | if (adev->pm.pcie_mlw_mask == 0) | |
4569 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 4570 | return; |
cd474ba0 | 4571 | } |
d0dd7f0c | 4572 | |
c5313457 HK |
4573 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
4574 | return; | |
4575 | ||
dbaa922b AD |
4576 | pcie_bandwidth_available(adev->pdev, NULL, |
4577 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 4578 | |
cd474ba0 | 4579 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
4580 | /* asic caps */ |
4581 | pdev = adev->pdev; | |
4582 | speed_cap = pcie_get_speed_cap(pdev); | |
4583 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
4584 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
4585 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
4586 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 4587 | } else { |
5d9a6330 AD |
4588 | if (speed_cap == PCIE_SPEED_16_0GT) |
4589 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4590 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4591 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4592 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
4593 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
4594 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4595 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4596 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
4597 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
4598 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4599 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4600 | else | |
4601 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4602 | } | |
4603 | /* platform caps */ | |
c5313457 | 4604 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
4605 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4606 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4607 | } else { | |
c5313457 | 4608 | if (platform_speed_cap == PCIE_SPEED_16_0GT) |
5d9a6330 AD |
4609 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4610 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4611 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4612 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 4613 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
4614 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4615 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4616 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 4617 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
4618 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4619 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4620 | else | |
4621 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4622 | ||
cd474ba0 AD |
4623 | } |
4624 | } | |
4625 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 4626 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
4627 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
4628 | } else { | |
c5313457 | 4629 | switch (platform_link_width) { |
5d9a6330 | 4630 | case PCIE_LNK_X32: |
cd474ba0 AD |
4631 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
4632 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
4633 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
4634 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4635 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4636 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4637 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4638 | break; | |
5d9a6330 | 4639 | case PCIE_LNK_X16: |
cd474ba0 AD |
4640 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
4641 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
4642 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4643 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4644 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4645 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4646 | break; | |
5d9a6330 | 4647 | case PCIE_LNK_X12: |
cd474ba0 AD |
4648 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
4649 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4650 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4651 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4652 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4653 | break; | |
5d9a6330 | 4654 | case PCIE_LNK_X8: |
cd474ba0 AD |
4655 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
4656 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4657 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4658 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4659 | break; | |
5d9a6330 | 4660 | case PCIE_LNK_X4: |
cd474ba0 AD |
4661 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
4662 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4663 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4664 | break; | |
5d9a6330 | 4665 | case PCIE_LNK_X2: |
cd474ba0 AD |
4666 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
4667 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4668 | break; | |
5d9a6330 | 4669 | case PCIE_LNK_X1: |
cd474ba0 AD |
4670 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
4671 | break; | |
4672 | default: | |
4673 | break; | |
4674 | } | |
d0dd7f0c AD |
4675 | } |
4676 | } | |
4677 | } | |
d38ceaf9 | 4678 | |
361dbd01 AD |
4679 | int amdgpu_device_baco_enter(struct drm_device *dev) |
4680 | { | |
1348969a | 4681 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 4682 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 4683 | |
4a580877 | 4684 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
4685 | return -ENOTSUPP; |
4686 | ||
7a22677b LM |
4687 | if (ras && ras->supported) |
4688 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); | |
4689 | ||
9530273e | 4690 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
4691 | } |
4692 | ||
4693 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
4694 | { | |
1348969a | 4695 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 4696 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 4697 | int ret = 0; |
361dbd01 | 4698 | |
4a580877 | 4699 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
4700 | return -ENOTSUPP; |
4701 | ||
9530273e EQ |
4702 | ret = amdgpu_dpm_baco_exit(adev); |
4703 | if (ret) | |
4704 | return ret; | |
7a22677b LM |
4705 | |
4706 | if (ras && ras->supported) | |
4707 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); | |
4708 | ||
4709 | return 0; | |
361dbd01 | 4710 | } |
c9a6b82f AG |
4711 | |
4712 | /** | |
4713 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
4714 | * @pdev: PCI device struct | |
4715 | * @state: PCI channel state | |
4716 | * | |
4717 | * Description: Called when a PCI error is detected. | |
4718 | * | |
4719 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
4720 | */ | |
4721 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
4722 | { | |
4723 | struct drm_device *dev = pci_get_drvdata(pdev); | |
4724 | struct amdgpu_device *adev = drm_to_adev(dev); | |
4725 | ||
4726 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
4727 | ||
4728 | switch (state) { | |
4729 | case pci_channel_io_normal: | |
4730 | return PCI_ERS_RESULT_CAN_RECOVER; | |
4731 | case pci_channel_io_frozen: | |
4732 | /* Fatal error, prepare for slot reset */ | |
4733 | amdgpu_device_lock_adev(adev); | |
4734 | return PCI_ERS_RESULT_NEED_RESET; | |
4735 | case pci_channel_io_perm_failure: | |
4736 | /* Permanent error, prepare for device removal */ | |
4737 | return PCI_ERS_RESULT_DISCONNECT; | |
4738 | } | |
4739 | ||
4740 | return PCI_ERS_RESULT_NEED_RESET; | |
4741 | } | |
4742 | ||
4743 | /** | |
4744 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
4745 | * @pdev: pointer to PCI device | |
4746 | */ | |
4747 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
4748 | { | |
4749 | ||
4750 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
4751 | ||
4752 | /* TODO - dump whatever for debugging purposes */ | |
4753 | ||
4754 | /* This called only if amdgpu_pci_error_detected returns | |
4755 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
4756 | * works, no need to reset slot. | |
4757 | */ | |
4758 | ||
4759 | return PCI_ERS_RESULT_RECOVERED; | |
4760 | } | |
4761 | ||
4762 | /** | |
4763 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
4764 | * @pdev: PCI device struct | |
4765 | * | |
4766 | * Description: This routine is called by the pci error recovery | |
4767 | * code after the PCI slot has been reset, just before we | |
4768 | * should resume normal operations. | |
4769 | */ | |
4770 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
4771 | { | |
4772 | struct drm_device *dev = pci_get_drvdata(pdev); | |
4773 | struct amdgpu_device *adev = drm_to_adev(dev); | |
4774 | int r; | |
4775 | bool vram_lost; | |
4776 | ||
4777 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
4778 | ||
4779 | pci_restore_state(pdev); | |
4780 | ||
4781 | r = amdgpu_device_ip_suspend(adev); | |
4782 | if (r) | |
4783 | goto out; | |
4784 | ||
4785 | ||
4786 | /* post card */ | |
4787 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
4788 | if (r) | |
4789 | goto out; | |
4790 | ||
4791 | r = amdgpu_device_ip_resume_phase1(adev); | |
4792 | if (r) | |
4793 | goto out; | |
4794 | ||
4795 | vram_lost = amdgpu_device_check_vram_lost(adev); | |
4796 | if (vram_lost) { | |
4797 | DRM_INFO("VRAM is lost due to GPU reset!\n"); | |
4798 | amdgpu_inc_vram_lost(adev); | |
4799 | } | |
4800 | ||
4801 | r = amdgpu_gtt_mgr_recover( | |
4802 | &adev->mman.bdev.man[TTM_PL_TT]); | |
4803 | if (r) | |
4804 | goto out; | |
4805 | ||
4806 | r = amdgpu_device_fw_loading(adev); | |
4807 | if (r) | |
4808 | return r; | |
4809 | ||
4810 | r = amdgpu_device_ip_resume_phase2(adev); | |
4811 | if (r) | |
4812 | goto out; | |
4813 | ||
4814 | if (vram_lost) | |
4815 | amdgpu_device_fill_reset_magic(adev); | |
4816 | ||
4817 | /* | |
4818 | * Add this ASIC as tracked as reset was already | |
4819 | * complete successfully. | |
4820 | */ | |
4821 | amdgpu_register_gpu_instance(adev); | |
4822 | ||
4823 | r = amdgpu_device_ip_late_init(adev); | |
4824 | if (r) | |
4825 | goto out; | |
4826 | ||
4827 | amdgpu_fbdev_set_suspend(adev, 0); | |
4828 | ||
4829 | /* must succeed. */ | |
4830 | amdgpu_ras_resume(adev); | |
4831 | ||
4832 | ||
4833 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
4834 | r = amdgpu_ib_ring_tests(adev); | |
4835 | if (r) | |
4836 | goto out; | |
4837 | ||
4838 | r = amdgpu_device_recover_vram(adev); | |
4839 | ||
4840 | out: | |
4841 | ||
4842 | if (!r) { | |
4843 | DRM_INFO("PCIe error recovery succeeded\n"); | |
4844 | } else { | |
4845 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
4846 | amdgpu_device_unlock_adev(adev); | |
4847 | } | |
4848 | ||
4849 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
4850 | } | |
4851 | ||
4852 | /** | |
4853 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
4854 | * @pdev: pointer to PCI device | |
4855 | * | |
4856 | * Called when the error recovery driver tells us that its | |
4857 | * OK to resume normal operation. Use completion to allow | |
4858 | * halted scsi ops to resume. | |
4859 | */ | |
4860 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
4861 | { | |
4862 | struct drm_device *dev = pci_get_drvdata(pdev); | |
4863 | struct amdgpu_device *adev = drm_to_adev(dev); | |
4864 | ||
4865 | amdgpu_device_unlock_adev(adev); | |
4866 | ||
4867 | DRM_INFO("PCI error: resume callback!!\n"); | |
4868 | } |