Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
4a74c38c | 33 | #include <linux/iommu.h> |
901e2be2 | 34 | #include <linux/pci.h> |
3d8785f6 SA |
35 | #include <linux/devcoredump.h> |
36 | #include <generated/utsrelease.h> | |
08a2fd23 | 37 | #include <linux/pci-p2pdma.h> |
fdf2f6c5 | 38 | |
4562236b | 39 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 40 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
41 | #include <drm/amdgpu_drm.h> |
42 | #include <linux/vgaarb.h> | |
43 | #include <linux/vga_switcheroo.h> | |
44 | #include <linux/efi.h> | |
45 | #include "amdgpu.h" | |
f4b373f4 | 46 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
47 | #include "amdgpu_i2c.h" |
48 | #include "atom.h" | |
49 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 50 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 51 | #include "amd_pcie.h" |
33f34802 KW |
52 | #ifdef CONFIG_DRM_AMDGPU_SI |
53 | #include "si.h" | |
54 | #endif | |
a2e73f56 AD |
55 | #ifdef CONFIG_DRM_AMDGPU_CIK |
56 | #include "cik.h" | |
57 | #endif | |
aaa36a97 | 58 | #include "vi.h" |
460826e6 | 59 | #include "soc15.h" |
0a5b8c7b | 60 | #include "nv.h" |
d38ceaf9 | 61 | #include "bif/bif_4_1_d.h" |
bec86378 | 62 | #include <linux/firmware.h> |
89041940 | 63 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 64 | |
ba997709 | 65 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 66 | #include "amdgpu_pm.h" |
d38ceaf9 | 67 | |
5183411b | 68 | #include "amdgpu_xgmi.h" |
c030f2e4 | 69 | #include "amdgpu_ras.h" |
9c7c85f7 | 70 | #include "amdgpu_pmu.h" |
bd607166 | 71 | #include "amdgpu_fru_eeprom.h" |
04442bf7 | 72 | #include "amdgpu_reset.h" |
5183411b | 73 | |
d5ea093e | 74 | #include <linux/suspend.h> |
c6a6e2db | 75 | #include <drm/task_barrier.h> |
3f12acc8 | 76 | #include <linux/pm_runtime.h> |
d5ea093e | 77 | |
f89f8c6b AG |
78 | #include <drm/drm_drv.h> |
79 | ||
e2a75f88 | 80 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 81 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 82 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 83 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 84 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 85 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
42b325e5 | 86 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
e2a75f88 | 87 | |
2dc80b00 | 88 | #define AMDGPU_RESUME_MS 2000 |
7258fa31 SK |
89 | #define AMDGPU_MAX_RETRY_LIMIT 2 |
90 | #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL) | |
2dc80b00 | 91 | |
050091ab | 92 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
93 | "TAHITI", |
94 | "PITCAIRN", | |
95 | "VERDE", | |
96 | "OLAND", | |
97 | "HAINAN", | |
d38ceaf9 AD |
98 | "BONAIRE", |
99 | "KAVERI", | |
100 | "KABINI", | |
101 | "HAWAII", | |
102 | "MULLINS", | |
103 | "TOPAZ", | |
104 | "TONGA", | |
48299f95 | 105 | "FIJI", |
d38ceaf9 | 106 | "CARRIZO", |
139f4917 | 107 | "STONEY", |
2cc0c0b5 FC |
108 | "POLARIS10", |
109 | "POLARIS11", | |
c4642a47 | 110 | "POLARIS12", |
48ff108d | 111 | "VEGAM", |
d4196f01 | 112 | "VEGA10", |
8fab806a | 113 | "VEGA12", |
956fcddc | 114 | "VEGA20", |
2ca8a5d2 | 115 | "RAVEN", |
d6c3b24e | 116 | "ARCTURUS", |
1eee4228 | 117 | "RENOIR", |
d46b417a | 118 | "ALDEBARAN", |
852a6626 | 119 | "NAVI10", |
d0f56dc2 | 120 | "CYAN_SKILLFISH", |
87dbad02 | 121 | "NAVI14", |
9802f5d7 | 122 | "NAVI12", |
ccaf72d3 | 123 | "SIENNA_CICHLID", |
ddd8fbe7 | 124 | "NAVY_FLOUNDER", |
4f1e9a76 | 125 | "VANGOGH", |
a2468e04 | 126 | "DIMGREY_CAVEFISH", |
6f169591 | 127 | "BEIGE_GOBY", |
ee9236b7 | 128 | "YELLOW_CARP", |
3ae695d6 | 129 | "IP DISCOVERY", |
d38ceaf9 AD |
130 | "LAST", |
131 | }; | |
132 | ||
dcea6e65 KR |
133 | /** |
134 | * DOC: pcie_replay_count | |
135 | * | |
136 | * The amdgpu driver provides a sysfs API for reporting the total number | |
137 | * of PCIe replays (NAKs) | |
138 | * The file pcie_replay_count is used for this and returns the total | |
139 | * number of replays as a sum of the NAKs generated and NAKs received | |
140 | */ | |
141 | ||
142 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
143 | struct device_attribute *attr, char *buf) | |
144 | { | |
145 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 146 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
147 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
148 | ||
36000c7a | 149 | return sysfs_emit(buf, "%llu\n", cnt); |
dcea6e65 KR |
150 | } |
151 | ||
152 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
153 | amdgpu_device_get_pcie_replay_count, NULL); | |
154 | ||
5494d864 AD |
155 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
156 | ||
bd607166 KR |
157 | /** |
158 | * DOC: product_name | |
159 | * | |
160 | * The amdgpu driver provides a sysfs API for reporting the product name | |
161 | * for the device | |
162 | * The file serial_number is used for this and returns the product name | |
163 | * as returned from the FRU. | |
164 | * NOTE: This is only available for certain server cards | |
165 | */ | |
166 | ||
167 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
168 | struct device_attribute *attr, char *buf) | |
169 | { | |
170 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 171 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 172 | |
36000c7a | 173 | return sysfs_emit(buf, "%s\n", adev->product_name); |
bd607166 KR |
174 | } |
175 | ||
176 | static DEVICE_ATTR(product_name, S_IRUGO, | |
177 | amdgpu_device_get_product_name, NULL); | |
178 | ||
179 | /** | |
180 | * DOC: product_number | |
181 | * | |
182 | * The amdgpu driver provides a sysfs API for reporting the part number | |
183 | * for the device | |
184 | * The file serial_number is used for this and returns the part number | |
185 | * as returned from the FRU. | |
186 | * NOTE: This is only available for certain server cards | |
187 | */ | |
188 | ||
189 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
190 | struct device_attribute *attr, char *buf) | |
191 | { | |
192 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 193 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 194 | |
36000c7a | 195 | return sysfs_emit(buf, "%s\n", adev->product_number); |
bd607166 KR |
196 | } |
197 | ||
198 | static DEVICE_ATTR(product_number, S_IRUGO, | |
199 | amdgpu_device_get_product_number, NULL); | |
200 | ||
201 | /** | |
202 | * DOC: serial_number | |
203 | * | |
204 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
205 | * for the device | |
206 | * The file serial_number is used for this and returns the serial number | |
207 | * as returned from the FRU. | |
208 | * NOTE: This is only available for certain server cards | |
209 | */ | |
210 | ||
211 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
212 | struct device_attribute *attr, char *buf) | |
213 | { | |
214 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 215 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 216 | |
36000c7a | 217 | return sysfs_emit(buf, "%s\n", adev->serial); |
bd607166 KR |
218 | } |
219 | ||
220 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
221 | amdgpu_device_get_serial_number, NULL); | |
222 | ||
fd496ca8 | 223 | /** |
b98c6299 | 224 | * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control |
fd496ca8 AD |
225 | * |
226 | * @dev: drm_device pointer | |
227 | * | |
b98c6299 | 228 | * Returns true if the device is a dGPU with ATPX power control, |
fd496ca8 AD |
229 | * otherwise return false. |
230 | */ | |
b98c6299 | 231 | bool amdgpu_device_supports_px(struct drm_device *dev) |
fd496ca8 AD |
232 | { |
233 | struct amdgpu_device *adev = drm_to_adev(dev); | |
234 | ||
b98c6299 | 235 | if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid()) |
fd496ca8 AD |
236 | return true; |
237 | return false; | |
238 | } | |
239 | ||
e3ecdffa | 240 | /** |
0330b848 | 241 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
242 | * |
243 | * @dev: drm_device pointer | |
244 | * | |
b98c6299 | 245 | * Returns true if the device is a dGPU with ACPI power control, |
e3ecdffa AD |
246 | * otherwise return false. |
247 | */ | |
31af062a | 248 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 249 | { |
1348969a | 250 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 251 | |
b98c6299 AD |
252 | if (adev->has_pr3 || |
253 | ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid())) | |
d38ceaf9 AD |
254 | return true; |
255 | return false; | |
256 | } | |
257 | ||
a69cba42 AD |
258 | /** |
259 | * amdgpu_device_supports_baco - Does the device support BACO | |
260 | * | |
261 | * @dev: drm_device pointer | |
262 | * | |
263 | * Returns true if the device supporte BACO, | |
264 | * otherwise return false. | |
265 | */ | |
266 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
267 | { | |
1348969a | 268 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
269 | |
270 | return amdgpu_asic_supports_baco(adev); | |
271 | } | |
272 | ||
3fa8f89d S |
273 | /** |
274 | * amdgpu_device_supports_smart_shift - Is the device dGPU with | |
275 | * smart shift support | |
276 | * | |
277 | * @dev: drm_device pointer | |
278 | * | |
279 | * Returns true if the device is a dGPU with Smart Shift support, | |
280 | * otherwise returns false. | |
281 | */ | |
282 | bool amdgpu_device_supports_smart_shift(struct drm_device *dev) | |
283 | { | |
284 | return (amdgpu_device_supports_boco(dev) && | |
285 | amdgpu_acpi_is_power_shift_control_supported()); | |
286 | } | |
287 | ||
6e3cd2a9 MCC |
288 | /* |
289 | * VRAM access helper functions | |
290 | */ | |
291 | ||
e35e2b11 | 292 | /** |
048af66b | 293 | * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA |
e35e2b11 TY |
294 | * |
295 | * @adev: amdgpu_device pointer | |
296 | * @pos: offset of the buffer in vram | |
297 | * @buf: virtual address of the buffer in system memory | |
298 | * @size: read/write size, sizeof(@buf) must > @size | |
299 | * @write: true - write to vram, otherwise - read from vram | |
300 | */ | |
048af66b KW |
301 | void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, |
302 | void *buf, size_t size, bool write) | |
e35e2b11 | 303 | { |
e35e2b11 | 304 | unsigned long flags; |
048af66b KW |
305 | uint32_t hi = ~0, tmp = 0; |
306 | uint32_t *data = buf; | |
ce05ac56 | 307 | uint64_t last; |
f89f8c6b | 308 | int idx; |
ce05ac56 | 309 | |
c58a863b | 310 | if (!drm_dev_enter(adev_to_drm(adev), &idx)) |
f89f8c6b | 311 | return; |
9d11eb0d | 312 | |
048af66b KW |
313 | BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4)); |
314 | ||
315 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
316 | for (last = pos + size; pos < last; pos += 4) { | |
317 | tmp = pos >> 31; | |
318 | ||
319 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); | |
320 | if (tmp != hi) { | |
321 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
322 | hi = tmp; | |
323 | } | |
324 | if (write) | |
325 | WREG32_NO_KIQ(mmMM_DATA, *data++); | |
326 | else | |
327 | *data++ = RREG32_NO_KIQ(mmMM_DATA); | |
328 | } | |
329 | ||
330 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
331 | drm_dev_exit(idx); | |
332 | } | |
333 | ||
334 | /** | |
bbe04dec | 335 | * amdgpu_device_aper_access - access vram by vram aperature |
048af66b KW |
336 | * |
337 | * @adev: amdgpu_device pointer | |
338 | * @pos: offset of the buffer in vram | |
339 | * @buf: virtual address of the buffer in system memory | |
340 | * @size: read/write size, sizeof(@buf) must > @size | |
341 | * @write: true - write to vram, otherwise - read from vram | |
342 | * | |
343 | * The return value means how many bytes have been transferred. | |
344 | */ | |
345 | size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, | |
346 | void *buf, size_t size, bool write) | |
347 | { | |
9d11eb0d | 348 | #ifdef CONFIG_64BIT |
048af66b KW |
349 | void __iomem *addr; |
350 | size_t count = 0; | |
351 | uint64_t last; | |
352 | ||
353 | if (!adev->mman.aper_base_kaddr) | |
354 | return 0; | |
355 | ||
9d11eb0d CK |
356 | last = min(pos + size, adev->gmc.visible_vram_size); |
357 | if (last > pos) { | |
048af66b KW |
358 | addr = adev->mman.aper_base_kaddr + pos; |
359 | count = last - pos; | |
9d11eb0d CK |
360 | |
361 | if (write) { | |
362 | memcpy_toio(addr, buf, count); | |
363 | mb(); | |
810085dd | 364 | amdgpu_device_flush_hdp(adev, NULL); |
9d11eb0d | 365 | } else { |
810085dd | 366 | amdgpu_device_invalidate_hdp(adev, NULL); |
9d11eb0d CK |
367 | mb(); |
368 | memcpy_fromio(buf, addr, count); | |
369 | } | |
370 | ||
9d11eb0d | 371 | } |
048af66b KW |
372 | |
373 | return count; | |
374 | #else | |
375 | return 0; | |
9d11eb0d | 376 | #endif |
048af66b | 377 | } |
9d11eb0d | 378 | |
048af66b KW |
379 | /** |
380 | * amdgpu_device_vram_access - read/write a buffer in vram | |
381 | * | |
382 | * @adev: amdgpu_device pointer | |
383 | * @pos: offset of the buffer in vram | |
384 | * @buf: virtual address of the buffer in system memory | |
385 | * @size: read/write size, sizeof(@buf) must > @size | |
386 | * @write: true - write to vram, otherwise - read from vram | |
387 | */ | |
388 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
389 | void *buf, size_t size, bool write) | |
390 | { | |
391 | size_t count; | |
e35e2b11 | 392 | |
048af66b KW |
393 | /* try to using vram apreature to access vram first */ |
394 | count = amdgpu_device_aper_access(adev, pos, buf, size, write); | |
395 | size -= count; | |
396 | if (size) { | |
397 | /* using MM to access rest vram */ | |
398 | pos += count; | |
399 | buf += count; | |
400 | amdgpu_device_mm_access(adev, pos, buf, size, write); | |
e35e2b11 TY |
401 | } |
402 | } | |
403 | ||
d38ceaf9 | 404 | /* |
f7ee1874 | 405 | * register access helper functions. |
d38ceaf9 | 406 | */ |
56b53c0b DL |
407 | |
408 | /* Check if hw access should be skipped because of hotplug or device error */ | |
409 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
410 | { | |
7afefb81 | 411 | if (adev->no_hw_access) |
56b53c0b DL |
412 | return true; |
413 | ||
414 | #ifdef CONFIG_LOCKDEP | |
415 | /* | |
416 | * This is a bit complicated to understand, so worth a comment. What we assert | |
417 | * here is that the GPU reset is not running on another thread in parallel. | |
418 | * | |
419 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
420 | * we know that the reset is not running in paralell. | |
421 | * | |
422 | * If the trylock fails we assert that we are either already holding the read | |
423 | * side of the lock or are the reset thread itself and hold the write side of | |
424 | * the lock. | |
425 | */ | |
426 | if (in_task()) { | |
d0fb18b5 AG |
427 | if (down_read_trylock(&adev->reset_domain->sem)) |
428 | up_read(&adev->reset_domain->sem); | |
56b53c0b | 429 | else |
d0fb18b5 | 430 | lockdep_assert_held(&adev->reset_domain->sem); |
56b53c0b DL |
431 | } |
432 | #endif | |
433 | return false; | |
434 | } | |
435 | ||
e3ecdffa | 436 | /** |
f7ee1874 | 437 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
438 | * |
439 | * @adev: amdgpu_device pointer | |
440 | * @reg: dword aligned register offset | |
441 | * @acc_flags: access flags which require special behavior | |
442 | * | |
443 | * Returns the 32 bit value from the offset specified. | |
444 | */ | |
f7ee1874 HZ |
445 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
446 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 447 | { |
f4b373f4 TSD |
448 | uint32_t ret; |
449 | ||
56b53c0b | 450 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
451 | return 0; |
452 | ||
f7ee1874 HZ |
453 | if ((reg * 4) < adev->rmmio_size) { |
454 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
455 | amdgpu_sriov_runtime(adev) && | |
d0fb18b5 | 456 | down_read_trylock(&adev->reset_domain->sem)) { |
f7ee1874 | 457 | ret = amdgpu_kiq_rreg(adev, reg); |
d0fb18b5 | 458 | up_read(&adev->reset_domain->sem); |
f7ee1874 HZ |
459 | } else { |
460 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
461 | } | |
462 | } else { | |
463 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 464 | } |
bc992ba5 | 465 | |
f7ee1874 | 466 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 467 | |
f4b373f4 | 468 | return ret; |
d38ceaf9 AD |
469 | } |
470 | ||
421a2a30 ML |
471 | /* |
472 | * MMIO register read with bytes helper functions | |
473 | * @offset:bytes offset from MMIO start | |
474 | * | |
475 | */ | |
476 | ||
e3ecdffa AD |
477 | /** |
478 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
479 | * | |
480 | * @adev: amdgpu_device pointer | |
481 | * @offset: byte aligned register offset | |
482 | * | |
483 | * Returns the 8 bit value from the offset specified. | |
484 | */ | |
7cbbc745 AG |
485 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
486 | { | |
56b53c0b | 487 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
488 | return 0; |
489 | ||
421a2a30 ML |
490 | if (offset < adev->rmmio_size) |
491 | return (readb(adev->rmmio + offset)); | |
492 | BUG(); | |
493 | } | |
494 | ||
495 | /* | |
496 | * MMIO register write with bytes helper functions | |
497 | * @offset:bytes offset from MMIO start | |
498 | * @value: the value want to be written to the register | |
499 | * | |
500 | */ | |
e3ecdffa AD |
501 | /** |
502 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
503 | * | |
504 | * @adev: amdgpu_device pointer | |
505 | * @offset: byte aligned register offset | |
506 | * @value: 8 bit value to write | |
507 | * | |
508 | * Writes the value specified to the offset specified. | |
509 | */ | |
7cbbc745 AG |
510 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
511 | { | |
56b53c0b | 512 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
513 | return; |
514 | ||
421a2a30 ML |
515 | if (offset < adev->rmmio_size) |
516 | writeb(value, adev->rmmio + offset); | |
517 | else | |
518 | BUG(); | |
519 | } | |
520 | ||
e3ecdffa | 521 | /** |
f7ee1874 | 522 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
523 | * |
524 | * @adev: amdgpu_device pointer | |
525 | * @reg: dword aligned register offset | |
526 | * @v: 32 bit value to write to the register | |
527 | * @acc_flags: access flags which require special behavior | |
528 | * | |
529 | * Writes the value specified to the offset specified. | |
530 | */ | |
f7ee1874 HZ |
531 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
532 | uint32_t reg, uint32_t v, | |
533 | uint32_t acc_flags) | |
d38ceaf9 | 534 | { |
56b53c0b | 535 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
536 | return; |
537 | ||
f7ee1874 HZ |
538 | if ((reg * 4) < adev->rmmio_size) { |
539 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
540 | amdgpu_sriov_runtime(adev) && | |
d0fb18b5 | 541 | down_read_trylock(&adev->reset_domain->sem)) { |
f7ee1874 | 542 | amdgpu_kiq_wreg(adev, reg, v); |
d0fb18b5 | 543 | up_read(&adev->reset_domain->sem); |
f7ee1874 HZ |
544 | } else { |
545 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
546 | } | |
547 | } else { | |
548 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 549 | } |
bc992ba5 | 550 | |
f7ee1874 | 551 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 552 | } |
d38ceaf9 | 553 | |
03f2abb0 | 554 | /** |
4cc9f86f | 555 | * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range |
2e0cc4d4 | 556 | * |
71579346 RB |
557 | * @adev: amdgpu_device pointer |
558 | * @reg: mmio/rlc register | |
559 | * @v: value to write | |
560 | * | |
561 | * this function is invoked only for the debugfs register access | |
03f2abb0 | 562 | */ |
f7ee1874 HZ |
563 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
564 | uint32_t reg, uint32_t v) | |
2e0cc4d4 | 565 | { |
56b53c0b | 566 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
567 | return; |
568 | ||
2e0cc4d4 | 569 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
570 | adev->gfx.rlc.funcs && |
571 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 | 572 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
1b2dc99e | 573 | return amdgpu_sriov_wreg(adev, reg, v, 0, 0); |
4cc9f86f TSD |
574 | } else if ((reg * 4) >= adev->rmmio_size) { |
575 | adev->pcie_wreg(adev, reg * 4, v); | |
f7ee1874 HZ |
576 | } else { |
577 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 578 | } |
d38ceaf9 AD |
579 | } |
580 | ||
d38ceaf9 AD |
581 | /** |
582 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
583 | * | |
584 | * @adev: amdgpu_device pointer | |
585 | * @index: doorbell index | |
586 | * | |
587 | * Returns the value in the doorbell aperture at the | |
588 | * requested doorbell index (CIK). | |
589 | */ | |
590 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
591 | { | |
56b53c0b | 592 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
593 | return 0; |
594 | ||
d38ceaf9 AD |
595 | if (index < adev->doorbell.num_doorbells) { |
596 | return readl(adev->doorbell.ptr + index); | |
597 | } else { | |
598 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
599 | return 0; | |
600 | } | |
601 | } | |
602 | ||
603 | /** | |
604 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
605 | * | |
606 | * @adev: amdgpu_device pointer | |
607 | * @index: doorbell index | |
608 | * @v: value to write | |
609 | * | |
610 | * Writes @v to the doorbell aperture at the | |
611 | * requested doorbell index (CIK). | |
612 | */ | |
613 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
614 | { | |
56b53c0b | 615 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
616 | return; |
617 | ||
d38ceaf9 AD |
618 | if (index < adev->doorbell.num_doorbells) { |
619 | writel(v, adev->doorbell.ptr + index); | |
620 | } else { | |
621 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
622 | } | |
623 | } | |
624 | ||
832be404 KW |
625 | /** |
626 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
627 | * | |
628 | * @adev: amdgpu_device pointer | |
629 | * @index: doorbell index | |
630 | * | |
631 | * Returns the value in the doorbell aperture at the | |
632 | * requested doorbell index (VEGA10+). | |
633 | */ | |
634 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
635 | { | |
56b53c0b | 636 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
637 | return 0; |
638 | ||
832be404 KW |
639 | if (index < adev->doorbell.num_doorbells) { |
640 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
641 | } else { | |
642 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
643 | return 0; | |
644 | } | |
645 | } | |
646 | ||
647 | /** | |
648 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
649 | * | |
650 | * @adev: amdgpu_device pointer | |
651 | * @index: doorbell index | |
652 | * @v: value to write | |
653 | * | |
654 | * Writes @v to the doorbell aperture at the | |
655 | * requested doorbell index (VEGA10+). | |
656 | */ | |
657 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
658 | { | |
56b53c0b | 659 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
660 | return; |
661 | ||
832be404 KW |
662 | if (index < adev->doorbell.num_doorbells) { |
663 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
664 | } else { | |
665 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
666 | } | |
667 | } | |
668 | ||
1bba3683 HZ |
669 | /** |
670 | * amdgpu_device_indirect_rreg - read an indirect register | |
671 | * | |
672 | * @adev: amdgpu_device pointer | |
673 | * @pcie_index: mmio register offset | |
674 | * @pcie_data: mmio register offset | |
22f453fb | 675 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
676 | * |
677 | * Returns the value of indirect register @reg_addr | |
678 | */ | |
679 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
680 | u32 pcie_index, u32 pcie_data, | |
681 | u32 reg_addr) | |
682 | { | |
683 | unsigned long flags; | |
684 | u32 r; | |
685 | void __iomem *pcie_index_offset; | |
686 | void __iomem *pcie_data_offset; | |
687 | ||
688 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
689 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
690 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
691 | ||
692 | writel(reg_addr, pcie_index_offset); | |
693 | readl(pcie_index_offset); | |
694 | r = readl(pcie_data_offset); | |
695 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
696 | ||
697 | return r; | |
698 | } | |
699 | ||
700 | /** | |
701 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
702 | * | |
703 | * @adev: amdgpu_device pointer | |
704 | * @pcie_index: mmio register offset | |
705 | * @pcie_data: mmio register offset | |
22f453fb | 706 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
707 | * |
708 | * Returns the value of indirect register @reg_addr | |
709 | */ | |
710 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
711 | u32 pcie_index, u32 pcie_data, | |
712 | u32 reg_addr) | |
713 | { | |
714 | unsigned long flags; | |
715 | u64 r; | |
716 | void __iomem *pcie_index_offset; | |
717 | void __iomem *pcie_data_offset; | |
718 | ||
719 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
720 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
721 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
722 | ||
723 | /* read low 32 bits */ | |
724 | writel(reg_addr, pcie_index_offset); | |
725 | readl(pcie_index_offset); | |
726 | r = readl(pcie_data_offset); | |
727 | /* read high 32 bits */ | |
728 | writel(reg_addr + 4, pcie_index_offset); | |
729 | readl(pcie_index_offset); | |
730 | r |= ((u64)readl(pcie_data_offset) << 32); | |
731 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
732 | ||
733 | return r; | |
734 | } | |
735 | ||
736 | /** | |
737 | * amdgpu_device_indirect_wreg - write an indirect register address | |
738 | * | |
739 | * @adev: amdgpu_device pointer | |
740 | * @pcie_index: mmio register offset | |
741 | * @pcie_data: mmio register offset | |
742 | * @reg_addr: indirect register offset | |
743 | * @reg_data: indirect register data | |
744 | * | |
745 | */ | |
746 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
747 | u32 pcie_index, u32 pcie_data, | |
748 | u32 reg_addr, u32 reg_data) | |
749 | { | |
750 | unsigned long flags; | |
751 | void __iomem *pcie_index_offset; | |
752 | void __iomem *pcie_data_offset; | |
753 | ||
754 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
755 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
756 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
757 | ||
758 | writel(reg_addr, pcie_index_offset); | |
759 | readl(pcie_index_offset); | |
760 | writel(reg_data, pcie_data_offset); | |
761 | readl(pcie_data_offset); | |
762 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
763 | } | |
764 | ||
765 | /** | |
766 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
767 | * | |
768 | * @adev: amdgpu_device pointer | |
769 | * @pcie_index: mmio register offset | |
770 | * @pcie_data: mmio register offset | |
771 | * @reg_addr: indirect register offset | |
772 | * @reg_data: indirect register data | |
773 | * | |
774 | */ | |
775 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
776 | u32 pcie_index, u32 pcie_data, | |
777 | u32 reg_addr, u64 reg_data) | |
778 | { | |
779 | unsigned long flags; | |
780 | void __iomem *pcie_index_offset; | |
781 | void __iomem *pcie_data_offset; | |
782 | ||
783 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
784 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
785 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
786 | ||
787 | /* write low 32 bits */ | |
788 | writel(reg_addr, pcie_index_offset); | |
789 | readl(pcie_index_offset); | |
790 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
791 | readl(pcie_data_offset); | |
792 | /* write high 32 bits */ | |
793 | writel(reg_addr + 4, pcie_index_offset); | |
794 | readl(pcie_index_offset); | |
795 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
796 | readl(pcie_data_offset); | |
797 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
798 | } | |
799 | ||
d38ceaf9 AD |
800 | /** |
801 | * amdgpu_invalid_rreg - dummy reg read function | |
802 | * | |
982a820b | 803 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
804 | * @reg: offset of register |
805 | * | |
806 | * Dummy register read function. Used for register blocks | |
807 | * that certain asics don't have (all asics). | |
808 | * Returns the value in the register. | |
809 | */ | |
810 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
811 | { | |
812 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
813 | BUG(); | |
814 | return 0; | |
815 | } | |
816 | ||
817 | /** | |
818 | * amdgpu_invalid_wreg - dummy reg write function | |
819 | * | |
982a820b | 820 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
821 | * @reg: offset of register |
822 | * @v: value to write to the register | |
823 | * | |
824 | * Dummy register read function. Used for register blocks | |
825 | * that certain asics don't have (all asics). | |
826 | */ | |
827 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
828 | { | |
829 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
830 | reg, v); | |
831 | BUG(); | |
832 | } | |
833 | ||
4fa1c6a6 TZ |
834 | /** |
835 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
836 | * | |
982a820b | 837 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
838 | * @reg: offset of register |
839 | * | |
840 | * Dummy register read function. Used for register blocks | |
841 | * that certain asics don't have (all asics). | |
842 | * Returns the value in the register. | |
843 | */ | |
844 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
845 | { | |
846 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
847 | BUG(); | |
848 | return 0; | |
849 | } | |
850 | ||
851 | /** | |
852 | * amdgpu_invalid_wreg64 - dummy reg write function | |
853 | * | |
982a820b | 854 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
855 | * @reg: offset of register |
856 | * @v: value to write to the register | |
857 | * | |
858 | * Dummy register read function. Used for register blocks | |
859 | * that certain asics don't have (all asics). | |
860 | */ | |
861 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
862 | { | |
863 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
864 | reg, v); | |
865 | BUG(); | |
866 | } | |
867 | ||
d38ceaf9 AD |
868 | /** |
869 | * amdgpu_block_invalid_rreg - dummy reg read function | |
870 | * | |
982a820b | 871 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
872 | * @block: offset of instance |
873 | * @reg: offset of register | |
874 | * | |
875 | * Dummy register read function. Used for register blocks | |
876 | * that certain asics don't have (all asics). | |
877 | * Returns the value in the register. | |
878 | */ | |
879 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
880 | uint32_t block, uint32_t reg) | |
881 | { | |
882 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
883 | reg, block); | |
884 | BUG(); | |
885 | return 0; | |
886 | } | |
887 | ||
888 | /** | |
889 | * amdgpu_block_invalid_wreg - dummy reg write function | |
890 | * | |
982a820b | 891 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
892 | * @block: offset of instance |
893 | * @reg: offset of register | |
894 | * @v: value to write to the register | |
895 | * | |
896 | * Dummy register read function. Used for register blocks | |
897 | * that certain asics don't have (all asics). | |
898 | */ | |
899 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
900 | uint32_t block, | |
901 | uint32_t reg, uint32_t v) | |
902 | { | |
903 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
904 | reg, block, v); | |
905 | BUG(); | |
906 | } | |
907 | ||
4d2997ab AD |
908 | /** |
909 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
910 | * | |
982a820b | 911 | * @adev: amdgpu_device pointer |
4d2997ab AD |
912 | * |
913 | * Does any asic specific work and then calls atom asic init. | |
914 | */ | |
915 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
916 | { | |
917 | amdgpu_asic_pre_asic_init(adev); | |
918 | ||
85d1bcc6 HZ |
919 | if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) |
920 | return amdgpu_atomfirmware_asic_init(adev, true); | |
921 | else | |
922 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
4d2997ab AD |
923 | } |
924 | ||
e3ecdffa AD |
925 | /** |
926 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
927 | * | |
982a820b | 928 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
929 | * |
930 | * Allocates a scratch page of VRAM for use by various things in the | |
931 | * driver. | |
932 | */ | |
06ec9070 | 933 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 934 | { |
a4a02777 CK |
935 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
936 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
937 | &adev->vram_scratch.robj, | |
938 | &adev->vram_scratch.gpu_addr, | |
939 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
940 | } |
941 | ||
e3ecdffa AD |
942 | /** |
943 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
944 | * | |
982a820b | 945 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
946 | * |
947 | * Frees the VRAM scratch page. | |
948 | */ | |
06ec9070 | 949 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 950 | { |
078af1a3 | 951 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
952 | } |
953 | ||
954 | /** | |
9c3f2b54 | 955 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
956 | * |
957 | * @adev: amdgpu_device pointer | |
958 | * @registers: pointer to the register array | |
959 | * @array_size: size of the register array | |
960 | * | |
961 | * Programs an array or registers with and and or masks. | |
962 | * This is a helper for setting golden registers. | |
963 | */ | |
9c3f2b54 AD |
964 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
965 | const u32 *registers, | |
966 | const u32 array_size) | |
d38ceaf9 AD |
967 | { |
968 | u32 tmp, reg, and_mask, or_mask; | |
969 | int i; | |
970 | ||
971 | if (array_size % 3) | |
972 | return; | |
973 | ||
974 | for (i = 0; i < array_size; i +=3) { | |
975 | reg = registers[i + 0]; | |
976 | and_mask = registers[i + 1]; | |
977 | or_mask = registers[i + 2]; | |
978 | ||
979 | if (and_mask == 0xffffffff) { | |
980 | tmp = or_mask; | |
981 | } else { | |
982 | tmp = RREG32(reg); | |
983 | tmp &= ~and_mask; | |
e0d07657 HZ |
984 | if (adev->family >= AMDGPU_FAMILY_AI) |
985 | tmp |= (or_mask & and_mask); | |
986 | else | |
987 | tmp |= or_mask; | |
d38ceaf9 AD |
988 | } |
989 | WREG32(reg, tmp); | |
990 | } | |
991 | } | |
992 | ||
e3ecdffa AD |
993 | /** |
994 | * amdgpu_device_pci_config_reset - reset the GPU | |
995 | * | |
996 | * @adev: amdgpu_device pointer | |
997 | * | |
998 | * Resets the GPU using the pci config reset sequence. | |
999 | * Only applicable to asics prior to vega10. | |
1000 | */ | |
8111c387 | 1001 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
1002 | { |
1003 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
1004 | } | |
1005 | ||
af484df8 AD |
1006 | /** |
1007 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
1008 | * | |
1009 | * @adev: amdgpu_device pointer | |
1010 | * | |
1011 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
1012 | */ | |
1013 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
1014 | { | |
1015 | return pci_reset_function(adev->pdev); | |
1016 | } | |
1017 | ||
d38ceaf9 AD |
1018 | /* |
1019 | * GPU doorbell aperture helpers function. | |
1020 | */ | |
1021 | /** | |
06ec9070 | 1022 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
1023 | * |
1024 | * @adev: amdgpu_device pointer | |
1025 | * | |
1026 | * Init doorbell driver information (CIK) | |
1027 | * Returns 0 on success, error on failure. | |
1028 | */ | |
06ec9070 | 1029 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 1030 | { |
6585661d | 1031 | |
705e519e CK |
1032 | /* No doorbell on SI hardware generation */ |
1033 | if (adev->asic_type < CHIP_BONAIRE) { | |
1034 | adev->doorbell.base = 0; | |
1035 | adev->doorbell.size = 0; | |
1036 | adev->doorbell.num_doorbells = 0; | |
1037 | adev->doorbell.ptr = NULL; | |
1038 | return 0; | |
1039 | } | |
1040 | ||
d6895ad3 CK |
1041 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
1042 | return -EINVAL; | |
1043 | ||
22357775 AD |
1044 | amdgpu_asic_init_doorbell_index(adev); |
1045 | ||
d38ceaf9 AD |
1046 | /* doorbell bar mapping */ |
1047 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
1048 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
1049 | ||
de33a329 JX |
1050 | if (adev->enable_mes) { |
1051 | adev->doorbell.num_doorbells = | |
1052 | adev->doorbell.size / sizeof(u32); | |
1053 | } else { | |
1054 | adev->doorbell.num_doorbells = | |
1055 | min_t(u32, adev->doorbell.size / sizeof(u32), | |
1056 | adev->doorbell_index.max_assignment+1); | |
1057 | if (adev->doorbell.num_doorbells == 0) | |
1058 | return -EINVAL; | |
1059 | ||
1060 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA | |
1061 | * paging queue doorbell use the second page. The | |
1062 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
1063 | * doorbells are in the first page. So with paging queue enabled, | |
1064 | * the max num_doorbells should + 1 page (0x400 in dword) | |
1065 | */ | |
1066 | if (adev->asic_type >= CHIP_VEGA10) | |
1067 | adev->doorbell.num_doorbells += 0x400; | |
1068 | } | |
ec3db8a6 | 1069 | |
8972e5d2 CK |
1070 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
1071 | adev->doorbell.num_doorbells * | |
1072 | sizeof(u32)); | |
1073 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 1074 | return -ENOMEM; |
d38ceaf9 AD |
1075 | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | /** | |
06ec9070 | 1080 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
1081 | * |
1082 | * @adev: amdgpu_device pointer | |
1083 | * | |
1084 | * Tear down doorbell driver information (CIK) | |
1085 | */ | |
06ec9070 | 1086 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1087 | { |
1088 | iounmap(adev->doorbell.ptr); | |
1089 | adev->doorbell.ptr = NULL; | |
1090 | } | |
1091 | ||
22cb0164 | 1092 | |
d38ceaf9 AD |
1093 | |
1094 | /* | |
06ec9070 | 1095 | * amdgpu_device_wb_*() |
455a7bc2 | 1096 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1097 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1098 | */ |
1099 | ||
1100 | /** | |
06ec9070 | 1101 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1102 | * |
1103 | * @adev: amdgpu_device pointer | |
1104 | * | |
1105 | * Disables Writeback and frees the Writeback memory (all asics). | |
1106 | * Used at driver shutdown. | |
1107 | */ | |
06ec9070 | 1108 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1109 | { |
1110 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1111 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1112 | &adev->wb.gpu_addr, | |
1113 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1114 | adev->wb.wb_obj = NULL; |
1115 | } | |
1116 | } | |
1117 | ||
1118 | /** | |
03f2abb0 | 1119 | * amdgpu_device_wb_init - Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1120 | * |
1121 | * @adev: amdgpu_device pointer | |
1122 | * | |
455a7bc2 | 1123 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1124 | * Used at driver startup. |
1125 | * Returns 0 on success or an -error on failure. | |
1126 | */ | |
06ec9070 | 1127 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1128 | { |
1129 | int r; | |
1130 | ||
1131 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1132 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1133 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1134 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1135 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1136 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1137 | if (r) { |
1138 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1139 | return r; | |
1140 | } | |
d38ceaf9 AD |
1141 | |
1142 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1143 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1144 | ||
1145 | /* clear wb memory */ | |
73469585 | 1146 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1147 | } |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | /** | |
131b4b36 | 1153 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1154 | * |
1155 | * @adev: amdgpu_device pointer | |
1156 | * @wb: wb index | |
1157 | * | |
1158 | * Allocate a wb slot for use by the driver (all asics). | |
1159 | * Returns 0 on success or -EINVAL on failure. | |
1160 | */ | |
131b4b36 | 1161 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1162 | { |
1163 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1164 | |
97407b63 | 1165 | if (offset < adev->wb.num_wb) { |
7014285a | 1166 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1167 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1168 | return 0; |
1169 | } else { | |
1170 | return -EINVAL; | |
1171 | } | |
1172 | } | |
1173 | ||
d38ceaf9 | 1174 | /** |
131b4b36 | 1175 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1176 | * |
1177 | * @adev: amdgpu_device pointer | |
1178 | * @wb: wb index | |
1179 | * | |
1180 | * Free a wb slot allocated for use by the driver (all asics) | |
1181 | */ | |
131b4b36 | 1182 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1183 | { |
73469585 | 1184 | wb >>= 3; |
d38ceaf9 | 1185 | if (wb < adev->wb.num_wb) |
73469585 | 1186 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1187 | } |
1188 | ||
d6895ad3 CK |
1189 | /** |
1190 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1191 | * | |
1192 | * @adev: amdgpu_device pointer | |
1193 | * | |
1194 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1195 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1196 | * driver loading by returning -ENODEV. | |
1197 | */ | |
1198 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1199 | { | |
453f617a | 1200 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1201 | struct pci_bus *root; |
1202 | struct resource *res; | |
1203 | unsigned i; | |
d6895ad3 CK |
1204 | u16 cmd; |
1205 | int r; | |
1206 | ||
0c03b912 | 1207 | /* Bypass for VF */ |
1208 | if (amdgpu_sriov_vf(adev)) | |
1209 | return 0; | |
1210 | ||
b7221f2b AD |
1211 | /* skip if the bios has already enabled large BAR */ |
1212 | if (adev->gmc.real_vram_size && | |
1213 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1214 | return 0; | |
1215 | ||
31b8adab CK |
1216 | /* Check if the root BUS has 64bit memory resources */ |
1217 | root = adev->pdev->bus; | |
1218 | while (root->parent) | |
1219 | root = root->parent; | |
1220 | ||
1221 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1222 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1223 | res->start > 0x100000000ull) |
1224 | break; | |
1225 | } | |
1226 | ||
1227 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1228 | if (!res) | |
1229 | return 0; | |
1230 | ||
453f617a ND |
1231 | /* Limit the BAR size to what is available */ |
1232 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1233 | rbar_size); | |
1234 | ||
d6895ad3 CK |
1235 | /* Disable memory decoding while we change the BAR addresses and size */ |
1236 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1237 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1238 | cmd & ~PCI_COMMAND_MEMORY); | |
1239 | ||
1240 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 1241 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
1242 | if (adev->asic_type >= CHIP_BONAIRE) |
1243 | pci_release_resource(adev->pdev, 2); | |
1244 | ||
1245 | pci_release_resource(adev->pdev, 0); | |
1246 | ||
1247 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1248 | if (r == -ENOSPC) | |
1249 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1250 | else if (r && r != -ENOTSUPP) | |
1251 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1252 | ||
1253 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1254 | ||
1255 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1256 | * using the device. | |
1257 | */ | |
06ec9070 | 1258 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
1259 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1260 | return -ENODEV; | |
1261 | ||
1262 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1263 | ||
1264 | return 0; | |
1265 | } | |
a05502e5 | 1266 | |
d38ceaf9 AD |
1267 | /* |
1268 | * GPU helpers function. | |
1269 | */ | |
1270 | /** | |
39c640c0 | 1271 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1272 | * |
1273 | * @adev: amdgpu_device pointer | |
1274 | * | |
c836fec5 JQ |
1275 | * Check if the asic has been initialized (all asics) at driver startup |
1276 | * or post is needed if hw reset is performed. | |
1277 | * Returns true if need or false if not. | |
d38ceaf9 | 1278 | */ |
39c640c0 | 1279 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1280 | { |
1281 | uint32_t reg; | |
1282 | ||
bec86378 ML |
1283 | if (amdgpu_sriov_vf(adev)) |
1284 | return false; | |
1285 | ||
1286 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1287 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1288 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1289 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1290 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1291 | */ |
1292 | if (adev->asic_type == CHIP_FIJI) { | |
1293 | int err; | |
1294 | uint32_t fw_ver; | |
1295 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1296 | /* force vPost if error occured */ | |
1297 | if (err) | |
1298 | return true; | |
1299 | ||
1300 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1301 | if (fw_ver < 0x00160e00) |
1302 | return true; | |
bec86378 | 1303 | } |
bec86378 | 1304 | } |
91fe77eb | 1305 | |
e3c1b071 | 1306 | /* Don't post if we need to reset whole hive on init */ |
1307 | if (adev->gmc.xgmi.pending_reset) | |
1308 | return false; | |
1309 | ||
91fe77eb | 1310 | if (adev->has_hw_reset) { |
1311 | adev->has_hw_reset = false; | |
1312 | return true; | |
1313 | } | |
1314 | ||
1315 | /* bios scratch used on CIK+ */ | |
1316 | if (adev->asic_type >= CHIP_BONAIRE) | |
1317 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1318 | ||
1319 | /* check MEM_SIZE for older asics */ | |
1320 | reg = amdgpu_asic_get_config_memsize(adev); | |
1321 | ||
1322 | if ((reg != 0) && (reg != 0xffffffff)) | |
1323 | return false; | |
1324 | ||
1325 | return true; | |
bec86378 ML |
1326 | } |
1327 | ||
0ab5d711 ML |
1328 | /** |
1329 | * amdgpu_device_should_use_aspm - check if the device should program ASPM | |
1330 | * | |
1331 | * @adev: amdgpu_device pointer | |
1332 | * | |
1333 | * Confirm whether the module parameter and pcie bridge agree that ASPM should | |
1334 | * be set for this device. | |
1335 | * | |
1336 | * Returns true if it should be used or false if not. | |
1337 | */ | |
1338 | bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) | |
1339 | { | |
1340 | switch (amdgpu_aspm) { | |
1341 | case -1: | |
1342 | break; | |
1343 | case 0: | |
1344 | return false; | |
1345 | case 1: | |
1346 | return true; | |
1347 | default: | |
1348 | return false; | |
1349 | } | |
1350 | return pcie_aspm_enabled(adev->pdev); | |
1351 | } | |
1352 | ||
d38ceaf9 AD |
1353 | /* if we get transitioned to only one device, take VGA back */ |
1354 | /** | |
06ec9070 | 1355 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 | 1356 | * |
bf44e8ce | 1357 | * @pdev: PCI device pointer |
d38ceaf9 AD |
1358 | * @state: enable/disable vga decode |
1359 | * | |
1360 | * Enable/disable vga decode (all asics). | |
1361 | * Returns VGA resource flags. | |
1362 | */ | |
bf44e8ce CH |
1363 | static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, |
1364 | bool state) | |
d38ceaf9 | 1365 | { |
bf44e8ce | 1366 | struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); |
d38ceaf9 AD |
1367 | amdgpu_asic_set_vga_state(adev, state); |
1368 | if (state) | |
1369 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1370 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1371 | else | |
1372 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1373 | } | |
1374 | ||
e3ecdffa AD |
1375 | /** |
1376 | * amdgpu_device_check_block_size - validate the vm block size | |
1377 | * | |
1378 | * @adev: amdgpu_device pointer | |
1379 | * | |
1380 | * Validates the vm block size specified via module parameter. | |
1381 | * The vm block size defines number of bits in page table versus page directory, | |
1382 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1383 | * page table and the remaining bits are in the page directory. | |
1384 | */ | |
06ec9070 | 1385 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1386 | { |
1387 | /* defines number of bits in page table versus page directory, | |
1388 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1389 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1390 | if (amdgpu_vm_block_size == -1) |
1391 | return; | |
a1adf8be | 1392 | |
bab4fee7 | 1393 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1394 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1395 | amdgpu_vm_block_size); | |
97489129 | 1396 | amdgpu_vm_block_size = -1; |
a1adf8be | 1397 | } |
a1adf8be CZ |
1398 | } |
1399 | ||
e3ecdffa AD |
1400 | /** |
1401 | * amdgpu_device_check_vm_size - validate the vm size | |
1402 | * | |
1403 | * @adev: amdgpu_device pointer | |
1404 | * | |
1405 | * Validates the vm size in GB specified via module parameter. | |
1406 | * The VM size is the size of the GPU virtual memory space in GB. | |
1407 | */ | |
06ec9070 | 1408 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1409 | { |
64dab074 AD |
1410 | /* no need to check the default value */ |
1411 | if (amdgpu_vm_size == -1) | |
1412 | return; | |
1413 | ||
83ca145d ZJ |
1414 | if (amdgpu_vm_size < 1) { |
1415 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1416 | amdgpu_vm_size); | |
f3368128 | 1417 | amdgpu_vm_size = -1; |
83ca145d | 1418 | } |
83ca145d ZJ |
1419 | } |
1420 | ||
7951e376 RZ |
1421 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1422 | { | |
1423 | struct sysinfo si; | |
a9d4fe2f | 1424 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1425 | uint64_t total_memory; |
1426 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1427 | uint64_t dram_size_three_GB = 0xB8000000; | |
1428 | ||
1429 | if (amdgpu_smu_memory_pool_size == 0) | |
1430 | return; | |
1431 | ||
1432 | if (!is_os_64) { | |
1433 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1434 | goto def_value; | |
1435 | } | |
1436 | si_meminfo(&si); | |
1437 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1438 | ||
1439 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1440 | (amdgpu_smu_memory_pool_size == 2)) { | |
1441 | if (total_memory < dram_size_three_GB) | |
1442 | goto def_value1; | |
1443 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1444 | (amdgpu_smu_memory_pool_size == 8)) { | |
1445 | if (total_memory < dram_size_seven_GB) | |
1446 | goto def_value1; | |
1447 | } else { | |
1448 | DRM_WARN("Smu memory pool size not supported\n"); | |
1449 | goto def_value; | |
1450 | } | |
1451 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1452 | ||
1453 | return; | |
1454 | ||
1455 | def_value1: | |
1456 | DRM_WARN("No enough system memory\n"); | |
1457 | def_value: | |
1458 | adev->pm.smu_prv_buffer_size = 0; | |
1459 | } | |
1460 | ||
9f6a7857 HR |
1461 | static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) |
1462 | { | |
1463 | if (!(adev->flags & AMD_IS_APU) || | |
1464 | adev->asic_type < CHIP_RAVEN) | |
1465 | return 0; | |
1466 | ||
1467 | switch (adev->asic_type) { | |
1468 | case CHIP_RAVEN: | |
1469 | if (adev->pdev->device == 0x15dd) | |
1470 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1471 | if (adev->pdev->device == 0x15d8) | |
1472 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
1473 | break; | |
1474 | case CHIP_RENOIR: | |
1475 | if ((adev->pdev->device == 0x1636) || | |
1476 | (adev->pdev->device == 0x164c)) | |
1477 | adev->apu_flags |= AMD_APU_IS_RENOIR; | |
1478 | else | |
1479 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1480 | break; | |
1481 | case CHIP_VANGOGH: | |
1482 | adev->apu_flags |= AMD_APU_IS_VANGOGH; | |
1483 | break; | |
1484 | case CHIP_YELLOW_CARP: | |
1485 | break; | |
d0f56dc2 | 1486 | case CHIP_CYAN_SKILLFISH: |
dfcc3e8c AD |
1487 | if ((adev->pdev->device == 0x13FE) || |
1488 | (adev->pdev->device == 0x143F)) | |
d0f56dc2 TZ |
1489 | adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2; |
1490 | break; | |
9f6a7857 | 1491 | default: |
4eaf21b7 | 1492 | break; |
9f6a7857 HR |
1493 | } |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
d38ceaf9 | 1498 | /** |
06ec9070 | 1499 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1500 | * |
1501 | * @adev: amdgpu_device pointer | |
1502 | * | |
1503 | * Validates certain module parameters and updates | |
1504 | * the associated values used by the driver (all asics). | |
1505 | */ | |
912dfc84 | 1506 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1507 | { |
5b011235 CZ |
1508 | if (amdgpu_sched_jobs < 4) { |
1509 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1510 | amdgpu_sched_jobs); | |
1511 | amdgpu_sched_jobs = 4; | |
76117507 | 1512 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1513 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1514 | amdgpu_sched_jobs); | |
1515 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1516 | } | |
d38ceaf9 | 1517 | |
83e74db6 | 1518 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1519 | /* gart size must be greater or equal to 32M */ |
1520 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1521 | amdgpu_gart_size); | |
83e74db6 | 1522 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1523 | } |
1524 | ||
36d38372 | 1525 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1526 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1527 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1528 | amdgpu_gtt_size); | |
1529 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1530 | } |
1531 | ||
d07f14be RH |
1532 | /* valid range is between 4 and 9 inclusive */ |
1533 | if (amdgpu_vm_fragment_size != -1 && | |
1534 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1535 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1536 | amdgpu_vm_fragment_size = -1; | |
1537 | } | |
1538 | ||
5d5bd5e3 KW |
1539 | if (amdgpu_sched_hw_submission < 2) { |
1540 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1541 | amdgpu_sched_hw_submission); | |
1542 | amdgpu_sched_hw_submission = 2; | |
1543 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1544 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1545 | amdgpu_sched_hw_submission); | |
1546 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1547 | } | |
1548 | ||
2656fd23 AG |
1549 | if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) { |
1550 | dev_warn(adev->dev, "invalid option for reset method, reverting to default\n"); | |
1551 | amdgpu_reset_method = -1; | |
1552 | } | |
1553 | ||
7951e376 RZ |
1554 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1555 | ||
06ec9070 | 1556 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1557 | |
06ec9070 | 1558 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1559 | |
19aede77 | 1560 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1561 | |
e3c00faa | 1562 | return 0; |
d38ceaf9 AD |
1563 | } |
1564 | ||
1565 | /** | |
1566 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1567 | * | |
1568 | * @pdev: pci dev pointer | |
1694467b | 1569 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1570 | * |
1571 | * Callback for the switcheroo driver. Suspends or resumes the | |
1572 | * the asics before or after it is powered up using ACPI methods. | |
1573 | */ | |
8aba21b7 LT |
1574 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1575 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1576 | { |
1577 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1578 | int r; |
d38ceaf9 | 1579 | |
b98c6299 | 1580 | if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1581 | return; |
1582 | ||
1583 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1584 | pr_info("switched on\n"); |
d38ceaf9 AD |
1585 | /* don't suspend or resume card normally */ |
1586 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1587 | ||
8f66090b TZ |
1588 | pci_set_power_state(pdev, PCI_D0); |
1589 | amdgpu_device_load_pci_state(pdev); | |
1590 | r = pci_enable_device(pdev); | |
de185019 AD |
1591 | if (r) |
1592 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1593 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1594 | |
d38ceaf9 | 1595 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1596 | } else { |
dd4fa6c1 | 1597 | pr_info("switched off\n"); |
d38ceaf9 | 1598 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
de185019 | 1599 | amdgpu_device_suspend(dev, true); |
8f66090b | 1600 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1601 | /* Shut down the device */ |
8f66090b TZ |
1602 | pci_disable_device(pdev); |
1603 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1604 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1605 | } | |
1606 | } | |
1607 | ||
1608 | /** | |
1609 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1610 | * | |
1611 | * @pdev: pci dev pointer | |
1612 | * | |
1613 | * Callback for the switcheroo driver. Check of the switcheroo | |
1614 | * state can be changed. | |
1615 | * Returns true if the state can be changed, false if not. | |
1616 | */ | |
1617 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1618 | { | |
1619 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1620 | ||
1621 | /* | |
1622 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1623 | * locking inversion with the driver load path. And the access here is | |
1624 | * completely racy anyway. So don't bother with locking for now. | |
1625 | */ | |
7e13ad89 | 1626 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1627 | } |
1628 | ||
1629 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1630 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1631 | .reprobe = NULL, | |
1632 | .can_switch = amdgpu_switcheroo_can_switch, | |
1633 | }; | |
1634 | ||
e3ecdffa AD |
1635 | /** |
1636 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1637 | * | |
87e3f136 | 1638 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1639 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1640 | * @state: clockgating state (gate or ungate) | |
1641 | * | |
1642 | * Sets the requested clockgating state for all instances of | |
1643 | * the hardware IP specified. | |
1644 | * Returns the error code from the last instance. | |
1645 | */ | |
43fa561f | 1646 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1647 | enum amd_ip_block_type block_type, |
1648 | enum amd_clockgating_state state) | |
d38ceaf9 | 1649 | { |
43fa561f | 1650 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1651 | int i, r = 0; |
1652 | ||
1653 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1654 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1655 | continue; |
c722865a RZ |
1656 | if (adev->ip_blocks[i].version->type != block_type) |
1657 | continue; | |
1658 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1659 | continue; | |
1660 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1661 | (void *)adev, state); | |
1662 | if (r) | |
1663 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1664 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1665 | } |
1666 | return r; | |
1667 | } | |
1668 | ||
e3ecdffa AD |
1669 | /** |
1670 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1671 | * | |
87e3f136 | 1672 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1673 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1674 | * @state: powergating state (gate or ungate) | |
1675 | * | |
1676 | * Sets the requested powergating state for all instances of | |
1677 | * the hardware IP specified. | |
1678 | * Returns the error code from the last instance. | |
1679 | */ | |
43fa561f | 1680 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1681 | enum amd_ip_block_type block_type, |
1682 | enum amd_powergating_state state) | |
d38ceaf9 | 1683 | { |
43fa561f | 1684 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1685 | int i, r = 0; |
1686 | ||
1687 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1688 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1689 | continue; |
c722865a RZ |
1690 | if (adev->ip_blocks[i].version->type != block_type) |
1691 | continue; | |
1692 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1693 | continue; | |
1694 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1695 | (void *)adev, state); | |
1696 | if (r) | |
1697 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1698 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1699 | } |
1700 | return r; | |
1701 | } | |
1702 | ||
e3ecdffa AD |
1703 | /** |
1704 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1705 | * | |
1706 | * @adev: amdgpu_device pointer | |
1707 | * @flags: clockgating feature flags | |
1708 | * | |
1709 | * Walks the list of IPs on the device and updates the clockgating | |
1710 | * flags for each IP. | |
1711 | * Updates @flags with the feature flags for each hardware IP where | |
1712 | * clockgating is enabled. | |
1713 | */ | |
2990a1fc | 1714 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
25faeddc | 1715 | u64 *flags) |
6cb2d4e4 HR |
1716 | { |
1717 | int i; | |
1718 | ||
1719 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1720 | if (!adev->ip_blocks[i].status.valid) | |
1721 | continue; | |
1722 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1723 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1724 | } | |
1725 | } | |
1726 | ||
e3ecdffa AD |
1727 | /** |
1728 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1729 | * | |
1730 | * @adev: amdgpu_device pointer | |
1731 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1732 | * | |
1733 | * Waits for the request hardware IP to be idle. | |
1734 | * Returns 0 for success or a negative error code on failure. | |
1735 | */ | |
2990a1fc AD |
1736 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1737 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1738 | { |
1739 | int i, r; | |
1740 | ||
1741 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1742 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1743 | continue; |
a1255107 AD |
1744 | if (adev->ip_blocks[i].version->type == block_type) { |
1745 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1746 | if (r) |
1747 | return r; | |
1748 | break; | |
1749 | } | |
1750 | } | |
1751 | return 0; | |
1752 | ||
1753 | } | |
1754 | ||
e3ecdffa AD |
1755 | /** |
1756 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1757 | * | |
1758 | * @adev: amdgpu_device pointer | |
1759 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1760 | * | |
1761 | * Check if the hardware IP is idle or not. | |
1762 | * Returns true if it the IP is idle, false if not. | |
1763 | */ | |
2990a1fc AD |
1764 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1765 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1766 | { |
1767 | int i; | |
1768 | ||
1769 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1770 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1771 | continue; |
a1255107 AD |
1772 | if (adev->ip_blocks[i].version->type == block_type) |
1773 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1774 | } |
1775 | return true; | |
1776 | ||
1777 | } | |
1778 | ||
e3ecdffa AD |
1779 | /** |
1780 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1781 | * | |
1782 | * @adev: amdgpu_device pointer | |
87e3f136 | 1783 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1784 | * |
1785 | * Returns a pointer to the hardware IP block structure | |
1786 | * if it exists for the asic, otherwise NULL. | |
1787 | */ | |
2990a1fc AD |
1788 | struct amdgpu_ip_block * |
1789 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1790 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1791 | { |
1792 | int i; | |
1793 | ||
1794 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1795 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1796 | return &adev->ip_blocks[i]; |
1797 | ||
1798 | return NULL; | |
1799 | } | |
1800 | ||
1801 | /** | |
2990a1fc | 1802 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1803 | * |
1804 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1805 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1806 | * @major: major version |
1807 | * @minor: minor version | |
1808 | * | |
1809 | * return 0 if equal or greater | |
1810 | * return 1 if smaller or the ip_block doesn't exist | |
1811 | */ | |
2990a1fc AD |
1812 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1813 | enum amd_ip_block_type type, | |
1814 | u32 major, u32 minor) | |
d38ceaf9 | 1815 | { |
2990a1fc | 1816 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1817 | |
a1255107 AD |
1818 | if (ip_block && ((ip_block->version->major > major) || |
1819 | ((ip_block->version->major == major) && | |
1820 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1821 | return 0; |
1822 | ||
1823 | return 1; | |
1824 | } | |
1825 | ||
a1255107 | 1826 | /** |
2990a1fc | 1827 | * amdgpu_device_ip_block_add |
a1255107 AD |
1828 | * |
1829 | * @adev: amdgpu_device pointer | |
1830 | * @ip_block_version: pointer to the IP to add | |
1831 | * | |
1832 | * Adds the IP block driver information to the collection of IPs | |
1833 | * on the asic. | |
1834 | */ | |
2990a1fc AD |
1835 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1836 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1837 | { |
1838 | if (!ip_block_version) | |
1839 | return -EINVAL; | |
1840 | ||
7bd939d0 LG |
1841 | switch (ip_block_version->type) { |
1842 | case AMD_IP_BLOCK_TYPE_VCN: | |
1843 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) | |
1844 | return 0; | |
1845 | break; | |
1846 | case AMD_IP_BLOCK_TYPE_JPEG: | |
1847 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) | |
1848 | return 0; | |
1849 | break; | |
1850 | default: | |
1851 | break; | |
1852 | } | |
1853 | ||
e966a725 | 1854 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1855 | ip_block_version->funcs->name); |
1856 | ||
a1255107 AD |
1857 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1858 | ||
1859 | return 0; | |
1860 | } | |
1861 | ||
e3ecdffa AD |
1862 | /** |
1863 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1864 | * | |
1865 | * @adev: amdgpu_device pointer | |
1866 | * | |
1867 | * Enabled the virtual display feature if the user has enabled it via | |
1868 | * the module parameter virtual_display. This feature provides a virtual | |
1869 | * display hardware on headless boards or in virtualized environments. | |
1870 | * This function parses and validates the configuration string specified by | |
1871 | * the user and configues the virtual display configuration (number of | |
1872 | * virtual connectors, crtcs, etc.) specified. | |
1873 | */ | |
483ef985 | 1874 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1875 | { |
1876 | adev->enable_virtual_display = false; | |
1877 | ||
1878 | if (amdgpu_virtual_display) { | |
8f66090b | 1879 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 1880 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1881 | |
1882 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1883 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1884 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1885 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1886 | if (!strcmp("all", pciaddname) |
1887 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1888 | long num_crtc; |
1889 | int res = -1; | |
1890 | ||
9accf2fd | 1891 | adev->enable_virtual_display = true; |
0f66356d ED |
1892 | |
1893 | if (pciaddname_tmp) | |
1894 | res = kstrtol(pciaddname_tmp, 10, | |
1895 | &num_crtc); | |
1896 | ||
1897 | if (!res) { | |
1898 | if (num_crtc < 1) | |
1899 | num_crtc = 1; | |
1900 | if (num_crtc > 6) | |
1901 | num_crtc = 6; | |
1902 | adev->mode_info.num_crtc = num_crtc; | |
1903 | } else { | |
1904 | adev->mode_info.num_crtc = 1; | |
1905 | } | |
9accf2fd ED |
1906 | break; |
1907 | } | |
1908 | } | |
1909 | ||
0f66356d ED |
1910 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1911 | amdgpu_virtual_display, pci_address_name, | |
1912 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1913 | |
1914 | kfree(pciaddstr); | |
1915 | } | |
1916 | } | |
1917 | ||
e3ecdffa AD |
1918 | /** |
1919 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1920 | * | |
1921 | * @adev: amdgpu_device pointer | |
1922 | * | |
1923 | * Parses the asic configuration parameters specified in the gpu info | |
1924 | * firmware and makes them availale to the driver for use in configuring | |
1925 | * the asic. | |
1926 | * Returns 0 on success, -EINVAL on failure. | |
1927 | */ | |
e2a75f88 AD |
1928 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1929 | { | |
e2a75f88 | 1930 | const char *chip_name; |
c0a43457 | 1931 | char fw_name[40]; |
e2a75f88 AD |
1932 | int err; |
1933 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1934 | ||
ab4fe3e1 HR |
1935 | adev->firmware.gpu_info_fw = NULL; |
1936 | ||
72de33f8 | 1937 | if (adev->mman.discovery_bin) { |
cc375d8c TY |
1938 | /* |
1939 | * FIXME: The bounding box is still needed by Navi12, so | |
e24d0e91 | 1940 | * temporarily read it from gpu_info firmware. Should be dropped |
cc375d8c TY |
1941 | * when DAL no longer needs it. |
1942 | */ | |
1943 | if (adev->asic_type != CHIP_NAVI12) | |
1944 | return 0; | |
258620d0 AD |
1945 | } |
1946 | ||
e2a75f88 | 1947 | switch (adev->asic_type) { |
e2a75f88 AD |
1948 | default: |
1949 | return 0; | |
1950 | case CHIP_VEGA10: | |
1951 | chip_name = "vega10"; | |
1952 | break; | |
3f76dced AD |
1953 | case CHIP_VEGA12: |
1954 | chip_name = "vega12"; | |
1955 | break; | |
2d2e5e7e | 1956 | case CHIP_RAVEN: |
54f78a76 | 1957 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1958 | chip_name = "raven2"; |
54f78a76 | 1959 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1960 | chip_name = "picasso"; |
54c4d17e FX |
1961 | else |
1962 | chip_name = "raven"; | |
2d2e5e7e | 1963 | break; |
65e60f6e LM |
1964 | case CHIP_ARCTURUS: |
1965 | chip_name = "arcturus"; | |
1966 | break; | |
42b325e5 XY |
1967 | case CHIP_NAVI12: |
1968 | chip_name = "navi12"; | |
1969 | break; | |
e2a75f88 AD |
1970 | } |
1971 | ||
1972 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1973 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1974 | if (err) { |
1975 | dev_err(adev->dev, | |
1976 | "Failed to load gpu_info firmware \"%s\"\n", | |
1977 | fw_name); | |
1978 | goto out; | |
1979 | } | |
ab4fe3e1 | 1980 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1981 | if (err) { |
1982 | dev_err(adev->dev, | |
1983 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1984 | fw_name); | |
1985 | goto out; | |
1986 | } | |
1987 | ||
ab4fe3e1 | 1988 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1989 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1990 | ||
1991 | switch (hdr->version_major) { | |
1992 | case 1: | |
1993 | { | |
1994 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1995 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1996 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1997 | ||
cc375d8c TY |
1998 | /* |
1999 | * Should be droped when DAL no longer needs it. | |
2000 | */ | |
2001 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
2002 | goto parse_soc_bounding_box; |
2003 | ||
b5ab16bf AD |
2004 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
2005 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
2006 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
2007 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 2008 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
2009 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
2010 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
2011 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
2012 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
2013 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 2014 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
2015 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
2016 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
2017 | adev->gfx.cu_info.max_waves_per_simd = |
2018 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
2019 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
2020 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
2021 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 2022 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
2023 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
2024 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
2025 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2026 | adev->gfx.config.num_sc_per_sh = | |
2027 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
2028 | adev->gfx.config.num_packer_per_sc = | |
2029 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
2030 | } | |
ec51d3fa XY |
2031 | |
2032 | parse_soc_bounding_box: | |
ec51d3fa XY |
2033 | /* |
2034 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 2035 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 2036 | */ |
48321c3d HW |
2037 | if (hdr->version_minor == 2) { |
2038 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
2039 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
2040 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2041 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
2042 | } | |
e2a75f88 AD |
2043 | break; |
2044 | } | |
2045 | default: | |
2046 | dev_err(adev->dev, | |
2047 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
2048 | err = -EINVAL; | |
2049 | goto out; | |
2050 | } | |
2051 | out: | |
e2a75f88 AD |
2052 | return err; |
2053 | } | |
2054 | ||
e3ecdffa AD |
2055 | /** |
2056 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
2057 | * | |
2058 | * @adev: amdgpu_device pointer | |
2059 | * | |
2060 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
2061 | * up each asic are discovered each IP's early_init callback is run. This | |
2062 | * is the first stage in initializing the asic. | |
2063 | * Returns 0 on success, negative error code on failure. | |
2064 | */ | |
06ec9070 | 2065 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 2066 | { |
901e2be2 AD |
2067 | struct drm_device *dev = adev_to_drm(adev); |
2068 | struct pci_dev *parent; | |
aaa36a97 | 2069 | int i, r; |
d38ceaf9 | 2070 | |
483ef985 | 2071 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 2072 | |
00a979f3 | 2073 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 2074 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
2075 | if (r) |
2076 | return r; | |
00a979f3 WS |
2077 | } |
2078 | ||
d38ceaf9 | 2079 | switch (adev->asic_type) { |
33f34802 KW |
2080 | #ifdef CONFIG_DRM_AMDGPU_SI |
2081 | case CHIP_VERDE: | |
2082 | case CHIP_TAHITI: | |
2083 | case CHIP_PITCAIRN: | |
2084 | case CHIP_OLAND: | |
2085 | case CHIP_HAINAN: | |
295d0daf | 2086 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
2087 | r = si_set_ip_blocks(adev); |
2088 | if (r) | |
2089 | return r; | |
2090 | break; | |
2091 | #endif | |
a2e73f56 AD |
2092 | #ifdef CONFIG_DRM_AMDGPU_CIK |
2093 | case CHIP_BONAIRE: | |
2094 | case CHIP_HAWAII: | |
2095 | case CHIP_KAVERI: | |
2096 | case CHIP_KABINI: | |
2097 | case CHIP_MULLINS: | |
e1ad2d53 | 2098 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 2099 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
2100 | else |
2101 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
2102 | |
2103 | r = cik_set_ip_blocks(adev); | |
2104 | if (r) | |
2105 | return r; | |
2106 | break; | |
2107 | #endif | |
da87c30b AD |
2108 | case CHIP_TOPAZ: |
2109 | case CHIP_TONGA: | |
2110 | case CHIP_FIJI: | |
2111 | case CHIP_POLARIS10: | |
2112 | case CHIP_POLARIS11: | |
2113 | case CHIP_POLARIS12: | |
2114 | case CHIP_VEGAM: | |
2115 | case CHIP_CARRIZO: | |
2116 | case CHIP_STONEY: | |
2117 | if (adev->flags & AMD_IS_APU) | |
2118 | adev->family = AMDGPU_FAMILY_CZ; | |
2119 | else | |
2120 | adev->family = AMDGPU_FAMILY_VI; | |
2121 | ||
2122 | r = vi_set_ip_blocks(adev); | |
2123 | if (r) | |
2124 | return r; | |
2125 | break; | |
d38ceaf9 | 2126 | default: |
63352b7f AD |
2127 | r = amdgpu_discovery_set_ip_blocks(adev); |
2128 | if (r) | |
2129 | return r; | |
2130 | break; | |
d38ceaf9 AD |
2131 | } |
2132 | ||
901e2be2 AD |
2133 | if (amdgpu_has_atpx() && |
2134 | (amdgpu_is_atpx_hybrid() || | |
2135 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
2136 | ((adev->flags & AMD_IS_APU) == 0) && | |
2137 | !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) | |
2138 | adev->flags |= AMD_IS_PX; | |
2139 | ||
85ac2021 AD |
2140 | if (!(adev->flags & AMD_IS_APU)) { |
2141 | parent = pci_upstream_bridge(adev->pdev); | |
2142 | adev->has_pr3 = parent ? pci_pr3_present(parent) : false; | |
2143 | } | |
901e2be2 | 2144 | |
c004d44e | 2145 | amdgpu_amdkfd_device_probe(adev); |
1884734a | 2146 | |
3b94fb10 | 2147 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2148 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2149 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2150 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2151 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
00f54b97 | 2152 | |
d38ceaf9 AD |
2153 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2154 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
2155 | DRM_ERROR("disabled ip block: %d <%s>\n", |
2156 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 2157 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2158 | } else { |
a1255107 AD |
2159 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2160 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2161 | if (r == -ENOENT) { |
a1255107 | 2162 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2163 | } else if (r) { |
a1255107 AD |
2164 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2165 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2166 | return r; |
2c1a2784 | 2167 | } else { |
a1255107 | 2168 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2169 | } |
974e6b64 | 2170 | } else { |
a1255107 | 2171 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2172 | } |
d38ceaf9 | 2173 | } |
21a249ca AD |
2174 | /* get the vbios after the asic_funcs are set up */ |
2175 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2176 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2177 | if (r) | |
2178 | return r; | |
2179 | ||
21a249ca AD |
2180 | /* Read BIOS */ |
2181 | if (!amdgpu_get_bios(adev)) | |
2182 | return -EINVAL; | |
2183 | ||
2184 | r = amdgpu_atombios_init(adev); | |
2185 | if (r) { | |
2186 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2187 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2188 | return r; | |
2189 | } | |
77eabc6f PJZ |
2190 | |
2191 | /*get pf2vf msg info at it's earliest time*/ | |
2192 | if (amdgpu_sriov_vf(adev)) | |
2193 | amdgpu_virt_init_data_exchange(adev); | |
2194 | ||
21a249ca | 2195 | } |
d38ceaf9 AD |
2196 | } |
2197 | ||
395d1fb9 NH |
2198 | adev->cg_flags &= amdgpu_cg_mask; |
2199 | adev->pg_flags &= amdgpu_pg_mask; | |
2200 | ||
d38ceaf9 AD |
2201 | return 0; |
2202 | } | |
2203 | ||
0a4f2520 RZ |
2204 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2205 | { | |
2206 | int i, r; | |
2207 | ||
2208 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2209 | if (!adev->ip_blocks[i].status.sw) | |
2210 | continue; | |
2211 | if (adev->ip_blocks[i].status.hw) | |
2212 | continue; | |
2213 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2214 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2215 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2216 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2217 | if (r) { | |
2218 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2219 | adev->ip_blocks[i].version->funcs->name, r); | |
2220 | return r; | |
2221 | } | |
2222 | adev->ip_blocks[i].status.hw = true; | |
2223 | } | |
2224 | } | |
2225 | ||
2226 | return 0; | |
2227 | } | |
2228 | ||
2229 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2230 | { | |
2231 | int i, r; | |
2232 | ||
2233 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2234 | if (!adev->ip_blocks[i].status.sw) | |
2235 | continue; | |
2236 | if (adev->ip_blocks[i].status.hw) | |
2237 | continue; | |
2238 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2239 | if (r) { | |
2240 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2241 | adev->ip_blocks[i].version->funcs->name, r); | |
2242 | return r; | |
2243 | } | |
2244 | adev->ip_blocks[i].status.hw = true; | |
2245 | } | |
2246 | ||
2247 | return 0; | |
2248 | } | |
2249 | ||
7a3e0bb2 RZ |
2250 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2251 | { | |
2252 | int r = 0; | |
2253 | int i; | |
80f41f84 | 2254 | uint32_t smu_version; |
7a3e0bb2 RZ |
2255 | |
2256 | if (adev->asic_type >= CHIP_VEGA10) { | |
2257 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2258 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2259 | continue; | |
2260 | ||
e3c1b071 | 2261 | if (!adev->ip_blocks[i].status.sw) |
2262 | continue; | |
2263 | ||
482f0e53 ML |
2264 | /* no need to do the fw loading again if already done*/ |
2265 | if (adev->ip_blocks[i].status.hw == true) | |
2266 | break; | |
2267 | ||
53b3f8f4 | 2268 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2269 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2270 | if (r) { | |
2271 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2272 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2273 | return r; |
2274 | } | |
2275 | } else { | |
2276 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2277 | if (r) { | |
2278 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2279 | adev->ip_blocks[i].version->funcs->name, r); | |
2280 | return r; | |
7a3e0bb2 | 2281 | } |
7a3e0bb2 | 2282 | } |
482f0e53 ML |
2283 | |
2284 | adev->ip_blocks[i].status.hw = true; | |
2285 | break; | |
7a3e0bb2 RZ |
2286 | } |
2287 | } | |
482f0e53 | 2288 | |
8973d9ec ED |
2289 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2290 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2291 | |
80f41f84 | 2292 | return r; |
7a3e0bb2 RZ |
2293 | } |
2294 | ||
5fd8518d AG |
2295 | static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) |
2296 | { | |
2297 | long timeout; | |
2298 | int r, i; | |
2299 | ||
2300 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2301 | struct amdgpu_ring *ring = adev->rings[i]; | |
2302 | ||
2303 | /* No need to setup the GPU scheduler for rings that don't need it */ | |
2304 | if (!ring || ring->no_scheduler) | |
2305 | continue; | |
2306 | ||
2307 | switch (ring->funcs->type) { | |
2308 | case AMDGPU_RING_TYPE_GFX: | |
2309 | timeout = adev->gfx_timeout; | |
2310 | break; | |
2311 | case AMDGPU_RING_TYPE_COMPUTE: | |
2312 | timeout = adev->compute_timeout; | |
2313 | break; | |
2314 | case AMDGPU_RING_TYPE_SDMA: | |
2315 | timeout = adev->sdma_timeout; | |
2316 | break; | |
2317 | default: | |
2318 | timeout = adev->video_timeout; | |
2319 | break; | |
2320 | } | |
2321 | ||
2322 | r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, | |
2323 | ring->num_hw_submission, amdgpu_job_hang_limit, | |
8ab62eda JG |
2324 | timeout, adev->reset_domain->wq, |
2325 | ring->sched_score, ring->name, | |
2326 | adev->dev); | |
5fd8518d AG |
2327 | if (r) { |
2328 | DRM_ERROR("Failed to create scheduler on ring %s.\n", | |
2329 | ring->name); | |
2330 | return r; | |
2331 | } | |
2332 | } | |
2333 | ||
2334 | return 0; | |
2335 | } | |
2336 | ||
2337 | ||
e3ecdffa AD |
2338 | /** |
2339 | * amdgpu_device_ip_init - run init for hardware IPs | |
2340 | * | |
2341 | * @adev: amdgpu_device pointer | |
2342 | * | |
2343 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2344 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2345 | * are run. sw_init initializes the software state associated with each IP | |
2346 | * and hw_init initializes the hardware associated with each IP. | |
2347 | * Returns 0 on success, negative error code on failure. | |
2348 | */ | |
06ec9070 | 2349 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2350 | { |
2351 | int i, r; | |
2352 | ||
c030f2e4 | 2353 | r = amdgpu_ras_init(adev); |
2354 | if (r) | |
2355 | return r; | |
2356 | ||
d38ceaf9 | 2357 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2358 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2359 | continue; |
a1255107 | 2360 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2361 | if (r) { |
a1255107 AD |
2362 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2363 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2364 | goto init_failed; |
2c1a2784 | 2365 | } |
a1255107 | 2366 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2367 | |
d38ceaf9 | 2368 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2369 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
892deb48 VS |
2370 | /* Try to reserve bad pages early */ |
2371 | if (amdgpu_sriov_vf(adev)) | |
2372 | amdgpu_virt_exchange_data(adev); | |
2373 | ||
06ec9070 | 2374 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2375 | if (r) { |
2376 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2377 | goto init_failed; |
2c1a2784 | 2378 | } |
a1255107 | 2379 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2380 | if (r) { |
2381 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2382 | goto init_failed; |
2c1a2784 | 2383 | } |
06ec9070 | 2384 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2385 | if (r) { |
06ec9070 | 2386 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2387 | goto init_failed; |
2c1a2784 | 2388 | } |
a1255107 | 2389 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2390 | |
2391 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2392 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2393 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2394 | AMDGPU_GEM_DOMAIN_VRAM, | |
2395 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2396 | if (r) { |
2397 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2398 | goto init_failed; |
2493664f ML |
2399 | } |
2400 | } | |
d38ceaf9 AD |
2401 | } |
2402 | } | |
2403 | ||
c9ffa427 | 2404 | if (amdgpu_sriov_vf(adev)) |
22c16d25 | 2405 | amdgpu_virt_init_data_exchange(adev); |
c9ffa427 | 2406 | |
533aed27 AG |
2407 | r = amdgpu_ib_pool_init(adev); |
2408 | if (r) { | |
2409 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2410 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2411 | goto init_failed; | |
2412 | } | |
2413 | ||
c8963ea4 RZ |
2414 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2415 | if (r) | |
72d3f592 | 2416 | goto init_failed; |
0a4f2520 RZ |
2417 | |
2418 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2419 | if (r) | |
72d3f592 | 2420 | goto init_failed; |
0a4f2520 | 2421 | |
7a3e0bb2 RZ |
2422 | r = amdgpu_device_fw_loading(adev); |
2423 | if (r) | |
72d3f592 | 2424 | goto init_failed; |
7a3e0bb2 | 2425 | |
0a4f2520 RZ |
2426 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2427 | if (r) | |
72d3f592 | 2428 | goto init_failed; |
d38ceaf9 | 2429 | |
121a2bc6 AG |
2430 | /* |
2431 | * retired pages will be loaded from eeprom and reserved here, | |
2432 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2433 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2434 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2435 | * |
2436 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2437 | * failure from bad gpu situation and stop amdgpu init process | |
2438 | * accordingly. For other failed cases, it will still release all | |
2439 | * the resource and print error message, rather than returning one | |
2440 | * negative value to upper level. | |
121a2bc6 AG |
2441 | * |
2442 | * Note: theoretically, this should be called before all vram allocations | |
2443 | * to protect retired page from abusing | |
2444 | */ | |
b82e65a9 GC |
2445 | r = amdgpu_ras_recovery_init(adev); |
2446 | if (r) | |
2447 | goto init_failed; | |
121a2bc6 | 2448 | |
cfbb6b00 AG |
2449 | /** |
2450 | * In case of XGMI grab extra reference for reset domain for this device | |
2451 | */ | |
a4c63caf | 2452 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
cfbb6b00 AG |
2453 | if (amdgpu_xgmi_add_device(adev) == 0) { |
2454 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); | |
a4c63caf | 2455 | |
cfbb6b00 AG |
2456 | if (!hive->reset_domain || |
2457 | !amdgpu_reset_get_reset_domain(hive->reset_domain)) { | |
2458 | r = -ENOENT; | |
2459 | goto init_failed; | |
2460 | } | |
e3c1b071 | 2461 | |
cfbb6b00 AG |
2462 | /* Drop the early temporary reset domain we created for device */ |
2463 | amdgpu_reset_put_reset_domain(adev->reset_domain); | |
2464 | adev->reset_domain = hive->reset_domain; | |
a4c63caf AG |
2465 | } |
2466 | } | |
2467 | ||
5fd8518d AG |
2468 | r = amdgpu_device_init_schedulers(adev); |
2469 | if (r) | |
2470 | goto init_failed; | |
e3c1b071 | 2471 | |
2472 | /* Don't init kfd if whole hive need to be reset during init */ | |
c004d44e | 2473 | if (!adev->gmc.xgmi.pending_reset) |
e3c1b071 | 2474 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 2475 | |
bd607166 KR |
2476 | amdgpu_fru_get_product_info(adev); |
2477 | ||
72d3f592 | 2478 | init_failed: |
c9ffa427 | 2479 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2480 | amdgpu_virt_release_full_gpu(adev, true); |
2481 | ||
72d3f592 | 2482 | return r; |
d38ceaf9 AD |
2483 | } |
2484 | ||
e3ecdffa AD |
2485 | /** |
2486 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2487 | * | |
2488 | * @adev: amdgpu_device pointer | |
2489 | * | |
2490 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2491 | * this function before a GPU reset. If the value is retained after a | |
2492 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2493 | */ | |
06ec9070 | 2494 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2495 | { |
2496 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2497 | } | |
2498 | ||
e3ecdffa AD |
2499 | /** |
2500 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2501 | * | |
2502 | * @adev: amdgpu_device pointer | |
2503 | * | |
2504 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2505 | * The driver calls this after a GPU reset to see if the contents of | |
2506 | * VRAM is lost or now. | |
2507 | * returns true if vram is lost, false if not. | |
2508 | */ | |
06ec9070 | 2509 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2510 | { |
dadce777 EQ |
2511 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2512 | AMDGPU_RESET_MAGIC_NUM)) | |
2513 | return true; | |
2514 | ||
53b3f8f4 | 2515 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2516 | return false; |
2517 | ||
2518 | /* | |
2519 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2520 | * always assumed to be lost. | |
2521 | */ | |
2522 | switch (amdgpu_asic_reset_method(adev)) { | |
2523 | case AMD_RESET_METHOD_BACO: | |
2524 | case AMD_RESET_METHOD_MODE1: | |
2525 | return true; | |
2526 | default: | |
2527 | return false; | |
2528 | } | |
0c49e0b8 CZ |
2529 | } |
2530 | ||
e3ecdffa | 2531 | /** |
1112a46b | 2532 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2533 | * |
2534 | * @adev: amdgpu_device pointer | |
b8b72130 | 2535 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2536 | * |
e3ecdffa | 2537 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2538 | * set_clockgating_state callbacks are run. |
2539 | * Late initialization pass enabling clockgating for hardware IPs. | |
2540 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2541 | * Returns 0 on success, negative error code on failure. |
2542 | */ | |
fdd34271 | 2543 | |
5d89bb2d LL |
2544 | int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2545 | enum amd_clockgating_state state) | |
d38ceaf9 | 2546 | { |
1112a46b | 2547 | int i, j, r; |
d38ceaf9 | 2548 | |
4a2ba394 SL |
2549 | if (amdgpu_emu_mode == 1) |
2550 | return 0; | |
2551 | ||
1112a46b RZ |
2552 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2553 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2554 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2555 | continue; |
5d70a549 PV |
2556 | /* skip CG for GFX on S0ix */ |
2557 | if (adev->in_s0ix && | |
2558 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2559 | continue; | |
4a446d55 | 2560 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2561 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2562 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2563 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2564 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2565 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2566 | /* enable clockgating to save power */ |
a1255107 | 2567 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2568 | state); |
4a446d55 AD |
2569 | if (r) { |
2570 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2571 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2572 | return r; |
2573 | } | |
b0b00ff1 | 2574 | } |
d38ceaf9 | 2575 | } |
06b18f61 | 2576 | |
c9f96fd5 RZ |
2577 | return 0; |
2578 | } | |
2579 | ||
5d89bb2d LL |
2580 | int amdgpu_device_set_pg_state(struct amdgpu_device *adev, |
2581 | enum amd_powergating_state state) | |
c9f96fd5 | 2582 | { |
1112a46b | 2583 | int i, j, r; |
06b18f61 | 2584 | |
c9f96fd5 RZ |
2585 | if (amdgpu_emu_mode == 1) |
2586 | return 0; | |
2587 | ||
1112a46b RZ |
2588 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2589 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2590 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 | 2591 | continue; |
5d70a549 PV |
2592 | /* skip PG for GFX on S0ix */ |
2593 | if (adev->in_s0ix && | |
2594 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2595 | continue; | |
c9f96fd5 RZ |
2596 | /* skip CG for VCE/UVD, it's handled specially */ |
2597 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2598 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2599 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2600 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2601 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2602 | /* enable powergating to save power */ | |
2603 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2604 | state); |
c9f96fd5 RZ |
2605 | if (r) { |
2606 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2607 | adev->ip_blocks[i].version->funcs->name, r); | |
2608 | return r; | |
2609 | } | |
2610 | } | |
2611 | } | |
2dc80b00 S |
2612 | return 0; |
2613 | } | |
2614 | ||
beff74bc AD |
2615 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2616 | { | |
2617 | struct amdgpu_gpu_instance *gpu_ins; | |
2618 | struct amdgpu_device *adev; | |
2619 | int i, ret = 0; | |
2620 | ||
2621 | mutex_lock(&mgpu_info.mutex); | |
2622 | ||
2623 | /* | |
2624 | * MGPU fan boost feature should be enabled | |
2625 | * only when there are two or more dGPUs in | |
2626 | * the system | |
2627 | */ | |
2628 | if (mgpu_info.num_dgpu < 2) | |
2629 | goto out; | |
2630 | ||
2631 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2632 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2633 | adev = gpu_ins->adev; | |
2634 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2635 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2636 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2637 | if (ret) | |
2638 | break; | |
2639 | ||
2640 | gpu_ins->mgpu_fan_enabled = 1; | |
2641 | } | |
2642 | } | |
2643 | ||
2644 | out: | |
2645 | mutex_unlock(&mgpu_info.mutex); | |
2646 | ||
2647 | return ret; | |
2648 | } | |
2649 | ||
e3ecdffa AD |
2650 | /** |
2651 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2652 | * | |
2653 | * @adev: amdgpu_device pointer | |
2654 | * | |
2655 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2656 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2657 | * late_init covers any special initialization that an IP requires | |
2658 | * after all of the have been initialized or something that needs to happen | |
2659 | * late in the init process. | |
2660 | * Returns 0 on success, negative error code on failure. | |
2661 | */ | |
06ec9070 | 2662 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2663 | { |
60599a03 | 2664 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2665 | int i = 0, r; |
2666 | ||
2667 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2668 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2669 | continue; |
2670 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2671 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2672 | if (r) { | |
2673 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2674 | adev->ip_blocks[i].version->funcs->name, r); | |
2675 | return r; | |
2676 | } | |
2dc80b00 | 2677 | } |
73f847db | 2678 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2679 | } |
2680 | ||
867e24ca | 2681 | r = amdgpu_ras_late_init(adev); |
2682 | if (r) { | |
2683 | DRM_ERROR("amdgpu_ras_late_init failed %d", r); | |
2684 | return r; | |
2685 | } | |
2686 | ||
a891d239 DL |
2687 | amdgpu_ras_set_error_query_ready(adev, true); |
2688 | ||
1112a46b RZ |
2689 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2690 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2691 | |
06ec9070 | 2692 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2693 | |
beff74bc AD |
2694 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2695 | if (r) | |
2696 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2697 | ||
4da8b639 | 2698 | /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */ |
2699 | if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)|| | |
2700 | adev->asic_type == CHIP_ALDEBARAN )) | |
bc143d8b | 2701 | amdgpu_dpm_handle_passthrough_sbr(adev, true); |
60599a03 EQ |
2702 | |
2703 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2704 | mutex_lock(&mgpu_info.mutex); | |
2705 | ||
2706 | /* | |
2707 | * Reset device p-state to low as this was booted with high. | |
2708 | * | |
2709 | * This should be performed only after all devices from the same | |
2710 | * hive get initialized. | |
2711 | * | |
2712 | * However, it's unknown how many device in the hive in advance. | |
2713 | * As this is counted one by one during devices initializations. | |
2714 | * | |
2715 | * So, we wait for all XGMI interlinked devices initialized. | |
2716 | * This may bring some delays as those devices may come from | |
2717 | * different hives. But that should be OK. | |
2718 | */ | |
2719 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2720 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2721 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2722 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2723 | continue; | |
2724 | ||
d84a430d JK |
2725 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2726 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2727 | if (r) { |
2728 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2729 | break; | |
2730 | } | |
2731 | } | |
2732 | } | |
2733 | ||
2734 | mutex_unlock(&mgpu_info.mutex); | |
2735 | } | |
2736 | ||
d38ceaf9 AD |
2737 | return 0; |
2738 | } | |
2739 | ||
613aa3ea LY |
2740 | /** |
2741 | * amdgpu_device_smu_fini_early - smu hw_fini wrapper | |
2742 | * | |
2743 | * @adev: amdgpu_device pointer | |
2744 | * | |
2745 | * For ASICs need to disable SMC first | |
2746 | */ | |
2747 | static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev) | |
2748 | { | |
2749 | int i, r; | |
2750 | ||
2751 | if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)) | |
2752 | return; | |
2753 | ||
2754 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2755 | if (!adev->ip_blocks[i].status.hw) | |
2756 | continue; | |
2757 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2758 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); | |
2759 | /* XXX handle errors */ | |
2760 | if (r) { | |
2761 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
2762 | adev->ip_blocks[i].version->funcs->name, r); | |
2763 | } | |
2764 | adev->ip_blocks[i].status.hw = false; | |
2765 | break; | |
2766 | } | |
2767 | } | |
2768 | } | |
2769 | ||
e9669fb7 | 2770 | static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) |
d38ceaf9 AD |
2771 | { |
2772 | int i, r; | |
2773 | ||
e9669fb7 AG |
2774 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2775 | if (!adev->ip_blocks[i].version->funcs->early_fini) | |
2776 | continue; | |
5278a159 | 2777 | |
e9669fb7 AG |
2778 | r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); |
2779 | if (r) { | |
2780 | DRM_DEBUG("early_fini of IP block <%s> failed %d\n", | |
2781 | adev->ip_blocks[i].version->funcs->name, r); | |
2782 | } | |
2783 | } | |
c030f2e4 | 2784 | |
05df1f01 | 2785 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
2786 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2787 | ||
7270e895 TY |
2788 | amdgpu_amdkfd_suspend(adev, false); |
2789 | ||
613aa3ea LY |
2790 | /* Workaroud for ASICs need to disable SMC first */ |
2791 | amdgpu_device_smu_fini_early(adev); | |
3e96dbfd | 2792 | |
d38ceaf9 | 2793 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2794 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2795 | continue; |
8201a67a | 2796 | |
a1255107 | 2797 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2798 | /* XXX handle errors */ |
2c1a2784 | 2799 | if (r) { |
a1255107 AD |
2800 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2801 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2802 | } |
8201a67a | 2803 | |
a1255107 | 2804 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2805 | } |
2806 | ||
6effad8a GC |
2807 | if (amdgpu_sriov_vf(adev)) { |
2808 | if (amdgpu_virt_release_full_gpu(adev, false)) | |
2809 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2810 | } | |
2811 | ||
e9669fb7 AG |
2812 | return 0; |
2813 | } | |
2814 | ||
2815 | /** | |
2816 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2817 | * | |
2818 | * @adev: amdgpu_device pointer | |
2819 | * | |
2820 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2821 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2822 | * are run. hw_fini tears down the hardware associated with each IP | |
2823 | * and sw_fini tears down any software state associated with each IP. | |
2824 | * Returns 0 on success, negative error code on failure. | |
2825 | */ | |
2826 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |
2827 | { | |
2828 | int i, r; | |
2829 | ||
2830 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) | |
2831 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2832 | ||
e9669fb7 AG |
2833 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2834 | amdgpu_xgmi_remove_device(adev); | |
2835 | ||
c004d44e | 2836 | amdgpu_amdkfd_device_fini_sw(adev); |
9950cda2 | 2837 | |
d38ceaf9 | 2838 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2839 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2840 | continue; |
c12aba3a ML |
2841 | |
2842 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2843 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2844 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2845 | amdgpu_device_wb_fini(adev); |
2846 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2847 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2848 | } |
2849 | ||
a1255107 | 2850 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2851 | /* XXX handle errors */ |
2c1a2784 | 2852 | if (r) { |
a1255107 AD |
2853 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2854 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2855 | } |
a1255107 AD |
2856 | adev->ip_blocks[i].status.sw = false; |
2857 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2858 | } |
2859 | ||
a6dcfd9c | 2860 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2861 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2862 | continue; |
a1255107 AD |
2863 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2864 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2865 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2866 | } |
2867 | ||
c030f2e4 | 2868 | amdgpu_ras_fini(adev); |
2869 | ||
d38ceaf9 AD |
2870 | return 0; |
2871 | } | |
2872 | ||
e3ecdffa | 2873 | /** |
beff74bc | 2874 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2875 | * |
1112a46b | 2876 | * @work: work_struct. |
e3ecdffa | 2877 | */ |
beff74bc | 2878 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2879 | { |
2880 | struct amdgpu_device *adev = | |
beff74bc | 2881 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2882 | int r; |
2883 | ||
2884 | r = amdgpu_ib_ring_tests(adev); | |
2885 | if (r) | |
2886 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2887 | } |
2888 | ||
1e317b99 RZ |
2889 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2890 | { | |
2891 | struct amdgpu_device *adev = | |
2892 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2893 | ||
90a92662 MD |
2894 | WARN_ON_ONCE(adev->gfx.gfx_off_state); |
2895 | WARN_ON_ONCE(adev->gfx.gfx_off_req_count); | |
2896 | ||
2897 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2898 | adev->gfx.gfx_off_state = true; | |
1e317b99 RZ |
2899 | } |
2900 | ||
e3ecdffa | 2901 | /** |
e7854a03 | 2902 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2903 | * |
2904 | * @adev: amdgpu_device pointer | |
2905 | * | |
2906 | * Main suspend function for hardware IPs. The list of all the hardware | |
2907 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2908 | * suspend callbacks are run. suspend puts the hardware and software state | |
2909 | * in each IP into a state suitable for suspend. | |
2910 | * Returns 0 on success, negative error code on failure. | |
2911 | */ | |
e7854a03 AD |
2912 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2913 | { | |
2914 | int i, r; | |
2915 | ||
50ec83f0 AD |
2916 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2917 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2918 | |
e7854a03 AD |
2919 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2920 | if (!adev->ip_blocks[i].status.valid) | |
2921 | continue; | |
2b9f7848 | 2922 | |
e7854a03 | 2923 | /* displays are handled separately */ |
2b9f7848 ND |
2924 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2925 | continue; | |
2926 | ||
2927 | /* XXX handle errors */ | |
2928 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2929 | /* XXX handle errors */ | |
2930 | if (r) { | |
2931 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2932 | adev->ip_blocks[i].version->funcs->name, r); | |
2933 | return r; | |
e7854a03 | 2934 | } |
2b9f7848 ND |
2935 | |
2936 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2937 | } |
2938 | ||
e7854a03 AD |
2939 | return 0; |
2940 | } | |
2941 | ||
2942 | /** | |
2943 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2944 | * | |
2945 | * @adev: amdgpu_device pointer | |
2946 | * | |
2947 | * Main suspend function for hardware IPs. The list of all the hardware | |
2948 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2949 | * suspend callbacks are run. suspend puts the hardware and software state | |
2950 | * in each IP into a state suitable for suspend. | |
2951 | * Returns 0 on success, negative error code on failure. | |
2952 | */ | |
2953 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2954 | { |
2955 | int i, r; | |
2956 | ||
557f42a2 | 2957 | if (adev->in_s0ix) |
bc143d8b | 2958 | amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry); |
34416931 | 2959 | |
d38ceaf9 | 2960 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2961 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2962 | continue; |
e7854a03 AD |
2963 | /* displays are handled in phase1 */ |
2964 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2965 | continue; | |
bff77e86 LM |
2966 | /* PSP lost connection when err_event_athub occurs */ |
2967 | if (amdgpu_ras_intr_triggered() && | |
2968 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2969 | adev->ip_blocks[i].status.hw = false; | |
2970 | continue; | |
2971 | } | |
e3c1b071 | 2972 | |
2973 | /* skip unnecessary suspend if we do not initialize them yet */ | |
2974 | if (adev->gmc.xgmi.pending_reset && | |
2975 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2976 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
2977 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2978 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
2979 | adev->ip_blocks[i].status.hw = false; | |
2980 | continue; | |
2981 | } | |
557f42a2 | 2982 | |
32ff160d AD |
2983 | /* skip suspend of gfx and psp for S0ix |
2984 | * gfx is in gfxoff state, so on resume it will exit gfxoff just | |
2985 | * like at runtime. PSP is also part of the always on hardware | |
2986 | * so no need to suspend it. | |
2987 | */ | |
557f42a2 | 2988 | if (adev->in_s0ix && |
32ff160d AD |
2989 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || |
2990 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)) | |
557f42a2 AD |
2991 | continue; |
2992 | ||
d38ceaf9 | 2993 | /* XXX handle errors */ |
a1255107 | 2994 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2995 | /* XXX handle errors */ |
2c1a2784 | 2996 | if (r) { |
a1255107 AD |
2997 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2998 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2999 | } |
876923fb | 3000 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 3001 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
3002 | if(!amdgpu_sriov_vf(adev)){ |
3003 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
3004 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
3005 | if (r) { | |
3006 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
3007 | adev->mp1_state, r); | |
3008 | return r; | |
3009 | } | |
a3a09142 AD |
3010 | } |
3011 | } | |
d38ceaf9 AD |
3012 | } |
3013 | ||
3014 | return 0; | |
3015 | } | |
3016 | ||
e7854a03 AD |
3017 | /** |
3018 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
3019 | * | |
3020 | * @adev: amdgpu_device pointer | |
3021 | * | |
3022 | * Main suspend function for hardware IPs. The list of all the hardware | |
3023 | * IPs that make up the asic is walked, clockgating is disabled and the | |
3024 | * suspend callbacks are run. suspend puts the hardware and software state | |
3025 | * in each IP into a state suitable for suspend. | |
3026 | * Returns 0 on success, negative error code on failure. | |
3027 | */ | |
3028 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
3029 | { | |
3030 | int r; | |
3031 | ||
3c73683c JC |
3032 | if (amdgpu_sriov_vf(adev)) { |
3033 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 3034 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 3035 | } |
e7819644 | 3036 | |
e7854a03 AD |
3037 | r = amdgpu_device_ip_suspend_phase1(adev); |
3038 | if (r) | |
3039 | return r; | |
3040 | r = amdgpu_device_ip_suspend_phase2(adev); | |
3041 | ||
e7819644 YT |
3042 | if (amdgpu_sriov_vf(adev)) |
3043 | amdgpu_virt_release_full_gpu(adev, false); | |
3044 | ||
e7854a03 AD |
3045 | return r; |
3046 | } | |
3047 | ||
06ec9070 | 3048 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3049 | { |
3050 | int i, r; | |
3051 | ||
2cb681b6 ML |
3052 | static enum amd_ip_block_type ip_order[] = { |
3053 | AMD_IP_BLOCK_TYPE_GMC, | |
3054 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 3055 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
3056 | AMD_IP_BLOCK_TYPE_IH, |
3057 | }; | |
a90ad3c2 | 3058 | |
95ea3dbc | 3059 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2cb681b6 ML |
3060 | int j; |
3061 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3062 | |
4cd2a96d J |
3063 | block = &adev->ip_blocks[i]; |
3064 | block->status.hw = false; | |
2cb681b6 | 3065 | |
4cd2a96d | 3066 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 3067 | |
4cd2a96d | 3068 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
3069 | !block->status.valid) |
3070 | continue; | |
3071 | ||
3072 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 3073 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3074 | if (r) |
3075 | return r; | |
482f0e53 | 3076 | block->status.hw = true; |
a90ad3c2 ML |
3077 | } |
3078 | } | |
3079 | ||
3080 | return 0; | |
3081 | } | |
3082 | ||
06ec9070 | 3083 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3084 | { |
3085 | int i, r; | |
3086 | ||
2cb681b6 ML |
3087 | static enum amd_ip_block_type ip_order[] = { |
3088 | AMD_IP_BLOCK_TYPE_SMC, | |
3089 | AMD_IP_BLOCK_TYPE_DCE, | |
3090 | AMD_IP_BLOCK_TYPE_GFX, | |
3091 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 3092 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
3093 | AMD_IP_BLOCK_TYPE_VCE, |
3094 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 3095 | }; |
a90ad3c2 | 3096 | |
2cb681b6 ML |
3097 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
3098 | int j; | |
3099 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3100 | |
2cb681b6 ML |
3101 | for (j = 0; j < adev->num_ip_blocks; j++) { |
3102 | block = &adev->ip_blocks[j]; | |
3103 | ||
3104 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
3105 | !block->status.valid || |
3106 | block->status.hw) | |
2cb681b6 ML |
3107 | continue; |
3108 | ||
895bd048 JZ |
3109 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
3110 | r = block->version->funcs->resume(adev); | |
3111 | else | |
3112 | r = block->version->funcs->hw_init(adev); | |
3113 | ||
0aaeefcc | 3114 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3115 | if (r) |
3116 | return r; | |
482f0e53 | 3117 | block->status.hw = true; |
a90ad3c2 ML |
3118 | } |
3119 | } | |
3120 | ||
3121 | return 0; | |
3122 | } | |
3123 | ||
e3ecdffa AD |
3124 | /** |
3125 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
3126 | * | |
3127 | * @adev: amdgpu_device pointer | |
3128 | * | |
3129 | * First resume function for hardware IPs. The list of all the hardware | |
3130 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3131 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
3132 | * after a suspend and updates the software state as necessary. This | |
3133 | * function is also used for restoring the GPU after a GPU reset. | |
3134 | * Returns 0 on success, negative error code on failure. | |
3135 | */ | |
06ec9070 | 3136 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
3137 | { |
3138 | int i, r; | |
3139 | ||
a90ad3c2 | 3140 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 3141 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 3142 | continue; |
a90ad3c2 | 3143 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
3144 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
3145 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 3146 | |
fcf0649f CZ |
3147 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
3148 | if (r) { | |
3149 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
3150 | adev->ip_blocks[i].version->funcs->name, r); | |
3151 | return r; | |
3152 | } | |
482f0e53 | 3153 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
3154 | } |
3155 | } | |
3156 | ||
3157 | return 0; | |
3158 | } | |
3159 | ||
e3ecdffa AD |
3160 | /** |
3161 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
3162 | * | |
3163 | * @adev: amdgpu_device pointer | |
3164 | * | |
3165 | * First resume function for hardware IPs. The list of all the hardware | |
3166 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3167 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
3168 | * functional state after a suspend and updates the software state as | |
3169 | * necessary. This function is also used for restoring the GPU after a GPU | |
3170 | * reset. | |
3171 | * Returns 0 on success, negative error code on failure. | |
3172 | */ | |
06ec9070 | 3173 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
3174 | { |
3175 | int i, r; | |
3176 | ||
3177 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 3178 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 3179 | continue; |
fcf0649f | 3180 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3181 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
3182 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3183 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 3184 | continue; |
a1255107 | 3185 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 3186 | if (r) { |
a1255107 AD |
3187 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
3188 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 3189 | return r; |
2c1a2784 | 3190 | } |
482f0e53 | 3191 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
3192 | } |
3193 | ||
3194 | return 0; | |
3195 | } | |
3196 | ||
e3ecdffa AD |
3197 | /** |
3198 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
3199 | * | |
3200 | * @adev: amdgpu_device pointer | |
3201 | * | |
3202 | * Main resume function for hardware IPs. The hardware IPs | |
3203 | * are split into two resume functions because they are | |
3204 | * are also used in in recovering from a GPU reset and some additional | |
3205 | * steps need to be take between them. In this case (S3/S4) they are | |
3206 | * run sequentially. | |
3207 | * Returns 0 on success, negative error code on failure. | |
3208 | */ | |
06ec9070 | 3209 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
3210 | { |
3211 | int r; | |
3212 | ||
9cec53c1 JZ |
3213 | r = amdgpu_amdkfd_resume_iommu(adev); |
3214 | if (r) | |
3215 | return r; | |
3216 | ||
06ec9070 | 3217 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
3218 | if (r) |
3219 | return r; | |
7a3e0bb2 RZ |
3220 | |
3221 | r = amdgpu_device_fw_loading(adev); | |
3222 | if (r) | |
3223 | return r; | |
3224 | ||
06ec9070 | 3225 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
3226 | |
3227 | return r; | |
3228 | } | |
3229 | ||
e3ecdffa AD |
3230 | /** |
3231 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
3232 | * | |
3233 | * @adev: amdgpu_device pointer | |
3234 | * | |
3235 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
3236 | */ | |
4e99a44e | 3237 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 3238 | { |
6867e1b5 ML |
3239 | if (amdgpu_sriov_vf(adev)) { |
3240 | if (adev->is_atom_fw) { | |
58ff791a | 3241 | if (amdgpu_atomfirmware_gpu_virtualization_supported(adev)) |
6867e1b5 ML |
3242 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; |
3243 | } else { | |
3244 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3245 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3246 | } | |
3247 | ||
3248 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3249 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3250 | } |
048765ad AR |
3251 | } |
3252 | ||
e3ecdffa AD |
3253 | /** |
3254 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3255 | * | |
3256 | * @asic_type: AMD asic type | |
3257 | * | |
3258 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3259 | * returns true if DC has support, false if not. | |
3260 | */ | |
4562236b HW |
3261 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3262 | { | |
3263 | switch (asic_type) { | |
0637d417 AD |
3264 | #ifdef CONFIG_DRM_AMDGPU_SI |
3265 | case CHIP_HAINAN: | |
3266 | #endif | |
3267 | case CHIP_TOPAZ: | |
3268 | /* chips with no display hardware */ | |
3269 | return false; | |
4562236b | 3270 | #if defined(CONFIG_DRM_AMD_DC) |
64200c46 MR |
3271 | case CHIP_TAHITI: |
3272 | case CHIP_PITCAIRN: | |
3273 | case CHIP_VERDE: | |
3274 | case CHIP_OLAND: | |
2d32ffd6 AD |
3275 | /* |
3276 | * We have systems in the wild with these ASICs that require | |
3277 | * LVDS and VGA support which is not supported with DC. | |
3278 | * | |
3279 | * Fallback to the non-DC driver here by default so as not to | |
3280 | * cause regressions. | |
3281 | */ | |
3282 | #if defined(CONFIG_DRM_AMD_DC_SI) | |
3283 | return amdgpu_dc > 0; | |
3284 | #else | |
3285 | return false; | |
64200c46 | 3286 | #endif |
4562236b | 3287 | case CHIP_BONAIRE: |
0d6fbccb | 3288 | case CHIP_KAVERI: |
367e6687 AD |
3289 | case CHIP_KABINI: |
3290 | case CHIP_MULLINS: | |
d9fda248 HW |
3291 | /* |
3292 | * We have systems in the wild with these ASICs that require | |
b5a0168e | 3293 | * VGA support which is not supported with DC. |
d9fda248 HW |
3294 | * |
3295 | * Fallback to the non-DC driver here by default so as not to | |
3296 | * cause regressions. | |
3297 | */ | |
3298 | return amdgpu_dc > 0; | |
f7f12b25 | 3299 | default: |
fd187853 | 3300 | return amdgpu_dc != 0; |
f7f12b25 | 3301 | #else |
4562236b | 3302 | default: |
93b09a9a | 3303 | if (amdgpu_dc > 0) |
044a48f4 | 3304 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter " |
93b09a9a | 3305 | "but isn't supported by ASIC, ignoring\n"); |
4562236b | 3306 | return false; |
f7f12b25 | 3307 | #endif |
4562236b HW |
3308 | } |
3309 | } | |
3310 | ||
3311 | /** | |
3312 | * amdgpu_device_has_dc_support - check if dc is supported | |
3313 | * | |
982a820b | 3314 | * @adev: amdgpu_device pointer |
4562236b HW |
3315 | * |
3316 | * Returns true for supported, false for not supported | |
3317 | */ | |
3318 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3319 | { | |
f74e78ca | 3320 | if (amdgpu_sriov_vf(adev) || |
abaf210c AS |
3321 | adev->enable_virtual_display || |
3322 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) | |
2555039d XY |
3323 | return false; |
3324 | ||
4562236b HW |
3325 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3326 | } | |
3327 | ||
d4535e2c AG |
3328 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) |
3329 | { | |
3330 | struct amdgpu_device *adev = | |
3331 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3332 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3333 | |
c6a6e2db AG |
3334 | /* It's a bug to not have a hive within this function */ |
3335 | if (WARN_ON(!hive)) | |
3336 | return; | |
3337 | ||
3338 | /* | |
3339 | * Use task barrier to synchronize all xgmi reset works across the | |
3340 | * hive. task_barrier_enter and task_barrier_exit will block | |
3341 | * until all the threads running the xgmi reset works reach | |
3342 | * those points. task_barrier_full will do both blocks. | |
3343 | */ | |
3344 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3345 | ||
3346 | task_barrier_enter(&hive->tb); | |
4a580877 | 3347 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3348 | |
3349 | if (adev->asic_reset_res) | |
3350 | goto fail; | |
3351 | ||
3352 | task_barrier_exit(&hive->tb); | |
4a580877 | 3353 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3354 | |
3355 | if (adev->asic_reset_res) | |
3356 | goto fail; | |
43c4d576 | 3357 | |
5e67bba3 | 3358 | if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && |
3359 | adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) | |
3360 | adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); | |
c6a6e2db AG |
3361 | } else { |
3362 | ||
3363 | task_barrier_full(&hive->tb); | |
3364 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3365 | } | |
ce316fa5 | 3366 | |
c6a6e2db | 3367 | fail: |
d4535e2c | 3368 | if (adev->asic_reset_res) |
fed184e9 | 3369 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3370 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3371 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3372 | } |
3373 | ||
71f98027 AD |
3374 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3375 | { | |
3376 | char *input = amdgpu_lockup_timeout; | |
3377 | char *timeout_setting = NULL; | |
3378 | int index = 0; | |
3379 | long timeout; | |
3380 | int ret = 0; | |
3381 | ||
3382 | /* | |
67387dfe AD |
3383 | * By default timeout for non compute jobs is 10000 |
3384 | * and 60000 for compute jobs. | |
71f98027 | 3385 | * In SR-IOV or passthrough mode, timeout for compute |
b7b2a316 | 3386 | * jobs are 60000 by default. |
71f98027 AD |
3387 | */ |
3388 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3389 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3390 | if (amdgpu_sriov_vf(adev)) |
3391 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3392 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
71f98027 | 3393 | else |
67387dfe | 3394 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 | 3395 | |
f440ff44 | 3396 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3397 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3398 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3399 | ret = kstrtol(timeout_setting, 0, &timeout); |
3400 | if (ret) | |
3401 | return ret; | |
3402 | ||
3403 | if (timeout == 0) { | |
3404 | index++; | |
3405 | continue; | |
3406 | } else if (timeout < 0) { | |
3407 | timeout = MAX_SCHEDULE_TIMEOUT; | |
127aedf9 CK |
3408 | dev_warn(adev->dev, "lockup timeout disabled"); |
3409 | add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK); | |
71f98027 AD |
3410 | } else { |
3411 | timeout = msecs_to_jiffies(timeout); | |
3412 | } | |
3413 | ||
3414 | switch (index++) { | |
3415 | case 0: | |
3416 | adev->gfx_timeout = timeout; | |
3417 | break; | |
3418 | case 1: | |
3419 | adev->compute_timeout = timeout; | |
3420 | break; | |
3421 | case 2: | |
3422 | adev->sdma_timeout = timeout; | |
3423 | break; | |
3424 | case 3: | |
3425 | adev->video_timeout = timeout; | |
3426 | break; | |
3427 | default: | |
3428 | break; | |
3429 | } | |
3430 | } | |
3431 | /* | |
3432 | * There is only one value specified and | |
3433 | * it should apply to all non-compute jobs. | |
3434 | */ | |
bcccee89 | 3435 | if (index == 1) { |
71f98027 | 3436 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3437 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3438 | adev->compute_timeout = adev->gfx_timeout; | |
3439 | } | |
71f98027 AD |
3440 | } |
3441 | ||
3442 | return ret; | |
3443 | } | |
d4535e2c | 3444 | |
4a74c38c PY |
3445 | /** |
3446 | * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU | |
3447 | * | |
3448 | * @adev: amdgpu_device pointer | |
3449 | * | |
3450 | * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode | |
3451 | */ | |
3452 | static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev) | |
3453 | { | |
3454 | struct iommu_domain *domain; | |
3455 | ||
3456 | domain = iommu_get_domain_for_dev(adev->dev); | |
3457 | if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) | |
3458 | adev->ram_is_direct_mapped = true; | |
3459 | } | |
3460 | ||
77f3a5cd ND |
3461 | static const struct attribute *amdgpu_dev_attributes[] = { |
3462 | &dev_attr_product_name.attr, | |
3463 | &dev_attr_product_number.attr, | |
3464 | &dev_attr_serial_number.attr, | |
3465 | &dev_attr_pcie_replay_count.attr, | |
3466 | NULL | |
3467 | }; | |
3468 | ||
d38ceaf9 AD |
3469 | /** |
3470 | * amdgpu_device_init - initialize the driver | |
3471 | * | |
3472 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3473 | * @flags: driver flags |
3474 | * | |
3475 | * Initializes the driver info and hw (all asics). | |
3476 | * Returns 0 for success or an error on failure. | |
3477 | * Called at driver startup. | |
3478 | */ | |
3479 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3480 | uint32_t flags) |
3481 | { | |
8aba21b7 LT |
3482 | struct drm_device *ddev = adev_to_drm(adev); |
3483 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3484 | int r, i; |
b98c6299 | 3485 | bool px = false; |
95844d20 | 3486 | u32 max_MBps; |
d38ceaf9 AD |
3487 | |
3488 | adev->shutdown = false; | |
d38ceaf9 | 3489 | adev->flags = flags; |
4e66d7d2 YZ |
3490 | |
3491 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3492 | adev->asic_type = amdgpu_force_asic_type; | |
3493 | else | |
3494 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3495 | ||
d38ceaf9 | 3496 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3497 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3498 | adev->usec_timeout *= 10; |
770d13b1 | 3499 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3500 | adev->accel_working = false; |
3501 | adev->num_rings = 0; | |
3502 | adev->mman.buffer_funcs = NULL; | |
3503 | adev->mman.buffer_funcs_ring = NULL; | |
3504 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3505 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3506 | adev->gmc.gmc_funcs = NULL; |
7bd939d0 | 3507 | adev->harvest_ip_mask = 0x0; |
f54d1867 | 3508 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3509 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3510 | |
3511 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3512 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3513 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3514 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3515 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3516 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3517 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3518 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3519 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3520 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3521 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3522 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3523 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3524 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3525 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3526 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3527 | ||
3e39ab90 AD |
3528 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3529 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3530 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3531 | |
3532 | /* mutex initialization are all done here so we | |
3533 | * can recall function without having locking issues */ | |
0e5ca0d1 | 3534 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3535 | mutex_init(&adev->pm.mutex); |
3536 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3537 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3538 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3539 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3540 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3541 | mutex_init(&adev->mn_lock); |
e23b74aa | 3542 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3543 | hash_init(adev->mn_hash); |
32eaeae0 | 3544 | mutex_init(&adev->psp.mutex); |
bd052211 | 3545 | mutex_init(&adev->notifier_lock); |
8cda7a4f | 3546 | mutex_init(&adev->pm.stable_pstate_ctx_lock); |
f113cc32 | 3547 | mutex_init(&adev->benchmark_mutex); |
d38ceaf9 | 3548 | |
ab3b9de6 | 3549 | amdgpu_device_init_apu_flags(adev); |
9f6a7857 | 3550 | |
912dfc84 EQ |
3551 | r = amdgpu_device_check_arguments(adev); |
3552 | if (r) | |
3553 | return r; | |
d38ceaf9 | 3554 | |
d38ceaf9 AD |
3555 | spin_lock_init(&adev->mmio_idx_lock); |
3556 | spin_lock_init(&adev->smc_idx_lock); | |
3557 | spin_lock_init(&adev->pcie_idx_lock); | |
3558 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3559 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3560 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3561 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3562 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3563 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3564 | |
0c4e7fa5 CZ |
3565 | INIT_LIST_HEAD(&adev->shadow_list); |
3566 | mutex_init(&adev->shadow_list_lock); | |
3567 | ||
655ce9cb | 3568 | INIT_LIST_HEAD(&adev->reset_list); |
3569 | ||
6492e1b0 | 3570 | INIT_LIST_HEAD(&adev->ras_list); |
3571 | ||
beff74bc AD |
3572 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3573 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3574 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3575 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3576 | |
d4535e2c AG |
3577 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3578 | ||
d23ee13f | 3579 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3580 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3581 | |
b265bdbd EQ |
3582 | atomic_set(&adev->throttling_logging_enabled, 1); |
3583 | /* | |
3584 | * If throttling continues, logging will be performed every minute | |
3585 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3586 | * throttling interrupt comes every second. Thus, the total logging | |
3587 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3588 | * for throttling interrupt) = 60 seconds. | |
3589 | */ | |
3590 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3591 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3592 | ||
0fa49558 AX |
3593 | /* Registers mapping */ |
3594 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3595 | if (adev->asic_type >= CHIP_BONAIRE) { |
3596 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3597 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3598 | } else { | |
3599 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3600 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3601 | } | |
d38ceaf9 | 3602 | |
6c08e0ef EQ |
3603 | for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++) |
3604 | atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); | |
3605 | ||
d38ceaf9 AD |
3606 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3607 | if (adev->rmmio == NULL) { | |
3608 | return -ENOMEM; | |
3609 | } | |
3610 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3611 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3612 | ||
5494d864 AD |
3613 | amdgpu_device_get_pcie_info(adev); |
3614 | ||
b239c017 JX |
3615 | if (amdgpu_mcbp) |
3616 | DRM_INFO("MCBP is enabled\n"); | |
3617 | ||
436afdfa PY |
3618 | /* |
3619 | * Reset domain needs to be present early, before XGMI hive discovered | |
3620 | * (if any) and intitialized to use reset sem and in_gpu reset flag | |
3621 | * early on during init and before calling to RREG32. | |
3622 | */ | |
3623 | adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev"); | |
3624 | if (!adev->reset_domain) | |
3625 | return -ENOMEM; | |
3626 | ||
3aa0115d ML |
3627 | /* detect hw virtualization here */ |
3628 | amdgpu_detect_virtualization(adev); | |
3629 | ||
dffa11b4 ML |
3630 | r = amdgpu_device_get_job_timeout_settings(adev); |
3631 | if (r) { | |
3632 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
4ef87d8f | 3633 | return r; |
a190d1c7 XY |
3634 | } |
3635 | ||
d38ceaf9 | 3636 | /* early init functions */ |
06ec9070 | 3637 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 3638 | if (r) |
4ef87d8f | 3639 | return r; |
d38ceaf9 | 3640 | |
4d33e704 SK |
3641 | /* Enable TMZ based on IP_VERSION */ |
3642 | amdgpu_gmc_tmz_set(adev); | |
3643 | ||
957b0787 | 3644 | amdgpu_gmc_noretry_set(adev); |
4a0165f0 VS |
3645 | /* Need to get xgmi info early to decide the reset behavior*/ |
3646 | if (adev->gmc.xgmi.supported) { | |
3647 | r = adev->gfxhub.funcs->get_xgmi_info(adev); | |
3648 | if (r) | |
3649 | return r; | |
3650 | } | |
3651 | ||
8e6d0b69 | 3652 | /* enable PCIE atomic ops */ |
3653 | if (amdgpu_sriov_vf(adev)) | |
3654 | adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *) | |
e15c9d06 | 3655 | adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags == |
8e6d0b69 | 3656 | (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); |
3657 | else | |
3658 | adev->have_atomics_support = | |
3659 | !pci_enable_atomic_ops_to_root(adev->pdev, | |
3660 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3661 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3662 | if (!adev->have_atomics_support) | |
3663 | dev_info(adev->dev, "PCIE atomic ops is not supported\n"); | |
3664 | ||
6585661d OZ |
3665 | /* doorbell bar mapping and doorbell index init*/ |
3666 | amdgpu_device_doorbell_init(adev); | |
3667 | ||
9475a943 SL |
3668 | if (amdgpu_emu_mode == 1) { |
3669 | /* post the asic on emulation mode */ | |
3670 | emu_soc_asic_init(adev); | |
bfca0289 | 3671 | goto fence_driver_init; |
9475a943 | 3672 | } |
bfca0289 | 3673 | |
04442bf7 LL |
3674 | amdgpu_reset_init(adev); |
3675 | ||
4e99a44e ML |
3676 | /* detect if we are with an SRIOV vbios */ |
3677 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3678 | |
95e8e59e AD |
3679 | /* check if we need to reset the asic |
3680 | * E.g., driver was not cleanly unloaded previously, etc. | |
3681 | */ | |
f14899fd | 3682 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 3683 | if (adev->gmc.xgmi.num_physical_nodes) { |
3684 | dev_info(adev->dev, "Pending hive reset.\n"); | |
3685 | adev->gmc.xgmi.pending_reset = true; | |
3686 | /* Only need to init necessary block for SMU to handle the reset */ | |
3687 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3688 | if (!adev->ip_blocks[i].status.valid) | |
3689 | continue; | |
3690 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3691 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3692 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
3693 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 3694 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 3695 | adev->ip_blocks[i].version->funcs->name); |
3696 | adev->ip_blocks[i].status.hw = true; | |
3697 | } | |
3698 | } | |
3699 | } else { | |
3700 | r = amdgpu_asic_reset(adev); | |
3701 | if (r) { | |
3702 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3703 | goto failed; | |
3704 | } | |
95e8e59e AD |
3705 | } |
3706 | } | |
3707 | ||
8f66090b | 3708 | pci_enable_pcie_error_reporting(adev->pdev); |
c9a6b82f | 3709 | |
d38ceaf9 | 3710 | /* Post card if necessary */ |
39c640c0 | 3711 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3712 | if (!adev->bios) { |
bec86378 | 3713 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3714 | r = -EINVAL; |
3715 | goto failed; | |
d38ceaf9 | 3716 | } |
bec86378 | 3717 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3718 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3719 | if (r) { |
3720 | dev_err(adev->dev, "gpu post error!\n"); | |
3721 | goto failed; | |
3722 | } | |
d38ceaf9 AD |
3723 | } |
3724 | ||
88b64e95 AD |
3725 | if (adev->is_atom_fw) { |
3726 | /* Initialize clocks */ | |
3727 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3728 | if (r) { | |
3729 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3730 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3731 | goto failed; |
3732 | } | |
3733 | } else { | |
a5bde2f9 AD |
3734 | /* Initialize clocks */ |
3735 | r = amdgpu_atombios_get_clock_info(adev); | |
3736 | if (r) { | |
3737 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3738 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3739 | goto failed; |
a5bde2f9 AD |
3740 | } |
3741 | /* init i2c buses */ | |
4562236b HW |
3742 | if (!amdgpu_device_has_dc_support(adev)) |
3743 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3744 | } |
d38ceaf9 | 3745 | |
bfca0289 | 3746 | fence_driver_init: |
d38ceaf9 | 3747 | /* Fence driver */ |
067f44c8 | 3748 | r = amdgpu_fence_driver_sw_init(adev); |
2c1a2784 | 3749 | if (r) { |
067f44c8 | 3750 | dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n"); |
e23b74aa | 3751 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3752 | goto failed; |
2c1a2784 | 3753 | } |
d38ceaf9 AD |
3754 | |
3755 | /* init the mode config */ | |
4a580877 | 3756 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3757 | |
06ec9070 | 3758 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3759 | if (r) { |
8840a387 | 3760 | /* failed in exclusive mode due to timeout */ |
3761 | if (amdgpu_sriov_vf(adev) && | |
3762 | !amdgpu_sriov_runtime(adev) && | |
3763 | amdgpu_virt_mmio_blocked(adev) && | |
3764 | !amdgpu_virt_wait_reset(adev)) { | |
3765 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3766 | /* Don't send request since VF is inactive. */ |
3767 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3768 | adev->virt.ops = NULL; | |
8840a387 | 3769 | r = -EAGAIN; |
970fd197 | 3770 | goto release_ras_con; |
8840a387 | 3771 | } |
06ec9070 | 3772 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3773 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 3774 | goto release_ras_con; |
d38ceaf9 AD |
3775 | } |
3776 | ||
8d35a259 LG |
3777 | amdgpu_fence_driver_hw_init(adev); |
3778 | ||
d69b8971 YZ |
3779 | dev_info(adev->dev, |
3780 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3781 | adev->gfx.config.max_shader_engines, |
3782 | adev->gfx.config.max_sh_per_se, | |
3783 | adev->gfx.config.max_cu_per_sh, | |
3784 | adev->gfx.cu_info.number); | |
3785 | ||
d38ceaf9 AD |
3786 | adev->accel_working = true; |
3787 | ||
e59c0205 AX |
3788 | amdgpu_vm_check_compute_bug(adev); |
3789 | ||
95844d20 MO |
3790 | /* Initialize the buffer migration limit. */ |
3791 | if (amdgpu_moverate >= 0) | |
3792 | max_MBps = amdgpu_moverate; | |
3793 | else | |
3794 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3795 | /* Get a log2 for easy divisions. */ | |
3796 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3797 | ||
d2f52ac8 | 3798 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3799 | if (r) { |
3800 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3801 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3802 | } else |
3803 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3804 | |
5bb23532 | 3805 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3806 | if (r) { |
3807 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3808 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3809 | } else |
3810 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3811 | |
8424f2cc LG |
3812 | r = amdgpu_psp_sysfs_init(adev); |
3813 | if (r) { | |
3814 | adev->psp_sysfs_en = false; | |
3815 | if (!amdgpu_sriov_vf(adev)) | |
3816 | DRM_ERROR("Creating psp sysfs failed\n"); | |
3817 | } else | |
3818 | adev->psp_sysfs_en = true; | |
3819 | ||
b0adca4d EQ |
3820 | /* |
3821 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3822 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3823 | * gpu instance is counted less. | |
3824 | */ | |
3825 | amdgpu_register_gpu_instance(adev); | |
3826 | ||
d38ceaf9 AD |
3827 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3828 | * explicit gating rather than handling it automatically. | |
3829 | */ | |
e3c1b071 | 3830 | if (!adev->gmc.xgmi.pending_reset) { |
3831 | r = amdgpu_device_ip_late_init(adev); | |
3832 | if (r) { | |
3833 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
3834 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 3835 | goto release_ras_con; |
e3c1b071 | 3836 | } |
3837 | /* must succeed. */ | |
3838 | amdgpu_ras_resume(adev); | |
3839 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
3840 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 3841 | } |
d38ceaf9 | 3842 | |
2c738637 ML |
3843 | if (amdgpu_sriov_vf(adev)) |
3844 | flush_delayed_work(&adev->delayed_init_work); | |
3845 | ||
77f3a5cd | 3846 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 3847 | if (r) |
77f3a5cd | 3848 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 3849 | |
d155bef0 AB |
3850 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3851 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3852 | if (r) |
3853 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3854 | ||
c1dd4aa6 AG |
3855 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
3856 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
3857 | pci_restore_state(pdev); | |
3858 | ||
8c3dd61c KHF |
3859 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3860 | /* this will fail for cards that aren't VGA class devices, just | |
3861 | * ignore it */ | |
3862 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) | |
bf44e8ce | 3863 | vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); |
8c3dd61c KHF |
3864 | |
3865 | if (amdgpu_device_supports_px(ddev)) { | |
3866 | px = true; | |
3867 | vga_switcheroo_register_client(adev->pdev, | |
3868 | &amdgpu_switcheroo_ops, px); | |
3869 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
3870 | } | |
3871 | ||
e3c1b071 | 3872 | if (adev->gmc.xgmi.pending_reset) |
3873 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
3874 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3875 | ||
4a74c38c PY |
3876 | amdgpu_device_check_iommu_direct_map(adev); |
3877 | ||
d38ceaf9 | 3878 | return 0; |
83ba126a | 3879 | |
970fd197 SY |
3880 | release_ras_con: |
3881 | amdgpu_release_ras_context(adev); | |
3882 | ||
83ba126a | 3883 | failed: |
89041940 | 3884 | amdgpu_vf_error_trans_all(adev); |
8840a387 | 3885 | |
83ba126a | 3886 | return r; |
d38ceaf9 AD |
3887 | } |
3888 | ||
07775fc1 AG |
3889 | static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) |
3890 | { | |
62d5f9f7 | 3891 | |
07775fc1 AG |
3892 | /* Clear all CPU mappings pointing to this device */ |
3893 | unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); | |
3894 | ||
3895 | /* Unmap all mapped bars - Doorbell, registers and VRAM */ | |
3896 | amdgpu_device_doorbell_fini(adev); | |
3897 | ||
3898 | iounmap(adev->rmmio); | |
3899 | adev->rmmio = NULL; | |
3900 | if (adev->mman.aper_base_kaddr) | |
3901 | iounmap(adev->mman.aper_base_kaddr); | |
3902 | adev->mman.aper_base_kaddr = NULL; | |
3903 | ||
3904 | /* Memory manager related */ | |
3905 | if (!adev->gmc.xgmi.connected_to_cpu) { | |
3906 | arch_phys_wc_del(adev->gmc.vram_mtrr); | |
3907 | arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); | |
3908 | } | |
3909 | } | |
3910 | ||
d38ceaf9 | 3911 | /** |
bbe04dec | 3912 | * amdgpu_device_fini_hw - tear down the driver |
d38ceaf9 AD |
3913 | * |
3914 | * @adev: amdgpu_device pointer | |
3915 | * | |
3916 | * Tear down the driver info (all asics). | |
3917 | * Called at driver shutdown. | |
3918 | */ | |
72c8c97b | 3919 | void amdgpu_device_fini_hw(struct amdgpu_device *adev) |
d38ceaf9 | 3920 | { |
aac89168 | 3921 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3922 | flush_delayed_work(&adev->delayed_init_work); |
d0d13fe8 | 3923 | adev->shutdown = true; |
9f875167 | 3924 | |
752c683d ML |
3925 | /* make sure IB test finished before entering exclusive mode |
3926 | * to avoid preemption on IB test | |
3927 | * */ | |
519b8b76 | 3928 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 3929 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
3930 | amdgpu_virt_fini_data_exchange(adev); |
3931 | } | |
752c683d | 3932 | |
e5b03032 ML |
3933 | /* disable all interrupts */ |
3934 | amdgpu_irq_disable_all(adev); | |
ff97cba8 | 3935 | if (adev->mode_info.mode_config_initialized){ |
1053b9c9 | 3936 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) |
4a580877 | 3937 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3938 | else |
4a580877 | 3939 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3940 | } |
8d35a259 | 3941 | amdgpu_fence_driver_hw_fini(adev); |
72c8c97b | 3942 | |
98f56188 YY |
3943 | if (adev->mman.initialized) { |
3944 | flush_delayed_work(&adev->mman.bdev.wq); | |
3945 | ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
3946 | } | |
3947 | ||
7c868b59 YT |
3948 | if (adev->pm_sysfs_en) |
3949 | amdgpu_pm_sysfs_fini(adev); | |
72c8c97b AG |
3950 | if (adev->ucode_sysfs_en) |
3951 | amdgpu_ucode_sysfs_fini(adev); | |
8424f2cc LG |
3952 | if (adev->psp_sysfs_en) |
3953 | amdgpu_psp_sysfs_fini(adev); | |
72c8c97b AG |
3954 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); |
3955 | ||
232d1d43 SY |
3956 | /* disable ras feature must before hw fini */ |
3957 | amdgpu_ras_pre_fini(adev); | |
3958 | ||
e9669fb7 | 3959 | amdgpu_device_ip_fini_early(adev); |
d10d0daa | 3960 | |
a3848df6 YW |
3961 | amdgpu_irq_fini_hw(adev); |
3962 | ||
b6fd6e0f SK |
3963 | if (adev->mman.initialized) |
3964 | ttm_device_clear_dma_mappings(&adev->mman.bdev); | |
894c6890 | 3965 | |
d10d0daa | 3966 | amdgpu_gart_dummy_page_fini(adev); |
07775fc1 | 3967 | |
87172e89 LS |
3968 | if (drm_dev_is_unplugged(adev_to_drm(adev))) |
3969 | amdgpu_device_unmap_mmio(adev); | |
3970 | ||
72c8c97b AG |
3971 | } |
3972 | ||
3973 | void amdgpu_device_fini_sw(struct amdgpu_device *adev) | |
3974 | { | |
62d5f9f7 LS |
3975 | int idx; |
3976 | ||
8d35a259 | 3977 | amdgpu_fence_driver_sw_fini(adev); |
a5c5d8d5 | 3978 | amdgpu_device_ip_fini(adev); |
75e1658e ND |
3979 | release_firmware(adev->firmware.gpu_info_fw); |
3980 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 | 3981 | adev->accel_working = false; |
04442bf7 LL |
3982 | |
3983 | amdgpu_reset_fini(adev); | |
3984 | ||
d38ceaf9 | 3985 | /* free i2c buses */ |
4562236b HW |
3986 | if (!amdgpu_device_has_dc_support(adev)) |
3987 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3988 | |
3989 | if (amdgpu_emu_mode != 1) | |
3990 | amdgpu_atombios_fini(adev); | |
3991 | ||
d38ceaf9 AD |
3992 | kfree(adev->bios); |
3993 | adev->bios = NULL; | |
b98c6299 | 3994 | if (amdgpu_device_supports_px(adev_to_drm(adev))) { |
84c8b22e | 3995 | vga_switcheroo_unregister_client(adev->pdev); |
83ba126a | 3996 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
b98c6299 | 3997 | } |
38d6be81 | 3998 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
b8779475 | 3999 | vga_client_unregister(adev->pdev); |
e9bc1bf7 | 4000 | |
62d5f9f7 LS |
4001 | if (drm_dev_enter(adev_to_drm(adev), &idx)) { |
4002 | ||
4003 | iounmap(adev->rmmio); | |
4004 | adev->rmmio = NULL; | |
4005 | amdgpu_device_doorbell_fini(adev); | |
4006 | drm_dev_exit(idx); | |
4007 | } | |
4008 | ||
d155bef0 AB |
4009 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
4010 | amdgpu_pmu_fini(adev); | |
72de33f8 | 4011 | if (adev->mman.discovery_bin) |
a190d1c7 | 4012 | amdgpu_discovery_fini(adev); |
72c8c97b | 4013 | |
cfbb6b00 AG |
4014 | amdgpu_reset_put_reset_domain(adev->reset_domain); |
4015 | adev->reset_domain = NULL; | |
4016 | ||
72c8c97b AG |
4017 | kfree(adev->pci_state); |
4018 | ||
d38ceaf9 AD |
4019 | } |
4020 | ||
58144d28 ND |
4021 | /** |
4022 | * amdgpu_device_evict_resources - evict device resources | |
4023 | * @adev: amdgpu device object | |
4024 | * | |
4025 | * Evicts all ttm device resources(vram BOs, gart table) from the lru list | |
4026 | * of the vram memory type. Mainly used for evicting device resources | |
4027 | * at suspend time. | |
4028 | * | |
4029 | */ | |
4030 | static void amdgpu_device_evict_resources(struct amdgpu_device *adev) | |
4031 | { | |
e53d9665 ML |
4032 | /* No need to evict vram on APUs for suspend to ram or s2idle */ |
4033 | if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU)) | |
58144d28 ND |
4034 | return; |
4035 | ||
4036 | if (amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM)) | |
4037 | DRM_WARN("evicting device resources failed\n"); | |
4038 | ||
4039 | } | |
d38ceaf9 AD |
4040 | |
4041 | /* | |
4042 | * Suspend & resume. | |
4043 | */ | |
4044 | /** | |
810ddc3a | 4045 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 4046 | * |
87e3f136 | 4047 | * @dev: drm dev pointer |
87e3f136 | 4048 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
4049 | * |
4050 | * Puts the hw in the suspend state (all asics). | |
4051 | * Returns 0 for success or an error on failure. | |
4052 | * Called at driver suspend. | |
4053 | */ | |
de185019 | 4054 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 4055 | { |
a2e15b0e | 4056 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 4057 | |
d38ceaf9 AD |
4058 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
4059 | return 0; | |
4060 | ||
44779b43 | 4061 | adev->in_suspend = true; |
3fa8f89d S |
4062 | |
4063 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3)) | |
4064 | DRM_WARN("smart shift update failed\n"); | |
4065 | ||
d38ceaf9 AD |
4066 | drm_kms_helper_poll_disable(dev); |
4067 | ||
5f818173 | 4068 | if (fbcon) |
087451f3 | 4069 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); |
5f818173 | 4070 | |
beff74bc | 4071 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 4072 | |
5e6932fe | 4073 | amdgpu_ras_suspend(adev); |
4074 | ||
2196927b | 4075 | amdgpu_device_ip_suspend_phase1(adev); |
fe1053b7 | 4076 | |
c004d44e | 4077 | if (!adev->in_s0ix) |
5d3a2d95 | 4078 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); |
94fa5660 | 4079 | |
58144d28 | 4080 | amdgpu_device_evict_resources(adev); |
d38ceaf9 | 4081 | |
8d35a259 | 4082 | amdgpu_fence_driver_hw_fini(adev); |
d38ceaf9 | 4083 | |
2196927b | 4084 | amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 4085 | |
d38ceaf9 AD |
4086 | return 0; |
4087 | } | |
4088 | ||
4089 | /** | |
810ddc3a | 4090 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 4091 | * |
87e3f136 | 4092 | * @dev: drm dev pointer |
87e3f136 | 4093 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
4094 | * |
4095 | * Bring the hw back to operating state (all asics). | |
4096 | * Returns 0 for success or an error on failure. | |
4097 | * Called at driver resume. | |
4098 | */ | |
de185019 | 4099 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 4100 | { |
1348969a | 4101 | struct amdgpu_device *adev = drm_to_adev(dev); |
03161a6e | 4102 | int r = 0; |
d38ceaf9 AD |
4103 | |
4104 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
4105 | return 0; | |
4106 | ||
62498733 | 4107 | if (adev->in_s0ix) |
bc143d8b | 4108 | amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry); |
628c36d7 | 4109 | |
d38ceaf9 | 4110 | /* post card */ |
39c640c0 | 4111 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 4112 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 4113 | if (r) |
aac89168 | 4114 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 4115 | } |
d38ceaf9 | 4116 | |
06ec9070 | 4117 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 4118 | if (r) { |
aac89168 | 4119 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 4120 | return r; |
e6707218 | 4121 | } |
8d35a259 | 4122 | amdgpu_fence_driver_hw_init(adev); |
5ceb54c6 | 4123 | |
06ec9070 | 4124 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 4125 | if (r) |
4d3b9ae5 | 4126 | return r; |
d38ceaf9 | 4127 | |
beff74bc AD |
4128 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
4129 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
4130 | ||
c004d44e | 4131 | if (!adev->in_s0ix) { |
5d3a2d95 AD |
4132 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); |
4133 | if (r) | |
4134 | return r; | |
4135 | } | |
756e6880 | 4136 | |
96a5d8d4 | 4137 | /* Make sure IB tests flushed */ |
beff74bc | 4138 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 4139 | |
a2e15b0e | 4140 | if (fbcon) |
087451f3 | 4141 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false); |
d38ceaf9 AD |
4142 | |
4143 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 4144 | |
5e6932fe | 4145 | amdgpu_ras_resume(adev); |
4146 | ||
23a1a9e5 L |
4147 | /* |
4148 | * Most of the connector probing functions try to acquire runtime pm | |
4149 | * refs to ensure that the GPU is powered on when connector polling is | |
4150 | * performed. Since we're calling this from a runtime PM callback, | |
4151 | * trying to acquire rpm refs will cause us to deadlock. | |
4152 | * | |
4153 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
4154 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
4155 | */ | |
4156 | #ifdef CONFIG_PM | |
4157 | dev->dev->power.disable_depth++; | |
4158 | #endif | |
4562236b HW |
4159 | if (!amdgpu_device_has_dc_support(adev)) |
4160 | drm_helper_hpd_irq_event(dev); | |
4161 | else | |
4162 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
4163 | #ifdef CONFIG_PM |
4164 | dev->dev->power.disable_depth--; | |
4165 | #endif | |
44779b43 RZ |
4166 | adev->in_suspend = false; |
4167 | ||
3fa8f89d S |
4168 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0)) |
4169 | DRM_WARN("smart shift update failed\n"); | |
4170 | ||
4d3b9ae5 | 4171 | return 0; |
d38ceaf9 AD |
4172 | } |
4173 | ||
e3ecdffa AD |
4174 | /** |
4175 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
4176 | * | |
4177 | * @adev: amdgpu_device pointer | |
4178 | * | |
4179 | * The list of all the hardware IPs that make up the asic is walked and | |
4180 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
4181 | * if the asic is still hung or not. | |
4182 | * Returns true if any of the IPs are still in a hung state, false if not. | |
4183 | */ | |
06ec9070 | 4184 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
4185 | { |
4186 | int i; | |
4187 | bool asic_hang = false; | |
4188 | ||
f993d628 ML |
4189 | if (amdgpu_sriov_vf(adev)) |
4190 | return true; | |
4191 | ||
8bc04c29 AD |
4192 | if (amdgpu_asic_need_full_reset(adev)) |
4193 | return true; | |
4194 | ||
63fbf42f | 4195 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4196 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 4197 | continue; |
a1255107 AD |
4198 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
4199 | adev->ip_blocks[i].status.hang = | |
4200 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
4201 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 4202 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
4203 | asic_hang = true; |
4204 | } | |
4205 | } | |
4206 | return asic_hang; | |
4207 | } | |
4208 | ||
e3ecdffa AD |
4209 | /** |
4210 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
4211 | * | |
4212 | * @adev: amdgpu_device pointer | |
4213 | * | |
4214 | * The list of all the hardware IPs that make up the asic is walked and the | |
4215 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
4216 | * handles any IP specific hardware or software state changes that are | |
4217 | * necessary for a soft reset to succeed. | |
4218 | * Returns 0 on success, negative error code on failure. | |
4219 | */ | |
06ec9070 | 4220 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
4221 | { |
4222 | int i, r = 0; | |
4223 | ||
4224 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4225 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 4226 | continue; |
a1255107 AD |
4227 | if (adev->ip_blocks[i].status.hang && |
4228 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
4229 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
4230 | if (r) |
4231 | return r; | |
4232 | } | |
4233 | } | |
4234 | ||
4235 | return 0; | |
4236 | } | |
4237 | ||
e3ecdffa AD |
4238 | /** |
4239 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
4240 | * | |
4241 | * @adev: amdgpu_device pointer | |
4242 | * | |
4243 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
4244 | * reset is necessary to recover. | |
4245 | * Returns true if a full asic reset is required, false if not. | |
4246 | */ | |
06ec9070 | 4247 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 4248 | { |
da146d3b AD |
4249 | int i; |
4250 | ||
8bc04c29 AD |
4251 | if (amdgpu_asic_need_full_reset(adev)) |
4252 | return true; | |
4253 | ||
da146d3b | 4254 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4255 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 4256 | continue; |
a1255107 AD |
4257 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
4258 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
4259 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
4260 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
4261 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 4262 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 4263 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
4264 | return true; |
4265 | } | |
4266 | } | |
35d782fe CZ |
4267 | } |
4268 | return false; | |
4269 | } | |
4270 | ||
e3ecdffa AD |
4271 | /** |
4272 | * amdgpu_device_ip_soft_reset - do a soft reset | |
4273 | * | |
4274 | * @adev: amdgpu_device pointer | |
4275 | * | |
4276 | * The list of all the hardware IPs that make up the asic is walked and the | |
4277 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
4278 | * IP specific hardware or software state changes that are necessary to soft | |
4279 | * reset the IP. | |
4280 | * Returns 0 on success, negative error code on failure. | |
4281 | */ | |
06ec9070 | 4282 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4283 | { |
4284 | int i, r = 0; | |
4285 | ||
4286 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4287 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4288 | continue; |
a1255107 AD |
4289 | if (adev->ip_blocks[i].status.hang && |
4290 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
4291 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
4292 | if (r) |
4293 | return r; | |
4294 | } | |
4295 | } | |
4296 | ||
4297 | return 0; | |
4298 | } | |
4299 | ||
e3ecdffa AD |
4300 | /** |
4301 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
4302 | * | |
4303 | * @adev: amdgpu_device pointer | |
4304 | * | |
4305 | * The list of all the hardware IPs that make up the asic is walked and the | |
4306 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
4307 | * handles any IP specific hardware or software state changes that are | |
4308 | * necessary after the IP has been soft reset. | |
4309 | * Returns 0 on success, negative error code on failure. | |
4310 | */ | |
06ec9070 | 4311 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4312 | { |
4313 | int i, r = 0; | |
4314 | ||
4315 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4316 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4317 | continue; |
a1255107 AD |
4318 | if (adev->ip_blocks[i].status.hang && |
4319 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
4320 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
4321 | if (r) |
4322 | return r; | |
4323 | } | |
4324 | ||
4325 | return 0; | |
4326 | } | |
4327 | ||
e3ecdffa | 4328 | /** |
c33adbc7 | 4329 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4330 | * |
4331 | * @adev: amdgpu_device pointer | |
4332 | * | |
4333 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4334 | * restore things like GPUVM page tables after a GPU reset where | |
4335 | * the contents of VRAM might be lost. | |
403009bf CK |
4336 | * |
4337 | * Returns: | |
4338 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4339 | */ |
c33adbc7 | 4340 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4341 | { |
c41d1cf6 | 4342 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf | 4343 | struct amdgpu_bo *shadow; |
e18aaea7 | 4344 | struct amdgpu_bo_vm *vmbo; |
403009bf | 4345 | long r = 1, tmo; |
c41d1cf6 ML |
4346 | |
4347 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4348 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4349 | else |
4350 | tmo = msecs_to_jiffies(100); | |
4351 | ||
aac89168 | 4352 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4353 | mutex_lock(&adev->shadow_list_lock); |
e18aaea7 ND |
4354 | list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { |
4355 | shadow = &vmbo->bo; | |
403009bf | 4356 | /* No need to recover an evicted BO */ |
d3116756 CK |
4357 | if (shadow->tbo.resource->mem_type != TTM_PL_TT || |
4358 | shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || | |
4359 | shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) | |
403009bf CK |
4360 | continue; |
4361 | ||
4362 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4363 | if (r) | |
4364 | break; | |
4365 | ||
c41d1cf6 | 4366 | if (fence) { |
1712fb1a | 4367 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4368 | dma_fence_put(fence); |
4369 | fence = next; | |
1712fb1a | 4370 | if (tmo == 0) { |
4371 | r = -ETIMEDOUT; | |
c41d1cf6 | 4372 | break; |
1712fb1a | 4373 | } else if (tmo < 0) { |
4374 | r = tmo; | |
4375 | break; | |
4376 | } | |
403009bf CK |
4377 | } else { |
4378 | fence = next; | |
c41d1cf6 | 4379 | } |
c41d1cf6 ML |
4380 | } |
4381 | mutex_unlock(&adev->shadow_list_lock); | |
4382 | ||
403009bf CK |
4383 | if (fence) |
4384 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4385 | dma_fence_put(fence); |
4386 | ||
1712fb1a | 4387 | if (r < 0 || tmo <= 0) { |
aac89168 | 4388 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4389 | return -EIO; |
4390 | } | |
c41d1cf6 | 4391 | |
aac89168 | 4392 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4393 | return 0; |
c41d1cf6 ML |
4394 | } |
4395 | ||
a90ad3c2 | 4396 | |
e3ecdffa | 4397 | /** |
06ec9070 | 4398 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4399 | * |
982a820b | 4400 | * @adev: amdgpu_device pointer |
87e3f136 | 4401 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4402 | * |
4403 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4404 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4405 | */ |
4406 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4407 | bool from_hypervisor) | |
5740682e ML |
4408 | { |
4409 | int r; | |
a5f67c93 | 4410 | struct amdgpu_hive_info *hive = NULL; |
7258fa31 | 4411 | int retry_limit = 0; |
5740682e | 4412 | |
7258fa31 | 4413 | retry: |
c004d44e | 4414 | amdgpu_amdkfd_pre_reset(adev); |
5740682e | 4415 | |
428890a3 | 4416 | amdgpu_amdkfd_pre_reset(adev); |
4417 | ||
5740682e ML |
4418 | if (from_hypervisor) |
4419 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4420 | else | |
4421 | r = amdgpu_virt_reset_gpu(adev); | |
4422 | if (r) | |
4423 | return r; | |
a90ad3c2 ML |
4424 | |
4425 | /* Resume IP prior to SMC */ | |
06ec9070 | 4426 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4427 | if (r) |
4428 | goto error; | |
a90ad3c2 | 4429 | |
c9ffa427 | 4430 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4431 | |
7a3e0bb2 RZ |
4432 | r = amdgpu_device_fw_loading(adev); |
4433 | if (r) | |
4434 | return r; | |
4435 | ||
a90ad3c2 | 4436 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4437 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4438 | if (r) |
4439 | goto error; | |
a90ad3c2 | 4440 | |
a5f67c93 ZL |
4441 | hive = amdgpu_get_xgmi_hive(adev); |
4442 | /* Update PSP FW topology after reset */ | |
4443 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) | |
4444 | r = amdgpu_xgmi_update_topology(hive, adev); | |
4445 | ||
4446 | if (hive) | |
4447 | amdgpu_put_xgmi_hive(hive); | |
4448 | ||
4449 | if (!r) { | |
4450 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
4451 | r = amdgpu_ib_ring_tests(adev); | |
9c12f5cd | 4452 | |
c004d44e | 4453 | amdgpu_amdkfd_post_reset(adev); |
a5f67c93 | 4454 | } |
a90ad3c2 | 4455 | |
abc34253 | 4456 | error: |
c41d1cf6 | 4457 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 4458 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 4459 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 | 4460 | } |
437f3e0b | 4461 | amdgpu_virt_release_full_gpu(adev, true); |
a90ad3c2 | 4462 | |
7258fa31 SK |
4463 | if (AMDGPU_RETRY_SRIOV_RESET(r)) { |
4464 | if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) { | |
4465 | retry_limit++; | |
4466 | goto retry; | |
4467 | } else | |
4468 | DRM_ERROR("GPU reset retry is beyond the retry limit\n"); | |
4469 | } | |
4470 | ||
a90ad3c2 ML |
4471 | return r; |
4472 | } | |
4473 | ||
9a1cddd6 | 4474 | /** |
4475 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
4476 | * | |
982a820b | 4477 | * @adev: amdgpu_device pointer |
9a1cddd6 | 4478 | * |
4479 | * check if there is any job in mirror list | |
4480 | */ | |
4481 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
4482 | { | |
4483 | int i; | |
4484 | struct drm_sched_job *job; | |
4485 | ||
4486 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4487 | struct amdgpu_ring *ring = adev->rings[i]; | |
4488 | ||
4489 | if (!ring || !ring->sched.thread) | |
4490 | continue; | |
4491 | ||
4492 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
4493 | job = list_first_entry_or_null(&ring->sched.pending_list, |
4494 | struct drm_sched_job, list); | |
9a1cddd6 | 4495 | spin_unlock(&ring->sched.job_list_lock); |
4496 | if (job) | |
4497 | return true; | |
4498 | } | |
4499 | return false; | |
4500 | } | |
4501 | ||
12938fad CK |
4502 | /** |
4503 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
4504 | * | |
982a820b | 4505 | * @adev: amdgpu_device pointer |
12938fad CK |
4506 | * |
4507 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
4508 | * a hung GPU. | |
4509 | */ | |
4510 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
4511 | { | |
4512 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4513 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
4514 | return false; |
4515 | } | |
4516 | ||
3ba7b418 AG |
4517 | if (amdgpu_gpu_recovery == 0) |
4518 | goto disabled; | |
4519 | ||
4520 | if (amdgpu_sriov_vf(adev)) | |
4521 | return true; | |
4522 | ||
4523 | if (amdgpu_gpu_recovery == -1) { | |
4524 | switch (adev->asic_type) { | |
b3523c45 AD |
4525 | #ifdef CONFIG_DRM_AMDGPU_SI |
4526 | case CHIP_VERDE: | |
4527 | case CHIP_TAHITI: | |
4528 | case CHIP_PITCAIRN: | |
4529 | case CHIP_OLAND: | |
4530 | case CHIP_HAINAN: | |
4531 | #endif | |
4532 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
4533 | case CHIP_KAVERI: | |
4534 | case CHIP_KABINI: | |
4535 | case CHIP_MULLINS: | |
4536 | #endif | |
4537 | case CHIP_CARRIZO: | |
4538 | case CHIP_STONEY: | |
4539 | case CHIP_CYAN_SKILLFISH: | |
3ba7b418 | 4540 | goto disabled; |
b3523c45 AD |
4541 | default: |
4542 | break; | |
3ba7b418 | 4543 | } |
12938fad CK |
4544 | } |
4545 | ||
4546 | return true; | |
3ba7b418 AG |
4547 | |
4548 | disabled: | |
aac89168 | 4549 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4550 | return false; |
12938fad CK |
4551 | } |
4552 | ||
5c03e584 FX |
4553 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
4554 | { | |
4555 | u32 i; | |
4556 | int ret = 0; | |
4557 | ||
4558 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
4559 | ||
4560 | dev_info(adev->dev, "GPU mode1 reset\n"); | |
4561 | ||
4562 | /* disable BM */ | |
4563 | pci_clear_master(adev->pdev); | |
4564 | ||
4565 | amdgpu_device_cache_pci_state(adev->pdev); | |
4566 | ||
4567 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
4568 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
4569 | ret = amdgpu_dpm_mode1_reset(adev); | |
4570 | } else { | |
4571 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
4572 | ret = psp_gpu_reset(adev); | |
4573 | } | |
4574 | ||
4575 | if (ret) | |
4576 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
4577 | ||
4578 | amdgpu_device_load_pci_state(adev->pdev); | |
4579 | ||
4580 | /* wait for asic to come out of reset */ | |
4581 | for (i = 0; i < adev->usec_timeout; i++) { | |
4582 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
4583 | ||
4584 | if (memsize != 0xffffffff) | |
4585 | break; | |
4586 | udelay(1); | |
4587 | } | |
4588 | ||
4589 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
4590 | return ret; | |
4591 | } | |
5c6dd71e | 4592 | |
e3c1b071 | 4593 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
04442bf7 | 4594 | struct amdgpu_reset_context *reset_context) |
26bc5340 | 4595 | { |
5c1e6fa4 | 4596 | int i, r = 0; |
04442bf7 LL |
4597 | struct amdgpu_job *job = NULL; |
4598 | bool need_full_reset = | |
4599 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4600 | ||
4601 | if (reset_context->reset_req_dev == adev) | |
4602 | job = reset_context->job; | |
71182665 | 4603 | |
b602ca5f TZ |
4604 | if (amdgpu_sriov_vf(adev)) { |
4605 | /* stop the data exchange thread */ | |
4606 | amdgpu_virt_fini_data_exchange(adev); | |
4607 | } | |
4608 | ||
9e225fb9 AG |
4609 | amdgpu_fence_driver_isr_toggle(adev, true); |
4610 | ||
71182665 | 4611 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4612 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4613 | struct amdgpu_ring *ring = adev->rings[i]; | |
4614 | ||
51687759 | 4615 | if (!ring || !ring->sched.thread) |
0875dc9e | 4616 | continue; |
5740682e | 4617 | |
c530b02f JZ |
4618 | /*clear job fence from fence drv to avoid force_completion |
4619 | *leave NULL and vm flush fence in fence drv */ | |
5c1e6fa4 | 4620 | amdgpu_fence_driver_clear_job_fences(ring); |
c530b02f | 4621 | |
2f9d4084 ML |
4622 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4623 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4624 | } |
d38ceaf9 | 4625 | |
9e225fb9 AG |
4626 | amdgpu_fence_driver_isr_toggle(adev, false); |
4627 | ||
ff99849b | 4628 | if (job && job->vm) |
222b5f04 AG |
4629 | drm_sched_increase_karma(&job->base); |
4630 | ||
04442bf7 | 4631 | r = amdgpu_reset_prepare_hwcontext(adev, reset_context); |
404b277b LL |
4632 | /* If reset handler not implemented, continue; otherwise return */ |
4633 | if (r == -ENOSYS) | |
4634 | r = 0; | |
4635 | else | |
04442bf7 LL |
4636 | return r; |
4637 | ||
1d721ed6 | 4638 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4639 | if (!amdgpu_sriov_vf(adev)) { |
4640 | ||
4641 | if (!need_full_reset) | |
4642 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4643 | ||
4644 | if (!need_full_reset) { | |
4645 | amdgpu_device_ip_pre_soft_reset(adev); | |
4646 | r = amdgpu_device_ip_soft_reset(adev); | |
4647 | amdgpu_device_ip_post_soft_reset(adev); | |
4648 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4649 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4650 | need_full_reset = true; |
4651 | } | |
4652 | } | |
4653 | ||
4654 | if (need_full_reset) | |
4655 | r = amdgpu_device_ip_suspend(adev); | |
04442bf7 LL |
4656 | if (need_full_reset) |
4657 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4658 | else | |
4659 | clear_bit(AMDGPU_NEED_FULL_RESET, | |
4660 | &reset_context->flags); | |
26bc5340 AG |
4661 | } |
4662 | ||
4663 | return r; | |
4664 | } | |
4665 | ||
15fd09a0 SA |
4666 | static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev) |
4667 | { | |
15fd09a0 SA |
4668 | int i; |
4669 | ||
38a15ad9 | 4670 | lockdep_assert_held(&adev->reset_domain->sem); |
15fd09a0 SA |
4671 | dump_stack(); |
4672 | ||
4673 | for (i = 0; i < adev->num_regs; i++) { | |
651d7ee6 SA |
4674 | adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]); |
4675 | trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], | |
4676 | adev->reset_dump_reg_value[i]); | |
15fd09a0 SA |
4677 | } |
4678 | ||
4679 | return 0; | |
4680 | } | |
4681 | ||
3d8785f6 SA |
4682 | #ifdef CONFIG_DEV_COREDUMP |
4683 | static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset, | |
4684 | size_t count, void *data, size_t datalen) | |
4685 | { | |
4686 | struct drm_printer p; | |
4687 | struct amdgpu_device *adev = data; | |
4688 | struct drm_print_iterator iter; | |
4689 | int i; | |
4690 | ||
4691 | iter.data = buffer; | |
4692 | iter.offset = 0; | |
4693 | iter.start = offset; | |
4694 | iter.remain = count; | |
4695 | ||
4696 | p = drm_coredump_printer(&iter); | |
4697 | ||
4698 | drm_printf(&p, "**** AMDGPU Device Coredump ****\n"); | |
4699 | drm_printf(&p, "kernel: " UTS_RELEASE "\n"); | |
4700 | drm_printf(&p, "module: " KBUILD_MODNAME "\n"); | |
4701 | drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec); | |
4702 | if (adev->reset_task_info.pid) | |
4703 | drm_printf(&p, "process_name: %s PID: %d\n", | |
4704 | adev->reset_task_info.process_name, | |
4705 | adev->reset_task_info.pid); | |
4706 | ||
4707 | if (adev->reset_vram_lost) | |
4708 | drm_printf(&p, "VRAM is lost due to GPU reset!\n"); | |
4709 | if (adev->num_regs) { | |
4710 | drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n"); | |
4711 | ||
4712 | for (i = 0; i < adev->num_regs; i++) | |
4713 | drm_printf(&p, "0x%08x: 0x%08x\n", | |
4714 | adev->reset_dump_reg_list[i], | |
4715 | adev->reset_dump_reg_value[i]); | |
4716 | } | |
4717 | ||
4718 | return count - iter.remain; | |
4719 | } | |
4720 | ||
4721 | static void amdgpu_devcoredump_free(void *data) | |
4722 | { | |
4723 | } | |
4724 | ||
4725 | static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev) | |
4726 | { | |
4727 | struct drm_device *dev = adev_to_drm(adev); | |
4728 | ||
4729 | ktime_get_ts64(&adev->reset_time); | |
4730 | dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL, | |
4731 | amdgpu_devcoredump_read, amdgpu_devcoredump_free); | |
4732 | } | |
4733 | #endif | |
4734 | ||
04442bf7 LL |
4735 | int amdgpu_do_asic_reset(struct list_head *device_list_handle, |
4736 | struct amdgpu_reset_context *reset_context) | |
26bc5340 AG |
4737 | { |
4738 | struct amdgpu_device *tmp_adev = NULL; | |
04442bf7 | 4739 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
26bc5340 AG |
4740 | int r = 0; |
4741 | ||
04442bf7 LL |
4742 | /* Try reset handler method first */ |
4743 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
4744 | reset_list); | |
15fd09a0 | 4745 | amdgpu_reset_reg_dumps(tmp_adev); |
04442bf7 | 4746 | r = amdgpu_reset_perform_reset(tmp_adev, reset_context); |
404b277b LL |
4747 | /* If reset handler not implemented, continue; otherwise return */ |
4748 | if (r == -ENOSYS) | |
4749 | r = 0; | |
4750 | else | |
04442bf7 LL |
4751 | return r; |
4752 | ||
4753 | /* Reset handler not implemented, use the default method */ | |
4754 | need_full_reset = | |
4755 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4756 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); | |
4757 | ||
26bc5340 | 4758 | /* |
655ce9cb | 4759 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
4760 | * to allow proper links negotiation in FW (within 1 sec) |
4761 | */ | |
7ac71382 | 4762 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 4763 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 4764 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4765 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 4766 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 4767 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4768 | r = -EALREADY; |
4769 | } else | |
4770 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4771 | |
041a62bc | 4772 | if (r) { |
aac89168 | 4773 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4774 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4775 | break; |
ce316fa5 LM |
4776 | } |
4777 | } | |
4778 | ||
041a62bc AG |
4779 | /* For XGMI wait for all resets to complete before proceed */ |
4780 | if (!r) { | |
655ce9cb | 4781 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
4782 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
4783 | flush_work(&tmp_adev->xgmi_reset_work); | |
4784 | r = tmp_adev->asic_reset_res; | |
4785 | if (r) | |
4786 | break; | |
ce316fa5 LM |
4787 | } |
4788 | } | |
4789 | } | |
ce316fa5 | 4790 | } |
26bc5340 | 4791 | |
43c4d576 | 4792 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 4793 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
5e67bba3 | 4794 | if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops && |
4795 | tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) | |
4796 | tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev); | |
43c4d576 JC |
4797 | } |
4798 | ||
00eaa571 | 4799 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4800 | } |
00eaa571 | 4801 | |
655ce9cb | 4802 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
4803 | if (need_full_reset) { |
4804 | /* post card */ | |
e3c1b071 | 4805 | r = amdgpu_device_asic_init(tmp_adev); |
4806 | if (r) { | |
aac89168 | 4807 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 4808 | } else { |
26bc5340 | 4809 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
9cec53c1 JZ |
4810 | r = amdgpu_amdkfd_resume_iommu(tmp_adev); |
4811 | if (r) | |
4812 | goto out; | |
4813 | ||
26bc5340 AG |
4814 | r = amdgpu_device_ip_resume_phase1(tmp_adev); |
4815 | if (r) | |
4816 | goto out; | |
4817 | ||
4818 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
3d8785f6 SA |
4819 | #ifdef CONFIG_DEV_COREDUMP |
4820 | tmp_adev->reset_vram_lost = vram_lost; | |
4821 | memset(&tmp_adev->reset_task_info, 0, | |
4822 | sizeof(tmp_adev->reset_task_info)); | |
4823 | if (reset_context->job && reset_context->job->vm) | |
4824 | tmp_adev->reset_task_info = | |
4825 | reset_context->job->vm->task_info; | |
4826 | amdgpu_reset_capture_coredumpm(tmp_adev); | |
4827 | #endif | |
26bc5340 | 4828 | if (vram_lost) { |
77e7f829 | 4829 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4830 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4831 | } |
4832 | ||
26bc5340 AG |
4833 | r = amdgpu_device_fw_loading(tmp_adev); |
4834 | if (r) | |
4835 | return r; | |
4836 | ||
4837 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4838 | if (r) | |
4839 | goto out; | |
4840 | ||
4841 | if (vram_lost) | |
4842 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4843 | ||
fdafb359 EQ |
4844 | /* |
4845 | * Add this ASIC as tracked as reset was already | |
4846 | * complete successfully. | |
4847 | */ | |
4848 | amdgpu_register_gpu_instance(tmp_adev); | |
4849 | ||
04442bf7 LL |
4850 | if (!reset_context->hive && |
4851 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
e3c1b071 | 4852 | amdgpu_xgmi_add_device(tmp_adev); |
4853 | ||
7c04ca50 | 4854 | r = amdgpu_device_ip_late_init(tmp_adev); |
4855 | if (r) | |
4856 | goto out; | |
4857 | ||
087451f3 | 4858 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false); |
565d1941 | 4859 | |
e8fbaf03 GC |
4860 | /* |
4861 | * The GPU enters bad state once faulty pages | |
4862 | * by ECC has reached the threshold, and ras | |
4863 | * recovery is scheduled next. So add one check | |
4864 | * here to break recovery if it indeed exceeds | |
4865 | * bad page threshold, and remind user to | |
4866 | * retire this GPU or setting one bigger | |
4867 | * bad_page_threshold value to fix this once | |
4868 | * probing driver again. | |
4869 | */ | |
11003c68 | 4870 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
4871 | /* must succeed. */ |
4872 | amdgpu_ras_resume(tmp_adev); | |
4873 | } else { | |
4874 | r = -EINVAL; | |
4875 | goto out; | |
4876 | } | |
e79a04d5 | 4877 | |
26bc5340 | 4878 | /* Update PSP FW topology after reset */ |
04442bf7 LL |
4879 | if (reset_context->hive && |
4880 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4881 | r = amdgpu_xgmi_update_topology( | |
4882 | reset_context->hive, tmp_adev); | |
26bc5340 AG |
4883 | } |
4884 | } | |
4885 | ||
26bc5340 AG |
4886 | out: |
4887 | if (!r) { | |
4888 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4889 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4890 | if (r) { | |
4891 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
26bc5340 AG |
4892 | need_full_reset = true; |
4893 | r = -EAGAIN; | |
4894 | goto end; | |
4895 | } | |
4896 | } | |
4897 | ||
4898 | if (!r) | |
4899 | r = amdgpu_device_recover_vram(tmp_adev); | |
4900 | else | |
4901 | tmp_adev->asic_reset_res = r; | |
4902 | } | |
4903 | ||
4904 | end: | |
04442bf7 LL |
4905 | if (need_full_reset) |
4906 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4907 | else | |
4908 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 AG |
4909 | return r; |
4910 | } | |
4911 | ||
e923be99 | 4912 | static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev) |
26bc5340 | 4913 | { |
5740682e | 4914 | |
a3a09142 AD |
4915 | switch (amdgpu_asic_reset_method(adev)) { |
4916 | case AMD_RESET_METHOD_MODE1: | |
4917 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4918 | break; | |
4919 | case AMD_RESET_METHOD_MODE2: | |
4920 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4921 | break; | |
4922 | default: | |
4923 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4924 | break; | |
4925 | } | |
26bc5340 | 4926 | } |
d38ceaf9 | 4927 | |
e923be99 | 4928 | static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev) |
26bc5340 | 4929 | { |
89041940 | 4930 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4931 | adev->mp1_state = PP_MP1_STATE_NONE; |
91fb309d HC |
4932 | } |
4933 | ||
3f12acc8 EQ |
4934 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4935 | { | |
4936 | struct pci_dev *p = NULL; | |
4937 | ||
4938 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4939 | adev->pdev->bus->number, 1); | |
4940 | if (p) { | |
4941 | pm_runtime_enable(&(p->dev)); | |
4942 | pm_runtime_resume(&(p->dev)); | |
4943 | } | |
4944 | } | |
4945 | ||
4946 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4947 | { | |
4948 | enum amd_reset_method reset_method; | |
4949 | struct pci_dev *p = NULL; | |
4950 | u64 expires; | |
4951 | ||
4952 | /* | |
4953 | * For now, only BACO and mode1 reset are confirmed | |
4954 | * to suffer the audio issue without proper suspended. | |
4955 | */ | |
4956 | reset_method = amdgpu_asic_reset_method(adev); | |
4957 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4958 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4959 | return -EINVAL; | |
4960 | ||
4961 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4962 | adev->pdev->bus->number, 1); | |
4963 | if (!p) | |
4964 | return -ENODEV; | |
4965 | ||
4966 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4967 | if (!expires) | |
4968 | /* | |
4969 | * If we cannot get the audio device autosuspend delay, | |
4970 | * a fixed 4S interval will be used. Considering 3S is | |
4971 | * the audio controller default autosuspend delay setting. | |
4972 | * 4S used here is guaranteed to cover that. | |
4973 | */ | |
54b7feb9 | 4974 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4975 | |
4976 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4977 | if (!pm_runtime_suspend(&(p->dev))) | |
4978 | break; | |
4979 | ||
4980 | if (expires < ktime_get_mono_fast_ns()) { | |
4981 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4982 | /* TODO: abort the succeeding gpu reset? */ | |
4983 | return -ETIMEDOUT; | |
4984 | } | |
4985 | } | |
4986 | ||
4987 | pm_runtime_disable(&(p->dev)); | |
4988 | ||
4989 | return 0; | |
4990 | } | |
4991 | ||
9d8d96be | 4992 | static void amdgpu_device_recheck_guilty_jobs( |
04442bf7 LL |
4993 | struct amdgpu_device *adev, struct list_head *device_list_handle, |
4994 | struct amdgpu_reset_context *reset_context) | |
e6c6338f JZ |
4995 | { |
4996 | int i, r = 0; | |
4997 | ||
4998 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4999 | struct amdgpu_ring *ring = adev->rings[i]; | |
5000 | int ret = 0; | |
5001 | struct drm_sched_job *s_job; | |
5002 | ||
5003 | if (!ring || !ring->sched.thread) | |
5004 | continue; | |
5005 | ||
5006 | s_job = list_first_entry_or_null(&ring->sched.pending_list, | |
5007 | struct drm_sched_job, list); | |
5008 | if (s_job == NULL) | |
5009 | continue; | |
5010 | ||
5011 | /* clear job's guilty and depend the folowing step to decide the real one */ | |
5012 | drm_sched_reset_karma(s_job); | |
5013 | drm_sched_resubmit_jobs_ext(&ring->sched, 1); | |
5014 | ||
9ae55f03 AG |
5015 | if (!s_job->s_fence->parent) { |
5016 | DRM_WARN("Failed to get a HW fence for job!"); | |
5017 | continue; | |
5018 | } | |
5019 | ||
e6c6338f JZ |
5020 | ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout); |
5021 | if (ret == 0) { /* timeout */ | |
5022 | DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n", | |
5023 | ring->sched.name, s_job->id); | |
5024 | ||
9ae55f03 AG |
5025 | |
5026 | amdgpu_fence_driver_isr_toggle(adev, true); | |
5027 | ||
5028 | /* Clear this failed job from fence array */ | |
5029 | amdgpu_fence_driver_clear_job_fences(ring); | |
5030 | ||
5031 | amdgpu_fence_driver_isr_toggle(adev, false); | |
5032 | ||
5033 | /* Since the job won't signal and we go for | |
5034 | * another resubmit drop this parent pointer | |
5035 | */ | |
5036 | dma_fence_put(s_job->s_fence->parent); | |
5037 | s_job->s_fence->parent = NULL; | |
5038 | ||
e6c6338f JZ |
5039 | /* set guilty */ |
5040 | drm_sched_increase_karma(s_job); | |
5041 | retry: | |
5042 | /* do hw reset */ | |
5043 | if (amdgpu_sriov_vf(adev)) { | |
5044 | amdgpu_virt_fini_data_exchange(adev); | |
5045 | r = amdgpu_device_reset_sriov(adev, false); | |
5046 | if (r) | |
5047 | adev->asic_reset_res = r; | |
5048 | } else { | |
04442bf7 LL |
5049 | clear_bit(AMDGPU_SKIP_HW_RESET, |
5050 | &reset_context->flags); | |
5051 | r = amdgpu_do_asic_reset(device_list_handle, | |
5052 | reset_context); | |
e6c6338f JZ |
5053 | if (r && r == -EAGAIN) |
5054 | goto retry; | |
5055 | } | |
5056 | ||
5057 | /* | |
5058 | * add reset counter so that the following | |
5059 | * resubmitted job could flush vmid | |
5060 | */ | |
5061 | atomic_inc(&adev->gpu_reset_counter); | |
5062 | continue; | |
5063 | } | |
5064 | ||
5065 | /* got the hw fence, signal finished fence */ | |
5066 | atomic_dec(ring->sched.score); | |
5067 | dma_fence_get(&s_job->s_fence->finished); | |
5068 | dma_fence_signal(&s_job->s_fence->finished); | |
5069 | dma_fence_put(&s_job->s_fence->finished); | |
5070 | ||
5071 | /* remove node from list and free the job */ | |
5072 | spin_lock(&ring->sched.job_list_lock); | |
5073 | list_del_init(&s_job->list); | |
5074 | spin_unlock(&ring->sched.job_list_lock); | |
5075 | ring->sched.ops->free_job(s_job); | |
5076 | } | |
5077 | } | |
5078 | ||
d193b12b | 5079 | static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) |
247c7b0d AG |
5080 | { |
5081 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
5082 | ||
5083 | #if defined(CONFIG_DEBUG_FS) | |
5084 | if (!amdgpu_sriov_vf(adev)) | |
5085 | cancel_work(&adev->reset_work); | |
5086 | #endif | |
5087 | ||
5088 | if (adev->kfd.dev) | |
5089 | cancel_work(&adev->kfd.reset_work); | |
5090 | ||
5091 | if (amdgpu_sriov_vf(adev)) | |
5092 | cancel_work(&adev->virt.flr_work); | |
5093 | ||
5094 | if (con && adev->ras_enabled) | |
5095 | cancel_work(&con->recovery_work); | |
5096 | ||
5097 | } | |
5098 | ||
5099 | ||
26bc5340 | 5100 | /** |
c7703ce3 | 5101 | * amdgpu_device_gpu_recover_imp - reset the asic and recover scheduler |
26bc5340 | 5102 | * |
982a820b | 5103 | * @adev: amdgpu_device pointer |
26bc5340 AG |
5104 | * @job: which job trigger hang |
5105 | * | |
5106 | * Attempt to reset the GPU if it has hung (all asics). | |
5107 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
5108 | * Returns 0 for success or an error on failure. | |
5109 | */ | |
5110 | ||
cf727044 | 5111 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
26bc5340 AG |
5112 | struct amdgpu_job *job) |
5113 | { | |
1d721ed6 | 5114 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 | 5115 | bool job_signaled = false; |
26bc5340 | 5116 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 5117 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 5118 | int i, r = 0; |
bb5c7235 | 5119 | bool need_emergency_restart = false; |
3f12acc8 | 5120 | bool audio_suspended = false; |
e6c6338f | 5121 | int tmp_vram_lost_counter; |
04442bf7 LL |
5122 | struct amdgpu_reset_context reset_context; |
5123 | ||
5124 | memset(&reset_context, 0, sizeof(reset_context)); | |
26bc5340 | 5125 | |
6e3cd2a9 | 5126 | /* |
bb5c7235 WS |
5127 | * Special case: RAS triggered and full reset isn't supported |
5128 | */ | |
5129 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
5130 | ||
d5ea093e AG |
5131 | /* |
5132 | * Flush RAM to disk so that after reboot | |
5133 | * the user can read log and see why the system rebooted. | |
5134 | */ | |
bb5c7235 | 5135 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
5136 | DRM_WARN("Emergency reboot."); |
5137 | ||
5138 | ksys_sync_helper(); | |
5139 | emergency_restart(); | |
5140 | } | |
5141 | ||
b823821f | 5142 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 5143 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 | 5144 | |
175ac6ec ZL |
5145 | if (!amdgpu_sriov_vf(adev)) |
5146 | hive = amdgpu_get_xgmi_hive(adev); | |
681260df | 5147 | if (hive) |
53b3f8f4 | 5148 | mutex_lock(&hive->hive_lock); |
26bc5340 | 5149 | |
04442bf7 LL |
5150 | reset_context.method = AMD_RESET_METHOD_NONE; |
5151 | reset_context.reset_req_dev = adev; | |
5152 | reset_context.job = job; | |
5153 | reset_context.hive = hive; | |
5154 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5155 | ||
9e94d22c EQ |
5156 | /* |
5157 | * Build list of devices to reset. | |
5158 | * In case we are in XGMI hive mode, resort the device list | |
5159 | * to put adev in the 1st position. | |
5160 | */ | |
5161 | INIT_LIST_HEAD(&device_list); | |
175ac6ec | 5162 | if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) { |
655ce9cb | 5163 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) |
5164 | list_add_tail(&tmp_adev->reset_list, &device_list); | |
5165 | if (!list_is_first(&adev->reset_list, &device_list)) | |
5166 | list_rotate_to_front(&adev->reset_list, &device_list); | |
5167 | device_list_handle = &device_list; | |
26bc5340 | 5168 | } else { |
655ce9cb | 5169 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
5170 | device_list_handle = &device_list; |
5171 | } | |
5172 | ||
e923be99 AG |
5173 | /* We need to lock reset domain only once both for XGMI and single device */ |
5174 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
5175 | reset_list); | |
3675c2f2 | 5176 | amdgpu_device_lock_reset_domain(tmp_adev->reset_domain); |
e923be99 | 5177 | |
1d721ed6 | 5178 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 5179 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
f287a3c5 | 5180 | |
e923be99 | 5181 | amdgpu_device_set_mp1_state(tmp_adev); |
f287a3c5 | 5182 | |
3f12acc8 EQ |
5183 | /* |
5184 | * Try to put the audio codec into suspend state | |
5185 | * before gpu reset started. | |
5186 | * | |
5187 | * Due to the power domain of the graphics device | |
5188 | * is shared with AZ power domain. Without this, | |
5189 | * we may change the audio hardware from behind | |
5190 | * the audio driver's back. That will trigger | |
5191 | * some audio codec errors. | |
5192 | */ | |
5193 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
5194 | audio_suspended = true; | |
5195 | ||
9e94d22c EQ |
5196 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
5197 | ||
52fb44cf EQ |
5198 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
5199 | ||
c004d44e | 5200 | if (!amdgpu_sriov_vf(tmp_adev)) |
428890a3 | 5201 | amdgpu_amdkfd_pre_reset(tmp_adev); |
9e94d22c | 5202 | |
12ffa55d AG |
5203 | /* |
5204 | * Mark these ASICs to be reseted as untracked first | |
5205 | * And add them back after reset completed | |
5206 | */ | |
5207 | amdgpu_unregister_gpu_instance(tmp_adev); | |
5208 | ||
163d4cd2 | 5209 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true); |
565d1941 | 5210 | |
f1c1314b | 5211 | /* disable ras on ALL IPs */ |
bb5c7235 | 5212 | if (!need_emergency_restart && |
b823821f | 5213 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 5214 | amdgpu_ras_suspend(tmp_adev); |
5215 | ||
1d721ed6 AG |
5216 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5217 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5218 | ||
5219 | if (!ring || !ring->sched.thread) | |
5220 | continue; | |
5221 | ||
0b2d2c2e | 5222 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 5223 | |
bb5c7235 | 5224 | if (need_emergency_restart) |
7c6e68c7 | 5225 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 5226 | } |
8f8c80f4 | 5227 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
5228 | } |
5229 | ||
bb5c7235 | 5230 | if (need_emergency_restart) |
7c6e68c7 AG |
5231 | goto skip_sched_resume; |
5232 | ||
1d721ed6 AG |
5233 | /* |
5234 | * Must check guilty signal here since after this point all old | |
5235 | * HW fences are force signaled. | |
5236 | * | |
5237 | * job->base holds a reference to parent fence | |
5238 | */ | |
9ae55f03 AG |
5239 | if (job && (job->hw_fence.ops != NULL) && |
5240 | dma_fence_is_signaled(&job->hw_fence)) { | |
1d721ed6 | 5241 | job_signaled = true; |
1d721ed6 AG |
5242 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
5243 | goto skip_hw_reset; | |
5244 | } | |
5245 | ||
26bc5340 | 5246 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 5247 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
04442bf7 | 5248 | r = amdgpu_device_pre_asic_reset(tmp_adev, &reset_context); |
26bc5340 AG |
5249 | /*TODO Should we stop ?*/ |
5250 | if (r) { | |
aac89168 | 5251 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 5252 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
5253 | tmp_adev->asic_reset_res = r; |
5254 | } | |
247c7b0d AG |
5255 | |
5256 | /* | |
5257 | * Drop all pending non scheduler resets. Scheduler resets | |
5258 | * were already dropped during drm_sched_stop | |
5259 | */ | |
d193b12b | 5260 | amdgpu_device_stop_pending_resets(tmp_adev); |
26bc5340 AG |
5261 | } |
5262 | ||
e6c6338f | 5263 | tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); |
26bc5340 | 5264 | /* Actual ASIC resets if needed.*/ |
4f30d920 | 5265 | /* Host driver will handle XGMI hive reset for SRIOV */ |
26bc5340 AG |
5266 | if (amdgpu_sriov_vf(adev)) { |
5267 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
5268 | if (r) | |
5269 | adev->asic_reset_res = r; | |
950d6425 SY |
5270 | |
5271 | /* Aldebaran supports ras in SRIOV, so need resume ras during reset */ | |
5272 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) | |
5273 | amdgpu_ras_resume(adev); | |
26bc5340 | 5274 | } else { |
04442bf7 | 5275 | r = amdgpu_do_asic_reset(device_list_handle, &reset_context); |
26bc5340 AG |
5276 | if (r && r == -EAGAIN) |
5277 | goto retry; | |
5278 | } | |
5279 | ||
1d721ed6 AG |
5280 | skip_hw_reset: |
5281 | ||
26bc5340 | 5282 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 5283 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 5284 | |
e6c6338f JZ |
5285 | /* |
5286 | * Sometimes a later bad compute job can block a good gfx job as gfx | |
5287 | * and compute ring share internal GC HW mutually. We add an additional | |
5288 | * guilty jobs recheck step to find the real guilty job, it synchronously | |
5289 | * submits and pends for the first job being signaled. If it gets timeout, | |
5290 | * we identify it as a real guilty job. | |
5291 | */ | |
5292 | if (amdgpu_gpu_recovery == 2 && | |
5293 | !(tmp_vram_lost_counter < atomic_read(&adev->vram_lost_counter))) | |
04442bf7 LL |
5294 | amdgpu_device_recheck_guilty_jobs( |
5295 | tmp_adev, device_list_handle, &reset_context); | |
e6c6338f | 5296 | |
1d721ed6 AG |
5297 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5298 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5299 | ||
5300 | if (!ring || !ring->sched.thread) | |
5301 | continue; | |
5302 | ||
5303 | /* No point to resubmit jobs if we didn't HW reset*/ | |
5304 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
5305 | drm_sched_resubmit_jobs(&ring->sched); | |
5306 | ||
5307 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
5308 | } | |
5309 | ||
1053b9c9 | 5310 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) { |
4a580877 | 5311 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
5312 | } |
5313 | ||
7258fa31 SK |
5314 | if (tmp_adev->asic_reset_res) |
5315 | r = tmp_adev->asic_reset_res; | |
5316 | ||
1d721ed6 | 5317 | tmp_adev->asic_reset_res = 0; |
26bc5340 AG |
5318 | |
5319 | if (r) { | |
5320 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 5321 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
5322 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
5323 | } else { | |
12ffa55d | 5324 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
3fa8f89d S |
5325 | if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0)) |
5326 | DRM_WARN("smart shift update failed\n"); | |
26bc5340 | 5327 | } |
7c6e68c7 | 5328 | } |
26bc5340 | 5329 | |
7c6e68c7 | 5330 | skip_sched_resume: |
655ce9cb | 5331 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
428890a3 | 5332 | /* unlock kfd: SRIOV would do it separately */ |
c004d44e | 5333 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
428890a3 | 5334 | amdgpu_amdkfd_post_reset(tmp_adev); |
8e2712e7 | 5335 | |
5336 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
5337 | * need to bring up kfd here if it's not be initialized before | |
5338 | */ | |
5339 | if (!adev->kfd.init_complete) | |
5340 | amdgpu_amdkfd_device_init(adev); | |
5341 | ||
3f12acc8 EQ |
5342 | if (audio_suspended) |
5343 | amdgpu_device_resume_display_audio(tmp_adev); | |
e923be99 AG |
5344 | |
5345 | amdgpu_device_unset_mp1_state(tmp_adev); | |
26bc5340 AG |
5346 | } |
5347 | ||
e923be99 AG |
5348 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, |
5349 | reset_list); | |
5350 | amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain); | |
5351 | ||
9e94d22c | 5352 | if (hive) { |
9e94d22c | 5353 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 5354 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 5355 | } |
26bc5340 | 5356 | |
f287a3c5 | 5357 | if (r) |
26bc5340 | 5358 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
ab9a0b1f AG |
5359 | |
5360 | atomic_set(&adev->reset_domain->reset_res, r); | |
d38ceaf9 AD |
5361 | return r; |
5362 | } | |
5363 | ||
e3ecdffa AD |
5364 | /** |
5365 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
5366 | * | |
5367 | * @adev: amdgpu_device pointer | |
5368 | * | |
5369 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
5370 | * and lanes) of the slot the device is in. Handles APUs and | |
5371 | * virtualized environments where PCIE config space may not be available. | |
5372 | */ | |
5494d864 | 5373 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 5374 | { |
5d9a6330 | 5375 | struct pci_dev *pdev; |
c5313457 HK |
5376 | enum pci_bus_speed speed_cap, platform_speed_cap; |
5377 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 5378 | |
cd474ba0 AD |
5379 | if (amdgpu_pcie_gen_cap) |
5380 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 5381 | |
cd474ba0 AD |
5382 | if (amdgpu_pcie_lane_cap) |
5383 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 5384 | |
cd474ba0 AD |
5385 | /* covers APUs as well */ |
5386 | if (pci_is_root_bus(adev->pdev->bus)) { | |
5387 | if (adev->pm.pcie_gen_mask == 0) | |
5388 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
5389 | if (adev->pm.pcie_mlw_mask == 0) | |
5390 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 5391 | return; |
cd474ba0 | 5392 | } |
d0dd7f0c | 5393 | |
c5313457 HK |
5394 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
5395 | return; | |
5396 | ||
dbaa922b AD |
5397 | pcie_bandwidth_available(adev->pdev, NULL, |
5398 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 5399 | |
cd474ba0 | 5400 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
5401 | /* asic caps */ |
5402 | pdev = adev->pdev; | |
5403 | speed_cap = pcie_get_speed_cap(pdev); | |
5404 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
5405 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
5406 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
5407 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 5408 | } else { |
2b3a1f51 FX |
5409 | if (speed_cap == PCIE_SPEED_32_0GT) |
5410 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5411 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5412 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5413 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5414 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5415 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5416 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5417 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5418 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5419 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
5420 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
5421 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5422 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5423 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
5424 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
5425 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5426 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5427 | else | |
5428 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5429 | } | |
5430 | /* platform caps */ | |
c5313457 | 5431 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
5432 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5433 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5434 | } else { | |
2b3a1f51 FX |
5435 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
5436 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5437 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5438 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5439 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5440 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5441 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5442 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5443 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5444 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5445 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 5446 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
5447 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5448 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5449 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 5450 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
5451 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5452 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5453 | else | |
5454 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5455 | ||
cd474ba0 AD |
5456 | } |
5457 | } | |
5458 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 5459 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
5460 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
5461 | } else { | |
c5313457 | 5462 | switch (platform_link_width) { |
5d9a6330 | 5463 | case PCIE_LNK_X32: |
cd474ba0 AD |
5464 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
5465 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
5466 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5467 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5468 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5469 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5470 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5471 | break; | |
5d9a6330 | 5472 | case PCIE_LNK_X16: |
cd474ba0 AD |
5473 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5474 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5475 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5476 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5477 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5478 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5479 | break; | |
5d9a6330 | 5480 | case PCIE_LNK_X12: |
cd474ba0 AD |
5481 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5482 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5483 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5484 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5485 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5486 | break; | |
5d9a6330 | 5487 | case PCIE_LNK_X8: |
cd474ba0 AD |
5488 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5489 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5490 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5491 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5492 | break; | |
5d9a6330 | 5493 | case PCIE_LNK_X4: |
cd474ba0 AD |
5494 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5495 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5496 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5497 | break; | |
5d9a6330 | 5498 | case PCIE_LNK_X2: |
cd474ba0 AD |
5499 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5500 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5501 | break; | |
5d9a6330 | 5502 | case PCIE_LNK_X1: |
cd474ba0 AD |
5503 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5504 | break; | |
5505 | default: | |
5506 | break; | |
5507 | } | |
d0dd7f0c AD |
5508 | } |
5509 | } | |
5510 | } | |
d38ceaf9 | 5511 | |
08a2fd23 RE |
5512 | /** |
5513 | * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR | |
5514 | * | |
5515 | * @adev: amdgpu_device pointer | |
5516 | * @peer_adev: amdgpu_device pointer for peer device trying to access @adev | |
5517 | * | |
5518 | * Return true if @peer_adev can access (DMA) @adev through the PCIe | |
5519 | * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of | |
5520 | * @peer_adev. | |
5521 | */ | |
5522 | bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, | |
5523 | struct amdgpu_device *peer_adev) | |
5524 | { | |
5525 | #ifdef CONFIG_HSA_AMD_P2P | |
5526 | uint64_t address_mask = peer_adev->dev->dma_mask ? | |
5527 | ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1); | |
5528 | resource_size_t aper_limit = | |
5529 | adev->gmc.aper_base + adev->gmc.aper_size - 1; | |
5530 | bool p2p_access = !(pci_p2pdma_distance_many(adev->pdev, | |
5531 | &peer_adev->dev, 1, true) < 0); | |
5532 | ||
5533 | return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && | |
5534 | adev->gmc.real_vram_size == adev->gmc.visible_vram_size && | |
5535 | !(adev->gmc.aper_base & address_mask || | |
5536 | aper_limit & address_mask)); | |
5537 | #else | |
5538 | return false; | |
5539 | #endif | |
5540 | } | |
5541 | ||
361dbd01 AD |
5542 | int amdgpu_device_baco_enter(struct drm_device *dev) |
5543 | { | |
1348969a | 5544 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5545 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 5546 | |
4a580877 | 5547 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5548 | return -ENOTSUPP; |
5549 | ||
8ab0d6f0 | 5550 | if (ras && adev->ras_enabled && |
acdae216 | 5551 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5552 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
5553 | ||
9530273e | 5554 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
5555 | } |
5556 | ||
5557 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
5558 | { | |
1348969a | 5559 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5560 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 5561 | int ret = 0; |
361dbd01 | 5562 | |
4a580877 | 5563 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5564 | return -ENOTSUPP; |
5565 | ||
9530273e EQ |
5566 | ret = amdgpu_dpm_baco_exit(adev); |
5567 | if (ret) | |
5568 | return ret; | |
7a22677b | 5569 | |
8ab0d6f0 | 5570 | if (ras && adev->ras_enabled && |
acdae216 | 5571 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5572 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
5573 | ||
1bece222 CL |
5574 | if (amdgpu_passthrough(adev) && |
5575 | adev->nbio.funcs->clear_doorbell_interrupt) | |
5576 | adev->nbio.funcs->clear_doorbell_interrupt(adev); | |
5577 | ||
7a22677b | 5578 | return 0; |
361dbd01 | 5579 | } |
c9a6b82f AG |
5580 | |
5581 | /** | |
5582 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
5583 | * @pdev: PCI device struct | |
5584 | * @state: PCI channel state | |
5585 | * | |
5586 | * Description: Called when a PCI error is detected. | |
5587 | * | |
5588 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
5589 | */ | |
5590 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5591 | { | |
5592 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5593 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5594 | int i; |
c9a6b82f AG |
5595 | |
5596 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
5597 | ||
6894305c AG |
5598 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
5599 | DRM_WARN("No support for XGMI hive yet..."); | |
5600 | return PCI_ERS_RESULT_DISCONNECT; | |
5601 | } | |
5602 | ||
e17e27f9 GC |
5603 | adev->pci_channel_state = state; |
5604 | ||
c9a6b82f AG |
5605 | switch (state) { |
5606 | case pci_channel_io_normal: | |
5607 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 5608 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
5609 | case pci_channel_io_frozen: |
5610 | /* | |
d0fb18b5 | 5611 | * Locking adev->reset_domain->sem will prevent any external access |
acd89fca AG |
5612 | * to GPU during PCI error recovery |
5613 | */ | |
3675c2f2 | 5614 | amdgpu_device_lock_reset_domain(adev->reset_domain); |
e923be99 | 5615 | amdgpu_device_set_mp1_state(adev); |
acd89fca AG |
5616 | |
5617 | /* | |
5618 | * Block any work scheduling as we do for regular GPU reset | |
5619 | * for the duration of the recovery | |
5620 | */ | |
5621 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5622 | struct amdgpu_ring *ring = adev->rings[i]; | |
5623 | ||
5624 | if (!ring || !ring->sched.thread) | |
5625 | continue; | |
5626 | ||
5627 | drm_sched_stop(&ring->sched, NULL); | |
5628 | } | |
8f8c80f4 | 5629 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
5630 | return PCI_ERS_RESULT_NEED_RESET; |
5631 | case pci_channel_io_perm_failure: | |
5632 | /* Permanent error, prepare for device removal */ | |
5633 | return PCI_ERS_RESULT_DISCONNECT; | |
5634 | } | |
5635 | ||
5636 | return PCI_ERS_RESULT_NEED_RESET; | |
5637 | } | |
5638 | ||
5639 | /** | |
5640 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
5641 | * @pdev: pointer to PCI device | |
5642 | */ | |
5643 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
5644 | { | |
5645 | ||
5646 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
5647 | ||
5648 | /* TODO - dump whatever for debugging purposes */ | |
5649 | ||
5650 | /* This called only if amdgpu_pci_error_detected returns | |
5651 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
5652 | * works, no need to reset slot. | |
5653 | */ | |
5654 | ||
5655 | return PCI_ERS_RESULT_RECOVERED; | |
5656 | } | |
5657 | ||
5658 | /** | |
5659 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
5660 | * @pdev: PCI device struct | |
5661 | * | |
5662 | * Description: This routine is called by the pci error recovery | |
5663 | * code after the PCI slot has been reset, just before we | |
5664 | * should resume normal operations. | |
5665 | */ | |
5666 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
5667 | { | |
5668 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5669 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 5670 | int r, i; |
04442bf7 | 5671 | struct amdgpu_reset_context reset_context; |
362c7b91 | 5672 | u32 memsize; |
7ac71382 | 5673 | struct list_head device_list; |
c9a6b82f AG |
5674 | |
5675 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
5676 | ||
04442bf7 LL |
5677 | memset(&reset_context, 0, sizeof(reset_context)); |
5678 | ||
7ac71382 | 5679 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 5680 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 5681 | |
362c7b91 AG |
5682 | /* wait for asic to come out of reset */ |
5683 | msleep(500); | |
5684 | ||
7ac71382 | 5685 | /* Restore PCI confspace */ |
c1dd4aa6 | 5686 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 5687 | |
362c7b91 AG |
5688 | /* confirm ASIC came out of reset */ |
5689 | for (i = 0; i < adev->usec_timeout; i++) { | |
5690 | memsize = amdgpu_asic_get_config_memsize(adev); | |
5691 | ||
5692 | if (memsize != 0xffffffff) | |
5693 | break; | |
5694 | udelay(1); | |
5695 | } | |
5696 | if (memsize == 0xffffffff) { | |
5697 | r = -ETIME; | |
5698 | goto out; | |
5699 | } | |
5700 | ||
04442bf7 LL |
5701 | reset_context.method = AMD_RESET_METHOD_NONE; |
5702 | reset_context.reset_req_dev = adev; | |
5703 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5704 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); | |
5705 | ||
7afefb81 | 5706 | adev->no_hw_access = true; |
04442bf7 | 5707 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
7afefb81 | 5708 | adev->no_hw_access = false; |
c9a6b82f AG |
5709 | if (r) |
5710 | goto out; | |
5711 | ||
04442bf7 | 5712 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
c9a6b82f AG |
5713 | |
5714 | out: | |
c9a6b82f | 5715 | if (!r) { |
c1dd4aa6 AG |
5716 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
5717 | pci_restore_state(adev->pdev); | |
5718 | ||
c9a6b82f AG |
5719 | DRM_INFO("PCIe error recovery succeeded\n"); |
5720 | } else { | |
5721 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
e923be99 AG |
5722 | amdgpu_device_unset_mp1_state(adev); |
5723 | amdgpu_device_unlock_reset_domain(adev->reset_domain); | |
c9a6b82f AG |
5724 | } |
5725 | ||
5726 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
5727 | } | |
5728 | ||
5729 | /** | |
5730 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
5731 | * @pdev: pointer to PCI device | |
5732 | * | |
5733 | * Called when the error recovery driver tells us that its | |
505199a3 | 5734 | * OK to resume normal operation. |
c9a6b82f AG |
5735 | */ |
5736 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
5737 | { | |
5738 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5739 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5740 | int i; |
c9a6b82f | 5741 | |
c9a6b82f AG |
5742 | |
5743 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca | 5744 | |
e17e27f9 GC |
5745 | /* Only continue execution for the case of pci_channel_io_frozen */ |
5746 | if (adev->pci_channel_state != pci_channel_io_frozen) | |
5747 | return; | |
5748 | ||
acd89fca AG |
5749 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5750 | struct amdgpu_ring *ring = adev->rings[i]; | |
5751 | ||
5752 | if (!ring || !ring->sched.thread) | |
5753 | continue; | |
5754 | ||
5755 | ||
5756 | drm_sched_resubmit_jobs(&ring->sched); | |
5757 | drm_sched_start(&ring->sched, true); | |
5758 | } | |
5759 | ||
e923be99 AG |
5760 | amdgpu_device_unset_mp1_state(adev); |
5761 | amdgpu_device_unlock_reset_domain(adev->reset_domain); | |
c9a6b82f | 5762 | } |
c1dd4aa6 AG |
5763 | |
5764 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
5765 | { | |
5766 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5767 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5768 | int r; | |
5769 | ||
5770 | r = pci_save_state(pdev); | |
5771 | if (!r) { | |
5772 | kfree(adev->pci_state); | |
5773 | ||
5774 | adev->pci_state = pci_store_saved_state(pdev); | |
5775 | ||
5776 | if (!adev->pci_state) { | |
5777 | DRM_ERROR("Failed to store PCI saved state"); | |
5778 | return false; | |
5779 | } | |
5780 | } else { | |
5781 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
5782 | return false; | |
5783 | } | |
5784 | ||
5785 | return true; | |
5786 | } | |
5787 | ||
5788 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
5789 | { | |
5790 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5791 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5792 | int r; | |
5793 | ||
5794 | if (!adev->pci_state) | |
5795 | return false; | |
5796 | ||
5797 | r = pci_load_saved_state(pdev, adev->pci_state); | |
5798 | ||
5799 | if (!r) { | |
5800 | pci_restore_state(pdev); | |
5801 | } else { | |
5802 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
5803 | return false; | |
5804 | } | |
5805 | ||
5806 | return true; | |
5807 | } | |
5808 | ||
810085dd EH |
5809 | void amdgpu_device_flush_hdp(struct amdgpu_device *adev, |
5810 | struct amdgpu_ring *ring) | |
5811 | { | |
5812 | #ifdef CONFIG_X86_64 | |
b818a5d3 | 5813 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
5814 | return; |
5815 | #endif | |
5816 | if (adev->gmc.xgmi.connected_to_cpu) | |
5817 | return; | |
5818 | ||
5819 | if (ring && ring->funcs->emit_hdp_flush) | |
5820 | amdgpu_ring_emit_hdp_flush(ring); | |
5821 | else | |
5822 | amdgpu_asic_flush_hdp(adev, ring); | |
5823 | } | |
c1dd4aa6 | 5824 | |
810085dd EH |
5825 | void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, |
5826 | struct amdgpu_ring *ring) | |
5827 | { | |
5828 | #ifdef CONFIG_X86_64 | |
b818a5d3 | 5829 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
5830 | return; |
5831 | #endif | |
5832 | if (adev->gmc.xgmi.connected_to_cpu) | |
5833 | return; | |
c1dd4aa6 | 5834 | |
810085dd EH |
5835 | amdgpu_asic_invalidate_hdp(adev, ring); |
5836 | } | |
34f3a4a9 | 5837 | |
89a7a870 AG |
5838 | int amdgpu_in_reset(struct amdgpu_device *adev) |
5839 | { | |
5840 | return atomic_read(&adev->reset_domain->in_gpu_reset); | |
5841 | } | |
5842 | ||
34f3a4a9 LY |
5843 | /** |
5844 | * amdgpu_device_halt() - bring hardware to some kind of halt state | |
5845 | * | |
5846 | * @adev: amdgpu_device pointer | |
5847 | * | |
5848 | * Bring hardware to some kind of halt state so that no one can touch it | |
5849 | * any more. It will help to maintain error context when error occurred. | |
5850 | * Compare to a simple hang, the system will keep stable at least for SSH | |
5851 | * access. Then it should be trivial to inspect the hardware state and | |
5852 | * see what's going on. Implemented as following: | |
5853 | * | |
5854 | * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc), | |
5855 | * clears all CPU mappings to device, disallows remappings through page faults | |
5856 | * 2. amdgpu_irq_disable_all() disables all interrupts | |
5857 | * 3. amdgpu_fence_driver_hw_fini() signals all HW fences | |
5858 | * 4. set adev->no_hw_access to avoid potential crashes after setp 5 | |
5859 | * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings | |
5860 | * 6. pci_disable_device() and pci_wait_for_pending_transaction() | |
5861 | * flush any in flight DMA operations | |
5862 | */ | |
5863 | void amdgpu_device_halt(struct amdgpu_device *adev) | |
5864 | { | |
5865 | struct pci_dev *pdev = adev->pdev; | |
e0f943b4 | 5866 | struct drm_device *ddev = adev_to_drm(adev); |
34f3a4a9 LY |
5867 | |
5868 | drm_dev_unplug(ddev); | |
5869 | ||
5870 | amdgpu_irq_disable_all(adev); | |
5871 | ||
5872 | amdgpu_fence_driver_hw_fini(adev); | |
5873 | ||
5874 | adev->no_hw_access = true; | |
5875 | ||
5876 | amdgpu_device_unmap_mmio(adev); | |
5877 | ||
5878 | pci_disable_device(pdev); | |
5879 | pci_wait_for_pending_transaction(pdev); | |
5880 | } | |
86700a40 XD |
5881 | |
5882 | u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, | |
5883 | u32 reg) | |
5884 | { | |
5885 | unsigned long flags, address, data; | |
5886 | u32 r; | |
5887 | ||
5888 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
5889 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
5890 | ||
5891 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
5892 | WREG32(address, reg * 4); | |
5893 | (void)RREG32(address); | |
5894 | r = RREG32(data); | |
5895 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
5896 | return r; | |
5897 | } | |
5898 | ||
5899 | void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, | |
5900 | u32 reg, u32 v) | |
5901 | { | |
5902 | unsigned long flags, address, data; | |
5903 | ||
5904 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
5905 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
5906 | ||
5907 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
5908 | WREG32(address, reg * 4); | |
5909 | (void)RREG32(address); | |
5910 | WREG32(data, v); | |
5911 | (void)RREG32(data); | |
5912 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
5913 | } |