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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
d38ceaf9 | 52 | #include "bif/bif_4_1_d.h" |
9accf2fd | 53 | #include <linux/pci.h> |
bec86378 | 54 | #include <linux/firmware.h> |
d1aff8ec | 55 | #include "amdgpu_pm.h" |
d38ceaf9 AD |
56 | |
57 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
58 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
59 | ||
60 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
61 | "TAHITI", |
62 | "PITCAIRN", | |
63 | "VERDE", | |
64 | "OLAND", | |
65 | "HAINAN", | |
d38ceaf9 AD |
66 | "BONAIRE", |
67 | "KAVERI", | |
68 | "KABINI", | |
69 | "HAWAII", | |
70 | "MULLINS", | |
71 | "TOPAZ", | |
72 | "TONGA", | |
48299f95 | 73 | "FIJI", |
d38ceaf9 | 74 | "CARRIZO", |
139f4917 | 75 | "STONEY", |
2cc0c0b5 FC |
76 | "POLARIS10", |
77 | "POLARIS11", | |
c4642a47 | 78 | "POLARIS12", |
d4196f01 | 79 | "VEGA10", |
d38ceaf9 AD |
80 | "LAST", |
81 | }; | |
82 | ||
83 | bool amdgpu_device_is_px(struct drm_device *dev) | |
84 | { | |
85 | struct amdgpu_device *adev = dev->dev_private; | |
86 | ||
2f7d10b3 | 87 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
88 | return true; |
89 | return false; | |
90 | } | |
91 | ||
92 | /* | |
93 | * MMIO register access helper functions. | |
94 | */ | |
95 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 96 | uint32_t acc_flags) |
d38ceaf9 | 97 | { |
f4b373f4 TSD |
98 | uint32_t ret; |
99 | ||
15d72fd7 | 100 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
101 | BUG_ON(in_interrupt()); |
102 | return amdgpu_virt_kiq_rreg(adev, reg); | |
103 | } | |
104 | ||
15d72fd7 | 105 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 106 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
107 | else { |
108 | unsigned long flags; | |
d38ceaf9 AD |
109 | |
110 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
111 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
112 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
113 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 114 | } |
f4b373f4 TSD |
115 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
116 | return ret; | |
d38ceaf9 AD |
117 | } |
118 | ||
119 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 120 | uint32_t acc_flags) |
d38ceaf9 | 121 | { |
f4b373f4 | 122 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 123 | |
15d72fd7 | 124 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
125 | BUG_ON(in_interrupt()); |
126 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
127 | } | |
128 | ||
15d72fd7 | 129 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
130 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
131 | else { | |
132 | unsigned long flags; | |
133 | ||
134 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
135 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
136 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
137 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
138 | } | |
139 | } | |
140 | ||
141 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
142 | { | |
143 | if ((reg * 4) < adev->rio_mem_size) | |
144 | return ioread32(adev->rio_mem + (reg * 4)); | |
145 | else { | |
146 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
147 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
148 | } | |
149 | } | |
150 | ||
151 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
152 | { | |
153 | ||
154 | if ((reg * 4) < adev->rio_mem_size) | |
155 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
156 | else { | |
157 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
158 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
159 | } | |
160 | } | |
161 | ||
162 | /** | |
163 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
164 | * | |
165 | * @adev: amdgpu_device pointer | |
166 | * @index: doorbell index | |
167 | * | |
168 | * Returns the value in the doorbell aperture at the | |
169 | * requested doorbell index (CIK). | |
170 | */ | |
171 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
172 | { | |
173 | if (index < adev->doorbell.num_doorbells) { | |
174 | return readl(adev->doorbell.ptr + index); | |
175 | } else { | |
176 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
177 | return 0; | |
178 | } | |
179 | } | |
180 | ||
181 | /** | |
182 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
183 | * | |
184 | * @adev: amdgpu_device pointer | |
185 | * @index: doorbell index | |
186 | * @v: value to write | |
187 | * | |
188 | * Writes @v to the doorbell aperture at the | |
189 | * requested doorbell index (CIK). | |
190 | */ | |
191 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
192 | { | |
193 | if (index < adev->doorbell.num_doorbells) { | |
194 | writel(v, adev->doorbell.ptr + index); | |
195 | } else { | |
196 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
197 | } | |
198 | } | |
199 | ||
832be404 KW |
200 | /** |
201 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
202 | * | |
203 | * @adev: amdgpu_device pointer | |
204 | * @index: doorbell index | |
205 | * | |
206 | * Returns the value in the doorbell aperture at the | |
207 | * requested doorbell index (VEGA10+). | |
208 | */ | |
209 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
210 | { | |
211 | if (index < adev->doorbell.num_doorbells) { | |
212 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
213 | } else { | |
214 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
215 | return 0; | |
216 | } | |
217 | } | |
218 | ||
219 | /** | |
220 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
221 | * | |
222 | * @adev: amdgpu_device pointer | |
223 | * @index: doorbell index | |
224 | * @v: value to write | |
225 | * | |
226 | * Writes @v to the doorbell aperture at the | |
227 | * requested doorbell index (VEGA10+). | |
228 | */ | |
229 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
230 | { | |
231 | if (index < adev->doorbell.num_doorbells) { | |
232 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
233 | } else { | |
234 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
235 | } | |
236 | } | |
237 | ||
d38ceaf9 AD |
238 | /** |
239 | * amdgpu_invalid_rreg - dummy reg read function | |
240 | * | |
241 | * @adev: amdgpu device pointer | |
242 | * @reg: offset of register | |
243 | * | |
244 | * Dummy register read function. Used for register blocks | |
245 | * that certain asics don't have (all asics). | |
246 | * Returns the value in the register. | |
247 | */ | |
248 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
249 | { | |
250 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
251 | BUG(); | |
252 | return 0; | |
253 | } | |
254 | ||
255 | /** | |
256 | * amdgpu_invalid_wreg - dummy reg write function | |
257 | * | |
258 | * @adev: amdgpu device pointer | |
259 | * @reg: offset of register | |
260 | * @v: value to write to the register | |
261 | * | |
262 | * Dummy register read function. Used for register blocks | |
263 | * that certain asics don't have (all asics). | |
264 | */ | |
265 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
266 | { | |
267 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
268 | reg, v); | |
269 | BUG(); | |
270 | } | |
271 | ||
272 | /** | |
273 | * amdgpu_block_invalid_rreg - dummy reg read function | |
274 | * | |
275 | * @adev: amdgpu device pointer | |
276 | * @block: offset of instance | |
277 | * @reg: offset of register | |
278 | * | |
279 | * Dummy register read function. Used for register blocks | |
280 | * that certain asics don't have (all asics). | |
281 | * Returns the value in the register. | |
282 | */ | |
283 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
284 | uint32_t block, uint32_t reg) | |
285 | { | |
286 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
287 | reg, block); | |
288 | BUG(); | |
289 | return 0; | |
290 | } | |
291 | ||
292 | /** | |
293 | * amdgpu_block_invalid_wreg - dummy reg write function | |
294 | * | |
295 | * @adev: amdgpu device pointer | |
296 | * @block: offset of instance | |
297 | * @reg: offset of register | |
298 | * @v: value to write to the register | |
299 | * | |
300 | * Dummy register read function. Used for register blocks | |
301 | * that certain asics don't have (all asics). | |
302 | */ | |
303 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
304 | uint32_t block, | |
305 | uint32_t reg, uint32_t v) | |
306 | { | |
307 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
308 | reg, block, v); | |
309 | BUG(); | |
310 | } | |
311 | ||
312 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
313 | { | |
314 | int r; | |
315 | ||
316 | if (adev->vram_scratch.robj == NULL) { | |
317 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 318 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
319 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
320 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 321 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
322 | if (r) { |
323 | return r; | |
324 | } | |
325 | } | |
326 | ||
327 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
328 | if (unlikely(r != 0)) | |
329 | return r; | |
330 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
331 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
332 | if (r) { | |
333 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
334 | return r; | |
335 | } | |
336 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
337 | (void **)&adev->vram_scratch.ptr); | |
338 | if (r) | |
339 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
340 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
341 | ||
342 | return r; | |
343 | } | |
344 | ||
345 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
346 | { | |
347 | int r; | |
348 | ||
349 | if (adev->vram_scratch.robj == NULL) { | |
350 | return; | |
351 | } | |
352 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
353 | if (likely(r == 0)) { | |
354 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
355 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
356 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
357 | } | |
358 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
359 | } | |
360 | ||
361 | /** | |
362 | * amdgpu_program_register_sequence - program an array of registers. | |
363 | * | |
364 | * @adev: amdgpu_device pointer | |
365 | * @registers: pointer to the register array | |
366 | * @array_size: size of the register array | |
367 | * | |
368 | * Programs an array or registers with and and or masks. | |
369 | * This is a helper for setting golden registers. | |
370 | */ | |
371 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
372 | const u32 *registers, | |
373 | const u32 array_size) | |
374 | { | |
375 | u32 tmp, reg, and_mask, or_mask; | |
376 | int i; | |
377 | ||
378 | if (array_size % 3) | |
379 | return; | |
380 | ||
381 | for (i = 0; i < array_size; i +=3) { | |
382 | reg = registers[i + 0]; | |
383 | and_mask = registers[i + 1]; | |
384 | or_mask = registers[i + 2]; | |
385 | ||
386 | if (and_mask == 0xffffffff) { | |
387 | tmp = or_mask; | |
388 | } else { | |
389 | tmp = RREG32(reg); | |
390 | tmp &= ~and_mask; | |
391 | tmp |= or_mask; | |
392 | } | |
393 | WREG32(reg, tmp); | |
394 | } | |
395 | } | |
396 | ||
397 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
398 | { | |
399 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
400 | } | |
401 | ||
402 | /* | |
403 | * GPU doorbell aperture helpers function. | |
404 | */ | |
405 | /** | |
406 | * amdgpu_doorbell_init - Init doorbell driver information. | |
407 | * | |
408 | * @adev: amdgpu_device pointer | |
409 | * | |
410 | * Init doorbell driver information (CIK) | |
411 | * Returns 0 on success, error on failure. | |
412 | */ | |
413 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
414 | { | |
415 | /* doorbell bar mapping */ | |
416 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
417 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
418 | ||
edf600da | 419 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
420 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
421 | if (adev->doorbell.num_doorbells == 0) | |
422 | return -EINVAL; | |
423 | ||
424 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
425 | if (adev->doorbell.ptr == NULL) { | |
426 | return -ENOMEM; | |
427 | } | |
428 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
429 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | /** | |
435 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
436 | * | |
437 | * @adev: amdgpu_device pointer | |
438 | * | |
439 | * Tear down doorbell driver information (CIK) | |
440 | */ | |
441 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
442 | { | |
443 | iounmap(adev->doorbell.ptr); | |
444 | adev->doorbell.ptr = NULL; | |
445 | } | |
446 | ||
447 | /** | |
448 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
449 | * setup amdkfd | |
450 | * | |
451 | * @adev: amdgpu_device pointer | |
452 | * @aperture_base: output returning doorbell aperture base physical address | |
453 | * @aperture_size: output returning doorbell aperture size in bytes | |
454 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
455 | * | |
456 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
457 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
458 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
459 | */ | |
460 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
461 | phys_addr_t *aperture_base, | |
462 | size_t *aperture_size, | |
463 | size_t *start_offset) | |
464 | { | |
465 | /* | |
466 | * The first num_doorbells are used by amdgpu. | |
467 | * amdkfd takes whatever's left in the aperture. | |
468 | */ | |
469 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
470 | *aperture_base = adev->doorbell.base; | |
471 | *aperture_size = adev->doorbell.size; | |
472 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
473 | } else { | |
474 | *aperture_base = 0; | |
475 | *aperture_size = 0; | |
476 | *start_offset = 0; | |
477 | } | |
478 | } | |
479 | ||
480 | /* | |
481 | * amdgpu_wb_*() | |
482 | * Writeback is the the method by which the the GPU updates special pages | |
483 | * in memory with the status of certain GPU events (fences, ring pointers, | |
484 | * etc.). | |
485 | */ | |
486 | ||
487 | /** | |
488 | * amdgpu_wb_fini - Disable Writeback and free memory | |
489 | * | |
490 | * @adev: amdgpu_device pointer | |
491 | * | |
492 | * Disables Writeback and frees the Writeback memory (all asics). | |
493 | * Used at driver shutdown. | |
494 | */ | |
495 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
496 | { | |
497 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
498 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
499 | &adev->wb.gpu_addr, | |
500 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
501 | adev->wb.wb_obj = NULL; |
502 | } | |
503 | } | |
504 | ||
505 | /** | |
506 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
507 | * | |
508 | * @adev: amdgpu_device pointer | |
509 | * | |
510 | * Disables Writeback and frees the Writeback memory (all asics). | |
511 | * Used at driver startup. | |
512 | * Returns 0 on success or an -error on failure. | |
513 | */ | |
514 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
515 | { | |
516 | int r; | |
517 | ||
518 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 519 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
520 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
521 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
522 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
523 | if (r) { |
524 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
525 | return r; | |
526 | } | |
d38ceaf9 AD |
527 | |
528 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
529 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
530 | ||
531 | /* clear wb memory */ | |
60a970a6 | 532 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
533 | } |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | /** | |
539 | * amdgpu_wb_get - Allocate a wb entry | |
540 | * | |
541 | * @adev: amdgpu_device pointer | |
542 | * @wb: wb index | |
543 | * | |
544 | * Allocate a wb slot for use by the driver (all asics). | |
545 | * Returns 0 on success or -EINVAL on failure. | |
546 | */ | |
547 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
548 | { | |
549 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
550 | if (offset < adev->wb.num_wb) { | |
551 | __set_bit(offset, adev->wb.used); | |
552 | *wb = offset; | |
553 | return 0; | |
554 | } else { | |
555 | return -EINVAL; | |
556 | } | |
557 | } | |
558 | ||
7014285a KW |
559 | /** |
560 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
561 | * | |
562 | * @adev: amdgpu_device pointer | |
563 | * @wb: wb index | |
564 | * | |
565 | * Allocate a wb slot for use by the driver (all asics). | |
566 | * Returns 0 on success or -EINVAL on failure. | |
567 | */ | |
568 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
569 | { | |
570 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
571 | adev->wb.num_wb, 0, 2, 7, 0); | |
572 | if ((offset + 1) < adev->wb.num_wb) { | |
573 | __set_bit(offset, adev->wb.used); | |
574 | __set_bit(offset + 1, adev->wb.used); | |
575 | *wb = offset; | |
576 | return 0; | |
577 | } else { | |
578 | return -EINVAL; | |
579 | } | |
580 | } | |
581 | ||
d38ceaf9 AD |
582 | /** |
583 | * amdgpu_wb_free - Free a wb entry | |
584 | * | |
585 | * @adev: amdgpu_device pointer | |
586 | * @wb: wb index | |
587 | * | |
588 | * Free a wb slot allocated for use by the driver (all asics) | |
589 | */ | |
590 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
591 | { | |
592 | if (wb < adev->wb.num_wb) | |
593 | __clear_bit(wb, adev->wb.used); | |
594 | } | |
595 | ||
7014285a KW |
596 | /** |
597 | * amdgpu_wb_free_64bit - Free a wb entry | |
598 | * | |
599 | * @adev: amdgpu_device pointer | |
600 | * @wb: wb index | |
601 | * | |
602 | * Free a wb slot allocated for use by the driver (all asics) | |
603 | */ | |
604 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
605 | { | |
606 | if ((wb + 1) < adev->wb.num_wb) { | |
607 | __clear_bit(wb, adev->wb.used); | |
608 | __clear_bit(wb + 1, adev->wb.used); | |
609 | } | |
610 | } | |
611 | ||
d38ceaf9 AD |
612 | /** |
613 | * amdgpu_vram_location - try to find VRAM location | |
614 | * @adev: amdgpu device structure holding all necessary informations | |
615 | * @mc: memory controller structure holding memory informations | |
616 | * @base: base address at which to put VRAM | |
617 | * | |
618 | * Function will place try to place VRAM at base address provided | |
619 | * as parameter (which is so far either PCI aperture address or | |
620 | * for IGP TOM base address). | |
621 | * | |
622 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
623 | * address space then we limit the VRAM size to the aperture. | |
624 | * | |
625 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
626 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
627 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
628 | * not IGP. | |
629 | * | |
630 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
631 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
632 | * Novell bug 204882 + along with lots of ubuntu ones | |
633 | * | |
634 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
635 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
636 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
637 | * ones) | |
638 | * | |
639 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
640 | * explicitly check for that thought. | |
641 | * | |
642 | * FIXME: when reducing VRAM size align new size on power of 2. | |
643 | */ | |
644 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
645 | { | |
646 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
647 | ||
648 | mc->vram_start = base; | |
649 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
650 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
651 | mc->real_vram_size = mc->aper_size; | |
652 | mc->mc_vram_size = mc->aper_size; | |
653 | } | |
654 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
655 | if (limit && limit < mc->real_vram_size) | |
656 | mc->real_vram_size = limit; | |
657 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
658 | mc->mc_vram_size >> 20, mc->vram_start, | |
659 | mc->vram_end, mc->real_vram_size >> 20); | |
660 | } | |
661 | ||
662 | /** | |
663 | * amdgpu_gtt_location - try to find GTT location | |
664 | * @adev: amdgpu device structure holding all necessary informations | |
665 | * @mc: memory controller structure holding memory informations | |
666 | * | |
667 | * Function will place try to place GTT before or after VRAM. | |
668 | * | |
669 | * If GTT size is bigger than space left then we ajust GTT size. | |
670 | * Thus function will never fails. | |
671 | * | |
672 | * FIXME: when reducing GTT size align new size on power of 2. | |
673 | */ | |
674 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
675 | { | |
676 | u64 size_af, size_bf; | |
677 | ||
678 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
679 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
680 | if (size_bf > size_af) { | |
681 | if (mc->gtt_size > size_bf) { | |
682 | dev_warn(adev->dev, "limiting GTT\n"); | |
683 | mc->gtt_size = size_bf; | |
684 | } | |
9dc5a91e | 685 | mc->gtt_start = 0; |
d38ceaf9 AD |
686 | } else { |
687 | if (mc->gtt_size > size_af) { | |
688 | dev_warn(adev->dev, "limiting GTT\n"); | |
689 | mc->gtt_size = size_af; | |
690 | } | |
691 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
692 | } | |
693 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
694 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
695 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
696 | } | |
697 | ||
698 | /* | |
699 | * GPU helpers function. | |
700 | */ | |
701 | /** | |
c836fec5 | 702 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
703 | * |
704 | * @adev: amdgpu_device pointer | |
705 | * | |
c836fec5 JQ |
706 | * Check if the asic has been initialized (all asics) at driver startup |
707 | * or post is needed if hw reset is performed. | |
708 | * Returns true if need or false if not. | |
d38ceaf9 | 709 | */ |
c836fec5 | 710 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
711 | { |
712 | uint32_t reg; | |
713 | ||
c836fec5 JQ |
714 | if (adev->has_hw_reset) { |
715 | adev->has_hw_reset = false; | |
716 | return true; | |
717 | } | |
d38ceaf9 | 718 | /* then check MEM_SIZE, in case the crtcs are off */ |
bbf282d8 | 719 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 AD |
720 | |
721 | if (reg) | |
c836fec5 | 722 | return false; |
d38ceaf9 | 723 | |
c836fec5 | 724 | return true; |
d38ceaf9 AD |
725 | |
726 | } | |
727 | ||
bec86378 ML |
728 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
729 | { | |
730 | if (amdgpu_sriov_vf(adev)) | |
731 | return false; | |
732 | ||
733 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
734 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
735 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
736 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
737 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
738 | */ |
739 | if (adev->asic_type == CHIP_FIJI) { | |
740 | int err; | |
741 | uint32_t fw_ver; | |
742 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
743 | /* force vPost if error occured */ | |
744 | if (err) | |
745 | return true; | |
746 | ||
747 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
748 | if (fw_ver < 0x00160e00) |
749 | return true; | |
bec86378 | 750 | } |
bec86378 | 751 | } |
c836fec5 | 752 | return amdgpu_need_post(adev); |
bec86378 ML |
753 | } |
754 | ||
d38ceaf9 AD |
755 | /** |
756 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
757 | * | |
758 | * @adev: amdgpu_device pointer | |
759 | * | |
760 | * Allocate the dummy page used by the driver (all asics). | |
761 | * This dummy page is used by the driver as a filler for gart entries | |
762 | * when pages are taken out of the GART | |
763 | * Returns 0 on sucess, -ENOMEM on failure. | |
764 | */ | |
765 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
766 | { | |
767 | if (adev->dummy_page.page) | |
768 | return 0; | |
769 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
770 | if (adev->dummy_page.page == NULL) | |
771 | return -ENOMEM; | |
772 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
773 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
774 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
775 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
776 | __free_page(adev->dummy_page.page); | |
777 | adev->dummy_page.page = NULL; | |
778 | return -ENOMEM; | |
779 | } | |
780 | return 0; | |
781 | } | |
782 | ||
783 | /** | |
784 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
785 | * | |
786 | * @adev: amdgpu_device pointer | |
787 | * | |
788 | * Frees the dummy page used by the driver (all asics). | |
789 | */ | |
790 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
791 | { | |
792 | if (adev->dummy_page.page == NULL) | |
793 | return; | |
794 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
795 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
796 | __free_page(adev->dummy_page.page); | |
797 | adev->dummy_page.page = NULL; | |
798 | } | |
799 | ||
800 | ||
801 | /* ATOM accessor methods */ | |
802 | /* | |
803 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
804 | * driver registers callbacks to access registers and the interpreter | |
805 | * in the driver parses the tables and executes then to program specific | |
806 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
807 | * atombios.h, and atom.c | |
808 | */ | |
809 | ||
810 | /** | |
811 | * cail_pll_read - read PLL register | |
812 | * | |
813 | * @info: atom card_info pointer | |
814 | * @reg: PLL register offset | |
815 | * | |
816 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
817 | * Returns the value of the PLL register. | |
818 | */ | |
819 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
820 | { | |
821 | return 0; | |
822 | } | |
823 | ||
824 | /** | |
825 | * cail_pll_write - write PLL register | |
826 | * | |
827 | * @info: atom card_info pointer | |
828 | * @reg: PLL register offset | |
829 | * @val: value to write to the pll register | |
830 | * | |
831 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
832 | */ | |
833 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
834 | { | |
835 | ||
836 | } | |
837 | ||
838 | /** | |
839 | * cail_mc_read - read MC (Memory Controller) register | |
840 | * | |
841 | * @info: atom card_info pointer | |
842 | * @reg: MC register offset | |
843 | * | |
844 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
845 | * Returns the value of the MC register. | |
846 | */ | |
847 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
848 | { | |
849 | return 0; | |
850 | } | |
851 | ||
852 | /** | |
853 | * cail_mc_write - write MC (Memory Controller) register | |
854 | * | |
855 | * @info: atom card_info pointer | |
856 | * @reg: MC register offset | |
857 | * @val: value to write to the pll register | |
858 | * | |
859 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
860 | */ | |
861 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
862 | { | |
863 | ||
864 | } | |
865 | ||
866 | /** | |
867 | * cail_reg_write - write MMIO register | |
868 | * | |
869 | * @info: atom card_info pointer | |
870 | * @reg: MMIO register offset | |
871 | * @val: value to write to the pll register | |
872 | * | |
873 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
874 | */ | |
875 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
876 | { | |
877 | struct amdgpu_device *adev = info->dev->dev_private; | |
878 | ||
879 | WREG32(reg, val); | |
880 | } | |
881 | ||
882 | /** | |
883 | * cail_reg_read - read MMIO register | |
884 | * | |
885 | * @info: atom card_info pointer | |
886 | * @reg: MMIO register offset | |
887 | * | |
888 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
889 | * Returns the value of the MMIO register. | |
890 | */ | |
891 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
892 | { | |
893 | struct amdgpu_device *adev = info->dev->dev_private; | |
894 | uint32_t r; | |
895 | ||
896 | r = RREG32(reg); | |
897 | return r; | |
898 | } | |
899 | ||
900 | /** | |
901 | * cail_ioreg_write - write IO register | |
902 | * | |
903 | * @info: atom card_info pointer | |
904 | * @reg: IO register offset | |
905 | * @val: value to write to the pll register | |
906 | * | |
907 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
908 | */ | |
909 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
910 | { | |
911 | struct amdgpu_device *adev = info->dev->dev_private; | |
912 | ||
913 | WREG32_IO(reg, val); | |
914 | } | |
915 | ||
916 | /** | |
917 | * cail_ioreg_read - read IO register | |
918 | * | |
919 | * @info: atom card_info pointer | |
920 | * @reg: IO register offset | |
921 | * | |
922 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
923 | * Returns the value of the IO register. | |
924 | */ | |
925 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
926 | { | |
927 | struct amdgpu_device *adev = info->dev->dev_private; | |
928 | uint32_t r; | |
929 | ||
930 | r = RREG32_IO(reg); | |
931 | return r; | |
932 | } | |
933 | ||
934 | /** | |
935 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
936 | * | |
937 | * @adev: amdgpu_device pointer | |
938 | * | |
939 | * Frees the driver info and register access callbacks for the ATOM | |
940 | * interpreter (r4xx+). | |
941 | * Called at driver shutdown. | |
942 | */ | |
943 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
944 | { | |
89e0ec9f | 945 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 946 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
947 | kfree(adev->mode_info.atom_context->iio); |
948 | } | |
d38ceaf9 AD |
949 | kfree(adev->mode_info.atom_context); |
950 | adev->mode_info.atom_context = NULL; | |
951 | kfree(adev->mode_info.atom_card_info); | |
952 | adev->mode_info.atom_card_info = NULL; | |
953 | } | |
954 | ||
955 | /** | |
956 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
957 | * | |
958 | * @adev: amdgpu_device pointer | |
959 | * | |
960 | * Initializes the driver info and register access callbacks for the | |
961 | * ATOM interpreter (r4xx+). | |
962 | * Returns 0 on sucess, -ENOMEM on failure. | |
963 | * Called at driver startup. | |
964 | */ | |
965 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
966 | { | |
967 | struct card_info *atom_card_info = | |
968 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
969 | ||
970 | if (!atom_card_info) | |
971 | return -ENOMEM; | |
972 | ||
973 | adev->mode_info.atom_card_info = atom_card_info; | |
974 | atom_card_info->dev = adev->ddev; | |
975 | atom_card_info->reg_read = cail_reg_read; | |
976 | atom_card_info->reg_write = cail_reg_write; | |
977 | /* needed for iio ops */ | |
978 | if (adev->rio_mem) { | |
979 | atom_card_info->ioreg_read = cail_ioreg_read; | |
980 | atom_card_info->ioreg_write = cail_ioreg_write; | |
981 | } else { | |
b64a18c5 | 982 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
983 | atom_card_info->ioreg_read = cail_reg_read; |
984 | atom_card_info->ioreg_write = cail_reg_write; | |
985 | } | |
986 | atom_card_info->mc_read = cail_mc_read; | |
987 | atom_card_info->mc_write = cail_mc_write; | |
988 | atom_card_info->pll_read = cail_pll_read; | |
989 | atom_card_info->pll_write = cail_pll_write; | |
990 | ||
991 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
992 | if (!adev->mode_info.atom_context) { | |
993 | amdgpu_atombios_fini(adev); | |
994 | return -ENOMEM; | |
995 | } | |
996 | ||
997 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
998 | if (adev->is_atom_fw) { |
999 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1000 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1001 | } else { | |
1002 | amdgpu_atombios_scratch_regs_init(adev); | |
1003 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1004 | } | |
d38ceaf9 AD |
1005 | return 0; |
1006 | } | |
1007 | ||
1008 | /* if we get transitioned to only one device, take VGA back */ | |
1009 | /** | |
1010 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1011 | * | |
1012 | * @cookie: amdgpu_device pointer | |
1013 | * @state: enable/disable vga decode | |
1014 | * | |
1015 | * Enable/disable vga decode (all asics). | |
1016 | * Returns VGA resource flags. | |
1017 | */ | |
1018 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1019 | { | |
1020 | struct amdgpu_device *adev = cookie; | |
1021 | amdgpu_asic_set_vga_state(adev, state); | |
1022 | if (state) | |
1023 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1024 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1025 | else | |
1026 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1027 | } | |
1028 | ||
1029 | /** | |
1030 | * amdgpu_check_pot_argument - check that argument is a power of two | |
1031 | * | |
1032 | * @arg: value to check | |
1033 | * | |
1034 | * Validates that a certain argument is a power of two (all asics). | |
1035 | * Returns true if argument is valid. | |
1036 | */ | |
1037 | static bool amdgpu_check_pot_argument(int arg) | |
1038 | { | |
1039 | return (arg & (arg - 1)) == 0; | |
1040 | } | |
1041 | ||
1042 | /** | |
1043 | * amdgpu_check_arguments - validate module params | |
1044 | * | |
1045 | * @adev: amdgpu_device pointer | |
1046 | * | |
1047 | * Validates certain module parameters and updates | |
1048 | * the associated values used by the driver (all asics). | |
1049 | */ | |
1050 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1051 | { | |
5b011235 CZ |
1052 | if (amdgpu_sched_jobs < 4) { |
1053 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1054 | amdgpu_sched_jobs); | |
1055 | amdgpu_sched_jobs = 4; | |
1056 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
1057 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
1058 | amdgpu_sched_jobs); | |
1059 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1060 | } | |
d38ceaf9 AD |
1061 | |
1062 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 1063 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
1064 | if (amdgpu_gart_size < 32) { |
1065 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1066 | amdgpu_gart_size); | |
1067 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
1068 | } |
1069 | } | |
1070 | ||
1071 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
1072 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
1073 | amdgpu_vm_size); | |
8dacc127 | 1074 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1075 | } |
1076 | ||
1077 | if (amdgpu_vm_size < 1) { | |
1078 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1079 | amdgpu_vm_size); | |
8dacc127 | 1080 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1081 | } |
1082 | ||
1083 | /* | |
1084 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
1085 | */ | |
1086 | if (amdgpu_vm_size > 1024) { | |
1087 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1088 | amdgpu_vm_size); | |
8dacc127 | 1089 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1090 | } |
1091 | ||
1092 | /* defines number of bits in page table versus page directory, | |
1093 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1094 | * page table and the remaining bits are in the page directory */ | |
1095 | if (amdgpu_vm_block_size == -1) { | |
1096 | ||
1097 | /* Total bits covered by PD + PTs */ | |
1098 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
1099 | ||
1100 | /* Make sure the PD is 4K in size up to 8GB address space. | |
1101 | Above that split equal between PD and PTs */ | |
1102 | if (amdgpu_vm_size <= 8) | |
1103 | amdgpu_vm_block_size = bits - 9; | |
1104 | else | |
1105 | amdgpu_vm_block_size = (bits + 3) / 2; | |
1106 | ||
1107 | } else if (amdgpu_vm_block_size < 9) { | |
1108 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
1109 | amdgpu_vm_block_size); | |
1110 | amdgpu_vm_block_size = 9; | |
1111 | } | |
1112 | ||
1113 | if (amdgpu_vm_block_size > 24 || | |
1114 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1115 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1116 | amdgpu_vm_block_size); | |
1117 | amdgpu_vm_block_size = 9; | |
1118 | } | |
6a7f76e7 | 1119 | |
526bae37 | 1120 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
1121 | !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { | |
6a7f76e7 CK |
1122 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1123 | amdgpu_vram_page_split); | |
1124 | amdgpu_vram_page_split = 1024; | |
1125 | } | |
d38ceaf9 AD |
1126 | } |
1127 | ||
1128 | /** | |
1129 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1130 | * | |
1131 | * @pdev: pci dev pointer | |
1694467b | 1132 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1133 | * |
1134 | * Callback for the switcheroo driver. Suspends or resumes the | |
1135 | * the asics before or after it is powered up using ACPI methods. | |
1136 | */ | |
1137 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1138 | { | |
1139 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1140 | ||
1141 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1142 | return; | |
1143 | ||
1144 | if (state == VGA_SWITCHEROO_ON) { | |
1145 | unsigned d3_delay = dev->pdev->d3_delay; | |
1146 | ||
7ca85295 | 1147 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1148 | /* don't suspend or resume card normally */ |
1149 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1150 | ||
810ddc3a | 1151 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1152 | |
1153 | dev->pdev->d3_delay = d3_delay; | |
1154 | ||
1155 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1156 | drm_kms_helper_poll_enable(dev); | |
1157 | } else { | |
7ca85295 | 1158 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1159 | drm_kms_helper_poll_disable(dev); |
1160 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1161 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1162 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1163 | } | |
1164 | } | |
1165 | ||
1166 | /** | |
1167 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1168 | * | |
1169 | * @pdev: pci dev pointer | |
1170 | * | |
1171 | * Callback for the switcheroo driver. Check of the switcheroo | |
1172 | * state can be changed. | |
1173 | * Returns true if the state can be changed, false if not. | |
1174 | */ | |
1175 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1176 | { | |
1177 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1178 | ||
1179 | /* | |
1180 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1181 | * locking inversion with the driver load path. And the access here is | |
1182 | * completely racy anyway. So don't bother with locking for now. | |
1183 | */ | |
1184 | return dev->open_count == 0; | |
1185 | } | |
1186 | ||
1187 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1188 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1189 | .reprobe = NULL, | |
1190 | .can_switch = amdgpu_switcheroo_can_switch, | |
1191 | }; | |
1192 | ||
1193 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1194 | enum amd_ip_block_type block_type, |
1195 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1196 | { |
1197 | int i, r = 0; | |
1198 | ||
1199 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1200 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1201 | continue; |
c722865a RZ |
1202 | if (adev->ip_blocks[i].version->type != block_type) |
1203 | continue; | |
1204 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1205 | continue; | |
1206 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1207 | (void *)adev, state); | |
1208 | if (r) | |
1209 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1210 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1211 | } |
1212 | return r; | |
1213 | } | |
1214 | ||
1215 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1216 | enum amd_ip_block_type block_type, |
1217 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1218 | { |
1219 | int i, r = 0; | |
1220 | ||
1221 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1222 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1223 | continue; |
c722865a RZ |
1224 | if (adev->ip_blocks[i].version->type != block_type) |
1225 | continue; | |
1226 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1227 | continue; | |
1228 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1229 | (void *)adev, state); | |
1230 | if (r) | |
1231 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1232 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1233 | } |
1234 | return r; | |
1235 | } | |
1236 | ||
6cb2d4e4 HR |
1237 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1238 | { | |
1239 | int i; | |
1240 | ||
1241 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1242 | if (!adev->ip_blocks[i].status.valid) | |
1243 | continue; | |
1244 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1245 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1246 | } | |
1247 | } | |
1248 | ||
5dbbb60b AD |
1249 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1250 | enum amd_ip_block_type block_type) | |
1251 | { | |
1252 | int i, r; | |
1253 | ||
1254 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1255 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1256 | continue; |
a1255107 AD |
1257 | if (adev->ip_blocks[i].version->type == block_type) { |
1258 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1259 | if (r) |
1260 | return r; | |
1261 | break; | |
1262 | } | |
1263 | } | |
1264 | return 0; | |
1265 | ||
1266 | } | |
1267 | ||
1268 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1269 | enum amd_ip_block_type block_type) | |
1270 | { | |
1271 | int i; | |
1272 | ||
1273 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1274 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1275 | continue; |
a1255107 AD |
1276 | if (adev->ip_blocks[i].version->type == block_type) |
1277 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1278 | } |
1279 | return true; | |
1280 | ||
1281 | } | |
1282 | ||
a1255107 AD |
1283 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1284 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1285 | { |
1286 | int i; | |
1287 | ||
1288 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1289 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1290 | return &adev->ip_blocks[i]; |
1291 | ||
1292 | return NULL; | |
1293 | } | |
1294 | ||
1295 | /** | |
1296 | * amdgpu_ip_block_version_cmp | |
1297 | * | |
1298 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1299 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1300 | * @major: major version |
1301 | * @minor: minor version | |
1302 | * | |
1303 | * return 0 if equal or greater | |
1304 | * return 1 if smaller or the ip_block doesn't exist | |
1305 | */ | |
1306 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1307 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1308 | u32 major, u32 minor) |
1309 | { | |
a1255107 | 1310 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1311 | |
a1255107 AD |
1312 | if (ip_block && ((ip_block->version->major > major) || |
1313 | ((ip_block->version->major == major) && | |
1314 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1315 | return 0; |
1316 | ||
1317 | return 1; | |
1318 | } | |
1319 | ||
a1255107 AD |
1320 | /** |
1321 | * amdgpu_ip_block_add | |
1322 | * | |
1323 | * @adev: amdgpu_device pointer | |
1324 | * @ip_block_version: pointer to the IP to add | |
1325 | * | |
1326 | * Adds the IP block driver information to the collection of IPs | |
1327 | * on the asic. | |
1328 | */ | |
1329 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1330 | const struct amdgpu_ip_block_version *ip_block_version) | |
1331 | { | |
1332 | if (!ip_block_version) | |
1333 | return -EINVAL; | |
1334 | ||
1335 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; | |
1336 | ||
1337 | return 0; | |
1338 | } | |
1339 | ||
483ef985 | 1340 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1341 | { |
1342 | adev->enable_virtual_display = false; | |
1343 | ||
1344 | if (amdgpu_virtual_display) { | |
1345 | struct drm_device *ddev = adev->ddev; | |
1346 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1347 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1348 | |
1349 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1350 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1351 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1352 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1353 | if (!strcmp("all", pciaddname) |
1354 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1355 | long num_crtc; |
1356 | int res = -1; | |
1357 | ||
9accf2fd | 1358 | adev->enable_virtual_display = true; |
0f66356d ED |
1359 | |
1360 | if (pciaddname_tmp) | |
1361 | res = kstrtol(pciaddname_tmp, 10, | |
1362 | &num_crtc); | |
1363 | ||
1364 | if (!res) { | |
1365 | if (num_crtc < 1) | |
1366 | num_crtc = 1; | |
1367 | if (num_crtc > 6) | |
1368 | num_crtc = 6; | |
1369 | adev->mode_info.num_crtc = num_crtc; | |
1370 | } else { | |
1371 | adev->mode_info.num_crtc = 1; | |
1372 | } | |
9accf2fd ED |
1373 | break; |
1374 | } | |
1375 | } | |
1376 | ||
0f66356d ED |
1377 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1378 | amdgpu_virtual_display, pci_address_name, | |
1379 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1380 | |
1381 | kfree(pciaddstr); | |
1382 | } | |
1383 | } | |
1384 | ||
d38ceaf9 AD |
1385 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1386 | { | |
aaa36a97 | 1387 | int i, r; |
d38ceaf9 | 1388 | |
483ef985 | 1389 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1390 | |
d38ceaf9 | 1391 | switch (adev->asic_type) { |
aaa36a97 AD |
1392 | case CHIP_TOPAZ: |
1393 | case CHIP_TONGA: | |
48299f95 | 1394 | case CHIP_FIJI: |
2cc0c0b5 FC |
1395 | case CHIP_POLARIS11: |
1396 | case CHIP_POLARIS10: | |
c4642a47 | 1397 | case CHIP_POLARIS12: |
aaa36a97 | 1398 | case CHIP_CARRIZO: |
39bb0c92 SL |
1399 | case CHIP_STONEY: |
1400 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1401 | adev->family = AMDGPU_FAMILY_CZ; |
1402 | else | |
1403 | adev->family = AMDGPU_FAMILY_VI; | |
1404 | ||
1405 | r = vi_set_ip_blocks(adev); | |
1406 | if (r) | |
1407 | return r; | |
1408 | break; | |
33f34802 KW |
1409 | #ifdef CONFIG_DRM_AMDGPU_SI |
1410 | case CHIP_VERDE: | |
1411 | case CHIP_TAHITI: | |
1412 | case CHIP_PITCAIRN: | |
1413 | case CHIP_OLAND: | |
1414 | case CHIP_HAINAN: | |
295d0daf | 1415 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1416 | r = si_set_ip_blocks(adev); |
1417 | if (r) | |
1418 | return r; | |
1419 | break; | |
1420 | #endif | |
a2e73f56 AD |
1421 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1422 | case CHIP_BONAIRE: | |
1423 | case CHIP_HAWAII: | |
1424 | case CHIP_KAVERI: | |
1425 | case CHIP_KABINI: | |
1426 | case CHIP_MULLINS: | |
1427 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1428 | adev->family = AMDGPU_FAMILY_CI; | |
1429 | else | |
1430 | adev->family = AMDGPU_FAMILY_KV; | |
1431 | ||
1432 | r = cik_set_ip_blocks(adev); | |
1433 | if (r) | |
1434 | return r; | |
1435 | break; | |
1436 | #endif | |
d38ceaf9 AD |
1437 | default: |
1438 | /* FIXME: not supported yet */ | |
1439 | return -EINVAL; | |
1440 | } | |
1441 | ||
3149d9da XY |
1442 | if (amdgpu_sriov_vf(adev)) { |
1443 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1444 | if (r) | |
1445 | return r; | |
1446 | } | |
1447 | ||
d38ceaf9 AD |
1448 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1449 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1450 | DRM_ERROR("disabled ip block: %d\n", i); | |
a1255107 | 1451 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1452 | } else { |
a1255107 AD |
1453 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1454 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1455 | if (r == -ENOENT) { |
a1255107 | 1456 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1457 | } else if (r) { |
a1255107 AD |
1458 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1459 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1460 | return r; |
2c1a2784 | 1461 | } else { |
a1255107 | 1462 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1463 | } |
974e6b64 | 1464 | } else { |
a1255107 | 1465 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1466 | } |
d38ceaf9 AD |
1467 | } |
1468 | } | |
1469 | ||
395d1fb9 NH |
1470 | adev->cg_flags &= amdgpu_cg_mask; |
1471 | adev->pg_flags &= amdgpu_pg_mask; | |
1472 | ||
d38ceaf9 AD |
1473 | return 0; |
1474 | } | |
1475 | ||
1476 | static int amdgpu_init(struct amdgpu_device *adev) | |
1477 | { | |
1478 | int i, r; | |
1479 | ||
1480 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1481 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1482 | continue; |
a1255107 | 1483 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1484 | if (r) { |
a1255107 AD |
1485 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1486 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1487 | return r; |
2c1a2784 | 1488 | } |
a1255107 | 1489 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1490 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1491 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1492 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1493 | if (r) { |
1494 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1495 | return r; |
2c1a2784 | 1496 | } |
a1255107 | 1497 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1498 | if (r) { |
1499 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1500 | return r; |
2c1a2784 | 1501 | } |
d38ceaf9 | 1502 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1503 | if (r) { |
1504 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1505 | return r; |
2c1a2784 | 1506 | } |
a1255107 | 1507 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1508 | |
1509 | /* right after GMC hw init, we create CSA */ | |
1510 | if (amdgpu_sriov_vf(adev)) { | |
1511 | r = amdgpu_allocate_static_csa(adev); | |
1512 | if (r) { | |
1513 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1514 | return r; | |
1515 | } | |
1516 | } | |
d38ceaf9 AD |
1517 | } |
1518 | } | |
1519 | ||
1520 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1521 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1522 | continue; |
1523 | /* gmc hw init is done early */ | |
a1255107 | 1524 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1525 | continue; |
a1255107 | 1526 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1527 | if (r) { |
a1255107 AD |
1528 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1529 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1530 | return r; |
2c1a2784 | 1531 | } |
a1255107 | 1532 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1533 | } |
1534 | ||
1535 | return 0; | |
1536 | } | |
1537 | ||
1538 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1539 | { | |
1540 | int i = 0, r; | |
1541 | ||
1542 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1543 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1544 | continue; |
a1255107 AD |
1545 | if (adev->ip_blocks[i].version->funcs->late_init) { |
1546 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2c1a2784 | 1547 | if (r) { |
a1255107 AD |
1548 | DRM_ERROR("late_init of IP block <%s> failed %d\n", |
1549 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1550 | return r; |
2c1a2784 | 1551 | } |
a1255107 | 1552 | adev->ip_blocks[i].status.late_initialized = true; |
d38ceaf9 | 1553 | } |
4a446d55 | 1554 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1555 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1556 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1557 | /* enable clockgating to save power */ |
a1255107 AD |
1558 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1559 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1560 | if (r) { |
1561 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1562 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1563 | return r; |
1564 | } | |
b0b00ff1 | 1565 | } |
d38ceaf9 AD |
1566 | } |
1567 | ||
d1aff8ec TSD |
1568 | amdgpu_dpm_enable_uvd(adev, false); |
1569 | amdgpu_dpm_enable_vce(adev, false); | |
1570 | ||
d38ceaf9 AD |
1571 | return 0; |
1572 | } | |
1573 | ||
1574 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1575 | { | |
1576 | int i, r; | |
1577 | ||
3e96dbfd AD |
1578 | /* need to disable SMC first */ |
1579 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1580 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1581 | continue; |
a1255107 | 1582 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1583 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1584 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1585 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1586 | if (r) { |
1587 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1588 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1589 | return r; |
1590 | } | |
a1255107 | 1591 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1592 | /* XXX handle errors */ |
1593 | if (r) { | |
1594 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1595 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1596 | } |
a1255107 | 1597 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1598 | break; |
1599 | } | |
1600 | } | |
1601 | ||
d38ceaf9 | 1602 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1603 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1604 | continue; |
a1255107 | 1605 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1606 | amdgpu_wb_fini(adev); |
1607 | amdgpu_vram_scratch_fini(adev); | |
1608 | } | |
8201a67a RZ |
1609 | |
1610 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1611 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1612 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1613 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1614 | AMD_CG_STATE_UNGATE); | |
1615 | if (r) { | |
1616 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1617 | adev->ip_blocks[i].version->funcs->name, r); | |
1618 | return r; | |
1619 | } | |
2c1a2784 | 1620 | } |
8201a67a | 1621 | |
a1255107 | 1622 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1623 | /* XXX handle errors */ |
2c1a2784 | 1624 | if (r) { |
a1255107 AD |
1625 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1626 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1627 | } |
8201a67a | 1628 | |
a1255107 | 1629 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1630 | } |
1631 | ||
1632 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1633 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1634 | continue; |
a1255107 | 1635 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1636 | /* XXX handle errors */ |
2c1a2784 | 1637 | if (r) { |
a1255107 AD |
1638 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1639 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1640 | } |
a1255107 AD |
1641 | adev->ip_blocks[i].status.sw = false; |
1642 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1643 | } |
1644 | ||
a6dcfd9c | 1645 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1646 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1647 | continue; |
a1255107 AD |
1648 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1649 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1650 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1651 | } |
1652 | ||
3149d9da | 1653 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1654 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1655 | amdgpu_virt_release_full_gpu(adev, false); |
1656 | } | |
2493664f | 1657 | |
d38ceaf9 AD |
1658 | return 0; |
1659 | } | |
1660 | ||
faefba95 | 1661 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1662 | { |
1663 | int i, r; | |
1664 | ||
e941ea99 XY |
1665 | if (amdgpu_sriov_vf(adev)) |
1666 | amdgpu_virt_request_full_gpu(adev, false); | |
1667 | ||
c5a93a28 FC |
1668 | /* ungate SMC block first */ |
1669 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1670 | AMD_CG_STATE_UNGATE); | |
1671 | if (r) { | |
1672 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1673 | } | |
1674 | ||
d38ceaf9 | 1675 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1676 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1677 | continue; |
1678 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1679 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1680 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1681 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1682 | if (r) { |
a1255107 AD |
1683 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1684 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1685 | } |
2c1a2784 | 1686 | } |
d38ceaf9 | 1687 | /* XXX handle errors */ |
a1255107 | 1688 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1689 | /* XXX handle errors */ |
2c1a2784 | 1690 | if (r) { |
a1255107 AD |
1691 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1692 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1693 | } |
d38ceaf9 AD |
1694 | } |
1695 | ||
e941ea99 XY |
1696 | if (amdgpu_sriov_vf(adev)) |
1697 | amdgpu_virt_release_full_gpu(adev, false); | |
1698 | ||
d38ceaf9 AD |
1699 | return 0; |
1700 | } | |
1701 | ||
e4f0fdcc | 1702 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1703 | { |
1704 | int i, r; | |
1705 | ||
1706 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1707 | if (!adev->ip_blocks[i].status.valid) | |
1708 | continue; | |
1709 | ||
1710 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1711 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1712 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) | |
e4f0fdcc | 1713 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); |
a90ad3c2 ML |
1714 | |
1715 | if (r) { | |
1716 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1717 | adev->ip_blocks[i].version->funcs->name, r); | |
1718 | return r; | |
1719 | } | |
1720 | } | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
e4f0fdcc | 1725 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1726 | { |
1727 | int i, r; | |
1728 | ||
1729 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1730 | if (!adev->ip_blocks[i].status.valid) | |
1731 | continue; | |
1732 | ||
1733 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1734 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1735 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1736 | continue; | |
1737 | ||
e4f0fdcc | 1738 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); |
a90ad3c2 ML |
1739 | if (r) { |
1740 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1741 | adev->ip_blocks[i].version->funcs->name, r); | |
1742 | return r; | |
1743 | } | |
1744 | } | |
1745 | ||
1746 | return 0; | |
1747 | } | |
1748 | ||
d38ceaf9 AD |
1749 | static int amdgpu_resume(struct amdgpu_device *adev) |
1750 | { | |
1751 | int i, r; | |
1752 | ||
1753 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1754 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1755 | continue; |
a1255107 | 1756 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1757 | if (r) { |
a1255107 AD |
1758 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1759 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1760 | return r; |
2c1a2784 | 1761 | } |
d38ceaf9 AD |
1762 | } |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
4e99a44e | 1767 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1768 | { |
a5bde2f9 AD |
1769 | if (adev->is_atom_fw) { |
1770 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
1771 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1772 | } else { | |
1773 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
1774 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1775 | } | |
048765ad AR |
1776 | } |
1777 | ||
d38ceaf9 AD |
1778 | /** |
1779 | * amdgpu_device_init - initialize the driver | |
1780 | * | |
1781 | * @adev: amdgpu_device pointer | |
1782 | * @pdev: drm dev pointer | |
1783 | * @pdev: pci dev pointer | |
1784 | * @flags: driver flags | |
1785 | * | |
1786 | * Initializes the driver info and hw (all asics). | |
1787 | * Returns 0 for success or an error on failure. | |
1788 | * Called at driver startup. | |
1789 | */ | |
1790 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1791 | struct drm_device *ddev, | |
1792 | struct pci_dev *pdev, | |
1793 | uint32_t flags) | |
1794 | { | |
1795 | int r, i; | |
1796 | bool runtime = false; | |
95844d20 | 1797 | u32 max_MBps; |
d38ceaf9 AD |
1798 | |
1799 | adev->shutdown = false; | |
1800 | adev->dev = &pdev->dev; | |
1801 | adev->ddev = ddev; | |
1802 | adev->pdev = pdev; | |
1803 | adev->flags = flags; | |
2f7d10b3 | 1804 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1805 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
1806 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1807 | adev->accel_working = false; | |
1808 | adev->num_rings = 0; | |
1809 | adev->mman.buffer_funcs = NULL; | |
1810 | adev->mman.buffer_funcs_ring = NULL; | |
1811 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1812 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 1813 | adev->gart.gart_funcs = NULL; |
f54d1867 | 1814 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
1815 | |
1816 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1817 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1818 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1819 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
1820 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
1821 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1822 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
1823 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1824 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1825 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
1826 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
1827 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1828 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
1829 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1830 | ||
ccdbb20a | 1831 | |
3e39ab90 AD |
1832 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1833 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1834 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1835 | |
1836 | /* mutex initialization are all done here so we | |
1837 | * can recall function without having locking issues */ | |
8d0a7cea | 1838 | mutex_init(&adev->vm_manager.lock); |
d38ceaf9 | 1839 | atomic_set(&adev->irq.ih.lock, 0); |
d38ceaf9 AD |
1840 | mutex_init(&adev->pm.mutex); |
1841 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1842 | mutex_init(&adev->srbm_mutex); | |
1843 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
1844 | mutex_init(&adev->mn_lock); |
1845 | hash_init(adev->mn_hash); | |
1846 | ||
1847 | amdgpu_check_arguments(adev); | |
1848 | ||
1849 | /* Registers mapping */ | |
1850 | /* TODO: block userspace mapping of io register */ | |
1851 | spin_lock_init(&adev->mmio_idx_lock); | |
1852 | spin_lock_init(&adev->smc_idx_lock); | |
1853 | spin_lock_init(&adev->pcie_idx_lock); | |
1854 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1855 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 1856 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 1857 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 1858 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 1859 | |
0c4e7fa5 CZ |
1860 | INIT_LIST_HEAD(&adev->shadow_list); |
1861 | mutex_init(&adev->shadow_list_lock); | |
1862 | ||
5c1354bd CZ |
1863 | INIT_LIST_HEAD(&adev->gtt_list); |
1864 | spin_lock_init(&adev->gtt_list_lock); | |
1865 | ||
da69c161 KW |
1866 | if (adev->asic_type >= CHIP_BONAIRE) { |
1867 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1868 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1869 | } else { | |
1870 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
1871 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
1872 | } | |
d38ceaf9 | 1873 | |
d38ceaf9 AD |
1874 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
1875 | if (adev->rmmio == NULL) { | |
1876 | return -ENOMEM; | |
1877 | } | |
1878 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1879 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1880 | ||
da69c161 KW |
1881 | if (adev->asic_type >= CHIP_BONAIRE) |
1882 | /* doorbell bar mapping */ | |
1883 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
1884 | |
1885 | /* io port mapping */ | |
1886 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1887 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1888 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1889 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1890 | break; | |
1891 | } | |
1892 | } | |
1893 | if (adev->rio_mem == NULL) | |
b64a18c5 | 1894 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
1895 | |
1896 | /* early init functions */ | |
1897 | r = amdgpu_early_init(adev); | |
1898 | if (r) | |
1899 | return r; | |
1900 | ||
1901 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1902 | /* this will fail for cards that aren't VGA class devices, just | |
1903 | * ignore it */ | |
1904 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1905 | ||
1906 | if (amdgpu_runtime_pm == 1) | |
1907 | runtime = true; | |
e9bef455 | 1908 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 AD |
1909 | runtime = true; |
1910 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1911 | if (runtime) | |
1912 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1913 | ||
1914 | /* Read BIOS */ | |
83ba126a AD |
1915 | if (!amdgpu_get_bios(adev)) { |
1916 | r = -EINVAL; | |
1917 | goto failed; | |
1918 | } | |
f7e9e9fe | 1919 | |
d38ceaf9 | 1920 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
1921 | if (r) { |
1922 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 1923 | goto failed; |
2c1a2784 | 1924 | } |
d38ceaf9 | 1925 | |
4e99a44e ML |
1926 | /* detect if we are with an SRIOV vbios */ |
1927 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 1928 | |
d38ceaf9 | 1929 | /* Post card if necessary */ |
bec86378 | 1930 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 1931 | if (!adev->bios) { |
bec86378 | 1932 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
1933 | r = -EINVAL; |
1934 | goto failed; | |
d38ceaf9 | 1935 | } |
bec86378 | 1936 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
1937 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
1938 | if (r) { | |
1939 | dev_err(adev->dev, "gpu post error!\n"); | |
1940 | goto failed; | |
1941 | } | |
1942 | } else { | |
1943 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
1944 | } |
1945 | ||
a5bde2f9 AD |
1946 | if (!adev->is_atom_fw) { |
1947 | /* Initialize clocks */ | |
1948 | r = amdgpu_atombios_get_clock_info(adev); | |
1949 | if (r) { | |
1950 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
1951 | return r; | |
1952 | } | |
1953 | /* init i2c buses */ | |
1954 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 1955 | } |
d38ceaf9 AD |
1956 | |
1957 | /* Fence driver */ | |
1958 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1959 | if (r) { |
1960 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 1961 | goto failed; |
2c1a2784 | 1962 | } |
d38ceaf9 AD |
1963 | |
1964 | /* init the mode config */ | |
1965 | drm_mode_config_init(adev->ddev); | |
1966 | ||
1967 | r = amdgpu_init(adev); | |
1968 | if (r) { | |
2c1a2784 | 1969 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 1970 | amdgpu_fini(adev); |
83ba126a | 1971 | goto failed; |
d38ceaf9 AD |
1972 | } |
1973 | ||
1974 | adev->accel_working = true; | |
1975 | ||
95844d20 MO |
1976 | /* Initialize the buffer migration limit. */ |
1977 | if (amdgpu_moverate >= 0) | |
1978 | max_MBps = amdgpu_moverate; | |
1979 | else | |
1980 | max_MBps = 8; /* Allow 8 MB/s. */ | |
1981 | /* Get a log2 for easy divisions. */ | |
1982 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
1983 | ||
d38ceaf9 AD |
1984 | r = amdgpu_ib_pool_init(adev); |
1985 | if (r) { | |
1986 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 1987 | goto failed; |
d38ceaf9 AD |
1988 | } |
1989 | ||
1990 | r = amdgpu_ib_ring_tests(adev); | |
1991 | if (r) | |
1992 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1993 | ||
9bc92b9c ML |
1994 | amdgpu_fbdev_init(adev); |
1995 | ||
d38ceaf9 | 1996 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 1997 | if (r) |
d38ceaf9 | 1998 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
1999 | |
2000 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2001 | if (r) |
d38ceaf9 | 2002 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2003 | |
50ab2533 | 2004 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2005 | if (r) |
50ab2533 | 2006 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2007 | |
d38ceaf9 AD |
2008 | if ((amdgpu_testing & 1)) { |
2009 | if (adev->accel_working) | |
2010 | amdgpu_test_moves(adev); | |
2011 | else | |
2012 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2013 | } | |
d38ceaf9 AD |
2014 | if (amdgpu_benchmarking) { |
2015 | if (adev->accel_working) | |
2016 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2017 | else | |
2018 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2019 | } | |
2020 | ||
2021 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2022 | * explicit gating rather than handling it automatically. | |
2023 | */ | |
2024 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2025 | if (r) { |
2026 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 2027 | goto failed; |
2c1a2784 | 2028 | } |
d38ceaf9 AD |
2029 | |
2030 | return 0; | |
83ba126a AD |
2031 | |
2032 | failed: | |
2033 | if (runtime) | |
2034 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2035 | return r; | |
d38ceaf9 AD |
2036 | } |
2037 | ||
d38ceaf9 AD |
2038 | /** |
2039 | * amdgpu_device_fini - tear down the driver | |
2040 | * | |
2041 | * @adev: amdgpu_device pointer | |
2042 | * | |
2043 | * Tear down the driver info (all asics). | |
2044 | * Called at driver shutdown. | |
2045 | */ | |
2046 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2047 | { | |
2048 | int r; | |
2049 | ||
2050 | DRM_INFO("amdgpu: finishing device.\n"); | |
2051 | adev->shutdown = true; | |
a951ed85 | 2052 | drm_crtc_force_disable_all(adev->ddev); |
d38ceaf9 AD |
2053 | /* evict vram memory */ |
2054 | amdgpu_bo_evict_vram(adev); | |
2055 | amdgpu_ib_pool_fini(adev); | |
2056 | amdgpu_fence_driver_fini(adev); | |
2057 | amdgpu_fbdev_fini(adev); | |
2058 | r = amdgpu_fini(adev); | |
d38ceaf9 AD |
2059 | adev->accel_working = false; |
2060 | /* free i2c buses */ | |
2061 | amdgpu_i2c_fini(adev); | |
2062 | amdgpu_atombios_fini(adev); | |
2063 | kfree(adev->bios); | |
2064 | adev->bios = NULL; | |
2065 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2066 | if (adev->flags & AMD_IS_PX) |
2067 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2068 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2069 | if (adev->rio_mem) | |
2070 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2071 | adev->rio_mem = NULL; | |
2072 | iounmap(adev->rmmio); | |
2073 | adev->rmmio = NULL; | |
da69c161 KW |
2074 | if (adev->asic_type >= CHIP_BONAIRE) |
2075 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2076 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2077 | } |
2078 | ||
2079 | ||
2080 | /* | |
2081 | * Suspend & resume. | |
2082 | */ | |
2083 | /** | |
810ddc3a | 2084 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2085 | * |
2086 | * @pdev: drm dev pointer | |
2087 | * @state: suspend state | |
2088 | * | |
2089 | * Puts the hw in the suspend state (all asics). | |
2090 | * Returns 0 for success or an error on failure. | |
2091 | * Called at driver suspend. | |
2092 | */ | |
810ddc3a | 2093 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2094 | { |
2095 | struct amdgpu_device *adev; | |
2096 | struct drm_crtc *crtc; | |
2097 | struct drm_connector *connector; | |
5ceb54c6 | 2098 | int r; |
d38ceaf9 AD |
2099 | |
2100 | if (dev == NULL || dev->dev_private == NULL) { | |
2101 | return -ENODEV; | |
2102 | } | |
2103 | ||
2104 | adev = dev->dev_private; | |
2105 | ||
2106 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2107 | return 0; | |
2108 | ||
2109 | drm_kms_helper_poll_disable(dev); | |
2110 | ||
2111 | /* turn off display hw */ | |
4c7fbc39 | 2112 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2113 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2114 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2115 | } | |
4c7fbc39 | 2116 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2117 | |
756e6880 | 2118 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2119 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2120 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2121 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2122 | struct amdgpu_bo *robj; | |
2123 | ||
756e6880 AD |
2124 | if (amdgpu_crtc->cursor_bo) { |
2125 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2126 | r = amdgpu_bo_reserve(aobj, false); | |
2127 | if (r == 0) { | |
2128 | amdgpu_bo_unpin(aobj); | |
2129 | amdgpu_bo_unreserve(aobj); | |
2130 | } | |
2131 | } | |
2132 | ||
d38ceaf9 AD |
2133 | if (rfb == NULL || rfb->obj == NULL) { |
2134 | continue; | |
2135 | } | |
2136 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2137 | /* don't unpin kernel fb objects */ | |
2138 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
2139 | r = amdgpu_bo_reserve(robj, false); | |
2140 | if (r == 0) { | |
2141 | amdgpu_bo_unpin(robj); | |
2142 | amdgpu_bo_unreserve(robj); | |
2143 | } | |
2144 | } | |
2145 | } | |
2146 | /* evict vram memory */ | |
2147 | amdgpu_bo_evict_vram(adev); | |
2148 | ||
5ceb54c6 | 2149 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2150 | |
2151 | r = amdgpu_suspend(adev); | |
2152 | ||
a0a71e49 AD |
2153 | /* evict remaining vram memory |
2154 | * This second call to evict vram is to evict the gart page table | |
2155 | * using the CPU. | |
2156 | */ | |
d38ceaf9 AD |
2157 | amdgpu_bo_evict_vram(adev); |
2158 | ||
be34d3bf AD |
2159 | if (adev->is_atom_fw) |
2160 | amdgpu_atomfirmware_scratch_regs_save(adev); | |
2161 | else | |
2162 | amdgpu_atombios_scratch_regs_save(adev); | |
d38ceaf9 AD |
2163 | pci_save_state(dev->pdev); |
2164 | if (suspend) { | |
2165 | /* Shut down the device */ | |
2166 | pci_disable_device(dev->pdev); | |
2167 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2168 | } else { |
2169 | r = amdgpu_asic_reset(adev); | |
2170 | if (r) | |
2171 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2172 | } |
2173 | ||
2174 | if (fbcon) { | |
2175 | console_lock(); | |
2176 | amdgpu_fbdev_set_suspend(adev, 1); | |
2177 | console_unlock(); | |
2178 | } | |
2179 | return 0; | |
2180 | } | |
2181 | ||
2182 | /** | |
810ddc3a | 2183 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2184 | * |
2185 | * @pdev: drm dev pointer | |
2186 | * | |
2187 | * Bring the hw back to operating state (all asics). | |
2188 | * Returns 0 for success or an error on failure. | |
2189 | * Called at driver resume. | |
2190 | */ | |
810ddc3a | 2191 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2192 | { |
2193 | struct drm_connector *connector; | |
2194 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2195 | struct drm_crtc *crtc; |
d38ceaf9 AD |
2196 | int r; |
2197 | ||
2198 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2199 | return 0; | |
2200 | ||
74b0b157 | 2201 | if (fbcon) |
d38ceaf9 | 2202 | console_lock(); |
74b0b157 | 2203 | |
d38ceaf9 AD |
2204 | if (resume) { |
2205 | pci_set_power_state(dev->pdev, PCI_D0); | |
2206 | pci_restore_state(dev->pdev); | |
74b0b157 | 2207 | r = pci_enable_device(dev->pdev); |
2208 | if (r) { | |
d38ceaf9 AD |
2209 | if (fbcon) |
2210 | console_unlock(); | |
74b0b157 | 2211 | return r; |
d38ceaf9 AD |
2212 | } |
2213 | } | |
be34d3bf AD |
2214 | if (adev->is_atom_fw) |
2215 | amdgpu_atomfirmware_scratch_regs_restore(adev); | |
2216 | else | |
2217 | amdgpu_atombios_scratch_regs_restore(adev); | |
d38ceaf9 AD |
2218 | |
2219 | /* post card */ | |
c836fec5 | 2220 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2221 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2222 | if (r) | |
2223 | DRM_ERROR("amdgpu asic init failed\n"); | |
2224 | } | |
d38ceaf9 AD |
2225 | |
2226 | r = amdgpu_resume(adev); | |
ca198528 FC |
2227 | if (r) |
2228 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); | |
d38ceaf9 | 2229 | |
5ceb54c6 AD |
2230 | amdgpu_fence_driver_resume(adev); |
2231 | ||
ca198528 FC |
2232 | if (resume) { |
2233 | r = amdgpu_ib_ring_tests(adev); | |
2234 | if (r) | |
2235 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2236 | } | |
d38ceaf9 AD |
2237 | |
2238 | r = amdgpu_late_init(adev); | |
c085bd51 JQ |
2239 | if (r) { |
2240 | if (fbcon) | |
2241 | console_unlock(); | |
d38ceaf9 | 2242 | return r; |
c085bd51 | 2243 | } |
d38ceaf9 | 2244 | |
756e6880 AD |
2245 | /* pin cursors */ |
2246 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2247 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2248 | ||
2249 | if (amdgpu_crtc->cursor_bo) { | |
2250 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2251 | r = amdgpu_bo_reserve(aobj, false); | |
2252 | if (r == 0) { | |
2253 | r = amdgpu_bo_pin(aobj, | |
2254 | AMDGPU_GEM_DOMAIN_VRAM, | |
2255 | &amdgpu_crtc->cursor_addr); | |
2256 | if (r != 0) | |
2257 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2258 | amdgpu_bo_unreserve(aobj); | |
2259 | } | |
2260 | } | |
2261 | } | |
2262 | ||
d38ceaf9 AD |
2263 | /* blat the mode back in */ |
2264 | if (fbcon) { | |
2265 | drm_helper_resume_force_mode(dev); | |
2266 | /* turn on display hw */ | |
4c7fbc39 | 2267 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2268 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2269 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2270 | } | |
4c7fbc39 | 2271 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2272 | } |
2273 | ||
2274 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2275 | |
2276 | /* | |
2277 | * Most of the connector probing functions try to acquire runtime pm | |
2278 | * refs to ensure that the GPU is powered on when connector polling is | |
2279 | * performed. Since we're calling this from a runtime PM callback, | |
2280 | * trying to acquire rpm refs will cause us to deadlock. | |
2281 | * | |
2282 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2283 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2284 | */ | |
2285 | #ifdef CONFIG_PM | |
2286 | dev->dev->power.disable_depth++; | |
2287 | #endif | |
54fb2a5c | 2288 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2289 | #ifdef CONFIG_PM |
2290 | dev->dev->power.disable_depth--; | |
2291 | #endif | |
d38ceaf9 AD |
2292 | |
2293 | if (fbcon) { | |
2294 | amdgpu_fbdev_set_suspend(adev, 0); | |
2295 | console_unlock(); | |
2296 | } | |
2297 | ||
2298 | return 0; | |
2299 | } | |
2300 | ||
63fbf42f CZ |
2301 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2302 | { | |
2303 | int i; | |
2304 | bool asic_hang = false; | |
2305 | ||
2306 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2307 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2308 | continue; |
a1255107 AD |
2309 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2310 | adev->ip_blocks[i].status.hang = | |
2311 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2312 | if (adev->ip_blocks[i].status.hang) { | |
2313 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2314 | asic_hang = true; |
2315 | } | |
2316 | } | |
2317 | return asic_hang; | |
2318 | } | |
2319 | ||
4d446656 | 2320 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2321 | { |
2322 | int i, r = 0; | |
2323 | ||
2324 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2325 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2326 | continue; |
a1255107 AD |
2327 | if (adev->ip_blocks[i].status.hang && |
2328 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2329 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2330 | if (r) |
2331 | return r; | |
2332 | } | |
2333 | } | |
2334 | ||
2335 | return 0; | |
2336 | } | |
2337 | ||
35d782fe CZ |
2338 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2339 | { | |
da146d3b AD |
2340 | int i; |
2341 | ||
2342 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2343 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2344 | continue; |
a1255107 AD |
2345 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2346 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2347 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2348 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2349 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2350 | DRM_INFO("Some block need full reset!\n"); |
2351 | return true; | |
2352 | } | |
2353 | } | |
35d782fe CZ |
2354 | } |
2355 | return false; | |
2356 | } | |
2357 | ||
2358 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2359 | { | |
2360 | int i, r = 0; | |
2361 | ||
2362 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2363 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2364 | continue; |
a1255107 AD |
2365 | if (adev->ip_blocks[i].status.hang && |
2366 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2367 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2368 | if (r) |
2369 | return r; | |
2370 | } | |
2371 | } | |
2372 | ||
2373 | return 0; | |
2374 | } | |
2375 | ||
2376 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2377 | { | |
2378 | int i, r = 0; | |
2379 | ||
2380 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2381 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2382 | continue; |
a1255107 AD |
2383 | if (adev->ip_blocks[i].status.hang && |
2384 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2385 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2386 | if (r) |
2387 | return r; | |
2388 | } | |
2389 | ||
2390 | return 0; | |
2391 | } | |
2392 | ||
3ad81f16 CZ |
2393 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2394 | { | |
2395 | if (adev->flags & AMD_IS_APU) | |
2396 | return false; | |
2397 | ||
2398 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2399 | } | |
2400 | ||
53cdccd5 CZ |
2401 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2402 | struct amdgpu_ring *ring, | |
2403 | struct amdgpu_bo *bo, | |
f54d1867 | 2404 | struct dma_fence **fence) |
53cdccd5 CZ |
2405 | { |
2406 | uint32_t domain; | |
2407 | int r; | |
2408 | ||
2409 | if (!bo->shadow) | |
2410 | return 0; | |
2411 | ||
2412 | r = amdgpu_bo_reserve(bo, false); | |
2413 | if (r) | |
2414 | return r; | |
2415 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2416 | /* if bo has been evicted, then no need to recover */ | |
2417 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
2418 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, | |
2419 | NULL, fence, true); | |
2420 | if (r) { | |
2421 | DRM_ERROR("recover page table failed!\n"); | |
2422 | goto err; | |
2423 | } | |
2424 | } | |
2425 | err: | |
2426 | amdgpu_bo_unreserve(bo); | |
2427 | return r; | |
2428 | } | |
2429 | ||
a90ad3c2 ML |
2430 | /** |
2431 | * amdgpu_sriov_gpu_reset - reset the asic | |
2432 | * | |
2433 | * @adev: amdgpu device pointer | |
2434 | * @voluntary: if this reset is requested by guest. | |
2435 | * (true means by guest and false means by HYPERVISOR ) | |
2436 | * | |
2437 | * Attempt the reset the GPU if it has hung (all asics). | |
2438 | * for SRIOV case. | |
2439 | * Returns 0 for success or an error on failure. | |
2440 | */ | |
2441 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary) | |
2442 | { | |
2443 | int i, r = 0; | |
2444 | int resched; | |
2445 | struct amdgpu_bo *bo, *tmp; | |
2446 | struct amdgpu_ring *ring; | |
2447 | struct dma_fence *fence = NULL, *next = NULL; | |
2448 | ||
147b5983 | 2449 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2450 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2451 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2452 | |
2453 | /* block TTM */ | |
2454 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2455 | ||
2456 | /* block scheduler */ | |
2457 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2458 | ring = adev->rings[i]; | |
2459 | ||
2460 | if (!ring || !ring->sched.thread) | |
2461 | continue; | |
2462 | ||
2463 | kthread_park(ring->sched.thread); | |
2464 | amd_sched_hw_job_reset(&ring->sched); | |
2465 | } | |
2466 | ||
2467 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ | |
2468 | amdgpu_fence_driver_force_completion(adev); | |
2469 | ||
2470 | /* request to take full control of GPU before re-initialization */ | |
2471 | if (voluntary) | |
2472 | amdgpu_virt_reset_gpu(adev); | |
2473 | else | |
2474 | amdgpu_virt_request_full_gpu(adev, true); | |
2475 | ||
2476 | ||
2477 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2478 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2479 | |
2480 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2481 | amdgpu_ttm_recover_gart(adev); | |
2482 | ||
2483 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2484 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2485 | |
2486 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2487 | ||
2488 | if (amdgpu_ib_ring_tests(adev)) | |
2489 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2490 | ||
2491 | /* release full control of GPU after ib test */ | |
2492 | amdgpu_virt_release_full_gpu(adev, true); | |
2493 | ||
2494 | DRM_INFO("recover vram bo from shadow\n"); | |
2495 | ||
2496 | ring = adev->mman.buffer_funcs_ring; | |
2497 | mutex_lock(&adev->shadow_list_lock); | |
2498 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2499 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); | |
2500 | if (fence) { | |
2501 | r = dma_fence_wait(fence, false); | |
2502 | if (r) { | |
2503 | WARN(r, "recovery from shadow isn't completed\n"); | |
2504 | break; | |
2505 | } | |
2506 | } | |
2507 | ||
2508 | dma_fence_put(fence); | |
2509 | fence = next; | |
2510 | } | |
2511 | mutex_unlock(&adev->shadow_list_lock); | |
2512 | ||
2513 | if (fence) { | |
2514 | r = dma_fence_wait(fence, false); | |
2515 | if (r) | |
2516 | WARN(r, "recovery from shadow isn't completed\n"); | |
2517 | } | |
2518 | dma_fence_put(fence); | |
2519 | ||
2520 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2521 | struct amdgpu_ring *ring = adev->rings[i]; | |
2522 | if (!ring || !ring->sched.thread) | |
2523 | continue; | |
2524 | ||
2525 | amd_sched_job_recovery(&ring->sched); | |
2526 | kthread_unpark(ring->sched.thread); | |
2527 | } | |
2528 | ||
2529 | drm_helper_resume_force_mode(adev->ddev); | |
2530 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2531 | if (r) { | |
2532 | /* bad news, how to tell it to userspace ? */ | |
2533 | dev_info(adev->dev, "GPU reset failed\n"); | |
2534 | } | |
2535 | ||
1fb37a3d | 2536 | adev->gfx.in_reset = false; |
147b5983 | 2537 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2538 | return r; |
2539 | } | |
2540 | ||
d38ceaf9 AD |
2541 | /** |
2542 | * amdgpu_gpu_reset - reset the asic | |
2543 | * | |
2544 | * @adev: amdgpu device pointer | |
2545 | * | |
2546 | * Attempt the reset the GPU if it has hung (all asics). | |
2547 | * Returns 0 for success or an error on failure. | |
2548 | */ | |
2549 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2550 | { | |
d38ceaf9 AD |
2551 | int i, r; |
2552 | int resched; | |
35d782fe | 2553 | bool need_full_reset; |
d38ceaf9 | 2554 | |
fb140b29 | 2555 | if (amdgpu_sriov_vf(adev)) |
a90ad3c2 | 2556 | return amdgpu_sriov_gpu_reset(adev, true); |
fb140b29 | 2557 | |
63fbf42f CZ |
2558 | if (!amdgpu_check_soft_reset(adev)) { |
2559 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2560 | return 0; | |
2561 | } | |
d38ceaf9 | 2562 | |
d94aed5a | 2563 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2564 | |
a3c47d6b CZ |
2565 | /* block TTM */ |
2566 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2567 | ||
0875dc9e CZ |
2568 | /* block scheduler */ |
2569 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2570 | struct amdgpu_ring *ring = adev->rings[i]; | |
2571 | ||
2572 | if (!ring) | |
2573 | continue; | |
2574 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2575 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2576 | } |
2200edac CZ |
2577 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2578 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2579 | |
35d782fe | 2580 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2581 | |
35d782fe CZ |
2582 | if (!need_full_reset) { |
2583 | amdgpu_pre_soft_reset(adev); | |
2584 | r = amdgpu_soft_reset(adev); | |
2585 | amdgpu_post_soft_reset(adev); | |
2586 | if (r || amdgpu_check_soft_reset(adev)) { | |
2587 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2588 | need_full_reset = true; | |
2589 | } | |
f1aa7e08 CZ |
2590 | } |
2591 | ||
35d782fe | 2592 | if (need_full_reset) { |
35d782fe | 2593 | r = amdgpu_suspend(adev); |
bfa99269 | 2594 | |
35d782fe CZ |
2595 | retry: |
2596 | /* Disable fb access */ | |
2597 | if (adev->mode_info.num_crtc) { | |
2598 | struct amdgpu_mode_mc_save save; | |
2599 | amdgpu_display_stop_mc_access(adev, &save); | |
2600 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
2601 | } | |
be34d3bf AD |
2602 | if (adev->is_atom_fw) |
2603 | amdgpu_atomfirmware_scratch_regs_save(adev); | |
2604 | else | |
2605 | amdgpu_atombios_scratch_regs_save(adev); | |
35d782fe | 2606 | r = amdgpu_asic_reset(adev); |
be34d3bf AD |
2607 | if (adev->is_atom_fw) |
2608 | amdgpu_atomfirmware_scratch_regs_restore(adev); | |
2609 | else | |
2610 | amdgpu_atombios_scratch_regs_restore(adev); | |
35d782fe CZ |
2611 | /* post card */ |
2612 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2613 | ||
2614 | if (!r) { | |
2615 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
2616 | r = amdgpu_resume(adev); | |
2617 | } | |
d38ceaf9 | 2618 | } |
d38ceaf9 | 2619 | if (!r) { |
e72cfd58 | 2620 | amdgpu_irq_gpu_reset_resume_helper(adev); |
2c0d7318 CZ |
2621 | if (need_full_reset && amdgpu_need_backup(adev)) { |
2622 | r = amdgpu_ttm_recover_gart(adev); | |
2623 | if (r) | |
2624 | DRM_ERROR("gart recovery failed!!!\n"); | |
2625 | } | |
1f465087 CZ |
2626 | r = amdgpu_ib_ring_tests(adev); |
2627 | if (r) { | |
2628 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2629 | r = amdgpu_suspend(adev); |
53cdccd5 | 2630 | need_full_reset = true; |
40019dc4 | 2631 | goto retry; |
1f465087 | 2632 | } |
53cdccd5 CZ |
2633 | /** |
2634 | * recovery vm page tables, since we cannot depend on VRAM is | |
2635 | * consistent after gpu full reset. | |
2636 | */ | |
2637 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2638 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2639 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2640 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2641 | |
2642 | DRM_INFO("recover vram bo from shadow\n"); | |
2643 | mutex_lock(&adev->shadow_list_lock); | |
2644 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2645 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); | |
2646 | if (fence) { | |
f54d1867 | 2647 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2648 | if (r) { |
1d7b17b0 | 2649 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2650 | break; |
2651 | } | |
2652 | } | |
1f465087 | 2653 | |
f54d1867 | 2654 | dma_fence_put(fence); |
53cdccd5 CZ |
2655 | fence = next; |
2656 | } | |
2657 | mutex_unlock(&adev->shadow_list_lock); | |
2658 | if (fence) { | |
f54d1867 | 2659 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2660 | if (r) |
1d7b17b0 | 2661 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2662 | } |
f54d1867 | 2663 | dma_fence_put(fence); |
53cdccd5 | 2664 | } |
d38ceaf9 AD |
2665 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2666 | struct amdgpu_ring *ring = adev->rings[i]; | |
2667 | if (!ring) | |
2668 | continue; | |
53cdccd5 | 2669 | |
aa1c8900 | 2670 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2671 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2672 | } |
d38ceaf9 | 2673 | } else { |
2200edac | 2674 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2675 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
0875dc9e CZ |
2676 | if (adev->rings[i]) { |
2677 | kthread_unpark(adev->rings[i]->sched.thread); | |
0875dc9e | 2678 | } |
d38ceaf9 AD |
2679 | } |
2680 | } | |
2681 | ||
2682 | drm_helper_resume_force_mode(adev->ddev); | |
2683 | ||
2684 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2685 | if (r) { | |
2686 | /* bad news, how to tell it to userspace ? */ | |
2687 | dev_info(adev->dev, "GPU reset failed\n"); | |
2688 | } | |
2689 | ||
d38ceaf9 AD |
2690 | return r; |
2691 | } | |
2692 | ||
d0dd7f0c AD |
2693 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2694 | { | |
2695 | u32 mask; | |
2696 | int ret; | |
2697 | ||
cd474ba0 AD |
2698 | if (amdgpu_pcie_gen_cap) |
2699 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2700 | |
cd474ba0 AD |
2701 | if (amdgpu_pcie_lane_cap) |
2702 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2703 | |
cd474ba0 AD |
2704 | /* covers APUs as well */ |
2705 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2706 | if (adev->pm.pcie_gen_mask == 0) | |
2707 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2708 | if (adev->pm.pcie_mlw_mask == 0) | |
2709 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2710 | return; |
cd474ba0 | 2711 | } |
d0dd7f0c | 2712 | |
cd474ba0 AD |
2713 | if (adev->pm.pcie_gen_mask == 0) { |
2714 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2715 | if (!ret) { | |
2716 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2717 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2718 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2719 | ||
2720 | if (mask & DRM_PCIE_SPEED_25) | |
2721 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2722 | if (mask & DRM_PCIE_SPEED_50) | |
2723 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2724 | if (mask & DRM_PCIE_SPEED_80) | |
2725 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2726 | } else { | |
2727 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2728 | } | |
2729 | } | |
2730 | if (adev->pm.pcie_mlw_mask == 0) { | |
2731 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2732 | if (!ret) { | |
2733 | switch (mask) { | |
2734 | case 32: | |
2735 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2736 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2737 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2738 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2739 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2740 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2741 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2742 | break; | |
2743 | case 16: | |
2744 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2745 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2746 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2747 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2748 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2749 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2750 | break; | |
2751 | case 12: | |
2752 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2753 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2754 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2755 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2756 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2757 | break; | |
2758 | case 8: | |
2759 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2760 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2761 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2762 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2763 | break; | |
2764 | case 4: | |
2765 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2766 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2767 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2768 | break; | |
2769 | case 2: | |
2770 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2771 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2772 | break; | |
2773 | case 1: | |
2774 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2775 | break; | |
2776 | default: | |
2777 | break; | |
2778 | } | |
2779 | } else { | |
2780 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2781 | } |
2782 | } | |
2783 | } | |
d38ceaf9 AD |
2784 | |
2785 | /* | |
2786 | * Debugfs | |
2787 | */ | |
2788 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 2789 | const struct drm_info_list *files, |
d38ceaf9 AD |
2790 | unsigned nfiles) |
2791 | { | |
2792 | unsigned i; | |
2793 | ||
2794 | for (i = 0; i < adev->debugfs_count; i++) { | |
2795 | if (adev->debugfs[i].files == files) { | |
2796 | /* Already registered */ | |
2797 | return 0; | |
2798 | } | |
2799 | } | |
2800 | ||
2801 | i = adev->debugfs_count + 1; | |
2802 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
2803 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
2804 | DRM_ERROR("Report so we increase " | |
2805 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
2806 | return -EINVAL; | |
2807 | } | |
2808 | adev->debugfs[adev->debugfs_count].files = files; | |
2809 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
2810 | adev->debugfs_count = i; | |
2811 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
2812 | drm_debugfs_create_files(files, nfiles, |
2813 | adev->ddev->primary->debugfs_root, | |
2814 | adev->ddev->primary); | |
2815 | #endif | |
2816 | return 0; | |
2817 | } | |
2818 | ||
d38ceaf9 AD |
2819 | #if defined(CONFIG_DEBUG_FS) |
2820 | ||
2821 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
2822 | size_t size, loff_t *pos) | |
2823 | { | |
45063097 | 2824 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
2825 | ssize_t result = 0; |
2826 | int r; | |
bd12267d | 2827 | bool pm_pg_lock, use_bank; |
56628159 | 2828 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
2829 | |
2830 | if (size & 0x3 || *pos & 0x3) | |
2831 | return -EINVAL; | |
2832 | ||
bd12267d TSD |
2833 | /* are we reading registers for which a PG lock is necessary? */ |
2834 | pm_pg_lock = (*pos >> 23) & 1; | |
2835 | ||
56628159 TSD |
2836 | if (*pos & (1ULL << 62)) { |
2837 | se_bank = (*pos >> 24) & 0x3FF; | |
2838 | sh_bank = (*pos >> 34) & 0x3FF; | |
2839 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
2840 | |
2841 | if (se_bank == 0x3FF) | |
2842 | se_bank = 0xFFFFFFFF; | |
2843 | if (sh_bank == 0x3FF) | |
2844 | sh_bank = 0xFFFFFFFF; | |
2845 | if (instance_bank == 0x3FF) | |
2846 | instance_bank = 0xFFFFFFFF; | |
56628159 | 2847 | use_bank = 1; |
56628159 TSD |
2848 | } else { |
2849 | use_bank = 0; | |
2850 | } | |
2851 | ||
801a6aa9 | 2852 | *pos &= (1UL << 22) - 1; |
bd12267d | 2853 | |
56628159 | 2854 | if (use_bank) { |
32977f93 TSD |
2855 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
2856 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
2857 | return -EINVAL; |
2858 | mutex_lock(&adev->grbm_idx_mutex); | |
2859 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2860 | sh_bank, instance_bank); | |
2861 | } | |
2862 | ||
bd12267d TSD |
2863 | if (pm_pg_lock) |
2864 | mutex_lock(&adev->pm.mutex); | |
2865 | ||
d38ceaf9 AD |
2866 | while (size) { |
2867 | uint32_t value; | |
2868 | ||
2869 | if (*pos > adev->rmmio_size) | |
56628159 | 2870 | goto end; |
d38ceaf9 AD |
2871 | |
2872 | value = RREG32(*pos >> 2); | |
2873 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
2874 | if (r) { |
2875 | result = r; | |
2876 | goto end; | |
2877 | } | |
d38ceaf9 AD |
2878 | |
2879 | result += 4; | |
2880 | buf += 4; | |
2881 | *pos += 4; | |
2882 | size -= 4; | |
2883 | } | |
2884 | ||
56628159 TSD |
2885 | end: |
2886 | if (use_bank) { | |
2887 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2888 | mutex_unlock(&adev->grbm_idx_mutex); | |
2889 | } | |
2890 | ||
bd12267d TSD |
2891 | if (pm_pg_lock) |
2892 | mutex_unlock(&adev->pm.mutex); | |
2893 | ||
d38ceaf9 AD |
2894 | return result; |
2895 | } | |
2896 | ||
2897 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
2898 | size_t size, loff_t *pos) | |
2899 | { | |
45063097 | 2900 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
2901 | ssize_t result = 0; |
2902 | int r; | |
394fdde2 TSD |
2903 | bool pm_pg_lock, use_bank; |
2904 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
2905 | |
2906 | if (size & 0x3 || *pos & 0x3) | |
2907 | return -EINVAL; | |
2908 | ||
394fdde2 TSD |
2909 | /* are we reading registers for which a PG lock is necessary? */ |
2910 | pm_pg_lock = (*pos >> 23) & 1; | |
2911 | ||
2912 | if (*pos & (1ULL << 62)) { | |
2913 | se_bank = (*pos >> 24) & 0x3FF; | |
2914 | sh_bank = (*pos >> 34) & 0x3FF; | |
2915 | instance_bank = (*pos >> 44) & 0x3FF; | |
2916 | ||
2917 | if (se_bank == 0x3FF) | |
2918 | se_bank = 0xFFFFFFFF; | |
2919 | if (sh_bank == 0x3FF) | |
2920 | sh_bank = 0xFFFFFFFF; | |
2921 | if (instance_bank == 0x3FF) | |
2922 | instance_bank = 0xFFFFFFFF; | |
2923 | use_bank = 1; | |
2924 | } else { | |
2925 | use_bank = 0; | |
2926 | } | |
2927 | ||
801a6aa9 | 2928 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
2929 | |
2930 | if (use_bank) { | |
2931 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
2932 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
2933 | return -EINVAL; | |
2934 | mutex_lock(&adev->grbm_idx_mutex); | |
2935 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2936 | sh_bank, instance_bank); | |
2937 | } | |
2938 | ||
2939 | if (pm_pg_lock) | |
2940 | mutex_lock(&adev->pm.mutex); | |
2941 | ||
d38ceaf9 AD |
2942 | while (size) { |
2943 | uint32_t value; | |
2944 | ||
2945 | if (*pos > adev->rmmio_size) | |
2946 | return result; | |
2947 | ||
2948 | r = get_user(value, (uint32_t *)buf); | |
2949 | if (r) | |
2950 | return r; | |
2951 | ||
2952 | WREG32(*pos >> 2, value); | |
2953 | ||
2954 | result += 4; | |
2955 | buf += 4; | |
2956 | *pos += 4; | |
2957 | size -= 4; | |
2958 | } | |
2959 | ||
394fdde2 TSD |
2960 | if (use_bank) { |
2961 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2962 | mutex_unlock(&adev->grbm_idx_mutex); | |
2963 | } | |
2964 | ||
2965 | if (pm_pg_lock) | |
2966 | mutex_unlock(&adev->pm.mutex); | |
2967 | ||
d38ceaf9 AD |
2968 | return result; |
2969 | } | |
2970 | ||
adcec288 TSD |
2971 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
2972 | size_t size, loff_t *pos) | |
2973 | { | |
45063097 | 2974 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
2975 | ssize_t result = 0; |
2976 | int r; | |
2977 | ||
2978 | if (size & 0x3 || *pos & 0x3) | |
2979 | return -EINVAL; | |
2980 | ||
2981 | while (size) { | |
2982 | uint32_t value; | |
2983 | ||
2984 | value = RREG32_PCIE(*pos >> 2); | |
2985 | r = put_user(value, (uint32_t *)buf); | |
2986 | if (r) | |
2987 | return r; | |
2988 | ||
2989 | result += 4; | |
2990 | buf += 4; | |
2991 | *pos += 4; | |
2992 | size -= 4; | |
2993 | } | |
2994 | ||
2995 | return result; | |
2996 | } | |
2997 | ||
2998 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
2999 | size_t size, loff_t *pos) | |
3000 | { | |
45063097 | 3001 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3002 | ssize_t result = 0; |
3003 | int r; | |
3004 | ||
3005 | if (size & 0x3 || *pos & 0x3) | |
3006 | return -EINVAL; | |
3007 | ||
3008 | while (size) { | |
3009 | uint32_t value; | |
3010 | ||
3011 | r = get_user(value, (uint32_t *)buf); | |
3012 | if (r) | |
3013 | return r; | |
3014 | ||
3015 | WREG32_PCIE(*pos >> 2, value); | |
3016 | ||
3017 | result += 4; | |
3018 | buf += 4; | |
3019 | *pos += 4; | |
3020 | size -= 4; | |
3021 | } | |
3022 | ||
3023 | return result; | |
3024 | } | |
3025 | ||
3026 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3027 | size_t size, loff_t *pos) | |
3028 | { | |
45063097 | 3029 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3030 | ssize_t result = 0; |
3031 | int r; | |
3032 | ||
3033 | if (size & 0x3 || *pos & 0x3) | |
3034 | return -EINVAL; | |
3035 | ||
3036 | while (size) { | |
3037 | uint32_t value; | |
3038 | ||
3039 | value = RREG32_DIDT(*pos >> 2); | |
3040 | r = put_user(value, (uint32_t *)buf); | |
3041 | if (r) | |
3042 | return r; | |
3043 | ||
3044 | result += 4; | |
3045 | buf += 4; | |
3046 | *pos += 4; | |
3047 | size -= 4; | |
3048 | } | |
3049 | ||
3050 | return result; | |
3051 | } | |
3052 | ||
3053 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3054 | size_t size, loff_t *pos) | |
3055 | { | |
45063097 | 3056 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3057 | ssize_t result = 0; |
3058 | int r; | |
3059 | ||
3060 | if (size & 0x3 || *pos & 0x3) | |
3061 | return -EINVAL; | |
3062 | ||
3063 | while (size) { | |
3064 | uint32_t value; | |
3065 | ||
3066 | r = get_user(value, (uint32_t *)buf); | |
3067 | if (r) | |
3068 | return r; | |
3069 | ||
3070 | WREG32_DIDT(*pos >> 2, value); | |
3071 | ||
3072 | result += 4; | |
3073 | buf += 4; | |
3074 | *pos += 4; | |
3075 | size -= 4; | |
3076 | } | |
3077 | ||
3078 | return result; | |
3079 | } | |
3080 | ||
3081 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3082 | size_t size, loff_t *pos) | |
3083 | { | |
45063097 | 3084 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3085 | ssize_t result = 0; |
3086 | int r; | |
3087 | ||
3088 | if (size & 0x3 || *pos & 0x3) | |
3089 | return -EINVAL; | |
3090 | ||
3091 | while (size) { | |
3092 | uint32_t value; | |
3093 | ||
6fc0deaf | 3094 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3095 | r = put_user(value, (uint32_t *)buf); |
3096 | if (r) | |
3097 | return r; | |
3098 | ||
3099 | result += 4; | |
3100 | buf += 4; | |
3101 | *pos += 4; | |
3102 | size -= 4; | |
3103 | } | |
3104 | ||
3105 | return result; | |
3106 | } | |
3107 | ||
3108 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3109 | size_t size, loff_t *pos) | |
3110 | { | |
45063097 | 3111 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3112 | ssize_t result = 0; |
3113 | int r; | |
3114 | ||
3115 | if (size & 0x3 || *pos & 0x3) | |
3116 | return -EINVAL; | |
3117 | ||
3118 | while (size) { | |
3119 | uint32_t value; | |
3120 | ||
3121 | r = get_user(value, (uint32_t *)buf); | |
3122 | if (r) | |
3123 | return r; | |
3124 | ||
6fc0deaf | 3125 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3126 | |
3127 | result += 4; | |
3128 | buf += 4; | |
3129 | *pos += 4; | |
3130 | size -= 4; | |
3131 | } | |
3132 | ||
3133 | return result; | |
3134 | } | |
3135 | ||
1e051413 TSD |
3136 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3137 | size_t size, loff_t *pos) | |
3138 | { | |
45063097 | 3139 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3140 | ssize_t result = 0; |
3141 | int r; | |
3142 | uint32_t *config, no_regs = 0; | |
3143 | ||
3144 | if (size & 0x3 || *pos & 0x3) | |
3145 | return -EINVAL; | |
3146 | ||
ecab7668 | 3147 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3148 | if (!config) |
3149 | return -ENOMEM; | |
3150 | ||
3151 | /* version, increment each time something is added */ | |
9a999359 | 3152 | config[no_regs++] = 3; |
1e051413 TSD |
3153 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3154 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3155 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3156 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3157 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3158 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3159 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3160 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3161 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3162 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3163 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3164 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3165 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3166 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3167 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3168 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3169 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3170 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3171 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3172 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3173 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3174 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3175 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3176 | ||
89a8f309 TSD |
3177 | /* rev==1 */ |
3178 | config[no_regs++] = adev->rev_id; | |
3179 | config[no_regs++] = adev->pg_flags; | |
3180 | config[no_regs++] = adev->cg_flags; | |
3181 | ||
e9f11dc8 TSD |
3182 | /* rev==2 */ |
3183 | config[no_regs++] = adev->family; | |
3184 | config[no_regs++] = adev->external_rev_id; | |
3185 | ||
9a999359 TSD |
3186 | /* rev==3 */ |
3187 | config[no_regs++] = adev->pdev->device; | |
3188 | config[no_regs++] = adev->pdev->revision; | |
3189 | config[no_regs++] = adev->pdev->subsystem_device; | |
3190 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3191 | ||
1e051413 TSD |
3192 | while (size && (*pos < no_regs * 4)) { |
3193 | uint32_t value; | |
3194 | ||
3195 | value = config[*pos >> 2]; | |
3196 | r = put_user(value, (uint32_t *)buf); | |
3197 | if (r) { | |
3198 | kfree(config); | |
3199 | return r; | |
3200 | } | |
3201 | ||
3202 | result += 4; | |
3203 | buf += 4; | |
3204 | *pos += 4; | |
3205 | size -= 4; | |
3206 | } | |
3207 | ||
3208 | kfree(config); | |
3209 | return result; | |
3210 | } | |
3211 | ||
f2cdaf20 TSD |
3212 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3213 | size_t size, loff_t *pos) | |
3214 | { | |
45063097 | 3215 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3216 | int idx, x, outsize, r, valuesize; |
3217 | uint32_t values[16]; | |
f2cdaf20 | 3218 | |
9f8df7d7 | 3219 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3220 | return -EINVAL; |
3221 | ||
3cbc614f SP |
3222 | if (amdgpu_dpm == 0) |
3223 | return -EINVAL; | |
3224 | ||
f2cdaf20 TSD |
3225 | /* convert offset to sensor number */ |
3226 | idx = *pos >> 2; | |
3227 | ||
9f8df7d7 | 3228 | valuesize = sizeof(values); |
f2cdaf20 | 3229 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3230 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3231 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3232 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3233 | &valuesize); | |
f2cdaf20 TSD |
3234 | else |
3235 | return -EINVAL; | |
3236 | ||
9f8df7d7 TSD |
3237 | if (size > valuesize) |
3238 | return -EINVAL; | |
3239 | ||
3240 | outsize = 0; | |
3241 | x = 0; | |
3242 | if (!r) { | |
3243 | while (size) { | |
3244 | r = put_user(values[x++], (int32_t *)buf); | |
3245 | buf += 4; | |
3246 | size -= 4; | |
3247 | outsize += 4; | |
3248 | } | |
3249 | } | |
f2cdaf20 | 3250 | |
9f8df7d7 | 3251 | return !r ? outsize : r; |
f2cdaf20 | 3252 | } |
1e051413 | 3253 | |
273d7aa1 TSD |
3254 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3255 | size_t size, loff_t *pos) | |
3256 | { | |
3257 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3258 | int r, x; | |
3259 | ssize_t result=0; | |
472259f0 | 3260 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3261 | |
3262 | if (size & 3 || *pos & 3) | |
3263 | return -EINVAL; | |
3264 | ||
3265 | /* decode offset */ | |
3266 | offset = (*pos & 0x7F); | |
3267 | se = ((*pos >> 7) & 0xFF); | |
3268 | sh = ((*pos >> 15) & 0xFF); | |
3269 | cu = ((*pos >> 23) & 0xFF); | |
3270 | wave = ((*pos >> 31) & 0xFF); | |
3271 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3272 | |
3273 | /* switch to the specific se/sh/cu */ | |
3274 | mutex_lock(&adev->grbm_idx_mutex); | |
3275 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3276 | ||
3277 | x = 0; | |
472259f0 TSD |
3278 | if (adev->gfx.funcs->read_wave_data) |
3279 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3280 | |
3281 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3282 | mutex_unlock(&adev->grbm_idx_mutex); | |
3283 | ||
5ecfb3b8 TSD |
3284 | if (!x) |
3285 | return -EINVAL; | |
3286 | ||
472259f0 | 3287 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3288 | uint32_t value; |
3289 | ||
472259f0 | 3290 | value = data[offset >> 2]; |
273d7aa1 TSD |
3291 | r = put_user(value, (uint32_t *)buf); |
3292 | if (r) | |
3293 | return r; | |
3294 | ||
3295 | result += 4; | |
3296 | buf += 4; | |
472259f0 | 3297 | offset += 4; |
273d7aa1 TSD |
3298 | size -= 4; |
3299 | } | |
3300 | ||
3301 | return result; | |
3302 | } | |
3303 | ||
c5a60ce8 TSD |
3304 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3305 | size_t size, loff_t *pos) | |
3306 | { | |
3307 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3308 | int r; | |
3309 | ssize_t result = 0; | |
3310 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3311 | ||
3312 | if (size & 3 || *pos & 3) | |
3313 | return -EINVAL; | |
3314 | ||
3315 | /* decode offset */ | |
3316 | offset = (*pos & 0xFFF); /* in dwords */ | |
3317 | se = ((*pos >> 12) & 0xFF); | |
3318 | sh = ((*pos >> 20) & 0xFF); | |
3319 | cu = ((*pos >> 28) & 0xFF); | |
3320 | wave = ((*pos >> 36) & 0xFF); | |
3321 | simd = ((*pos >> 44) & 0xFF); | |
3322 | thread = ((*pos >> 52) & 0xFF); | |
3323 | bank = ((*pos >> 60) & 1); | |
3324 | ||
3325 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3326 | if (!data) | |
3327 | return -ENOMEM; | |
3328 | ||
3329 | /* switch to the specific se/sh/cu */ | |
3330 | mutex_lock(&adev->grbm_idx_mutex); | |
3331 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3332 | ||
3333 | if (bank == 0) { | |
3334 | if (adev->gfx.funcs->read_wave_vgprs) | |
3335 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3336 | } else { | |
3337 | if (adev->gfx.funcs->read_wave_sgprs) | |
3338 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3339 | } | |
3340 | ||
3341 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3342 | mutex_unlock(&adev->grbm_idx_mutex); | |
3343 | ||
3344 | while (size) { | |
3345 | uint32_t value; | |
3346 | ||
3347 | value = data[offset++]; | |
3348 | r = put_user(value, (uint32_t *)buf); | |
3349 | if (r) { | |
3350 | result = r; | |
3351 | goto err; | |
3352 | } | |
3353 | ||
3354 | result += 4; | |
3355 | buf += 4; | |
3356 | size -= 4; | |
3357 | } | |
3358 | ||
3359 | err: | |
3360 | kfree(data); | |
3361 | return result; | |
3362 | } | |
3363 | ||
d38ceaf9 AD |
3364 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3365 | .owner = THIS_MODULE, | |
3366 | .read = amdgpu_debugfs_regs_read, | |
3367 | .write = amdgpu_debugfs_regs_write, | |
3368 | .llseek = default_llseek | |
3369 | }; | |
adcec288 TSD |
3370 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3371 | .owner = THIS_MODULE, | |
3372 | .read = amdgpu_debugfs_regs_didt_read, | |
3373 | .write = amdgpu_debugfs_regs_didt_write, | |
3374 | .llseek = default_llseek | |
3375 | }; | |
3376 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3377 | .owner = THIS_MODULE, | |
3378 | .read = amdgpu_debugfs_regs_pcie_read, | |
3379 | .write = amdgpu_debugfs_regs_pcie_write, | |
3380 | .llseek = default_llseek | |
3381 | }; | |
3382 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3383 | .owner = THIS_MODULE, | |
3384 | .read = amdgpu_debugfs_regs_smc_read, | |
3385 | .write = amdgpu_debugfs_regs_smc_write, | |
3386 | .llseek = default_llseek | |
3387 | }; | |
3388 | ||
1e051413 TSD |
3389 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3390 | .owner = THIS_MODULE, | |
3391 | .read = amdgpu_debugfs_gca_config_read, | |
3392 | .llseek = default_llseek | |
3393 | }; | |
3394 | ||
f2cdaf20 TSD |
3395 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3396 | .owner = THIS_MODULE, | |
3397 | .read = amdgpu_debugfs_sensor_read, | |
3398 | .llseek = default_llseek | |
3399 | }; | |
3400 | ||
273d7aa1 TSD |
3401 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3402 | .owner = THIS_MODULE, | |
3403 | .read = amdgpu_debugfs_wave_read, | |
3404 | .llseek = default_llseek | |
3405 | }; | |
c5a60ce8 TSD |
3406 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3407 | .owner = THIS_MODULE, | |
3408 | .read = amdgpu_debugfs_gpr_read, | |
3409 | .llseek = default_llseek | |
3410 | }; | |
273d7aa1 | 3411 | |
adcec288 TSD |
3412 | static const struct file_operations *debugfs_regs[] = { |
3413 | &amdgpu_debugfs_regs_fops, | |
3414 | &amdgpu_debugfs_regs_didt_fops, | |
3415 | &amdgpu_debugfs_regs_pcie_fops, | |
3416 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3417 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3418 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3419 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3420 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3421 | }; |
3422 | ||
3423 | static const char *debugfs_regs_names[] = { | |
3424 | "amdgpu_regs", | |
3425 | "amdgpu_regs_didt", | |
3426 | "amdgpu_regs_pcie", | |
3427 | "amdgpu_regs_smc", | |
1e051413 | 3428 | "amdgpu_gca_config", |
f2cdaf20 | 3429 | "amdgpu_sensors", |
273d7aa1 | 3430 | "amdgpu_wave", |
c5a60ce8 | 3431 | "amdgpu_gpr", |
adcec288 | 3432 | }; |
d38ceaf9 AD |
3433 | |
3434 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3435 | { | |
3436 | struct drm_minor *minor = adev->ddev->primary; | |
3437 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3438 | unsigned i, j; |
3439 | ||
3440 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3441 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3442 | S_IFREG | S_IRUGO, root, | |
3443 | adev, debugfs_regs[i]); | |
3444 | if (IS_ERR(ent)) { | |
3445 | for (j = 0; j < i; j++) { | |
3446 | debugfs_remove(adev->debugfs_regs[i]); | |
3447 | adev->debugfs_regs[i] = NULL; | |
3448 | } | |
3449 | return PTR_ERR(ent); | |
3450 | } | |
d38ceaf9 | 3451 | |
adcec288 TSD |
3452 | if (!i) |
3453 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3454 | adev->debugfs_regs[i] = ent; | |
3455 | } | |
d38ceaf9 AD |
3456 | |
3457 | return 0; | |
3458 | } | |
3459 | ||
3460 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3461 | { | |
adcec288 TSD |
3462 | unsigned i; |
3463 | ||
3464 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3465 | if (adev->debugfs_regs[i]) { | |
3466 | debugfs_remove(adev->debugfs_regs[i]); | |
3467 | adev->debugfs_regs[i] = NULL; | |
3468 | } | |
3469 | } | |
d38ceaf9 AD |
3470 | } |
3471 | ||
3472 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
3473 | { | |
3474 | return 0; | |
3475 | } | |
7cebc728 AK |
3476 | #else |
3477 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3478 | { | |
3479 | return 0; | |
3480 | } | |
3481 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3482 | #endif |