Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
4562236b | 33 | #include <drm/drm_atomic_helper.h> |
d38ceaf9 AD |
34 | #include <drm/amdgpu_drm.h> |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
ba997709 | 58 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 59 | #include "amdgpu_pm.h" |
d38ceaf9 | 60 | |
e2a75f88 | 61 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 62 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 63 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 64 | |
2dc80b00 S |
65 | #define AMDGPU_RESUME_MS 2000 |
66 | ||
d38ceaf9 | 67 | static const char *amdgpu_asic_name[] = { |
da69c161 KW |
68 | "TAHITI", |
69 | "PITCAIRN", | |
70 | "VERDE", | |
71 | "OLAND", | |
72 | "HAINAN", | |
d38ceaf9 AD |
73 | "BONAIRE", |
74 | "KAVERI", | |
75 | "KABINI", | |
76 | "HAWAII", | |
77 | "MULLINS", | |
78 | "TOPAZ", | |
79 | "TONGA", | |
48299f95 | 80 | "FIJI", |
d38ceaf9 | 81 | "CARRIZO", |
139f4917 | 82 | "STONEY", |
2cc0c0b5 FC |
83 | "POLARIS10", |
84 | "POLARIS11", | |
c4642a47 | 85 | "POLARIS12", |
48ff108d | 86 | "VEGAM", |
d4196f01 | 87 | "VEGA10", |
8fab806a | 88 | "VEGA12", |
956fcddc | 89 | "VEGA20", |
2ca8a5d2 | 90 | "RAVEN", |
d38ceaf9 AD |
91 | "LAST", |
92 | }; | |
93 | ||
5494d864 AD |
94 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
95 | ||
e3ecdffa AD |
96 | /** |
97 | * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control | |
98 | * | |
99 | * @dev: drm_device pointer | |
100 | * | |
101 | * Returns true if the device is a dGPU with HG/PX power control, | |
102 | * otherwise return false. | |
103 | */ | |
d38ceaf9 AD |
104 | bool amdgpu_device_is_px(struct drm_device *dev) |
105 | { | |
106 | struct amdgpu_device *adev = dev->dev_private; | |
107 | ||
2f7d10b3 | 108 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
109 | return true; |
110 | return false; | |
111 | } | |
112 | ||
113 | /* | |
114 | * MMIO register access helper functions. | |
115 | */ | |
e3ecdffa AD |
116 | /** |
117 | * amdgpu_mm_rreg - read a memory mapped IO register | |
118 | * | |
119 | * @adev: amdgpu_device pointer | |
120 | * @reg: dword aligned register offset | |
121 | * @acc_flags: access flags which require special behavior | |
122 | * | |
123 | * Returns the 32 bit value from the offset specified. | |
124 | */ | |
d38ceaf9 | 125 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
15d72fd7 | 126 | uint32_t acc_flags) |
d38ceaf9 | 127 | { |
f4b373f4 TSD |
128 | uint32_t ret; |
129 | ||
43ca8efa | 130 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 131 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 132 | |
15d72fd7 | 133 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 134 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
135 | else { |
136 | unsigned long flags; | |
d38ceaf9 AD |
137 | |
138 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
139 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
140 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
141 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 142 | } |
f4b373f4 TSD |
143 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
144 | return ret; | |
d38ceaf9 AD |
145 | } |
146 | ||
421a2a30 ML |
147 | /* |
148 | * MMIO register read with bytes helper functions | |
149 | * @offset:bytes offset from MMIO start | |
150 | * | |
151 | */ | |
152 | ||
e3ecdffa AD |
153 | /** |
154 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
155 | * | |
156 | * @adev: amdgpu_device pointer | |
157 | * @offset: byte aligned register offset | |
158 | * | |
159 | * Returns the 8 bit value from the offset specified. | |
160 | */ | |
421a2a30 ML |
161 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
162 | if (offset < adev->rmmio_size) | |
163 | return (readb(adev->rmmio + offset)); | |
164 | BUG(); | |
165 | } | |
166 | ||
167 | /* | |
168 | * MMIO register write with bytes helper functions | |
169 | * @offset:bytes offset from MMIO start | |
170 | * @value: the value want to be written to the register | |
171 | * | |
172 | */ | |
e3ecdffa AD |
173 | /** |
174 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
175 | * | |
176 | * @adev: amdgpu_device pointer | |
177 | * @offset: byte aligned register offset | |
178 | * @value: 8 bit value to write | |
179 | * | |
180 | * Writes the value specified to the offset specified. | |
181 | */ | |
421a2a30 ML |
182 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
183 | if (offset < adev->rmmio_size) | |
184 | writeb(value, adev->rmmio + offset); | |
185 | else | |
186 | BUG(); | |
187 | } | |
188 | ||
e3ecdffa AD |
189 | /** |
190 | * amdgpu_mm_wreg - write to a memory mapped IO register | |
191 | * | |
192 | * @adev: amdgpu_device pointer | |
193 | * @reg: dword aligned register offset | |
194 | * @v: 32 bit value to write to the register | |
195 | * @acc_flags: access flags which require special behavior | |
196 | * | |
197 | * Writes the value specified to the offset specified. | |
198 | */ | |
d38ceaf9 | 199 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 200 | uint32_t acc_flags) |
d38ceaf9 | 201 | { |
f4b373f4 | 202 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 203 | |
47ed4e1c KW |
204 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
205 | adev->last_mm_index = v; | |
206 | } | |
207 | ||
43ca8efa | 208 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 209 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 210 | |
15d72fd7 | 211 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
212 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
213 | else { | |
214 | unsigned long flags; | |
215 | ||
216 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
217 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
218 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
219 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
220 | } | |
47ed4e1c KW |
221 | |
222 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
223 | udelay(500); | |
224 | } | |
d38ceaf9 AD |
225 | } |
226 | ||
e3ecdffa AD |
227 | /** |
228 | * amdgpu_io_rreg - read an IO register | |
229 | * | |
230 | * @adev: amdgpu_device pointer | |
231 | * @reg: dword aligned register offset | |
232 | * | |
233 | * Returns the 32 bit value from the offset specified. | |
234 | */ | |
d38ceaf9 AD |
235 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
236 | { | |
237 | if ((reg * 4) < adev->rio_mem_size) | |
238 | return ioread32(adev->rio_mem + (reg * 4)); | |
239 | else { | |
240 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
241 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
242 | } | |
243 | } | |
244 | ||
e3ecdffa AD |
245 | /** |
246 | * amdgpu_io_wreg - write to an IO register | |
247 | * | |
248 | * @adev: amdgpu_device pointer | |
249 | * @reg: dword aligned register offset | |
250 | * @v: 32 bit value to write to the register | |
251 | * | |
252 | * Writes the value specified to the offset specified. | |
253 | */ | |
d38ceaf9 AD |
254 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
255 | { | |
47ed4e1c KW |
256 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
257 | adev->last_mm_index = v; | |
258 | } | |
d38ceaf9 AD |
259 | |
260 | if ((reg * 4) < adev->rio_mem_size) | |
261 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
262 | else { | |
263 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
264 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
265 | } | |
47ed4e1c KW |
266 | |
267 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
268 | udelay(500); | |
269 | } | |
d38ceaf9 AD |
270 | } |
271 | ||
272 | /** | |
273 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
274 | * | |
275 | * @adev: amdgpu_device pointer | |
276 | * @index: doorbell index | |
277 | * | |
278 | * Returns the value in the doorbell aperture at the | |
279 | * requested doorbell index (CIK). | |
280 | */ | |
281 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
282 | { | |
283 | if (index < adev->doorbell.num_doorbells) { | |
284 | return readl(adev->doorbell.ptr + index); | |
285 | } else { | |
286 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
287 | return 0; | |
288 | } | |
289 | } | |
290 | ||
291 | /** | |
292 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
293 | * | |
294 | * @adev: amdgpu_device pointer | |
295 | * @index: doorbell index | |
296 | * @v: value to write | |
297 | * | |
298 | * Writes @v to the doorbell aperture at the | |
299 | * requested doorbell index (CIK). | |
300 | */ | |
301 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
302 | { | |
303 | if (index < adev->doorbell.num_doorbells) { | |
304 | writel(v, adev->doorbell.ptr + index); | |
305 | } else { | |
306 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
307 | } | |
308 | } | |
309 | ||
832be404 KW |
310 | /** |
311 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
312 | * | |
313 | * @adev: amdgpu_device pointer | |
314 | * @index: doorbell index | |
315 | * | |
316 | * Returns the value in the doorbell aperture at the | |
317 | * requested doorbell index (VEGA10+). | |
318 | */ | |
319 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
320 | { | |
321 | if (index < adev->doorbell.num_doorbells) { | |
322 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
323 | } else { | |
324 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
325 | return 0; | |
326 | } | |
327 | } | |
328 | ||
329 | /** | |
330 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
331 | * | |
332 | * @adev: amdgpu_device pointer | |
333 | * @index: doorbell index | |
334 | * @v: value to write | |
335 | * | |
336 | * Writes @v to the doorbell aperture at the | |
337 | * requested doorbell index (VEGA10+). | |
338 | */ | |
339 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
340 | { | |
341 | if (index < adev->doorbell.num_doorbells) { | |
342 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
343 | } else { | |
344 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
345 | } | |
346 | } | |
347 | ||
d38ceaf9 AD |
348 | /** |
349 | * amdgpu_invalid_rreg - dummy reg read function | |
350 | * | |
351 | * @adev: amdgpu device pointer | |
352 | * @reg: offset of register | |
353 | * | |
354 | * Dummy register read function. Used for register blocks | |
355 | * that certain asics don't have (all asics). | |
356 | * Returns the value in the register. | |
357 | */ | |
358 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
359 | { | |
360 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
361 | BUG(); | |
362 | return 0; | |
363 | } | |
364 | ||
365 | /** | |
366 | * amdgpu_invalid_wreg - dummy reg write function | |
367 | * | |
368 | * @adev: amdgpu device pointer | |
369 | * @reg: offset of register | |
370 | * @v: value to write to the register | |
371 | * | |
372 | * Dummy register read function. Used for register blocks | |
373 | * that certain asics don't have (all asics). | |
374 | */ | |
375 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
376 | { | |
377 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
378 | reg, v); | |
379 | BUG(); | |
380 | } | |
381 | ||
382 | /** | |
383 | * amdgpu_block_invalid_rreg - dummy reg read function | |
384 | * | |
385 | * @adev: amdgpu device pointer | |
386 | * @block: offset of instance | |
387 | * @reg: offset of register | |
388 | * | |
389 | * Dummy register read function. Used for register blocks | |
390 | * that certain asics don't have (all asics). | |
391 | * Returns the value in the register. | |
392 | */ | |
393 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
394 | uint32_t block, uint32_t reg) | |
395 | { | |
396 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
397 | reg, block); | |
398 | BUG(); | |
399 | return 0; | |
400 | } | |
401 | ||
402 | /** | |
403 | * amdgpu_block_invalid_wreg - dummy reg write function | |
404 | * | |
405 | * @adev: amdgpu device pointer | |
406 | * @block: offset of instance | |
407 | * @reg: offset of register | |
408 | * @v: value to write to the register | |
409 | * | |
410 | * Dummy register read function. Used for register blocks | |
411 | * that certain asics don't have (all asics). | |
412 | */ | |
413 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
414 | uint32_t block, | |
415 | uint32_t reg, uint32_t v) | |
416 | { | |
417 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
418 | reg, block, v); | |
419 | BUG(); | |
420 | } | |
421 | ||
e3ecdffa AD |
422 | /** |
423 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
424 | * | |
425 | * @adev: amdgpu device pointer | |
426 | * | |
427 | * Allocates a scratch page of VRAM for use by various things in the | |
428 | * driver. | |
429 | */ | |
06ec9070 | 430 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 431 | { |
a4a02777 CK |
432 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
433 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
434 | &adev->vram_scratch.robj, | |
435 | &adev->vram_scratch.gpu_addr, | |
436 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
437 | } |
438 | ||
e3ecdffa AD |
439 | /** |
440 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
441 | * | |
442 | * @adev: amdgpu device pointer | |
443 | * | |
444 | * Frees the VRAM scratch page. | |
445 | */ | |
06ec9070 | 446 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 447 | { |
078af1a3 | 448 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
449 | } |
450 | ||
451 | /** | |
9c3f2b54 | 452 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
453 | * |
454 | * @adev: amdgpu_device pointer | |
455 | * @registers: pointer to the register array | |
456 | * @array_size: size of the register array | |
457 | * | |
458 | * Programs an array or registers with and and or masks. | |
459 | * This is a helper for setting golden registers. | |
460 | */ | |
9c3f2b54 AD |
461 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
462 | const u32 *registers, | |
463 | const u32 array_size) | |
d38ceaf9 AD |
464 | { |
465 | u32 tmp, reg, and_mask, or_mask; | |
466 | int i; | |
467 | ||
468 | if (array_size % 3) | |
469 | return; | |
470 | ||
471 | for (i = 0; i < array_size; i +=3) { | |
472 | reg = registers[i + 0]; | |
473 | and_mask = registers[i + 1]; | |
474 | or_mask = registers[i + 2]; | |
475 | ||
476 | if (and_mask == 0xffffffff) { | |
477 | tmp = or_mask; | |
478 | } else { | |
479 | tmp = RREG32(reg); | |
480 | tmp &= ~and_mask; | |
481 | tmp |= or_mask; | |
482 | } | |
483 | WREG32(reg, tmp); | |
484 | } | |
485 | } | |
486 | ||
e3ecdffa AD |
487 | /** |
488 | * amdgpu_device_pci_config_reset - reset the GPU | |
489 | * | |
490 | * @adev: amdgpu_device pointer | |
491 | * | |
492 | * Resets the GPU using the pci config reset sequence. | |
493 | * Only applicable to asics prior to vega10. | |
494 | */ | |
8111c387 | 495 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
496 | { |
497 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
498 | } | |
499 | ||
500 | /* | |
501 | * GPU doorbell aperture helpers function. | |
502 | */ | |
503 | /** | |
06ec9070 | 504 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
505 | * |
506 | * @adev: amdgpu_device pointer | |
507 | * | |
508 | * Init doorbell driver information (CIK) | |
509 | * Returns 0 on success, error on failure. | |
510 | */ | |
06ec9070 | 511 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 512 | { |
705e519e CK |
513 | /* No doorbell on SI hardware generation */ |
514 | if (adev->asic_type < CHIP_BONAIRE) { | |
515 | adev->doorbell.base = 0; | |
516 | adev->doorbell.size = 0; | |
517 | adev->doorbell.num_doorbells = 0; | |
518 | adev->doorbell.ptr = NULL; | |
519 | return 0; | |
520 | } | |
521 | ||
d6895ad3 CK |
522 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
523 | return -EINVAL; | |
524 | ||
d38ceaf9 AD |
525 | /* doorbell bar mapping */ |
526 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
527 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
528 | ||
edf600da | 529 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
530 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
531 | if (adev->doorbell.num_doorbells == 0) | |
532 | return -EINVAL; | |
533 | ||
8972e5d2 CK |
534 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
535 | adev->doorbell.num_doorbells * | |
536 | sizeof(u32)); | |
537 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 538 | return -ENOMEM; |
d38ceaf9 AD |
539 | |
540 | return 0; | |
541 | } | |
542 | ||
543 | /** | |
06ec9070 | 544 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
545 | * |
546 | * @adev: amdgpu_device pointer | |
547 | * | |
548 | * Tear down doorbell driver information (CIK) | |
549 | */ | |
06ec9070 | 550 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
551 | { |
552 | iounmap(adev->doorbell.ptr); | |
553 | adev->doorbell.ptr = NULL; | |
554 | } | |
555 | ||
22cb0164 | 556 | |
d38ceaf9 AD |
557 | |
558 | /* | |
06ec9070 | 559 | * amdgpu_device_wb_*() |
455a7bc2 | 560 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 561 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
562 | */ |
563 | ||
564 | /** | |
06ec9070 | 565 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
566 | * |
567 | * @adev: amdgpu_device pointer | |
568 | * | |
569 | * Disables Writeback and frees the Writeback memory (all asics). | |
570 | * Used at driver shutdown. | |
571 | */ | |
06ec9070 | 572 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
573 | { |
574 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
575 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
576 | &adev->wb.gpu_addr, | |
577 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
578 | adev->wb.wb_obj = NULL; |
579 | } | |
580 | } | |
581 | ||
582 | /** | |
06ec9070 | 583 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
584 | * |
585 | * @adev: amdgpu_device pointer | |
586 | * | |
455a7bc2 | 587 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
588 | * Used at driver startup. |
589 | * Returns 0 on success or an -error on failure. | |
590 | */ | |
06ec9070 | 591 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
592 | { |
593 | int r; | |
594 | ||
595 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
596 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
597 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
598 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
599 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
600 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
601 | if (r) { |
602 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
603 | return r; | |
604 | } | |
d38ceaf9 AD |
605 | |
606 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
607 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
608 | ||
609 | /* clear wb memory */ | |
73469585 | 610 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
611 | } |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | /** | |
131b4b36 | 617 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
618 | * |
619 | * @adev: amdgpu_device pointer | |
620 | * @wb: wb index | |
621 | * | |
622 | * Allocate a wb slot for use by the driver (all asics). | |
623 | * Returns 0 on success or -EINVAL on failure. | |
624 | */ | |
131b4b36 | 625 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
626 | { |
627 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 628 | |
97407b63 | 629 | if (offset < adev->wb.num_wb) { |
7014285a | 630 | __set_bit(offset, adev->wb.used); |
63ae07ca | 631 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
632 | return 0; |
633 | } else { | |
634 | return -EINVAL; | |
635 | } | |
636 | } | |
637 | ||
d38ceaf9 | 638 | /** |
131b4b36 | 639 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
640 | * |
641 | * @adev: amdgpu_device pointer | |
642 | * @wb: wb index | |
643 | * | |
644 | * Free a wb slot allocated for use by the driver (all asics) | |
645 | */ | |
131b4b36 | 646 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 647 | { |
73469585 | 648 | wb >>= 3; |
d38ceaf9 | 649 | if (wb < adev->wb.num_wb) |
73469585 | 650 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
651 | } |
652 | ||
653 | /** | |
2543e28a | 654 | * amdgpu_device_vram_location - try to find VRAM location |
e3ecdffa | 655 | * |
d38ceaf9 AD |
656 | * @adev: amdgpu device structure holding all necessary informations |
657 | * @mc: memory controller structure holding memory informations | |
658 | * @base: base address at which to put VRAM | |
659 | * | |
455a7bc2 | 660 | * Function will try to place VRAM at base address provided |
3d647c8f | 661 | * as parameter. |
d38ceaf9 | 662 | */ |
2543e28a | 663 | void amdgpu_device_vram_location(struct amdgpu_device *adev, |
770d13b1 | 664 | struct amdgpu_gmc *mc, u64 base) |
d38ceaf9 AD |
665 | { |
666 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
667 | ||
668 | mc->vram_start = base; | |
d38ceaf9 AD |
669 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
670 | if (limit && limit < mc->real_vram_size) | |
671 | mc->real_vram_size = limit; | |
672 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
673 | mc->mc_vram_size >> 20, mc->vram_start, | |
674 | mc->vram_end, mc->real_vram_size >> 20); | |
675 | } | |
676 | ||
677 | /** | |
2543e28a | 678 | * amdgpu_device_gart_location - try to find GTT location |
e3ecdffa | 679 | * |
d38ceaf9 AD |
680 | * @adev: amdgpu device structure holding all necessary informations |
681 | * @mc: memory controller structure holding memory informations | |
682 | * | |
683 | * Function will place try to place GTT before or after VRAM. | |
684 | * | |
685 | * If GTT size is bigger than space left then we ajust GTT size. | |
686 | * Thus function will never fails. | |
687 | * | |
688 | * FIXME: when reducing GTT size align new size on power of 2. | |
689 | */ | |
2543e28a | 690 | void amdgpu_device_gart_location(struct amdgpu_device *adev, |
770d13b1 | 691 | struct amdgpu_gmc *mc) |
d38ceaf9 AD |
692 | { |
693 | u64 size_af, size_bf; | |
694 | ||
7951e376 RZ |
695 | mc->gart_size += adev->pm.smu_prv_buffer_size; |
696 | ||
770d13b1 | 697 | size_af = adev->gmc.mc_mask - mc->vram_end; |
ed21c047 | 698 | size_bf = mc->vram_start; |
d38ceaf9 | 699 | if (size_bf > size_af) { |
6f02a696 | 700 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 701 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 702 | mc->gart_size = size_bf; |
d38ceaf9 | 703 | } |
6f02a696 | 704 | mc->gart_start = 0; |
d38ceaf9 | 705 | } else { |
6f02a696 | 706 | if (mc->gart_size > size_af) { |
d38ceaf9 | 707 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 708 | mc->gart_size = size_af; |
d38ceaf9 | 709 | } |
b98f1b9e CK |
710 | /* VCE doesn't like it when BOs cross a 4GB segment, so align |
711 | * the GART base on a 4GB boundary as well. | |
712 | */ | |
713 | mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL); | |
d38ceaf9 | 714 | } |
6f02a696 | 715 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 716 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 717 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
718 | } |
719 | ||
d6895ad3 CK |
720 | /** |
721 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
722 | * | |
723 | * @adev: amdgpu_device pointer | |
724 | * | |
725 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
726 | * to fail, but if any of the BARs is not accessible after the size we abort | |
727 | * driver loading by returning -ENODEV. | |
728 | */ | |
729 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
730 | { | |
770d13b1 | 731 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 732 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
733 | struct pci_bus *root; |
734 | struct resource *res; | |
735 | unsigned i; | |
d6895ad3 CK |
736 | u16 cmd; |
737 | int r; | |
738 | ||
0c03b912 | 739 | /* Bypass for VF */ |
740 | if (amdgpu_sriov_vf(adev)) | |
741 | return 0; | |
742 | ||
31b8adab CK |
743 | /* Check if the root BUS has 64bit memory resources */ |
744 | root = adev->pdev->bus; | |
745 | while (root->parent) | |
746 | root = root->parent; | |
747 | ||
748 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 749 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
750 | res->start > 0x100000000ull) |
751 | break; | |
752 | } | |
753 | ||
754 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
755 | if (!res) | |
756 | return 0; | |
757 | ||
d6895ad3 CK |
758 | /* Disable memory decoding while we change the BAR addresses and size */ |
759 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
760 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
761 | cmd & ~PCI_COMMAND_MEMORY); | |
762 | ||
763 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 764 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
765 | if (adev->asic_type >= CHIP_BONAIRE) |
766 | pci_release_resource(adev->pdev, 2); | |
767 | ||
768 | pci_release_resource(adev->pdev, 0); | |
769 | ||
770 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
771 | if (r == -ENOSPC) | |
772 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
773 | else if (r && r != -ENOTSUPP) | |
774 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
775 | ||
776 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
777 | ||
778 | /* When the doorbell or fb BAR isn't available we have no chance of | |
779 | * using the device. | |
780 | */ | |
06ec9070 | 781 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
782 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
783 | return -ENODEV; | |
784 | ||
785 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
786 | ||
787 | return 0; | |
788 | } | |
a05502e5 | 789 | |
d38ceaf9 AD |
790 | /* |
791 | * GPU helpers function. | |
792 | */ | |
793 | /** | |
39c640c0 | 794 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
795 | * |
796 | * @adev: amdgpu_device pointer | |
797 | * | |
c836fec5 JQ |
798 | * Check if the asic has been initialized (all asics) at driver startup |
799 | * or post is needed if hw reset is performed. | |
800 | * Returns true if need or false if not. | |
d38ceaf9 | 801 | */ |
39c640c0 | 802 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
803 | { |
804 | uint32_t reg; | |
805 | ||
bec86378 ML |
806 | if (amdgpu_sriov_vf(adev)) |
807 | return false; | |
808 | ||
809 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
810 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
811 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
812 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
813 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
814 | */ |
815 | if (adev->asic_type == CHIP_FIJI) { | |
816 | int err; | |
817 | uint32_t fw_ver; | |
818 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
819 | /* force vPost if error occured */ | |
820 | if (err) | |
821 | return true; | |
822 | ||
823 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
824 | if (fw_ver < 0x00160e00) |
825 | return true; | |
bec86378 | 826 | } |
bec86378 | 827 | } |
91fe77eb | 828 | |
829 | if (adev->has_hw_reset) { | |
830 | adev->has_hw_reset = false; | |
831 | return true; | |
832 | } | |
833 | ||
834 | /* bios scratch used on CIK+ */ | |
835 | if (adev->asic_type >= CHIP_BONAIRE) | |
836 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
837 | ||
838 | /* check MEM_SIZE for older asics */ | |
839 | reg = amdgpu_asic_get_config_memsize(adev); | |
840 | ||
841 | if ((reg != 0) && (reg != 0xffffffff)) | |
842 | return false; | |
843 | ||
844 | return true; | |
bec86378 ML |
845 | } |
846 | ||
d38ceaf9 AD |
847 | /* if we get transitioned to only one device, take VGA back */ |
848 | /** | |
06ec9070 | 849 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
850 | * |
851 | * @cookie: amdgpu_device pointer | |
852 | * @state: enable/disable vga decode | |
853 | * | |
854 | * Enable/disable vga decode (all asics). | |
855 | * Returns VGA resource flags. | |
856 | */ | |
06ec9070 | 857 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
858 | { |
859 | struct amdgpu_device *adev = cookie; | |
860 | amdgpu_asic_set_vga_state(adev, state); | |
861 | if (state) | |
862 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
863 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
864 | else | |
865 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
866 | } | |
867 | ||
e3ecdffa AD |
868 | /** |
869 | * amdgpu_device_check_block_size - validate the vm block size | |
870 | * | |
871 | * @adev: amdgpu_device pointer | |
872 | * | |
873 | * Validates the vm block size specified via module parameter. | |
874 | * The vm block size defines number of bits in page table versus page directory, | |
875 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
876 | * page table and the remaining bits are in the page directory. | |
877 | */ | |
06ec9070 | 878 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
879 | { |
880 | /* defines number of bits in page table versus page directory, | |
881 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
882 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
883 | if (amdgpu_vm_block_size == -1) |
884 | return; | |
a1adf8be | 885 | |
bab4fee7 | 886 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
887 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
888 | amdgpu_vm_block_size); | |
97489129 | 889 | amdgpu_vm_block_size = -1; |
a1adf8be | 890 | } |
a1adf8be CZ |
891 | } |
892 | ||
e3ecdffa AD |
893 | /** |
894 | * amdgpu_device_check_vm_size - validate the vm size | |
895 | * | |
896 | * @adev: amdgpu_device pointer | |
897 | * | |
898 | * Validates the vm size in GB specified via module parameter. | |
899 | * The VM size is the size of the GPU virtual memory space in GB. | |
900 | */ | |
06ec9070 | 901 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 902 | { |
64dab074 AD |
903 | /* no need to check the default value */ |
904 | if (amdgpu_vm_size == -1) | |
905 | return; | |
906 | ||
83ca145d ZJ |
907 | if (amdgpu_vm_size < 1) { |
908 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
909 | amdgpu_vm_size); | |
f3368128 | 910 | amdgpu_vm_size = -1; |
83ca145d | 911 | } |
83ca145d ZJ |
912 | } |
913 | ||
7951e376 RZ |
914 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
915 | { | |
916 | struct sysinfo si; | |
917 | bool is_os_64 = (sizeof(void *) == 8) ? true : false; | |
918 | uint64_t total_memory; | |
919 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
920 | uint64_t dram_size_three_GB = 0xB8000000; | |
921 | ||
922 | if (amdgpu_smu_memory_pool_size == 0) | |
923 | return; | |
924 | ||
925 | if (!is_os_64) { | |
926 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
927 | goto def_value; | |
928 | } | |
929 | si_meminfo(&si); | |
930 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
931 | ||
932 | if ((amdgpu_smu_memory_pool_size == 1) || | |
933 | (amdgpu_smu_memory_pool_size == 2)) { | |
934 | if (total_memory < dram_size_three_GB) | |
935 | goto def_value1; | |
936 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
937 | (amdgpu_smu_memory_pool_size == 8)) { | |
938 | if (total_memory < dram_size_seven_GB) | |
939 | goto def_value1; | |
940 | } else { | |
941 | DRM_WARN("Smu memory pool size not supported\n"); | |
942 | goto def_value; | |
943 | } | |
944 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
945 | ||
946 | return; | |
947 | ||
948 | def_value1: | |
949 | DRM_WARN("No enough system memory\n"); | |
950 | def_value: | |
951 | adev->pm.smu_prv_buffer_size = 0; | |
952 | } | |
953 | ||
d38ceaf9 | 954 | /** |
06ec9070 | 955 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
956 | * |
957 | * @adev: amdgpu_device pointer | |
958 | * | |
959 | * Validates certain module parameters and updates | |
960 | * the associated values used by the driver (all asics). | |
961 | */ | |
06ec9070 | 962 | static void amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 963 | { |
5b011235 CZ |
964 | if (amdgpu_sched_jobs < 4) { |
965 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
966 | amdgpu_sched_jobs); | |
967 | amdgpu_sched_jobs = 4; | |
76117507 | 968 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
969 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
970 | amdgpu_sched_jobs); | |
971 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
972 | } | |
d38ceaf9 | 973 | |
83e74db6 | 974 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
975 | /* gart size must be greater or equal to 32M */ |
976 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
977 | amdgpu_gart_size); | |
83e74db6 | 978 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
979 | } |
980 | ||
36d38372 | 981 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 982 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
983 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
984 | amdgpu_gtt_size); | |
985 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
986 | } |
987 | ||
d07f14be RH |
988 | /* valid range is between 4 and 9 inclusive */ |
989 | if (amdgpu_vm_fragment_size != -1 && | |
990 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
991 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
992 | amdgpu_vm_fragment_size = -1; | |
993 | } | |
994 | ||
7951e376 RZ |
995 | amdgpu_device_check_smu_prv_buffer_size(adev); |
996 | ||
06ec9070 | 997 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 998 | |
06ec9070 | 999 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1000 | |
526bae37 | 1001 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1002 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1003 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1004 | amdgpu_vram_page_split); | |
1005 | amdgpu_vram_page_split = 1024; | |
1006 | } | |
8854695a AG |
1007 | |
1008 | if (amdgpu_lockup_timeout == 0) { | |
1009 | dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n"); | |
1010 | amdgpu_lockup_timeout = 10000; | |
1011 | } | |
19aede77 AD |
1012 | |
1013 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); | |
d38ceaf9 AD |
1014 | } |
1015 | ||
1016 | /** | |
1017 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1018 | * | |
1019 | * @pdev: pci dev pointer | |
1694467b | 1020 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1021 | * |
1022 | * Callback for the switcheroo driver. Suspends or resumes the | |
1023 | * the asics before or after it is powered up using ACPI methods. | |
1024 | */ | |
1025 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1026 | { | |
1027 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1028 | ||
1029 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1030 | return; | |
1031 | ||
1032 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1033 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1034 | /* don't suspend or resume card normally */ |
1035 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1036 | ||
810ddc3a | 1037 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1038 | |
d38ceaf9 AD |
1039 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1040 | drm_kms_helper_poll_enable(dev); | |
1041 | } else { | |
7ca85295 | 1042 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1043 | drm_kms_helper_poll_disable(dev); |
1044 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1045 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1046 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1047 | } | |
1048 | } | |
1049 | ||
1050 | /** | |
1051 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1052 | * | |
1053 | * @pdev: pci dev pointer | |
1054 | * | |
1055 | * Callback for the switcheroo driver. Check of the switcheroo | |
1056 | * state can be changed. | |
1057 | * Returns true if the state can be changed, false if not. | |
1058 | */ | |
1059 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1060 | { | |
1061 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1062 | ||
1063 | /* | |
1064 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1065 | * locking inversion with the driver load path. And the access here is | |
1066 | * completely racy anyway. So don't bother with locking for now. | |
1067 | */ | |
1068 | return dev->open_count == 0; | |
1069 | } | |
1070 | ||
1071 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1072 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1073 | .reprobe = NULL, | |
1074 | .can_switch = amdgpu_switcheroo_can_switch, | |
1075 | }; | |
1076 | ||
e3ecdffa AD |
1077 | /** |
1078 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1079 | * | |
1080 | * @adev: amdgpu_device pointer | |
1081 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1082 | * @state: clockgating state (gate or ungate) | |
1083 | * | |
1084 | * Sets the requested clockgating state for all instances of | |
1085 | * the hardware IP specified. | |
1086 | * Returns the error code from the last instance. | |
1087 | */ | |
43fa561f | 1088 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1089 | enum amd_ip_block_type block_type, |
1090 | enum amd_clockgating_state state) | |
d38ceaf9 | 1091 | { |
43fa561f | 1092 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1093 | int i, r = 0; |
1094 | ||
1095 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1096 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1097 | continue; |
c722865a RZ |
1098 | if (adev->ip_blocks[i].version->type != block_type) |
1099 | continue; | |
1100 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1101 | continue; | |
1102 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1103 | (void *)adev, state); | |
1104 | if (r) | |
1105 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1106 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1107 | } |
1108 | return r; | |
1109 | } | |
1110 | ||
e3ecdffa AD |
1111 | /** |
1112 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1113 | * | |
1114 | * @adev: amdgpu_device pointer | |
1115 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1116 | * @state: powergating state (gate or ungate) | |
1117 | * | |
1118 | * Sets the requested powergating state for all instances of | |
1119 | * the hardware IP specified. | |
1120 | * Returns the error code from the last instance. | |
1121 | */ | |
43fa561f | 1122 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1123 | enum amd_ip_block_type block_type, |
1124 | enum amd_powergating_state state) | |
d38ceaf9 | 1125 | { |
43fa561f | 1126 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1127 | int i, r = 0; |
1128 | ||
1129 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1130 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1131 | continue; |
c722865a RZ |
1132 | if (adev->ip_blocks[i].version->type != block_type) |
1133 | continue; | |
1134 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1135 | continue; | |
1136 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1137 | (void *)adev, state); | |
1138 | if (r) | |
1139 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1140 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1141 | } |
1142 | return r; | |
1143 | } | |
1144 | ||
e3ecdffa AD |
1145 | /** |
1146 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1147 | * | |
1148 | * @adev: amdgpu_device pointer | |
1149 | * @flags: clockgating feature flags | |
1150 | * | |
1151 | * Walks the list of IPs on the device and updates the clockgating | |
1152 | * flags for each IP. | |
1153 | * Updates @flags with the feature flags for each hardware IP where | |
1154 | * clockgating is enabled. | |
1155 | */ | |
2990a1fc AD |
1156 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1157 | u32 *flags) | |
6cb2d4e4 HR |
1158 | { |
1159 | int i; | |
1160 | ||
1161 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1162 | if (!adev->ip_blocks[i].status.valid) | |
1163 | continue; | |
1164 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1165 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1166 | } | |
1167 | } | |
1168 | ||
e3ecdffa AD |
1169 | /** |
1170 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1171 | * | |
1172 | * @adev: amdgpu_device pointer | |
1173 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1174 | * | |
1175 | * Waits for the request hardware IP to be idle. | |
1176 | * Returns 0 for success or a negative error code on failure. | |
1177 | */ | |
2990a1fc AD |
1178 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1179 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1180 | { |
1181 | int i, r; | |
1182 | ||
1183 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1184 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1185 | continue; |
a1255107 AD |
1186 | if (adev->ip_blocks[i].version->type == block_type) { |
1187 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1188 | if (r) |
1189 | return r; | |
1190 | break; | |
1191 | } | |
1192 | } | |
1193 | return 0; | |
1194 | ||
1195 | } | |
1196 | ||
e3ecdffa AD |
1197 | /** |
1198 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1199 | * | |
1200 | * @adev: amdgpu_device pointer | |
1201 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1202 | * | |
1203 | * Check if the hardware IP is idle or not. | |
1204 | * Returns true if it the IP is idle, false if not. | |
1205 | */ | |
2990a1fc AD |
1206 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1207 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1208 | { |
1209 | int i; | |
1210 | ||
1211 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1212 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1213 | continue; |
a1255107 AD |
1214 | if (adev->ip_blocks[i].version->type == block_type) |
1215 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1216 | } |
1217 | return true; | |
1218 | ||
1219 | } | |
1220 | ||
e3ecdffa AD |
1221 | /** |
1222 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1223 | * | |
1224 | * @adev: amdgpu_device pointer | |
1225 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1226 | * | |
1227 | * Returns a pointer to the hardware IP block structure | |
1228 | * if it exists for the asic, otherwise NULL. | |
1229 | */ | |
2990a1fc AD |
1230 | struct amdgpu_ip_block * |
1231 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1232 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1233 | { |
1234 | int i; | |
1235 | ||
1236 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1237 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1238 | return &adev->ip_blocks[i]; |
1239 | ||
1240 | return NULL; | |
1241 | } | |
1242 | ||
1243 | /** | |
2990a1fc | 1244 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1245 | * |
1246 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1247 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1248 | * @major: major version |
1249 | * @minor: minor version | |
1250 | * | |
1251 | * return 0 if equal or greater | |
1252 | * return 1 if smaller or the ip_block doesn't exist | |
1253 | */ | |
2990a1fc AD |
1254 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1255 | enum amd_ip_block_type type, | |
1256 | u32 major, u32 minor) | |
d38ceaf9 | 1257 | { |
2990a1fc | 1258 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1259 | |
a1255107 AD |
1260 | if (ip_block && ((ip_block->version->major > major) || |
1261 | ((ip_block->version->major == major) && | |
1262 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1263 | return 0; |
1264 | ||
1265 | return 1; | |
1266 | } | |
1267 | ||
a1255107 | 1268 | /** |
2990a1fc | 1269 | * amdgpu_device_ip_block_add |
a1255107 AD |
1270 | * |
1271 | * @adev: amdgpu_device pointer | |
1272 | * @ip_block_version: pointer to the IP to add | |
1273 | * | |
1274 | * Adds the IP block driver information to the collection of IPs | |
1275 | * on the asic. | |
1276 | */ | |
2990a1fc AD |
1277 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1278 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1279 | { |
1280 | if (!ip_block_version) | |
1281 | return -EINVAL; | |
1282 | ||
e966a725 | 1283 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1284 | ip_block_version->funcs->name); |
1285 | ||
a1255107 AD |
1286 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
e3ecdffa AD |
1291 | /** |
1292 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1293 | * | |
1294 | * @adev: amdgpu_device pointer | |
1295 | * | |
1296 | * Enabled the virtual display feature if the user has enabled it via | |
1297 | * the module parameter virtual_display. This feature provides a virtual | |
1298 | * display hardware on headless boards or in virtualized environments. | |
1299 | * This function parses and validates the configuration string specified by | |
1300 | * the user and configues the virtual display configuration (number of | |
1301 | * virtual connectors, crtcs, etc.) specified. | |
1302 | */ | |
483ef985 | 1303 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1304 | { |
1305 | adev->enable_virtual_display = false; | |
1306 | ||
1307 | if (amdgpu_virtual_display) { | |
1308 | struct drm_device *ddev = adev->ddev; | |
1309 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1310 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1311 | |
1312 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1313 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1314 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1315 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1316 | if (!strcmp("all", pciaddname) |
1317 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1318 | long num_crtc; |
1319 | int res = -1; | |
1320 | ||
9accf2fd | 1321 | adev->enable_virtual_display = true; |
0f66356d ED |
1322 | |
1323 | if (pciaddname_tmp) | |
1324 | res = kstrtol(pciaddname_tmp, 10, | |
1325 | &num_crtc); | |
1326 | ||
1327 | if (!res) { | |
1328 | if (num_crtc < 1) | |
1329 | num_crtc = 1; | |
1330 | if (num_crtc > 6) | |
1331 | num_crtc = 6; | |
1332 | adev->mode_info.num_crtc = num_crtc; | |
1333 | } else { | |
1334 | adev->mode_info.num_crtc = 1; | |
1335 | } | |
9accf2fd ED |
1336 | break; |
1337 | } | |
1338 | } | |
1339 | ||
0f66356d ED |
1340 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1341 | amdgpu_virtual_display, pci_address_name, | |
1342 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1343 | |
1344 | kfree(pciaddstr); | |
1345 | } | |
1346 | } | |
1347 | ||
e3ecdffa AD |
1348 | /** |
1349 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1350 | * | |
1351 | * @adev: amdgpu_device pointer | |
1352 | * | |
1353 | * Parses the asic configuration parameters specified in the gpu info | |
1354 | * firmware and makes them availale to the driver for use in configuring | |
1355 | * the asic. | |
1356 | * Returns 0 on success, -EINVAL on failure. | |
1357 | */ | |
e2a75f88 AD |
1358 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1359 | { | |
e2a75f88 AD |
1360 | const char *chip_name; |
1361 | char fw_name[30]; | |
1362 | int err; | |
1363 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1364 | ||
ab4fe3e1 HR |
1365 | adev->firmware.gpu_info_fw = NULL; |
1366 | ||
e2a75f88 AD |
1367 | switch (adev->asic_type) { |
1368 | case CHIP_TOPAZ: | |
1369 | case CHIP_TONGA: | |
1370 | case CHIP_FIJI: | |
e2a75f88 | 1371 | case CHIP_POLARIS10: |
cc07f18d | 1372 | case CHIP_POLARIS11: |
e2a75f88 | 1373 | case CHIP_POLARIS12: |
cc07f18d | 1374 | case CHIP_VEGAM: |
e2a75f88 AD |
1375 | case CHIP_CARRIZO: |
1376 | case CHIP_STONEY: | |
1377 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1378 | case CHIP_VERDE: | |
1379 | case CHIP_TAHITI: | |
1380 | case CHIP_PITCAIRN: | |
1381 | case CHIP_OLAND: | |
1382 | case CHIP_HAINAN: | |
1383 | #endif | |
1384 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1385 | case CHIP_BONAIRE: | |
1386 | case CHIP_HAWAII: | |
1387 | case CHIP_KAVERI: | |
1388 | case CHIP_KABINI: | |
1389 | case CHIP_MULLINS: | |
1390 | #endif | |
27c0bc71 | 1391 | case CHIP_VEGA20: |
e2a75f88 AD |
1392 | default: |
1393 | return 0; | |
1394 | case CHIP_VEGA10: | |
1395 | chip_name = "vega10"; | |
1396 | break; | |
3f76dced AD |
1397 | case CHIP_VEGA12: |
1398 | chip_name = "vega12"; | |
1399 | break; | |
2d2e5e7e AD |
1400 | case CHIP_RAVEN: |
1401 | chip_name = "raven"; | |
1402 | break; | |
e2a75f88 AD |
1403 | } |
1404 | ||
1405 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1406 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1407 | if (err) { |
1408 | dev_err(adev->dev, | |
1409 | "Failed to load gpu_info firmware \"%s\"\n", | |
1410 | fw_name); | |
1411 | goto out; | |
1412 | } | |
ab4fe3e1 | 1413 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1414 | if (err) { |
1415 | dev_err(adev->dev, | |
1416 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1417 | fw_name); | |
1418 | goto out; | |
1419 | } | |
1420 | ||
ab4fe3e1 | 1421 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1422 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1423 | ||
1424 | switch (hdr->version_major) { | |
1425 | case 1: | |
1426 | { | |
1427 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1428 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1429 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1430 | ||
b5ab16bf AD |
1431 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1432 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1433 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1434 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1435 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1436 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1437 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1438 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1439 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1440 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1441 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1442 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1443 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1444 | adev->gfx.cu_info.max_waves_per_simd = |
1445 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1446 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1447 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1448 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1449 | break; |
1450 | } | |
1451 | default: | |
1452 | dev_err(adev->dev, | |
1453 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1454 | err = -EINVAL; | |
1455 | goto out; | |
1456 | } | |
1457 | out: | |
e2a75f88 AD |
1458 | return err; |
1459 | } | |
1460 | ||
e3ecdffa AD |
1461 | /** |
1462 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1463 | * | |
1464 | * @adev: amdgpu_device pointer | |
1465 | * | |
1466 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1467 | * up each asic are discovered each IP's early_init callback is run. This | |
1468 | * is the first stage in initializing the asic. | |
1469 | * Returns 0 on success, negative error code on failure. | |
1470 | */ | |
06ec9070 | 1471 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1472 | { |
aaa36a97 | 1473 | int i, r; |
d38ceaf9 | 1474 | |
483ef985 | 1475 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1476 | |
d38ceaf9 | 1477 | switch (adev->asic_type) { |
aaa36a97 AD |
1478 | case CHIP_TOPAZ: |
1479 | case CHIP_TONGA: | |
48299f95 | 1480 | case CHIP_FIJI: |
2cc0c0b5 | 1481 | case CHIP_POLARIS10: |
32cc7e53 | 1482 | case CHIP_POLARIS11: |
c4642a47 | 1483 | case CHIP_POLARIS12: |
32cc7e53 | 1484 | case CHIP_VEGAM: |
aaa36a97 | 1485 | case CHIP_CARRIZO: |
39bb0c92 SL |
1486 | case CHIP_STONEY: |
1487 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1488 | adev->family = AMDGPU_FAMILY_CZ; |
1489 | else | |
1490 | adev->family = AMDGPU_FAMILY_VI; | |
1491 | ||
1492 | r = vi_set_ip_blocks(adev); | |
1493 | if (r) | |
1494 | return r; | |
1495 | break; | |
33f34802 KW |
1496 | #ifdef CONFIG_DRM_AMDGPU_SI |
1497 | case CHIP_VERDE: | |
1498 | case CHIP_TAHITI: | |
1499 | case CHIP_PITCAIRN: | |
1500 | case CHIP_OLAND: | |
1501 | case CHIP_HAINAN: | |
295d0daf | 1502 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1503 | r = si_set_ip_blocks(adev); |
1504 | if (r) | |
1505 | return r; | |
1506 | break; | |
1507 | #endif | |
a2e73f56 AD |
1508 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1509 | case CHIP_BONAIRE: | |
1510 | case CHIP_HAWAII: | |
1511 | case CHIP_KAVERI: | |
1512 | case CHIP_KABINI: | |
1513 | case CHIP_MULLINS: | |
1514 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1515 | adev->family = AMDGPU_FAMILY_CI; | |
1516 | else | |
1517 | adev->family = AMDGPU_FAMILY_KV; | |
1518 | ||
1519 | r = cik_set_ip_blocks(adev); | |
1520 | if (r) | |
1521 | return r; | |
1522 | break; | |
1523 | #endif | |
e48a3cd9 AD |
1524 | case CHIP_VEGA10: |
1525 | case CHIP_VEGA12: | |
e4bd8170 | 1526 | case CHIP_VEGA20: |
e48a3cd9 | 1527 | case CHIP_RAVEN: |
2ca8a5d2 CZ |
1528 | if (adev->asic_type == CHIP_RAVEN) |
1529 | adev->family = AMDGPU_FAMILY_RV; | |
1530 | else | |
1531 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1532 | |
1533 | r = soc15_set_ip_blocks(adev); | |
1534 | if (r) | |
1535 | return r; | |
1536 | break; | |
d38ceaf9 AD |
1537 | default: |
1538 | /* FIXME: not supported yet */ | |
1539 | return -EINVAL; | |
1540 | } | |
1541 | ||
e2a75f88 AD |
1542 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1543 | if (r) | |
1544 | return r; | |
1545 | ||
1884734a | 1546 | amdgpu_amdkfd_device_probe(adev); |
1547 | ||
3149d9da XY |
1548 | if (amdgpu_sriov_vf(adev)) { |
1549 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1550 | if (r) | |
5ffa61c1 | 1551 | return -EAGAIN; |
3149d9da XY |
1552 | } |
1553 | ||
00f54b97 HR |
1554 | adev->powerplay.pp_feature = amdgpu_pp_feature_mask; |
1555 | ||
d38ceaf9 AD |
1556 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1557 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1558 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1559 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1560 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1561 | } else { |
a1255107 AD |
1562 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1563 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1564 | if (r == -ENOENT) { |
a1255107 | 1565 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1566 | } else if (r) { |
a1255107 AD |
1567 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1568 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1569 | return r; |
2c1a2784 | 1570 | } else { |
a1255107 | 1571 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1572 | } |
974e6b64 | 1573 | } else { |
a1255107 | 1574 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1575 | } |
d38ceaf9 AD |
1576 | } |
1577 | } | |
1578 | ||
395d1fb9 NH |
1579 | adev->cg_flags &= amdgpu_cg_mask; |
1580 | adev->pg_flags &= amdgpu_pg_mask; | |
1581 | ||
d38ceaf9 AD |
1582 | return 0; |
1583 | } | |
1584 | ||
e3ecdffa AD |
1585 | /** |
1586 | * amdgpu_device_ip_init - run init for hardware IPs | |
1587 | * | |
1588 | * @adev: amdgpu_device pointer | |
1589 | * | |
1590 | * Main initialization pass for hardware IPs. The list of all the hardware | |
1591 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
1592 | * are run. sw_init initializes the software state associated with each IP | |
1593 | * and hw_init initializes the hardware associated with each IP. | |
1594 | * Returns 0 on success, negative error code on failure. | |
1595 | */ | |
06ec9070 | 1596 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1597 | { |
1598 | int i, r; | |
1599 | ||
1600 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1601 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1602 | continue; |
a1255107 | 1603 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1604 | if (r) { |
a1255107 AD |
1605 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1606 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1607 | return r; |
2c1a2784 | 1608 | } |
a1255107 | 1609 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 1610 | |
d38ceaf9 | 1611 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1612 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 1613 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
1614 | if (r) { |
1615 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1616 | return r; |
2c1a2784 | 1617 | } |
a1255107 | 1618 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1619 | if (r) { |
1620 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1621 | return r; |
2c1a2784 | 1622 | } |
06ec9070 | 1623 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 1624 | if (r) { |
06ec9070 | 1625 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
d38ceaf9 | 1626 | return r; |
2c1a2784 | 1627 | } |
a1255107 | 1628 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1629 | |
1630 | /* right after GMC hw init, we create CSA */ | |
1631 | if (amdgpu_sriov_vf(adev)) { | |
1632 | r = amdgpu_allocate_static_csa(adev); | |
1633 | if (r) { | |
1634 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1635 | return r; | |
1636 | } | |
1637 | } | |
d38ceaf9 AD |
1638 | } |
1639 | } | |
1640 | ||
1641 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1642 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1643 | continue; |
bfca0289 | 1644 | if (adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1645 | continue; |
a1255107 | 1646 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1647 | if (r) { |
a1255107 AD |
1648 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1649 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1650 | return r; |
2c1a2784 | 1651 | } |
a1255107 | 1652 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1653 | } |
1654 | ||
1884734a | 1655 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1656 | |
1657 | if (amdgpu_sriov_vf(adev)) | |
1658 | amdgpu_virt_release_full_gpu(adev, true); | |
1659 | ||
d38ceaf9 AD |
1660 | return 0; |
1661 | } | |
1662 | ||
e3ecdffa AD |
1663 | /** |
1664 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
1665 | * | |
1666 | * @adev: amdgpu_device pointer | |
1667 | * | |
1668 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
1669 | * this function before a GPU reset. If the value is retained after a | |
1670 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
1671 | */ | |
06ec9070 | 1672 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1673 | { |
1674 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1675 | } | |
1676 | ||
e3ecdffa AD |
1677 | /** |
1678 | * amdgpu_device_check_vram_lost - check if vram is valid | |
1679 | * | |
1680 | * @adev: amdgpu_device pointer | |
1681 | * | |
1682 | * Checks the reset magic value written to the gart pointer in VRAM. | |
1683 | * The driver calls this after a GPU reset to see if the contents of | |
1684 | * VRAM is lost or now. | |
1685 | * returns true if vram is lost, false if not. | |
1686 | */ | |
06ec9070 | 1687 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1688 | { |
1689 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1690 | AMDGPU_RESET_MAGIC_NUM); | |
1691 | } | |
1692 | ||
e3ecdffa AD |
1693 | /** |
1694 | * amdgpu_device_ip_late_set_cg_state - late init for clockgating | |
1695 | * | |
1696 | * @adev: amdgpu_device pointer | |
1697 | * | |
1698 | * Late initialization pass enabling clockgating for hardware IPs. | |
1699 | * The list of all the hardware IPs that make up the asic is walked and the | |
1700 | * set_clockgating_state callbacks are run. This stage is run late | |
1701 | * in the init process. | |
1702 | * Returns 0 on success, negative error code on failure. | |
1703 | */ | |
06ec9070 | 1704 | static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1705 | { |
1706 | int i = 0, r; | |
1707 | ||
4a2ba394 SL |
1708 | if (amdgpu_emu_mode == 1) |
1709 | return 0; | |
1710 | ||
2c773de2 S |
1711 | r = amdgpu_ib_ring_tests(adev); |
1712 | if (r) | |
1713 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1714 | ||
d38ceaf9 | 1715 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 1716 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1717 | continue; |
4a446d55 | 1718 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 1719 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 1720 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 1721 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
57716327 | 1722 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 1723 | /* enable clockgating to save power */ |
a1255107 AD |
1724 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1725 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1726 | if (r) { |
1727 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1728 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1729 | return r; |
1730 | } | |
b0b00ff1 | 1731 | } |
d38ceaf9 | 1732 | } |
06b18f61 HR |
1733 | |
1734 | if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) { | |
1735 | /* enable gfx powergating */ | |
1736 | amdgpu_device_ip_set_powergating_state(adev, | |
1737 | AMD_IP_BLOCK_TYPE_GFX, | |
1738 | AMD_PG_STATE_GATE); | |
1739 | /* enable gfxoff */ | |
1740 | amdgpu_device_ip_set_powergating_state(adev, | |
1741 | AMD_IP_BLOCK_TYPE_SMC, | |
1742 | AMD_PG_STATE_GATE); | |
1743 | } | |
1744 | ||
2dc80b00 S |
1745 | return 0; |
1746 | } | |
1747 | ||
e3ecdffa AD |
1748 | /** |
1749 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
1750 | * | |
1751 | * @adev: amdgpu_device pointer | |
1752 | * | |
1753 | * Late initialization pass for hardware IPs. The list of all the hardware | |
1754 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
1755 | * late_init covers any special initialization that an IP requires | |
1756 | * after all of the have been initialized or something that needs to happen | |
1757 | * late in the init process. | |
1758 | * Returns 0 on success, negative error code on failure. | |
1759 | */ | |
06ec9070 | 1760 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 S |
1761 | { |
1762 | int i = 0, r; | |
1763 | ||
1764 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1765 | if (!adev->ip_blocks[i].status.valid) | |
1766 | continue; | |
1767 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1768 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1769 | if (r) { | |
1770 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1771 | adev->ip_blocks[i].version->funcs->name, r); | |
1772 | return r; | |
1773 | } | |
1774 | adev->ip_blocks[i].status.late_initialized = true; | |
1775 | } | |
1776 | } | |
1777 | ||
2c773de2 S |
1778 | queue_delayed_work(system_wq, &adev->late_init_work, |
1779 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1780 | |
06ec9070 | 1781 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 AD |
1782 | |
1783 | return 0; | |
1784 | } | |
1785 | ||
e3ecdffa AD |
1786 | /** |
1787 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
1788 | * | |
1789 | * @adev: amdgpu_device pointer | |
1790 | * | |
1791 | * Main teardown pass for hardware IPs. The list of all the hardware | |
1792 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
1793 | * are run. hw_fini tears down the hardware associated with each IP | |
1794 | * and sw_fini tears down any software state associated with each IP. | |
1795 | * Returns 0 on success, negative error code on failure. | |
1796 | */ | |
06ec9070 | 1797 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1798 | { |
1799 | int i, r; | |
1800 | ||
1884734a | 1801 | amdgpu_amdkfd_device_fini(adev); |
3e96dbfd AD |
1802 | /* need to disable SMC first */ |
1803 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1804 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1805 | continue; |
57716327 RZ |
1806 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC && |
1807 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { | |
3e96dbfd | 1808 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1809 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1810 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1811 | if (r) { |
1812 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1813 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1814 | return r; |
1815 | } | |
a1255107 | 1816 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1817 | /* XXX handle errors */ |
1818 | if (r) { | |
1819 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1820 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1821 | } |
a1255107 | 1822 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1823 | break; |
1824 | } | |
1825 | } | |
1826 | ||
d38ceaf9 | 1827 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1828 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1829 | continue; |
8201a67a RZ |
1830 | |
1831 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
81ce8bea | 1832 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 1833 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
81ce8bea | 1834 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
8201a67a RZ |
1835 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
1836 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1837 | AMD_CG_STATE_UNGATE); | |
1838 | if (r) { | |
1839 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1840 | adev->ip_blocks[i].version->funcs->name, r); | |
1841 | return r; | |
1842 | } | |
2c1a2784 | 1843 | } |
8201a67a | 1844 | |
a1255107 | 1845 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1846 | /* XXX handle errors */ |
2c1a2784 | 1847 | if (r) { |
a1255107 AD |
1848 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1849 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1850 | } |
8201a67a | 1851 | |
a1255107 | 1852 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1853 | } |
1854 | ||
9950cda2 | 1855 | |
d38ceaf9 | 1856 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1857 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1858 | continue; |
c12aba3a ML |
1859 | |
1860 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
1861 | amdgpu_free_static_csa(adev); | |
1862 | amdgpu_device_wb_fini(adev); | |
1863 | amdgpu_device_vram_scratch_fini(adev); | |
1864 | } | |
1865 | ||
a1255107 | 1866 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1867 | /* XXX handle errors */ |
2c1a2784 | 1868 | if (r) { |
a1255107 AD |
1869 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1870 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1871 | } |
a1255107 AD |
1872 | adev->ip_blocks[i].status.sw = false; |
1873 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1874 | } |
1875 | ||
a6dcfd9c | 1876 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1877 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1878 | continue; |
a1255107 AD |
1879 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1880 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1881 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1882 | } |
1883 | ||
030308fc | 1884 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
1885 | if (amdgpu_virt_release_full_gpu(adev, false)) |
1886 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 1887 | |
d38ceaf9 AD |
1888 | return 0; |
1889 | } | |
1890 | ||
e3ecdffa AD |
1891 | /** |
1892 | * amdgpu_device_ip_late_init_func_handler - work handler for clockgating | |
1893 | * | |
1894 | * @work: work_struct | |
1895 | * | |
1896 | * Work handler for amdgpu_device_ip_late_set_cg_state. We put the | |
1897 | * clockgating setup into a worker thread to speed up driver init and | |
1898 | * resume from suspend. | |
1899 | */ | |
06ec9070 | 1900 | static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) |
2dc80b00 S |
1901 | { |
1902 | struct amdgpu_device *adev = | |
1903 | container_of(work, struct amdgpu_device, late_init_work.work); | |
06ec9070 | 1904 | amdgpu_device_ip_late_set_cg_state(adev); |
2dc80b00 S |
1905 | } |
1906 | ||
e3ecdffa AD |
1907 | /** |
1908 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
1909 | * | |
1910 | * @adev: amdgpu_device pointer | |
1911 | * | |
1912 | * Main suspend function for hardware IPs. The list of all the hardware | |
1913 | * IPs that make up the asic is walked, clockgating is disabled and the | |
1914 | * suspend callbacks are run. suspend puts the hardware and software state | |
1915 | * in each IP into a state suitable for suspend. | |
1916 | * Returns 0 on success, negative error code on failure. | |
1917 | */ | |
cdd61df6 | 1918 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1919 | { |
1920 | int i, r; | |
1921 | ||
e941ea99 XY |
1922 | if (amdgpu_sriov_vf(adev)) |
1923 | amdgpu_virt_request_full_gpu(adev, false); | |
1924 | ||
b0833696 HR |
1925 | /* ungate SMC block powergating */ |
1926 | if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) | |
1927 | amdgpu_device_ip_set_powergating_state(adev, | |
1928 | AMD_IP_BLOCK_TYPE_SMC, | |
1929 | AMD_CG_STATE_UNGATE); | |
1930 | ||
c5a93a28 | 1931 | /* ungate SMC block first */ |
2990a1fc AD |
1932 | r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, |
1933 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1934 | if (r) { |
2990a1fc | 1935 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r); |
c5a93a28 FC |
1936 | } |
1937 | ||
d38ceaf9 | 1938 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1939 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1940 | continue; |
1941 | /* ungate blocks so that suspend can properly shut them down */ | |
5b2a3d2c | 1942 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_SMC && |
57716327 | 1943 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
a1255107 AD |
1944 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1945 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1946 | if (r) { |
a1255107 AD |
1947 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1948 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1949 | } |
2c1a2784 | 1950 | } |
d38ceaf9 | 1951 | /* XXX handle errors */ |
a1255107 | 1952 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1953 | /* XXX handle errors */ |
2c1a2784 | 1954 | if (r) { |
a1255107 AD |
1955 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1956 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1957 | } |
d38ceaf9 AD |
1958 | } |
1959 | ||
e941ea99 XY |
1960 | if (amdgpu_sriov_vf(adev)) |
1961 | amdgpu_virt_release_full_gpu(adev, false); | |
1962 | ||
d38ceaf9 AD |
1963 | return 0; |
1964 | } | |
1965 | ||
06ec9070 | 1966 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1967 | { |
1968 | int i, r; | |
1969 | ||
2cb681b6 ML |
1970 | static enum amd_ip_block_type ip_order[] = { |
1971 | AMD_IP_BLOCK_TYPE_GMC, | |
1972 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1973 | AMD_IP_BLOCK_TYPE_IH, |
1974 | }; | |
a90ad3c2 | 1975 | |
2cb681b6 ML |
1976 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1977 | int j; | |
1978 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1979 | |
2cb681b6 ML |
1980 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1981 | block = &adev->ip_blocks[j]; | |
1982 | ||
1983 | if (block->version->type != ip_order[i] || | |
1984 | !block->status.valid) | |
1985 | continue; | |
1986 | ||
1987 | r = block->version->funcs->hw_init(adev); | |
1988 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
c41d1cf6 ML |
1989 | if (r) |
1990 | return r; | |
a90ad3c2 ML |
1991 | } |
1992 | } | |
1993 | ||
1994 | return 0; | |
1995 | } | |
1996 | ||
06ec9070 | 1997 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1998 | { |
1999 | int i, r; | |
2000 | ||
2cb681b6 ML |
2001 | static enum amd_ip_block_type ip_order[] = { |
2002 | AMD_IP_BLOCK_TYPE_SMC, | |
ef4c166d | 2003 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2004 | AMD_IP_BLOCK_TYPE_DCE, |
2005 | AMD_IP_BLOCK_TYPE_GFX, | |
2006 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
2007 | AMD_IP_BLOCK_TYPE_UVD, |
2008 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 2009 | }; |
a90ad3c2 | 2010 | |
2cb681b6 ML |
2011 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2012 | int j; | |
2013 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2014 | |
2cb681b6 ML |
2015 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2016 | block = &adev->ip_blocks[j]; | |
2017 | ||
2018 | if (block->version->type != ip_order[i] || | |
2019 | !block->status.valid) | |
2020 | continue; | |
2021 | ||
2022 | r = block->version->funcs->hw_init(adev); | |
2023 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
c41d1cf6 ML |
2024 | if (r) |
2025 | return r; | |
a90ad3c2 ML |
2026 | } |
2027 | } | |
2028 | ||
2029 | return 0; | |
2030 | } | |
2031 | ||
e3ecdffa AD |
2032 | /** |
2033 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2034 | * | |
2035 | * @adev: amdgpu_device pointer | |
2036 | * | |
2037 | * First resume function for hardware IPs. The list of all the hardware | |
2038 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2039 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2040 | * after a suspend and updates the software state as necessary. This | |
2041 | * function is also used for restoring the GPU after a GPU reset. | |
2042 | * Returns 0 on success, negative error code on failure. | |
2043 | */ | |
06ec9070 | 2044 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2045 | { |
2046 | int i, r; | |
2047 | ||
a90ad3c2 ML |
2048 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2049 | if (!adev->ip_blocks[i].status.valid) | |
2050 | continue; | |
a90ad3c2 | 2051 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2052 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2053 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
fcf0649f CZ |
2054 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2055 | if (r) { | |
2056 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2057 | adev->ip_blocks[i].version->funcs->name, r); | |
2058 | return r; | |
2059 | } | |
a90ad3c2 ML |
2060 | } |
2061 | } | |
2062 | ||
2063 | return 0; | |
2064 | } | |
2065 | ||
e3ecdffa AD |
2066 | /** |
2067 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2068 | * | |
2069 | * @adev: amdgpu_device pointer | |
2070 | * | |
2071 | * First resume function for hardware IPs. The list of all the hardware | |
2072 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2073 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2074 | * functional state after a suspend and updates the software state as | |
2075 | * necessary. This function is also used for restoring the GPU after a GPU | |
2076 | * reset. | |
2077 | * Returns 0 on success, negative error code on failure. | |
2078 | */ | |
06ec9070 | 2079 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2080 | { |
2081 | int i, r; | |
2082 | ||
2083 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2084 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2085 | continue; |
fcf0649f | 2086 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2087 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2088 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) | |
fcf0649f | 2089 | continue; |
a1255107 | 2090 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2091 | if (r) { |
a1255107 AD |
2092 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2093 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2094 | return r; |
2c1a2784 | 2095 | } |
d38ceaf9 AD |
2096 | } |
2097 | ||
2098 | return 0; | |
2099 | } | |
2100 | ||
e3ecdffa AD |
2101 | /** |
2102 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2103 | * | |
2104 | * @adev: amdgpu_device pointer | |
2105 | * | |
2106 | * Main resume function for hardware IPs. The hardware IPs | |
2107 | * are split into two resume functions because they are | |
2108 | * are also used in in recovering from a GPU reset and some additional | |
2109 | * steps need to be take between them. In this case (S3/S4) they are | |
2110 | * run sequentially. | |
2111 | * Returns 0 on success, negative error code on failure. | |
2112 | */ | |
06ec9070 | 2113 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2114 | { |
2115 | int r; | |
2116 | ||
06ec9070 | 2117 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2118 | if (r) |
2119 | return r; | |
06ec9070 | 2120 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2121 | |
2122 | return r; | |
2123 | } | |
2124 | ||
e3ecdffa AD |
2125 | /** |
2126 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2127 | * | |
2128 | * @adev: amdgpu_device pointer | |
2129 | * | |
2130 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2131 | */ | |
4e99a44e | 2132 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2133 | { |
6867e1b5 ML |
2134 | if (amdgpu_sriov_vf(adev)) { |
2135 | if (adev->is_atom_fw) { | |
2136 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2137 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2138 | } else { | |
2139 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2140 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2141 | } | |
2142 | ||
2143 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2144 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2145 | } |
048765ad AR |
2146 | } |
2147 | ||
e3ecdffa AD |
2148 | /** |
2149 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2150 | * | |
2151 | * @asic_type: AMD asic type | |
2152 | * | |
2153 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2154 | * returns true if DC has support, false if not. | |
2155 | */ | |
4562236b HW |
2156 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2157 | { | |
2158 | switch (asic_type) { | |
2159 | #if defined(CONFIG_DRM_AMD_DC) | |
2160 | case CHIP_BONAIRE: | |
0d6fbccb | 2161 | case CHIP_KAVERI: |
367e6687 AD |
2162 | case CHIP_KABINI: |
2163 | case CHIP_MULLINS: | |
d9fda248 HW |
2164 | /* |
2165 | * We have systems in the wild with these ASICs that require | |
2166 | * LVDS and VGA support which is not supported with DC. | |
2167 | * | |
2168 | * Fallback to the non-DC driver here by default so as not to | |
2169 | * cause regressions. | |
2170 | */ | |
2171 | return amdgpu_dc > 0; | |
2172 | case CHIP_HAWAII: | |
4562236b HW |
2173 | case CHIP_CARRIZO: |
2174 | case CHIP_STONEY: | |
4562236b | 2175 | case CHIP_POLARIS10: |
675fd32b | 2176 | case CHIP_POLARIS11: |
2c8ad2d5 | 2177 | case CHIP_POLARIS12: |
675fd32b | 2178 | case CHIP_VEGAM: |
4562236b HW |
2179 | case CHIP_TONGA: |
2180 | case CHIP_FIJI: | |
42f8ffa1 | 2181 | case CHIP_VEGA10: |
dca7b401 | 2182 | case CHIP_VEGA12: |
c6034aa2 | 2183 | case CHIP_VEGA20: |
42f8ffa1 | 2184 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
fd187853 | 2185 | case CHIP_RAVEN: |
42f8ffa1 | 2186 | #endif |
fd187853 | 2187 | return amdgpu_dc != 0; |
4562236b HW |
2188 | #endif |
2189 | default: | |
2190 | return false; | |
2191 | } | |
2192 | } | |
2193 | ||
2194 | /** | |
2195 | * amdgpu_device_has_dc_support - check if dc is supported | |
2196 | * | |
2197 | * @adev: amdgpu_device_pointer | |
2198 | * | |
2199 | * Returns true for supported, false for not supported | |
2200 | */ | |
2201 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2202 | { | |
2555039d XY |
2203 | if (amdgpu_sriov_vf(adev)) |
2204 | return false; | |
2205 | ||
4562236b HW |
2206 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2207 | } | |
2208 | ||
d38ceaf9 AD |
2209 | /** |
2210 | * amdgpu_device_init - initialize the driver | |
2211 | * | |
2212 | * @adev: amdgpu_device pointer | |
2213 | * @pdev: drm dev pointer | |
2214 | * @pdev: pci dev pointer | |
2215 | * @flags: driver flags | |
2216 | * | |
2217 | * Initializes the driver info and hw (all asics). | |
2218 | * Returns 0 for success or an error on failure. | |
2219 | * Called at driver startup. | |
2220 | */ | |
2221 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2222 | struct drm_device *ddev, | |
2223 | struct pci_dev *pdev, | |
2224 | uint32_t flags) | |
2225 | { | |
2226 | int r, i; | |
2227 | bool runtime = false; | |
95844d20 | 2228 | u32 max_MBps; |
d38ceaf9 AD |
2229 | |
2230 | adev->shutdown = false; | |
2231 | adev->dev = &pdev->dev; | |
2232 | adev->ddev = ddev; | |
2233 | adev->pdev = pdev; | |
2234 | adev->flags = flags; | |
2f7d10b3 | 2235 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2236 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 SL |
2237 | if (amdgpu_emu_mode == 1) |
2238 | adev->usec_timeout *= 2; | |
770d13b1 | 2239 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2240 | adev->accel_working = false; |
2241 | adev->num_rings = 0; | |
2242 | adev->mman.buffer_funcs = NULL; | |
2243 | adev->mman.buffer_funcs_ring = NULL; | |
2244 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2245 | adev->vm_manager.vm_pte_num_rings = 0; |
132f34e4 | 2246 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 2247 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2248 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2249 | |
2250 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2251 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2252 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2253 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2254 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2255 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2256 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2257 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2258 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2259 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2260 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2261 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2262 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2263 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2264 | ||
3e39ab90 AD |
2265 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2266 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2267 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2268 | |
2269 | /* mutex initialization are all done here so we | |
2270 | * can recall function without having locking issues */ | |
d38ceaf9 | 2271 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2272 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2273 | mutex_init(&adev->pm.mutex); |
2274 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2275 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2276 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d38ceaf9 | 2277 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2278 | mutex_init(&adev->mn_lock); |
e23b74aa | 2279 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 2280 | hash_init(adev->mn_hash); |
13a752e3 | 2281 | mutex_init(&adev->lock_reset); |
d38ceaf9 | 2282 | |
06ec9070 | 2283 | amdgpu_device_check_arguments(adev); |
d38ceaf9 | 2284 | |
d38ceaf9 AD |
2285 | spin_lock_init(&adev->mmio_idx_lock); |
2286 | spin_lock_init(&adev->smc_idx_lock); | |
2287 | spin_lock_init(&adev->pcie_idx_lock); | |
2288 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2289 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2290 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2291 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2292 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2293 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2294 | |
0c4e7fa5 CZ |
2295 | INIT_LIST_HEAD(&adev->shadow_list); |
2296 | mutex_init(&adev->shadow_list_lock); | |
2297 | ||
795f2813 AR |
2298 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2299 | spin_lock_init(&adev->ring_lru_list_lock); | |
2300 | ||
06ec9070 AD |
2301 | INIT_DELAYED_WORK(&adev->late_init_work, |
2302 | amdgpu_device_ip_late_init_func_handler); | |
2dc80b00 | 2303 | |
0fa49558 AX |
2304 | /* Registers mapping */ |
2305 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2306 | if (adev->asic_type >= CHIP_BONAIRE) { |
2307 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2308 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2309 | } else { | |
2310 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2311 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2312 | } | |
d38ceaf9 | 2313 | |
d38ceaf9 AD |
2314 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2315 | if (adev->rmmio == NULL) { | |
2316 | return -ENOMEM; | |
2317 | } | |
2318 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2319 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2320 | ||
705e519e | 2321 | /* doorbell bar mapping */ |
06ec9070 | 2322 | amdgpu_device_doorbell_init(adev); |
d38ceaf9 AD |
2323 | |
2324 | /* io port mapping */ | |
2325 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2326 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2327 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2328 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2329 | break; | |
2330 | } | |
2331 | } | |
2332 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2333 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 2334 | |
5494d864 AD |
2335 | amdgpu_device_get_pcie_info(adev); |
2336 | ||
d38ceaf9 | 2337 | /* early init functions */ |
06ec9070 | 2338 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
2339 | if (r) |
2340 | return r; | |
2341 | ||
2342 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2343 | /* this will fail for cards that aren't VGA class devices, just | |
2344 | * ignore it */ | |
06ec9070 | 2345 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 2346 | |
e9bef455 | 2347 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2348 | runtime = true; |
84c8b22e LW |
2349 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2350 | vga_switcheroo_register_client(adev->pdev, | |
2351 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2352 | if (runtime) |
2353 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2354 | ||
9475a943 SL |
2355 | if (amdgpu_emu_mode == 1) { |
2356 | /* post the asic on emulation mode */ | |
2357 | emu_soc_asic_init(adev); | |
bfca0289 | 2358 | goto fence_driver_init; |
9475a943 | 2359 | } |
bfca0289 | 2360 | |
d38ceaf9 | 2361 | /* Read BIOS */ |
83ba126a AD |
2362 | if (!amdgpu_get_bios(adev)) { |
2363 | r = -EINVAL; | |
2364 | goto failed; | |
2365 | } | |
f7e9e9fe | 2366 | |
d38ceaf9 | 2367 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2368 | if (r) { |
2369 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
e23b74aa | 2370 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2371 | goto failed; |
2c1a2784 | 2372 | } |
d38ceaf9 | 2373 | |
4e99a44e ML |
2374 | /* detect if we are with an SRIOV vbios */ |
2375 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2376 | |
d38ceaf9 | 2377 | /* Post card if necessary */ |
39c640c0 | 2378 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 2379 | if (!adev->bios) { |
bec86378 | 2380 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2381 | r = -EINVAL; |
2382 | goto failed; | |
d38ceaf9 | 2383 | } |
bec86378 | 2384 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2385 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2386 | if (r) { | |
2387 | dev_err(adev->dev, "gpu post error!\n"); | |
2388 | goto failed; | |
2389 | } | |
d38ceaf9 AD |
2390 | } |
2391 | ||
88b64e95 AD |
2392 | if (adev->is_atom_fw) { |
2393 | /* Initialize clocks */ | |
2394 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2395 | if (r) { | |
2396 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2397 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2398 | goto failed; |
2399 | } | |
2400 | } else { | |
a5bde2f9 AD |
2401 | /* Initialize clocks */ |
2402 | r = amdgpu_atombios_get_clock_info(adev); | |
2403 | if (r) { | |
2404 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2405 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2406 | goto failed; |
a5bde2f9 AD |
2407 | } |
2408 | /* init i2c buses */ | |
4562236b HW |
2409 | if (!amdgpu_device_has_dc_support(adev)) |
2410 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2411 | } |
d38ceaf9 | 2412 | |
bfca0289 | 2413 | fence_driver_init: |
d38ceaf9 AD |
2414 | /* Fence driver */ |
2415 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2416 | if (r) { |
2417 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2418 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2419 | goto failed; |
2c1a2784 | 2420 | } |
d38ceaf9 AD |
2421 | |
2422 | /* init the mode config */ | |
2423 | drm_mode_config_init(adev->ddev); | |
2424 | ||
06ec9070 | 2425 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 2426 | if (r) { |
8840a387 | 2427 | /* failed in exclusive mode due to timeout */ |
2428 | if (amdgpu_sriov_vf(adev) && | |
2429 | !amdgpu_sriov_runtime(adev) && | |
2430 | amdgpu_virt_mmio_blocked(adev) && | |
2431 | !amdgpu_virt_wait_reset(adev)) { | |
2432 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
2433 | /* Don't send request since VF is inactive. */ |
2434 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
2435 | adev->virt.ops = NULL; | |
8840a387 | 2436 | r = -EAGAIN; |
2437 | goto failed; | |
2438 | } | |
06ec9070 | 2439 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 2440 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
83ba126a | 2441 | goto failed; |
d38ceaf9 AD |
2442 | } |
2443 | ||
2444 | adev->accel_working = true; | |
2445 | ||
e59c0205 AX |
2446 | amdgpu_vm_check_compute_bug(adev); |
2447 | ||
95844d20 MO |
2448 | /* Initialize the buffer migration limit. */ |
2449 | if (amdgpu_moverate >= 0) | |
2450 | max_MBps = amdgpu_moverate; | |
2451 | else | |
2452 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2453 | /* Get a log2 for easy divisions. */ | |
2454 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2455 | ||
d38ceaf9 AD |
2456 | r = amdgpu_ib_pool_init(adev); |
2457 | if (r) { | |
2458 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
e23b74aa | 2459 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2460 | goto failed; |
d38ceaf9 AD |
2461 | } |
2462 | ||
2dc8f81e HC |
2463 | if (amdgpu_sriov_vf(adev)) |
2464 | amdgpu_virt_init_data_exchange(adev); | |
2465 | ||
9bc92b9c ML |
2466 | amdgpu_fbdev_init(adev); |
2467 | ||
d2f52ac8 RZ |
2468 | r = amdgpu_pm_sysfs_init(adev); |
2469 | if (r) | |
2470 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2471 | ||
75758255 | 2472 | r = amdgpu_debugfs_gem_init(adev); |
3f14e623 | 2473 | if (r) |
d38ceaf9 | 2474 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2475 | |
2476 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2477 | if (r) |
d38ceaf9 | 2478 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2479 | |
50ab2533 | 2480 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2481 | if (r) |
50ab2533 | 2482 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2483 | |
763efb6c | 2484 | r = amdgpu_debugfs_init(adev); |
db95e218 | 2485 | if (r) |
763efb6c | 2486 | DRM_ERROR("Creating debugfs files failed (%d).\n", r); |
db95e218 | 2487 | |
d38ceaf9 AD |
2488 | if ((amdgpu_testing & 1)) { |
2489 | if (adev->accel_working) | |
2490 | amdgpu_test_moves(adev); | |
2491 | else | |
2492 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2493 | } | |
d38ceaf9 AD |
2494 | if (amdgpu_benchmarking) { |
2495 | if (adev->accel_working) | |
2496 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2497 | else | |
2498 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2499 | } | |
2500 | ||
2501 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2502 | * explicit gating rather than handling it automatically. | |
2503 | */ | |
06ec9070 | 2504 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 2505 | if (r) { |
06ec9070 | 2506 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 2507 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2508 | goto failed; |
2c1a2784 | 2509 | } |
d38ceaf9 AD |
2510 | |
2511 | return 0; | |
83ba126a AD |
2512 | |
2513 | failed: | |
89041940 | 2514 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2515 | if (runtime) |
2516 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 2517 | |
83ba126a | 2518 | return r; |
d38ceaf9 AD |
2519 | } |
2520 | ||
d38ceaf9 AD |
2521 | /** |
2522 | * amdgpu_device_fini - tear down the driver | |
2523 | * | |
2524 | * @adev: amdgpu_device pointer | |
2525 | * | |
2526 | * Tear down the driver info (all asics). | |
2527 | * Called at driver shutdown. | |
2528 | */ | |
2529 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2530 | { | |
2531 | int r; | |
2532 | ||
2533 | DRM_INFO("amdgpu: finishing device.\n"); | |
2534 | adev->shutdown = true; | |
e5b03032 ML |
2535 | /* disable all interrupts */ |
2536 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
2537 | if (adev->mode_info.mode_config_initialized){ |
2538 | if (!amdgpu_device_has_dc_support(adev)) | |
2539 | drm_crtc_force_disable_all(adev->ddev); | |
2540 | else | |
2541 | drm_atomic_helper_shutdown(adev->ddev); | |
2542 | } | |
d38ceaf9 AD |
2543 | amdgpu_ib_pool_fini(adev); |
2544 | amdgpu_fence_driver_fini(adev); | |
58e955d9 | 2545 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2546 | amdgpu_fbdev_fini(adev); |
06ec9070 | 2547 | r = amdgpu_device_ip_fini(adev); |
ab4fe3e1 HR |
2548 | if (adev->firmware.gpu_info_fw) { |
2549 | release_firmware(adev->firmware.gpu_info_fw); | |
2550 | adev->firmware.gpu_info_fw = NULL; | |
2551 | } | |
d38ceaf9 | 2552 | adev->accel_working = false; |
2dc80b00 | 2553 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 | 2554 | /* free i2c buses */ |
4562236b HW |
2555 | if (!amdgpu_device_has_dc_support(adev)) |
2556 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
2557 | |
2558 | if (amdgpu_emu_mode != 1) | |
2559 | amdgpu_atombios_fini(adev); | |
2560 | ||
d38ceaf9 AD |
2561 | kfree(adev->bios); |
2562 | adev->bios = NULL; | |
84c8b22e LW |
2563 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2564 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2565 | if (adev->flags & AMD_IS_PX) |
2566 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2567 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2568 | if (adev->rio_mem) | |
2569 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2570 | adev->rio_mem = NULL; | |
2571 | iounmap(adev->rmmio); | |
2572 | adev->rmmio = NULL; | |
06ec9070 | 2573 | amdgpu_device_doorbell_fini(adev); |
d38ceaf9 | 2574 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2575 | } |
2576 | ||
2577 | ||
2578 | /* | |
2579 | * Suspend & resume. | |
2580 | */ | |
2581 | /** | |
810ddc3a | 2582 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2583 | * |
2584 | * @pdev: drm dev pointer | |
2585 | * @state: suspend state | |
2586 | * | |
2587 | * Puts the hw in the suspend state (all asics). | |
2588 | * Returns 0 for success or an error on failure. | |
2589 | * Called at driver suspend. | |
2590 | */ | |
810ddc3a | 2591 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2592 | { |
2593 | struct amdgpu_device *adev; | |
2594 | struct drm_crtc *crtc; | |
2595 | struct drm_connector *connector; | |
5ceb54c6 | 2596 | int r; |
d38ceaf9 AD |
2597 | |
2598 | if (dev == NULL || dev->dev_private == NULL) { | |
2599 | return -ENODEV; | |
2600 | } | |
2601 | ||
2602 | adev = dev->dev_private; | |
2603 | ||
2604 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2605 | return 0; | |
2606 | ||
2607 | drm_kms_helper_poll_disable(dev); | |
2608 | ||
4562236b HW |
2609 | if (!amdgpu_device_has_dc_support(adev)) { |
2610 | /* turn off display hw */ | |
2611 | drm_modeset_lock_all(dev); | |
2612 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2613 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2614 | } | |
2615 | drm_modeset_unlock_all(dev); | |
d38ceaf9 AD |
2616 | } |
2617 | ||
ba997709 YZ |
2618 | amdgpu_amdkfd_suspend(adev); |
2619 | ||
756e6880 | 2620 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2621 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2622 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
e68d14dd | 2623 | struct drm_framebuffer *fb = crtc->primary->fb; |
d38ceaf9 AD |
2624 | struct amdgpu_bo *robj; |
2625 | ||
756e6880 AD |
2626 | if (amdgpu_crtc->cursor_bo) { |
2627 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2628 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2629 | if (r == 0) { |
2630 | amdgpu_bo_unpin(aobj); | |
2631 | amdgpu_bo_unreserve(aobj); | |
2632 | } | |
2633 | } | |
2634 | ||
e68d14dd | 2635 | if (fb == NULL || fb->obj[0] == NULL) { |
d38ceaf9 AD |
2636 | continue; |
2637 | } | |
e68d14dd | 2638 | robj = gem_to_amdgpu_bo(fb->obj[0]); |
d38ceaf9 AD |
2639 | /* don't unpin kernel fb objects */ |
2640 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2641 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2642 | if (r == 0) { |
2643 | amdgpu_bo_unpin(robj); | |
2644 | amdgpu_bo_unreserve(robj); | |
2645 | } | |
2646 | } | |
2647 | } | |
2648 | /* evict vram memory */ | |
2649 | amdgpu_bo_evict_vram(adev); | |
2650 | ||
5ceb54c6 | 2651 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 2652 | |
cdd61df6 | 2653 | r = amdgpu_device_ip_suspend(adev); |
d38ceaf9 | 2654 | |
a0a71e49 AD |
2655 | /* evict remaining vram memory |
2656 | * This second call to evict vram is to evict the gart page table | |
2657 | * using the CPU. | |
2658 | */ | |
d38ceaf9 AD |
2659 | amdgpu_bo_evict_vram(adev); |
2660 | ||
2661 | pci_save_state(dev->pdev); | |
2662 | if (suspend) { | |
2663 | /* Shut down the device */ | |
2664 | pci_disable_device(dev->pdev); | |
2665 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2666 | } else { |
2667 | r = amdgpu_asic_reset(adev); | |
2668 | if (r) | |
2669 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2670 | } |
2671 | ||
2672 | if (fbcon) { | |
2673 | console_lock(); | |
2674 | amdgpu_fbdev_set_suspend(adev, 1); | |
2675 | console_unlock(); | |
2676 | } | |
2677 | return 0; | |
2678 | } | |
2679 | ||
2680 | /** | |
810ddc3a | 2681 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2682 | * |
2683 | * @pdev: drm dev pointer | |
2684 | * | |
2685 | * Bring the hw back to operating state (all asics). | |
2686 | * Returns 0 for success or an error on failure. | |
2687 | * Called at driver resume. | |
2688 | */ | |
810ddc3a | 2689 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2690 | { |
2691 | struct drm_connector *connector; | |
2692 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2693 | struct drm_crtc *crtc; |
03161a6e | 2694 | int r = 0; |
d38ceaf9 AD |
2695 | |
2696 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2697 | return 0; | |
2698 | ||
74b0b157 | 2699 | if (fbcon) |
d38ceaf9 | 2700 | console_lock(); |
74b0b157 | 2701 | |
d38ceaf9 AD |
2702 | if (resume) { |
2703 | pci_set_power_state(dev->pdev, PCI_D0); | |
2704 | pci_restore_state(dev->pdev); | |
74b0b157 | 2705 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2706 | if (r) |
2707 | goto unlock; | |
d38ceaf9 AD |
2708 | } |
2709 | ||
2710 | /* post card */ | |
39c640c0 | 2711 | if (amdgpu_device_need_post(adev)) { |
74b0b157 | 2712 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2713 | if (r) | |
2714 | DRM_ERROR("amdgpu asic init failed\n"); | |
2715 | } | |
d38ceaf9 | 2716 | |
06ec9070 | 2717 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 2718 | if (r) { |
06ec9070 | 2719 | DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); |
03161a6e | 2720 | goto unlock; |
e6707218 | 2721 | } |
5ceb54c6 AD |
2722 | amdgpu_fence_driver_resume(adev); |
2723 | ||
d38ceaf9 | 2724 | |
06ec9070 | 2725 | r = amdgpu_device_ip_late_init(adev); |
03161a6e HR |
2726 | if (r) |
2727 | goto unlock; | |
d38ceaf9 | 2728 | |
756e6880 AD |
2729 | /* pin cursors */ |
2730 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2731 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2732 | ||
2733 | if (amdgpu_crtc->cursor_bo) { | |
2734 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2735 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2736 | if (r == 0) { |
2737 | r = amdgpu_bo_pin(aobj, | |
2738 | AMDGPU_GEM_DOMAIN_VRAM, | |
2739 | &amdgpu_crtc->cursor_addr); | |
2740 | if (r != 0) | |
2741 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2742 | amdgpu_bo_unreserve(aobj); | |
2743 | } | |
2744 | } | |
2745 | } | |
ba997709 YZ |
2746 | r = amdgpu_amdkfd_resume(adev); |
2747 | if (r) | |
2748 | return r; | |
756e6880 | 2749 | |
d38ceaf9 AD |
2750 | /* blat the mode back in */ |
2751 | if (fbcon) { | |
4562236b HW |
2752 | if (!amdgpu_device_has_dc_support(adev)) { |
2753 | /* pre DCE11 */ | |
2754 | drm_helper_resume_force_mode(dev); | |
2755 | ||
2756 | /* turn on display hw */ | |
2757 | drm_modeset_lock_all(dev); | |
2758 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2759 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2760 | } | |
2761 | drm_modeset_unlock_all(dev); | |
d38ceaf9 AD |
2762 | } |
2763 | } | |
2764 | ||
2765 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2766 | |
2767 | /* | |
2768 | * Most of the connector probing functions try to acquire runtime pm | |
2769 | * refs to ensure that the GPU is powered on when connector polling is | |
2770 | * performed. Since we're calling this from a runtime PM callback, | |
2771 | * trying to acquire rpm refs will cause us to deadlock. | |
2772 | * | |
2773 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2774 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2775 | */ | |
2776 | #ifdef CONFIG_PM | |
2777 | dev->dev->power.disable_depth++; | |
2778 | #endif | |
4562236b HW |
2779 | if (!amdgpu_device_has_dc_support(adev)) |
2780 | drm_helper_hpd_irq_event(dev); | |
2781 | else | |
2782 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
2783 | #ifdef CONFIG_PM |
2784 | dev->dev->power.disable_depth--; | |
2785 | #endif | |
d38ceaf9 | 2786 | |
03161a6e | 2787 | if (fbcon) |
d38ceaf9 | 2788 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2789 | |
2790 | unlock: | |
2791 | if (fbcon) | |
d38ceaf9 | 2792 | console_unlock(); |
d38ceaf9 | 2793 | |
03161a6e | 2794 | return r; |
d38ceaf9 AD |
2795 | } |
2796 | ||
e3ecdffa AD |
2797 | /** |
2798 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
2799 | * | |
2800 | * @adev: amdgpu_device pointer | |
2801 | * | |
2802 | * The list of all the hardware IPs that make up the asic is walked and | |
2803 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
2804 | * if the asic is still hung or not. | |
2805 | * Returns true if any of the IPs are still in a hung state, false if not. | |
2806 | */ | |
06ec9070 | 2807 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
2808 | { |
2809 | int i; | |
2810 | bool asic_hang = false; | |
2811 | ||
f993d628 ML |
2812 | if (amdgpu_sriov_vf(adev)) |
2813 | return true; | |
2814 | ||
8bc04c29 AD |
2815 | if (amdgpu_asic_need_full_reset(adev)) |
2816 | return true; | |
2817 | ||
63fbf42f | 2818 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2819 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2820 | continue; |
a1255107 AD |
2821 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2822 | adev->ip_blocks[i].status.hang = | |
2823 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2824 | if (adev->ip_blocks[i].status.hang) { | |
2825 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2826 | asic_hang = true; |
2827 | } | |
2828 | } | |
2829 | return asic_hang; | |
2830 | } | |
2831 | ||
e3ecdffa AD |
2832 | /** |
2833 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
2834 | * | |
2835 | * @adev: amdgpu_device pointer | |
2836 | * | |
2837 | * The list of all the hardware IPs that make up the asic is walked and the | |
2838 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
2839 | * handles any IP specific hardware or software state changes that are | |
2840 | * necessary for a soft reset to succeed. | |
2841 | * Returns 0 on success, negative error code on failure. | |
2842 | */ | |
06ec9070 | 2843 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2844 | { |
2845 | int i, r = 0; | |
2846 | ||
2847 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2848 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2849 | continue; |
a1255107 AD |
2850 | if (adev->ip_blocks[i].status.hang && |
2851 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2852 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2853 | if (r) |
2854 | return r; | |
2855 | } | |
2856 | } | |
2857 | ||
2858 | return 0; | |
2859 | } | |
2860 | ||
e3ecdffa AD |
2861 | /** |
2862 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
2863 | * | |
2864 | * @adev: amdgpu_device pointer | |
2865 | * | |
2866 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
2867 | * reset is necessary to recover. | |
2868 | * Returns true if a full asic reset is required, false if not. | |
2869 | */ | |
06ec9070 | 2870 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 2871 | { |
da146d3b AD |
2872 | int i; |
2873 | ||
8bc04c29 AD |
2874 | if (amdgpu_asic_need_full_reset(adev)) |
2875 | return true; | |
2876 | ||
da146d3b | 2877 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2878 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2879 | continue; |
a1255107 AD |
2880 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2881 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2882 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
2883 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
2884 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 2885 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
2886 | DRM_INFO("Some block need full reset!\n"); |
2887 | return true; | |
2888 | } | |
2889 | } | |
35d782fe CZ |
2890 | } |
2891 | return false; | |
2892 | } | |
2893 | ||
e3ecdffa AD |
2894 | /** |
2895 | * amdgpu_device_ip_soft_reset - do a soft reset | |
2896 | * | |
2897 | * @adev: amdgpu_device pointer | |
2898 | * | |
2899 | * The list of all the hardware IPs that make up the asic is walked and the | |
2900 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
2901 | * IP specific hardware or software state changes that are necessary to soft | |
2902 | * reset the IP. | |
2903 | * Returns 0 on success, negative error code on failure. | |
2904 | */ | |
06ec9070 | 2905 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2906 | { |
2907 | int i, r = 0; | |
2908 | ||
2909 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2910 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2911 | continue; |
a1255107 AD |
2912 | if (adev->ip_blocks[i].status.hang && |
2913 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2914 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2915 | if (r) |
2916 | return r; | |
2917 | } | |
2918 | } | |
2919 | ||
2920 | return 0; | |
2921 | } | |
2922 | ||
e3ecdffa AD |
2923 | /** |
2924 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
2925 | * | |
2926 | * @adev: amdgpu_device pointer | |
2927 | * | |
2928 | * The list of all the hardware IPs that make up the asic is walked and the | |
2929 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
2930 | * handles any IP specific hardware or software state changes that are | |
2931 | * necessary after the IP has been soft reset. | |
2932 | * Returns 0 on success, negative error code on failure. | |
2933 | */ | |
06ec9070 | 2934 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2935 | { |
2936 | int i, r = 0; | |
2937 | ||
2938 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2939 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2940 | continue; |
a1255107 AD |
2941 | if (adev->ip_blocks[i].status.hang && |
2942 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2943 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2944 | if (r) |
2945 | return r; | |
2946 | } | |
2947 | ||
2948 | return 0; | |
2949 | } | |
2950 | ||
e3ecdffa AD |
2951 | /** |
2952 | * amdgpu_device_recover_vram_from_shadow - restore shadowed VRAM buffers | |
2953 | * | |
2954 | * @adev: amdgpu_device pointer | |
2955 | * @ring: amdgpu_ring for the engine handling the buffer operations | |
2956 | * @bo: amdgpu_bo buffer whose shadow is being restored | |
2957 | * @fence: dma_fence associated with the operation | |
2958 | * | |
2959 | * Restores the VRAM buffer contents from the shadow in GTT. Used to | |
2960 | * restore things like GPUVM page tables after a GPU reset where | |
2961 | * the contents of VRAM might be lost. | |
2962 | * Returns 0 on success, negative error code on failure. | |
2963 | */ | |
06ec9070 AD |
2964 | static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev, |
2965 | struct amdgpu_ring *ring, | |
2966 | struct amdgpu_bo *bo, | |
2967 | struct dma_fence **fence) | |
53cdccd5 CZ |
2968 | { |
2969 | uint32_t domain; | |
2970 | int r; | |
2971 | ||
23d2e504 RH |
2972 | if (!bo->shadow) |
2973 | return 0; | |
2974 | ||
1d284797 | 2975 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2976 | if (r) |
2977 | return r; | |
2978 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2979 | /* if bo has been evicted, then no need to recover */ | |
2980 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2981 | r = amdgpu_bo_validate(bo->shadow); |
2982 | if (r) { | |
2983 | DRM_ERROR("bo validate failed!\n"); | |
2984 | goto err; | |
2985 | } | |
2986 | ||
23d2e504 | 2987 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2988 | NULL, fence, true); |
23d2e504 RH |
2989 | if (r) { |
2990 | DRM_ERROR("recover page table failed!\n"); | |
2991 | goto err; | |
2992 | } | |
2993 | } | |
53cdccd5 | 2994 | err: |
23d2e504 RH |
2995 | amdgpu_bo_unreserve(bo); |
2996 | return r; | |
53cdccd5 CZ |
2997 | } |
2998 | ||
e3ecdffa AD |
2999 | /** |
3000 | * amdgpu_device_handle_vram_lost - Handle the loss of VRAM contents | |
3001 | * | |
3002 | * @adev: amdgpu_device pointer | |
3003 | * | |
3004 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
3005 | * restore things like GPUVM page tables after a GPU reset where | |
3006 | * the contents of VRAM might be lost. | |
3007 | * Returns 0 on success, 1 on failure. | |
3008 | */ | |
c41d1cf6 ML |
3009 | static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev) |
3010 | { | |
3011 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
3012 | struct amdgpu_bo *bo, *tmp; | |
3013 | struct dma_fence *fence = NULL, *next = NULL; | |
3014 | long r = 1; | |
3015 | int i = 0; | |
3016 | long tmo; | |
3017 | ||
3018 | if (amdgpu_sriov_runtime(adev)) | |
3019 | tmo = msecs_to_jiffies(amdgpu_lockup_timeout); | |
3020 | else | |
3021 | tmo = msecs_to_jiffies(100); | |
3022 | ||
3023 | DRM_INFO("recover vram bo from shadow start\n"); | |
3024 | mutex_lock(&adev->shadow_list_lock); | |
3025 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
3026 | next = NULL; | |
3027 | amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next); | |
3028 | if (fence) { | |
3029 | r = dma_fence_wait_timeout(fence, false, tmo); | |
3030 | if (r == 0) | |
3031 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
3032 | else if (r < 0) | |
3033 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
3034 | if (r < 1) { | |
3035 | dma_fence_put(fence); | |
3036 | fence = next; | |
3037 | break; | |
3038 | } | |
3039 | i++; | |
3040 | } | |
3041 | ||
3042 | dma_fence_put(fence); | |
3043 | fence = next; | |
3044 | } | |
3045 | mutex_unlock(&adev->shadow_list_lock); | |
3046 | ||
3047 | if (fence) { | |
3048 | r = dma_fence_wait_timeout(fence, false, tmo); | |
3049 | if (r == 0) | |
3050 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
3051 | else if (r < 0) | |
3052 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
3053 | ||
3054 | } | |
3055 | dma_fence_put(fence); | |
3056 | ||
3057 | if (r > 0) | |
3058 | DRM_INFO("recover vram bo from shadow done\n"); | |
3059 | else | |
3060 | DRM_ERROR("recover vram bo from shadow failed\n"); | |
3061 | ||
e3ecdffa | 3062 | return (r > 0) ? 0 : 1; |
c41d1cf6 ML |
3063 | } |
3064 | ||
e3ecdffa | 3065 | /** |
06ec9070 | 3066 | * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough |
a90ad3c2 ML |
3067 | * |
3068 | * @adev: amdgpu device pointer | |
a90ad3c2 | 3069 | * |
5740682e ML |
3070 | * attempt to do soft-reset or full-reset and reinitialize Asic |
3071 | * return 0 means successed otherwise failed | |
e3ecdffa | 3072 | */ |
c41d1cf6 | 3073 | static int amdgpu_device_reset(struct amdgpu_device *adev) |
a90ad3c2 | 3074 | { |
5740682e ML |
3075 | bool need_full_reset, vram_lost = 0; |
3076 | int r; | |
a90ad3c2 | 3077 | |
06ec9070 | 3078 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); |
a90ad3c2 | 3079 | |
5740682e | 3080 | if (!need_full_reset) { |
06ec9070 AD |
3081 | amdgpu_device_ip_pre_soft_reset(adev); |
3082 | r = amdgpu_device_ip_soft_reset(adev); | |
3083 | amdgpu_device_ip_post_soft_reset(adev); | |
3084 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
5740682e ML |
3085 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); |
3086 | need_full_reset = true; | |
3087 | } | |
5740682e | 3088 | } |
a90ad3c2 | 3089 | |
5740682e | 3090 | if (need_full_reset) { |
cdd61df6 | 3091 | r = amdgpu_device_ip_suspend(adev); |
a90ad3c2 | 3092 | |
5740682e | 3093 | retry: |
5740682e | 3094 | r = amdgpu_asic_reset(adev); |
5740682e ML |
3095 | /* post card */ |
3096 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
65781c78 | 3097 | |
5740682e ML |
3098 | if (!r) { |
3099 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
06ec9070 | 3100 | r = amdgpu_device_ip_resume_phase1(adev); |
5740682e ML |
3101 | if (r) |
3102 | goto out; | |
65781c78 | 3103 | |
06ec9070 | 3104 | vram_lost = amdgpu_device_check_vram_lost(adev); |
5740682e ML |
3105 | if (vram_lost) { |
3106 | DRM_ERROR("VRAM is lost!\n"); | |
3107 | atomic_inc(&adev->vram_lost_counter); | |
3108 | } | |
3109 | ||
c1c7ce8f CK |
3110 | r = amdgpu_gtt_mgr_recover( |
3111 | &adev->mman.bdev.man[TTM_PL_TT]); | |
5740682e ML |
3112 | if (r) |
3113 | goto out; | |
3114 | ||
06ec9070 | 3115 | r = amdgpu_device_ip_resume_phase2(adev); |
5740682e ML |
3116 | if (r) |
3117 | goto out; | |
3118 | ||
3119 | if (vram_lost) | |
06ec9070 | 3120 | amdgpu_device_fill_reset_magic(adev); |
65781c78 | 3121 | } |
5740682e | 3122 | } |
65781c78 | 3123 | |
5740682e ML |
3124 | out: |
3125 | if (!r) { | |
3126 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
3127 | r = amdgpu_ib_ring_tests(adev); | |
3128 | if (r) { | |
3129 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
cdd61df6 | 3130 | r = amdgpu_device_ip_suspend(adev); |
5740682e ML |
3131 | need_full_reset = true; |
3132 | goto retry; | |
3133 | } | |
3134 | } | |
65781c78 | 3135 | |
c41d1cf6 ML |
3136 | if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost)) |
3137 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 | 3138 | |
5740682e ML |
3139 | return r; |
3140 | } | |
a90ad3c2 | 3141 | |
e3ecdffa | 3142 | /** |
06ec9070 | 3143 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3144 | * |
3145 | * @adev: amdgpu device pointer | |
5740682e ML |
3146 | * |
3147 | * do VF FLR and reinitialize Asic | |
3148 | * return 0 means successed otherwise failed | |
e3ecdffa AD |
3149 | */ |
3150 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3151 | bool from_hypervisor) | |
5740682e ML |
3152 | { |
3153 | int r; | |
3154 | ||
3155 | if (from_hypervisor) | |
3156 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3157 | else | |
3158 | r = amdgpu_virt_reset_gpu(adev); | |
3159 | if (r) | |
3160 | return r; | |
a90ad3c2 ML |
3161 | |
3162 | /* Resume IP prior to SMC */ | |
06ec9070 | 3163 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3164 | if (r) |
3165 | goto error; | |
a90ad3c2 ML |
3166 | |
3167 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 3168 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 ML |
3169 | |
3170 | /* now we are okay to resume SMC/CP/SDMA */ | |
06ec9070 | 3171 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
3172 | if (r) |
3173 | goto error; | |
a90ad3c2 ML |
3174 | |
3175 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3176 | r = amdgpu_ib_ring_tests(adev); |
a90ad3c2 | 3177 | |
abc34253 ED |
3178 | error: |
3179 | amdgpu_virt_release_full_gpu(adev, true); | |
c41d1cf6 ML |
3180 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
3181 | atomic_inc(&adev->vram_lost_counter); | |
3182 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 ML |
3183 | } |
3184 | ||
3185 | return r; | |
3186 | } | |
3187 | ||
d38ceaf9 | 3188 | /** |
5f152b5e | 3189 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler |
d38ceaf9 AD |
3190 | * |
3191 | * @adev: amdgpu device pointer | |
5740682e | 3192 | * @job: which job trigger hang |
dcebf026 | 3193 | * @force forces reset regardless of amdgpu_gpu_recovery |
d38ceaf9 | 3194 | * |
5740682e | 3195 | * Attempt to reset the GPU if it has hung (all asics). |
d38ceaf9 AD |
3196 | * Returns 0 for success or an error on failure. |
3197 | */ | |
5f152b5e AD |
3198 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
3199 | struct amdgpu_job *job, bool force) | |
d38ceaf9 | 3200 | { |
5740682e | 3201 | int i, r, resched; |
fb140b29 | 3202 | |
54bc1398 | 3203 | if (!force && !amdgpu_device_ip_check_soft_reset(adev)) { |
63fbf42f CZ |
3204 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); |
3205 | return 0; | |
3206 | } | |
d38ceaf9 | 3207 | |
dcebf026 AG |
3208 | if (!force && (amdgpu_gpu_recovery == 0 || |
3209 | (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) { | |
3210 | DRM_INFO("GPU recovery disabled.\n"); | |
3211 | return 0; | |
3212 | } | |
3213 | ||
5740682e ML |
3214 | dev_info(adev->dev, "GPU reset begin!\n"); |
3215 | ||
13a752e3 | 3216 | mutex_lock(&adev->lock_reset); |
d94aed5a | 3217 | atomic_inc(&adev->gpu_reset_counter); |
13a752e3 | 3218 | adev->in_gpu_reset = 1; |
d38ceaf9 | 3219 | |
a3c47d6b CZ |
3220 | /* block TTM */ |
3221 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
71182665 | 3222 | |
71182665 | 3223 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
3224 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3225 | struct amdgpu_ring *ring = adev->rings[i]; | |
3226 | ||
51687759 | 3227 | if (!ring || !ring->sched.thread) |
0875dc9e | 3228 | continue; |
5740682e | 3229 | |
71182665 ML |
3230 | kthread_park(ring->sched.thread); |
3231 | ||
5740682e ML |
3232 | if (job && job->ring->idx != i) |
3233 | continue; | |
3234 | ||
1b1f42d8 | 3235 | drm_sched_hw_job_reset(&ring->sched, &job->base); |
5740682e | 3236 | |
2f9d4084 ML |
3237 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
3238 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 3239 | } |
d38ceaf9 | 3240 | |
5740682e | 3241 | if (amdgpu_sriov_vf(adev)) |
c41d1cf6 | 3242 | r = amdgpu_device_reset_sriov(adev, job ? false : true); |
5740682e | 3243 | else |
c41d1cf6 | 3244 | r = amdgpu_device_reset(adev); |
5740682e | 3245 | |
71182665 ML |
3246 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3247 | struct amdgpu_ring *ring = adev->rings[i]; | |
53cdccd5 | 3248 | |
71182665 ML |
3249 | if (!ring || !ring->sched.thread) |
3250 | continue; | |
5740682e | 3251 | |
71182665 ML |
3252 | /* only need recovery sched of the given job's ring |
3253 | * or all rings (in the case @job is NULL) | |
3254 | * after above amdgpu_reset accomplished | |
3255 | */ | |
3256 | if ((!job || job->ring->idx == i) && !r) | |
1b1f42d8 | 3257 | drm_sched_job_recovery(&ring->sched); |
5740682e | 3258 | |
71182665 | 3259 | kthread_unpark(ring->sched.thread); |
d38ceaf9 AD |
3260 | } |
3261 | ||
bf830604 | 3262 | if (!amdgpu_device_has_dc_support(adev)) { |
4562236b | 3263 | drm_helper_resume_force_mode(adev->ddev); |
5740682e | 3264 | } |
d38ceaf9 AD |
3265 | |
3266 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
5740682e | 3267 | |
89041940 | 3268 | if (r) { |
d38ceaf9 | 3269 | /* bad news, how to tell it to userspace ? */ |
5740682e ML |
3270 | dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); |
3271 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); | |
3272 | } else { | |
3273 | dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter)); | |
89041940 | 3274 | } |
d38ceaf9 | 3275 | |
89041940 | 3276 | amdgpu_vf_error_trans_all(adev); |
13a752e3 ML |
3277 | adev->in_gpu_reset = 0; |
3278 | mutex_unlock(&adev->lock_reset); | |
d38ceaf9 AD |
3279 | return r; |
3280 | } | |
3281 | ||
e3ecdffa AD |
3282 | /** |
3283 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
3284 | * | |
3285 | * @adev: amdgpu_device pointer | |
3286 | * | |
3287 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
3288 | * and lanes) of the slot the device is in. Handles APUs and | |
3289 | * virtualized environments where PCIE config space may not be available. | |
3290 | */ | |
5494d864 | 3291 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c AD |
3292 | { |
3293 | u32 mask; | |
3294 | int ret; | |
3295 | ||
cd474ba0 AD |
3296 | if (amdgpu_pcie_gen_cap) |
3297 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3298 | |
cd474ba0 AD |
3299 | if (amdgpu_pcie_lane_cap) |
3300 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3301 | |
cd474ba0 AD |
3302 | /* covers APUs as well */ |
3303 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3304 | if (adev->pm.pcie_gen_mask == 0) | |
3305 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3306 | if (adev->pm.pcie_mlw_mask == 0) | |
3307 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3308 | return; |
cd474ba0 | 3309 | } |
d0dd7f0c | 3310 | |
cd474ba0 AD |
3311 | if (adev->pm.pcie_gen_mask == 0) { |
3312 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
3313 | if (!ret) { | |
3314 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3315 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3316 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3317 | ||
3318 | if (mask & DRM_PCIE_SPEED_25) | |
3319 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3320 | if (mask & DRM_PCIE_SPEED_50) | |
3321 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3322 | if (mask & DRM_PCIE_SPEED_80) | |
3323 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3324 | } else { | |
3325 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3326 | } | |
3327 | } | |
3328 | if (adev->pm.pcie_mlw_mask == 0) { | |
3329 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3330 | if (!ret) { | |
3331 | switch (mask) { | |
3332 | case 32: | |
3333 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3334 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3335 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3336 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3337 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3338 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3339 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3340 | break; | |
3341 | case 16: | |
3342 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3343 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3344 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3345 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3346 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3347 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3348 | break; | |
3349 | case 12: | |
3350 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3351 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3352 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3353 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3354 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3355 | break; | |
3356 | case 8: | |
3357 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3358 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3359 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3360 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3361 | break; | |
3362 | case 4: | |
3363 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3364 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3365 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3366 | break; | |
3367 | case 2: | |
3368 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3369 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3370 | break; | |
3371 | case 1: | |
3372 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3373 | break; | |
3374 | default: | |
3375 | break; | |
3376 | } | |
3377 | } else { | |
3378 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3379 | } |
3380 | } | |
3381 | } | |
d38ceaf9 | 3382 |