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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
ba997709 | 58 | #include "amdgpu_amdkfd.h" |
d38ceaf9 | 59 | |
e2a75f88 | 60 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 61 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 62 | |
2dc80b00 S |
63 | #define AMDGPU_RESUME_MS 2000 |
64 | ||
d38ceaf9 AD |
65 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
66 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
4f0955fc | 67 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); |
d38ceaf9 AD |
68 | |
69 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
70 | "TAHITI", |
71 | "PITCAIRN", | |
72 | "VERDE", | |
73 | "OLAND", | |
74 | "HAINAN", | |
d38ceaf9 AD |
75 | "BONAIRE", |
76 | "KAVERI", | |
77 | "KABINI", | |
78 | "HAWAII", | |
79 | "MULLINS", | |
80 | "TOPAZ", | |
81 | "TONGA", | |
48299f95 | 82 | "FIJI", |
d38ceaf9 | 83 | "CARRIZO", |
139f4917 | 84 | "STONEY", |
2cc0c0b5 FC |
85 | "POLARIS10", |
86 | "POLARIS11", | |
c4642a47 | 87 | "POLARIS12", |
d4196f01 | 88 | "VEGA10", |
2ca8a5d2 | 89 | "RAVEN", |
d38ceaf9 AD |
90 | "LAST", |
91 | }; | |
92 | ||
93 | bool amdgpu_device_is_px(struct drm_device *dev) | |
94 | { | |
95 | struct amdgpu_device *adev = dev->dev_private; | |
96 | ||
2f7d10b3 | 97 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
98 | return true; |
99 | return false; | |
100 | } | |
101 | ||
102 | /* | |
103 | * MMIO register access helper functions. | |
104 | */ | |
105 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 106 | uint32_t acc_flags) |
d38ceaf9 | 107 | { |
f4b373f4 TSD |
108 | uint32_t ret; |
109 | ||
15d72fd7 | 110 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
111 | BUG_ON(in_interrupt()); |
112 | return amdgpu_virt_kiq_rreg(adev, reg); | |
113 | } | |
114 | ||
15d72fd7 | 115 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 116 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
117 | else { |
118 | unsigned long flags; | |
d38ceaf9 AD |
119 | |
120 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
121 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
122 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
123 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 124 | } |
f4b373f4 TSD |
125 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
126 | return ret; | |
d38ceaf9 AD |
127 | } |
128 | ||
129 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 130 | uint32_t acc_flags) |
d38ceaf9 | 131 | { |
f4b373f4 | 132 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 133 | |
47ed4e1c KW |
134 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
135 | adev->last_mm_index = v; | |
136 | } | |
137 | ||
15d72fd7 | 138 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
139 | BUG_ON(in_interrupt()); |
140 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
141 | } | |
142 | ||
15d72fd7 | 143 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
144 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
145 | else { | |
146 | unsigned long flags; | |
147 | ||
148 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
149 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
150 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
151 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
152 | } | |
47ed4e1c KW |
153 | |
154 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
155 | udelay(500); | |
156 | } | |
d38ceaf9 AD |
157 | } |
158 | ||
159 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
160 | { | |
161 | if ((reg * 4) < adev->rio_mem_size) | |
162 | return ioread32(adev->rio_mem + (reg * 4)); | |
163 | else { | |
164 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
165 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
166 | } | |
167 | } | |
168 | ||
169 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
170 | { | |
47ed4e1c KW |
171 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
172 | adev->last_mm_index = v; | |
173 | } | |
d38ceaf9 AD |
174 | |
175 | if ((reg * 4) < adev->rio_mem_size) | |
176 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
177 | else { | |
178 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
179 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
180 | } | |
47ed4e1c KW |
181 | |
182 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
183 | udelay(500); | |
184 | } | |
d38ceaf9 AD |
185 | } |
186 | ||
187 | /** | |
188 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
189 | * | |
190 | * @adev: amdgpu_device pointer | |
191 | * @index: doorbell index | |
192 | * | |
193 | * Returns the value in the doorbell aperture at the | |
194 | * requested doorbell index (CIK). | |
195 | */ | |
196 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
197 | { | |
198 | if (index < adev->doorbell.num_doorbells) { | |
199 | return readl(adev->doorbell.ptr + index); | |
200 | } else { | |
201 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
202 | return 0; | |
203 | } | |
204 | } | |
205 | ||
206 | /** | |
207 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
208 | * | |
209 | * @adev: amdgpu_device pointer | |
210 | * @index: doorbell index | |
211 | * @v: value to write | |
212 | * | |
213 | * Writes @v to the doorbell aperture at the | |
214 | * requested doorbell index (CIK). | |
215 | */ | |
216 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
217 | { | |
218 | if (index < adev->doorbell.num_doorbells) { | |
219 | writel(v, adev->doorbell.ptr + index); | |
220 | } else { | |
221 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
222 | } | |
223 | } | |
224 | ||
832be404 KW |
225 | /** |
226 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
227 | * | |
228 | * @adev: amdgpu_device pointer | |
229 | * @index: doorbell index | |
230 | * | |
231 | * Returns the value in the doorbell aperture at the | |
232 | * requested doorbell index (VEGA10+). | |
233 | */ | |
234 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
235 | { | |
236 | if (index < adev->doorbell.num_doorbells) { | |
237 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
238 | } else { | |
239 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
240 | return 0; | |
241 | } | |
242 | } | |
243 | ||
244 | /** | |
245 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
246 | * | |
247 | * @adev: amdgpu_device pointer | |
248 | * @index: doorbell index | |
249 | * @v: value to write | |
250 | * | |
251 | * Writes @v to the doorbell aperture at the | |
252 | * requested doorbell index (VEGA10+). | |
253 | */ | |
254 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
255 | { | |
256 | if (index < adev->doorbell.num_doorbells) { | |
257 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
258 | } else { | |
259 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
260 | } | |
261 | } | |
262 | ||
d38ceaf9 AD |
263 | /** |
264 | * amdgpu_invalid_rreg - dummy reg read function | |
265 | * | |
266 | * @adev: amdgpu device pointer | |
267 | * @reg: offset of register | |
268 | * | |
269 | * Dummy register read function. Used for register blocks | |
270 | * that certain asics don't have (all asics). | |
271 | * Returns the value in the register. | |
272 | */ | |
273 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
274 | { | |
275 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
276 | BUG(); | |
277 | return 0; | |
278 | } | |
279 | ||
280 | /** | |
281 | * amdgpu_invalid_wreg - dummy reg write function | |
282 | * | |
283 | * @adev: amdgpu device pointer | |
284 | * @reg: offset of register | |
285 | * @v: value to write to the register | |
286 | * | |
287 | * Dummy register read function. Used for register blocks | |
288 | * that certain asics don't have (all asics). | |
289 | */ | |
290 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
291 | { | |
292 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
293 | reg, v); | |
294 | BUG(); | |
295 | } | |
296 | ||
297 | /** | |
298 | * amdgpu_block_invalid_rreg - dummy reg read function | |
299 | * | |
300 | * @adev: amdgpu device pointer | |
301 | * @block: offset of instance | |
302 | * @reg: offset of register | |
303 | * | |
304 | * Dummy register read function. Used for register blocks | |
305 | * that certain asics don't have (all asics). | |
306 | * Returns the value in the register. | |
307 | */ | |
308 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
309 | uint32_t block, uint32_t reg) | |
310 | { | |
311 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
312 | reg, block); | |
313 | BUG(); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | /** | |
318 | * amdgpu_block_invalid_wreg - dummy reg write function | |
319 | * | |
320 | * @adev: amdgpu device pointer | |
321 | * @block: offset of instance | |
322 | * @reg: offset of register | |
323 | * @v: value to write to the register | |
324 | * | |
325 | * Dummy register read function. Used for register blocks | |
326 | * that certain asics don't have (all asics). | |
327 | */ | |
328 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
329 | uint32_t block, | |
330 | uint32_t reg, uint32_t v) | |
331 | { | |
332 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
333 | reg, block, v); | |
334 | BUG(); | |
335 | } | |
336 | ||
337 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
338 | { | |
a4a02777 CK |
339 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
340 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
341 | &adev->vram_scratch.robj, | |
342 | &adev->vram_scratch.gpu_addr, | |
343 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
344 | } |
345 | ||
346 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
347 | { | |
078af1a3 | 348 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
349 | } |
350 | ||
351 | /** | |
352 | * amdgpu_program_register_sequence - program an array of registers. | |
353 | * | |
354 | * @adev: amdgpu_device pointer | |
355 | * @registers: pointer to the register array | |
356 | * @array_size: size of the register array | |
357 | * | |
358 | * Programs an array or registers with and and or masks. | |
359 | * This is a helper for setting golden registers. | |
360 | */ | |
361 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
362 | const u32 *registers, | |
363 | const u32 array_size) | |
364 | { | |
365 | u32 tmp, reg, and_mask, or_mask; | |
366 | int i; | |
367 | ||
368 | if (array_size % 3) | |
369 | return; | |
370 | ||
371 | for (i = 0; i < array_size; i +=3) { | |
372 | reg = registers[i + 0]; | |
373 | and_mask = registers[i + 1]; | |
374 | or_mask = registers[i + 2]; | |
375 | ||
376 | if (and_mask == 0xffffffff) { | |
377 | tmp = or_mask; | |
378 | } else { | |
379 | tmp = RREG32(reg); | |
380 | tmp &= ~and_mask; | |
381 | tmp |= or_mask; | |
382 | } | |
383 | WREG32(reg, tmp); | |
384 | } | |
385 | } | |
386 | ||
387 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
388 | { | |
389 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
390 | } | |
391 | ||
392 | /* | |
393 | * GPU doorbell aperture helpers function. | |
394 | */ | |
395 | /** | |
396 | * amdgpu_doorbell_init - Init doorbell driver information. | |
397 | * | |
398 | * @adev: amdgpu_device pointer | |
399 | * | |
400 | * Init doorbell driver information (CIK) | |
401 | * Returns 0 on success, error on failure. | |
402 | */ | |
403 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
404 | { | |
405 | /* doorbell bar mapping */ | |
406 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
407 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
408 | ||
edf600da | 409 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
410 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
411 | if (adev->doorbell.num_doorbells == 0) | |
412 | return -EINVAL; | |
413 | ||
8972e5d2 CK |
414 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
415 | adev->doorbell.num_doorbells * | |
416 | sizeof(u32)); | |
417 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 418 | return -ENOMEM; |
d38ceaf9 AD |
419 | |
420 | return 0; | |
421 | } | |
422 | ||
423 | /** | |
424 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
425 | * | |
426 | * @adev: amdgpu_device pointer | |
427 | * | |
428 | * Tear down doorbell driver information (CIK) | |
429 | */ | |
430 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
431 | { | |
432 | iounmap(adev->doorbell.ptr); | |
433 | adev->doorbell.ptr = NULL; | |
434 | } | |
435 | ||
436 | /** | |
437 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
438 | * setup amdkfd | |
439 | * | |
440 | * @adev: amdgpu_device pointer | |
441 | * @aperture_base: output returning doorbell aperture base physical address | |
442 | * @aperture_size: output returning doorbell aperture size in bytes | |
443 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
444 | * | |
445 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
446 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
447 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
448 | */ | |
449 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
450 | phys_addr_t *aperture_base, | |
451 | size_t *aperture_size, | |
452 | size_t *start_offset) | |
453 | { | |
454 | /* | |
455 | * The first num_doorbells are used by amdgpu. | |
456 | * amdkfd takes whatever's left in the aperture. | |
457 | */ | |
458 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
459 | *aperture_base = adev->doorbell.base; | |
460 | *aperture_size = adev->doorbell.size; | |
461 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
462 | } else { | |
463 | *aperture_base = 0; | |
464 | *aperture_size = 0; | |
465 | *start_offset = 0; | |
466 | } | |
467 | } | |
468 | ||
469 | /* | |
470 | * amdgpu_wb_*() | |
455a7bc2 | 471 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 472 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
473 | */ |
474 | ||
475 | /** | |
476 | * amdgpu_wb_fini - Disable Writeback and free memory | |
477 | * | |
478 | * @adev: amdgpu_device pointer | |
479 | * | |
480 | * Disables Writeback and frees the Writeback memory (all asics). | |
481 | * Used at driver shutdown. | |
482 | */ | |
483 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
484 | { | |
485 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
486 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
487 | &adev->wb.gpu_addr, | |
488 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
489 | adev->wb.wb_obj = NULL; |
490 | } | |
491 | } | |
492 | ||
493 | /** | |
494 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
495 | * | |
496 | * @adev: amdgpu_device pointer | |
497 | * | |
455a7bc2 | 498 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
499 | * Used at driver startup. |
500 | * Returns 0 on success or an -error on failure. | |
501 | */ | |
502 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
503 | { | |
504 | int r; | |
505 | ||
506 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 507 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
508 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
509 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
510 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
511 | if (r) { |
512 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
513 | return r; | |
514 | } | |
d38ceaf9 AD |
515 | |
516 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
517 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
518 | ||
519 | /* clear wb memory */ | |
60a970a6 | 520 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
521 | } |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /** | |
527 | * amdgpu_wb_get - Allocate a wb entry | |
528 | * | |
529 | * @adev: amdgpu_device pointer | |
530 | * @wb: wb index | |
531 | * | |
532 | * Allocate a wb slot for use by the driver (all asics). | |
533 | * Returns 0 on success or -EINVAL on failure. | |
534 | */ | |
535 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
536 | { | |
537 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
538 | if (offset < adev->wb.num_wb) { | |
539 | __set_bit(offset, adev->wb.used); | |
540 | *wb = offset; | |
541 | return 0; | |
542 | } else { | |
543 | return -EINVAL; | |
544 | } | |
545 | } | |
546 | ||
7014285a KW |
547 | /** |
548 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
549 | * | |
550 | * @adev: amdgpu_device pointer | |
551 | * @wb: wb index | |
552 | * | |
553 | * Allocate a wb slot for use by the driver (all asics). | |
554 | * Returns 0 on success or -EINVAL on failure. | |
555 | */ | |
556 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
557 | { | |
558 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
559 | adev->wb.num_wb, 0, 2, 7, 0); | |
560 | if ((offset + 1) < adev->wb.num_wb) { | |
561 | __set_bit(offset, adev->wb.used); | |
562 | __set_bit(offset + 1, adev->wb.used); | |
563 | *wb = offset; | |
564 | return 0; | |
565 | } else { | |
566 | return -EINVAL; | |
567 | } | |
568 | } | |
569 | ||
eacf3e14 | 570 | int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb) |
0915fdbc ML |
571 | { |
572 | int i = 0; | |
573 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
574 | adev->wb.num_wb, 0, 8, 63, 0); | |
575 | if ((offset + 7) < adev->wb.num_wb) { | |
576 | for (i = 0; i < 8; i++) | |
577 | __set_bit(offset + i, adev->wb.used); | |
578 | *wb = offset; | |
579 | return 0; | |
580 | } else { | |
581 | return -EINVAL; | |
582 | } | |
583 | } | |
584 | ||
d38ceaf9 AD |
585 | /** |
586 | * amdgpu_wb_free - Free a wb entry | |
587 | * | |
588 | * @adev: amdgpu_device pointer | |
589 | * @wb: wb index | |
590 | * | |
591 | * Free a wb slot allocated for use by the driver (all asics) | |
592 | */ | |
593 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
594 | { | |
595 | if (wb < adev->wb.num_wb) | |
596 | __clear_bit(wb, adev->wb.used); | |
597 | } | |
598 | ||
7014285a KW |
599 | /** |
600 | * amdgpu_wb_free_64bit - Free a wb entry | |
601 | * | |
602 | * @adev: amdgpu_device pointer | |
603 | * @wb: wb index | |
604 | * | |
605 | * Free a wb slot allocated for use by the driver (all asics) | |
606 | */ | |
607 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
608 | { | |
609 | if ((wb + 1) < adev->wb.num_wb) { | |
610 | __clear_bit(wb, adev->wb.used); | |
611 | __clear_bit(wb + 1, adev->wb.used); | |
612 | } | |
613 | } | |
614 | ||
0915fdbc ML |
615 | /** |
616 | * amdgpu_wb_free_256bit - Free a wb entry | |
617 | * | |
618 | * @adev: amdgpu_device pointer | |
619 | * @wb: wb index | |
620 | * | |
621 | * Free a wb slot allocated for use by the driver (all asics) | |
622 | */ | |
623 | void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb) | |
624 | { | |
625 | int i = 0; | |
626 | ||
627 | if ((wb + 7) < adev->wb.num_wb) | |
628 | for (i = 0; i < 8; i++) | |
629 | __clear_bit(wb + i, adev->wb.used); | |
630 | } | |
631 | ||
d38ceaf9 AD |
632 | /** |
633 | * amdgpu_vram_location - try to find VRAM location | |
634 | * @adev: amdgpu device structure holding all necessary informations | |
635 | * @mc: memory controller structure holding memory informations | |
636 | * @base: base address at which to put VRAM | |
637 | * | |
455a7bc2 | 638 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
639 | * as parameter (which is so far either PCI aperture address or |
640 | * for IGP TOM base address). | |
641 | * | |
642 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
643 | * address space then we limit the VRAM size to the aperture. | |
644 | * | |
645 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
646 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
647 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
648 | * not IGP. | |
649 | * | |
650 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
651 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
652 | * Novell bug 204882 + along with lots of ubuntu ones | |
653 | * | |
654 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
655 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
656 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
657 | * ones) | |
658 | * | |
659 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 660 | * explicitly check for that though. |
d38ceaf9 AD |
661 | * |
662 | * FIXME: when reducing VRAM size align new size on power of 2. | |
663 | */ | |
664 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
665 | { | |
666 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
667 | ||
668 | mc->vram_start = base; | |
669 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
670 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
671 | mc->real_vram_size = mc->aper_size; | |
672 | mc->mc_vram_size = mc->aper_size; | |
673 | } | |
674 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
675 | if (limit && limit < mc->real_vram_size) | |
676 | mc->real_vram_size = limit; | |
677 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
678 | mc->mc_vram_size >> 20, mc->vram_start, | |
679 | mc->vram_end, mc->real_vram_size >> 20); | |
680 | } | |
681 | ||
682 | /** | |
6f02a696 | 683 | * amdgpu_gart_location - try to find GTT location |
d38ceaf9 AD |
684 | * @adev: amdgpu device structure holding all necessary informations |
685 | * @mc: memory controller structure holding memory informations | |
686 | * | |
687 | * Function will place try to place GTT before or after VRAM. | |
688 | * | |
689 | * If GTT size is bigger than space left then we ajust GTT size. | |
690 | * Thus function will never fails. | |
691 | * | |
692 | * FIXME: when reducing GTT size align new size on power of 2. | |
693 | */ | |
6f02a696 | 694 | void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) |
d38ceaf9 AD |
695 | { |
696 | u64 size_af, size_bf; | |
697 | ||
ed21c047 CK |
698 | size_af = adev->mc.mc_mask - mc->vram_end; |
699 | size_bf = mc->vram_start; | |
d38ceaf9 | 700 | if (size_bf > size_af) { |
6f02a696 | 701 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 702 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 703 | mc->gart_size = size_bf; |
d38ceaf9 | 704 | } |
6f02a696 | 705 | mc->gart_start = 0; |
d38ceaf9 | 706 | } else { |
6f02a696 | 707 | if (mc->gart_size > size_af) { |
d38ceaf9 | 708 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 709 | mc->gart_size = size_af; |
d38ceaf9 | 710 | } |
6f02a696 | 711 | mc->gart_start = mc->vram_end + 1; |
d38ceaf9 | 712 | } |
6f02a696 | 713 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 714 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 715 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
716 | } |
717 | ||
718 | /* | |
719 | * GPU helpers function. | |
720 | */ | |
721 | /** | |
c836fec5 | 722 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
723 | * |
724 | * @adev: amdgpu_device pointer | |
725 | * | |
c836fec5 JQ |
726 | * Check if the asic has been initialized (all asics) at driver startup |
727 | * or post is needed if hw reset is performed. | |
728 | * Returns true if need or false if not. | |
d38ceaf9 | 729 | */ |
c836fec5 | 730 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
731 | { |
732 | uint32_t reg; | |
733 | ||
c836fec5 JQ |
734 | if (adev->has_hw_reset) { |
735 | adev->has_hw_reset = false; | |
736 | return true; | |
737 | } | |
70d17a25 AD |
738 | |
739 | /* bios scratch used on CIK+ */ | |
740 | if (adev->asic_type >= CHIP_BONAIRE) | |
741 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
742 | ||
743 | /* check MEM_SIZE for older asics */ | |
bbf282d8 | 744 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 | 745 | |
f2713e8c | 746 | if ((reg != 0) && (reg != 0xffffffff)) |
c836fec5 | 747 | return false; |
d38ceaf9 | 748 | |
c836fec5 | 749 | return true; |
d38ceaf9 AD |
750 | |
751 | } | |
752 | ||
bec86378 ML |
753 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
754 | { | |
755 | if (amdgpu_sriov_vf(adev)) | |
756 | return false; | |
757 | ||
758 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
759 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
760 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
761 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
762 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
763 | */ |
764 | if (adev->asic_type == CHIP_FIJI) { | |
765 | int err; | |
766 | uint32_t fw_ver; | |
767 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
768 | /* force vPost if error occured */ | |
769 | if (err) | |
770 | return true; | |
771 | ||
772 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
773 | if (fw_ver < 0x00160e00) |
774 | return true; | |
bec86378 | 775 | } |
bec86378 | 776 | } |
c836fec5 | 777 | return amdgpu_need_post(adev); |
bec86378 ML |
778 | } |
779 | ||
d38ceaf9 AD |
780 | /** |
781 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
782 | * | |
783 | * @adev: amdgpu_device pointer | |
784 | * | |
785 | * Allocate the dummy page used by the driver (all asics). | |
786 | * This dummy page is used by the driver as a filler for gart entries | |
787 | * when pages are taken out of the GART | |
788 | * Returns 0 on sucess, -ENOMEM on failure. | |
789 | */ | |
790 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
791 | { | |
792 | if (adev->dummy_page.page) | |
793 | return 0; | |
794 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
795 | if (adev->dummy_page.page == NULL) | |
796 | return -ENOMEM; | |
797 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
798 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
799 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
800 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
801 | __free_page(adev->dummy_page.page); | |
802 | adev->dummy_page.page = NULL; | |
803 | return -ENOMEM; | |
804 | } | |
805 | return 0; | |
806 | } | |
807 | ||
808 | /** | |
809 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
810 | * | |
811 | * @adev: amdgpu_device pointer | |
812 | * | |
813 | * Frees the dummy page used by the driver (all asics). | |
814 | */ | |
815 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
816 | { | |
817 | if (adev->dummy_page.page == NULL) | |
818 | return; | |
819 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
820 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
821 | __free_page(adev->dummy_page.page); | |
822 | adev->dummy_page.page = NULL; | |
823 | } | |
824 | ||
825 | ||
826 | /* ATOM accessor methods */ | |
827 | /* | |
828 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
829 | * driver registers callbacks to access registers and the interpreter | |
830 | * in the driver parses the tables and executes then to program specific | |
831 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
832 | * atombios.h, and atom.c | |
833 | */ | |
834 | ||
835 | /** | |
836 | * cail_pll_read - read PLL register | |
837 | * | |
838 | * @info: atom card_info pointer | |
839 | * @reg: PLL register offset | |
840 | * | |
841 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
842 | * Returns the value of the PLL register. | |
843 | */ | |
844 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
845 | { | |
846 | return 0; | |
847 | } | |
848 | ||
849 | /** | |
850 | * cail_pll_write - write PLL register | |
851 | * | |
852 | * @info: atom card_info pointer | |
853 | * @reg: PLL register offset | |
854 | * @val: value to write to the pll register | |
855 | * | |
856 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
857 | */ | |
858 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
859 | { | |
860 | ||
861 | } | |
862 | ||
863 | /** | |
864 | * cail_mc_read - read MC (Memory Controller) register | |
865 | * | |
866 | * @info: atom card_info pointer | |
867 | * @reg: MC register offset | |
868 | * | |
869 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
870 | * Returns the value of the MC register. | |
871 | */ | |
872 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
873 | { | |
874 | return 0; | |
875 | } | |
876 | ||
877 | /** | |
878 | * cail_mc_write - write MC (Memory Controller) register | |
879 | * | |
880 | * @info: atom card_info pointer | |
881 | * @reg: MC register offset | |
882 | * @val: value to write to the pll register | |
883 | * | |
884 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
885 | */ | |
886 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
887 | { | |
888 | ||
889 | } | |
890 | ||
891 | /** | |
892 | * cail_reg_write - write MMIO register | |
893 | * | |
894 | * @info: atom card_info pointer | |
895 | * @reg: MMIO register offset | |
896 | * @val: value to write to the pll register | |
897 | * | |
898 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
899 | */ | |
900 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
901 | { | |
902 | struct amdgpu_device *adev = info->dev->dev_private; | |
903 | ||
904 | WREG32(reg, val); | |
905 | } | |
906 | ||
907 | /** | |
908 | * cail_reg_read - read MMIO register | |
909 | * | |
910 | * @info: atom card_info pointer | |
911 | * @reg: MMIO register offset | |
912 | * | |
913 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
914 | * Returns the value of the MMIO register. | |
915 | */ | |
916 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
917 | { | |
918 | struct amdgpu_device *adev = info->dev->dev_private; | |
919 | uint32_t r; | |
920 | ||
921 | r = RREG32(reg); | |
922 | return r; | |
923 | } | |
924 | ||
925 | /** | |
926 | * cail_ioreg_write - write IO register | |
927 | * | |
928 | * @info: atom card_info pointer | |
929 | * @reg: IO register offset | |
930 | * @val: value to write to the pll register | |
931 | * | |
932 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
933 | */ | |
934 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
935 | { | |
936 | struct amdgpu_device *adev = info->dev->dev_private; | |
937 | ||
938 | WREG32_IO(reg, val); | |
939 | } | |
940 | ||
941 | /** | |
942 | * cail_ioreg_read - read IO register | |
943 | * | |
944 | * @info: atom card_info pointer | |
945 | * @reg: IO register offset | |
946 | * | |
947 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
948 | * Returns the value of the IO register. | |
949 | */ | |
950 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
951 | { | |
952 | struct amdgpu_device *adev = info->dev->dev_private; | |
953 | uint32_t r; | |
954 | ||
955 | r = RREG32_IO(reg); | |
956 | return r; | |
957 | } | |
958 | ||
959 | /** | |
960 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
961 | * | |
962 | * @adev: amdgpu_device pointer | |
963 | * | |
964 | * Frees the driver info and register access callbacks for the ATOM | |
965 | * interpreter (r4xx+). | |
966 | * Called at driver shutdown. | |
967 | */ | |
968 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
969 | { | |
89e0ec9f | 970 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 971 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
972 | kfree(adev->mode_info.atom_context->iio); |
973 | } | |
d38ceaf9 AD |
974 | kfree(adev->mode_info.atom_context); |
975 | adev->mode_info.atom_context = NULL; | |
976 | kfree(adev->mode_info.atom_card_info); | |
977 | adev->mode_info.atom_card_info = NULL; | |
978 | } | |
979 | ||
980 | /** | |
981 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
982 | * | |
983 | * @adev: amdgpu_device pointer | |
984 | * | |
985 | * Initializes the driver info and register access callbacks for the | |
986 | * ATOM interpreter (r4xx+). | |
987 | * Returns 0 on sucess, -ENOMEM on failure. | |
988 | * Called at driver startup. | |
989 | */ | |
990 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
991 | { | |
992 | struct card_info *atom_card_info = | |
993 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
994 | ||
995 | if (!atom_card_info) | |
996 | return -ENOMEM; | |
997 | ||
998 | adev->mode_info.atom_card_info = atom_card_info; | |
999 | atom_card_info->dev = adev->ddev; | |
1000 | atom_card_info->reg_read = cail_reg_read; | |
1001 | atom_card_info->reg_write = cail_reg_write; | |
1002 | /* needed for iio ops */ | |
1003 | if (adev->rio_mem) { | |
1004 | atom_card_info->ioreg_read = cail_ioreg_read; | |
1005 | atom_card_info->ioreg_write = cail_ioreg_write; | |
1006 | } else { | |
b64a18c5 | 1007 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
1008 | atom_card_info->ioreg_read = cail_reg_read; |
1009 | atom_card_info->ioreg_write = cail_reg_write; | |
1010 | } | |
1011 | atom_card_info->mc_read = cail_mc_read; | |
1012 | atom_card_info->mc_write = cail_mc_write; | |
1013 | atom_card_info->pll_read = cail_pll_read; | |
1014 | atom_card_info->pll_write = cail_pll_write; | |
1015 | ||
1016 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
1017 | if (!adev->mode_info.atom_context) { | |
1018 | amdgpu_atombios_fini(adev); | |
1019 | return -ENOMEM; | |
1020 | } | |
1021 | ||
1022 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1023 | if (adev->is_atom_fw) { |
1024 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1025 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1026 | } else { | |
1027 | amdgpu_atombios_scratch_regs_init(adev); | |
1028 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1029 | } | |
d38ceaf9 AD |
1030 | return 0; |
1031 | } | |
1032 | ||
1033 | /* if we get transitioned to only one device, take VGA back */ | |
1034 | /** | |
1035 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1036 | * | |
1037 | * @cookie: amdgpu_device pointer | |
1038 | * @state: enable/disable vga decode | |
1039 | * | |
1040 | * Enable/disable vga decode (all asics). | |
1041 | * Returns VGA resource flags. | |
1042 | */ | |
1043 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1044 | { | |
1045 | struct amdgpu_device *adev = cookie; | |
1046 | amdgpu_asic_set_vga_state(adev, state); | |
1047 | if (state) | |
1048 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1049 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1050 | else | |
1051 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1052 | } | |
1053 | ||
bab4fee7 | 1054 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1055 | { |
1056 | /* defines number of bits in page table versus page directory, | |
1057 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1058 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1059 | if (amdgpu_vm_block_size == -1) |
1060 | return; | |
a1adf8be | 1061 | |
bab4fee7 | 1062 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1063 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1064 | amdgpu_vm_block_size); | |
bab4fee7 | 1065 | goto def_value; |
a1adf8be CZ |
1066 | } |
1067 | ||
1068 | if (amdgpu_vm_block_size > 24 || | |
1069 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1070 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1071 | amdgpu_vm_block_size); | |
bab4fee7 | 1072 | goto def_value; |
a1adf8be | 1073 | } |
bab4fee7 JZ |
1074 | |
1075 | return; | |
1076 | ||
1077 | def_value: | |
1078 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1079 | } |
1080 | ||
83ca145d ZJ |
1081 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1082 | { | |
64dab074 AD |
1083 | /* no need to check the default value */ |
1084 | if (amdgpu_vm_size == -1) | |
1085 | return; | |
1086 | ||
76117507 | 1087 | if (!is_power_of_2(amdgpu_vm_size)) { |
83ca145d ZJ |
1088 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", |
1089 | amdgpu_vm_size); | |
1090 | goto def_value; | |
1091 | } | |
1092 | ||
1093 | if (amdgpu_vm_size < 1) { | |
1094 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1095 | amdgpu_vm_size); | |
1096 | goto def_value; | |
1097 | } | |
1098 | ||
1099 | /* | |
1100 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1101 | */ | |
1102 | if (amdgpu_vm_size > 1024) { | |
1103 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1104 | amdgpu_vm_size); | |
1105 | goto def_value; | |
1106 | } | |
1107 | ||
1108 | return; | |
1109 | ||
1110 | def_value: | |
bab4fee7 | 1111 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1112 | } |
1113 | ||
d38ceaf9 AD |
1114 | /** |
1115 | * amdgpu_check_arguments - validate module params | |
1116 | * | |
1117 | * @adev: amdgpu_device pointer | |
1118 | * | |
1119 | * Validates certain module parameters and updates | |
1120 | * the associated values used by the driver (all asics). | |
1121 | */ | |
1122 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1123 | { | |
5b011235 CZ |
1124 | if (amdgpu_sched_jobs < 4) { |
1125 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1126 | amdgpu_sched_jobs); | |
1127 | amdgpu_sched_jobs = 4; | |
76117507 | 1128 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1129 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1130 | amdgpu_sched_jobs); | |
1131 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1132 | } | |
d38ceaf9 | 1133 | |
f9321cc4 CK |
1134 | if (amdgpu_gart_size < 32) { |
1135 | /* gart size must be greater or equal to 32M */ | |
1136 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1137 | amdgpu_gart_size); | |
1138 | amdgpu_gart_size = 32; | |
d38ceaf9 AD |
1139 | } |
1140 | ||
36d38372 | 1141 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1142 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1143 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1144 | amdgpu_gtt_size); | |
1145 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1146 | } |
1147 | ||
83ca145d | 1148 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1149 | |
bab4fee7 | 1150 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1151 | |
526bae37 | 1152 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1153 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1154 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1155 | amdgpu_vram_page_split); | |
1156 | amdgpu_vram_page_split = 1024; | |
1157 | } | |
d38ceaf9 AD |
1158 | } |
1159 | ||
1160 | /** | |
1161 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1162 | * | |
1163 | * @pdev: pci dev pointer | |
1694467b | 1164 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1165 | * |
1166 | * Callback for the switcheroo driver. Suspends or resumes the | |
1167 | * the asics before or after it is powered up using ACPI methods. | |
1168 | */ | |
1169 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1170 | { | |
1171 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1172 | ||
1173 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1174 | return; | |
1175 | ||
1176 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1177 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1178 | /* don't suspend or resume card normally */ |
1179 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1180 | ||
810ddc3a | 1181 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1182 | |
d38ceaf9 AD |
1183 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1184 | drm_kms_helper_poll_enable(dev); | |
1185 | } else { | |
7ca85295 | 1186 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1187 | drm_kms_helper_poll_disable(dev); |
1188 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1189 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1190 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1191 | } | |
1192 | } | |
1193 | ||
1194 | /** | |
1195 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1196 | * | |
1197 | * @pdev: pci dev pointer | |
1198 | * | |
1199 | * Callback for the switcheroo driver. Check of the switcheroo | |
1200 | * state can be changed. | |
1201 | * Returns true if the state can be changed, false if not. | |
1202 | */ | |
1203 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1204 | { | |
1205 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1206 | ||
1207 | /* | |
1208 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1209 | * locking inversion with the driver load path. And the access here is | |
1210 | * completely racy anyway. So don't bother with locking for now. | |
1211 | */ | |
1212 | return dev->open_count == 0; | |
1213 | } | |
1214 | ||
1215 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1216 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1217 | .reprobe = NULL, | |
1218 | .can_switch = amdgpu_switcheroo_can_switch, | |
1219 | }; | |
1220 | ||
1221 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1222 | enum amd_ip_block_type block_type, |
1223 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1224 | { |
1225 | int i, r = 0; | |
1226 | ||
1227 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1228 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1229 | continue; |
c722865a RZ |
1230 | if (adev->ip_blocks[i].version->type != block_type) |
1231 | continue; | |
1232 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1233 | continue; | |
1234 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1235 | (void *)adev, state); | |
1236 | if (r) | |
1237 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1238 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1239 | } |
1240 | return r; | |
1241 | } | |
1242 | ||
1243 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1244 | enum amd_ip_block_type block_type, |
1245 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1246 | { |
1247 | int i, r = 0; | |
1248 | ||
1249 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1250 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1251 | continue; |
c722865a RZ |
1252 | if (adev->ip_blocks[i].version->type != block_type) |
1253 | continue; | |
1254 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1255 | continue; | |
1256 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1257 | (void *)adev, state); | |
1258 | if (r) | |
1259 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1260 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1261 | } |
1262 | return r; | |
1263 | } | |
1264 | ||
6cb2d4e4 HR |
1265 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1266 | { | |
1267 | int i; | |
1268 | ||
1269 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1270 | if (!adev->ip_blocks[i].status.valid) | |
1271 | continue; | |
1272 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1273 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1274 | } | |
1275 | } | |
1276 | ||
5dbbb60b AD |
1277 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1278 | enum amd_ip_block_type block_type) | |
1279 | { | |
1280 | int i, r; | |
1281 | ||
1282 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1283 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1284 | continue; |
a1255107 AD |
1285 | if (adev->ip_blocks[i].version->type == block_type) { |
1286 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1287 | if (r) |
1288 | return r; | |
1289 | break; | |
1290 | } | |
1291 | } | |
1292 | return 0; | |
1293 | ||
1294 | } | |
1295 | ||
1296 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1297 | enum amd_ip_block_type block_type) | |
1298 | { | |
1299 | int i; | |
1300 | ||
1301 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1302 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1303 | continue; |
a1255107 AD |
1304 | if (adev->ip_blocks[i].version->type == block_type) |
1305 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1306 | } |
1307 | return true; | |
1308 | ||
1309 | } | |
1310 | ||
a1255107 AD |
1311 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1312 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1313 | { |
1314 | int i; | |
1315 | ||
1316 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1317 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1318 | return &adev->ip_blocks[i]; |
1319 | ||
1320 | return NULL; | |
1321 | } | |
1322 | ||
1323 | /** | |
1324 | * amdgpu_ip_block_version_cmp | |
1325 | * | |
1326 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1327 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1328 | * @major: major version |
1329 | * @minor: minor version | |
1330 | * | |
1331 | * return 0 if equal or greater | |
1332 | * return 1 if smaller or the ip_block doesn't exist | |
1333 | */ | |
1334 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1335 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1336 | u32 major, u32 minor) |
1337 | { | |
a1255107 | 1338 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1339 | |
a1255107 AD |
1340 | if (ip_block && ((ip_block->version->major > major) || |
1341 | ((ip_block->version->major == major) && | |
1342 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1343 | return 0; |
1344 | ||
1345 | return 1; | |
1346 | } | |
1347 | ||
a1255107 AD |
1348 | /** |
1349 | * amdgpu_ip_block_add | |
1350 | * | |
1351 | * @adev: amdgpu_device pointer | |
1352 | * @ip_block_version: pointer to the IP to add | |
1353 | * | |
1354 | * Adds the IP block driver information to the collection of IPs | |
1355 | * on the asic. | |
1356 | */ | |
1357 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1358 | const struct amdgpu_ip_block_version *ip_block_version) | |
1359 | { | |
1360 | if (!ip_block_version) | |
1361 | return -EINVAL; | |
1362 | ||
a0bae357 HR |
1363 | DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, |
1364 | ip_block_version->funcs->name); | |
1365 | ||
a1255107 AD |
1366 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
483ef985 | 1371 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1372 | { |
1373 | adev->enable_virtual_display = false; | |
1374 | ||
1375 | if (amdgpu_virtual_display) { | |
1376 | struct drm_device *ddev = adev->ddev; | |
1377 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1378 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1379 | |
1380 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1381 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1382 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1383 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1384 | if (!strcmp("all", pciaddname) |
1385 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1386 | long num_crtc; |
1387 | int res = -1; | |
1388 | ||
9accf2fd | 1389 | adev->enable_virtual_display = true; |
0f66356d ED |
1390 | |
1391 | if (pciaddname_tmp) | |
1392 | res = kstrtol(pciaddname_tmp, 10, | |
1393 | &num_crtc); | |
1394 | ||
1395 | if (!res) { | |
1396 | if (num_crtc < 1) | |
1397 | num_crtc = 1; | |
1398 | if (num_crtc > 6) | |
1399 | num_crtc = 6; | |
1400 | adev->mode_info.num_crtc = num_crtc; | |
1401 | } else { | |
1402 | adev->mode_info.num_crtc = 1; | |
1403 | } | |
9accf2fd ED |
1404 | break; |
1405 | } | |
1406 | } | |
1407 | ||
0f66356d ED |
1408 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1409 | amdgpu_virtual_display, pci_address_name, | |
1410 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1411 | |
1412 | kfree(pciaddstr); | |
1413 | } | |
1414 | } | |
1415 | ||
e2a75f88 AD |
1416 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1417 | { | |
e2a75f88 AD |
1418 | const char *chip_name; |
1419 | char fw_name[30]; | |
1420 | int err; | |
1421 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1422 | ||
ab4fe3e1 HR |
1423 | adev->firmware.gpu_info_fw = NULL; |
1424 | ||
e2a75f88 AD |
1425 | switch (adev->asic_type) { |
1426 | case CHIP_TOPAZ: | |
1427 | case CHIP_TONGA: | |
1428 | case CHIP_FIJI: | |
1429 | case CHIP_POLARIS11: | |
1430 | case CHIP_POLARIS10: | |
1431 | case CHIP_POLARIS12: | |
1432 | case CHIP_CARRIZO: | |
1433 | case CHIP_STONEY: | |
1434 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1435 | case CHIP_VERDE: | |
1436 | case CHIP_TAHITI: | |
1437 | case CHIP_PITCAIRN: | |
1438 | case CHIP_OLAND: | |
1439 | case CHIP_HAINAN: | |
1440 | #endif | |
1441 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1442 | case CHIP_BONAIRE: | |
1443 | case CHIP_HAWAII: | |
1444 | case CHIP_KAVERI: | |
1445 | case CHIP_KABINI: | |
1446 | case CHIP_MULLINS: | |
1447 | #endif | |
1448 | default: | |
1449 | return 0; | |
1450 | case CHIP_VEGA10: | |
1451 | chip_name = "vega10"; | |
1452 | break; | |
2d2e5e7e AD |
1453 | case CHIP_RAVEN: |
1454 | chip_name = "raven"; | |
1455 | break; | |
e2a75f88 AD |
1456 | } |
1457 | ||
1458 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1459 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1460 | if (err) { |
1461 | dev_err(adev->dev, | |
1462 | "Failed to load gpu_info firmware \"%s\"\n", | |
1463 | fw_name); | |
1464 | goto out; | |
1465 | } | |
ab4fe3e1 | 1466 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1467 | if (err) { |
1468 | dev_err(adev->dev, | |
1469 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1470 | fw_name); | |
1471 | goto out; | |
1472 | } | |
1473 | ||
ab4fe3e1 | 1474 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1475 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1476 | ||
1477 | switch (hdr->version_major) { | |
1478 | case 1: | |
1479 | { | |
1480 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1481 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1482 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1483 | ||
b5ab16bf AD |
1484 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1485 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1486 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1487 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1488 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1489 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1490 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1491 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1492 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1493 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1494 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1495 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1496 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1497 | adev->gfx.cu_info.max_waves_per_simd = |
1498 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1499 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1500 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1501 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1502 | break; |
1503 | } | |
1504 | default: | |
1505 | dev_err(adev->dev, | |
1506 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1507 | err = -EINVAL; | |
1508 | goto out; | |
1509 | } | |
1510 | out: | |
e2a75f88 AD |
1511 | return err; |
1512 | } | |
1513 | ||
d38ceaf9 AD |
1514 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1515 | { | |
aaa36a97 | 1516 | int i, r; |
d38ceaf9 | 1517 | |
483ef985 | 1518 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1519 | |
d38ceaf9 | 1520 | switch (adev->asic_type) { |
aaa36a97 AD |
1521 | case CHIP_TOPAZ: |
1522 | case CHIP_TONGA: | |
48299f95 | 1523 | case CHIP_FIJI: |
2cc0c0b5 FC |
1524 | case CHIP_POLARIS11: |
1525 | case CHIP_POLARIS10: | |
c4642a47 | 1526 | case CHIP_POLARIS12: |
aaa36a97 | 1527 | case CHIP_CARRIZO: |
39bb0c92 SL |
1528 | case CHIP_STONEY: |
1529 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1530 | adev->family = AMDGPU_FAMILY_CZ; |
1531 | else | |
1532 | adev->family = AMDGPU_FAMILY_VI; | |
1533 | ||
1534 | r = vi_set_ip_blocks(adev); | |
1535 | if (r) | |
1536 | return r; | |
1537 | break; | |
33f34802 KW |
1538 | #ifdef CONFIG_DRM_AMDGPU_SI |
1539 | case CHIP_VERDE: | |
1540 | case CHIP_TAHITI: | |
1541 | case CHIP_PITCAIRN: | |
1542 | case CHIP_OLAND: | |
1543 | case CHIP_HAINAN: | |
295d0daf | 1544 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1545 | r = si_set_ip_blocks(adev); |
1546 | if (r) | |
1547 | return r; | |
1548 | break; | |
1549 | #endif | |
a2e73f56 AD |
1550 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1551 | case CHIP_BONAIRE: | |
1552 | case CHIP_HAWAII: | |
1553 | case CHIP_KAVERI: | |
1554 | case CHIP_KABINI: | |
1555 | case CHIP_MULLINS: | |
1556 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1557 | adev->family = AMDGPU_FAMILY_CI; | |
1558 | else | |
1559 | adev->family = AMDGPU_FAMILY_KV; | |
1560 | ||
1561 | r = cik_set_ip_blocks(adev); | |
1562 | if (r) | |
1563 | return r; | |
1564 | break; | |
1565 | #endif | |
2ca8a5d2 CZ |
1566 | case CHIP_VEGA10: |
1567 | case CHIP_RAVEN: | |
1568 | if (adev->asic_type == CHIP_RAVEN) | |
1569 | adev->family = AMDGPU_FAMILY_RV; | |
1570 | else | |
1571 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1572 | |
1573 | r = soc15_set_ip_blocks(adev); | |
1574 | if (r) | |
1575 | return r; | |
1576 | break; | |
d38ceaf9 AD |
1577 | default: |
1578 | /* FIXME: not supported yet */ | |
1579 | return -EINVAL; | |
1580 | } | |
1581 | ||
e2a75f88 AD |
1582 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1583 | if (r) | |
1584 | return r; | |
1585 | ||
3149d9da XY |
1586 | if (amdgpu_sriov_vf(adev)) { |
1587 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1588 | if (r) | |
1589 | return r; | |
1590 | } | |
1591 | ||
d38ceaf9 AD |
1592 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1593 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1594 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1595 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1596 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1597 | } else { |
a1255107 AD |
1598 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1599 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1600 | if (r == -ENOENT) { |
a1255107 | 1601 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1602 | } else if (r) { |
a1255107 AD |
1603 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1604 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1605 | return r; |
2c1a2784 | 1606 | } else { |
a1255107 | 1607 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1608 | } |
974e6b64 | 1609 | } else { |
a1255107 | 1610 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1611 | } |
d38ceaf9 AD |
1612 | } |
1613 | } | |
1614 | ||
395d1fb9 NH |
1615 | adev->cg_flags &= amdgpu_cg_mask; |
1616 | adev->pg_flags &= amdgpu_pg_mask; | |
1617 | ||
d38ceaf9 AD |
1618 | return 0; |
1619 | } | |
1620 | ||
1621 | static int amdgpu_init(struct amdgpu_device *adev) | |
1622 | { | |
1623 | int i, r; | |
1624 | ||
1625 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1626 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1627 | continue; |
a1255107 | 1628 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1629 | if (r) { |
a1255107 AD |
1630 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1631 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1632 | return r; |
2c1a2784 | 1633 | } |
a1255107 | 1634 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1635 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1636 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1637 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1638 | if (r) { |
1639 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1640 | return r; |
2c1a2784 | 1641 | } |
a1255107 | 1642 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1643 | if (r) { |
1644 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1645 | return r; |
2c1a2784 | 1646 | } |
d38ceaf9 | 1647 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1648 | if (r) { |
1649 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1650 | return r; |
2c1a2784 | 1651 | } |
a1255107 | 1652 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1653 | |
1654 | /* right after GMC hw init, we create CSA */ | |
1655 | if (amdgpu_sriov_vf(adev)) { | |
1656 | r = amdgpu_allocate_static_csa(adev); | |
1657 | if (r) { | |
1658 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1659 | return r; | |
1660 | } | |
1661 | } | |
d38ceaf9 AD |
1662 | } |
1663 | } | |
1664 | ||
1665 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1666 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1667 | continue; |
1668 | /* gmc hw init is done early */ | |
a1255107 | 1669 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1670 | continue; |
a1255107 | 1671 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1672 | if (r) { |
a1255107 AD |
1673 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1674 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1675 | return r; |
2c1a2784 | 1676 | } |
a1255107 | 1677 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1678 | } |
1679 | ||
1680 | return 0; | |
1681 | } | |
1682 | ||
0c49e0b8 CZ |
1683 | static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) |
1684 | { | |
1685 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1686 | } | |
1687 | ||
1688 | static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) | |
1689 | { | |
1690 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1691 | AMDGPU_RESET_MAGIC_NUM); | |
1692 | } | |
1693 | ||
2dc80b00 | 1694 | static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1695 | { |
1696 | int i = 0, r; | |
1697 | ||
1698 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1699 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1700 | continue; |
4a446d55 | 1701 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1702 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1703 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1704 | /* enable clockgating to save power */ |
a1255107 AD |
1705 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1706 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1707 | if (r) { |
1708 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1709 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1710 | return r; |
1711 | } | |
b0b00ff1 | 1712 | } |
d38ceaf9 | 1713 | } |
2dc80b00 S |
1714 | return 0; |
1715 | } | |
1716 | ||
1717 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1718 | { | |
1719 | int i = 0, r; | |
1720 | ||
1721 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1722 | if (!adev->ip_blocks[i].status.valid) | |
1723 | continue; | |
1724 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1725 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1726 | if (r) { | |
1727 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1728 | adev->ip_blocks[i].version->funcs->name, r); | |
1729 | return r; | |
1730 | } | |
1731 | adev->ip_blocks[i].status.late_initialized = true; | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1736 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1737 | |
0c49e0b8 | 1738 | amdgpu_fill_reset_magic(adev); |
d38ceaf9 AD |
1739 | |
1740 | return 0; | |
1741 | } | |
1742 | ||
1743 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1744 | { | |
1745 | int i, r; | |
1746 | ||
3e96dbfd AD |
1747 | /* need to disable SMC first */ |
1748 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1749 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1750 | continue; |
a1255107 | 1751 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1752 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1753 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1754 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1755 | if (r) { |
1756 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1757 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1758 | return r; |
1759 | } | |
a1255107 | 1760 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1761 | /* XXX handle errors */ |
1762 | if (r) { | |
1763 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1764 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1765 | } |
a1255107 | 1766 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1767 | break; |
1768 | } | |
1769 | } | |
1770 | ||
d38ceaf9 | 1771 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1772 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1773 | continue; |
a1255107 | 1774 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1775 | amdgpu_wb_fini(adev); |
1776 | amdgpu_vram_scratch_fini(adev); | |
1777 | } | |
8201a67a RZ |
1778 | |
1779 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1780 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1781 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1782 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1783 | AMD_CG_STATE_UNGATE); | |
1784 | if (r) { | |
1785 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1786 | adev->ip_blocks[i].version->funcs->name, r); | |
1787 | return r; | |
1788 | } | |
2c1a2784 | 1789 | } |
8201a67a | 1790 | |
a1255107 | 1791 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1792 | /* XXX handle errors */ |
2c1a2784 | 1793 | if (r) { |
a1255107 AD |
1794 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1795 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1796 | } |
8201a67a | 1797 | |
a1255107 | 1798 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1799 | } |
1800 | ||
1801 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1802 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1803 | continue; |
a1255107 | 1804 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1805 | /* XXX handle errors */ |
2c1a2784 | 1806 | if (r) { |
a1255107 AD |
1807 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1808 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1809 | } |
a1255107 AD |
1810 | adev->ip_blocks[i].status.sw = false; |
1811 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1812 | } |
1813 | ||
a6dcfd9c | 1814 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1815 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1816 | continue; |
a1255107 AD |
1817 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1818 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1819 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1820 | } |
1821 | ||
3149d9da | 1822 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1823 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1824 | amdgpu_virt_release_full_gpu(adev, false); |
1825 | } | |
2493664f | 1826 | |
d38ceaf9 AD |
1827 | return 0; |
1828 | } | |
1829 | ||
2dc80b00 S |
1830 | static void amdgpu_late_init_func_handler(struct work_struct *work) |
1831 | { | |
1832 | struct amdgpu_device *adev = | |
1833 | container_of(work, struct amdgpu_device, late_init_work.work); | |
1834 | amdgpu_late_set_cg_state(adev); | |
1835 | } | |
1836 | ||
faefba95 | 1837 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1838 | { |
1839 | int i, r; | |
1840 | ||
e941ea99 XY |
1841 | if (amdgpu_sriov_vf(adev)) |
1842 | amdgpu_virt_request_full_gpu(adev, false); | |
1843 | ||
c5a93a28 FC |
1844 | /* ungate SMC block first */ |
1845 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1846 | AMD_CG_STATE_UNGATE); | |
1847 | if (r) { | |
1848 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1849 | } | |
1850 | ||
d38ceaf9 | 1851 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1852 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1853 | continue; |
1854 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1855 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1856 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1857 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1858 | if (r) { |
a1255107 AD |
1859 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1860 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1861 | } |
2c1a2784 | 1862 | } |
d38ceaf9 | 1863 | /* XXX handle errors */ |
a1255107 | 1864 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1865 | /* XXX handle errors */ |
2c1a2784 | 1866 | if (r) { |
a1255107 AD |
1867 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1868 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1869 | } |
d38ceaf9 AD |
1870 | } |
1871 | ||
e941ea99 XY |
1872 | if (amdgpu_sriov_vf(adev)) |
1873 | amdgpu_virt_release_full_gpu(adev, false); | |
1874 | ||
d38ceaf9 AD |
1875 | return 0; |
1876 | } | |
1877 | ||
e4f0fdcc | 1878 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1879 | { |
1880 | int i, r; | |
1881 | ||
2cb681b6 ML |
1882 | static enum amd_ip_block_type ip_order[] = { |
1883 | AMD_IP_BLOCK_TYPE_GMC, | |
1884 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1885 | AMD_IP_BLOCK_TYPE_IH, |
1886 | }; | |
a90ad3c2 | 1887 | |
2cb681b6 ML |
1888 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1889 | int j; | |
1890 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1891 | |
2cb681b6 ML |
1892 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1893 | block = &adev->ip_blocks[j]; | |
1894 | ||
1895 | if (block->version->type != ip_order[i] || | |
1896 | !block->status.valid) | |
1897 | continue; | |
1898 | ||
1899 | r = block->version->funcs->hw_init(adev); | |
1900 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1901 | } |
1902 | } | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | ||
e4f0fdcc | 1907 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1908 | { |
1909 | int i, r; | |
1910 | ||
2cb681b6 ML |
1911 | static enum amd_ip_block_type ip_order[] = { |
1912 | AMD_IP_BLOCK_TYPE_SMC, | |
1913 | AMD_IP_BLOCK_TYPE_DCE, | |
1914 | AMD_IP_BLOCK_TYPE_GFX, | |
1915 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
1916 | AMD_IP_BLOCK_TYPE_UVD, |
1917 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 1918 | }; |
a90ad3c2 | 1919 | |
2cb681b6 ML |
1920 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1921 | int j; | |
1922 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1923 | |
2cb681b6 ML |
1924 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1925 | block = &adev->ip_blocks[j]; | |
1926 | ||
1927 | if (block->version->type != ip_order[i] || | |
1928 | !block->status.valid) | |
1929 | continue; | |
1930 | ||
1931 | r = block->version->funcs->hw_init(adev); | |
1932 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1933 | } |
1934 | } | |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
fcf0649f | 1939 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1940 | { |
1941 | int i, r; | |
1942 | ||
a90ad3c2 ML |
1943 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1944 | if (!adev->ip_blocks[i].status.valid) | |
1945 | continue; | |
a90ad3c2 ML |
1946 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1947 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
fcf0649f CZ |
1948 | adev->ip_blocks[i].version->type == |
1949 | AMD_IP_BLOCK_TYPE_IH) { | |
1950 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1951 | if (r) { | |
1952 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1953 | adev->ip_blocks[i].version->funcs->name, r); | |
1954 | return r; | |
1955 | } | |
a90ad3c2 ML |
1956 | } |
1957 | } | |
1958 | ||
1959 | return 0; | |
1960 | } | |
1961 | ||
fcf0649f | 1962 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
1963 | { |
1964 | int i, r; | |
1965 | ||
1966 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1967 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1968 | continue; |
fcf0649f CZ |
1969 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1970 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1971 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1972 | continue; | |
a1255107 | 1973 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1974 | if (r) { |
a1255107 AD |
1975 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1976 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1977 | return r; |
2c1a2784 | 1978 | } |
d38ceaf9 AD |
1979 | } |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
fcf0649f CZ |
1984 | static int amdgpu_resume(struct amdgpu_device *adev) |
1985 | { | |
1986 | int r; | |
1987 | ||
1988 | r = amdgpu_resume_phase1(adev); | |
1989 | if (r) | |
1990 | return r; | |
1991 | r = amdgpu_resume_phase2(adev); | |
1992 | ||
1993 | return r; | |
1994 | } | |
1995 | ||
4e99a44e | 1996 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1997 | { |
a5bde2f9 AD |
1998 | if (adev->is_atom_fw) { |
1999 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2000 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2001 | } else { | |
2002 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2003 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2004 | } | |
048765ad AR |
2005 | } |
2006 | ||
d38ceaf9 AD |
2007 | /** |
2008 | * amdgpu_device_init - initialize the driver | |
2009 | * | |
2010 | * @adev: amdgpu_device pointer | |
2011 | * @pdev: drm dev pointer | |
2012 | * @pdev: pci dev pointer | |
2013 | * @flags: driver flags | |
2014 | * | |
2015 | * Initializes the driver info and hw (all asics). | |
2016 | * Returns 0 for success or an error on failure. | |
2017 | * Called at driver startup. | |
2018 | */ | |
2019 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2020 | struct drm_device *ddev, | |
2021 | struct pci_dev *pdev, | |
2022 | uint32_t flags) | |
2023 | { | |
2024 | int r, i; | |
2025 | bool runtime = false; | |
95844d20 | 2026 | u32 max_MBps; |
d38ceaf9 AD |
2027 | |
2028 | adev->shutdown = false; | |
2029 | adev->dev = &pdev->dev; | |
2030 | adev->ddev = ddev; | |
2031 | adev->pdev = pdev; | |
2032 | adev->flags = flags; | |
2f7d10b3 | 2033 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2034 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
6f02a696 | 2035 | adev->mc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2036 | adev->accel_working = false; |
2037 | adev->num_rings = 0; | |
2038 | adev->mman.buffer_funcs = NULL; | |
2039 | adev->mman.buffer_funcs_ring = NULL; | |
2040 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2041 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 2042 | adev->gart.gart_funcs = NULL; |
f54d1867 | 2043 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
2044 | |
2045 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2046 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2047 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2048 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2049 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2050 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2051 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2052 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2053 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2054 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2055 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2056 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2057 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2058 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2059 | ||
ccdbb20a | 2060 | |
3e39ab90 AD |
2061 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2062 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2063 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2064 | |
2065 | /* mutex initialization are all done here so we | |
2066 | * can recall function without having locking issues */ | |
d38ceaf9 | 2067 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2068 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2069 | mutex_init(&adev->pm.mutex); |
2070 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2071 | mutex_init(&adev->srbm_mutex); | |
2072 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
2073 | mutex_init(&adev->mn_lock); |
2074 | hash_init(adev->mn_hash); | |
2075 | ||
2076 | amdgpu_check_arguments(adev); | |
2077 | ||
d38ceaf9 AD |
2078 | spin_lock_init(&adev->mmio_idx_lock); |
2079 | spin_lock_init(&adev->smc_idx_lock); | |
2080 | spin_lock_init(&adev->pcie_idx_lock); | |
2081 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2082 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2083 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2084 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2085 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2086 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2087 | |
0c4e7fa5 CZ |
2088 | INIT_LIST_HEAD(&adev->shadow_list); |
2089 | mutex_init(&adev->shadow_list_lock); | |
2090 | ||
5c1354bd CZ |
2091 | INIT_LIST_HEAD(&adev->gtt_list); |
2092 | spin_lock_init(&adev->gtt_list_lock); | |
2093 | ||
795f2813 AR |
2094 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2095 | spin_lock_init(&adev->ring_lru_list_lock); | |
2096 | ||
2dc80b00 S |
2097 | INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); |
2098 | ||
0fa49558 AX |
2099 | /* Registers mapping */ |
2100 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2101 | if (adev->asic_type >= CHIP_BONAIRE) { |
2102 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2103 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2104 | } else { | |
2105 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2106 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2107 | } | |
d38ceaf9 | 2108 | |
d38ceaf9 AD |
2109 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2110 | if (adev->rmmio == NULL) { | |
2111 | return -ENOMEM; | |
2112 | } | |
2113 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2114 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2115 | ||
da69c161 KW |
2116 | if (adev->asic_type >= CHIP_BONAIRE) |
2117 | /* doorbell bar mapping */ | |
2118 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2119 | |
2120 | /* io port mapping */ | |
2121 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2122 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2123 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2124 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2125 | break; | |
2126 | } | |
2127 | } | |
2128 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2129 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2130 | |
2131 | /* early init functions */ | |
2132 | r = amdgpu_early_init(adev); | |
2133 | if (r) | |
2134 | return r; | |
2135 | ||
2136 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2137 | /* this will fail for cards that aren't VGA class devices, just | |
2138 | * ignore it */ | |
2139 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2140 | ||
2141 | if (amdgpu_runtime_pm == 1) | |
2142 | runtime = true; | |
e9bef455 | 2143 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2144 | runtime = true; |
84c8b22e LW |
2145 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2146 | vga_switcheroo_register_client(adev->pdev, | |
2147 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2148 | if (runtime) |
2149 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2150 | ||
2151 | /* Read BIOS */ | |
83ba126a AD |
2152 | if (!amdgpu_get_bios(adev)) { |
2153 | r = -EINVAL; | |
2154 | goto failed; | |
2155 | } | |
f7e9e9fe | 2156 | |
d38ceaf9 | 2157 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2158 | if (r) { |
2159 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
89041940 | 2160 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2161 | goto failed; |
2c1a2784 | 2162 | } |
d38ceaf9 | 2163 | |
4e99a44e ML |
2164 | /* detect if we are with an SRIOV vbios */ |
2165 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2166 | |
d38ceaf9 | 2167 | /* Post card if necessary */ |
bec86378 | 2168 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 2169 | if (!adev->bios) { |
bec86378 | 2170 | dev_err(adev->dev, "no vBIOS found\n"); |
89041940 | 2171 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); |
83ba126a AD |
2172 | r = -EINVAL; |
2173 | goto failed; | |
d38ceaf9 | 2174 | } |
bec86378 | 2175 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2176 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2177 | if (r) { | |
2178 | dev_err(adev->dev, "gpu post error!\n"); | |
89041940 | 2179 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0); |
4e99a44e ML |
2180 | goto failed; |
2181 | } | |
2182 | } else { | |
2183 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
2184 | } |
2185 | ||
88b64e95 AD |
2186 | if (adev->is_atom_fw) { |
2187 | /* Initialize clocks */ | |
2188 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2189 | if (r) { | |
2190 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
2191 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); | |
2192 | goto failed; | |
2193 | } | |
2194 | } else { | |
a5bde2f9 AD |
2195 | /* Initialize clocks */ |
2196 | r = amdgpu_atombios_get_clock_info(adev); | |
2197 | if (r) { | |
2198 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
89041940 GW |
2199 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
2200 | goto failed; | |
a5bde2f9 AD |
2201 | } |
2202 | /* init i2c buses */ | |
2203 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2204 | } |
d38ceaf9 AD |
2205 | |
2206 | /* Fence driver */ | |
2207 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2208 | if (r) { |
2209 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
89041940 | 2210 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2211 | goto failed; |
2c1a2784 | 2212 | } |
d38ceaf9 AD |
2213 | |
2214 | /* init the mode config */ | |
2215 | drm_mode_config_init(adev->ddev); | |
2216 | ||
2217 | r = amdgpu_init(adev); | |
2218 | if (r) { | |
2c1a2784 | 2219 | dev_err(adev->dev, "amdgpu_init failed\n"); |
89041940 | 2220 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
d38ceaf9 | 2221 | amdgpu_fini(adev); |
83ba126a | 2222 | goto failed; |
d38ceaf9 AD |
2223 | } |
2224 | ||
2225 | adev->accel_working = true; | |
2226 | ||
e59c0205 AX |
2227 | amdgpu_vm_check_compute_bug(adev); |
2228 | ||
95844d20 MO |
2229 | /* Initialize the buffer migration limit. */ |
2230 | if (amdgpu_moverate >= 0) | |
2231 | max_MBps = amdgpu_moverate; | |
2232 | else | |
2233 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2234 | /* Get a log2 for easy divisions. */ | |
2235 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2236 | ||
d38ceaf9 AD |
2237 | r = amdgpu_ib_pool_init(adev); |
2238 | if (r) { | |
2239 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
89041940 | 2240 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2241 | goto failed; |
d38ceaf9 AD |
2242 | } |
2243 | ||
2244 | r = amdgpu_ib_ring_tests(adev); | |
2245 | if (r) | |
2246 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2247 | ||
9bc92b9c ML |
2248 | amdgpu_fbdev_init(adev); |
2249 | ||
d38ceaf9 | 2250 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2251 | if (r) |
d38ceaf9 | 2252 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2253 | |
2254 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2255 | if (r) |
d38ceaf9 | 2256 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2257 | |
4f0955fc HR |
2258 | r = amdgpu_debugfs_test_ib_ring_init(adev); |
2259 | if (r) | |
2260 | DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); | |
2261 | ||
50ab2533 | 2262 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2263 | if (r) |
50ab2533 | 2264 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2265 | |
d38ceaf9 AD |
2266 | if ((amdgpu_testing & 1)) { |
2267 | if (adev->accel_working) | |
2268 | amdgpu_test_moves(adev); | |
2269 | else | |
2270 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2271 | } | |
d38ceaf9 AD |
2272 | if (amdgpu_benchmarking) { |
2273 | if (adev->accel_working) | |
2274 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2275 | else | |
2276 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2277 | } | |
2278 | ||
2279 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2280 | * explicit gating rather than handling it automatically. | |
2281 | */ | |
2282 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2283 | if (r) { |
2284 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
89041940 | 2285 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2286 | goto failed; |
2c1a2784 | 2287 | } |
d38ceaf9 AD |
2288 | |
2289 | return 0; | |
83ba126a AD |
2290 | |
2291 | failed: | |
89041940 | 2292 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2293 | if (runtime) |
2294 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2295 | return r; | |
d38ceaf9 AD |
2296 | } |
2297 | ||
d38ceaf9 AD |
2298 | /** |
2299 | * amdgpu_device_fini - tear down the driver | |
2300 | * | |
2301 | * @adev: amdgpu_device pointer | |
2302 | * | |
2303 | * Tear down the driver info (all asics). | |
2304 | * Called at driver shutdown. | |
2305 | */ | |
2306 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2307 | { | |
2308 | int r; | |
2309 | ||
2310 | DRM_INFO("amdgpu: finishing device.\n"); | |
2311 | adev->shutdown = true; | |
db2c2a97 PD |
2312 | if (adev->mode_info.mode_config_initialized) |
2313 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2314 | /* evict vram memory */ |
2315 | amdgpu_bo_evict_vram(adev); | |
2316 | amdgpu_ib_pool_fini(adev); | |
2317 | amdgpu_fence_driver_fini(adev); | |
2318 | amdgpu_fbdev_fini(adev); | |
2319 | r = amdgpu_fini(adev); | |
ab4fe3e1 HR |
2320 | if (adev->firmware.gpu_info_fw) { |
2321 | release_firmware(adev->firmware.gpu_info_fw); | |
2322 | adev->firmware.gpu_info_fw = NULL; | |
2323 | } | |
d38ceaf9 | 2324 | adev->accel_working = false; |
2dc80b00 | 2325 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 AD |
2326 | /* free i2c buses */ |
2327 | amdgpu_i2c_fini(adev); | |
2328 | amdgpu_atombios_fini(adev); | |
2329 | kfree(adev->bios); | |
2330 | adev->bios = NULL; | |
84c8b22e LW |
2331 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2332 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2333 | if (adev->flags & AMD_IS_PX) |
2334 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2335 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2336 | if (adev->rio_mem) | |
2337 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2338 | adev->rio_mem = NULL; | |
2339 | iounmap(adev->rmmio); | |
2340 | adev->rmmio = NULL; | |
da69c161 KW |
2341 | if (adev->asic_type >= CHIP_BONAIRE) |
2342 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2343 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2344 | } |
2345 | ||
2346 | ||
2347 | /* | |
2348 | * Suspend & resume. | |
2349 | */ | |
2350 | /** | |
810ddc3a | 2351 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2352 | * |
2353 | * @pdev: drm dev pointer | |
2354 | * @state: suspend state | |
2355 | * | |
2356 | * Puts the hw in the suspend state (all asics). | |
2357 | * Returns 0 for success or an error on failure. | |
2358 | * Called at driver suspend. | |
2359 | */ | |
810ddc3a | 2360 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2361 | { |
2362 | struct amdgpu_device *adev; | |
2363 | struct drm_crtc *crtc; | |
2364 | struct drm_connector *connector; | |
5ceb54c6 | 2365 | int r; |
d38ceaf9 AD |
2366 | |
2367 | if (dev == NULL || dev->dev_private == NULL) { | |
2368 | return -ENODEV; | |
2369 | } | |
2370 | ||
2371 | adev = dev->dev_private; | |
2372 | ||
2373 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2374 | return 0; | |
2375 | ||
2376 | drm_kms_helper_poll_disable(dev); | |
2377 | ||
2378 | /* turn off display hw */ | |
4c7fbc39 | 2379 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2380 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2381 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2382 | } | |
4c7fbc39 | 2383 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2384 | |
ba997709 YZ |
2385 | amdgpu_amdkfd_suspend(adev); |
2386 | ||
756e6880 | 2387 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2388 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2389 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2390 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2391 | struct amdgpu_bo *robj; | |
2392 | ||
756e6880 AD |
2393 | if (amdgpu_crtc->cursor_bo) { |
2394 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2395 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2396 | if (r == 0) { |
2397 | amdgpu_bo_unpin(aobj); | |
2398 | amdgpu_bo_unreserve(aobj); | |
2399 | } | |
2400 | } | |
2401 | ||
d38ceaf9 AD |
2402 | if (rfb == NULL || rfb->obj == NULL) { |
2403 | continue; | |
2404 | } | |
2405 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2406 | /* don't unpin kernel fb objects */ | |
2407 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2408 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2409 | if (r == 0) { |
2410 | amdgpu_bo_unpin(robj); | |
2411 | amdgpu_bo_unreserve(robj); | |
2412 | } | |
2413 | } | |
2414 | } | |
2415 | /* evict vram memory */ | |
2416 | amdgpu_bo_evict_vram(adev); | |
2417 | ||
5ceb54c6 | 2418 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2419 | |
2420 | r = amdgpu_suspend(adev); | |
2421 | ||
a0a71e49 AD |
2422 | /* evict remaining vram memory |
2423 | * This second call to evict vram is to evict the gart page table | |
2424 | * using the CPU. | |
2425 | */ | |
d38ceaf9 AD |
2426 | amdgpu_bo_evict_vram(adev); |
2427 | ||
d05da0e2 | 2428 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
2429 | pci_save_state(dev->pdev); |
2430 | if (suspend) { | |
2431 | /* Shut down the device */ | |
2432 | pci_disable_device(dev->pdev); | |
2433 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2434 | } else { |
2435 | r = amdgpu_asic_reset(adev); | |
2436 | if (r) | |
2437 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2438 | } |
2439 | ||
2440 | if (fbcon) { | |
2441 | console_lock(); | |
2442 | amdgpu_fbdev_set_suspend(adev, 1); | |
2443 | console_unlock(); | |
2444 | } | |
2445 | return 0; | |
2446 | } | |
2447 | ||
2448 | /** | |
810ddc3a | 2449 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2450 | * |
2451 | * @pdev: drm dev pointer | |
2452 | * | |
2453 | * Bring the hw back to operating state (all asics). | |
2454 | * Returns 0 for success or an error on failure. | |
2455 | * Called at driver resume. | |
2456 | */ | |
810ddc3a | 2457 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2458 | { |
2459 | struct drm_connector *connector; | |
2460 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2461 | struct drm_crtc *crtc; |
03161a6e | 2462 | int r = 0; |
d38ceaf9 AD |
2463 | |
2464 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2465 | return 0; | |
2466 | ||
74b0b157 | 2467 | if (fbcon) |
d38ceaf9 | 2468 | console_lock(); |
74b0b157 | 2469 | |
d38ceaf9 AD |
2470 | if (resume) { |
2471 | pci_set_power_state(dev->pdev, PCI_D0); | |
2472 | pci_restore_state(dev->pdev); | |
74b0b157 | 2473 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2474 | if (r) |
2475 | goto unlock; | |
d38ceaf9 | 2476 | } |
d05da0e2 | 2477 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2478 | |
2479 | /* post card */ | |
c836fec5 | 2480 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2481 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2482 | if (r) | |
2483 | DRM_ERROR("amdgpu asic init failed\n"); | |
2484 | } | |
d38ceaf9 AD |
2485 | |
2486 | r = amdgpu_resume(adev); | |
e6707218 | 2487 | if (r) { |
ca198528 | 2488 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2489 | goto unlock; |
e6707218 | 2490 | } |
5ceb54c6 AD |
2491 | amdgpu_fence_driver_resume(adev); |
2492 | ||
ca198528 FC |
2493 | if (resume) { |
2494 | r = amdgpu_ib_ring_tests(adev); | |
2495 | if (r) | |
2496 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2497 | } | |
d38ceaf9 AD |
2498 | |
2499 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2500 | if (r) |
2501 | goto unlock; | |
d38ceaf9 | 2502 | |
756e6880 AD |
2503 | /* pin cursors */ |
2504 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2505 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2506 | ||
2507 | if (amdgpu_crtc->cursor_bo) { | |
2508 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2509 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2510 | if (r == 0) { |
2511 | r = amdgpu_bo_pin(aobj, | |
2512 | AMDGPU_GEM_DOMAIN_VRAM, | |
2513 | &amdgpu_crtc->cursor_addr); | |
2514 | if (r != 0) | |
2515 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2516 | amdgpu_bo_unreserve(aobj); | |
2517 | } | |
2518 | } | |
2519 | } | |
ba997709 YZ |
2520 | r = amdgpu_amdkfd_resume(adev); |
2521 | if (r) | |
2522 | return r; | |
756e6880 | 2523 | |
d38ceaf9 AD |
2524 | /* blat the mode back in */ |
2525 | if (fbcon) { | |
2526 | drm_helper_resume_force_mode(dev); | |
2527 | /* turn on display hw */ | |
4c7fbc39 | 2528 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2529 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2530 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2531 | } | |
4c7fbc39 | 2532 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2533 | } |
2534 | ||
2535 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2536 | |
2537 | /* | |
2538 | * Most of the connector probing functions try to acquire runtime pm | |
2539 | * refs to ensure that the GPU is powered on when connector polling is | |
2540 | * performed. Since we're calling this from a runtime PM callback, | |
2541 | * trying to acquire rpm refs will cause us to deadlock. | |
2542 | * | |
2543 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2544 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2545 | */ | |
2546 | #ifdef CONFIG_PM | |
2547 | dev->dev->power.disable_depth++; | |
2548 | #endif | |
54fb2a5c | 2549 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2550 | #ifdef CONFIG_PM |
2551 | dev->dev->power.disable_depth--; | |
2552 | #endif | |
d38ceaf9 | 2553 | |
03161a6e | 2554 | if (fbcon) |
d38ceaf9 | 2555 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2556 | |
2557 | unlock: | |
2558 | if (fbcon) | |
d38ceaf9 | 2559 | console_unlock(); |
d38ceaf9 | 2560 | |
03161a6e | 2561 | return r; |
d38ceaf9 AD |
2562 | } |
2563 | ||
63fbf42f CZ |
2564 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2565 | { | |
2566 | int i; | |
2567 | bool asic_hang = false; | |
2568 | ||
2569 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2570 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2571 | continue; |
a1255107 AD |
2572 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2573 | adev->ip_blocks[i].status.hang = | |
2574 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2575 | if (adev->ip_blocks[i].status.hang) { | |
2576 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2577 | asic_hang = true; |
2578 | } | |
2579 | } | |
2580 | return asic_hang; | |
2581 | } | |
2582 | ||
4d446656 | 2583 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2584 | { |
2585 | int i, r = 0; | |
2586 | ||
2587 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2588 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2589 | continue; |
a1255107 AD |
2590 | if (adev->ip_blocks[i].status.hang && |
2591 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2592 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2593 | if (r) |
2594 | return r; | |
2595 | } | |
2596 | } | |
2597 | ||
2598 | return 0; | |
2599 | } | |
2600 | ||
35d782fe CZ |
2601 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2602 | { | |
da146d3b AD |
2603 | int i; |
2604 | ||
2605 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2606 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2607 | continue; |
a1255107 AD |
2608 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2609 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2610 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2611 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2612 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2613 | DRM_INFO("Some block need full reset!\n"); |
2614 | return true; | |
2615 | } | |
2616 | } | |
35d782fe CZ |
2617 | } |
2618 | return false; | |
2619 | } | |
2620 | ||
2621 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2622 | { | |
2623 | int i, r = 0; | |
2624 | ||
2625 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2626 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2627 | continue; |
a1255107 AD |
2628 | if (adev->ip_blocks[i].status.hang && |
2629 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2630 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2631 | if (r) |
2632 | return r; | |
2633 | } | |
2634 | } | |
2635 | ||
2636 | return 0; | |
2637 | } | |
2638 | ||
2639 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2640 | { | |
2641 | int i, r = 0; | |
2642 | ||
2643 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2644 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2645 | continue; |
a1255107 AD |
2646 | if (adev->ip_blocks[i].status.hang && |
2647 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2648 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2649 | if (r) |
2650 | return r; | |
2651 | } | |
2652 | ||
2653 | return 0; | |
2654 | } | |
2655 | ||
3ad81f16 CZ |
2656 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2657 | { | |
2658 | if (adev->flags & AMD_IS_APU) | |
2659 | return false; | |
2660 | ||
2661 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2662 | } | |
2663 | ||
53cdccd5 CZ |
2664 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2665 | struct amdgpu_ring *ring, | |
2666 | struct amdgpu_bo *bo, | |
f54d1867 | 2667 | struct dma_fence **fence) |
53cdccd5 CZ |
2668 | { |
2669 | uint32_t domain; | |
2670 | int r; | |
2671 | ||
23d2e504 RH |
2672 | if (!bo->shadow) |
2673 | return 0; | |
2674 | ||
1d284797 | 2675 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2676 | if (r) |
2677 | return r; | |
2678 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2679 | /* if bo has been evicted, then no need to recover */ | |
2680 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2681 | r = amdgpu_bo_validate(bo->shadow); |
2682 | if (r) { | |
2683 | DRM_ERROR("bo validate failed!\n"); | |
2684 | goto err; | |
2685 | } | |
2686 | ||
2687 | r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem); | |
2688 | if (r) { | |
2689 | DRM_ERROR("%p bind failed\n", bo->shadow); | |
2690 | goto err; | |
2691 | } | |
2692 | ||
23d2e504 | 2693 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2694 | NULL, fence, true); |
23d2e504 RH |
2695 | if (r) { |
2696 | DRM_ERROR("recover page table failed!\n"); | |
2697 | goto err; | |
2698 | } | |
2699 | } | |
53cdccd5 | 2700 | err: |
23d2e504 RH |
2701 | amdgpu_bo_unreserve(bo); |
2702 | return r; | |
53cdccd5 CZ |
2703 | } |
2704 | ||
a90ad3c2 ML |
2705 | /** |
2706 | * amdgpu_sriov_gpu_reset - reset the asic | |
2707 | * | |
2708 | * @adev: amdgpu device pointer | |
7225f873 | 2709 | * @job: which job trigger hang |
a90ad3c2 ML |
2710 | * |
2711 | * Attempt the reset the GPU if it has hung (all asics). | |
2712 | * for SRIOV case. | |
2713 | * Returns 0 for success or an error on failure. | |
2714 | */ | |
7225f873 | 2715 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) |
a90ad3c2 | 2716 | { |
65781c78 | 2717 | int i, j, r = 0; |
a90ad3c2 ML |
2718 | int resched; |
2719 | struct amdgpu_bo *bo, *tmp; | |
2720 | struct amdgpu_ring *ring; | |
2721 | struct dma_fence *fence = NULL, *next = NULL; | |
2722 | ||
147b5983 | 2723 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2724 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2725 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2726 | |
2727 | /* block TTM */ | |
2728 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2729 | ||
65781c78 ML |
2730 | /* we start from the ring trigger GPU hang */ |
2731 | j = job ? job->ring->idx : 0; | |
a90ad3c2 | 2732 | |
65781c78 ML |
2733 | /* block scheduler */ |
2734 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { | |
2735 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2736 | if (!ring || !ring->sched.thread) |
2737 | continue; | |
2738 | ||
2739 | kthread_park(ring->sched.thread); | |
65781c78 ML |
2740 | |
2741 | if (job && j != i) | |
2742 | continue; | |
2743 | ||
4f059ecd | 2744 | /* here give the last chance to check if job removed from mirror-list |
65781c78 | 2745 | * since we already pay some time on kthread_park */ |
4f059ecd | 2746 | if (job && list_empty(&job->base.node)) { |
65781c78 ML |
2747 | kthread_unpark(ring->sched.thread); |
2748 | goto give_up_reset; | |
2749 | } | |
2750 | ||
2751 | if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) | |
2752 | amd_sched_job_kickout(&job->base); | |
2753 | ||
2754 | /* only do job_reset on the hang ring if @job not NULL */ | |
a90ad3c2 | 2755 | amd_sched_hw_job_reset(&ring->sched); |
a90ad3c2 | 2756 | |
65781c78 ML |
2757 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2758 | amdgpu_fence_driver_force_completion_ring(ring); | |
2759 | } | |
a90ad3c2 ML |
2760 | |
2761 | /* request to take full control of GPU before re-initialization */ | |
7225f873 | 2762 | if (job) |
a90ad3c2 ML |
2763 | amdgpu_virt_reset_gpu(adev); |
2764 | else | |
2765 | amdgpu_virt_request_full_gpu(adev, true); | |
2766 | ||
2767 | ||
2768 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2769 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2770 | |
2771 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2772 | amdgpu_ttm_recover_gart(adev); | |
2773 | ||
2774 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2775 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2776 | |
2777 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2778 | ||
2779 | if (amdgpu_ib_ring_tests(adev)) | |
2780 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2781 | ||
2782 | /* release full control of GPU after ib test */ | |
2783 | amdgpu_virt_release_full_gpu(adev, true); | |
2784 | ||
2785 | DRM_INFO("recover vram bo from shadow\n"); | |
2786 | ||
2787 | ring = adev->mman.buffer_funcs_ring; | |
2788 | mutex_lock(&adev->shadow_list_lock); | |
2789 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2790 | next = NULL; |
a90ad3c2 ML |
2791 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2792 | if (fence) { | |
2793 | r = dma_fence_wait(fence, false); | |
2794 | if (r) { | |
2795 | WARN(r, "recovery from shadow isn't completed\n"); | |
2796 | break; | |
2797 | } | |
2798 | } | |
2799 | ||
2800 | dma_fence_put(fence); | |
2801 | fence = next; | |
2802 | } | |
2803 | mutex_unlock(&adev->shadow_list_lock); | |
2804 | ||
2805 | if (fence) { | |
2806 | r = dma_fence_wait(fence, false); | |
2807 | if (r) | |
2808 | WARN(r, "recovery from shadow isn't completed\n"); | |
2809 | } | |
2810 | dma_fence_put(fence); | |
2811 | ||
65781c78 ML |
2812 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { |
2813 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2814 | if (!ring || !ring->sched.thread) |
2815 | continue; | |
2816 | ||
65781c78 ML |
2817 | if (job && j != i) { |
2818 | kthread_unpark(ring->sched.thread); | |
2819 | continue; | |
2820 | } | |
2821 | ||
a90ad3c2 ML |
2822 | amd_sched_job_recovery(&ring->sched); |
2823 | kthread_unpark(ring->sched.thread); | |
2824 | } | |
2825 | ||
2826 | drm_helper_resume_force_mode(adev->ddev); | |
65781c78 | 2827 | give_up_reset: |
a90ad3c2 ML |
2828 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); |
2829 | if (r) { | |
2830 | /* bad news, how to tell it to userspace ? */ | |
2831 | dev_info(adev->dev, "GPU reset failed\n"); | |
65781c78 ML |
2832 | } else { |
2833 | dev_info(adev->dev, "GPU reset successed!\n"); | |
a90ad3c2 ML |
2834 | } |
2835 | ||
1fb37a3d | 2836 | adev->gfx.in_reset = false; |
147b5983 | 2837 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2838 | return r; |
2839 | } | |
2840 | ||
d38ceaf9 AD |
2841 | /** |
2842 | * amdgpu_gpu_reset - reset the asic | |
2843 | * | |
2844 | * @adev: amdgpu device pointer | |
2845 | * | |
2846 | * Attempt the reset the GPU if it has hung (all asics). | |
2847 | * Returns 0 for success or an error on failure. | |
2848 | */ | |
2849 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2850 | { | |
d38ceaf9 AD |
2851 | int i, r; |
2852 | int resched; | |
0c49e0b8 | 2853 | bool need_full_reset, vram_lost = false; |
fb140b29 | 2854 | |
63fbf42f CZ |
2855 | if (!amdgpu_check_soft_reset(adev)) { |
2856 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2857 | return 0; | |
2858 | } | |
d38ceaf9 | 2859 | |
d94aed5a | 2860 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2861 | |
a3c47d6b CZ |
2862 | /* block TTM */ |
2863 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2864 | ||
0875dc9e CZ |
2865 | /* block scheduler */ |
2866 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2867 | struct amdgpu_ring *ring = adev->rings[i]; | |
2868 | ||
51687759 | 2869 | if (!ring || !ring->sched.thread) |
0875dc9e CZ |
2870 | continue; |
2871 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2872 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2873 | } |
2200edac CZ |
2874 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2875 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2876 | |
35d782fe | 2877 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2878 | |
35d782fe CZ |
2879 | if (!need_full_reset) { |
2880 | amdgpu_pre_soft_reset(adev); | |
2881 | r = amdgpu_soft_reset(adev); | |
2882 | amdgpu_post_soft_reset(adev); | |
2883 | if (r || amdgpu_check_soft_reset(adev)) { | |
2884 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2885 | need_full_reset = true; | |
2886 | } | |
f1aa7e08 CZ |
2887 | } |
2888 | ||
35d782fe | 2889 | if (need_full_reset) { |
35d782fe | 2890 | r = amdgpu_suspend(adev); |
bfa99269 | 2891 | |
35d782fe | 2892 | retry: |
d05da0e2 | 2893 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2894 | r = amdgpu_asic_reset(adev); |
d05da0e2 | 2895 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2896 | /* post card */ |
2897 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2898 | ||
2899 | if (!r) { | |
2900 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
fcf0649f CZ |
2901 | r = amdgpu_resume_phase1(adev); |
2902 | if (r) | |
2903 | goto out; | |
0c49e0b8 | 2904 | vram_lost = amdgpu_check_vram_lost(adev); |
f1892138 | 2905 | if (vram_lost) { |
0c49e0b8 | 2906 | DRM_ERROR("VRAM is lost!\n"); |
f1892138 CZ |
2907 | atomic_inc(&adev->vram_lost_counter); |
2908 | } | |
fcf0649f CZ |
2909 | r = amdgpu_ttm_recover_gart(adev); |
2910 | if (r) | |
2911 | goto out; | |
2912 | r = amdgpu_resume_phase2(adev); | |
2913 | if (r) | |
2914 | goto out; | |
0c49e0b8 CZ |
2915 | if (vram_lost) |
2916 | amdgpu_fill_reset_magic(adev); | |
35d782fe | 2917 | } |
d38ceaf9 | 2918 | } |
fcf0649f | 2919 | out: |
d38ceaf9 | 2920 | if (!r) { |
e72cfd58 | 2921 | amdgpu_irq_gpu_reset_resume_helper(adev); |
1f465087 CZ |
2922 | r = amdgpu_ib_ring_tests(adev); |
2923 | if (r) { | |
2924 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2925 | r = amdgpu_suspend(adev); |
53cdccd5 | 2926 | need_full_reset = true; |
40019dc4 | 2927 | goto retry; |
1f465087 | 2928 | } |
53cdccd5 CZ |
2929 | /** |
2930 | * recovery vm page tables, since we cannot depend on VRAM is | |
2931 | * consistent after gpu full reset. | |
2932 | */ | |
2933 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2934 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2935 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2936 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2937 | |
2938 | DRM_INFO("recover vram bo from shadow\n"); | |
2939 | mutex_lock(&adev->shadow_list_lock); | |
2940 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2941 | next = NULL; |
53cdccd5 CZ |
2942 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2943 | if (fence) { | |
f54d1867 | 2944 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2945 | if (r) { |
1d7b17b0 | 2946 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2947 | break; |
2948 | } | |
2949 | } | |
1f465087 | 2950 | |
f54d1867 | 2951 | dma_fence_put(fence); |
53cdccd5 CZ |
2952 | fence = next; |
2953 | } | |
2954 | mutex_unlock(&adev->shadow_list_lock); | |
2955 | if (fence) { | |
f54d1867 | 2956 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2957 | if (r) |
1d7b17b0 | 2958 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2959 | } |
f54d1867 | 2960 | dma_fence_put(fence); |
53cdccd5 | 2961 | } |
d38ceaf9 AD |
2962 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2963 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
2964 | |
2965 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 2966 | continue; |
53cdccd5 | 2967 | |
aa1c8900 | 2968 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2969 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2970 | } |
d38ceaf9 | 2971 | } else { |
2200edac | 2972 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
89041940 | 2973 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r); |
d38ceaf9 | 2974 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
51687759 | 2975 | if (adev->rings[i] && adev->rings[i]->sched.thread) { |
0875dc9e | 2976 | kthread_unpark(adev->rings[i]->sched.thread); |
0875dc9e | 2977 | } |
d38ceaf9 AD |
2978 | } |
2979 | } | |
2980 | ||
2981 | drm_helper_resume_force_mode(adev->ddev); | |
2982 | ||
2983 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
89041940 | 2984 | if (r) { |
d38ceaf9 AD |
2985 | /* bad news, how to tell it to userspace ? */ |
2986 | dev_info(adev->dev, "GPU reset failed\n"); | |
89041940 GW |
2987 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
2988 | } | |
2989 | else { | |
6643be65 | 2990 | dev_info(adev->dev, "GPU reset successed!\n"); |
89041940 | 2991 | } |
d38ceaf9 | 2992 | |
89041940 | 2993 | amdgpu_vf_error_trans_all(adev); |
d38ceaf9 AD |
2994 | return r; |
2995 | } | |
2996 | ||
d0dd7f0c AD |
2997 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2998 | { | |
2999 | u32 mask; | |
3000 | int ret; | |
3001 | ||
cd474ba0 AD |
3002 | if (amdgpu_pcie_gen_cap) |
3003 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3004 | |
cd474ba0 AD |
3005 | if (amdgpu_pcie_lane_cap) |
3006 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3007 | |
cd474ba0 AD |
3008 | /* covers APUs as well */ |
3009 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3010 | if (adev->pm.pcie_gen_mask == 0) | |
3011 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3012 | if (adev->pm.pcie_mlw_mask == 0) | |
3013 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3014 | return; |
cd474ba0 | 3015 | } |
d0dd7f0c | 3016 | |
cd474ba0 AD |
3017 | if (adev->pm.pcie_gen_mask == 0) { |
3018 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
3019 | if (!ret) { | |
3020 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3021 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3022 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3023 | ||
3024 | if (mask & DRM_PCIE_SPEED_25) | |
3025 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3026 | if (mask & DRM_PCIE_SPEED_50) | |
3027 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3028 | if (mask & DRM_PCIE_SPEED_80) | |
3029 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3030 | } else { | |
3031 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3032 | } | |
3033 | } | |
3034 | if (adev->pm.pcie_mlw_mask == 0) { | |
3035 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3036 | if (!ret) { | |
3037 | switch (mask) { | |
3038 | case 32: | |
3039 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3040 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3041 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3042 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3043 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3044 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3045 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3046 | break; | |
3047 | case 16: | |
3048 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3049 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3050 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3051 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3052 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3053 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3054 | break; | |
3055 | case 12: | |
3056 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3057 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3058 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3059 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3060 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3061 | break; | |
3062 | case 8: | |
3063 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3064 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3065 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3066 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3067 | break; | |
3068 | case 4: | |
3069 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3070 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3071 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3072 | break; | |
3073 | case 2: | |
3074 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3075 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3076 | break; | |
3077 | case 1: | |
3078 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3079 | break; | |
3080 | default: | |
3081 | break; | |
3082 | } | |
3083 | } else { | |
3084 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3085 | } |
3086 | } | |
3087 | } | |
d38ceaf9 AD |
3088 | |
3089 | /* | |
3090 | * Debugfs | |
3091 | */ | |
3092 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3093 | const struct drm_info_list *files, |
d38ceaf9 AD |
3094 | unsigned nfiles) |
3095 | { | |
3096 | unsigned i; | |
3097 | ||
3098 | for (i = 0; i < adev->debugfs_count; i++) { | |
3099 | if (adev->debugfs[i].files == files) { | |
3100 | /* Already registered */ | |
3101 | return 0; | |
3102 | } | |
3103 | } | |
3104 | ||
3105 | i = adev->debugfs_count + 1; | |
3106 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3107 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3108 | DRM_ERROR("Report so we increase " | |
3109 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3110 | return -EINVAL; | |
3111 | } | |
3112 | adev->debugfs[adev->debugfs_count].files = files; | |
3113 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3114 | adev->debugfs_count = i; | |
3115 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3116 | drm_debugfs_create_files(files, nfiles, |
3117 | adev->ddev->primary->debugfs_root, | |
3118 | adev->ddev->primary); | |
3119 | #endif | |
3120 | return 0; | |
3121 | } | |
3122 | ||
d38ceaf9 AD |
3123 | #if defined(CONFIG_DEBUG_FS) |
3124 | ||
3125 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3126 | size_t size, loff_t *pos) | |
3127 | { | |
45063097 | 3128 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3129 | ssize_t result = 0; |
3130 | int r; | |
bd12267d | 3131 | bool pm_pg_lock, use_bank; |
56628159 | 3132 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3133 | |
3134 | if (size & 0x3 || *pos & 0x3) | |
3135 | return -EINVAL; | |
3136 | ||
bd12267d TSD |
3137 | /* are we reading registers for which a PG lock is necessary? */ |
3138 | pm_pg_lock = (*pos >> 23) & 1; | |
3139 | ||
56628159 TSD |
3140 | if (*pos & (1ULL << 62)) { |
3141 | se_bank = (*pos >> 24) & 0x3FF; | |
3142 | sh_bank = (*pos >> 34) & 0x3FF; | |
3143 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
3144 | |
3145 | if (se_bank == 0x3FF) | |
3146 | se_bank = 0xFFFFFFFF; | |
3147 | if (sh_bank == 0x3FF) | |
3148 | sh_bank = 0xFFFFFFFF; | |
3149 | if (instance_bank == 0x3FF) | |
3150 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3151 | use_bank = 1; |
56628159 TSD |
3152 | } else { |
3153 | use_bank = 0; | |
3154 | } | |
3155 | ||
801a6aa9 | 3156 | *pos &= (1UL << 22) - 1; |
bd12267d | 3157 | |
56628159 | 3158 | if (use_bank) { |
32977f93 TSD |
3159 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3160 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3161 | return -EINVAL; |
3162 | mutex_lock(&adev->grbm_idx_mutex); | |
3163 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3164 | sh_bank, instance_bank); | |
3165 | } | |
3166 | ||
bd12267d TSD |
3167 | if (pm_pg_lock) |
3168 | mutex_lock(&adev->pm.mutex); | |
3169 | ||
d38ceaf9 AD |
3170 | while (size) { |
3171 | uint32_t value; | |
3172 | ||
3173 | if (*pos > adev->rmmio_size) | |
56628159 | 3174 | goto end; |
d38ceaf9 AD |
3175 | |
3176 | value = RREG32(*pos >> 2); | |
3177 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3178 | if (r) { |
3179 | result = r; | |
3180 | goto end; | |
3181 | } | |
d38ceaf9 AD |
3182 | |
3183 | result += 4; | |
3184 | buf += 4; | |
3185 | *pos += 4; | |
3186 | size -= 4; | |
3187 | } | |
3188 | ||
56628159 TSD |
3189 | end: |
3190 | if (use_bank) { | |
3191 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3192 | mutex_unlock(&adev->grbm_idx_mutex); | |
3193 | } | |
3194 | ||
bd12267d TSD |
3195 | if (pm_pg_lock) |
3196 | mutex_unlock(&adev->pm.mutex); | |
3197 | ||
d38ceaf9 AD |
3198 | return result; |
3199 | } | |
3200 | ||
3201 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3202 | size_t size, loff_t *pos) | |
3203 | { | |
45063097 | 3204 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3205 | ssize_t result = 0; |
3206 | int r; | |
394fdde2 TSD |
3207 | bool pm_pg_lock, use_bank; |
3208 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3209 | |
3210 | if (size & 0x3 || *pos & 0x3) | |
3211 | return -EINVAL; | |
3212 | ||
394fdde2 TSD |
3213 | /* are we reading registers for which a PG lock is necessary? */ |
3214 | pm_pg_lock = (*pos >> 23) & 1; | |
3215 | ||
3216 | if (*pos & (1ULL << 62)) { | |
3217 | se_bank = (*pos >> 24) & 0x3FF; | |
3218 | sh_bank = (*pos >> 34) & 0x3FF; | |
3219 | instance_bank = (*pos >> 44) & 0x3FF; | |
3220 | ||
3221 | if (se_bank == 0x3FF) | |
3222 | se_bank = 0xFFFFFFFF; | |
3223 | if (sh_bank == 0x3FF) | |
3224 | sh_bank = 0xFFFFFFFF; | |
3225 | if (instance_bank == 0x3FF) | |
3226 | instance_bank = 0xFFFFFFFF; | |
3227 | use_bank = 1; | |
3228 | } else { | |
3229 | use_bank = 0; | |
3230 | } | |
3231 | ||
801a6aa9 | 3232 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3233 | |
3234 | if (use_bank) { | |
3235 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3236 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3237 | return -EINVAL; | |
3238 | mutex_lock(&adev->grbm_idx_mutex); | |
3239 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3240 | sh_bank, instance_bank); | |
3241 | } | |
3242 | ||
3243 | if (pm_pg_lock) | |
3244 | mutex_lock(&adev->pm.mutex); | |
3245 | ||
d38ceaf9 AD |
3246 | while (size) { |
3247 | uint32_t value; | |
3248 | ||
3249 | if (*pos > adev->rmmio_size) | |
3250 | return result; | |
3251 | ||
3252 | r = get_user(value, (uint32_t *)buf); | |
3253 | if (r) | |
3254 | return r; | |
3255 | ||
3256 | WREG32(*pos >> 2, value); | |
3257 | ||
3258 | result += 4; | |
3259 | buf += 4; | |
3260 | *pos += 4; | |
3261 | size -= 4; | |
3262 | } | |
3263 | ||
394fdde2 TSD |
3264 | if (use_bank) { |
3265 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3266 | mutex_unlock(&adev->grbm_idx_mutex); | |
3267 | } | |
3268 | ||
3269 | if (pm_pg_lock) | |
3270 | mutex_unlock(&adev->pm.mutex); | |
3271 | ||
d38ceaf9 AD |
3272 | return result; |
3273 | } | |
3274 | ||
adcec288 TSD |
3275 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3276 | size_t size, loff_t *pos) | |
3277 | { | |
45063097 | 3278 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3279 | ssize_t result = 0; |
3280 | int r; | |
3281 | ||
3282 | if (size & 0x3 || *pos & 0x3) | |
3283 | return -EINVAL; | |
3284 | ||
3285 | while (size) { | |
3286 | uint32_t value; | |
3287 | ||
3288 | value = RREG32_PCIE(*pos >> 2); | |
3289 | r = put_user(value, (uint32_t *)buf); | |
3290 | if (r) | |
3291 | return r; | |
3292 | ||
3293 | result += 4; | |
3294 | buf += 4; | |
3295 | *pos += 4; | |
3296 | size -= 4; | |
3297 | } | |
3298 | ||
3299 | return result; | |
3300 | } | |
3301 | ||
3302 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3303 | size_t size, loff_t *pos) | |
3304 | { | |
45063097 | 3305 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3306 | ssize_t result = 0; |
3307 | int r; | |
3308 | ||
3309 | if (size & 0x3 || *pos & 0x3) | |
3310 | return -EINVAL; | |
3311 | ||
3312 | while (size) { | |
3313 | uint32_t value; | |
3314 | ||
3315 | r = get_user(value, (uint32_t *)buf); | |
3316 | if (r) | |
3317 | return r; | |
3318 | ||
3319 | WREG32_PCIE(*pos >> 2, value); | |
3320 | ||
3321 | result += 4; | |
3322 | buf += 4; | |
3323 | *pos += 4; | |
3324 | size -= 4; | |
3325 | } | |
3326 | ||
3327 | return result; | |
3328 | } | |
3329 | ||
3330 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3331 | size_t size, loff_t *pos) | |
3332 | { | |
45063097 | 3333 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3334 | ssize_t result = 0; |
3335 | int r; | |
3336 | ||
3337 | if (size & 0x3 || *pos & 0x3) | |
3338 | return -EINVAL; | |
3339 | ||
3340 | while (size) { | |
3341 | uint32_t value; | |
3342 | ||
3343 | value = RREG32_DIDT(*pos >> 2); | |
3344 | r = put_user(value, (uint32_t *)buf); | |
3345 | if (r) | |
3346 | return r; | |
3347 | ||
3348 | result += 4; | |
3349 | buf += 4; | |
3350 | *pos += 4; | |
3351 | size -= 4; | |
3352 | } | |
3353 | ||
3354 | return result; | |
3355 | } | |
3356 | ||
3357 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3358 | size_t size, loff_t *pos) | |
3359 | { | |
45063097 | 3360 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3361 | ssize_t result = 0; |
3362 | int r; | |
3363 | ||
3364 | if (size & 0x3 || *pos & 0x3) | |
3365 | return -EINVAL; | |
3366 | ||
3367 | while (size) { | |
3368 | uint32_t value; | |
3369 | ||
3370 | r = get_user(value, (uint32_t *)buf); | |
3371 | if (r) | |
3372 | return r; | |
3373 | ||
3374 | WREG32_DIDT(*pos >> 2, value); | |
3375 | ||
3376 | result += 4; | |
3377 | buf += 4; | |
3378 | *pos += 4; | |
3379 | size -= 4; | |
3380 | } | |
3381 | ||
3382 | return result; | |
3383 | } | |
3384 | ||
3385 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3386 | size_t size, loff_t *pos) | |
3387 | { | |
45063097 | 3388 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3389 | ssize_t result = 0; |
3390 | int r; | |
3391 | ||
3392 | if (size & 0x3 || *pos & 0x3) | |
3393 | return -EINVAL; | |
3394 | ||
3395 | while (size) { | |
3396 | uint32_t value; | |
3397 | ||
6fc0deaf | 3398 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3399 | r = put_user(value, (uint32_t *)buf); |
3400 | if (r) | |
3401 | return r; | |
3402 | ||
3403 | result += 4; | |
3404 | buf += 4; | |
3405 | *pos += 4; | |
3406 | size -= 4; | |
3407 | } | |
3408 | ||
3409 | return result; | |
3410 | } | |
3411 | ||
3412 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3413 | size_t size, loff_t *pos) | |
3414 | { | |
45063097 | 3415 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3416 | ssize_t result = 0; |
3417 | int r; | |
3418 | ||
3419 | if (size & 0x3 || *pos & 0x3) | |
3420 | return -EINVAL; | |
3421 | ||
3422 | while (size) { | |
3423 | uint32_t value; | |
3424 | ||
3425 | r = get_user(value, (uint32_t *)buf); | |
3426 | if (r) | |
3427 | return r; | |
3428 | ||
6fc0deaf | 3429 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3430 | |
3431 | result += 4; | |
3432 | buf += 4; | |
3433 | *pos += 4; | |
3434 | size -= 4; | |
3435 | } | |
3436 | ||
3437 | return result; | |
3438 | } | |
3439 | ||
1e051413 TSD |
3440 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3441 | size_t size, loff_t *pos) | |
3442 | { | |
45063097 | 3443 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3444 | ssize_t result = 0; |
3445 | int r; | |
3446 | uint32_t *config, no_regs = 0; | |
3447 | ||
3448 | if (size & 0x3 || *pos & 0x3) | |
3449 | return -EINVAL; | |
3450 | ||
ecab7668 | 3451 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3452 | if (!config) |
3453 | return -ENOMEM; | |
3454 | ||
3455 | /* version, increment each time something is added */ | |
9a999359 | 3456 | config[no_regs++] = 3; |
1e051413 TSD |
3457 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3458 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3459 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3460 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3461 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3462 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3463 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3464 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3465 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3466 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3467 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3468 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3469 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3470 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3471 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3472 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3473 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3474 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3475 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3476 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3477 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3478 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3479 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3480 | ||
89a8f309 TSD |
3481 | /* rev==1 */ |
3482 | config[no_regs++] = adev->rev_id; | |
3483 | config[no_regs++] = adev->pg_flags; | |
3484 | config[no_regs++] = adev->cg_flags; | |
3485 | ||
e9f11dc8 TSD |
3486 | /* rev==2 */ |
3487 | config[no_regs++] = adev->family; | |
3488 | config[no_regs++] = adev->external_rev_id; | |
3489 | ||
9a999359 TSD |
3490 | /* rev==3 */ |
3491 | config[no_regs++] = adev->pdev->device; | |
3492 | config[no_regs++] = adev->pdev->revision; | |
3493 | config[no_regs++] = adev->pdev->subsystem_device; | |
3494 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3495 | ||
1e051413 TSD |
3496 | while (size && (*pos < no_regs * 4)) { |
3497 | uint32_t value; | |
3498 | ||
3499 | value = config[*pos >> 2]; | |
3500 | r = put_user(value, (uint32_t *)buf); | |
3501 | if (r) { | |
3502 | kfree(config); | |
3503 | return r; | |
3504 | } | |
3505 | ||
3506 | result += 4; | |
3507 | buf += 4; | |
3508 | *pos += 4; | |
3509 | size -= 4; | |
3510 | } | |
3511 | ||
3512 | kfree(config); | |
3513 | return result; | |
3514 | } | |
3515 | ||
f2cdaf20 TSD |
3516 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3517 | size_t size, loff_t *pos) | |
3518 | { | |
45063097 | 3519 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3520 | int idx, x, outsize, r, valuesize; |
3521 | uint32_t values[16]; | |
f2cdaf20 | 3522 | |
9f8df7d7 | 3523 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3524 | return -EINVAL; |
3525 | ||
3cbc614f SP |
3526 | if (amdgpu_dpm == 0) |
3527 | return -EINVAL; | |
3528 | ||
f2cdaf20 TSD |
3529 | /* convert offset to sensor number */ |
3530 | idx = *pos >> 2; | |
3531 | ||
9f8df7d7 | 3532 | valuesize = sizeof(values); |
f2cdaf20 | 3533 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3534 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3535 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3536 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3537 | &valuesize); | |
f2cdaf20 TSD |
3538 | else |
3539 | return -EINVAL; | |
3540 | ||
9f8df7d7 TSD |
3541 | if (size > valuesize) |
3542 | return -EINVAL; | |
3543 | ||
3544 | outsize = 0; | |
3545 | x = 0; | |
3546 | if (!r) { | |
3547 | while (size) { | |
3548 | r = put_user(values[x++], (int32_t *)buf); | |
3549 | buf += 4; | |
3550 | size -= 4; | |
3551 | outsize += 4; | |
3552 | } | |
3553 | } | |
f2cdaf20 | 3554 | |
9f8df7d7 | 3555 | return !r ? outsize : r; |
f2cdaf20 | 3556 | } |
1e051413 | 3557 | |
273d7aa1 TSD |
3558 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3559 | size_t size, loff_t *pos) | |
3560 | { | |
3561 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3562 | int r, x; | |
3563 | ssize_t result=0; | |
472259f0 | 3564 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3565 | |
3566 | if (size & 3 || *pos & 3) | |
3567 | return -EINVAL; | |
3568 | ||
3569 | /* decode offset */ | |
3570 | offset = (*pos & 0x7F); | |
3571 | se = ((*pos >> 7) & 0xFF); | |
3572 | sh = ((*pos >> 15) & 0xFF); | |
3573 | cu = ((*pos >> 23) & 0xFF); | |
3574 | wave = ((*pos >> 31) & 0xFF); | |
3575 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3576 | |
3577 | /* switch to the specific se/sh/cu */ | |
3578 | mutex_lock(&adev->grbm_idx_mutex); | |
3579 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3580 | ||
3581 | x = 0; | |
472259f0 TSD |
3582 | if (adev->gfx.funcs->read_wave_data) |
3583 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3584 | |
3585 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3586 | mutex_unlock(&adev->grbm_idx_mutex); | |
3587 | ||
5ecfb3b8 TSD |
3588 | if (!x) |
3589 | return -EINVAL; | |
3590 | ||
472259f0 | 3591 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3592 | uint32_t value; |
3593 | ||
472259f0 | 3594 | value = data[offset >> 2]; |
273d7aa1 TSD |
3595 | r = put_user(value, (uint32_t *)buf); |
3596 | if (r) | |
3597 | return r; | |
3598 | ||
3599 | result += 4; | |
3600 | buf += 4; | |
472259f0 | 3601 | offset += 4; |
273d7aa1 TSD |
3602 | size -= 4; |
3603 | } | |
3604 | ||
3605 | return result; | |
3606 | } | |
3607 | ||
c5a60ce8 TSD |
3608 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3609 | size_t size, loff_t *pos) | |
3610 | { | |
3611 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3612 | int r; | |
3613 | ssize_t result = 0; | |
3614 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3615 | ||
3616 | if (size & 3 || *pos & 3) | |
3617 | return -EINVAL; | |
3618 | ||
3619 | /* decode offset */ | |
3620 | offset = (*pos & 0xFFF); /* in dwords */ | |
3621 | se = ((*pos >> 12) & 0xFF); | |
3622 | sh = ((*pos >> 20) & 0xFF); | |
3623 | cu = ((*pos >> 28) & 0xFF); | |
3624 | wave = ((*pos >> 36) & 0xFF); | |
3625 | simd = ((*pos >> 44) & 0xFF); | |
3626 | thread = ((*pos >> 52) & 0xFF); | |
3627 | bank = ((*pos >> 60) & 1); | |
3628 | ||
3629 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3630 | if (!data) | |
3631 | return -ENOMEM; | |
3632 | ||
3633 | /* switch to the specific se/sh/cu */ | |
3634 | mutex_lock(&adev->grbm_idx_mutex); | |
3635 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3636 | ||
3637 | if (bank == 0) { | |
3638 | if (adev->gfx.funcs->read_wave_vgprs) | |
3639 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3640 | } else { | |
3641 | if (adev->gfx.funcs->read_wave_sgprs) | |
3642 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3643 | } | |
3644 | ||
3645 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3646 | mutex_unlock(&adev->grbm_idx_mutex); | |
3647 | ||
3648 | while (size) { | |
3649 | uint32_t value; | |
3650 | ||
3651 | value = data[offset++]; | |
3652 | r = put_user(value, (uint32_t *)buf); | |
3653 | if (r) { | |
3654 | result = r; | |
3655 | goto err; | |
3656 | } | |
3657 | ||
3658 | result += 4; | |
3659 | buf += 4; | |
3660 | size -= 4; | |
3661 | } | |
3662 | ||
3663 | err: | |
3664 | kfree(data); | |
3665 | return result; | |
3666 | } | |
3667 | ||
d38ceaf9 AD |
3668 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3669 | .owner = THIS_MODULE, | |
3670 | .read = amdgpu_debugfs_regs_read, | |
3671 | .write = amdgpu_debugfs_regs_write, | |
3672 | .llseek = default_llseek | |
3673 | }; | |
adcec288 TSD |
3674 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3675 | .owner = THIS_MODULE, | |
3676 | .read = amdgpu_debugfs_regs_didt_read, | |
3677 | .write = amdgpu_debugfs_regs_didt_write, | |
3678 | .llseek = default_llseek | |
3679 | }; | |
3680 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3681 | .owner = THIS_MODULE, | |
3682 | .read = amdgpu_debugfs_regs_pcie_read, | |
3683 | .write = amdgpu_debugfs_regs_pcie_write, | |
3684 | .llseek = default_llseek | |
3685 | }; | |
3686 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3687 | .owner = THIS_MODULE, | |
3688 | .read = amdgpu_debugfs_regs_smc_read, | |
3689 | .write = amdgpu_debugfs_regs_smc_write, | |
3690 | .llseek = default_llseek | |
3691 | }; | |
3692 | ||
1e051413 TSD |
3693 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3694 | .owner = THIS_MODULE, | |
3695 | .read = amdgpu_debugfs_gca_config_read, | |
3696 | .llseek = default_llseek | |
3697 | }; | |
3698 | ||
f2cdaf20 TSD |
3699 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3700 | .owner = THIS_MODULE, | |
3701 | .read = amdgpu_debugfs_sensor_read, | |
3702 | .llseek = default_llseek | |
3703 | }; | |
3704 | ||
273d7aa1 TSD |
3705 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3706 | .owner = THIS_MODULE, | |
3707 | .read = amdgpu_debugfs_wave_read, | |
3708 | .llseek = default_llseek | |
3709 | }; | |
c5a60ce8 TSD |
3710 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3711 | .owner = THIS_MODULE, | |
3712 | .read = amdgpu_debugfs_gpr_read, | |
3713 | .llseek = default_llseek | |
3714 | }; | |
273d7aa1 | 3715 | |
adcec288 TSD |
3716 | static const struct file_operations *debugfs_regs[] = { |
3717 | &amdgpu_debugfs_regs_fops, | |
3718 | &amdgpu_debugfs_regs_didt_fops, | |
3719 | &amdgpu_debugfs_regs_pcie_fops, | |
3720 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3721 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3722 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3723 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3724 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3725 | }; |
3726 | ||
3727 | static const char *debugfs_regs_names[] = { | |
3728 | "amdgpu_regs", | |
3729 | "amdgpu_regs_didt", | |
3730 | "amdgpu_regs_pcie", | |
3731 | "amdgpu_regs_smc", | |
1e051413 | 3732 | "amdgpu_gca_config", |
f2cdaf20 | 3733 | "amdgpu_sensors", |
273d7aa1 | 3734 | "amdgpu_wave", |
c5a60ce8 | 3735 | "amdgpu_gpr", |
adcec288 | 3736 | }; |
d38ceaf9 AD |
3737 | |
3738 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3739 | { | |
3740 | struct drm_minor *minor = adev->ddev->primary; | |
3741 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3742 | unsigned i, j; |
3743 | ||
3744 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3745 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3746 | S_IFREG | S_IRUGO, root, | |
3747 | adev, debugfs_regs[i]); | |
3748 | if (IS_ERR(ent)) { | |
3749 | for (j = 0; j < i; j++) { | |
3750 | debugfs_remove(adev->debugfs_regs[i]); | |
3751 | adev->debugfs_regs[i] = NULL; | |
3752 | } | |
3753 | return PTR_ERR(ent); | |
3754 | } | |
d38ceaf9 | 3755 | |
adcec288 TSD |
3756 | if (!i) |
3757 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3758 | adev->debugfs_regs[i] = ent; | |
3759 | } | |
d38ceaf9 AD |
3760 | |
3761 | return 0; | |
3762 | } | |
3763 | ||
3764 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3765 | { | |
adcec288 TSD |
3766 | unsigned i; |
3767 | ||
3768 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3769 | if (adev->debugfs_regs[i]) { | |
3770 | debugfs_remove(adev->debugfs_regs[i]); | |
3771 | adev->debugfs_regs[i] = NULL; | |
3772 | } | |
3773 | } | |
d38ceaf9 AD |
3774 | } |
3775 | ||
4f0955fc HR |
3776 | static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) |
3777 | { | |
3778 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3779 | struct drm_device *dev = node->minor->dev; | |
3780 | struct amdgpu_device *adev = dev->dev_private; | |
3781 | int r = 0, i; | |
3782 | ||
3783 | /* hold on the scheduler */ | |
3784 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3785 | struct amdgpu_ring *ring = adev->rings[i]; | |
3786 | ||
3787 | if (!ring || !ring->sched.thread) | |
3788 | continue; | |
3789 | kthread_park(ring->sched.thread); | |
3790 | } | |
3791 | ||
3792 | seq_printf(m, "run ib test:\n"); | |
3793 | r = amdgpu_ib_ring_tests(adev); | |
3794 | if (r) | |
3795 | seq_printf(m, "ib ring tests failed (%d).\n", r); | |
3796 | else | |
3797 | seq_printf(m, "ib ring tests passed.\n"); | |
3798 | ||
3799 | /* go on the scheduler */ | |
3800 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3801 | struct amdgpu_ring *ring = adev->rings[i]; | |
3802 | ||
3803 | if (!ring || !ring->sched.thread) | |
3804 | continue; | |
3805 | kthread_unpark(ring->sched.thread); | |
3806 | } | |
3807 | ||
3808 | return 0; | |
3809 | } | |
3810 | ||
3811 | static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { | |
3812 | {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} | |
3813 | }; | |
3814 | ||
3815 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) | |
3816 | { | |
3817 | return amdgpu_debugfs_add_files(adev, | |
3818 | amdgpu_debugfs_test_ib_ring_list, 1); | |
3819 | } | |
3820 | ||
d38ceaf9 AD |
3821 | int amdgpu_debugfs_init(struct drm_minor *minor) |
3822 | { | |
3823 | return 0; | |
3824 | } | |
7cebc728 | 3825 | #else |
27bad5b9 | 3826 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) |
4f0955fc HR |
3827 | { |
3828 | return 0; | |
3829 | } | |
7cebc728 AK |
3830 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) |
3831 | { | |
3832 | return 0; | |
3833 | } | |
3834 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3835 | #endif |