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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
fdf2f6c5 | 33 | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 35 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
36 | #include <drm/amdgpu_drm.h> |
37 | #include <linux/vgaarb.h> | |
38 | #include <linux/vga_switcheroo.h> | |
39 | #include <linux/efi.h> | |
40 | #include "amdgpu.h" | |
f4b373f4 | 41 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
42 | #include "amdgpu_i2c.h" |
43 | #include "atom.h" | |
44 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 45 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 46 | #include "amd_pcie.h" |
33f34802 KW |
47 | #ifdef CONFIG_DRM_AMDGPU_SI |
48 | #include "si.h" | |
49 | #endif | |
a2e73f56 AD |
50 | #ifdef CONFIG_DRM_AMDGPU_CIK |
51 | #include "cik.h" | |
52 | #endif | |
aaa36a97 | 53 | #include "vi.h" |
460826e6 | 54 | #include "soc15.h" |
0a5b8c7b | 55 | #include "nv.h" |
d38ceaf9 | 56 | #include "bif/bif_4_1_d.h" |
9accf2fd | 57 | #include <linux/pci.h> |
bec86378 | 58 | #include <linux/firmware.h> |
89041940 | 59 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 60 | |
ba997709 | 61 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 62 | #include "amdgpu_pm.h" |
d38ceaf9 | 63 | |
5183411b | 64 | #include "amdgpu_xgmi.h" |
c030f2e4 | 65 | #include "amdgpu_ras.h" |
9c7c85f7 | 66 | #include "amdgpu_pmu.h" |
5183411b | 67 | |
d5ea093e AG |
68 | #include <linux/suspend.h> |
69 | ||
e2a75f88 | 70 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 71 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 72 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 73 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 74 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 75 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 76 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 77 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 78 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 79 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
e2a75f88 | 80 | |
2dc80b00 S |
81 | #define AMDGPU_RESUME_MS 2000 |
82 | ||
050091ab | 83 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
84 | "TAHITI", |
85 | "PITCAIRN", | |
86 | "VERDE", | |
87 | "OLAND", | |
88 | "HAINAN", | |
d38ceaf9 AD |
89 | "BONAIRE", |
90 | "KAVERI", | |
91 | "KABINI", | |
92 | "HAWAII", | |
93 | "MULLINS", | |
94 | "TOPAZ", | |
95 | "TONGA", | |
48299f95 | 96 | "FIJI", |
d38ceaf9 | 97 | "CARRIZO", |
139f4917 | 98 | "STONEY", |
2cc0c0b5 FC |
99 | "POLARIS10", |
100 | "POLARIS11", | |
c4642a47 | 101 | "POLARIS12", |
48ff108d | 102 | "VEGAM", |
d4196f01 | 103 | "VEGA10", |
8fab806a | 104 | "VEGA12", |
956fcddc | 105 | "VEGA20", |
2ca8a5d2 | 106 | "RAVEN", |
d6c3b24e | 107 | "ARCTURUS", |
1eee4228 | 108 | "RENOIR", |
852a6626 | 109 | "NAVI10", |
87dbad02 | 110 | "NAVI14", |
9802f5d7 | 111 | "NAVI12", |
d38ceaf9 AD |
112 | "LAST", |
113 | }; | |
114 | ||
dcea6e65 KR |
115 | /** |
116 | * DOC: pcie_replay_count | |
117 | * | |
118 | * The amdgpu driver provides a sysfs API for reporting the total number | |
119 | * of PCIe replays (NAKs) | |
120 | * The file pcie_replay_count is used for this and returns the total | |
121 | * number of replays as a sum of the NAKs generated and NAKs received | |
122 | */ | |
123 | ||
124 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
125 | struct device_attribute *attr, char *buf) | |
126 | { | |
127 | struct drm_device *ddev = dev_get_drvdata(dev); | |
128 | struct amdgpu_device *adev = ddev->dev_private; | |
129 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); | |
130 | ||
131 | return snprintf(buf, PAGE_SIZE, "%llu\n", cnt); | |
132 | } | |
133 | ||
134 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
135 | amdgpu_device_get_pcie_replay_count, NULL); | |
136 | ||
5494d864 AD |
137 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
138 | ||
e3ecdffa AD |
139 | /** |
140 | * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control | |
141 | * | |
142 | * @dev: drm_device pointer | |
143 | * | |
144 | * Returns true if the device is a dGPU with HG/PX power control, | |
145 | * otherwise return false. | |
146 | */ | |
d38ceaf9 AD |
147 | bool amdgpu_device_is_px(struct drm_device *dev) |
148 | { | |
149 | struct amdgpu_device *adev = dev->dev_private; | |
150 | ||
2f7d10b3 | 151 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
152 | return true; |
153 | return false; | |
154 | } | |
155 | ||
156 | /* | |
157 | * MMIO register access helper functions. | |
158 | */ | |
e3ecdffa AD |
159 | /** |
160 | * amdgpu_mm_rreg - read a memory mapped IO register | |
161 | * | |
162 | * @adev: amdgpu_device pointer | |
163 | * @reg: dword aligned register offset | |
164 | * @acc_flags: access flags which require special behavior | |
165 | * | |
166 | * Returns the 32 bit value from the offset specified. | |
167 | */ | |
d38ceaf9 | 168 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
15d72fd7 | 169 | uint32_t acc_flags) |
d38ceaf9 | 170 | { |
f4b373f4 TSD |
171 | uint32_t ret; |
172 | ||
43ca8efa | 173 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 174 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 175 | |
15d72fd7 | 176 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 177 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
178 | else { |
179 | unsigned long flags; | |
d38ceaf9 AD |
180 | |
181 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
182 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
183 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
184 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 185 | } |
f4b373f4 TSD |
186 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
187 | return ret; | |
d38ceaf9 AD |
188 | } |
189 | ||
421a2a30 ML |
190 | /* |
191 | * MMIO register read with bytes helper functions | |
192 | * @offset:bytes offset from MMIO start | |
193 | * | |
194 | */ | |
195 | ||
e3ecdffa AD |
196 | /** |
197 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
198 | * | |
199 | * @adev: amdgpu_device pointer | |
200 | * @offset: byte aligned register offset | |
201 | * | |
202 | * Returns the 8 bit value from the offset specified. | |
203 | */ | |
421a2a30 ML |
204 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
205 | if (offset < adev->rmmio_size) | |
206 | return (readb(adev->rmmio + offset)); | |
207 | BUG(); | |
208 | } | |
209 | ||
210 | /* | |
211 | * MMIO register write with bytes helper functions | |
212 | * @offset:bytes offset from MMIO start | |
213 | * @value: the value want to be written to the register | |
214 | * | |
215 | */ | |
e3ecdffa AD |
216 | /** |
217 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
218 | * | |
219 | * @adev: amdgpu_device pointer | |
220 | * @offset: byte aligned register offset | |
221 | * @value: 8 bit value to write | |
222 | * | |
223 | * Writes the value specified to the offset specified. | |
224 | */ | |
421a2a30 ML |
225 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
226 | if (offset < adev->rmmio_size) | |
227 | writeb(value, adev->rmmio + offset); | |
228 | else | |
229 | BUG(); | |
230 | } | |
231 | ||
e3ecdffa AD |
232 | /** |
233 | * amdgpu_mm_wreg - write to a memory mapped IO register | |
234 | * | |
235 | * @adev: amdgpu_device pointer | |
236 | * @reg: dword aligned register offset | |
237 | * @v: 32 bit value to write to the register | |
238 | * @acc_flags: access flags which require special behavior | |
239 | * | |
240 | * Writes the value specified to the offset specified. | |
241 | */ | |
d38ceaf9 | 242 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 243 | uint32_t acc_flags) |
d38ceaf9 | 244 | { |
f4b373f4 | 245 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 246 | |
47ed4e1c KW |
247 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
248 | adev->last_mm_index = v; | |
249 | } | |
250 | ||
43ca8efa | 251 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 252 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 253 | |
15d72fd7 | 254 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
255 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
256 | else { | |
257 | unsigned long flags; | |
258 | ||
259 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
260 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
261 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
262 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
263 | } | |
47ed4e1c KW |
264 | |
265 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
266 | udelay(500); | |
267 | } | |
d38ceaf9 AD |
268 | } |
269 | ||
e3ecdffa AD |
270 | /** |
271 | * amdgpu_io_rreg - read an IO register | |
272 | * | |
273 | * @adev: amdgpu_device pointer | |
274 | * @reg: dword aligned register offset | |
275 | * | |
276 | * Returns the 32 bit value from the offset specified. | |
277 | */ | |
d38ceaf9 AD |
278 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
279 | { | |
280 | if ((reg * 4) < adev->rio_mem_size) | |
281 | return ioread32(adev->rio_mem + (reg * 4)); | |
282 | else { | |
283 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
284 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
285 | } | |
286 | } | |
287 | ||
e3ecdffa AD |
288 | /** |
289 | * amdgpu_io_wreg - write to an IO register | |
290 | * | |
291 | * @adev: amdgpu_device pointer | |
292 | * @reg: dword aligned register offset | |
293 | * @v: 32 bit value to write to the register | |
294 | * | |
295 | * Writes the value specified to the offset specified. | |
296 | */ | |
d38ceaf9 AD |
297 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
298 | { | |
47ed4e1c KW |
299 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
300 | adev->last_mm_index = v; | |
301 | } | |
d38ceaf9 AD |
302 | |
303 | if ((reg * 4) < adev->rio_mem_size) | |
304 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
305 | else { | |
306 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
307 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
308 | } | |
47ed4e1c KW |
309 | |
310 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
311 | udelay(500); | |
312 | } | |
d38ceaf9 AD |
313 | } |
314 | ||
315 | /** | |
316 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
317 | * | |
318 | * @adev: amdgpu_device pointer | |
319 | * @index: doorbell index | |
320 | * | |
321 | * Returns the value in the doorbell aperture at the | |
322 | * requested doorbell index (CIK). | |
323 | */ | |
324 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
325 | { | |
326 | if (index < adev->doorbell.num_doorbells) { | |
327 | return readl(adev->doorbell.ptr + index); | |
328 | } else { | |
329 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
330 | return 0; | |
331 | } | |
332 | } | |
333 | ||
334 | /** | |
335 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
336 | * | |
337 | * @adev: amdgpu_device pointer | |
338 | * @index: doorbell index | |
339 | * @v: value to write | |
340 | * | |
341 | * Writes @v to the doorbell aperture at the | |
342 | * requested doorbell index (CIK). | |
343 | */ | |
344 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
345 | { | |
346 | if (index < adev->doorbell.num_doorbells) { | |
347 | writel(v, adev->doorbell.ptr + index); | |
348 | } else { | |
349 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
350 | } | |
351 | } | |
352 | ||
832be404 KW |
353 | /** |
354 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
355 | * | |
356 | * @adev: amdgpu_device pointer | |
357 | * @index: doorbell index | |
358 | * | |
359 | * Returns the value in the doorbell aperture at the | |
360 | * requested doorbell index (VEGA10+). | |
361 | */ | |
362 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
363 | { | |
364 | if (index < adev->doorbell.num_doorbells) { | |
365 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
366 | } else { | |
367 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
368 | return 0; | |
369 | } | |
370 | } | |
371 | ||
372 | /** | |
373 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
374 | * | |
375 | * @adev: amdgpu_device pointer | |
376 | * @index: doorbell index | |
377 | * @v: value to write | |
378 | * | |
379 | * Writes @v to the doorbell aperture at the | |
380 | * requested doorbell index (VEGA10+). | |
381 | */ | |
382 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
383 | { | |
384 | if (index < adev->doorbell.num_doorbells) { | |
385 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
386 | } else { | |
387 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
388 | } | |
389 | } | |
390 | ||
d38ceaf9 AD |
391 | /** |
392 | * amdgpu_invalid_rreg - dummy reg read function | |
393 | * | |
394 | * @adev: amdgpu device pointer | |
395 | * @reg: offset of register | |
396 | * | |
397 | * Dummy register read function. Used for register blocks | |
398 | * that certain asics don't have (all asics). | |
399 | * Returns the value in the register. | |
400 | */ | |
401 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
402 | { | |
403 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
404 | BUG(); | |
405 | return 0; | |
406 | } | |
407 | ||
408 | /** | |
409 | * amdgpu_invalid_wreg - dummy reg write function | |
410 | * | |
411 | * @adev: amdgpu device pointer | |
412 | * @reg: offset of register | |
413 | * @v: value to write to the register | |
414 | * | |
415 | * Dummy register read function. Used for register blocks | |
416 | * that certain asics don't have (all asics). | |
417 | */ | |
418 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
419 | { | |
420 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
421 | reg, v); | |
422 | BUG(); | |
423 | } | |
424 | ||
4fa1c6a6 TZ |
425 | /** |
426 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
427 | * | |
428 | * @adev: amdgpu device pointer | |
429 | * @reg: offset of register | |
430 | * | |
431 | * Dummy register read function. Used for register blocks | |
432 | * that certain asics don't have (all asics). | |
433 | * Returns the value in the register. | |
434 | */ | |
435 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
436 | { | |
437 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
438 | BUG(); | |
439 | return 0; | |
440 | } | |
441 | ||
442 | /** | |
443 | * amdgpu_invalid_wreg64 - dummy reg write function | |
444 | * | |
445 | * @adev: amdgpu device pointer | |
446 | * @reg: offset of register | |
447 | * @v: value to write to the register | |
448 | * | |
449 | * Dummy register read function. Used for register blocks | |
450 | * that certain asics don't have (all asics). | |
451 | */ | |
452 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
453 | { | |
454 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
455 | reg, v); | |
456 | BUG(); | |
457 | } | |
458 | ||
d38ceaf9 AD |
459 | /** |
460 | * amdgpu_block_invalid_rreg - dummy reg read function | |
461 | * | |
462 | * @adev: amdgpu device pointer | |
463 | * @block: offset of instance | |
464 | * @reg: offset of register | |
465 | * | |
466 | * Dummy register read function. Used for register blocks | |
467 | * that certain asics don't have (all asics). | |
468 | * Returns the value in the register. | |
469 | */ | |
470 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
471 | uint32_t block, uint32_t reg) | |
472 | { | |
473 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
474 | reg, block); | |
475 | BUG(); | |
476 | return 0; | |
477 | } | |
478 | ||
479 | /** | |
480 | * amdgpu_block_invalid_wreg - dummy reg write function | |
481 | * | |
482 | * @adev: amdgpu device pointer | |
483 | * @block: offset of instance | |
484 | * @reg: offset of register | |
485 | * @v: value to write to the register | |
486 | * | |
487 | * Dummy register read function. Used for register blocks | |
488 | * that certain asics don't have (all asics). | |
489 | */ | |
490 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
491 | uint32_t block, | |
492 | uint32_t reg, uint32_t v) | |
493 | { | |
494 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
495 | reg, block, v); | |
496 | BUG(); | |
497 | } | |
498 | ||
e3ecdffa AD |
499 | /** |
500 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
501 | * | |
502 | * @adev: amdgpu device pointer | |
503 | * | |
504 | * Allocates a scratch page of VRAM for use by various things in the | |
505 | * driver. | |
506 | */ | |
06ec9070 | 507 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 508 | { |
a4a02777 CK |
509 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
510 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
511 | &adev->vram_scratch.robj, | |
512 | &adev->vram_scratch.gpu_addr, | |
513 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
514 | } |
515 | ||
e3ecdffa AD |
516 | /** |
517 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
518 | * | |
519 | * @adev: amdgpu device pointer | |
520 | * | |
521 | * Frees the VRAM scratch page. | |
522 | */ | |
06ec9070 | 523 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 524 | { |
078af1a3 | 525 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
526 | } |
527 | ||
528 | /** | |
9c3f2b54 | 529 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
530 | * |
531 | * @adev: amdgpu_device pointer | |
532 | * @registers: pointer to the register array | |
533 | * @array_size: size of the register array | |
534 | * | |
535 | * Programs an array or registers with and and or masks. | |
536 | * This is a helper for setting golden registers. | |
537 | */ | |
9c3f2b54 AD |
538 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
539 | const u32 *registers, | |
540 | const u32 array_size) | |
d38ceaf9 AD |
541 | { |
542 | u32 tmp, reg, and_mask, or_mask; | |
543 | int i; | |
544 | ||
545 | if (array_size % 3) | |
546 | return; | |
547 | ||
548 | for (i = 0; i < array_size; i +=3) { | |
549 | reg = registers[i + 0]; | |
550 | and_mask = registers[i + 1]; | |
551 | or_mask = registers[i + 2]; | |
552 | ||
553 | if (and_mask == 0xffffffff) { | |
554 | tmp = or_mask; | |
555 | } else { | |
556 | tmp = RREG32(reg); | |
557 | tmp &= ~and_mask; | |
e0d07657 HZ |
558 | if (adev->family >= AMDGPU_FAMILY_AI) |
559 | tmp |= (or_mask & and_mask); | |
560 | else | |
561 | tmp |= or_mask; | |
d38ceaf9 AD |
562 | } |
563 | WREG32(reg, tmp); | |
564 | } | |
565 | } | |
566 | ||
e3ecdffa AD |
567 | /** |
568 | * amdgpu_device_pci_config_reset - reset the GPU | |
569 | * | |
570 | * @adev: amdgpu_device pointer | |
571 | * | |
572 | * Resets the GPU using the pci config reset sequence. | |
573 | * Only applicable to asics prior to vega10. | |
574 | */ | |
8111c387 | 575 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
576 | { |
577 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
578 | } | |
579 | ||
580 | /* | |
581 | * GPU doorbell aperture helpers function. | |
582 | */ | |
583 | /** | |
06ec9070 | 584 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
585 | * |
586 | * @adev: amdgpu_device pointer | |
587 | * | |
588 | * Init doorbell driver information (CIK) | |
589 | * Returns 0 on success, error on failure. | |
590 | */ | |
06ec9070 | 591 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 592 | { |
6585661d | 593 | |
705e519e CK |
594 | /* No doorbell on SI hardware generation */ |
595 | if (adev->asic_type < CHIP_BONAIRE) { | |
596 | adev->doorbell.base = 0; | |
597 | adev->doorbell.size = 0; | |
598 | adev->doorbell.num_doorbells = 0; | |
599 | adev->doorbell.ptr = NULL; | |
600 | return 0; | |
601 | } | |
602 | ||
d6895ad3 CK |
603 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
604 | return -EINVAL; | |
605 | ||
22357775 AD |
606 | amdgpu_asic_init_doorbell_index(adev); |
607 | ||
d38ceaf9 AD |
608 | /* doorbell bar mapping */ |
609 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
610 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
611 | ||
edf600da | 612 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 613 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
614 | if (adev->doorbell.num_doorbells == 0) |
615 | return -EINVAL; | |
616 | ||
ec3db8a6 | 617 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
618 | * paging queue doorbell use the second page. The |
619 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
620 | * doorbells are in the first page. So with paging queue enabled, | |
621 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
622 | */ |
623 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 624 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 625 | |
8972e5d2 CK |
626 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
627 | adev->doorbell.num_doorbells * | |
628 | sizeof(u32)); | |
629 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 630 | return -ENOMEM; |
d38ceaf9 AD |
631 | |
632 | return 0; | |
633 | } | |
634 | ||
635 | /** | |
06ec9070 | 636 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
637 | * |
638 | * @adev: amdgpu_device pointer | |
639 | * | |
640 | * Tear down doorbell driver information (CIK) | |
641 | */ | |
06ec9070 | 642 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
643 | { |
644 | iounmap(adev->doorbell.ptr); | |
645 | adev->doorbell.ptr = NULL; | |
646 | } | |
647 | ||
22cb0164 | 648 | |
d38ceaf9 AD |
649 | |
650 | /* | |
06ec9070 | 651 | * amdgpu_device_wb_*() |
455a7bc2 | 652 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 653 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
654 | */ |
655 | ||
656 | /** | |
06ec9070 | 657 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
658 | * |
659 | * @adev: amdgpu_device pointer | |
660 | * | |
661 | * Disables Writeback and frees the Writeback memory (all asics). | |
662 | * Used at driver shutdown. | |
663 | */ | |
06ec9070 | 664 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
665 | { |
666 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
667 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
668 | &adev->wb.gpu_addr, | |
669 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
670 | adev->wb.wb_obj = NULL; |
671 | } | |
672 | } | |
673 | ||
674 | /** | |
06ec9070 | 675 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
676 | * |
677 | * @adev: amdgpu_device pointer | |
678 | * | |
455a7bc2 | 679 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
680 | * Used at driver startup. |
681 | * Returns 0 on success or an -error on failure. | |
682 | */ | |
06ec9070 | 683 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
684 | { |
685 | int r; | |
686 | ||
687 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
688 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
689 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
690 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
691 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
692 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
693 | if (r) { |
694 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
695 | return r; | |
696 | } | |
d38ceaf9 AD |
697 | |
698 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
699 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
700 | ||
701 | /* clear wb memory */ | |
73469585 | 702 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
703 | } |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | /** | |
131b4b36 | 709 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
710 | * |
711 | * @adev: amdgpu_device pointer | |
712 | * @wb: wb index | |
713 | * | |
714 | * Allocate a wb slot for use by the driver (all asics). | |
715 | * Returns 0 on success or -EINVAL on failure. | |
716 | */ | |
131b4b36 | 717 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
718 | { |
719 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 720 | |
97407b63 | 721 | if (offset < adev->wb.num_wb) { |
7014285a | 722 | __set_bit(offset, adev->wb.used); |
63ae07ca | 723 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
724 | return 0; |
725 | } else { | |
726 | return -EINVAL; | |
727 | } | |
728 | } | |
729 | ||
d38ceaf9 | 730 | /** |
131b4b36 | 731 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
732 | * |
733 | * @adev: amdgpu_device pointer | |
734 | * @wb: wb index | |
735 | * | |
736 | * Free a wb slot allocated for use by the driver (all asics) | |
737 | */ | |
131b4b36 | 738 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 739 | { |
73469585 | 740 | wb >>= 3; |
d38ceaf9 | 741 | if (wb < adev->wb.num_wb) |
73469585 | 742 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
743 | } |
744 | ||
d6895ad3 CK |
745 | /** |
746 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
747 | * | |
748 | * @adev: amdgpu_device pointer | |
749 | * | |
750 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
751 | * to fail, but if any of the BARs is not accessible after the size we abort | |
752 | * driver loading by returning -ENODEV. | |
753 | */ | |
754 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
755 | { | |
770d13b1 | 756 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 757 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
758 | struct pci_bus *root; |
759 | struct resource *res; | |
760 | unsigned i; | |
d6895ad3 CK |
761 | u16 cmd; |
762 | int r; | |
763 | ||
0c03b912 | 764 | /* Bypass for VF */ |
765 | if (amdgpu_sriov_vf(adev)) | |
766 | return 0; | |
767 | ||
31b8adab CK |
768 | /* Check if the root BUS has 64bit memory resources */ |
769 | root = adev->pdev->bus; | |
770 | while (root->parent) | |
771 | root = root->parent; | |
772 | ||
773 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 774 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
775 | res->start > 0x100000000ull) |
776 | break; | |
777 | } | |
778 | ||
779 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
780 | if (!res) | |
781 | return 0; | |
782 | ||
d6895ad3 CK |
783 | /* Disable memory decoding while we change the BAR addresses and size */ |
784 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
785 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
786 | cmd & ~PCI_COMMAND_MEMORY); | |
787 | ||
788 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 789 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
790 | if (adev->asic_type >= CHIP_BONAIRE) |
791 | pci_release_resource(adev->pdev, 2); | |
792 | ||
793 | pci_release_resource(adev->pdev, 0); | |
794 | ||
795 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
796 | if (r == -ENOSPC) | |
797 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
798 | else if (r && r != -ENOTSUPP) | |
799 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
800 | ||
801 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
802 | ||
803 | /* When the doorbell or fb BAR isn't available we have no chance of | |
804 | * using the device. | |
805 | */ | |
06ec9070 | 806 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
807 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
808 | return -ENODEV; | |
809 | ||
810 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
811 | ||
812 | return 0; | |
813 | } | |
a05502e5 | 814 | |
d38ceaf9 AD |
815 | /* |
816 | * GPU helpers function. | |
817 | */ | |
818 | /** | |
39c640c0 | 819 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
820 | * |
821 | * @adev: amdgpu_device pointer | |
822 | * | |
c836fec5 JQ |
823 | * Check if the asic has been initialized (all asics) at driver startup |
824 | * or post is needed if hw reset is performed. | |
825 | * Returns true if need or false if not. | |
d38ceaf9 | 826 | */ |
39c640c0 | 827 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
828 | { |
829 | uint32_t reg; | |
830 | ||
bec86378 ML |
831 | if (amdgpu_sriov_vf(adev)) |
832 | return false; | |
833 | ||
834 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
835 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
836 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
837 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
838 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
839 | */ |
840 | if (adev->asic_type == CHIP_FIJI) { | |
841 | int err; | |
842 | uint32_t fw_ver; | |
843 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
844 | /* force vPost if error occured */ | |
845 | if (err) | |
846 | return true; | |
847 | ||
848 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
849 | if (fw_ver < 0x00160e00) |
850 | return true; | |
bec86378 | 851 | } |
bec86378 | 852 | } |
91fe77eb | 853 | |
854 | if (adev->has_hw_reset) { | |
855 | adev->has_hw_reset = false; | |
856 | return true; | |
857 | } | |
858 | ||
859 | /* bios scratch used on CIK+ */ | |
860 | if (adev->asic_type >= CHIP_BONAIRE) | |
861 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
862 | ||
863 | /* check MEM_SIZE for older asics */ | |
864 | reg = amdgpu_asic_get_config_memsize(adev); | |
865 | ||
866 | if ((reg != 0) && (reg != 0xffffffff)) | |
867 | return false; | |
868 | ||
869 | return true; | |
bec86378 ML |
870 | } |
871 | ||
d38ceaf9 AD |
872 | /* if we get transitioned to only one device, take VGA back */ |
873 | /** | |
06ec9070 | 874 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
875 | * |
876 | * @cookie: amdgpu_device pointer | |
877 | * @state: enable/disable vga decode | |
878 | * | |
879 | * Enable/disable vga decode (all asics). | |
880 | * Returns VGA resource flags. | |
881 | */ | |
06ec9070 | 882 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
883 | { |
884 | struct amdgpu_device *adev = cookie; | |
885 | amdgpu_asic_set_vga_state(adev, state); | |
886 | if (state) | |
887 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
888 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
889 | else | |
890 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
891 | } | |
892 | ||
e3ecdffa AD |
893 | /** |
894 | * amdgpu_device_check_block_size - validate the vm block size | |
895 | * | |
896 | * @adev: amdgpu_device pointer | |
897 | * | |
898 | * Validates the vm block size specified via module parameter. | |
899 | * The vm block size defines number of bits in page table versus page directory, | |
900 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
901 | * page table and the remaining bits are in the page directory. | |
902 | */ | |
06ec9070 | 903 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
904 | { |
905 | /* defines number of bits in page table versus page directory, | |
906 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
907 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
908 | if (amdgpu_vm_block_size == -1) |
909 | return; | |
a1adf8be | 910 | |
bab4fee7 | 911 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
912 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
913 | amdgpu_vm_block_size); | |
97489129 | 914 | amdgpu_vm_block_size = -1; |
a1adf8be | 915 | } |
a1adf8be CZ |
916 | } |
917 | ||
e3ecdffa AD |
918 | /** |
919 | * amdgpu_device_check_vm_size - validate the vm size | |
920 | * | |
921 | * @adev: amdgpu_device pointer | |
922 | * | |
923 | * Validates the vm size in GB specified via module parameter. | |
924 | * The VM size is the size of the GPU virtual memory space in GB. | |
925 | */ | |
06ec9070 | 926 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 927 | { |
64dab074 AD |
928 | /* no need to check the default value */ |
929 | if (amdgpu_vm_size == -1) | |
930 | return; | |
931 | ||
83ca145d ZJ |
932 | if (amdgpu_vm_size < 1) { |
933 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
934 | amdgpu_vm_size); | |
f3368128 | 935 | amdgpu_vm_size = -1; |
83ca145d | 936 | } |
83ca145d ZJ |
937 | } |
938 | ||
7951e376 RZ |
939 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
940 | { | |
941 | struct sysinfo si; | |
942 | bool is_os_64 = (sizeof(void *) == 8) ? true : false; | |
943 | uint64_t total_memory; | |
944 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
945 | uint64_t dram_size_three_GB = 0xB8000000; | |
946 | ||
947 | if (amdgpu_smu_memory_pool_size == 0) | |
948 | return; | |
949 | ||
950 | if (!is_os_64) { | |
951 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
952 | goto def_value; | |
953 | } | |
954 | si_meminfo(&si); | |
955 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
956 | ||
957 | if ((amdgpu_smu_memory_pool_size == 1) || | |
958 | (amdgpu_smu_memory_pool_size == 2)) { | |
959 | if (total_memory < dram_size_three_GB) | |
960 | goto def_value1; | |
961 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
962 | (amdgpu_smu_memory_pool_size == 8)) { | |
963 | if (total_memory < dram_size_seven_GB) | |
964 | goto def_value1; | |
965 | } else { | |
966 | DRM_WARN("Smu memory pool size not supported\n"); | |
967 | goto def_value; | |
968 | } | |
969 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
970 | ||
971 | return; | |
972 | ||
973 | def_value1: | |
974 | DRM_WARN("No enough system memory\n"); | |
975 | def_value: | |
976 | adev->pm.smu_prv_buffer_size = 0; | |
977 | } | |
978 | ||
d38ceaf9 | 979 | /** |
06ec9070 | 980 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
981 | * |
982 | * @adev: amdgpu_device pointer | |
983 | * | |
984 | * Validates certain module parameters and updates | |
985 | * the associated values used by the driver (all asics). | |
986 | */ | |
912dfc84 | 987 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 988 | { |
912dfc84 EQ |
989 | int ret = 0; |
990 | ||
5b011235 CZ |
991 | if (amdgpu_sched_jobs < 4) { |
992 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
993 | amdgpu_sched_jobs); | |
994 | amdgpu_sched_jobs = 4; | |
76117507 | 995 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
996 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
997 | amdgpu_sched_jobs); | |
998 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
999 | } | |
d38ceaf9 | 1000 | |
83e74db6 | 1001 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1002 | /* gart size must be greater or equal to 32M */ |
1003 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1004 | amdgpu_gart_size); | |
83e74db6 | 1005 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1006 | } |
1007 | ||
36d38372 | 1008 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1009 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1010 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1011 | amdgpu_gtt_size); | |
1012 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1013 | } |
1014 | ||
d07f14be RH |
1015 | /* valid range is between 4 and 9 inclusive */ |
1016 | if (amdgpu_vm_fragment_size != -1 && | |
1017 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1018 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1019 | amdgpu_vm_fragment_size = -1; | |
1020 | } | |
1021 | ||
7951e376 RZ |
1022 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1023 | ||
06ec9070 | 1024 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1025 | |
06ec9070 | 1026 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1027 | |
19aede77 | 1028 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 EQ |
1029 | |
1030 | return ret; | |
d38ceaf9 AD |
1031 | } |
1032 | ||
1033 | /** | |
1034 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1035 | * | |
1036 | * @pdev: pci dev pointer | |
1694467b | 1037 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1038 | * |
1039 | * Callback for the switcheroo driver. Suspends or resumes the | |
1040 | * the asics before or after it is powered up using ACPI methods. | |
1041 | */ | |
1042 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1043 | { | |
1044 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1045 | ||
1046 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1047 | return; | |
1048 | ||
1049 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1050 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1051 | /* don't suspend or resume card normally */ |
1052 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1053 | ||
810ddc3a | 1054 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1055 | |
d38ceaf9 AD |
1056 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1057 | drm_kms_helper_poll_enable(dev); | |
1058 | } else { | |
7ca85295 | 1059 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1060 | drm_kms_helper_poll_disable(dev); |
1061 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1062 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1063 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1064 | } | |
1065 | } | |
1066 | ||
1067 | /** | |
1068 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1069 | * | |
1070 | * @pdev: pci dev pointer | |
1071 | * | |
1072 | * Callback for the switcheroo driver. Check of the switcheroo | |
1073 | * state can be changed. | |
1074 | * Returns true if the state can be changed, false if not. | |
1075 | */ | |
1076 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1077 | { | |
1078 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1079 | ||
1080 | /* | |
1081 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1082 | * locking inversion with the driver load path. And the access here is | |
1083 | * completely racy anyway. So don't bother with locking for now. | |
1084 | */ | |
1085 | return dev->open_count == 0; | |
1086 | } | |
1087 | ||
1088 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1089 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1090 | .reprobe = NULL, | |
1091 | .can_switch = amdgpu_switcheroo_can_switch, | |
1092 | }; | |
1093 | ||
e3ecdffa AD |
1094 | /** |
1095 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1096 | * | |
87e3f136 | 1097 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1098 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1099 | * @state: clockgating state (gate or ungate) | |
1100 | * | |
1101 | * Sets the requested clockgating state for all instances of | |
1102 | * the hardware IP specified. | |
1103 | * Returns the error code from the last instance. | |
1104 | */ | |
43fa561f | 1105 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1106 | enum amd_ip_block_type block_type, |
1107 | enum amd_clockgating_state state) | |
d38ceaf9 | 1108 | { |
43fa561f | 1109 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1110 | int i, r = 0; |
1111 | ||
1112 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1113 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1114 | continue; |
c722865a RZ |
1115 | if (adev->ip_blocks[i].version->type != block_type) |
1116 | continue; | |
1117 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1118 | continue; | |
1119 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1120 | (void *)adev, state); | |
1121 | if (r) | |
1122 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1123 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1124 | } |
1125 | return r; | |
1126 | } | |
1127 | ||
e3ecdffa AD |
1128 | /** |
1129 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1130 | * | |
87e3f136 | 1131 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1132 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1133 | * @state: powergating state (gate or ungate) | |
1134 | * | |
1135 | * Sets the requested powergating state for all instances of | |
1136 | * the hardware IP specified. | |
1137 | * Returns the error code from the last instance. | |
1138 | */ | |
43fa561f | 1139 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1140 | enum amd_ip_block_type block_type, |
1141 | enum amd_powergating_state state) | |
d38ceaf9 | 1142 | { |
43fa561f | 1143 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1144 | int i, r = 0; |
1145 | ||
1146 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1147 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1148 | continue; |
c722865a RZ |
1149 | if (adev->ip_blocks[i].version->type != block_type) |
1150 | continue; | |
1151 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1152 | continue; | |
1153 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1154 | (void *)adev, state); | |
1155 | if (r) | |
1156 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1157 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1158 | } |
1159 | return r; | |
1160 | } | |
1161 | ||
e3ecdffa AD |
1162 | /** |
1163 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1164 | * | |
1165 | * @adev: amdgpu_device pointer | |
1166 | * @flags: clockgating feature flags | |
1167 | * | |
1168 | * Walks the list of IPs on the device and updates the clockgating | |
1169 | * flags for each IP. | |
1170 | * Updates @flags with the feature flags for each hardware IP where | |
1171 | * clockgating is enabled. | |
1172 | */ | |
2990a1fc AD |
1173 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1174 | u32 *flags) | |
6cb2d4e4 HR |
1175 | { |
1176 | int i; | |
1177 | ||
1178 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1179 | if (!adev->ip_blocks[i].status.valid) | |
1180 | continue; | |
1181 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1182 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1183 | } | |
1184 | } | |
1185 | ||
e3ecdffa AD |
1186 | /** |
1187 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1188 | * | |
1189 | * @adev: amdgpu_device pointer | |
1190 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1191 | * | |
1192 | * Waits for the request hardware IP to be idle. | |
1193 | * Returns 0 for success or a negative error code on failure. | |
1194 | */ | |
2990a1fc AD |
1195 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1196 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1197 | { |
1198 | int i, r; | |
1199 | ||
1200 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1201 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1202 | continue; |
a1255107 AD |
1203 | if (adev->ip_blocks[i].version->type == block_type) { |
1204 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1205 | if (r) |
1206 | return r; | |
1207 | break; | |
1208 | } | |
1209 | } | |
1210 | return 0; | |
1211 | ||
1212 | } | |
1213 | ||
e3ecdffa AD |
1214 | /** |
1215 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1216 | * | |
1217 | * @adev: amdgpu_device pointer | |
1218 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1219 | * | |
1220 | * Check if the hardware IP is idle or not. | |
1221 | * Returns true if it the IP is idle, false if not. | |
1222 | */ | |
2990a1fc AD |
1223 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1224 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1225 | { |
1226 | int i; | |
1227 | ||
1228 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1229 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1230 | continue; |
a1255107 AD |
1231 | if (adev->ip_blocks[i].version->type == block_type) |
1232 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1233 | } |
1234 | return true; | |
1235 | ||
1236 | } | |
1237 | ||
e3ecdffa AD |
1238 | /** |
1239 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1240 | * | |
1241 | * @adev: amdgpu_device pointer | |
87e3f136 | 1242 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1243 | * |
1244 | * Returns a pointer to the hardware IP block structure | |
1245 | * if it exists for the asic, otherwise NULL. | |
1246 | */ | |
2990a1fc AD |
1247 | struct amdgpu_ip_block * |
1248 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1249 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1250 | { |
1251 | int i; | |
1252 | ||
1253 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1254 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1255 | return &adev->ip_blocks[i]; |
1256 | ||
1257 | return NULL; | |
1258 | } | |
1259 | ||
1260 | /** | |
2990a1fc | 1261 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1262 | * |
1263 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1264 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1265 | * @major: major version |
1266 | * @minor: minor version | |
1267 | * | |
1268 | * return 0 if equal or greater | |
1269 | * return 1 if smaller or the ip_block doesn't exist | |
1270 | */ | |
2990a1fc AD |
1271 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1272 | enum amd_ip_block_type type, | |
1273 | u32 major, u32 minor) | |
d38ceaf9 | 1274 | { |
2990a1fc | 1275 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1276 | |
a1255107 AD |
1277 | if (ip_block && ((ip_block->version->major > major) || |
1278 | ((ip_block->version->major == major) && | |
1279 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1280 | return 0; |
1281 | ||
1282 | return 1; | |
1283 | } | |
1284 | ||
a1255107 | 1285 | /** |
2990a1fc | 1286 | * amdgpu_device_ip_block_add |
a1255107 AD |
1287 | * |
1288 | * @adev: amdgpu_device pointer | |
1289 | * @ip_block_version: pointer to the IP to add | |
1290 | * | |
1291 | * Adds the IP block driver information to the collection of IPs | |
1292 | * on the asic. | |
1293 | */ | |
2990a1fc AD |
1294 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1295 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1296 | { |
1297 | if (!ip_block_version) | |
1298 | return -EINVAL; | |
1299 | ||
e966a725 | 1300 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1301 | ip_block_version->funcs->name); |
1302 | ||
a1255107 AD |
1303 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
e3ecdffa AD |
1308 | /** |
1309 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1310 | * | |
1311 | * @adev: amdgpu_device pointer | |
1312 | * | |
1313 | * Enabled the virtual display feature if the user has enabled it via | |
1314 | * the module parameter virtual_display. This feature provides a virtual | |
1315 | * display hardware on headless boards or in virtualized environments. | |
1316 | * This function parses and validates the configuration string specified by | |
1317 | * the user and configues the virtual display configuration (number of | |
1318 | * virtual connectors, crtcs, etc.) specified. | |
1319 | */ | |
483ef985 | 1320 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1321 | { |
1322 | adev->enable_virtual_display = false; | |
1323 | ||
1324 | if (amdgpu_virtual_display) { | |
1325 | struct drm_device *ddev = adev->ddev; | |
1326 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1327 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1328 | |
1329 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1330 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1331 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1332 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1333 | if (!strcmp("all", pciaddname) |
1334 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1335 | long num_crtc; |
1336 | int res = -1; | |
1337 | ||
9accf2fd | 1338 | adev->enable_virtual_display = true; |
0f66356d ED |
1339 | |
1340 | if (pciaddname_tmp) | |
1341 | res = kstrtol(pciaddname_tmp, 10, | |
1342 | &num_crtc); | |
1343 | ||
1344 | if (!res) { | |
1345 | if (num_crtc < 1) | |
1346 | num_crtc = 1; | |
1347 | if (num_crtc > 6) | |
1348 | num_crtc = 6; | |
1349 | adev->mode_info.num_crtc = num_crtc; | |
1350 | } else { | |
1351 | adev->mode_info.num_crtc = 1; | |
1352 | } | |
9accf2fd ED |
1353 | break; |
1354 | } | |
1355 | } | |
1356 | ||
0f66356d ED |
1357 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1358 | amdgpu_virtual_display, pci_address_name, | |
1359 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1360 | |
1361 | kfree(pciaddstr); | |
1362 | } | |
1363 | } | |
1364 | ||
e3ecdffa AD |
1365 | /** |
1366 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1367 | * | |
1368 | * @adev: amdgpu_device pointer | |
1369 | * | |
1370 | * Parses the asic configuration parameters specified in the gpu info | |
1371 | * firmware and makes them availale to the driver for use in configuring | |
1372 | * the asic. | |
1373 | * Returns 0 on success, -EINVAL on failure. | |
1374 | */ | |
e2a75f88 AD |
1375 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1376 | { | |
e2a75f88 AD |
1377 | const char *chip_name; |
1378 | char fw_name[30]; | |
1379 | int err; | |
1380 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1381 | ||
ab4fe3e1 HR |
1382 | adev->firmware.gpu_info_fw = NULL; |
1383 | ||
e2a75f88 AD |
1384 | switch (adev->asic_type) { |
1385 | case CHIP_TOPAZ: | |
1386 | case CHIP_TONGA: | |
1387 | case CHIP_FIJI: | |
e2a75f88 | 1388 | case CHIP_POLARIS10: |
cc07f18d | 1389 | case CHIP_POLARIS11: |
e2a75f88 | 1390 | case CHIP_POLARIS12: |
cc07f18d | 1391 | case CHIP_VEGAM: |
e2a75f88 AD |
1392 | case CHIP_CARRIZO: |
1393 | case CHIP_STONEY: | |
1394 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1395 | case CHIP_VERDE: | |
1396 | case CHIP_TAHITI: | |
1397 | case CHIP_PITCAIRN: | |
1398 | case CHIP_OLAND: | |
1399 | case CHIP_HAINAN: | |
1400 | #endif | |
1401 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1402 | case CHIP_BONAIRE: | |
1403 | case CHIP_HAWAII: | |
1404 | case CHIP_KAVERI: | |
1405 | case CHIP_KABINI: | |
1406 | case CHIP_MULLINS: | |
1407 | #endif | |
27c0bc71 | 1408 | case CHIP_VEGA20: |
e2a75f88 AD |
1409 | default: |
1410 | return 0; | |
1411 | case CHIP_VEGA10: | |
1412 | chip_name = "vega10"; | |
1413 | break; | |
3f76dced AD |
1414 | case CHIP_VEGA12: |
1415 | chip_name = "vega12"; | |
1416 | break; | |
2d2e5e7e | 1417 | case CHIP_RAVEN: |
54c4d17e FX |
1418 | if (adev->rev_id >= 8) |
1419 | chip_name = "raven2"; | |
741deade AD |
1420 | else if (adev->pdev->device == 0x15d8) |
1421 | chip_name = "picasso"; | |
54c4d17e FX |
1422 | else |
1423 | chip_name = "raven"; | |
2d2e5e7e | 1424 | break; |
65e60f6e LM |
1425 | case CHIP_ARCTURUS: |
1426 | chip_name = "arcturus"; | |
1427 | break; | |
b51a26a0 HR |
1428 | case CHIP_RENOIR: |
1429 | chip_name = "renoir"; | |
1430 | break; | |
23c6268e HR |
1431 | case CHIP_NAVI10: |
1432 | chip_name = "navi10"; | |
1433 | break; | |
ed42cfe1 XY |
1434 | case CHIP_NAVI14: |
1435 | chip_name = "navi14"; | |
1436 | break; | |
42b325e5 XY |
1437 | case CHIP_NAVI12: |
1438 | chip_name = "navi12"; | |
1439 | break; | |
e2a75f88 AD |
1440 | } |
1441 | ||
1442 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1443 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1444 | if (err) { |
1445 | dev_err(adev->dev, | |
1446 | "Failed to load gpu_info firmware \"%s\"\n", | |
1447 | fw_name); | |
1448 | goto out; | |
1449 | } | |
ab4fe3e1 | 1450 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1451 | if (err) { |
1452 | dev_err(adev->dev, | |
1453 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1454 | fw_name); | |
1455 | goto out; | |
1456 | } | |
1457 | ||
ab4fe3e1 | 1458 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1459 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1460 | ||
1461 | switch (hdr->version_major) { | |
1462 | case 1: | |
1463 | { | |
1464 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1465 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1466 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1467 | ||
ec51d3fa XY |
1468 | if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) |
1469 | goto parse_soc_bounding_box; | |
1470 | ||
b5ab16bf AD |
1471 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1472 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1473 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1474 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1475 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1476 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1477 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1478 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1479 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1480 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1481 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1482 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1483 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1484 | adev->gfx.cu_info.max_waves_per_simd = |
1485 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1486 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1487 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1488 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 1489 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
1490 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
1491 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
1492 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1493 | adev->gfx.config.num_sc_per_sh = | |
1494 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
1495 | adev->gfx.config.num_packer_per_sc = | |
1496 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
1497 | } | |
ec51d3fa XY |
1498 | |
1499 | parse_soc_bounding_box: | |
48321c3d | 1500 | #ifdef CONFIG_DRM_AMD_DC_DCN2_0 |
ec51d3fa XY |
1501 | /* |
1502 | * soc bounding box info is not integrated in disocovery table, | |
1503 | * we always need to parse it from gpu info firmware. | |
1504 | */ | |
48321c3d HW |
1505 | if (hdr->version_minor == 2) { |
1506 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
1507 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
1508 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1509 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
1510 | } | |
1511 | #endif | |
e2a75f88 AD |
1512 | break; |
1513 | } | |
1514 | default: | |
1515 | dev_err(adev->dev, | |
1516 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1517 | err = -EINVAL; | |
1518 | goto out; | |
1519 | } | |
1520 | out: | |
e2a75f88 AD |
1521 | return err; |
1522 | } | |
1523 | ||
e3ecdffa AD |
1524 | /** |
1525 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1526 | * | |
1527 | * @adev: amdgpu_device pointer | |
1528 | * | |
1529 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1530 | * up each asic are discovered each IP's early_init callback is run. This | |
1531 | * is the first stage in initializing the asic. | |
1532 | * Returns 0 on success, negative error code on failure. | |
1533 | */ | |
06ec9070 | 1534 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1535 | { |
aaa36a97 | 1536 | int i, r; |
d38ceaf9 | 1537 | |
483ef985 | 1538 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1539 | |
d38ceaf9 | 1540 | switch (adev->asic_type) { |
aaa36a97 AD |
1541 | case CHIP_TOPAZ: |
1542 | case CHIP_TONGA: | |
48299f95 | 1543 | case CHIP_FIJI: |
2cc0c0b5 | 1544 | case CHIP_POLARIS10: |
32cc7e53 | 1545 | case CHIP_POLARIS11: |
c4642a47 | 1546 | case CHIP_POLARIS12: |
32cc7e53 | 1547 | case CHIP_VEGAM: |
aaa36a97 | 1548 | case CHIP_CARRIZO: |
39bb0c92 SL |
1549 | case CHIP_STONEY: |
1550 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1551 | adev->family = AMDGPU_FAMILY_CZ; |
1552 | else | |
1553 | adev->family = AMDGPU_FAMILY_VI; | |
1554 | ||
1555 | r = vi_set_ip_blocks(adev); | |
1556 | if (r) | |
1557 | return r; | |
1558 | break; | |
33f34802 KW |
1559 | #ifdef CONFIG_DRM_AMDGPU_SI |
1560 | case CHIP_VERDE: | |
1561 | case CHIP_TAHITI: | |
1562 | case CHIP_PITCAIRN: | |
1563 | case CHIP_OLAND: | |
1564 | case CHIP_HAINAN: | |
295d0daf | 1565 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1566 | r = si_set_ip_blocks(adev); |
1567 | if (r) | |
1568 | return r; | |
1569 | break; | |
1570 | #endif | |
a2e73f56 AD |
1571 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1572 | case CHIP_BONAIRE: | |
1573 | case CHIP_HAWAII: | |
1574 | case CHIP_KAVERI: | |
1575 | case CHIP_KABINI: | |
1576 | case CHIP_MULLINS: | |
1577 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1578 | adev->family = AMDGPU_FAMILY_CI; | |
1579 | else | |
1580 | adev->family = AMDGPU_FAMILY_KV; | |
1581 | ||
1582 | r = cik_set_ip_blocks(adev); | |
1583 | if (r) | |
1584 | return r; | |
1585 | break; | |
1586 | #endif | |
e48a3cd9 AD |
1587 | case CHIP_VEGA10: |
1588 | case CHIP_VEGA12: | |
e4bd8170 | 1589 | case CHIP_VEGA20: |
e48a3cd9 | 1590 | case CHIP_RAVEN: |
61cf44c1 | 1591 | case CHIP_ARCTURUS: |
b51a26a0 HR |
1592 | case CHIP_RENOIR: |
1593 | if (adev->asic_type == CHIP_RAVEN || | |
1594 | adev->asic_type == CHIP_RENOIR) | |
2ca8a5d2 CZ |
1595 | adev->family = AMDGPU_FAMILY_RV; |
1596 | else | |
1597 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1598 | |
1599 | r = soc15_set_ip_blocks(adev); | |
1600 | if (r) | |
1601 | return r; | |
1602 | break; | |
0a5b8c7b | 1603 | case CHIP_NAVI10: |
7ecb5cd4 | 1604 | case CHIP_NAVI14: |
4808cf9c | 1605 | case CHIP_NAVI12: |
0a5b8c7b HR |
1606 | adev->family = AMDGPU_FAMILY_NV; |
1607 | ||
1608 | r = nv_set_ip_blocks(adev); | |
1609 | if (r) | |
1610 | return r; | |
1611 | break; | |
d38ceaf9 AD |
1612 | default: |
1613 | /* FIXME: not supported yet */ | |
1614 | return -EINVAL; | |
1615 | } | |
1616 | ||
e2a75f88 AD |
1617 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1618 | if (r) | |
1619 | return r; | |
1620 | ||
ec51d3fa XY |
1621 | if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) |
1622 | amdgpu_discovery_get_gfx_info(adev); | |
1623 | ||
1884734a | 1624 | amdgpu_amdkfd_device_probe(adev); |
1625 | ||
3149d9da XY |
1626 | if (amdgpu_sriov_vf(adev)) { |
1627 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1628 | if (r) | |
5ffa61c1 | 1629 | return -EAGAIN; |
3149d9da XY |
1630 | } |
1631 | ||
3b94fb10 | 1632 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 1633 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 1634 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
00f54b97 | 1635 | |
d38ceaf9 AD |
1636 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1637 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1638 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1639 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1640 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1641 | } else { |
a1255107 AD |
1642 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1643 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1644 | if (r == -ENOENT) { |
a1255107 | 1645 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1646 | } else if (r) { |
a1255107 AD |
1647 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1648 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1649 | return r; |
2c1a2784 | 1650 | } else { |
a1255107 | 1651 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1652 | } |
974e6b64 | 1653 | } else { |
a1255107 | 1654 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1655 | } |
d38ceaf9 | 1656 | } |
21a249ca AD |
1657 | /* get the vbios after the asic_funcs are set up */ |
1658 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
1659 | /* Read BIOS */ | |
1660 | if (!amdgpu_get_bios(adev)) | |
1661 | return -EINVAL; | |
1662 | ||
1663 | r = amdgpu_atombios_init(adev); | |
1664 | if (r) { | |
1665 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
1666 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
1667 | return r; | |
1668 | } | |
1669 | } | |
d38ceaf9 AD |
1670 | } |
1671 | ||
395d1fb9 NH |
1672 | adev->cg_flags &= amdgpu_cg_mask; |
1673 | adev->pg_flags &= amdgpu_pg_mask; | |
1674 | ||
d38ceaf9 AD |
1675 | return 0; |
1676 | } | |
1677 | ||
0a4f2520 RZ |
1678 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
1679 | { | |
1680 | int i, r; | |
1681 | ||
1682 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1683 | if (!adev->ip_blocks[i].status.sw) | |
1684 | continue; | |
1685 | if (adev->ip_blocks[i].status.hw) | |
1686 | continue; | |
1687 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 1688 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
1689 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
1690 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1691 | if (r) { | |
1692 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1693 | adev->ip_blocks[i].version->funcs->name, r); | |
1694 | return r; | |
1695 | } | |
1696 | adev->ip_blocks[i].status.hw = true; | |
1697 | } | |
1698 | } | |
1699 | ||
1700 | return 0; | |
1701 | } | |
1702 | ||
1703 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
1704 | { | |
1705 | int i, r; | |
1706 | ||
1707 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1708 | if (!adev->ip_blocks[i].status.sw) | |
1709 | continue; | |
1710 | if (adev->ip_blocks[i].status.hw) | |
1711 | continue; | |
1712 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1713 | if (r) { | |
1714 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1715 | adev->ip_blocks[i].version->funcs->name, r); | |
1716 | return r; | |
1717 | } | |
1718 | adev->ip_blocks[i].status.hw = true; | |
1719 | } | |
1720 | ||
1721 | return 0; | |
1722 | } | |
1723 | ||
7a3e0bb2 RZ |
1724 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
1725 | { | |
1726 | int r = 0; | |
1727 | int i; | |
80f41f84 | 1728 | uint32_t smu_version; |
7a3e0bb2 RZ |
1729 | |
1730 | if (adev->asic_type >= CHIP_VEGA10) { | |
1731 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
1732 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
1733 | continue; | |
1734 | ||
1735 | /* no need to do the fw loading again if already done*/ | |
1736 | if (adev->ip_blocks[i].status.hw == true) | |
1737 | break; | |
1738 | ||
1739 | if (adev->in_gpu_reset || adev->in_suspend) { | |
1740 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1741 | if (r) { | |
1742 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 1743 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
1744 | return r; |
1745 | } | |
1746 | } else { | |
1747 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1748 | if (r) { | |
1749 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1750 | adev->ip_blocks[i].version->funcs->name, r); | |
1751 | return r; | |
7a3e0bb2 | 1752 | } |
7a3e0bb2 | 1753 | } |
482f0e53 ML |
1754 | |
1755 | adev->ip_blocks[i].status.hw = true; | |
1756 | break; | |
7a3e0bb2 RZ |
1757 | } |
1758 | } | |
482f0e53 | 1759 | |
80f41f84 | 1760 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); |
7a3e0bb2 | 1761 | |
80f41f84 | 1762 | return r; |
7a3e0bb2 RZ |
1763 | } |
1764 | ||
e3ecdffa AD |
1765 | /** |
1766 | * amdgpu_device_ip_init - run init for hardware IPs | |
1767 | * | |
1768 | * @adev: amdgpu_device pointer | |
1769 | * | |
1770 | * Main initialization pass for hardware IPs. The list of all the hardware | |
1771 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
1772 | * are run. sw_init initializes the software state associated with each IP | |
1773 | * and hw_init initializes the hardware associated with each IP. | |
1774 | * Returns 0 on success, negative error code on failure. | |
1775 | */ | |
06ec9070 | 1776 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1777 | { |
1778 | int i, r; | |
1779 | ||
c030f2e4 | 1780 | r = amdgpu_ras_init(adev); |
1781 | if (r) | |
1782 | return r; | |
1783 | ||
d38ceaf9 | 1784 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 1785 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1786 | continue; |
a1255107 | 1787 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1788 | if (r) { |
a1255107 AD |
1789 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1790 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 1791 | goto init_failed; |
2c1a2784 | 1792 | } |
a1255107 | 1793 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 1794 | |
d38ceaf9 | 1795 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1796 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 1797 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
1798 | if (r) { |
1799 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 1800 | goto init_failed; |
2c1a2784 | 1801 | } |
a1255107 | 1802 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1803 | if (r) { |
1804 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 1805 | goto init_failed; |
2c1a2784 | 1806 | } |
06ec9070 | 1807 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 1808 | if (r) { |
06ec9070 | 1809 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 1810 | goto init_failed; |
2c1a2784 | 1811 | } |
a1255107 | 1812 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1813 | |
1814 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 1815 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
1816 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
1817 | AMDGPU_GEM_DOMAIN_VRAM, | |
1818 | AMDGPU_CSA_SIZE); | |
2493664f ML |
1819 | if (r) { |
1820 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 1821 | goto init_failed; |
2493664f ML |
1822 | } |
1823 | } | |
d38ceaf9 AD |
1824 | } |
1825 | } | |
1826 | ||
533aed27 AG |
1827 | r = amdgpu_ib_pool_init(adev); |
1828 | if (r) { | |
1829 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
1830 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
1831 | goto init_failed; | |
1832 | } | |
1833 | ||
c8963ea4 RZ |
1834 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
1835 | if (r) | |
72d3f592 | 1836 | goto init_failed; |
0a4f2520 RZ |
1837 | |
1838 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
1839 | if (r) | |
72d3f592 | 1840 | goto init_failed; |
0a4f2520 | 1841 | |
7a3e0bb2 RZ |
1842 | r = amdgpu_device_fw_loading(adev); |
1843 | if (r) | |
72d3f592 | 1844 | goto init_failed; |
7a3e0bb2 | 1845 | |
0a4f2520 RZ |
1846 | r = amdgpu_device_ip_hw_init_phase2(adev); |
1847 | if (r) | |
72d3f592 | 1848 | goto init_failed; |
d38ceaf9 | 1849 | |
3e2e2ab5 HZ |
1850 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
1851 | amdgpu_xgmi_add_device(adev); | |
1884734a | 1852 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1853 | |
72d3f592 | 1854 | init_failed: |
d3c117e5 | 1855 | if (amdgpu_sriov_vf(adev)) { |
72d3f592 ED |
1856 | if (!r) |
1857 | amdgpu_virt_init_data_exchange(adev); | |
c6332b97 | 1858 | amdgpu_virt_release_full_gpu(adev, true); |
d3c117e5 | 1859 | } |
c6332b97 | 1860 | |
72d3f592 | 1861 | return r; |
d38ceaf9 AD |
1862 | } |
1863 | ||
e3ecdffa AD |
1864 | /** |
1865 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
1866 | * | |
1867 | * @adev: amdgpu_device pointer | |
1868 | * | |
1869 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
1870 | * this function before a GPU reset. If the value is retained after a | |
1871 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
1872 | */ | |
06ec9070 | 1873 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1874 | { |
1875 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1876 | } | |
1877 | ||
e3ecdffa AD |
1878 | /** |
1879 | * amdgpu_device_check_vram_lost - check if vram is valid | |
1880 | * | |
1881 | * @adev: amdgpu_device pointer | |
1882 | * | |
1883 | * Checks the reset magic value written to the gart pointer in VRAM. | |
1884 | * The driver calls this after a GPU reset to see if the contents of | |
1885 | * VRAM is lost or now. | |
1886 | * returns true if vram is lost, false if not. | |
1887 | */ | |
06ec9070 | 1888 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1889 | { |
1890 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1891 | AMDGPU_RESET_MAGIC_NUM); | |
1892 | } | |
1893 | ||
e3ecdffa | 1894 | /** |
1112a46b | 1895 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
1896 | * |
1897 | * @adev: amdgpu_device pointer | |
1898 | * | |
e3ecdffa | 1899 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
1900 | * set_clockgating_state callbacks are run. |
1901 | * Late initialization pass enabling clockgating for hardware IPs. | |
1902 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
1903 | * Returns 0 on success, negative error code on failure. |
1904 | */ | |
fdd34271 | 1905 | |
1112a46b RZ |
1906 | static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
1907 | enum amd_clockgating_state state) | |
d38ceaf9 | 1908 | { |
1112a46b | 1909 | int i, j, r; |
d38ceaf9 | 1910 | |
4a2ba394 SL |
1911 | if (amdgpu_emu_mode == 1) |
1912 | return 0; | |
1913 | ||
1112a46b RZ |
1914 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1915 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 1916 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 1917 | continue; |
4a446d55 | 1918 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 1919 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 1920 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 1921 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
57716327 | 1922 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 1923 | /* enable clockgating to save power */ |
a1255107 | 1924 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 1925 | state); |
4a446d55 AD |
1926 | if (r) { |
1927 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1928 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1929 | return r; |
1930 | } | |
b0b00ff1 | 1931 | } |
d38ceaf9 | 1932 | } |
06b18f61 | 1933 | |
c9f96fd5 RZ |
1934 | return 0; |
1935 | } | |
1936 | ||
1112a46b | 1937 | static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state) |
c9f96fd5 | 1938 | { |
1112a46b | 1939 | int i, j, r; |
06b18f61 | 1940 | |
c9f96fd5 RZ |
1941 | if (amdgpu_emu_mode == 1) |
1942 | return 0; | |
1943 | ||
1112a46b RZ |
1944 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1945 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 1946 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 RZ |
1947 | continue; |
1948 | /* skip CG for VCE/UVD, it's handled specially */ | |
1949 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1950 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
1951 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
1952 | adev->ip_blocks[i].version->funcs->set_powergating_state) { | |
1953 | /* enable powergating to save power */ | |
1954 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 1955 | state); |
c9f96fd5 RZ |
1956 | if (r) { |
1957 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
1958 | adev->ip_blocks[i].version->funcs->name, r); | |
1959 | return r; | |
1960 | } | |
1961 | } | |
1962 | } | |
2dc80b00 S |
1963 | return 0; |
1964 | } | |
1965 | ||
beff74bc AD |
1966 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
1967 | { | |
1968 | struct amdgpu_gpu_instance *gpu_ins; | |
1969 | struct amdgpu_device *adev; | |
1970 | int i, ret = 0; | |
1971 | ||
1972 | mutex_lock(&mgpu_info.mutex); | |
1973 | ||
1974 | /* | |
1975 | * MGPU fan boost feature should be enabled | |
1976 | * only when there are two or more dGPUs in | |
1977 | * the system | |
1978 | */ | |
1979 | if (mgpu_info.num_dgpu < 2) | |
1980 | goto out; | |
1981 | ||
1982 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
1983 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
1984 | adev = gpu_ins->adev; | |
1985 | if (!(adev->flags & AMD_IS_APU) && | |
1986 | !gpu_ins->mgpu_fan_enabled && | |
1987 | adev->powerplay.pp_funcs && | |
1988 | adev->powerplay.pp_funcs->enable_mgpu_fan_boost) { | |
1989 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); | |
1990 | if (ret) | |
1991 | break; | |
1992 | ||
1993 | gpu_ins->mgpu_fan_enabled = 1; | |
1994 | } | |
1995 | } | |
1996 | ||
1997 | out: | |
1998 | mutex_unlock(&mgpu_info.mutex); | |
1999 | ||
2000 | return ret; | |
2001 | } | |
2002 | ||
e3ecdffa AD |
2003 | /** |
2004 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2005 | * | |
2006 | * @adev: amdgpu_device pointer | |
2007 | * | |
2008 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2009 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2010 | * late_init covers any special initialization that an IP requires | |
2011 | * after all of the have been initialized or something that needs to happen | |
2012 | * late in the init process. | |
2013 | * Returns 0 on success, negative error code on failure. | |
2014 | */ | |
06ec9070 | 2015 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 S |
2016 | { |
2017 | int i = 0, r; | |
2018 | ||
2019 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2020 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2021 | continue; |
2022 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2023 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2024 | if (r) { | |
2025 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2026 | adev->ip_blocks[i].version->funcs->name, r); | |
2027 | return r; | |
2028 | } | |
2dc80b00 | 2029 | } |
73f847db | 2030 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2031 | } |
2032 | ||
1112a46b RZ |
2033 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2034 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2035 | |
06ec9070 | 2036 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2037 | |
beff74bc AD |
2038 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2039 | if (r) | |
2040 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2041 | ||
2042 | /* set to low pstate by default */ | |
2043 | amdgpu_xgmi_set_pstate(adev, 0); | |
2044 | ||
d38ceaf9 AD |
2045 | return 0; |
2046 | } | |
2047 | ||
e3ecdffa AD |
2048 | /** |
2049 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2050 | * | |
2051 | * @adev: amdgpu_device pointer | |
2052 | * | |
2053 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2054 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2055 | * are run. hw_fini tears down the hardware associated with each IP | |
2056 | * and sw_fini tears down any software state associated with each IP. | |
2057 | * Returns 0 on success, negative error code on failure. | |
2058 | */ | |
06ec9070 | 2059 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
2060 | { |
2061 | int i, r; | |
2062 | ||
c030f2e4 | 2063 | amdgpu_ras_pre_fini(adev); |
2064 | ||
a82400b5 AG |
2065 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2066 | amdgpu_xgmi_remove_device(adev); | |
2067 | ||
1884734a | 2068 | amdgpu_amdkfd_device_fini(adev); |
05df1f01 RZ |
2069 | |
2070 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); | |
fdd34271 RZ |
2071 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2072 | ||
3e96dbfd AD |
2073 | /* need to disable SMC first */ |
2074 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2075 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 2076 | continue; |
fdd34271 | 2077 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 2078 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
2079 | /* XXX handle errors */ |
2080 | if (r) { | |
2081 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 2082 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 2083 | } |
a1255107 | 2084 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
2085 | break; |
2086 | } | |
2087 | } | |
2088 | ||
d38ceaf9 | 2089 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2090 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2091 | continue; |
8201a67a | 2092 | |
a1255107 | 2093 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2094 | /* XXX handle errors */ |
2c1a2784 | 2095 | if (r) { |
a1255107 AD |
2096 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2097 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2098 | } |
8201a67a | 2099 | |
a1255107 | 2100 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2101 | } |
2102 | ||
9950cda2 | 2103 | |
d38ceaf9 | 2104 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2105 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2106 | continue; |
c12aba3a ML |
2107 | |
2108 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2109 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2110 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2111 | amdgpu_device_wb_fini(adev); |
2112 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2113 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2114 | } |
2115 | ||
a1255107 | 2116 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2117 | /* XXX handle errors */ |
2c1a2784 | 2118 | if (r) { |
a1255107 AD |
2119 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2120 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2121 | } |
a1255107 AD |
2122 | adev->ip_blocks[i].status.sw = false; |
2123 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2124 | } |
2125 | ||
a6dcfd9c | 2126 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2127 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2128 | continue; |
a1255107 AD |
2129 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2130 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2131 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2132 | } |
2133 | ||
c030f2e4 | 2134 | amdgpu_ras_fini(adev); |
2135 | ||
030308fc | 2136 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
2137 | if (amdgpu_virt_release_full_gpu(adev, false)) |
2138 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 2139 | |
d38ceaf9 AD |
2140 | return 0; |
2141 | } | |
2142 | ||
e3ecdffa | 2143 | /** |
beff74bc | 2144 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2145 | * |
1112a46b | 2146 | * @work: work_struct. |
e3ecdffa | 2147 | */ |
beff74bc | 2148 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2149 | { |
2150 | struct amdgpu_device *adev = | |
beff74bc | 2151 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2152 | int r; |
2153 | ||
2154 | r = amdgpu_ib_ring_tests(adev); | |
2155 | if (r) | |
2156 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2157 | } |
2158 | ||
1e317b99 RZ |
2159 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2160 | { | |
2161 | struct amdgpu_device *adev = | |
2162 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2163 | ||
2164 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
2165 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
2166 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2167 | adev->gfx.gfx_off_state = true; | |
2168 | } | |
2169 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
2170 | } | |
2171 | ||
e3ecdffa | 2172 | /** |
e7854a03 | 2173 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2174 | * |
2175 | * @adev: amdgpu_device pointer | |
2176 | * | |
2177 | * Main suspend function for hardware IPs. The list of all the hardware | |
2178 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2179 | * suspend callbacks are run. suspend puts the hardware and software state | |
2180 | * in each IP into a state suitable for suspend. | |
2181 | * Returns 0 on success, negative error code on failure. | |
2182 | */ | |
e7854a03 AD |
2183 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2184 | { | |
2185 | int i, r; | |
2186 | ||
05df1f01 | 2187 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 | 2188 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
05df1f01 | 2189 | |
e7854a03 AD |
2190 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2191 | if (!adev->ip_blocks[i].status.valid) | |
2192 | continue; | |
2193 | /* displays are handled separately */ | |
2194 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { | |
e7854a03 AD |
2195 | /* XXX handle errors */ |
2196 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2197 | /* XXX handle errors */ | |
2198 | if (r) { | |
2199 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2200 | adev->ip_blocks[i].version->funcs->name, r); | |
482f0e53 | 2201 | return r; |
e7854a03 | 2202 | } |
482f0e53 | 2203 | adev->ip_blocks[i].status.hw = false; |
e7854a03 AD |
2204 | } |
2205 | } | |
2206 | ||
e7854a03 AD |
2207 | return 0; |
2208 | } | |
2209 | ||
2210 | /** | |
2211 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2212 | * | |
2213 | * @adev: amdgpu_device pointer | |
2214 | * | |
2215 | * Main suspend function for hardware IPs. The list of all the hardware | |
2216 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2217 | * suspend callbacks are run. suspend puts the hardware and software state | |
2218 | * in each IP into a state suitable for suspend. | |
2219 | * Returns 0 on success, negative error code on failure. | |
2220 | */ | |
2221 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2222 | { |
2223 | int i, r; | |
2224 | ||
2225 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 2226 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2227 | continue; |
e7854a03 AD |
2228 | /* displays are handled in phase1 */ |
2229 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2230 | continue; | |
d38ceaf9 | 2231 | /* XXX handle errors */ |
a1255107 | 2232 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2233 | /* XXX handle errors */ |
2c1a2784 | 2234 | if (r) { |
a1255107 AD |
2235 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2236 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2237 | } |
876923fb | 2238 | adev->ip_blocks[i].status.hw = false; |
a3a09142 AD |
2239 | /* handle putting the SMC in the appropriate state */ |
2240 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2241 | if (is_support_sw_smu(adev)) { | |
0e0b89c0 | 2242 | r = smu_set_mp1_state(&adev->smu, adev->mp1_state); |
a3a09142 | 2243 | } else if (adev->powerplay.pp_funcs && |
482f0e53 | 2244 | adev->powerplay.pp_funcs->set_mp1_state) { |
a3a09142 AD |
2245 | r = adev->powerplay.pp_funcs->set_mp1_state( |
2246 | adev->powerplay.pp_handle, | |
2247 | adev->mp1_state); | |
0e0b89c0 EQ |
2248 | } |
2249 | if (r) { | |
2250 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2251 | adev->mp1_state, r); | |
2252 | return r; | |
a3a09142 AD |
2253 | } |
2254 | } | |
b5507c7e AG |
2255 | |
2256 | adev->ip_blocks[i].status.hw = false; | |
d38ceaf9 AD |
2257 | } |
2258 | ||
2259 | return 0; | |
2260 | } | |
2261 | ||
e7854a03 AD |
2262 | /** |
2263 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2264 | * | |
2265 | * @adev: amdgpu_device pointer | |
2266 | * | |
2267 | * Main suspend function for hardware IPs. The list of all the hardware | |
2268 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2269 | * suspend callbacks are run. suspend puts the hardware and software state | |
2270 | * in each IP into a state suitable for suspend. | |
2271 | * Returns 0 on success, negative error code on failure. | |
2272 | */ | |
2273 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2274 | { | |
2275 | int r; | |
2276 | ||
e7819644 YT |
2277 | if (amdgpu_sriov_vf(adev)) |
2278 | amdgpu_virt_request_full_gpu(adev, false); | |
2279 | ||
e7854a03 AD |
2280 | r = amdgpu_device_ip_suspend_phase1(adev); |
2281 | if (r) | |
2282 | return r; | |
2283 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2284 | ||
e7819644 YT |
2285 | if (amdgpu_sriov_vf(adev)) |
2286 | amdgpu_virt_release_full_gpu(adev, false); | |
2287 | ||
e7854a03 AD |
2288 | return r; |
2289 | } | |
2290 | ||
06ec9070 | 2291 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2292 | { |
2293 | int i, r; | |
2294 | ||
2cb681b6 ML |
2295 | static enum amd_ip_block_type ip_order[] = { |
2296 | AMD_IP_BLOCK_TYPE_GMC, | |
2297 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2298 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2299 | AMD_IP_BLOCK_TYPE_IH, |
2300 | }; | |
a90ad3c2 | 2301 | |
2cb681b6 ML |
2302 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2303 | int j; | |
2304 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2305 | |
2cb681b6 ML |
2306 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2307 | block = &adev->ip_blocks[j]; | |
2308 | ||
482f0e53 | 2309 | block->status.hw = false; |
2cb681b6 ML |
2310 | if (block->version->type != ip_order[i] || |
2311 | !block->status.valid) | |
2312 | continue; | |
2313 | ||
2314 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2315 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2316 | if (r) |
2317 | return r; | |
482f0e53 | 2318 | block->status.hw = true; |
a90ad3c2 ML |
2319 | } |
2320 | } | |
2321 | ||
2322 | return 0; | |
2323 | } | |
2324 | ||
06ec9070 | 2325 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2326 | { |
2327 | int i, r; | |
2328 | ||
2cb681b6 ML |
2329 | static enum amd_ip_block_type ip_order[] = { |
2330 | AMD_IP_BLOCK_TYPE_SMC, | |
2331 | AMD_IP_BLOCK_TYPE_DCE, | |
2332 | AMD_IP_BLOCK_TYPE_GFX, | |
2333 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
2334 | AMD_IP_BLOCK_TYPE_UVD, |
2335 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 2336 | }; |
a90ad3c2 | 2337 | |
2cb681b6 ML |
2338 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2339 | int j; | |
2340 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2341 | |
2cb681b6 ML |
2342 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2343 | block = &adev->ip_blocks[j]; | |
2344 | ||
2345 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
2346 | !block->status.valid || |
2347 | block->status.hw) | |
2cb681b6 ML |
2348 | continue; |
2349 | ||
2350 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2351 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2352 | if (r) |
2353 | return r; | |
482f0e53 | 2354 | block->status.hw = true; |
a90ad3c2 ML |
2355 | } |
2356 | } | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
e3ecdffa AD |
2361 | /** |
2362 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2363 | * | |
2364 | * @adev: amdgpu_device pointer | |
2365 | * | |
2366 | * First resume function for hardware IPs. The list of all the hardware | |
2367 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2368 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2369 | * after a suspend and updates the software state as necessary. This | |
2370 | * function is also used for restoring the GPU after a GPU reset. | |
2371 | * Returns 0 on success, negative error code on failure. | |
2372 | */ | |
06ec9070 | 2373 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2374 | { |
2375 | int i, r; | |
2376 | ||
a90ad3c2 | 2377 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 2378 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 2379 | continue; |
a90ad3c2 | 2380 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2381 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2382 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 2383 | |
fcf0649f CZ |
2384 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2385 | if (r) { | |
2386 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2387 | adev->ip_blocks[i].version->funcs->name, r); | |
2388 | return r; | |
2389 | } | |
482f0e53 | 2390 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
2391 | } |
2392 | } | |
2393 | ||
2394 | return 0; | |
2395 | } | |
2396 | ||
e3ecdffa AD |
2397 | /** |
2398 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2399 | * | |
2400 | * @adev: amdgpu_device pointer | |
2401 | * | |
2402 | * First resume function for hardware IPs. The list of all the hardware | |
2403 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2404 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2405 | * functional state after a suspend and updates the software state as | |
2406 | * necessary. This function is also used for restoring the GPU after a GPU | |
2407 | * reset. | |
2408 | * Returns 0 on success, negative error code on failure. | |
2409 | */ | |
06ec9070 | 2410 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2411 | { |
2412 | int i, r; | |
2413 | ||
2414 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 2415 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2416 | continue; |
fcf0649f | 2417 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 2418 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
2419 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
2420 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 2421 | continue; |
a1255107 | 2422 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2423 | if (r) { |
a1255107 AD |
2424 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2425 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2426 | return r; |
2c1a2784 | 2427 | } |
482f0e53 | 2428 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
2429 | } |
2430 | ||
2431 | return 0; | |
2432 | } | |
2433 | ||
e3ecdffa AD |
2434 | /** |
2435 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2436 | * | |
2437 | * @adev: amdgpu_device pointer | |
2438 | * | |
2439 | * Main resume function for hardware IPs. The hardware IPs | |
2440 | * are split into two resume functions because they are | |
2441 | * are also used in in recovering from a GPU reset and some additional | |
2442 | * steps need to be take between them. In this case (S3/S4) they are | |
2443 | * run sequentially. | |
2444 | * Returns 0 on success, negative error code on failure. | |
2445 | */ | |
06ec9070 | 2446 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2447 | { |
2448 | int r; | |
2449 | ||
06ec9070 | 2450 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2451 | if (r) |
2452 | return r; | |
7a3e0bb2 RZ |
2453 | |
2454 | r = amdgpu_device_fw_loading(adev); | |
2455 | if (r) | |
2456 | return r; | |
2457 | ||
06ec9070 | 2458 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2459 | |
2460 | return r; | |
2461 | } | |
2462 | ||
e3ecdffa AD |
2463 | /** |
2464 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2465 | * | |
2466 | * @adev: amdgpu_device pointer | |
2467 | * | |
2468 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2469 | */ | |
4e99a44e | 2470 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2471 | { |
6867e1b5 ML |
2472 | if (amdgpu_sriov_vf(adev)) { |
2473 | if (adev->is_atom_fw) { | |
2474 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2475 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2476 | } else { | |
2477 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2478 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2479 | } | |
2480 | ||
2481 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2482 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2483 | } |
048765ad AR |
2484 | } |
2485 | ||
e3ecdffa AD |
2486 | /** |
2487 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2488 | * | |
2489 | * @asic_type: AMD asic type | |
2490 | * | |
2491 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2492 | * returns true if DC has support, false if not. | |
2493 | */ | |
4562236b HW |
2494 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2495 | { | |
2496 | switch (asic_type) { | |
2497 | #if defined(CONFIG_DRM_AMD_DC) | |
2498 | case CHIP_BONAIRE: | |
0d6fbccb | 2499 | case CHIP_KAVERI: |
367e6687 AD |
2500 | case CHIP_KABINI: |
2501 | case CHIP_MULLINS: | |
d9fda248 HW |
2502 | /* |
2503 | * We have systems in the wild with these ASICs that require | |
2504 | * LVDS and VGA support which is not supported with DC. | |
2505 | * | |
2506 | * Fallback to the non-DC driver here by default so as not to | |
2507 | * cause regressions. | |
2508 | */ | |
2509 | return amdgpu_dc > 0; | |
2510 | case CHIP_HAWAII: | |
4562236b HW |
2511 | case CHIP_CARRIZO: |
2512 | case CHIP_STONEY: | |
4562236b | 2513 | case CHIP_POLARIS10: |
675fd32b | 2514 | case CHIP_POLARIS11: |
2c8ad2d5 | 2515 | case CHIP_POLARIS12: |
675fd32b | 2516 | case CHIP_VEGAM: |
4562236b HW |
2517 | case CHIP_TONGA: |
2518 | case CHIP_FIJI: | |
42f8ffa1 | 2519 | case CHIP_VEGA10: |
dca7b401 | 2520 | case CHIP_VEGA12: |
c6034aa2 | 2521 | case CHIP_VEGA20: |
dc37a9a0 | 2522 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
fd187853 | 2523 | case CHIP_RAVEN: |
b4f199c7 HW |
2524 | #endif |
2525 | #if defined(CONFIG_DRM_AMD_DC_DCN2_0) | |
2526 | case CHIP_NAVI10: | |
8fceceb6 | 2527 | case CHIP_NAVI14: |
078655d9 | 2528 | case CHIP_NAVI12: |
e1c14c43 RL |
2529 | #endif |
2530 | #if defined(CONFIG_DRM_AMD_DC_DCN2_1) | |
2531 | case CHIP_RENOIR: | |
42f8ffa1 | 2532 | #endif |
fd187853 | 2533 | return amdgpu_dc != 0; |
4562236b HW |
2534 | #endif |
2535 | default: | |
2536 | return false; | |
2537 | } | |
2538 | } | |
2539 | ||
2540 | /** | |
2541 | * amdgpu_device_has_dc_support - check if dc is supported | |
2542 | * | |
2543 | * @adev: amdgpu_device_pointer | |
2544 | * | |
2545 | * Returns true for supported, false for not supported | |
2546 | */ | |
2547 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2548 | { | |
2555039d XY |
2549 | if (amdgpu_sriov_vf(adev)) |
2550 | return false; | |
2551 | ||
4562236b HW |
2552 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2553 | } | |
2554 | ||
d4535e2c AG |
2555 | |
2556 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) | |
2557 | { | |
2558 | struct amdgpu_device *adev = | |
2559 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
2560 | ||
2561 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
2562 | if (adev->asic_reset_res) | |
fed184e9 | 2563 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
d4535e2c AG |
2564 | adev->asic_reset_res, adev->ddev->unique); |
2565 | } | |
2566 | ||
71f98027 AD |
2567 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
2568 | { | |
2569 | char *input = amdgpu_lockup_timeout; | |
2570 | char *timeout_setting = NULL; | |
2571 | int index = 0; | |
2572 | long timeout; | |
2573 | int ret = 0; | |
2574 | ||
2575 | /* | |
2576 | * By default timeout for non compute jobs is 10000. | |
2577 | * And there is no timeout enforced on compute jobs. | |
2578 | * In SR-IOV or passthrough mode, timeout for compute | |
2579 | * jobs are 10000 by default. | |
2580 | */ | |
2581 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
2582 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
2583 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) | |
2584 | adev->compute_timeout = adev->gfx_timeout; | |
2585 | else | |
2586 | adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; | |
2587 | ||
2588 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { | |
2589 | while ((timeout_setting = strsep(&input, ",")) && | |
2590 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { | |
2591 | ret = kstrtol(timeout_setting, 0, &timeout); | |
2592 | if (ret) | |
2593 | return ret; | |
2594 | ||
2595 | if (timeout == 0) { | |
2596 | index++; | |
2597 | continue; | |
2598 | } else if (timeout < 0) { | |
2599 | timeout = MAX_SCHEDULE_TIMEOUT; | |
2600 | } else { | |
2601 | timeout = msecs_to_jiffies(timeout); | |
2602 | } | |
2603 | ||
2604 | switch (index++) { | |
2605 | case 0: | |
2606 | adev->gfx_timeout = timeout; | |
2607 | break; | |
2608 | case 1: | |
2609 | adev->compute_timeout = timeout; | |
2610 | break; | |
2611 | case 2: | |
2612 | adev->sdma_timeout = timeout; | |
2613 | break; | |
2614 | case 3: | |
2615 | adev->video_timeout = timeout; | |
2616 | break; | |
2617 | default: | |
2618 | break; | |
2619 | } | |
2620 | } | |
2621 | /* | |
2622 | * There is only one value specified and | |
2623 | * it should apply to all non-compute jobs. | |
2624 | */ | |
2625 | if (index == 1) | |
2626 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
2627 | } | |
2628 | ||
2629 | return ret; | |
2630 | } | |
d4535e2c | 2631 | |
d38ceaf9 AD |
2632 | /** |
2633 | * amdgpu_device_init - initialize the driver | |
2634 | * | |
2635 | * @adev: amdgpu_device pointer | |
87e3f136 | 2636 | * @ddev: drm dev pointer |
d38ceaf9 AD |
2637 | * @pdev: pci dev pointer |
2638 | * @flags: driver flags | |
2639 | * | |
2640 | * Initializes the driver info and hw (all asics). | |
2641 | * Returns 0 for success or an error on failure. | |
2642 | * Called at driver startup. | |
2643 | */ | |
2644 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2645 | struct drm_device *ddev, | |
2646 | struct pci_dev *pdev, | |
2647 | uint32_t flags) | |
2648 | { | |
2649 | int r, i; | |
2650 | bool runtime = false; | |
95844d20 | 2651 | u32 max_MBps; |
d38ceaf9 AD |
2652 | |
2653 | adev->shutdown = false; | |
2654 | adev->dev = &pdev->dev; | |
2655 | adev->ddev = ddev; | |
2656 | adev->pdev = pdev; | |
2657 | adev->flags = flags; | |
4e66d7d2 YZ |
2658 | |
2659 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
2660 | adev->asic_type = amdgpu_force_asic_type; | |
2661 | else | |
2662 | adev->asic_type = flags & AMD_ASIC_MASK; | |
2663 | ||
d38ceaf9 | 2664 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 SL |
2665 | if (amdgpu_emu_mode == 1) |
2666 | adev->usec_timeout *= 2; | |
770d13b1 | 2667 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2668 | adev->accel_working = false; |
2669 | adev->num_rings = 0; | |
2670 | adev->mman.buffer_funcs = NULL; | |
2671 | adev->mman.buffer_funcs_ring = NULL; | |
2672 | adev->vm_manager.vm_pte_funcs = NULL; | |
3798e9a6 | 2673 | adev->vm_manager.vm_pte_num_rqs = 0; |
132f34e4 | 2674 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 2675 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2676 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2677 | |
2678 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2679 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2680 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2681 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2682 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2683 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
2684 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
2685 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
2686 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2687 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2688 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2689 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2690 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2691 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2692 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2693 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2694 | ||
3e39ab90 AD |
2695 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2696 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2697 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2698 | |
2699 | /* mutex initialization are all done here so we | |
2700 | * can recall function without having locking issues */ | |
d38ceaf9 | 2701 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2702 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2703 | mutex_init(&adev->pm.mutex); |
2704 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2705 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2706 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 2707 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 2708 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2709 | mutex_init(&adev->mn_lock); |
e23b74aa | 2710 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 2711 | hash_init(adev->mn_hash); |
13a752e3 | 2712 | mutex_init(&adev->lock_reset); |
bb5a2bdf | 2713 | mutex_init(&adev->virt.dpm_mutex); |
32eaeae0 | 2714 | mutex_init(&adev->psp.mutex); |
d38ceaf9 | 2715 | |
912dfc84 EQ |
2716 | r = amdgpu_device_check_arguments(adev); |
2717 | if (r) | |
2718 | return r; | |
d38ceaf9 | 2719 | |
d38ceaf9 AD |
2720 | spin_lock_init(&adev->mmio_idx_lock); |
2721 | spin_lock_init(&adev->smc_idx_lock); | |
2722 | spin_lock_init(&adev->pcie_idx_lock); | |
2723 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2724 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2725 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2726 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2727 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2728 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2729 | |
0c4e7fa5 CZ |
2730 | INIT_LIST_HEAD(&adev->shadow_list); |
2731 | mutex_init(&adev->shadow_list_lock); | |
2732 | ||
795f2813 AR |
2733 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2734 | spin_lock_init(&adev->ring_lru_list_lock); | |
2735 | ||
beff74bc AD |
2736 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
2737 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
2738 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
2739 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 2740 | |
d4535e2c AG |
2741 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
2742 | ||
d23ee13f | 2743 | adev->gfx.gfx_off_req_count = 1; |
b1ddf548 RZ |
2744 | adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false; |
2745 | ||
0fa49558 AX |
2746 | /* Registers mapping */ |
2747 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2748 | if (adev->asic_type >= CHIP_BONAIRE) { |
2749 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2750 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2751 | } else { | |
2752 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2753 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2754 | } | |
d38ceaf9 | 2755 | |
d38ceaf9 AD |
2756 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2757 | if (adev->rmmio == NULL) { | |
2758 | return -ENOMEM; | |
2759 | } | |
2760 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2761 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2762 | ||
d38ceaf9 AD |
2763 | /* io port mapping */ |
2764 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2765 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2766 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2767 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2768 | break; | |
2769 | } | |
2770 | } | |
2771 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2772 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 2773 | |
b2109d8e JX |
2774 | /* enable PCIE atomic ops */ |
2775 | r = pci_enable_atomic_ops_to_root(adev->pdev, | |
2776 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
2777 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
2778 | if (r) { | |
2779 | adev->have_atomics_support = false; | |
2780 | DRM_INFO("PCIE atomic ops is not supported\n"); | |
2781 | } else { | |
2782 | adev->have_atomics_support = true; | |
2783 | } | |
2784 | ||
5494d864 AD |
2785 | amdgpu_device_get_pcie_info(adev); |
2786 | ||
b239c017 JX |
2787 | if (amdgpu_mcbp) |
2788 | DRM_INFO("MCBP is enabled\n"); | |
2789 | ||
5f84cc63 JX |
2790 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
2791 | adev->enable_mes = true; | |
2792 | ||
f54eeab4 | 2793 | if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) { |
a190d1c7 XY |
2794 | r = amdgpu_discovery_init(adev); |
2795 | if (r) { | |
2796 | dev_err(adev->dev, "amdgpu_discovery_init failed\n"); | |
2797 | return r; | |
2798 | } | |
2799 | } | |
2800 | ||
d38ceaf9 | 2801 | /* early init functions */ |
06ec9070 | 2802 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
2803 | if (r) |
2804 | return r; | |
2805 | ||
df99ac0f JZ |
2806 | r = amdgpu_device_get_job_timeout_settings(adev); |
2807 | if (r) { | |
2808 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
2809 | return r; | |
2810 | } | |
2811 | ||
6585661d OZ |
2812 | /* doorbell bar mapping and doorbell index init*/ |
2813 | amdgpu_device_doorbell_init(adev); | |
2814 | ||
d38ceaf9 AD |
2815 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
2816 | /* this will fail for cards that aren't VGA class devices, just | |
2817 | * ignore it */ | |
06ec9070 | 2818 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 2819 | |
e9bef455 | 2820 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2821 | runtime = true; |
84c8b22e LW |
2822 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2823 | vga_switcheroo_register_client(adev->pdev, | |
2824 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2825 | if (runtime) |
2826 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2827 | ||
9475a943 SL |
2828 | if (amdgpu_emu_mode == 1) { |
2829 | /* post the asic on emulation mode */ | |
2830 | emu_soc_asic_init(adev); | |
bfca0289 | 2831 | goto fence_driver_init; |
9475a943 | 2832 | } |
bfca0289 | 2833 | |
4e99a44e ML |
2834 | /* detect if we are with an SRIOV vbios */ |
2835 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2836 | |
95e8e59e AD |
2837 | /* check if we need to reset the asic |
2838 | * E.g., driver was not cleanly unloaded previously, etc. | |
2839 | */ | |
f14899fd | 2840 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
95e8e59e AD |
2841 | r = amdgpu_asic_reset(adev); |
2842 | if (r) { | |
2843 | dev_err(adev->dev, "asic reset on init failed\n"); | |
2844 | goto failed; | |
2845 | } | |
2846 | } | |
2847 | ||
d38ceaf9 | 2848 | /* Post card if necessary */ |
39c640c0 | 2849 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 2850 | if (!adev->bios) { |
bec86378 | 2851 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2852 | r = -EINVAL; |
2853 | goto failed; | |
d38ceaf9 | 2854 | } |
bec86378 | 2855 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2856 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2857 | if (r) { | |
2858 | dev_err(adev->dev, "gpu post error!\n"); | |
2859 | goto failed; | |
2860 | } | |
d38ceaf9 AD |
2861 | } |
2862 | ||
88b64e95 AD |
2863 | if (adev->is_atom_fw) { |
2864 | /* Initialize clocks */ | |
2865 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2866 | if (r) { | |
2867 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2868 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2869 | goto failed; |
2870 | } | |
2871 | } else { | |
a5bde2f9 AD |
2872 | /* Initialize clocks */ |
2873 | r = amdgpu_atombios_get_clock_info(adev); | |
2874 | if (r) { | |
2875 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2876 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2877 | goto failed; |
a5bde2f9 AD |
2878 | } |
2879 | /* init i2c buses */ | |
4562236b HW |
2880 | if (!amdgpu_device_has_dc_support(adev)) |
2881 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2882 | } |
d38ceaf9 | 2883 | |
bfca0289 | 2884 | fence_driver_init: |
d38ceaf9 AD |
2885 | /* Fence driver */ |
2886 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2887 | if (r) { |
2888 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2889 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2890 | goto failed; |
2c1a2784 | 2891 | } |
d38ceaf9 AD |
2892 | |
2893 | /* init the mode config */ | |
2894 | drm_mode_config_init(adev->ddev); | |
2895 | ||
06ec9070 | 2896 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 2897 | if (r) { |
8840a387 | 2898 | /* failed in exclusive mode due to timeout */ |
2899 | if (amdgpu_sriov_vf(adev) && | |
2900 | !amdgpu_sriov_runtime(adev) && | |
2901 | amdgpu_virt_mmio_blocked(adev) && | |
2902 | !amdgpu_virt_wait_reset(adev)) { | |
2903 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
2904 | /* Don't send request since VF is inactive. */ |
2905 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
2906 | adev->virt.ops = NULL; | |
8840a387 | 2907 | r = -EAGAIN; |
2908 | goto failed; | |
2909 | } | |
06ec9070 | 2910 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 2911 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
72d3f592 ED |
2912 | if (amdgpu_virt_request_full_gpu(adev, false)) |
2913 | amdgpu_virt_release_full_gpu(adev, false); | |
83ba126a | 2914 | goto failed; |
d38ceaf9 AD |
2915 | } |
2916 | ||
2917 | adev->accel_working = true; | |
2918 | ||
e59c0205 AX |
2919 | amdgpu_vm_check_compute_bug(adev); |
2920 | ||
95844d20 MO |
2921 | /* Initialize the buffer migration limit. */ |
2922 | if (amdgpu_moverate >= 0) | |
2923 | max_MBps = amdgpu_moverate; | |
2924 | else | |
2925 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2926 | /* Get a log2 for easy divisions. */ | |
2927 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2928 | ||
9bc92b9c ML |
2929 | amdgpu_fbdev_init(adev); |
2930 | ||
e9bc1bf7 YT |
2931 | if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)) |
2932 | amdgpu_pm_virt_sysfs_init(adev); | |
2933 | ||
d2f52ac8 RZ |
2934 | r = amdgpu_pm_sysfs_init(adev); |
2935 | if (r) | |
2936 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2937 | ||
5bb23532 OM |
2938 | r = amdgpu_ucode_sysfs_init(adev); |
2939 | if (r) | |
2940 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); | |
2941 | ||
75758255 | 2942 | r = amdgpu_debugfs_gem_init(adev); |
3f14e623 | 2943 | if (r) |
d38ceaf9 | 2944 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2945 | |
2946 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2947 | if (r) |
d38ceaf9 | 2948 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2949 | |
50ab2533 | 2950 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2951 | if (r) |
50ab2533 | 2952 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2953 | |
763efb6c | 2954 | r = amdgpu_debugfs_init(adev); |
db95e218 | 2955 | if (r) |
763efb6c | 2956 | DRM_ERROR("Creating debugfs files failed (%d).\n", r); |
db95e218 | 2957 | |
d38ceaf9 AD |
2958 | if ((amdgpu_testing & 1)) { |
2959 | if (adev->accel_working) | |
2960 | amdgpu_test_moves(adev); | |
2961 | else | |
2962 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2963 | } | |
d38ceaf9 AD |
2964 | if (amdgpu_benchmarking) { |
2965 | if (adev->accel_working) | |
2966 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2967 | else | |
2968 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2969 | } | |
2970 | ||
2971 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2972 | * explicit gating rather than handling it automatically. | |
2973 | */ | |
06ec9070 | 2974 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 2975 | if (r) { |
06ec9070 | 2976 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 2977 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2978 | goto failed; |
2c1a2784 | 2979 | } |
d38ceaf9 | 2980 | |
108c6a63 | 2981 | /* must succeed. */ |
511fdbc3 | 2982 | amdgpu_ras_resume(adev); |
108c6a63 | 2983 | |
beff74bc AD |
2984 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
2985 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2986 | ||
dcea6e65 KR |
2987 | r = device_create_file(adev->dev, &dev_attr_pcie_replay_count); |
2988 | if (r) { | |
2989 | dev_err(adev->dev, "Could not create pcie_replay_count"); | |
2990 | return r; | |
2991 | } | |
108c6a63 | 2992 | |
d155bef0 AB |
2993 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
2994 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
2995 | if (r) |
2996 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
2997 | ||
d38ceaf9 | 2998 | return 0; |
83ba126a AD |
2999 | |
3000 | failed: | |
89041940 | 3001 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
3002 | if (runtime) |
3003 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 3004 | |
83ba126a | 3005 | return r; |
d38ceaf9 AD |
3006 | } |
3007 | ||
d38ceaf9 AD |
3008 | /** |
3009 | * amdgpu_device_fini - tear down the driver | |
3010 | * | |
3011 | * @adev: amdgpu_device pointer | |
3012 | * | |
3013 | * Tear down the driver info (all asics). | |
3014 | * Called at driver shutdown. | |
3015 | */ | |
3016 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
3017 | { | |
3018 | int r; | |
3019 | ||
3020 | DRM_INFO("amdgpu: finishing device.\n"); | |
3021 | adev->shutdown = true; | |
e5b03032 ML |
3022 | /* disable all interrupts */ |
3023 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
3024 | if (adev->mode_info.mode_config_initialized){ |
3025 | if (!amdgpu_device_has_dc_support(adev)) | |
c2d88e06 | 3026 | drm_helper_force_disable_all(adev->ddev); |
ff97cba8 ML |
3027 | else |
3028 | drm_atomic_helper_shutdown(adev->ddev); | |
3029 | } | |
d38ceaf9 | 3030 | amdgpu_fence_driver_fini(adev); |
58e955d9 | 3031 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 3032 | amdgpu_fbdev_fini(adev); |
06ec9070 | 3033 | r = amdgpu_device_ip_fini(adev); |
ab4fe3e1 HR |
3034 | if (adev->firmware.gpu_info_fw) { |
3035 | release_firmware(adev->firmware.gpu_info_fw); | |
3036 | adev->firmware.gpu_info_fw = NULL; | |
3037 | } | |
d38ceaf9 | 3038 | adev->accel_working = false; |
beff74bc | 3039 | cancel_delayed_work_sync(&adev->delayed_init_work); |
d38ceaf9 | 3040 | /* free i2c buses */ |
4562236b HW |
3041 | if (!amdgpu_device_has_dc_support(adev)) |
3042 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3043 | |
3044 | if (amdgpu_emu_mode != 1) | |
3045 | amdgpu_atombios_fini(adev); | |
3046 | ||
d38ceaf9 AD |
3047 | kfree(adev->bios); |
3048 | adev->bios = NULL; | |
84c8b22e LW |
3049 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
3050 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
3051 | if (adev->flags & AMD_IS_PX) |
3052 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
3053 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
3054 | if (adev->rio_mem) | |
3055 | pci_iounmap(adev->pdev, adev->rio_mem); | |
3056 | adev->rio_mem = NULL; | |
3057 | iounmap(adev->rmmio); | |
3058 | adev->rmmio = NULL; | |
06ec9070 | 3059 | amdgpu_device_doorbell_fini(adev); |
e9bc1bf7 YT |
3060 | if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)) |
3061 | amdgpu_pm_virt_sysfs_fini(adev); | |
3062 | ||
d38ceaf9 | 3063 | amdgpu_debugfs_regs_cleanup(adev); |
dcea6e65 | 3064 | device_remove_file(adev->dev, &dev_attr_pcie_replay_count); |
5bb23532 | 3065 | amdgpu_ucode_sysfs_fini(adev); |
d155bef0 AB |
3066 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3067 | amdgpu_pmu_fini(adev); | |
6698a3d0 | 3068 | amdgpu_debugfs_preempt_cleanup(adev); |
f54eeab4 | 3069 | if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) |
a190d1c7 | 3070 | amdgpu_discovery_fini(adev); |
d38ceaf9 AD |
3071 | } |
3072 | ||
3073 | ||
3074 | /* | |
3075 | * Suspend & resume. | |
3076 | */ | |
3077 | /** | |
810ddc3a | 3078 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3079 | * |
87e3f136 DP |
3080 | * @dev: drm dev pointer |
3081 | * @suspend: suspend state | |
3082 | * @fbcon : notify the fbdev of suspend | |
d38ceaf9 AD |
3083 | * |
3084 | * Puts the hw in the suspend state (all asics). | |
3085 | * Returns 0 for success or an error on failure. | |
3086 | * Called at driver suspend. | |
3087 | */ | |
810ddc3a | 3088 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
3089 | { |
3090 | struct amdgpu_device *adev; | |
3091 | struct drm_crtc *crtc; | |
3092 | struct drm_connector *connector; | |
f8d2d39e | 3093 | struct drm_connector_list_iter iter; |
5ceb54c6 | 3094 | int r; |
d38ceaf9 AD |
3095 | |
3096 | if (dev == NULL || dev->dev_private == NULL) { | |
3097 | return -ENODEV; | |
3098 | } | |
3099 | ||
3100 | adev = dev->dev_private; | |
3101 | ||
3102 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3103 | return 0; | |
3104 | ||
44779b43 | 3105 | adev->in_suspend = true; |
d38ceaf9 AD |
3106 | drm_kms_helper_poll_disable(dev); |
3107 | ||
5f818173 S |
3108 | if (fbcon) |
3109 | amdgpu_fbdev_set_suspend(adev, 1); | |
3110 | ||
beff74bc | 3111 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3112 | |
4562236b HW |
3113 | if (!amdgpu_device_has_dc_support(adev)) { |
3114 | /* turn off display hw */ | |
3115 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3116 | drm_connector_list_iter_begin(dev, &iter); |
3117 | drm_for_each_connector_iter(connector, &iter) | |
3118 | drm_helper_connector_dpms(connector, | |
3119 | DRM_MODE_DPMS_OFF); | |
3120 | drm_connector_list_iter_end(&iter); | |
4562236b | 3121 | drm_modeset_unlock_all(dev); |
fe1053b7 AD |
3122 | /* unpin the front buffers and cursors */ |
3123 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3124 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3125 | struct drm_framebuffer *fb = crtc->primary->fb; | |
3126 | struct amdgpu_bo *robj; | |
3127 | ||
91334223 | 3128 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3129 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3130 | r = amdgpu_bo_reserve(aobj, true); | |
3131 | if (r == 0) { | |
3132 | amdgpu_bo_unpin(aobj); | |
3133 | amdgpu_bo_unreserve(aobj); | |
3134 | } | |
756e6880 | 3135 | } |
756e6880 | 3136 | |
fe1053b7 AD |
3137 | if (fb == NULL || fb->obj[0] == NULL) { |
3138 | continue; | |
3139 | } | |
3140 | robj = gem_to_amdgpu_bo(fb->obj[0]); | |
3141 | /* don't unpin kernel fb objects */ | |
3142 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
3143 | r = amdgpu_bo_reserve(robj, true); | |
3144 | if (r == 0) { | |
3145 | amdgpu_bo_unpin(robj); | |
3146 | amdgpu_bo_unreserve(robj); | |
3147 | } | |
d38ceaf9 AD |
3148 | } |
3149 | } | |
3150 | } | |
fe1053b7 AD |
3151 | |
3152 | amdgpu_amdkfd_suspend(adev); | |
3153 | ||
5e6932fe | 3154 | amdgpu_ras_suspend(adev); |
3155 | ||
fe1053b7 AD |
3156 | r = amdgpu_device_ip_suspend_phase1(adev); |
3157 | ||
d38ceaf9 AD |
3158 | /* evict vram memory */ |
3159 | amdgpu_bo_evict_vram(adev); | |
3160 | ||
5ceb54c6 | 3161 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 3162 | |
fe1053b7 | 3163 | r = amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 3164 | |
a0a71e49 AD |
3165 | /* evict remaining vram memory |
3166 | * This second call to evict vram is to evict the gart page table | |
3167 | * using the CPU. | |
3168 | */ | |
d38ceaf9 AD |
3169 | amdgpu_bo_evict_vram(adev); |
3170 | ||
3171 | pci_save_state(dev->pdev); | |
3172 | if (suspend) { | |
3173 | /* Shut down the device */ | |
3174 | pci_disable_device(dev->pdev); | |
3175 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 3176 | } else { |
3177 | r = amdgpu_asic_reset(adev); | |
3178 | if (r) | |
3179 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
3180 | } |
3181 | ||
d38ceaf9 AD |
3182 | return 0; |
3183 | } | |
3184 | ||
3185 | /** | |
810ddc3a | 3186 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 3187 | * |
87e3f136 DP |
3188 | * @dev: drm dev pointer |
3189 | * @resume: resume state | |
3190 | * @fbcon : notify the fbdev of resume | |
d38ceaf9 AD |
3191 | * |
3192 | * Bring the hw back to operating state (all asics). | |
3193 | * Returns 0 for success or an error on failure. | |
3194 | * Called at driver resume. | |
3195 | */ | |
810ddc3a | 3196 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
3197 | { |
3198 | struct drm_connector *connector; | |
f8d2d39e | 3199 | struct drm_connector_list_iter iter; |
d38ceaf9 | 3200 | struct amdgpu_device *adev = dev->dev_private; |
756e6880 | 3201 | struct drm_crtc *crtc; |
03161a6e | 3202 | int r = 0; |
d38ceaf9 AD |
3203 | |
3204 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3205 | return 0; | |
3206 | ||
d38ceaf9 AD |
3207 | if (resume) { |
3208 | pci_set_power_state(dev->pdev, PCI_D0); | |
3209 | pci_restore_state(dev->pdev); | |
74b0b157 | 3210 | r = pci_enable_device(dev->pdev); |
03161a6e | 3211 | if (r) |
4d3b9ae5 | 3212 | return r; |
d38ceaf9 AD |
3213 | } |
3214 | ||
3215 | /* post card */ | |
39c640c0 | 3216 | if (amdgpu_device_need_post(adev)) { |
74b0b157 | 3217 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
3218 | if (r) | |
3219 | DRM_ERROR("amdgpu asic init failed\n"); | |
3220 | } | |
d38ceaf9 | 3221 | |
06ec9070 | 3222 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 3223 | if (r) { |
06ec9070 | 3224 | DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 3225 | return r; |
e6707218 | 3226 | } |
5ceb54c6 AD |
3227 | amdgpu_fence_driver_resume(adev); |
3228 | ||
d38ceaf9 | 3229 | |
06ec9070 | 3230 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 3231 | if (r) |
4d3b9ae5 | 3232 | return r; |
d38ceaf9 | 3233 | |
beff74bc AD |
3234 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3235 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3236 | ||
fe1053b7 AD |
3237 | if (!amdgpu_device_has_dc_support(adev)) { |
3238 | /* pin cursors */ | |
3239 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3240 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3241 | ||
91334223 | 3242 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3243 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3244 | r = amdgpu_bo_reserve(aobj, true); | |
3245 | if (r == 0) { | |
3246 | r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); | |
3247 | if (r != 0) | |
3248 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
3249 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); | |
3250 | amdgpu_bo_unreserve(aobj); | |
3251 | } | |
756e6880 AD |
3252 | } |
3253 | } | |
3254 | } | |
ba997709 YZ |
3255 | r = amdgpu_amdkfd_resume(adev); |
3256 | if (r) | |
3257 | return r; | |
756e6880 | 3258 | |
96a5d8d4 | 3259 | /* Make sure IB tests flushed */ |
beff74bc | 3260 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 3261 | |
d38ceaf9 AD |
3262 | /* blat the mode back in */ |
3263 | if (fbcon) { | |
4562236b HW |
3264 | if (!amdgpu_device_has_dc_support(adev)) { |
3265 | /* pre DCE11 */ | |
3266 | drm_helper_resume_force_mode(dev); | |
3267 | ||
3268 | /* turn on display hw */ | |
3269 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3270 | |
3271 | drm_connector_list_iter_begin(dev, &iter); | |
3272 | drm_for_each_connector_iter(connector, &iter) | |
3273 | drm_helper_connector_dpms(connector, | |
3274 | DRM_MODE_DPMS_ON); | |
3275 | drm_connector_list_iter_end(&iter); | |
3276 | ||
4562236b | 3277 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 3278 | } |
4d3b9ae5 | 3279 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
3280 | } |
3281 | ||
3282 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 3283 | |
5e6932fe | 3284 | amdgpu_ras_resume(adev); |
3285 | ||
23a1a9e5 L |
3286 | /* |
3287 | * Most of the connector probing functions try to acquire runtime pm | |
3288 | * refs to ensure that the GPU is powered on when connector polling is | |
3289 | * performed. Since we're calling this from a runtime PM callback, | |
3290 | * trying to acquire rpm refs will cause us to deadlock. | |
3291 | * | |
3292 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
3293 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
3294 | */ | |
3295 | #ifdef CONFIG_PM | |
3296 | dev->dev->power.disable_depth++; | |
3297 | #endif | |
4562236b HW |
3298 | if (!amdgpu_device_has_dc_support(adev)) |
3299 | drm_helper_hpd_irq_event(dev); | |
3300 | else | |
3301 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
3302 | #ifdef CONFIG_PM |
3303 | dev->dev->power.disable_depth--; | |
3304 | #endif | |
44779b43 RZ |
3305 | adev->in_suspend = false; |
3306 | ||
4d3b9ae5 | 3307 | return 0; |
d38ceaf9 AD |
3308 | } |
3309 | ||
e3ecdffa AD |
3310 | /** |
3311 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
3312 | * | |
3313 | * @adev: amdgpu_device pointer | |
3314 | * | |
3315 | * The list of all the hardware IPs that make up the asic is walked and | |
3316 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
3317 | * if the asic is still hung or not. | |
3318 | * Returns true if any of the IPs are still in a hung state, false if not. | |
3319 | */ | |
06ec9070 | 3320 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
3321 | { |
3322 | int i; | |
3323 | bool asic_hang = false; | |
3324 | ||
f993d628 ML |
3325 | if (amdgpu_sriov_vf(adev)) |
3326 | return true; | |
3327 | ||
8bc04c29 AD |
3328 | if (amdgpu_asic_need_full_reset(adev)) |
3329 | return true; | |
3330 | ||
63fbf42f | 3331 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3332 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 3333 | continue; |
a1255107 AD |
3334 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
3335 | adev->ip_blocks[i].status.hang = | |
3336 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
3337 | if (adev->ip_blocks[i].status.hang) { | |
3338 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
3339 | asic_hang = true; |
3340 | } | |
3341 | } | |
3342 | return asic_hang; | |
3343 | } | |
3344 | ||
e3ecdffa AD |
3345 | /** |
3346 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
3347 | * | |
3348 | * @adev: amdgpu_device pointer | |
3349 | * | |
3350 | * The list of all the hardware IPs that make up the asic is walked and the | |
3351 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
3352 | * handles any IP specific hardware or software state changes that are | |
3353 | * necessary for a soft reset to succeed. | |
3354 | * Returns 0 on success, negative error code on failure. | |
3355 | */ | |
06ec9070 | 3356 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
3357 | { |
3358 | int i, r = 0; | |
3359 | ||
3360 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3361 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 3362 | continue; |
a1255107 AD |
3363 | if (adev->ip_blocks[i].status.hang && |
3364 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
3365 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
3366 | if (r) |
3367 | return r; | |
3368 | } | |
3369 | } | |
3370 | ||
3371 | return 0; | |
3372 | } | |
3373 | ||
e3ecdffa AD |
3374 | /** |
3375 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
3376 | * | |
3377 | * @adev: amdgpu_device pointer | |
3378 | * | |
3379 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
3380 | * reset is necessary to recover. | |
3381 | * Returns true if a full asic reset is required, false if not. | |
3382 | */ | |
06ec9070 | 3383 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 3384 | { |
da146d3b AD |
3385 | int i; |
3386 | ||
8bc04c29 AD |
3387 | if (amdgpu_asic_need_full_reset(adev)) |
3388 | return true; | |
3389 | ||
da146d3b | 3390 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3391 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 3392 | continue; |
a1255107 AD |
3393 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
3394 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
3395 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
3396 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
3397 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 3398 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
3399 | DRM_INFO("Some block need full reset!\n"); |
3400 | return true; | |
3401 | } | |
3402 | } | |
35d782fe CZ |
3403 | } |
3404 | return false; | |
3405 | } | |
3406 | ||
e3ecdffa AD |
3407 | /** |
3408 | * amdgpu_device_ip_soft_reset - do a soft reset | |
3409 | * | |
3410 | * @adev: amdgpu_device pointer | |
3411 | * | |
3412 | * The list of all the hardware IPs that make up the asic is walked and the | |
3413 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
3414 | * IP specific hardware or software state changes that are necessary to soft | |
3415 | * reset the IP. | |
3416 | * Returns 0 on success, negative error code on failure. | |
3417 | */ | |
06ec9070 | 3418 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3419 | { |
3420 | int i, r = 0; | |
3421 | ||
3422 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3423 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3424 | continue; |
a1255107 AD |
3425 | if (adev->ip_blocks[i].status.hang && |
3426 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
3427 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
3428 | if (r) |
3429 | return r; | |
3430 | } | |
3431 | } | |
3432 | ||
3433 | return 0; | |
3434 | } | |
3435 | ||
e3ecdffa AD |
3436 | /** |
3437 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
3438 | * | |
3439 | * @adev: amdgpu_device pointer | |
3440 | * | |
3441 | * The list of all the hardware IPs that make up the asic is walked and the | |
3442 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
3443 | * handles any IP specific hardware or software state changes that are | |
3444 | * necessary after the IP has been soft reset. | |
3445 | * Returns 0 on success, negative error code on failure. | |
3446 | */ | |
06ec9070 | 3447 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3448 | { |
3449 | int i, r = 0; | |
3450 | ||
3451 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3452 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3453 | continue; |
a1255107 AD |
3454 | if (adev->ip_blocks[i].status.hang && |
3455 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
3456 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
3457 | if (r) |
3458 | return r; | |
3459 | } | |
3460 | ||
3461 | return 0; | |
3462 | } | |
3463 | ||
e3ecdffa | 3464 | /** |
c33adbc7 | 3465 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
3466 | * |
3467 | * @adev: amdgpu_device pointer | |
3468 | * | |
3469 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
3470 | * restore things like GPUVM page tables after a GPU reset where | |
3471 | * the contents of VRAM might be lost. | |
403009bf CK |
3472 | * |
3473 | * Returns: | |
3474 | * 0 on success, negative error code on failure. | |
e3ecdffa | 3475 | */ |
c33adbc7 | 3476 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 3477 | { |
c41d1cf6 | 3478 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf CK |
3479 | struct amdgpu_bo *shadow; |
3480 | long r = 1, tmo; | |
c41d1cf6 ML |
3481 | |
3482 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 3483 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
3484 | else |
3485 | tmo = msecs_to_jiffies(100); | |
3486 | ||
3487 | DRM_INFO("recover vram bo from shadow start\n"); | |
3488 | mutex_lock(&adev->shadow_list_lock); | |
403009bf CK |
3489 | list_for_each_entry(shadow, &adev->shadow_list, shadow_list) { |
3490 | ||
3491 | /* No need to recover an evicted BO */ | |
3492 | if (shadow->tbo.mem.mem_type != TTM_PL_TT || | |
b575f10d | 3493 | shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET || |
403009bf CK |
3494 | shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM) |
3495 | continue; | |
3496 | ||
3497 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
3498 | if (r) | |
3499 | break; | |
3500 | ||
c41d1cf6 | 3501 | if (fence) { |
1712fb1a | 3502 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
3503 | dma_fence_put(fence); |
3504 | fence = next; | |
1712fb1a | 3505 | if (tmo == 0) { |
3506 | r = -ETIMEDOUT; | |
c41d1cf6 | 3507 | break; |
1712fb1a | 3508 | } else if (tmo < 0) { |
3509 | r = tmo; | |
3510 | break; | |
3511 | } | |
403009bf CK |
3512 | } else { |
3513 | fence = next; | |
c41d1cf6 | 3514 | } |
c41d1cf6 ML |
3515 | } |
3516 | mutex_unlock(&adev->shadow_list_lock); | |
3517 | ||
403009bf CK |
3518 | if (fence) |
3519 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
3520 | dma_fence_put(fence); |
3521 | ||
1712fb1a | 3522 | if (r < 0 || tmo <= 0) { |
3523 | DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); | |
403009bf CK |
3524 | return -EIO; |
3525 | } | |
c41d1cf6 | 3526 | |
403009bf CK |
3527 | DRM_INFO("recover vram bo from shadow done\n"); |
3528 | return 0; | |
c41d1cf6 ML |
3529 | } |
3530 | ||
a90ad3c2 | 3531 | |
e3ecdffa | 3532 | /** |
06ec9070 | 3533 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3534 | * |
3535 | * @adev: amdgpu device pointer | |
87e3f136 | 3536 | * @from_hypervisor: request from hypervisor |
5740682e ML |
3537 | * |
3538 | * do VF FLR and reinitialize Asic | |
3f48c681 | 3539 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
3540 | */ |
3541 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3542 | bool from_hypervisor) | |
5740682e ML |
3543 | { |
3544 | int r; | |
3545 | ||
3546 | if (from_hypervisor) | |
3547 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3548 | else | |
3549 | r = amdgpu_virt_reset_gpu(adev); | |
3550 | if (r) | |
3551 | return r; | |
a90ad3c2 | 3552 | |
f81e8d53 WL |
3553 | amdgpu_amdkfd_pre_reset(adev); |
3554 | ||
a90ad3c2 | 3555 | /* Resume IP prior to SMC */ |
06ec9070 | 3556 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3557 | if (r) |
3558 | goto error; | |
a90ad3c2 ML |
3559 | |
3560 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 3561 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 | 3562 | |
7a3e0bb2 RZ |
3563 | r = amdgpu_device_fw_loading(adev); |
3564 | if (r) | |
3565 | return r; | |
3566 | ||
a90ad3c2 | 3567 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 3568 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
3569 | if (r) |
3570 | goto error; | |
a90ad3c2 ML |
3571 | |
3572 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3573 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 3574 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 3575 | |
abc34253 | 3576 | error: |
d3c117e5 | 3577 | amdgpu_virt_init_data_exchange(adev); |
abc34253 | 3578 | amdgpu_virt_release_full_gpu(adev, true); |
c41d1cf6 | 3579 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 3580 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 3581 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 ML |
3582 | } |
3583 | ||
3584 | return r; | |
3585 | } | |
3586 | ||
12938fad CK |
3587 | /** |
3588 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
3589 | * | |
3590 | * @adev: amdgpu device pointer | |
3591 | * | |
3592 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
3593 | * a hung GPU. | |
3594 | */ | |
3595 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
3596 | { | |
3597 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
3598 | DRM_INFO("Timeout, but no hardware hang detected.\n"); | |
3599 | return false; | |
3600 | } | |
3601 | ||
3ba7b418 AG |
3602 | if (amdgpu_gpu_recovery == 0) |
3603 | goto disabled; | |
3604 | ||
3605 | if (amdgpu_sriov_vf(adev)) | |
3606 | return true; | |
3607 | ||
3608 | if (amdgpu_gpu_recovery == -1) { | |
3609 | switch (adev->asic_type) { | |
fc42d47c AG |
3610 | case CHIP_BONAIRE: |
3611 | case CHIP_HAWAII: | |
3ba7b418 AG |
3612 | case CHIP_TOPAZ: |
3613 | case CHIP_TONGA: | |
3614 | case CHIP_FIJI: | |
3615 | case CHIP_POLARIS10: | |
3616 | case CHIP_POLARIS11: | |
3617 | case CHIP_POLARIS12: | |
3618 | case CHIP_VEGAM: | |
3619 | case CHIP_VEGA20: | |
3620 | case CHIP_VEGA10: | |
3621 | case CHIP_VEGA12: | |
c43b849f | 3622 | case CHIP_RAVEN: |
3ba7b418 AG |
3623 | break; |
3624 | default: | |
3625 | goto disabled; | |
3626 | } | |
12938fad CK |
3627 | } |
3628 | ||
3629 | return true; | |
3ba7b418 AG |
3630 | |
3631 | disabled: | |
3632 | DRM_INFO("GPU recovery disabled.\n"); | |
3633 | return false; | |
12938fad CK |
3634 | } |
3635 | ||
5c6dd71e | 3636 | |
26bc5340 AG |
3637 | static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
3638 | struct amdgpu_job *job, | |
3639 | bool *need_full_reset_arg) | |
3640 | { | |
3641 | int i, r = 0; | |
3642 | bool need_full_reset = *need_full_reset_arg; | |
71182665 | 3643 | |
71182665 | 3644 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
3645 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3646 | struct amdgpu_ring *ring = adev->rings[i]; | |
3647 | ||
51687759 | 3648 | if (!ring || !ring->sched.thread) |
0875dc9e | 3649 | continue; |
5740682e | 3650 | |
2f9d4084 ML |
3651 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
3652 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 3653 | } |
d38ceaf9 | 3654 | |
222b5f04 AG |
3655 | if(job) |
3656 | drm_sched_increase_karma(&job->base); | |
3657 | ||
1d721ed6 | 3658 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
3659 | if (!amdgpu_sriov_vf(adev)) { |
3660 | ||
3661 | if (!need_full_reset) | |
3662 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
3663 | ||
3664 | if (!need_full_reset) { | |
3665 | amdgpu_device_ip_pre_soft_reset(adev); | |
3666 | r = amdgpu_device_ip_soft_reset(adev); | |
3667 | amdgpu_device_ip_post_soft_reset(adev); | |
3668 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
3669 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
3670 | need_full_reset = true; | |
3671 | } | |
3672 | } | |
3673 | ||
3674 | if (need_full_reset) | |
3675 | r = amdgpu_device_ip_suspend(adev); | |
3676 | ||
3677 | *need_full_reset_arg = need_full_reset; | |
3678 | } | |
3679 | ||
3680 | return r; | |
3681 | } | |
3682 | ||
3683 | static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, | |
3684 | struct list_head *device_list_handle, | |
3685 | bool *need_full_reset_arg) | |
3686 | { | |
3687 | struct amdgpu_device *tmp_adev = NULL; | |
3688 | bool need_full_reset = *need_full_reset_arg, vram_lost = false; | |
3689 | int r = 0; | |
3690 | ||
3691 | /* | |
3692 | * ASIC reset has to be done on all HGMI hive nodes ASAP | |
3693 | * to allow proper links negotiation in FW (within 1 sec) | |
3694 | */ | |
3695 | if (need_full_reset) { | |
3696 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
d4535e2c AG |
3697 | /* For XGMI run all resets in parallel to speed up the process */ |
3698 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { | |
3699 | if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work)) | |
3700 | r = -EALREADY; | |
3701 | } else | |
3702 | r = amdgpu_asic_reset(tmp_adev); | |
3703 | ||
3704 | if (r) { | |
fed184e9 | 3705 | DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s", |
26bc5340 | 3706 | r, tmp_adev->ddev->unique); |
d4535e2c AG |
3707 | break; |
3708 | } | |
3709 | } | |
3710 | ||
3711 | /* For XGMI wait for all PSP resets to complete before proceed */ | |
3712 | if (!r) { | |
3713 | list_for_each_entry(tmp_adev, device_list_handle, | |
3714 | gmc.xgmi.head) { | |
3715 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { | |
3716 | flush_work(&tmp_adev->xgmi_reset_work); | |
3717 | r = tmp_adev->asic_reset_res; | |
3718 | if (r) | |
3719 | break; | |
3720 | } | |
3721 | } | |
26bc5340 AG |
3722 | } |
3723 | } | |
3724 | ||
3725 | ||
3726 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
3727 | if (need_full_reset) { | |
3728 | /* post card */ | |
3729 | if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context)) | |
3730 | DRM_WARN("asic atom init failed!"); | |
3731 | ||
3732 | if (!r) { | |
3733 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); | |
3734 | r = amdgpu_device_ip_resume_phase1(tmp_adev); | |
3735 | if (r) | |
3736 | goto out; | |
3737 | ||
3738 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
3739 | if (vram_lost) { | |
77e7f829 | 3740 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 3741 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
3742 | } |
3743 | ||
3744 | r = amdgpu_gtt_mgr_recover( | |
3745 | &tmp_adev->mman.bdev.man[TTM_PL_TT]); | |
3746 | if (r) | |
3747 | goto out; | |
3748 | ||
3749 | r = amdgpu_device_fw_loading(tmp_adev); | |
3750 | if (r) | |
3751 | return r; | |
3752 | ||
3753 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
3754 | if (r) | |
3755 | goto out; | |
3756 | ||
3757 | if (vram_lost) | |
3758 | amdgpu_device_fill_reset_magic(tmp_adev); | |
3759 | ||
fdafb359 EQ |
3760 | /* |
3761 | * Add this ASIC as tracked as reset was already | |
3762 | * complete successfully. | |
3763 | */ | |
3764 | amdgpu_register_gpu_instance(tmp_adev); | |
3765 | ||
7c04ca50 | 3766 | r = amdgpu_device_ip_late_init(tmp_adev); |
3767 | if (r) | |
3768 | goto out; | |
3769 | ||
e79a04d5 | 3770 | /* must succeed. */ |
511fdbc3 | 3771 | amdgpu_ras_resume(tmp_adev); |
e79a04d5 | 3772 | |
26bc5340 AG |
3773 | /* Update PSP FW topology after reset */ |
3774 | if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
3775 | r = amdgpu_xgmi_update_topology(hive, tmp_adev); | |
3776 | } | |
3777 | } | |
3778 | ||
3779 | ||
3780 | out: | |
3781 | if (!r) { | |
3782 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
3783 | r = amdgpu_ib_ring_tests(tmp_adev); | |
3784 | if (r) { | |
3785 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
3786 | r = amdgpu_device_ip_suspend(tmp_adev); | |
3787 | need_full_reset = true; | |
3788 | r = -EAGAIN; | |
3789 | goto end; | |
3790 | } | |
3791 | } | |
3792 | ||
3793 | if (!r) | |
3794 | r = amdgpu_device_recover_vram(tmp_adev); | |
3795 | else | |
3796 | tmp_adev->asic_reset_res = r; | |
3797 | } | |
3798 | ||
3799 | end: | |
3800 | *need_full_reset_arg = need_full_reset; | |
3801 | return r; | |
3802 | } | |
3803 | ||
1d721ed6 | 3804 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock) |
26bc5340 | 3805 | { |
1d721ed6 AG |
3806 | if (trylock) { |
3807 | if (!mutex_trylock(&adev->lock_reset)) | |
3808 | return false; | |
3809 | } else | |
3810 | mutex_lock(&adev->lock_reset); | |
5740682e | 3811 | |
26bc5340 AG |
3812 | atomic_inc(&adev->gpu_reset_counter); |
3813 | adev->in_gpu_reset = 1; | |
a3a09142 AD |
3814 | switch (amdgpu_asic_reset_method(adev)) { |
3815 | case AMD_RESET_METHOD_MODE1: | |
3816 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
3817 | break; | |
3818 | case AMD_RESET_METHOD_MODE2: | |
3819 | adev->mp1_state = PP_MP1_STATE_RESET; | |
3820 | break; | |
3821 | default: | |
3822 | adev->mp1_state = PP_MP1_STATE_NONE; | |
3823 | break; | |
3824 | } | |
1d721ed6 AG |
3825 | |
3826 | return true; | |
26bc5340 | 3827 | } |
d38ceaf9 | 3828 | |
26bc5340 AG |
3829 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
3830 | { | |
89041940 | 3831 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 3832 | adev->mp1_state = PP_MP1_STATE_NONE; |
13a752e3 ML |
3833 | adev->in_gpu_reset = 0; |
3834 | mutex_unlock(&adev->lock_reset); | |
26bc5340 AG |
3835 | } |
3836 | ||
26bc5340 AG |
3837 | /** |
3838 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
3839 | * | |
3840 | * @adev: amdgpu device pointer | |
3841 | * @job: which job trigger hang | |
3842 | * | |
3843 | * Attempt to reset the GPU if it has hung (all asics). | |
3844 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
3845 | * Returns 0 for success or an error on failure. | |
3846 | */ | |
3847 | ||
3848 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
3849 | struct amdgpu_job *job) | |
3850 | { | |
1d721ed6 AG |
3851 | struct list_head device_list, *device_list_handle = NULL; |
3852 | bool need_full_reset, job_signaled; | |
26bc5340 | 3853 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 3854 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 3855 | int i, r = 0; |
7c6e68c7 | 3856 | bool in_ras_intr = amdgpu_ras_intr_triggered(); |
26bc5340 | 3857 | |
d5ea093e AG |
3858 | /* |
3859 | * Flush RAM to disk so that after reboot | |
3860 | * the user can read log and see why the system rebooted. | |
3861 | */ | |
3862 | if (in_ras_intr && amdgpu_ras_get_context(adev)->reboot) { | |
3863 | ||
3864 | DRM_WARN("Emergency reboot."); | |
3865 | ||
3866 | ksys_sync_helper(); | |
3867 | emergency_restart(); | |
3868 | } | |
3869 | ||
1d721ed6 | 3870 | need_full_reset = job_signaled = false; |
26bc5340 AG |
3871 | INIT_LIST_HEAD(&device_list); |
3872 | ||
7c6e68c7 | 3873 | dev_info(adev->dev, "GPU %s begin!\n", in_ras_intr ? "jobs stop":"reset"); |
26bc5340 | 3874 | |
beff74bc | 3875 | cancel_delayed_work_sync(&adev->delayed_init_work); |
c53e4db7 | 3876 | |
1d721ed6 AG |
3877 | hive = amdgpu_get_xgmi_hive(adev, false); |
3878 | ||
26bc5340 | 3879 | /* |
1d721ed6 AG |
3880 | * Here we trylock to avoid chain of resets executing from |
3881 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
3882 | * different schedulers for same device while this TO handler is running. | |
3883 | * We always reset all schedulers for device and all devices for XGMI | |
3884 | * hive so that should take care of them too. | |
26bc5340 | 3885 | */ |
1d721ed6 AG |
3886 | |
3887 | if (hive && !mutex_trylock(&hive->reset_lock)) { | |
3888 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
0b2d2c2e | 3889 | job ? job->base.id : -1, hive->hive_id); |
26bc5340 | 3890 | return 0; |
1d721ed6 | 3891 | } |
26bc5340 AG |
3892 | |
3893 | /* Start with adev pre asic reset first for soft reset check.*/ | |
1d721ed6 AG |
3894 | if (!amdgpu_device_lock_adev(adev, !hive)) { |
3895 | DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress", | |
0b2d2c2e | 3896 | job ? job->base.id : -1); |
1d721ed6 | 3897 | return 0; |
26bc5340 AG |
3898 | } |
3899 | ||
7c6e68c7 AG |
3900 | /* Block kfd: SRIOV would do it separately */ |
3901 | if (!amdgpu_sriov_vf(adev)) | |
3902 | amdgpu_amdkfd_pre_reset(adev); | |
3903 | ||
26bc5340 | 3904 | /* Build list of devices to reset */ |
1d721ed6 | 3905 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
26bc5340 | 3906 | if (!hive) { |
7c6e68c7 AG |
3907 | /*unlock kfd: SRIOV would do it separately */ |
3908 | if (!amdgpu_sriov_vf(adev)) | |
3909 | amdgpu_amdkfd_post_reset(adev); | |
26bc5340 AG |
3910 | amdgpu_device_unlock_adev(adev); |
3911 | return -ENODEV; | |
3912 | } | |
3913 | ||
3914 | /* | |
3915 | * In case we are in XGMI hive mode device reset is done for all the | |
3916 | * nodes in the hive to retrain all XGMI links and hence the reset | |
3917 | * sequence is executed in loop on all nodes. | |
3918 | */ | |
3919 | device_list_handle = &hive->device_list; | |
3920 | } else { | |
3921 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
3922 | device_list_handle = &device_list; | |
3923 | } | |
3924 | ||
1d721ed6 AG |
3925 | /* block all schedulers and reset given job's ring */ |
3926 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
7c6e68c7 | 3927 | if (tmp_adev != adev) { |
12ffa55d | 3928 | amdgpu_device_lock_adev(tmp_adev, false); |
7c6e68c7 AG |
3929 | if (!amdgpu_sriov_vf(tmp_adev)) |
3930 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
3931 | } | |
3932 | ||
12ffa55d AG |
3933 | /* |
3934 | * Mark these ASICs to be reseted as untracked first | |
3935 | * And add them back after reset completed | |
3936 | */ | |
3937 | amdgpu_unregister_gpu_instance(tmp_adev); | |
3938 | ||
f1c1314b | 3939 | /* disable ras on ALL IPs */ |
7c6e68c7 | 3940 | if (!in_ras_intr && amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 3941 | amdgpu_ras_suspend(tmp_adev); |
3942 | ||
1d721ed6 AG |
3943 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3944 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
3945 | ||
3946 | if (!ring || !ring->sched.thread) | |
3947 | continue; | |
3948 | ||
0b2d2c2e | 3949 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 AG |
3950 | |
3951 | if (in_ras_intr) | |
3952 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); | |
1d721ed6 AG |
3953 | } |
3954 | } | |
3955 | ||
3956 | ||
7c6e68c7 AG |
3957 | if (in_ras_intr) |
3958 | goto skip_sched_resume; | |
3959 | ||
1d721ed6 AG |
3960 | /* |
3961 | * Must check guilty signal here since after this point all old | |
3962 | * HW fences are force signaled. | |
3963 | * | |
3964 | * job->base holds a reference to parent fence | |
3965 | */ | |
3966 | if (job && job->base.s_fence->parent && | |
3967 | dma_fence_is_signaled(job->base.s_fence->parent)) | |
3968 | job_signaled = true; | |
3969 | ||
1d721ed6 AG |
3970 | if (job_signaled) { |
3971 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); | |
3972 | goto skip_hw_reset; | |
3973 | } | |
3974 | ||
3975 | ||
3976 | /* Guilty job will be freed after this*/ | |
0b2d2c2e | 3977 | r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset); |
1d721ed6 AG |
3978 | if (r) { |
3979 | /*TODO Should we stop ?*/ | |
3980 | DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ", | |
3981 | r, adev->ddev->unique); | |
3982 | adev->asic_reset_res = r; | |
3983 | } | |
3984 | ||
26bc5340 AG |
3985 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
3986 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
3987 | ||
3988 | if (tmp_adev == adev) | |
3989 | continue; | |
3990 | ||
26bc5340 AG |
3991 | r = amdgpu_device_pre_asic_reset(tmp_adev, |
3992 | NULL, | |
3993 | &need_full_reset); | |
3994 | /*TODO Should we stop ?*/ | |
3995 | if (r) { | |
3996 | DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ", | |
3997 | r, tmp_adev->ddev->unique); | |
3998 | tmp_adev->asic_reset_res = r; | |
3999 | } | |
4000 | } | |
4001 | ||
4002 | /* Actual ASIC resets if needed.*/ | |
4003 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
4004 | if (amdgpu_sriov_vf(adev)) { | |
4005 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
4006 | if (r) | |
4007 | adev->asic_reset_res = r; | |
4008 | } else { | |
4009 | r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset); | |
4010 | if (r && r == -EAGAIN) | |
4011 | goto retry; | |
4012 | } | |
4013 | ||
1d721ed6 AG |
4014 | skip_hw_reset: |
4015 | ||
26bc5340 AG |
4016 | /* Post ASIC reset for all devs .*/ |
4017 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
7c6e68c7 | 4018 | |
1d721ed6 AG |
4019 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4020 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4021 | ||
4022 | if (!ring || !ring->sched.thread) | |
4023 | continue; | |
4024 | ||
4025 | /* No point to resubmit jobs if we didn't HW reset*/ | |
4026 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
4027 | drm_sched_resubmit_jobs(&ring->sched); | |
4028 | ||
4029 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
4030 | } | |
4031 | ||
4032 | if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) { | |
4033 | drm_helper_resume_force_mode(tmp_adev->ddev); | |
4034 | } | |
4035 | ||
4036 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
4037 | |
4038 | if (r) { | |
4039 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 4040 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
4041 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
4042 | } else { | |
12ffa55d | 4043 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 | 4044 | } |
7c6e68c7 | 4045 | } |
26bc5340 | 4046 | |
7c6e68c7 AG |
4047 | skip_sched_resume: |
4048 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
4049 | /*unlock kfd: SRIOV would do it separately */ | |
4050 | if (!in_ras_intr && !amdgpu_sriov_vf(tmp_adev)) | |
4051 | amdgpu_amdkfd_post_reset(tmp_adev); | |
26bc5340 AG |
4052 | amdgpu_device_unlock_adev(tmp_adev); |
4053 | } | |
4054 | ||
1d721ed6 | 4055 | if (hive) |
22d6575b | 4056 | mutex_unlock(&hive->reset_lock); |
26bc5340 AG |
4057 | |
4058 | if (r) | |
4059 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); | |
d38ceaf9 AD |
4060 | return r; |
4061 | } | |
4062 | ||
e3ecdffa AD |
4063 | /** |
4064 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
4065 | * | |
4066 | * @adev: amdgpu_device pointer | |
4067 | * | |
4068 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
4069 | * and lanes) of the slot the device is in. Handles APUs and | |
4070 | * virtualized environments where PCIE config space may not be available. | |
4071 | */ | |
5494d864 | 4072 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 4073 | { |
5d9a6330 | 4074 | struct pci_dev *pdev; |
c5313457 HK |
4075 | enum pci_bus_speed speed_cap, platform_speed_cap; |
4076 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 4077 | |
cd474ba0 AD |
4078 | if (amdgpu_pcie_gen_cap) |
4079 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 4080 | |
cd474ba0 AD |
4081 | if (amdgpu_pcie_lane_cap) |
4082 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 4083 | |
cd474ba0 AD |
4084 | /* covers APUs as well */ |
4085 | if (pci_is_root_bus(adev->pdev->bus)) { | |
4086 | if (adev->pm.pcie_gen_mask == 0) | |
4087 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
4088 | if (adev->pm.pcie_mlw_mask == 0) | |
4089 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 4090 | return; |
cd474ba0 | 4091 | } |
d0dd7f0c | 4092 | |
c5313457 HK |
4093 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
4094 | return; | |
4095 | ||
dbaa922b AD |
4096 | pcie_bandwidth_available(adev->pdev, NULL, |
4097 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 4098 | |
cd474ba0 | 4099 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
4100 | /* asic caps */ |
4101 | pdev = adev->pdev; | |
4102 | speed_cap = pcie_get_speed_cap(pdev); | |
4103 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
4104 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
4105 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
4106 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 4107 | } else { |
5d9a6330 AD |
4108 | if (speed_cap == PCIE_SPEED_16_0GT) |
4109 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4110 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4111 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4112 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
4113 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
4114 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4115 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4116 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
4117 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
4118 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4119 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4120 | else | |
4121 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4122 | } | |
4123 | /* platform caps */ | |
c5313457 | 4124 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
4125 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4126 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4127 | } else { | |
c5313457 | 4128 | if (platform_speed_cap == PCIE_SPEED_16_0GT) |
5d9a6330 AD |
4129 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4130 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4131 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4132 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 4133 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
4134 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4135 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4136 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 4137 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
4138 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4139 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4140 | else | |
4141 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4142 | ||
cd474ba0 AD |
4143 | } |
4144 | } | |
4145 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 4146 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
4147 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
4148 | } else { | |
c5313457 | 4149 | switch (platform_link_width) { |
5d9a6330 | 4150 | case PCIE_LNK_X32: |
cd474ba0 AD |
4151 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
4152 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
4153 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
4154 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4155 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4156 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4157 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4158 | break; | |
5d9a6330 | 4159 | case PCIE_LNK_X16: |
cd474ba0 AD |
4160 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
4161 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
4162 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4163 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4164 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4165 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4166 | break; | |
5d9a6330 | 4167 | case PCIE_LNK_X12: |
cd474ba0 AD |
4168 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
4169 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4170 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4171 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4172 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4173 | break; | |
5d9a6330 | 4174 | case PCIE_LNK_X8: |
cd474ba0 AD |
4175 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
4176 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
4177 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4178 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4179 | break; | |
5d9a6330 | 4180 | case PCIE_LNK_X4: |
cd474ba0 AD |
4181 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
4182 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
4183 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4184 | break; | |
5d9a6330 | 4185 | case PCIE_LNK_X2: |
cd474ba0 AD |
4186 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
4187 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
4188 | break; | |
5d9a6330 | 4189 | case PCIE_LNK_X1: |
cd474ba0 AD |
4190 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
4191 | break; | |
4192 | default: | |
4193 | break; | |
4194 | } | |
d0dd7f0c AD |
4195 | } |
4196 | } | |
4197 | } | |
d38ceaf9 | 4198 |