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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
fdf2f6c5 | 33 | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 35 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
36 | #include <drm/amdgpu_drm.h> |
37 | #include <linux/vgaarb.h> | |
38 | #include <linux/vga_switcheroo.h> | |
39 | #include <linux/efi.h> | |
40 | #include "amdgpu.h" | |
f4b373f4 | 41 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
42 | #include "amdgpu_i2c.h" |
43 | #include "atom.h" | |
44 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 45 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 46 | #include "amd_pcie.h" |
33f34802 KW |
47 | #ifdef CONFIG_DRM_AMDGPU_SI |
48 | #include "si.h" | |
49 | #endif | |
a2e73f56 AD |
50 | #ifdef CONFIG_DRM_AMDGPU_CIK |
51 | #include "cik.h" | |
52 | #endif | |
aaa36a97 | 53 | #include "vi.h" |
460826e6 | 54 | #include "soc15.h" |
0a5b8c7b | 55 | #include "nv.h" |
d38ceaf9 | 56 | #include "bif/bif_4_1_d.h" |
9accf2fd | 57 | #include <linux/pci.h> |
bec86378 | 58 | #include <linux/firmware.h> |
89041940 | 59 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 60 | |
ba997709 | 61 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 62 | #include "amdgpu_pm.h" |
d38ceaf9 | 63 | |
5183411b | 64 | #include "amdgpu_xgmi.h" |
c030f2e4 | 65 | #include "amdgpu_ras.h" |
9c7c85f7 | 66 | #include "amdgpu_pmu.h" |
bd607166 | 67 | #include "amdgpu_fru_eeprom.h" |
5183411b | 68 | |
d5ea093e | 69 | #include <linux/suspend.h> |
c6a6e2db | 70 | #include <drm/task_barrier.h> |
3f12acc8 | 71 | #include <linux/pm_runtime.h> |
d5ea093e | 72 | |
e2a75f88 | 73 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 74 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 75 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 76 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 77 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 78 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 79 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 80 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 81 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 82 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
4e52a9f8 | 83 | MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin"); |
e2a75f88 | 84 | |
2dc80b00 S |
85 | #define AMDGPU_RESUME_MS 2000 |
86 | ||
050091ab | 87 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
88 | "TAHITI", |
89 | "PITCAIRN", | |
90 | "VERDE", | |
91 | "OLAND", | |
92 | "HAINAN", | |
d38ceaf9 AD |
93 | "BONAIRE", |
94 | "KAVERI", | |
95 | "KABINI", | |
96 | "HAWAII", | |
97 | "MULLINS", | |
98 | "TOPAZ", | |
99 | "TONGA", | |
48299f95 | 100 | "FIJI", |
d38ceaf9 | 101 | "CARRIZO", |
139f4917 | 102 | "STONEY", |
2cc0c0b5 FC |
103 | "POLARIS10", |
104 | "POLARIS11", | |
c4642a47 | 105 | "POLARIS12", |
48ff108d | 106 | "VEGAM", |
d4196f01 | 107 | "VEGA10", |
8fab806a | 108 | "VEGA12", |
956fcddc | 109 | "VEGA20", |
2ca8a5d2 | 110 | "RAVEN", |
d6c3b24e | 111 | "ARCTURUS", |
1eee4228 | 112 | "RENOIR", |
d46b417a | 113 | "ALDEBARAN", |
852a6626 | 114 | "NAVI10", |
87dbad02 | 115 | "NAVI14", |
9802f5d7 | 116 | "NAVI12", |
ccaf72d3 | 117 | "SIENNA_CICHLID", |
ddd8fbe7 | 118 | "NAVY_FLOUNDER", |
4f1e9a76 | 119 | "VANGOGH", |
a2468e04 | 120 | "DIMGREY_CAVEFISH", |
d38ceaf9 AD |
121 | "LAST", |
122 | }; | |
123 | ||
dcea6e65 KR |
124 | /** |
125 | * DOC: pcie_replay_count | |
126 | * | |
127 | * The amdgpu driver provides a sysfs API for reporting the total number | |
128 | * of PCIe replays (NAKs) | |
129 | * The file pcie_replay_count is used for this and returns the total | |
130 | * number of replays as a sum of the NAKs generated and NAKs received | |
131 | */ | |
132 | ||
133 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
134 | struct device_attribute *attr, char *buf) | |
135 | { | |
136 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 137 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
138 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
139 | ||
140 | return snprintf(buf, PAGE_SIZE, "%llu\n", cnt); | |
141 | } | |
142 | ||
143 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
144 | amdgpu_device_get_pcie_replay_count, NULL); | |
145 | ||
5494d864 AD |
146 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
147 | ||
bd607166 KR |
148 | /** |
149 | * DOC: product_name | |
150 | * | |
151 | * The amdgpu driver provides a sysfs API for reporting the product name | |
152 | * for the device | |
153 | * The file serial_number is used for this and returns the product name | |
154 | * as returned from the FRU. | |
155 | * NOTE: This is only available for certain server cards | |
156 | */ | |
157 | ||
158 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
159 | struct device_attribute *attr, char *buf) | |
160 | { | |
161 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 162 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
163 | |
164 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name); | |
165 | } | |
166 | ||
167 | static DEVICE_ATTR(product_name, S_IRUGO, | |
168 | amdgpu_device_get_product_name, NULL); | |
169 | ||
170 | /** | |
171 | * DOC: product_number | |
172 | * | |
173 | * The amdgpu driver provides a sysfs API for reporting the part number | |
174 | * for the device | |
175 | * The file serial_number is used for this and returns the part number | |
176 | * as returned from the FRU. | |
177 | * NOTE: This is only available for certain server cards | |
178 | */ | |
179 | ||
180 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
181 | struct device_attribute *attr, char *buf) | |
182 | { | |
183 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 184 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
185 | |
186 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number); | |
187 | } | |
188 | ||
189 | static DEVICE_ATTR(product_number, S_IRUGO, | |
190 | amdgpu_device_get_product_number, NULL); | |
191 | ||
192 | /** | |
193 | * DOC: serial_number | |
194 | * | |
195 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
196 | * for the device | |
197 | * The file serial_number is used for this and returns the serial number | |
198 | * as returned from the FRU. | |
199 | * NOTE: This is only available for certain server cards | |
200 | */ | |
201 | ||
202 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
203 | struct device_attribute *attr, char *buf) | |
204 | { | |
205 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 206 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 KR |
207 | |
208 | return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial); | |
209 | } | |
210 | ||
211 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
212 | amdgpu_device_get_serial_number, NULL); | |
213 | ||
fd496ca8 AD |
214 | /** |
215 | * amdgpu_device_supports_atpx - Is the device a dGPU with HG/PX power control | |
216 | * | |
217 | * @dev: drm_device pointer | |
218 | * | |
219 | * Returns true if the device is a dGPU with HG/PX power control, | |
220 | * otherwise return false. | |
221 | */ | |
222 | bool amdgpu_device_supports_atpx(struct drm_device *dev) | |
223 | { | |
224 | struct amdgpu_device *adev = drm_to_adev(dev); | |
225 | ||
226 | if (adev->flags & AMD_IS_PX) | |
227 | return true; | |
228 | return false; | |
229 | } | |
230 | ||
e3ecdffa | 231 | /** |
0330b848 | 232 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
233 | * |
234 | * @dev: drm_device pointer | |
235 | * | |
236 | * Returns true if the device is a dGPU with HG/PX power control, | |
237 | * otherwise return false. | |
238 | */ | |
31af062a | 239 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 240 | { |
1348969a | 241 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 242 | |
0330b848 | 243 | if (adev->has_pr3) |
d38ceaf9 AD |
244 | return true; |
245 | return false; | |
246 | } | |
247 | ||
a69cba42 AD |
248 | /** |
249 | * amdgpu_device_supports_baco - Does the device support BACO | |
250 | * | |
251 | * @dev: drm_device pointer | |
252 | * | |
253 | * Returns true if the device supporte BACO, | |
254 | * otherwise return false. | |
255 | */ | |
256 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
257 | { | |
1348969a | 258 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
259 | |
260 | return amdgpu_asic_supports_baco(adev); | |
261 | } | |
262 | ||
6e3cd2a9 MCC |
263 | /* |
264 | * VRAM access helper functions | |
265 | */ | |
266 | ||
e35e2b11 | 267 | /** |
e35e2b11 TY |
268 | * amdgpu_device_vram_access - read/write a buffer in vram |
269 | * | |
270 | * @adev: amdgpu_device pointer | |
271 | * @pos: offset of the buffer in vram | |
272 | * @buf: virtual address of the buffer in system memory | |
273 | * @size: read/write size, sizeof(@buf) must > @size | |
274 | * @write: true - write to vram, otherwise - read from vram | |
275 | */ | |
276 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
277 | uint32_t *buf, size_t size, bool write) | |
278 | { | |
e35e2b11 | 279 | unsigned long flags; |
ce05ac56 CK |
280 | uint32_t hi = ~0; |
281 | uint64_t last; | |
282 | ||
9d11eb0d CK |
283 | |
284 | #ifdef CONFIG_64BIT | |
285 | last = min(pos + size, adev->gmc.visible_vram_size); | |
286 | if (last > pos) { | |
287 | void __iomem *addr = adev->mman.aper_base_kaddr + pos; | |
288 | size_t count = last - pos; | |
289 | ||
290 | if (write) { | |
291 | memcpy_toio(addr, buf, count); | |
292 | mb(); | |
293 | amdgpu_asic_flush_hdp(adev, NULL); | |
294 | } else { | |
295 | amdgpu_asic_invalidate_hdp(adev, NULL); | |
296 | mb(); | |
297 | memcpy_fromio(buf, addr, count); | |
298 | } | |
299 | ||
300 | if (count == size) | |
301 | return; | |
302 | ||
303 | pos += count; | |
304 | buf += count / 4; | |
305 | size -= count; | |
306 | } | |
307 | #endif | |
308 | ||
ce05ac56 CK |
309 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); |
310 | for (last = pos + size; pos < last; pos += 4) { | |
311 | uint32_t tmp = pos >> 31; | |
e35e2b11 | 312 | |
e35e2b11 | 313 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); |
ce05ac56 CK |
314 | if (tmp != hi) { |
315 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
316 | hi = tmp; | |
317 | } | |
e35e2b11 TY |
318 | if (write) |
319 | WREG32_NO_KIQ(mmMM_DATA, *buf++); | |
320 | else | |
321 | *buf++ = RREG32_NO_KIQ(mmMM_DATA); | |
e35e2b11 | 322 | } |
ce05ac56 | 323 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); |
e35e2b11 TY |
324 | } |
325 | ||
d38ceaf9 | 326 | /* |
f7ee1874 | 327 | * register access helper functions. |
d38ceaf9 | 328 | */ |
56b53c0b DL |
329 | |
330 | /* Check if hw access should be skipped because of hotplug or device error */ | |
331 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
332 | { | |
333 | if (adev->in_pci_err_recovery) | |
334 | return true; | |
335 | ||
336 | #ifdef CONFIG_LOCKDEP | |
337 | /* | |
338 | * This is a bit complicated to understand, so worth a comment. What we assert | |
339 | * here is that the GPU reset is not running on another thread in parallel. | |
340 | * | |
341 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
342 | * we know that the reset is not running in paralell. | |
343 | * | |
344 | * If the trylock fails we assert that we are either already holding the read | |
345 | * side of the lock or are the reset thread itself and hold the write side of | |
346 | * the lock. | |
347 | */ | |
348 | if (in_task()) { | |
349 | if (down_read_trylock(&adev->reset_sem)) | |
350 | up_read(&adev->reset_sem); | |
351 | else | |
352 | lockdep_assert_held(&adev->reset_sem); | |
353 | } | |
354 | #endif | |
355 | return false; | |
356 | } | |
357 | ||
e3ecdffa | 358 | /** |
f7ee1874 | 359 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
360 | * |
361 | * @adev: amdgpu_device pointer | |
362 | * @reg: dword aligned register offset | |
363 | * @acc_flags: access flags which require special behavior | |
364 | * | |
365 | * Returns the 32 bit value from the offset specified. | |
366 | */ | |
f7ee1874 HZ |
367 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
368 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 369 | { |
f4b373f4 TSD |
370 | uint32_t ret; |
371 | ||
56b53c0b | 372 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
373 | return 0; |
374 | ||
f7ee1874 HZ |
375 | if ((reg * 4) < adev->rmmio_size) { |
376 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
377 | amdgpu_sriov_runtime(adev) && | |
378 | down_read_trylock(&adev->reset_sem)) { | |
379 | ret = amdgpu_kiq_rreg(adev, reg); | |
380 | up_read(&adev->reset_sem); | |
381 | } else { | |
382 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
383 | } | |
384 | } else { | |
385 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 386 | } |
bc992ba5 | 387 | |
f7ee1874 | 388 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 389 | |
f4b373f4 | 390 | return ret; |
d38ceaf9 AD |
391 | } |
392 | ||
421a2a30 ML |
393 | /* |
394 | * MMIO register read with bytes helper functions | |
395 | * @offset:bytes offset from MMIO start | |
396 | * | |
397 | */ | |
398 | ||
e3ecdffa AD |
399 | /** |
400 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
401 | * | |
402 | * @adev: amdgpu_device pointer | |
403 | * @offset: byte aligned register offset | |
404 | * | |
405 | * Returns the 8 bit value from the offset specified. | |
406 | */ | |
7cbbc745 AG |
407 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
408 | { | |
56b53c0b | 409 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
410 | return 0; |
411 | ||
421a2a30 ML |
412 | if (offset < adev->rmmio_size) |
413 | return (readb(adev->rmmio + offset)); | |
414 | BUG(); | |
415 | } | |
416 | ||
417 | /* | |
418 | * MMIO register write with bytes helper functions | |
419 | * @offset:bytes offset from MMIO start | |
420 | * @value: the value want to be written to the register | |
421 | * | |
422 | */ | |
e3ecdffa AD |
423 | /** |
424 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
425 | * | |
426 | * @adev: amdgpu_device pointer | |
427 | * @offset: byte aligned register offset | |
428 | * @value: 8 bit value to write | |
429 | * | |
430 | * Writes the value specified to the offset specified. | |
431 | */ | |
7cbbc745 AG |
432 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
433 | { | |
56b53c0b | 434 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
435 | return; |
436 | ||
421a2a30 ML |
437 | if (offset < adev->rmmio_size) |
438 | writeb(value, adev->rmmio + offset); | |
439 | else | |
440 | BUG(); | |
441 | } | |
442 | ||
e3ecdffa | 443 | /** |
f7ee1874 | 444 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
445 | * |
446 | * @adev: amdgpu_device pointer | |
447 | * @reg: dword aligned register offset | |
448 | * @v: 32 bit value to write to the register | |
449 | * @acc_flags: access flags which require special behavior | |
450 | * | |
451 | * Writes the value specified to the offset specified. | |
452 | */ | |
f7ee1874 HZ |
453 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
454 | uint32_t reg, uint32_t v, | |
455 | uint32_t acc_flags) | |
d38ceaf9 | 456 | { |
56b53c0b | 457 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
458 | return; |
459 | ||
f7ee1874 HZ |
460 | if ((reg * 4) < adev->rmmio_size) { |
461 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
462 | amdgpu_sriov_runtime(adev) && | |
463 | down_read_trylock(&adev->reset_sem)) { | |
464 | amdgpu_kiq_wreg(adev, reg, v); | |
465 | up_read(&adev->reset_sem); | |
466 | } else { | |
467 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
468 | } | |
469 | } else { | |
470 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 471 | } |
bc992ba5 | 472 | |
f7ee1874 | 473 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 474 | } |
d38ceaf9 | 475 | |
2e0cc4d4 ML |
476 | /* |
477 | * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range | |
478 | * | |
479 | * this function is invoked only the debugfs register access | |
480 | * */ | |
f7ee1874 HZ |
481 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
482 | uint32_t reg, uint32_t v) | |
2e0cc4d4 | 483 | { |
56b53c0b | 484 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
485 | return; |
486 | ||
2e0cc4d4 | 487 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
488 | adev->gfx.rlc.funcs && |
489 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 ML |
490 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
491 | return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v); | |
f7ee1874 HZ |
492 | } else { |
493 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 494 | } |
d38ceaf9 AD |
495 | } |
496 | ||
d38ceaf9 AD |
497 | /** |
498 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
499 | * | |
500 | * @adev: amdgpu_device pointer | |
501 | * @index: doorbell index | |
502 | * | |
503 | * Returns the value in the doorbell aperture at the | |
504 | * requested doorbell index (CIK). | |
505 | */ | |
506 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
507 | { | |
56b53c0b | 508 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
509 | return 0; |
510 | ||
d38ceaf9 AD |
511 | if (index < adev->doorbell.num_doorbells) { |
512 | return readl(adev->doorbell.ptr + index); | |
513 | } else { | |
514 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
515 | return 0; | |
516 | } | |
517 | } | |
518 | ||
519 | /** | |
520 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
521 | * | |
522 | * @adev: amdgpu_device pointer | |
523 | * @index: doorbell index | |
524 | * @v: value to write | |
525 | * | |
526 | * Writes @v to the doorbell aperture at the | |
527 | * requested doorbell index (CIK). | |
528 | */ | |
529 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
530 | { | |
56b53c0b | 531 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
532 | return; |
533 | ||
d38ceaf9 AD |
534 | if (index < adev->doorbell.num_doorbells) { |
535 | writel(v, adev->doorbell.ptr + index); | |
536 | } else { | |
537 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
538 | } | |
539 | } | |
540 | ||
832be404 KW |
541 | /** |
542 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
543 | * | |
544 | * @adev: amdgpu_device pointer | |
545 | * @index: doorbell index | |
546 | * | |
547 | * Returns the value in the doorbell aperture at the | |
548 | * requested doorbell index (VEGA10+). | |
549 | */ | |
550 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
551 | { | |
56b53c0b | 552 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
553 | return 0; |
554 | ||
832be404 KW |
555 | if (index < adev->doorbell.num_doorbells) { |
556 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
557 | } else { | |
558 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
559 | return 0; | |
560 | } | |
561 | } | |
562 | ||
563 | /** | |
564 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
565 | * | |
566 | * @adev: amdgpu_device pointer | |
567 | * @index: doorbell index | |
568 | * @v: value to write | |
569 | * | |
570 | * Writes @v to the doorbell aperture at the | |
571 | * requested doorbell index (VEGA10+). | |
572 | */ | |
573 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
574 | { | |
56b53c0b | 575 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
576 | return; |
577 | ||
832be404 KW |
578 | if (index < adev->doorbell.num_doorbells) { |
579 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
580 | } else { | |
581 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
582 | } | |
583 | } | |
584 | ||
1bba3683 HZ |
585 | /** |
586 | * amdgpu_device_indirect_rreg - read an indirect register | |
587 | * | |
588 | * @adev: amdgpu_device pointer | |
589 | * @pcie_index: mmio register offset | |
590 | * @pcie_data: mmio register offset | |
22f453fb | 591 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
592 | * |
593 | * Returns the value of indirect register @reg_addr | |
594 | */ | |
595 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
596 | u32 pcie_index, u32 pcie_data, | |
597 | u32 reg_addr) | |
598 | { | |
599 | unsigned long flags; | |
600 | u32 r; | |
601 | void __iomem *pcie_index_offset; | |
602 | void __iomem *pcie_data_offset; | |
603 | ||
604 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
605 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
606 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
607 | ||
608 | writel(reg_addr, pcie_index_offset); | |
609 | readl(pcie_index_offset); | |
610 | r = readl(pcie_data_offset); | |
611 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
612 | ||
613 | return r; | |
614 | } | |
615 | ||
616 | /** | |
617 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
618 | * | |
619 | * @adev: amdgpu_device pointer | |
620 | * @pcie_index: mmio register offset | |
621 | * @pcie_data: mmio register offset | |
22f453fb | 622 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
623 | * |
624 | * Returns the value of indirect register @reg_addr | |
625 | */ | |
626 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
627 | u32 pcie_index, u32 pcie_data, | |
628 | u32 reg_addr) | |
629 | { | |
630 | unsigned long flags; | |
631 | u64 r; | |
632 | void __iomem *pcie_index_offset; | |
633 | void __iomem *pcie_data_offset; | |
634 | ||
635 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
636 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
637 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
638 | ||
639 | /* read low 32 bits */ | |
640 | writel(reg_addr, pcie_index_offset); | |
641 | readl(pcie_index_offset); | |
642 | r = readl(pcie_data_offset); | |
643 | /* read high 32 bits */ | |
644 | writel(reg_addr + 4, pcie_index_offset); | |
645 | readl(pcie_index_offset); | |
646 | r |= ((u64)readl(pcie_data_offset) << 32); | |
647 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
648 | ||
649 | return r; | |
650 | } | |
651 | ||
652 | /** | |
653 | * amdgpu_device_indirect_wreg - write an indirect register address | |
654 | * | |
655 | * @adev: amdgpu_device pointer | |
656 | * @pcie_index: mmio register offset | |
657 | * @pcie_data: mmio register offset | |
658 | * @reg_addr: indirect register offset | |
659 | * @reg_data: indirect register data | |
660 | * | |
661 | */ | |
662 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
663 | u32 pcie_index, u32 pcie_data, | |
664 | u32 reg_addr, u32 reg_data) | |
665 | { | |
666 | unsigned long flags; | |
667 | void __iomem *pcie_index_offset; | |
668 | void __iomem *pcie_data_offset; | |
669 | ||
670 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
671 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
672 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
673 | ||
674 | writel(reg_addr, pcie_index_offset); | |
675 | readl(pcie_index_offset); | |
676 | writel(reg_data, pcie_data_offset); | |
677 | readl(pcie_data_offset); | |
678 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
679 | } | |
680 | ||
681 | /** | |
682 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
683 | * | |
684 | * @adev: amdgpu_device pointer | |
685 | * @pcie_index: mmio register offset | |
686 | * @pcie_data: mmio register offset | |
687 | * @reg_addr: indirect register offset | |
688 | * @reg_data: indirect register data | |
689 | * | |
690 | */ | |
691 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
692 | u32 pcie_index, u32 pcie_data, | |
693 | u32 reg_addr, u64 reg_data) | |
694 | { | |
695 | unsigned long flags; | |
696 | void __iomem *pcie_index_offset; | |
697 | void __iomem *pcie_data_offset; | |
698 | ||
699 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
700 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
701 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
702 | ||
703 | /* write low 32 bits */ | |
704 | writel(reg_addr, pcie_index_offset); | |
705 | readl(pcie_index_offset); | |
706 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
707 | readl(pcie_data_offset); | |
708 | /* write high 32 bits */ | |
709 | writel(reg_addr + 4, pcie_index_offset); | |
710 | readl(pcie_index_offset); | |
711 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
712 | readl(pcie_data_offset); | |
713 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
714 | } | |
715 | ||
d38ceaf9 AD |
716 | /** |
717 | * amdgpu_invalid_rreg - dummy reg read function | |
718 | * | |
982a820b | 719 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
720 | * @reg: offset of register |
721 | * | |
722 | * Dummy register read function. Used for register blocks | |
723 | * that certain asics don't have (all asics). | |
724 | * Returns the value in the register. | |
725 | */ | |
726 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
727 | { | |
728 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
729 | BUG(); | |
730 | return 0; | |
731 | } | |
732 | ||
733 | /** | |
734 | * amdgpu_invalid_wreg - dummy reg write function | |
735 | * | |
982a820b | 736 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
737 | * @reg: offset of register |
738 | * @v: value to write to the register | |
739 | * | |
740 | * Dummy register read function. Used for register blocks | |
741 | * that certain asics don't have (all asics). | |
742 | */ | |
743 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
744 | { | |
745 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
746 | reg, v); | |
747 | BUG(); | |
748 | } | |
749 | ||
4fa1c6a6 TZ |
750 | /** |
751 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
752 | * | |
982a820b | 753 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
754 | * @reg: offset of register |
755 | * | |
756 | * Dummy register read function. Used for register blocks | |
757 | * that certain asics don't have (all asics). | |
758 | * Returns the value in the register. | |
759 | */ | |
760 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
761 | { | |
762 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
763 | BUG(); | |
764 | return 0; | |
765 | } | |
766 | ||
767 | /** | |
768 | * amdgpu_invalid_wreg64 - dummy reg write function | |
769 | * | |
982a820b | 770 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
771 | * @reg: offset of register |
772 | * @v: value to write to the register | |
773 | * | |
774 | * Dummy register read function. Used for register blocks | |
775 | * that certain asics don't have (all asics). | |
776 | */ | |
777 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
778 | { | |
779 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
780 | reg, v); | |
781 | BUG(); | |
782 | } | |
783 | ||
d38ceaf9 AD |
784 | /** |
785 | * amdgpu_block_invalid_rreg - dummy reg read function | |
786 | * | |
982a820b | 787 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
788 | * @block: offset of instance |
789 | * @reg: offset of register | |
790 | * | |
791 | * Dummy register read function. Used for register blocks | |
792 | * that certain asics don't have (all asics). | |
793 | * Returns the value in the register. | |
794 | */ | |
795 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
796 | uint32_t block, uint32_t reg) | |
797 | { | |
798 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
799 | reg, block); | |
800 | BUG(); | |
801 | return 0; | |
802 | } | |
803 | ||
804 | /** | |
805 | * amdgpu_block_invalid_wreg - dummy reg write function | |
806 | * | |
982a820b | 807 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
808 | * @block: offset of instance |
809 | * @reg: offset of register | |
810 | * @v: value to write to the register | |
811 | * | |
812 | * Dummy register read function. Used for register blocks | |
813 | * that certain asics don't have (all asics). | |
814 | */ | |
815 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
816 | uint32_t block, | |
817 | uint32_t reg, uint32_t v) | |
818 | { | |
819 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
820 | reg, block, v); | |
821 | BUG(); | |
822 | } | |
823 | ||
4d2997ab AD |
824 | /** |
825 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
826 | * | |
982a820b | 827 | * @adev: amdgpu_device pointer |
4d2997ab AD |
828 | * |
829 | * Does any asic specific work and then calls atom asic init. | |
830 | */ | |
831 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
832 | { | |
833 | amdgpu_asic_pre_asic_init(adev); | |
834 | ||
835 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
836 | } | |
837 | ||
e3ecdffa AD |
838 | /** |
839 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
840 | * | |
982a820b | 841 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
842 | * |
843 | * Allocates a scratch page of VRAM for use by various things in the | |
844 | * driver. | |
845 | */ | |
06ec9070 | 846 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 847 | { |
a4a02777 CK |
848 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
849 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
850 | &adev->vram_scratch.robj, | |
851 | &adev->vram_scratch.gpu_addr, | |
852 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
853 | } |
854 | ||
e3ecdffa AD |
855 | /** |
856 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
857 | * | |
982a820b | 858 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
859 | * |
860 | * Frees the VRAM scratch page. | |
861 | */ | |
06ec9070 | 862 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 863 | { |
078af1a3 | 864 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
865 | } |
866 | ||
867 | /** | |
9c3f2b54 | 868 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
869 | * |
870 | * @adev: amdgpu_device pointer | |
871 | * @registers: pointer to the register array | |
872 | * @array_size: size of the register array | |
873 | * | |
874 | * Programs an array or registers with and and or masks. | |
875 | * This is a helper for setting golden registers. | |
876 | */ | |
9c3f2b54 AD |
877 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
878 | const u32 *registers, | |
879 | const u32 array_size) | |
d38ceaf9 AD |
880 | { |
881 | u32 tmp, reg, and_mask, or_mask; | |
882 | int i; | |
883 | ||
884 | if (array_size % 3) | |
885 | return; | |
886 | ||
887 | for (i = 0; i < array_size; i +=3) { | |
888 | reg = registers[i + 0]; | |
889 | and_mask = registers[i + 1]; | |
890 | or_mask = registers[i + 2]; | |
891 | ||
892 | if (and_mask == 0xffffffff) { | |
893 | tmp = or_mask; | |
894 | } else { | |
895 | tmp = RREG32(reg); | |
896 | tmp &= ~and_mask; | |
e0d07657 HZ |
897 | if (adev->family >= AMDGPU_FAMILY_AI) |
898 | tmp |= (or_mask & and_mask); | |
899 | else | |
900 | tmp |= or_mask; | |
d38ceaf9 AD |
901 | } |
902 | WREG32(reg, tmp); | |
903 | } | |
904 | } | |
905 | ||
e3ecdffa AD |
906 | /** |
907 | * amdgpu_device_pci_config_reset - reset the GPU | |
908 | * | |
909 | * @adev: amdgpu_device pointer | |
910 | * | |
911 | * Resets the GPU using the pci config reset sequence. | |
912 | * Only applicable to asics prior to vega10. | |
913 | */ | |
8111c387 | 914 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
915 | { |
916 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
917 | } | |
918 | ||
af484df8 AD |
919 | /** |
920 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
921 | * | |
922 | * @adev: amdgpu_device pointer | |
923 | * | |
924 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
925 | */ | |
926 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
927 | { | |
928 | return pci_reset_function(adev->pdev); | |
929 | } | |
930 | ||
d38ceaf9 AD |
931 | /* |
932 | * GPU doorbell aperture helpers function. | |
933 | */ | |
934 | /** | |
06ec9070 | 935 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
936 | * |
937 | * @adev: amdgpu_device pointer | |
938 | * | |
939 | * Init doorbell driver information (CIK) | |
940 | * Returns 0 on success, error on failure. | |
941 | */ | |
06ec9070 | 942 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 943 | { |
6585661d | 944 | |
705e519e CK |
945 | /* No doorbell on SI hardware generation */ |
946 | if (adev->asic_type < CHIP_BONAIRE) { | |
947 | adev->doorbell.base = 0; | |
948 | adev->doorbell.size = 0; | |
949 | adev->doorbell.num_doorbells = 0; | |
950 | adev->doorbell.ptr = NULL; | |
951 | return 0; | |
952 | } | |
953 | ||
d6895ad3 CK |
954 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
955 | return -EINVAL; | |
956 | ||
22357775 AD |
957 | amdgpu_asic_init_doorbell_index(adev); |
958 | ||
d38ceaf9 AD |
959 | /* doorbell bar mapping */ |
960 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
961 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
962 | ||
edf600da | 963 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 964 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
965 | if (adev->doorbell.num_doorbells == 0) |
966 | return -EINVAL; | |
967 | ||
ec3db8a6 | 968 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
969 | * paging queue doorbell use the second page. The |
970 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
971 | * doorbells are in the first page. So with paging queue enabled, | |
972 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
973 | */ |
974 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 975 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 976 | |
8972e5d2 CK |
977 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
978 | adev->doorbell.num_doorbells * | |
979 | sizeof(u32)); | |
980 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 981 | return -ENOMEM; |
d38ceaf9 AD |
982 | |
983 | return 0; | |
984 | } | |
985 | ||
986 | /** | |
06ec9070 | 987 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
988 | * |
989 | * @adev: amdgpu_device pointer | |
990 | * | |
991 | * Tear down doorbell driver information (CIK) | |
992 | */ | |
06ec9070 | 993 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
994 | { |
995 | iounmap(adev->doorbell.ptr); | |
996 | adev->doorbell.ptr = NULL; | |
997 | } | |
998 | ||
22cb0164 | 999 | |
d38ceaf9 AD |
1000 | |
1001 | /* | |
06ec9070 | 1002 | * amdgpu_device_wb_*() |
455a7bc2 | 1003 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1004 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1005 | */ |
1006 | ||
1007 | /** | |
06ec9070 | 1008 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1009 | * |
1010 | * @adev: amdgpu_device pointer | |
1011 | * | |
1012 | * Disables Writeback and frees the Writeback memory (all asics). | |
1013 | * Used at driver shutdown. | |
1014 | */ | |
06ec9070 | 1015 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1016 | { |
1017 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1018 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1019 | &adev->wb.gpu_addr, | |
1020 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1021 | adev->wb.wb_obj = NULL; |
1022 | } | |
1023 | } | |
1024 | ||
1025 | /** | |
06ec9070 | 1026 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1027 | * |
1028 | * @adev: amdgpu_device pointer | |
1029 | * | |
455a7bc2 | 1030 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1031 | * Used at driver startup. |
1032 | * Returns 0 on success or an -error on failure. | |
1033 | */ | |
06ec9070 | 1034 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1035 | { |
1036 | int r; | |
1037 | ||
1038 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1039 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1040 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1041 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1042 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1043 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1044 | if (r) { |
1045 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1046 | return r; | |
1047 | } | |
d38ceaf9 AD |
1048 | |
1049 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1050 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1051 | ||
1052 | /* clear wb memory */ | |
73469585 | 1053 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1054 | } |
1055 | ||
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | /** | |
131b4b36 | 1060 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1061 | * |
1062 | * @adev: amdgpu_device pointer | |
1063 | * @wb: wb index | |
1064 | * | |
1065 | * Allocate a wb slot for use by the driver (all asics). | |
1066 | * Returns 0 on success or -EINVAL on failure. | |
1067 | */ | |
131b4b36 | 1068 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1069 | { |
1070 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1071 | |
97407b63 | 1072 | if (offset < adev->wb.num_wb) { |
7014285a | 1073 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1074 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1075 | return 0; |
1076 | } else { | |
1077 | return -EINVAL; | |
1078 | } | |
1079 | } | |
1080 | ||
d38ceaf9 | 1081 | /** |
131b4b36 | 1082 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1083 | * |
1084 | * @adev: amdgpu_device pointer | |
1085 | * @wb: wb index | |
1086 | * | |
1087 | * Free a wb slot allocated for use by the driver (all asics) | |
1088 | */ | |
131b4b36 | 1089 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1090 | { |
73469585 | 1091 | wb >>= 3; |
d38ceaf9 | 1092 | if (wb < adev->wb.num_wb) |
73469585 | 1093 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1094 | } |
1095 | ||
d6895ad3 CK |
1096 | /** |
1097 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1098 | * | |
1099 | * @adev: amdgpu_device pointer | |
1100 | * | |
1101 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1102 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1103 | * driver loading by returning -ENODEV. | |
1104 | */ | |
1105 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1106 | { | |
453f617a | 1107 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1108 | struct pci_bus *root; |
1109 | struct resource *res; | |
1110 | unsigned i; | |
d6895ad3 CK |
1111 | u16 cmd; |
1112 | int r; | |
1113 | ||
0c03b912 | 1114 | /* Bypass for VF */ |
1115 | if (amdgpu_sriov_vf(adev)) | |
1116 | return 0; | |
1117 | ||
b7221f2b AD |
1118 | /* skip if the bios has already enabled large BAR */ |
1119 | if (adev->gmc.real_vram_size && | |
1120 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1121 | return 0; | |
1122 | ||
31b8adab CK |
1123 | /* Check if the root BUS has 64bit memory resources */ |
1124 | root = adev->pdev->bus; | |
1125 | while (root->parent) | |
1126 | root = root->parent; | |
1127 | ||
1128 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1129 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1130 | res->start > 0x100000000ull) |
1131 | break; | |
1132 | } | |
1133 | ||
1134 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1135 | if (!res) | |
1136 | return 0; | |
1137 | ||
453f617a ND |
1138 | /* Limit the BAR size to what is available */ |
1139 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1140 | rbar_size); | |
1141 | ||
d6895ad3 CK |
1142 | /* Disable memory decoding while we change the BAR addresses and size */ |
1143 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1144 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1145 | cmd & ~PCI_COMMAND_MEMORY); | |
1146 | ||
1147 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 1148 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
1149 | if (adev->asic_type >= CHIP_BONAIRE) |
1150 | pci_release_resource(adev->pdev, 2); | |
1151 | ||
1152 | pci_release_resource(adev->pdev, 0); | |
1153 | ||
1154 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1155 | if (r == -ENOSPC) | |
1156 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1157 | else if (r && r != -ENOTSUPP) | |
1158 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1159 | ||
1160 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1161 | ||
1162 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1163 | * using the device. | |
1164 | */ | |
06ec9070 | 1165 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
1166 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1167 | return -ENODEV; | |
1168 | ||
1169 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1170 | ||
1171 | return 0; | |
1172 | } | |
a05502e5 | 1173 | |
d38ceaf9 AD |
1174 | /* |
1175 | * GPU helpers function. | |
1176 | */ | |
1177 | /** | |
39c640c0 | 1178 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1179 | * |
1180 | * @adev: amdgpu_device pointer | |
1181 | * | |
c836fec5 JQ |
1182 | * Check if the asic has been initialized (all asics) at driver startup |
1183 | * or post is needed if hw reset is performed. | |
1184 | * Returns true if need or false if not. | |
d38ceaf9 | 1185 | */ |
39c640c0 | 1186 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1187 | { |
1188 | uint32_t reg; | |
1189 | ||
bec86378 ML |
1190 | if (amdgpu_sriov_vf(adev)) |
1191 | return false; | |
1192 | ||
1193 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1194 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1195 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1196 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1197 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1198 | */ |
1199 | if (adev->asic_type == CHIP_FIJI) { | |
1200 | int err; | |
1201 | uint32_t fw_ver; | |
1202 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1203 | /* force vPost if error occured */ | |
1204 | if (err) | |
1205 | return true; | |
1206 | ||
1207 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1208 | if (fw_ver < 0x00160e00) |
1209 | return true; | |
bec86378 | 1210 | } |
bec86378 | 1211 | } |
91fe77eb | 1212 | |
e3c1b071 | 1213 | /* Don't post if we need to reset whole hive on init */ |
1214 | if (adev->gmc.xgmi.pending_reset) | |
1215 | return false; | |
1216 | ||
91fe77eb | 1217 | if (adev->has_hw_reset) { |
1218 | adev->has_hw_reset = false; | |
1219 | return true; | |
1220 | } | |
1221 | ||
1222 | /* bios scratch used on CIK+ */ | |
1223 | if (adev->asic_type >= CHIP_BONAIRE) | |
1224 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1225 | ||
1226 | /* check MEM_SIZE for older asics */ | |
1227 | reg = amdgpu_asic_get_config_memsize(adev); | |
1228 | ||
1229 | if ((reg != 0) && (reg != 0xffffffff)) | |
1230 | return false; | |
1231 | ||
1232 | return true; | |
bec86378 ML |
1233 | } |
1234 | ||
d38ceaf9 AD |
1235 | /* if we get transitioned to only one device, take VGA back */ |
1236 | /** | |
06ec9070 | 1237 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
1238 | * |
1239 | * @cookie: amdgpu_device pointer | |
1240 | * @state: enable/disable vga decode | |
1241 | * | |
1242 | * Enable/disable vga decode (all asics). | |
1243 | * Returns VGA resource flags. | |
1244 | */ | |
06ec9070 | 1245 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
1246 | { |
1247 | struct amdgpu_device *adev = cookie; | |
1248 | amdgpu_asic_set_vga_state(adev, state); | |
1249 | if (state) | |
1250 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1251 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1252 | else | |
1253 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1254 | } | |
1255 | ||
e3ecdffa AD |
1256 | /** |
1257 | * amdgpu_device_check_block_size - validate the vm block size | |
1258 | * | |
1259 | * @adev: amdgpu_device pointer | |
1260 | * | |
1261 | * Validates the vm block size specified via module parameter. | |
1262 | * The vm block size defines number of bits in page table versus page directory, | |
1263 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1264 | * page table and the remaining bits are in the page directory. | |
1265 | */ | |
06ec9070 | 1266 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1267 | { |
1268 | /* defines number of bits in page table versus page directory, | |
1269 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1270 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1271 | if (amdgpu_vm_block_size == -1) |
1272 | return; | |
a1adf8be | 1273 | |
bab4fee7 | 1274 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1275 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1276 | amdgpu_vm_block_size); | |
97489129 | 1277 | amdgpu_vm_block_size = -1; |
a1adf8be | 1278 | } |
a1adf8be CZ |
1279 | } |
1280 | ||
e3ecdffa AD |
1281 | /** |
1282 | * amdgpu_device_check_vm_size - validate the vm size | |
1283 | * | |
1284 | * @adev: amdgpu_device pointer | |
1285 | * | |
1286 | * Validates the vm size in GB specified via module parameter. | |
1287 | * The VM size is the size of the GPU virtual memory space in GB. | |
1288 | */ | |
06ec9070 | 1289 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1290 | { |
64dab074 AD |
1291 | /* no need to check the default value */ |
1292 | if (amdgpu_vm_size == -1) | |
1293 | return; | |
1294 | ||
83ca145d ZJ |
1295 | if (amdgpu_vm_size < 1) { |
1296 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1297 | amdgpu_vm_size); | |
f3368128 | 1298 | amdgpu_vm_size = -1; |
83ca145d | 1299 | } |
83ca145d ZJ |
1300 | } |
1301 | ||
7951e376 RZ |
1302 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1303 | { | |
1304 | struct sysinfo si; | |
a9d4fe2f | 1305 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1306 | uint64_t total_memory; |
1307 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1308 | uint64_t dram_size_three_GB = 0xB8000000; | |
1309 | ||
1310 | if (amdgpu_smu_memory_pool_size == 0) | |
1311 | return; | |
1312 | ||
1313 | if (!is_os_64) { | |
1314 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1315 | goto def_value; | |
1316 | } | |
1317 | si_meminfo(&si); | |
1318 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1319 | ||
1320 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1321 | (amdgpu_smu_memory_pool_size == 2)) { | |
1322 | if (total_memory < dram_size_three_GB) | |
1323 | goto def_value1; | |
1324 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1325 | (amdgpu_smu_memory_pool_size == 8)) { | |
1326 | if (total_memory < dram_size_seven_GB) | |
1327 | goto def_value1; | |
1328 | } else { | |
1329 | DRM_WARN("Smu memory pool size not supported\n"); | |
1330 | goto def_value; | |
1331 | } | |
1332 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1333 | ||
1334 | return; | |
1335 | ||
1336 | def_value1: | |
1337 | DRM_WARN("No enough system memory\n"); | |
1338 | def_value: | |
1339 | adev->pm.smu_prv_buffer_size = 0; | |
1340 | } | |
1341 | ||
d38ceaf9 | 1342 | /** |
06ec9070 | 1343 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1344 | * |
1345 | * @adev: amdgpu_device pointer | |
1346 | * | |
1347 | * Validates certain module parameters and updates | |
1348 | * the associated values used by the driver (all asics). | |
1349 | */ | |
912dfc84 | 1350 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1351 | { |
5b011235 CZ |
1352 | if (amdgpu_sched_jobs < 4) { |
1353 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1354 | amdgpu_sched_jobs); | |
1355 | amdgpu_sched_jobs = 4; | |
76117507 | 1356 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1357 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1358 | amdgpu_sched_jobs); | |
1359 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1360 | } | |
d38ceaf9 | 1361 | |
83e74db6 | 1362 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1363 | /* gart size must be greater or equal to 32M */ |
1364 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1365 | amdgpu_gart_size); | |
83e74db6 | 1366 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1367 | } |
1368 | ||
36d38372 | 1369 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1370 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1371 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1372 | amdgpu_gtt_size); | |
1373 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1374 | } |
1375 | ||
d07f14be RH |
1376 | /* valid range is between 4 and 9 inclusive */ |
1377 | if (amdgpu_vm_fragment_size != -1 && | |
1378 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1379 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1380 | amdgpu_vm_fragment_size = -1; | |
1381 | } | |
1382 | ||
5d5bd5e3 KW |
1383 | if (amdgpu_sched_hw_submission < 2) { |
1384 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1385 | amdgpu_sched_hw_submission); | |
1386 | amdgpu_sched_hw_submission = 2; | |
1387 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1388 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1389 | amdgpu_sched_hw_submission); | |
1390 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1391 | } | |
1392 | ||
7951e376 RZ |
1393 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1394 | ||
06ec9070 | 1395 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1396 | |
06ec9070 | 1397 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1398 | |
19aede77 | 1399 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1400 | |
c6252390 | 1401 | amdgpu_gmc_tmz_set(adev); |
01a8dcec | 1402 | |
9b498efa AD |
1403 | amdgpu_gmc_noretry_set(adev); |
1404 | ||
e3c00faa | 1405 | return 0; |
d38ceaf9 AD |
1406 | } |
1407 | ||
1408 | /** | |
1409 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1410 | * | |
1411 | * @pdev: pci dev pointer | |
1694467b | 1412 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1413 | * |
1414 | * Callback for the switcheroo driver. Suspends or resumes the | |
1415 | * the asics before or after it is powered up using ACPI methods. | |
1416 | */ | |
8aba21b7 LT |
1417 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1418 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1419 | { |
1420 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1421 | int r; |
d38ceaf9 | 1422 | |
fd496ca8 | 1423 | if (amdgpu_device_supports_atpx(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1424 | return; |
1425 | ||
1426 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1427 | pr_info("switched on\n"); |
d38ceaf9 AD |
1428 | /* don't suspend or resume card normally */ |
1429 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1430 | ||
8f66090b TZ |
1431 | pci_set_power_state(pdev, PCI_D0); |
1432 | amdgpu_device_load_pci_state(pdev); | |
1433 | r = pci_enable_device(pdev); | |
de185019 AD |
1434 | if (r) |
1435 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1436 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1437 | |
d38ceaf9 | 1438 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1439 | } else { |
dd4fa6c1 | 1440 | pr_info("switched off\n"); |
d38ceaf9 | 1441 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
de185019 | 1442 | amdgpu_device_suspend(dev, true); |
8f66090b | 1443 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1444 | /* Shut down the device */ |
8f66090b TZ |
1445 | pci_disable_device(pdev); |
1446 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1447 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1448 | } | |
1449 | } | |
1450 | ||
1451 | /** | |
1452 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1453 | * | |
1454 | * @pdev: pci dev pointer | |
1455 | * | |
1456 | * Callback for the switcheroo driver. Check of the switcheroo | |
1457 | * state can be changed. | |
1458 | * Returns true if the state can be changed, false if not. | |
1459 | */ | |
1460 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1461 | { | |
1462 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1463 | ||
1464 | /* | |
1465 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1466 | * locking inversion with the driver load path. And the access here is | |
1467 | * completely racy anyway. So don't bother with locking for now. | |
1468 | */ | |
7e13ad89 | 1469 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1470 | } |
1471 | ||
1472 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1473 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1474 | .reprobe = NULL, | |
1475 | .can_switch = amdgpu_switcheroo_can_switch, | |
1476 | }; | |
1477 | ||
e3ecdffa AD |
1478 | /** |
1479 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1480 | * | |
87e3f136 | 1481 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1482 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1483 | * @state: clockgating state (gate or ungate) | |
1484 | * | |
1485 | * Sets the requested clockgating state for all instances of | |
1486 | * the hardware IP specified. | |
1487 | * Returns the error code from the last instance. | |
1488 | */ | |
43fa561f | 1489 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1490 | enum amd_ip_block_type block_type, |
1491 | enum amd_clockgating_state state) | |
d38ceaf9 | 1492 | { |
43fa561f | 1493 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1494 | int i, r = 0; |
1495 | ||
1496 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1497 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1498 | continue; |
c722865a RZ |
1499 | if (adev->ip_blocks[i].version->type != block_type) |
1500 | continue; | |
1501 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1502 | continue; | |
1503 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1504 | (void *)adev, state); | |
1505 | if (r) | |
1506 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1507 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1508 | } |
1509 | return r; | |
1510 | } | |
1511 | ||
e3ecdffa AD |
1512 | /** |
1513 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1514 | * | |
87e3f136 | 1515 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1516 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1517 | * @state: powergating state (gate or ungate) | |
1518 | * | |
1519 | * Sets the requested powergating state for all instances of | |
1520 | * the hardware IP specified. | |
1521 | * Returns the error code from the last instance. | |
1522 | */ | |
43fa561f | 1523 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1524 | enum amd_ip_block_type block_type, |
1525 | enum amd_powergating_state state) | |
d38ceaf9 | 1526 | { |
43fa561f | 1527 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1528 | int i, r = 0; |
1529 | ||
1530 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1531 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1532 | continue; |
c722865a RZ |
1533 | if (adev->ip_blocks[i].version->type != block_type) |
1534 | continue; | |
1535 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1536 | continue; | |
1537 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1538 | (void *)adev, state); | |
1539 | if (r) | |
1540 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1541 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1542 | } |
1543 | return r; | |
1544 | } | |
1545 | ||
e3ecdffa AD |
1546 | /** |
1547 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1548 | * | |
1549 | * @adev: amdgpu_device pointer | |
1550 | * @flags: clockgating feature flags | |
1551 | * | |
1552 | * Walks the list of IPs on the device and updates the clockgating | |
1553 | * flags for each IP. | |
1554 | * Updates @flags with the feature flags for each hardware IP where | |
1555 | * clockgating is enabled. | |
1556 | */ | |
2990a1fc AD |
1557 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1558 | u32 *flags) | |
6cb2d4e4 HR |
1559 | { |
1560 | int i; | |
1561 | ||
1562 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1563 | if (!adev->ip_blocks[i].status.valid) | |
1564 | continue; | |
1565 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1566 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1567 | } | |
1568 | } | |
1569 | ||
e3ecdffa AD |
1570 | /** |
1571 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1572 | * | |
1573 | * @adev: amdgpu_device pointer | |
1574 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1575 | * | |
1576 | * Waits for the request hardware IP to be idle. | |
1577 | * Returns 0 for success or a negative error code on failure. | |
1578 | */ | |
2990a1fc AD |
1579 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1580 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1581 | { |
1582 | int i, r; | |
1583 | ||
1584 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1585 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1586 | continue; |
a1255107 AD |
1587 | if (adev->ip_blocks[i].version->type == block_type) { |
1588 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1589 | if (r) |
1590 | return r; | |
1591 | break; | |
1592 | } | |
1593 | } | |
1594 | return 0; | |
1595 | ||
1596 | } | |
1597 | ||
e3ecdffa AD |
1598 | /** |
1599 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1600 | * | |
1601 | * @adev: amdgpu_device pointer | |
1602 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1603 | * | |
1604 | * Check if the hardware IP is idle or not. | |
1605 | * Returns true if it the IP is idle, false if not. | |
1606 | */ | |
2990a1fc AD |
1607 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1608 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1609 | { |
1610 | int i; | |
1611 | ||
1612 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1613 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1614 | continue; |
a1255107 AD |
1615 | if (adev->ip_blocks[i].version->type == block_type) |
1616 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1617 | } |
1618 | return true; | |
1619 | ||
1620 | } | |
1621 | ||
e3ecdffa AD |
1622 | /** |
1623 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1624 | * | |
1625 | * @adev: amdgpu_device pointer | |
87e3f136 | 1626 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1627 | * |
1628 | * Returns a pointer to the hardware IP block structure | |
1629 | * if it exists for the asic, otherwise NULL. | |
1630 | */ | |
2990a1fc AD |
1631 | struct amdgpu_ip_block * |
1632 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1633 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1634 | { |
1635 | int i; | |
1636 | ||
1637 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1638 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1639 | return &adev->ip_blocks[i]; |
1640 | ||
1641 | return NULL; | |
1642 | } | |
1643 | ||
1644 | /** | |
2990a1fc | 1645 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1646 | * |
1647 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1648 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1649 | * @major: major version |
1650 | * @minor: minor version | |
1651 | * | |
1652 | * return 0 if equal or greater | |
1653 | * return 1 if smaller or the ip_block doesn't exist | |
1654 | */ | |
2990a1fc AD |
1655 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1656 | enum amd_ip_block_type type, | |
1657 | u32 major, u32 minor) | |
d38ceaf9 | 1658 | { |
2990a1fc | 1659 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1660 | |
a1255107 AD |
1661 | if (ip_block && ((ip_block->version->major > major) || |
1662 | ((ip_block->version->major == major) && | |
1663 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1664 | return 0; |
1665 | ||
1666 | return 1; | |
1667 | } | |
1668 | ||
a1255107 | 1669 | /** |
2990a1fc | 1670 | * amdgpu_device_ip_block_add |
a1255107 AD |
1671 | * |
1672 | * @adev: amdgpu_device pointer | |
1673 | * @ip_block_version: pointer to the IP to add | |
1674 | * | |
1675 | * Adds the IP block driver information to the collection of IPs | |
1676 | * on the asic. | |
1677 | */ | |
2990a1fc AD |
1678 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1679 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1680 | { |
1681 | if (!ip_block_version) | |
1682 | return -EINVAL; | |
1683 | ||
e966a725 | 1684 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1685 | ip_block_version->funcs->name); |
1686 | ||
a1255107 AD |
1687 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1688 | ||
1689 | return 0; | |
1690 | } | |
1691 | ||
e3ecdffa AD |
1692 | /** |
1693 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1694 | * | |
1695 | * @adev: amdgpu_device pointer | |
1696 | * | |
1697 | * Enabled the virtual display feature if the user has enabled it via | |
1698 | * the module parameter virtual_display. This feature provides a virtual | |
1699 | * display hardware on headless boards or in virtualized environments. | |
1700 | * This function parses and validates the configuration string specified by | |
1701 | * the user and configues the virtual display configuration (number of | |
1702 | * virtual connectors, crtcs, etc.) specified. | |
1703 | */ | |
483ef985 | 1704 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1705 | { |
1706 | adev->enable_virtual_display = false; | |
1707 | ||
1708 | if (amdgpu_virtual_display) { | |
8f66090b | 1709 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 1710 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1711 | |
1712 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1713 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1714 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1715 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1716 | if (!strcmp("all", pciaddname) |
1717 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1718 | long num_crtc; |
1719 | int res = -1; | |
1720 | ||
9accf2fd | 1721 | adev->enable_virtual_display = true; |
0f66356d ED |
1722 | |
1723 | if (pciaddname_tmp) | |
1724 | res = kstrtol(pciaddname_tmp, 10, | |
1725 | &num_crtc); | |
1726 | ||
1727 | if (!res) { | |
1728 | if (num_crtc < 1) | |
1729 | num_crtc = 1; | |
1730 | if (num_crtc > 6) | |
1731 | num_crtc = 6; | |
1732 | adev->mode_info.num_crtc = num_crtc; | |
1733 | } else { | |
1734 | adev->mode_info.num_crtc = 1; | |
1735 | } | |
9accf2fd ED |
1736 | break; |
1737 | } | |
1738 | } | |
1739 | ||
0f66356d ED |
1740 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1741 | amdgpu_virtual_display, pci_address_name, | |
1742 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1743 | |
1744 | kfree(pciaddstr); | |
1745 | } | |
1746 | } | |
1747 | ||
e3ecdffa AD |
1748 | /** |
1749 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1750 | * | |
1751 | * @adev: amdgpu_device pointer | |
1752 | * | |
1753 | * Parses the asic configuration parameters specified in the gpu info | |
1754 | * firmware and makes them availale to the driver for use in configuring | |
1755 | * the asic. | |
1756 | * Returns 0 on success, -EINVAL on failure. | |
1757 | */ | |
e2a75f88 AD |
1758 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1759 | { | |
e2a75f88 | 1760 | const char *chip_name; |
c0a43457 | 1761 | char fw_name[40]; |
e2a75f88 AD |
1762 | int err; |
1763 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1764 | ||
ab4fe3e1 HR |
1765 | adev->firmware.gpu_info_fw = NULL; |
1766 | ||
72de33f8 | 1767 | if (adev->mman.discovery_bin) { |
258620d0 | 1768 | amdgpu_discovery_get_gfx_info(adev); |
cc375d8c TY |
1769 | |
1770 | /* | |
1771 | * FIXME: The bounding box is still needed by Navi12, so | |
1772 | * temporarily read it from gpu_info firmware. Should be droped | |
1773 | * when DAL no longer needs it. | |
1774 | */ | |
1775 | if (adev->asic_type != CHIP_NAVI12) | |
1776 | return 0; | |
258620d0 AD |
1777 | } |
1778 | ||
e2a75f88 | 1779 | switch (adev->asic_type) { |
e2a75f88 AD |
1780 | #ifdef CONFIG_DRM_AMDGPU_SI |
1781 | case CHIP_VERDE: | |
1782 | case CHIP_TAHITI: | |
1783 | case CHIP_PITCAIRN: | |
1784 | case CHIP_OLAND: | |
1785 | case CHIP_HAINAN: | |
1786 | #endif | |
1787 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1788 | case CHIP_BONAIRE: | |
1789 | case CHIP_HAWAII: | |
1790 | case CHIP_KAVERI: | |
1791 | case CHIP_KABINI: | |
1792 | case CHIP_MULLINS: | |
1793 | #endif | |
da87c30b AD |
1794 | case CHIP_TOPAZ: |
1795 | case CHIP_TONGA: | |
1796 | case CHIP_FIJI: | |
1797 | case CHIP_POLARIS10: | |
1798 | case CHIP_POLARIS11: | |
1799 | case CHIP_POLARIS12: | |
1800 | case CHIP_VEGAM: | |
1801 | case CHIP_CARRIZO: | |
1802 | case CHIP_STONEY: | |
27c0bc71 | 1803 | case CHIP_VEGA20: |
44b3253a | 1804 | case CHIP_ALDEBARAN: |
84d244a3 JC |
1805 | case CHIP_SIENNA_CICHLID: |
1806 | case CHIP_NAVY_FLOUNDER: | |
eac88a5f | 1807 | case CHIP_DIMGREY_CAVEFISH: |
e2a75f88 AD |
1808 | default: |
1809 | return 0; | |
1810 | case CHIP_VEGA10: | |
1811 | chip_name = "vega10"; | |
1812 | break; | |
3f76dced AD |
1813 | case CHIP_VEGA12: |
1814 | chip_name = "vega12"; | |
1815 | break; | |
2d2e5e7e | 1816 | case CHIP_RAVEN: |
54f78a76 | 1817 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1818 | chip_name = "raven2"; |
54f78a76 | 1819 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1820 | chip_name = "picasso"; |
54c4d17e FX |
1821 | else |
1822 | chip_name = "raven"; | |
2d2e5e7e | 1823 | break; |
65e60f6e LM |
1824 | case CHIP_ARCTURUS: |
1825 | chip_name = "arcturus"; | |
1826 | break; | |
b51a26a0 | 1827 | case CHIP_RENOIR: |
2e62f0b5 PL |
1828 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
1829 | chip_name = "renoir"; | |
1830 | else | |
1831 | chip_name = "green_sardine"; | |
b51a26a0 | 1832 | break; |
23c6268e HR |
1833 | case CHIP_NAVI10: |
1834 | chip_name = "navi10"; | |
1835 | break; | |
ed42cfe1 XY |
1836 | case CHIP_NAVI14: |
1837 | chip_name = "navi14"; | |
1838 | break; | |
42b325e5 XY |
1839 | case CHIP_NAVI12: |
1840 | chip_name = "navi12"; | |
1841 | break; | |
4e52a9f8 HR |
1842 | case CHIP_VANGOGH: |
1843 | chip_name = "vangogh"; | |
1844 | break; | |
e2a75f88 AD |
1845 | } |
1846 | ||
1847 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1848 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1849 | if (err) { |
1850 | dev_err(adev->dev, | |
1851 | "Failed to load gpu_info firmware \"%s\"\n", | |
1852 | fw_name); | |
1853 | goto out; | |
1854 | } | |
ab4fe3e1 | 1855 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1856 | if (err) { |
1857 | dev_err(adev->dev, | |
1858 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1859 | fw_name); | |
1860 | goto out; | |
1861 | } | |
1862 | ||
ab4fe3e1 | 1863 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1864 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1865 | ||
1866 | switch (hdr->version_major) { | |
1867 | case 1: | |
1868 | { | |
1869 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1870 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1871 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1872 | ||
cc375d8c TY |
1873 | /* |
1874 | * Should be droped when DAL no longer needs it. | |
1875 | */ | |
1876 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
1877 | goto parse_soc_bounding_box; |
1878 | ||
b5ab16bf AD |
1879 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1880 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1881 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1882 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1883 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1884 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1885 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1886 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1887 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1888 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1889 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1890 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1891 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1892 | adev->gfx.cu_info.max_waves_per_simd = |
1893 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1894 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1895 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1896 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 1897 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
1898 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
1899 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
1900 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1901 | adev->gfx.config.num_sc_per_sh = | |
1902 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
1903 | adev->gfx.config.num_packer_per_sc = | |
1904 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
1905 | } | |
ec51d3fa XY |
1906 | |
1907 | parse_soc_bounding_box: | |
ec51d3fa XY |
1908 | /* |
1909 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 1910 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 1911 | */ |
48321c3d HW |
1912 | if (hdr->version_minor == 2) { |
1913 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
1914 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
1915 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1916 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
1917 | } | |
e2a75f88 AD |
1918 | break; |
1919 | } | |
1920 | default: | |
1921 | dev_err(adev->dev, | |
1922 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1923 | err = -EINVAL; | |
1924 | goto out; | |
1925 | } | |
1926 | out: | |
e2a75f88 AD |
1927 | return err; |
1928 | } | |
1929 | ||
e3ecdffa AD |
1930 | /** |
1931 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1932 | * | |
1933 | * @adev: amdgpu_device pointer | |
1934 | * | |
1935 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1936 | * up each asic are discovered each IP's early_init callback is run. This | |
1937 | * is the first stage in initializing the asic. | |
1938 | * Returns 0 on success, negative error code on failure. | |
1939 | */ | |
06ec9070 | 1940 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1941 | { |
aaa36a97 | 1942 | int i, r; |
d38ceaf9 | 1943 | |
483ef985 | 1944 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1945 | |
00a979f3 | 1946 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 1947 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
1948 | if (r) |
1949 | return r; | |
00a979f3 WS |
1950 | } |
1951 | ||
d38ceaf9 | 1952 | switch (adev->asic_type) { |
33f34802 KW |
1953 | #ifdef CONFIG_DRM_AMDGPU_SI |
1954 | case CHIP_VERDE: | |
1955 | case CHIP_TAHITI: | |
1956 | case CHIP_PITCAIRN: | |
1957 | case CHIP_OLAND: | |
1958 | case CHIP_HAINAN: | |
295d0daf | 1959 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1960 | r = si_set_ip_blocks(adev); |
1961 | if (r) | |
1962 | return r; | |
1963 | break; | |
1964 | #endif | |
a2e73f56 AD |
1965 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1966 | case CHIP_BONAIRE: | |
1967 | case CHIP_HAWAII: | |
1968 | case CHIP_KAVERI: | |
1969 | case CHIP_KABINI: | |
1970 | case CHIP_MULLINS: | |
e1ad2d53 | 1971 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 1972 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
1973 | else |
1974 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
1975 | |
1976 | r = cik_set_ip_blocks(adev); | |
1977 | if (r) | |
1978 | return r; | |
1979 | break; | |
1980 | #endif | |
da87c30b AD |
1981 | case CHIP_TOPAZ: |
1982 | case CHIP_TONGA: | |
1983 | case CHIP_FIJI: | |
1984 | case CHIP_POLARIS10: | |
1985 | case CHIP_POLARIS11: | |
1986 | case CHIP_POLARIS12: | |
1987 | case CHIP_VEGAM: | |
1988 | case CHIP_CARRIZO: | |
1989 | case CHIP_STONEY: | |
1990 | if (adev->flags & AMD_IS_APU) | |
1991 | adev->family = AMDGPU_FAMILY_CZ; | |
1992 | else | |
1993 | adev->family = AMDGPU_FAMILY_VI; | |
1994 | ||
1995 | r = vi_set_ip_blocks(adev); | |
1996 | if (r) | |
1997 | return r; | |
1998 | break; | |
e48a3cd9 AD |
1999 | case CHIP_VEGA10: |
2000 | case CHIP_VEGA12: | |
e4bd8170 | 2001 | case CHIP_VEGA20: |
e48a3cd9 | 2002 | case CHIP_RAVEN: |
61cf44c1 | 2003 | case CHIP_ARCTURUS: |
b51a26a0 | 2004 | case CHIP_RENOIR: |
c00a18ec | 2005 | case CHIP_ALDEBARAN: |
70534d1e | 2006 | if (adev->flags & AMD_IS_APU) |
2ca8a5d2 CZ |
2007 | adev->family = AMDGPU_FAMILY_RV; |
2008 | else | |
2009 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
2010 | |
2011 | r = soc15_set_ip_blocks(adev); | |
2012 | if (r) | |
2013 | return r; | |
2014 | break; | |
0a5b8c7b | 2015 | case CHIP_NAVI10: |
7ecb5cd4 | 2016 | case CHIP_NAVI14: |
4808cf9c | 2017 | case CHIP_NAVI12: |
11e8aef5 | 2018 | case CHIP_SIENNA_CICHLID: |
41f446bf | 2019 | case CHIP_NAVY_FLOUNDER: |
144722fa | 2020 | case CHIP_DIMGREY_CAVEFISH: |
4e52a9f8 HR |
2021 | case CHIP_VANGOGH: |
2022 | if (adev->asic_type == CHIP_VANGOGH) | |
2023 | adev->family = AMDGPU_FAMILY_VGH; | |
2024 | else | |
2025 | adev->family = AMDGPU_FAMILY_NV; | |
0a5b8c7b HR |
2026 | |
2027 | r = nv_set_ip_blocks(adev); | |
2028 | if (r) | |
2029 | return r; | |
2030 | break; | |
d38ceaf9 AD |
2031 | default: |
2032 | /* FIXME: not supported yet */ | |
2033 | return -EINVAL; | |
2034 | } | |
2035 | ||
1884734a | 2036 | amdgpu_amdkfd_device_probe(adev); |
2037 | ||
3b94fb10 | 2038 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2039 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2040 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2041 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2042 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
00f54b97 | 2043 | |
d38ceaf9 AD |
2044 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2045 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
2046 | DRM_ERROR("disabled ip block: %d <%s>\n", |
2047 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 2048 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2049 | } else { |
a1255107 AD |
2050 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2051 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2052 | if (r == -ENOENT) { |
a1255107 | 2053 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2054 | } else if (r) { |
a1255107 AD |
2055 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2056 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2057 | return r; |
2c1a2784 | 2058 | } else { |
a1255107 | 2059 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2060 | } |
974e6b64 | 2061 | } else { |
a1255107 | 2062 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2063 | } |
d38ceaf9 | 2064 | } |
21a249ca AD |
2065 | /* get the vbios after the asic_funcs are set up */ |
2066 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2067 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2068 | if (r) | |
2069 | return r; | |
2070 | ||
21a249ca AD |
2071 | /* Read BIOS */ |
2072 | if (!amdgpu_get_bios(adev)) | |
2073 | return -EINVAL; | |
2074 | ||
2075 | r = amdgpu_atombios_init(adev); | |
2076 | if (r) { | |
2077 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2078 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2079 | return r; | |
2080 | } | |
2081 | } | |
d38ceaf9 AD |
2082 | } |
2083 | ||
395d1fb9 NH |
2084 | adev->cg_flags &= amdgpu_cg_mask; |
2085 | adev->pg_flags &= amdgpu_pg_mask; | |
2086 | ||
d38ceaf9 AD |
2087 | return 0; |
2088 | } | |
2089 | ||
0a4f2520 RZ |
2090 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2091 | { | |
2092 | int i, r; | |
2093 | ||
2094 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2095 | if (!adev->ip_blocks[i].status.sw) | |
2096 | continue; | |
2097 | if (adev->ip_blocks[i].status.hw) | |
2098 | continue; | |
2099 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2100 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2101 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2102 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2103 | if (r) { | |
2104 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2105 | adev->ip_blocks[i].version->funcs->name, r); | |
2106 | return r; | |
2107 | } | |
2108 | adev->ip_blocks[i].status.hw = true; | |
2109 | } | |
2110 | } | |
2111 | ||
2112 | return 0; | |
2113 | } | |
2114 | ||
2115 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2116 | { | |
2117 | int i, r; | |
2118 | ||
2119 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2120 | if (!adev->ip_blocks[i].status.sw) | |
2121 | continue; | |
2122 | if (adev->ip_blocks[i].status.hw) | |
2123 | continue; | |
2124 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2125 | if (r) { | |
2126 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2127 | adev->ip_blocks[i].version->funcs->name, r); | |
2128 | return r; | |
2129 | } | |
2130 | adev->ip_blocks[i].status.hw = true; | |
2131 | } | |
2132 | ||
2133 | return 0; | |
2134 | } | |
2135 | ||
7a3e0bb2 RZ |
2136 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2137 | { | |
2138 | int r = 0; | |
2139 | int i; | |
80f41f84 | 2140 | uint32_t smu_version; |
7a3e0bb2 RZ |
2141 | |
2142 | if (adev->asic_type >= CHIP_VEGA10) { | |
2143 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2144 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2145 | continue; | |
2146 | ||
e3c1b071 | 2147 | if (!adev->ip_blocks[i].status.sw) |
2148 | continue; | |
2149 | ||
482f0e53 ML |
2150 | /* no need to do the fw loading again if already done*/ |
2151 | if (adev->ip_blocks[i].status.hw == true) | |
2152 | break; | |
2153 | ||
53b3f8f4 | 2154 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2155 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2156 | if (r) { | |
2157 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2158 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2159 | return r; |
2160 | } | |
2161 | } else { | |
2162 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2163 | if (r) { | |
2164 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2165 | adev->ip_blocks[i].version->funcs->name, r); | |
2166 | return r; | |
7a3e0bb2 | 2167 | } |
7a3e0bb2 | 2168 | } |
482f0e53 ML |
2169 | |
2170 | adev->ip_blocks[i].status.hw = true; | |
2171 | break; | |
7a3e0bb2 RZ |
2172 | } |
2173 | } | |
482f0e53 | 2174 | |
8973d9ec ED |
2175 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2176 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2177 | |
80f41f84 | 2178 | return r; |
7a3e0bb2 RZ |
2179 | } |
2180 | ||
e3ecdffa AD |
2181 | /** |
2182 | * amdgpu_device_ip_init - run init for hardware IPs | |
2183 | * | |
2184 | * @adev: amdgpu_device pointer | |
2185 | * | |
2186 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2187 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2188 | * are run. sw_init initializes the software state associated with each IP | |
2189 | * and hw_init initializes the hardware associated with each IP. | |
2190 | * Returns 0 on success, negative error code on failure. | |
2191 | */ | |
06ec9070 | 2192 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2193 | { |
2194 | int i, r; | |
2195 | ||
c030f2e4 | 2196 | r = amdgpu_ras_init(adev); |
2197 | if (r) | |
2198 | return r; | |
2199 | ||
d38ceaf9 | 2200 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2201 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2202 | continue; |
a1255107 | 2203 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2204 | if (r) { |
a1255107 AD |
2205 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2206 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2207 | goto init_failed; |
2c1a2784 | 2208 | } |
a1255107 | 2209 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2210 | |
d38ceaf9 | 2211 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2212 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 2213 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2214 | if (r) { |
2215 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2216 | goto init_failed; |
2c1a2784 | 2217 | } |
a1255107 | 2218 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2219 | if (r) { |
2220 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2221 | goto init_failed; |
2c1a2784 | 2222 | } |
06ec9070 | 2223 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2224 | if (r) { |
06ec9070 | 2225 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2226 | goto init_failed; |
2c1a2784 | 2227 | } |
a1255107 | 2228 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2229 | |
2230 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2231 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2232 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2233 | AMDGPU_GEM_DOMAIN_VRAM, | |
2234 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2235 | if (r) { |
2236 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2237 | goto init_failed; |
2493664f ML |
2238 | } |
2239 | } | |
d38ceaf9 AD |
2240 | } |
2241 | } | |
2242 | ||
c9ffa427 YT |
2243 | if (amdgpu_sriov_vf(adev)) |
2244 | amdgpu_virt_init_data_exchange(adev); | |
2245 | ||
533aed27 AG |
2246 | r = amdgpu_ib_pool_init(adev); |
2247 | if (r) { | |
2248 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2249 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2250 | goto init_failed; | |
2251 | } | |
2252 | ||
c8963ea4 RZ |
2253 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2254 | if (r) | |
72d3f592 | 2255 | goto init_failed; |
0a4f2520 RZ |
2256 | |
2257 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2258 | if (r) | |
72d3f592 | 2259 | goto init_failed; |
0a4f2520 | 2260 | |
7a3e0bb2 RZ |
2261 | r = amdgpu_device_fw_loading(adev); |
2262 | if (r) | |
72d3f592 | 2263 | goto init_failed; |
7a3e0bb2 | 2264 | |
0a4f2520 RZ |
2265 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2266 | if (r) | |
72d3f592 | 2267 | goto init_failed; |
d38ceaf9 | 2268 | |
121a2bc6 AG |
2269 | /* |
2270 | * retired pages will be loaded from eeprom and reserved here, | |
2271 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2272 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2273 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2274 | * |
2275 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2276 | * failure from bad gpu situation and stop amdgpu init process | |
2277 | * accordingly. For other failed cases, it will still release all | |
2278 | * the resource and print error message, rather than returning one | |
2279 | * negative value to upper level. | |
121a2bc6 AG |
2280 | * |
2281 | * Note: theoretically, this should be called before all vram allocations | |
2282 | * to protect retired page from abusing | |
2283 | */ | |
b82e65a9 GC |
2284 | r = amdgpu_ras_recovery_init(adev); |
2285 | if (r) | |
2286 | goto init_failed; | |
121a2bc6 | 2287 | |
3e2e2ab5 HZ |
2288 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2289 | amdgpu_xgmi_add_device(adev); | |
e3c1b071 | 2290 | |
2291 | /* Don't init kfd if whole hive need to be reset during init */ | |
2292 | if (!adev->gmc.xgmi.pending_reset) | |
2293 | amdgpu_amdkfd_device_init(adev); | |
c6332b97 | 2294 | |
bd607166 KR |
2295 | amdgpu_fru_get_product_info(adev); |
2296 | ||
72d3f592 | 2297 | init_failed: |
c9ffa427 | 2298 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2299 | amdgpu_virt_release_full_gpu(adev, true); |
2300 | ||
72d3f592 | 2301 | return r; |
d38ceaf9 AD |
2302 | } |
2303 | ||
e3ecdffa AD |
2304 | /** |
2305 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2306 | * | |
2307 | * @adev: amdgpu_device pointer | |
2308 | * | |
2309 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2310 | * this function before a GPU reset. If the value is retained after a | |
2311 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2312 | */ | |
06ec9070 | 2313 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2314 | { |
2315 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2316 | } | |
2317 | ||
e3ecdffa AD |
2318 | /** |
2319 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2320 | * | |
2321 | * @adev: amdgpu_device pointer | |
2322 | * | |
2323 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2324 | * The driver calls this after a GPU reset to see if the contents of | |
2325 | * VRAM is lost or now. | |
2326 | * returns true if vram is lost, false if not. | |
2327 | */ | |
06ec9070 | 2328 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2329 | { |
dadce777 EQ |
2330 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2331 | AMDGPU_RESET_MAGIC_NUM)) | |
2332 | return true; | |
2333 | ||
53b3f8f4 | 2334 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2335 | return false; |
2336 | ||
2337 | /* | |
2338 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2339 | * always assumed to be lost. | |
2340 | */ | |
2341 | switch (amdgpu_asic_reset_method(adev)) { | |
2342 | case AMD_RESET_METHOD_BACO: | |
2343 | case AMD_RESET_METHOD_MODE1: | |
2344 | return true; | |
2345 | default: | |
2346 | return false; | |
2347 | } | |
0c49e0b8 CZ |
2348 | } |
2349 | ||
e3ecdffa | 2350 | /** |
1112a46b | 2351 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2352 | * |
2353 | * @adev: amdgpu_device pointer | |
b8b72130 | 2354 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2355 | * |
e3ecdffa | 2356 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2357 | * set_clockgating_state callbacks are run. |
2358 | * Late initialization pass enabling clockgating for hardware IPs. | |
2359 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2360 | * Returns 0 on success, negative error code on failure. |
2361 | */ | |
fdd34271 | 2362 | |
1112a46b RZ |
2363 | static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2364 | enum amd_clockgating_state state) | |
d38ceaf9 | 2365 | { |
1112a46b | 2366 | int i, j, r; |
d38ceaf9 | 2367 | |
4a2ba394 SL |
2368 | if (amdgpu_emu_mode == 1) |
2369 | return 0; | |
2370 | ||
1112a46b RZ |
2371 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2372 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2373 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2374 | continue; |
4a446d55 | 2375 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2376 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2377 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2378 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2379 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2380 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2381 | /* enable clockgating to save power */ |
a1255107 | 2382 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2383 | state); |
4a446d55 AD |
2384 | if (r) { |
2385 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2386 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2387 | return r; |
2388 | } | |
b0b00ff1 | 2389 | } |
d38ceaf9 | 2390 | } |
06b18f61 | 2391 | |
c9f96fd5 RZ |
2392 | return 0; |
2393 | } | |
2394 | ||
1112a46b | 2395 | static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state) |
c9f96fd5 | 2396 | { |
1112a46b | 2397 | int i, j, r; |
06b18f61 | 2398 | |
c9f96fd5 RZ |
2399 | if (amdgpu_emu_mode == 1) |
2400 | return 0; | |
2401 | ||
1112a46b RZ |
2402 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2403 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2404 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 RZ |
2405 | continue; |
2406 | /* skip CG for VCE/UVD, it's handled specially */ | |
2407 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2408 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2409 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2410 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2411 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2412 | /* enable powergating to save power */ | |
2413 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2414 | state); |
c9f96fd5 RZ |
2415 | if (r) { |
2416 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2417 | adev->ip_blocks[i].version->funcs->name, r); | |
2418 | return r; | |
2419 | } | |
2420 | } | |
2421 | } | |
2dc80b00 S |
2422 | return 0; |
2423 | } | |
2424 | ||
beff74bc AD |
2425 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2426 | { | |
2427 | struct amdgpu_gpu_instance *gpu_ins; | |
2428 | struct amdgpu_device *adev; | |
2429 | int i, ret = 0; | |
2430 | ||
2431 | mutex_lock(&mgpu_info.mutex); | |
2432 | ||
2433 | /* | |
2434 | * MGPU fan boost feature should be enabled | |
2435 | * only when there are two or more dGPUs in | |
2436 | * the system | |
2437 | */ | |
2438 | if (mgpu_info.num_dgpu < 2) | |
2439 | goto out; | |
2440 | ||
2441 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2442 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2443 | adev = gpu_ins->adev; | |
2444 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2445 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2446 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2447 | if (ret) | |
2448 | break; | |
2449 | ||
2450 | gpu_ins->mgpu_fan_enabled = 1; | |
2451 | } | |
2452 | } | |
2453 | ||
2454 | out: | |
2455 | mutex_unlock(&mgpu_info.mutex); | |
2456 | ||
2457 | return ret; | |
2458 | } | |
2459 | ||
e3ecdffa AD |
2460 | /** |
2461 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2462 | * | |
2463 | * @adev: amdgpu_device pointer | |
2464 | * | |
2465 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2466 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2467 | * late_init covers any special initialization that an IP requires | |
2468 | * after all of the have been initialized or something that needs to happen | |
2469 | * late in the init process. | |
2470 | * Returns 0 on success, negative error code on failure. | |
2471 | */ | |
06ec9070 | 2472 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2473 | { |
60599a03 | 2474 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2475 | int i = 0, r; |
2476 | ||
2477 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2478 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2479 | continue; |
2480 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2481 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2482 | if (r) { | |
2483 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2484 | adev->ip_blocks[i].version->funcs->name, r); | |
2485 | return r; | |
2486 | } | |
2dc80b00 | 2487 | } |
73f847db | 2488 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2489 | } |
2490 | ||
a891d239 DL |
2491 | amdgpu_ras_set_error_query_ready(adev, true); |
2492 | ||
1112a46b RZ |
2493 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2494 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2495 | |
06ec9070 | 2496 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2497 | |
beff74bc AD |
2498 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2499 | if (r) | |
2500 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2501 | ||
2d02893f | 2502 | /* For XGMI + passthrough configuration on arcturus, enable light SBR */ |
2503 | if (adev->asic_type == CHIP_ARCTURUS && | |
2504 | amdgpu_passthrough(adev) && | |
2505 | adev->gmc.xgmi.num_physical_nodes > 1) | |
2506 | smu_set_light_sbr(&adev->smu, true); | |
60599a03 EQ |
2507 | |
2508 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2509 | mutex_lock(&mgpu_info.mutex); | |
2510 | ||
2511 | /* | |
2512 | * Reset device p-state to low as this was booted with high. | |
2513 | * | |
2514 | * This should be performed only after all devices from the same | |
2515 | * hive get initialized. | |
2516 | * | |
2517 | * However, it's unknown how many device in the hive in advance. | |
2518 | * As this is counted one by one during devices initializations. | |
2519 | * | |
2520 | * So, we wait for all XGMI interlinked devices initialized. | |
2521 | * This may bring some delays as those devices may come from | |
2522 | * different hives. But that should be OK. | |
2523 | */ | |
2524 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2525 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2526 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2527 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2528 | continue; | |
2529 | ||
d84a430d JK |
2530 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2531 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2532 | if (r) { |
2533 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2534 | break; | |
2535 | } | |
2536 | } | |
2537 | } | |
2538 | ||
2539 | mutex_unlock(&mgpu_info.mutex); | |
2540 | } | |
2541 | ||
d38ceaf9 AD |
2542 | return 0; |
2543 | } | |
2544 | ||
e3ecdffa AD |
2545 | /** |
2546 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2547 | * | |
2548 | * @adev: amdgpu_device pointer | |
2549 | * | |
2550 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2551 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2552 | * are run. hw_fini tears down the hardware associated with each IP | |
2553 | * and sw_fini tears down any software state associated with each IP. | |
2554 | * Returns 0 on success, negative error code on failure. | |
2555 | */ | |
06ec9070 | 2556 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
2557 | { |
2558 | int i, r; | |
2559 | ||
5278a159 SY |
2560 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) |
2561 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2562 | ||
c030f2e4 | 2563 | amdgpu_ras_pre_fini(adev); |
2564 | ||
a82400b5 AG |
2565 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2566 | amdgpu_xgmi_remove_device(adev); | |
2567 | ||
05df1f01 | 2568 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
2569 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2570 | ||
26eb6b51 DL |
2571 | amdgpu_amdkfd_device_fini(adev); |
2572 | ||
3e96dbfd AD |
2573 | /* need to disable SMC first */ |
2574 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2575 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 2576 | continue; |
fdd34271 | 2577 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 2578 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
2579 | /* XXX handle errors */ |
2580 | if (r) { | |
2581 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 2582 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 2583 | } |
a1255107 | 2584 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
2585 | break; |
2586 | } | |
2587 | } | |
2588 | ||
d38ceaf9 | 2589 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2590 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2591 | continue; |
8201a67a | 2592 | |
a1255107 | 2593 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2594 | /* XXX handle errors */ |
2c1a2784 | 2595 | if (r) { |
a1255107 AD |
2596 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2597 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2598 | } |
8201a67a | 2599 | |
a1255107 | 2600 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2601 | } |
2602 | ||
9950cda2 | 2603 | |
d38ceaf9 | 2604 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2605 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2606 | continue; |
c12aba3a ML |
2607 | |
2608 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2609 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2610 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2611 | amdgpu_device_wb_fini(adev); |
2612 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2613 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2614 | } |
2615 | ||
a1255107 | 2616 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2617 | /* XXX handle errors */ |
2c1a2784 | 2618 | if (r) { |
a1255107 AD |
2619 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2620 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2621 | } |
a1255107 AD |
2622 | adev->ip_blocks[i].status.sw = false; |
2623 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2624 | } |
2625 | ||
a6dcfd9c | 2626 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2627 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2628 | continue; |
a1255107 AD |
2629 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2630 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2631 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2632 | } |
2633 | ||
c030f2e4 | 2634 | amdgpu_ras_fini(adev); |
2635 | ||
030308fc | 2636 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
2637 | if (amdgpu_virt_release_full_gpu(adev, false)) |
2638 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 2639 | |
d38ceaf9 AD |
2640 | return 0; |
2641 | } | |
2642 | ||
e3ecdffa | 2643 | /** |
beff74bc | 2644 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2645 | * |
1112a46b | 2646 | * @work: work_struct. |
e3ecdffa | 2647 | */ |
beff74bc | 2648 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2649 | { |
2650 | struct amdgpu_device *adev = | |
beff74bc | 2651 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2652 | int r; |
2653 | ||
2654 | r = amdgpu_ib_ring_tests(adev); | |
2655 | if (r) | |
2656 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2657 | } |
2658 | ||
1e317b99 RZ |
2659 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2660 | { | |
2661 | struct amdgpu_device *adev = | |
2662 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2663 | ||
2664 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
2665 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
2666 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2667 | adev->gfx.gfx_off_state = true; | |
2668 | } | |
2669 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
2670 | } | |
2671 | ||
e3ecdffa | 2672 | /** |
e7854a03 | 2673 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2674 | * |
2675 | * @adev: amdgpu_device pointer | |
2676 | * | |
2677 | * Main suspend function for hardware IPs. The list of all the hardware | |
2678 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2679 | * suspend callbacks are run. suspend puts the hardware and software state | |
2680 | * in each IP into a state suitable for suspend. | |
2681 | * Returns 0 on success, negative error code on failure. | |
2682 | */ | |
e7854a03 AD |
2683 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2684 | { | |
2685 | int i, r; | |
2686 | ||
b00978de PL |
2687 | if (adev->in_poweroff_reboot_com || |
2688 | !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) { | |
628c36d7 PL |
2689 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2690 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
2691 | } | |
05df1f01 | 2692 | |
e7854a03 AD |
2693 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2694 | if (!adev->ip_blocks[i].status.valid) | |
2695 | continue; | |
2b9f7848 | 2696 | |
e7854a03 | 2697 | /* displays are handled separately */ |
2b9f7848 ND |
2698 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2699 | continue; | |
2700 | ||
2701 | /* XXX handle errors */ | |
2702 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2703 | /* XXX handle errors */ | |
2704 | if (r) { | |
2705 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2706 | adev->ip_blocks[i].version->funcs->name, r); | |
2707 | return r; | |
e7854a03 | 2708 | } |
2b9f7848 ND |
2709 | |
2710 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2711 | } |
2712 | ||
e7854a03 AD |
2713 | return 0; |
2714 | } | |
2715 | ||
2716 | /** | |
2717 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2718 | * | |
2719 | * @adev: amdgpu_device pointer | |
2720 | * | |
2721 | * Main suspend function for hardware IPs. The list of all the hardware | |
2722 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2723 | * suspend callbacks are run. suspend puts the hardware and software state | |
2724 | * in each IP into a state suitable for suspend. | |
2725 | * Returns 0 on success, negative error code on failure. | |
2726 | */ | |
2727 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2728 | { |
2729 | int i, r; | |
2730 | ||
2731 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 2732 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2733 | continue; |
e7854a03 AD |
2734 | /* displays are handled in phase1 */ |
2735 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2736 | continue; | |
bff77e86 LM |
2737 | /* PSP lost connection when err_event_athub occurs */ |
2738 | if (amdgpu_ras_intr_triggered() && | |
2739 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2740 | adev->ip_blocks[i].status.hw = false; | |
2741 | continue; | |
2742 | } | |
e3c1b071 | 2743 | |
2744 | /* skip unnecessary suspend if we do not initialize them yet */ | |
2745 | if (adev->gmc.xgmi.pending_reset && | |
2746 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2747 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
2748 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2749 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
2750 | adev->ip_blocks[i].status.hw = false; | |
2751 | continue; | |
2752 | } | |
d38ceaf9 | 2753 | /* XXX handle errors */ |
a1255107 | 2754 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2755 | /* XXX handle errors */ |
2c1a2784 | 2756 | if (r) { |
a1255107 AD |
2757 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2758 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2759 | } |
876923fb | 2760 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 2761 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
2762 | if(!amdgpu_sriov_vf(adev)){ |
2763 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2764 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
2765 | if (r) { | |
2766 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2767 | adev->mp1_state, r); | |
2768 | return r; | |
2769 | } | |
a3a09142 AD |
2770 | } |
2771 | } | |
d38ceaf9 AD |
2772 | } |
2773 | ||
2774 | return 0; | |
2775 | } | |
2776 | ||
e7854a03 AD |
2777 | /** |
2778 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2779 | * | |
2780 | * @adev: amdgpu_device pointer | |
2781 | * | |
2782 | * Main suspend function for hardware IPs. The list of all the hardware | |
2783 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2784 | * suspend callbacks are run. suspend puts the hardware and software state | |
2785 | * in each IP into a state suitable for suspend. | |
2786 | * Returns 0 on success, negative error code on failure. | |
2787 | */ | |
2788 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2789 | { | |
2790 | int r; | |
2791 | ||
3c73683c JC |
2792 | if (amdgpu_sriov_vf(adev)) { |
2793 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 2794 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 2795 | } |
e7819644 | 2796 | |
e7854a03 AD |
2797 | r = amdgpu_device_ip_suspend_phase1(adev); |
2798 | if (r) | |
2799 | return r; | |
2800 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2801 | ||
e7819644 YT |
2802 | if (amdgpu_sriov_vf(adev)) |
2803 | amdgpu_virt_release_full_gpu(adev, false); | |
2804 | ||
e7854a03 AD |
2805 | return r; |
2806 | } | |
2807 | ||
06ec9070 | 2808 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2809 | { |
2810 | int i, r; | |
2811 | ||
2cb681b6 ML |
2812 | static enum amd_ip_block_type ip_order[] = { |
2813 | AMD_IP_BLOCK_TYPE_GMC, | |
2814 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2815 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2816 | AMD_IP_BLOCK_TYPE_IH, |
2817 | }; | |
a90ad3c2 | 2818 | |
2cb681b6 ML |
2819 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2820 | int j; | |
2821 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2822 | |
4cd2a96d J |
2823 | block = &adev->ip_blocks[i]; |
2824 | block->status.hw = false; | |
2cb681b6 | 2825 | |
4cd2a96d | 2826 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 2827 | |
4cd2a96d | 2828 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
2829 | !block->status.valid) |
2830 | continue; | |
2831 | ||
2832 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2833 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2834 | if (r) |
2835 | return r; | |
482f0e53 | 2836 | block->status.hw = true; |
a90ad3c2 ML |
2837 | } |
2838 | } | |
2839 | ||
2840 | return 0; | |
2841 | } | |
2842 | ||
06ec9070 | 2843 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2844 | { |
2845 | int i, r; | |
2846 | ||
2cb681b6 ML |
2847 | static enum amd_ip_block_type ip_order[] = { |
2848 | AMD_IP_BLOCK_TYPE_SMC, | |
2849 | AMD_IP_BLOCK_TYPE_DCE, | |
2850 | AMD_IP_BLOCK_TYPE_GFX, | |
2851 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 2852 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
2853 | AMD_IP_BLOCK_TYPE_VCE, |
2854 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 2855 | }; |
a90ad3c2 | 2856 | |
2cb681b6 ML |
2857 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2858 | int j; | |
2859 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2860 | |
2cb681b6 ML |
2861 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2862 | block = &adev->ip_blocks[j]; | |
2863 | ||
2864 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
2865 | !block->status.valid || |
2866 | block->status.hw) | |
2cb681b6 ML |
2867 | continue; |
2868 | ||
895bd048 JZ |
2869 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
2870 | r = block->version->funcs->resume(adev); | |
2871 | else | |
2872 | r = block->version->funcs->hw_init(adev); | |
2873 | ||
0aaeefcc | 2874 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2875 | if (r) |
2876 | return r; | |
482f0e53 | 2877 | block->status.hw = true; |
a90ad3c2 ML |
2878 | } |
2879 | } | |
2880 | ||
2881 | return 0; | |
2882 | } | |
2883 | ||
e3ecdffa AD |
2884 | /** |
2885 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2886 | * | |
2887 | * @adev: amdgpu_device pointer | |
2888 | * | |
2889 | * First resume function for hardware IPs. The list of all the hardware | |
2890 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2891 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2892 | * after a suspend and updates the software state as necessary. This | |
2893 | * function is also used for restoring the GPU after a GPU reset. | |
2894 | * Returns 0 on success, negative error code on failure. | |
2895 | */ | |
06ec9070 | 2896 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2897 | { |
2898 | int i, r; | |
2899 | ||
a90ad3c2 | 2900 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 2901 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 2902 | continue; |
a90ad3c2 | 2903 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2904 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2905 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 2906 | |
fcf0649f CZ |
2907 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2908 | if (r) { | |
2909 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2910 | adev->ip_blocks[i].version->funcs->name, r); | |
2911 | return r; | |
2912 | } | |
482f0e53 | 2913 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
2914 | } |
2915 | } | |
2916 | ||
2917 | return 0; | |
2918 | } | |
2919 | ||
e3ecdffa AD |
2920 | /** |
2921 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2922 | * | |
2923 | * @adev: amdgpu_device pointer | |
2924 | * | |
2925 | * First resume function for hardware IPs. The list of all the hardware | |
2926 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2927 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2928 | * functional state after a suspend and updates the software state as | |
2929 | * necessary. This function is also used for restoring the GPU after a GPU | |
2930 | * reset. | |
2931 | * Returns 0 on success, negative error code on failure. | |
2932 | */ | |
06ec9070 | 2933 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2934 | { |
2935 | int i, r; | |
2936 | ||
2937 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 2938 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2939 | continue; |
fcf0649f | 2940 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 2941 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
2942 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
2943 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 2944 | continue; |
a1255107 | 2945 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2946 | if (r) { |
a1255107 AD |
2947 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2948 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2949 | return r; |
2c1a2784 | 2950 | } |
482f0e53 | 2951 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
2952 | } |
2953 | ||
2954 | return 0; | |
2955 | } | |
2956 | ||
e3ecdffa AD |
2957 | /** |
2958 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2959 | * | |
2960 | * @adev: amdgpu_device pointer | |
2961 | * | |
2962 | * Main resume function for hardware IPs. The hardware IPs | |
2963 | * are split into two resume functions because they are | |
2964 | * are also used in in recovering from a GPU reset and some additional | |
2965 | * steps need to be take between them. In this case (S3/S4) they are | |
2966 | * run sequentially. | |
2967 | * Returns 0 on success, negative error code on failure. | |
2968 | */ | |
06ec9070 | 2969 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2970 | { |
2971 | int r; | |
2972 | ||
06ec9070 | 2973 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2974 | if (r) |
2975 | return r; | |
7a3e0bb2 RZ |
2976 | |
2977 | r = amdgpu_device_fw_loading(adev); | |
2978 | if (r) | |
2979 | return r; | |
2980 | ||
06ec9070 | 2981 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2982 | |
2983 | return r; | |
2984 | } | |
2985 | ||
e3ecdffa AD |
2986 | /** |
2987 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2988 | * | |
2989 | * @adev: amdgpu_device pointer | |
2990 | * | |
2991 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2992 | */ | |
4e99a44e | 2993 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2994 | { |
6867e1b5 ML |
2995 | if (amdgpu_sriov_vf(adev)) { |
2996 | if (adev->is_atom_fw) { | |
2997 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2998 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2999 | } else { | |
3000 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3001 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3002 | } | |
3003 | ||
3004 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3005 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3006 | } |
048765ad AR |
3007 | } |
3008 | ||
e3ecdffa AD |
3009 | /** |
3010 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3011 | * | |
3012 | * @asic_type: AMD asic type | |
3013 | * | |
3014 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3015 | * returns true if DC has support, false if not. | |
3016 | */ | |
4562236b HW |
3017 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3018 | { | |
3019 | switch (asic_type) { | |
3020 | #if defined(CONFIG_DRM_AMD_DC) | |
64200c46 MR |
3021 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3022 | case CHIP_TAHITI: | |
3023 | case CHIP_PITCAIRN: | |
3024 | case CHIP_VERDE: | |
3025 | case CHIP_OLAND: | |
3026 | #endif | |
4562236b | 3027 | case CHIP_BONAIRE: |
0d6fbccb | 3028 | case CHIP_KAVERI: |
367e6687 AD |
3029 | case CHIP_KABINI: |
3030 | case CHIP_MULLINS: | |
d9fda248 HW |
3031 | /* |
3032 | * We have systems in the wild with these ASICs that require | |
3033 | * LVDS and VGA support which is not supported with DC. | |
3034 | * | |
3035 | * Fallback to the non-DC driver here by default so as not to | |
3036 | * cause regressions. | |
3037 | */ | |
3038 | return amdgpu_dc > 0; | |
3039 | case CHIP_HAWAII: | |
4562236b HW |
3040 | case CHIP_CARRIZO: |
3041 | case CHIP_STONEY: | |
4562236b | 3042 | case CHIP_POLARIS10: |
675fd32b | 3043 | case CHIP_POLARIS11: |
2c8ad2d5 | 3044 | case CHIP_POLARIS12: |
675fd32b | 3045 | case CHIP_VEGAM: |
4562236b HW |
3046 | case CHIP_TONGA: |
3047 | case CHIP_FIJI: | |
42f8ffa1 | 3048 | case CHIP_VEGA10: |
dca7b401 | 3049 | case CHIP_VEGA12: |
c6034aa2 | 3050 | case CHIP_VEGA20: |
b86a1aa3 | 3051 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
fd187853 | 3052 | case CHIP_RAVEN: |
b4f199c7 | 3053 | case CHIP_NAVI10: |
8fceceb6 | 3054 | case CHIP_NAVI14: |
078655d9 | 3055 | case CHIP_NAVI12: |
e1c14c43 | 3056 | case CHIP_RENOIR: |
81d9bfb8 | 3057 | case CHIP_SIENNA_CICHLID: |
a6c5308f | 3058 | case CHIP_NAVY_FLOUNDER: |
7cc656e2 | 3059 | case CHIP_DIMGREY_CAVEFISH: |
84b934bc | 3060 | case CHIP_VANGOGH: |
42f8ffa1 | 3061 | #endif |
fd187853 | 3062 | return amdgpu_dc != 0; |
4562236b HW |
3063 | #endif |
3064 | default: | |
93b09a9a | 3065 | if (amdgpu_dc > 0) |
044a48f4 | 3066 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter " |
93b09a9a | 3067 | "but isn't supported by ASIC, ignoring\n"); |
4562236b HW |
3068 | return false; |
3069 | } | |
3070 | } | |
3071 | ||
3072 | /** | |
3073 | * amdgpu_device_has_dc_support - check if dc is supported | |
3074 | * | |
982a820b | 3075 | * @adev: amdgpu_device pointer |
4562236b HW |
3076 | * |
3077 | * Returns true for supported, false for not supported | |
3078 | */ | |
3079 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3080 | { | |
c997e8e2 | 3081 | if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display) |
2555039d XY |
3082 | return false; |
3083 | ||
4562236b HW |
3084 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3085 | } | |
3086 | ||
d4535e2c AG |
3087 | |
3088 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) | |
3089 | { | |
3090 | struct amdgpu_device *adev = | |
3091 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3092 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3093 | |
c6a6e2db AG |
3094 | /* It's a bug to not have a hive within this function */ |
3095 | if (WARN_ON(!hive)) | |
3096 | return; | |
3097 | ||
3098 | /* | |
3099 | * Use task barrier to synchronize all xgmi reset works across the | |
3100 | * hive. task_barrier_enter and task_barrier_exit will block | |
3101 | * until all the threads running the xgmi reset works reach | |
3102 | * those points. task_barrier_full will do both blocks. | |
3103 | */ | |
3104 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3105 | ||
3106 | task_barrier_enter(&hive->tb); | |
4a580877 | 3107 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3108 | |
3109 | if (adev->asic_reset_res) | |
3110 | goto fail; | |
3111 | ||
3112 | task_barrier_exit(&hive->tb); | |
4a580877 | 3113 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3114 | |
3115 | if (adev->asic_reset_res) | |
3116 | goto fail; | |
43c4d576 JC |
3117 | |
3118 | if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count) | |
3119 | adev->mmhub.funcs->reset_ras_error_count(adev); | |
c6a6e2db AG |
3120 | } else { |
3121 | ||
3122 | task_barrier_full(&hive->tb); | |
3123 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3124 | } | |
ce316fa5 | 3125 | |
c6a6e2db | 3126 | fail: |
d4535e2c | 3127 | if (adev->asic_reset_res) |
fed184e9 | 3128 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3129 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3130 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3131 | } |
3132 | ||
71f98027 AD |
3133 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3134 | { | |
3135 | char *input = amdgpu_lockup_timeout; | |
3136 | char *timeout_setting = NULL; | |
3137 | int index = 0; | |
3138 | long timeout; | |
3139 | int ret = 0; | |
3140 | ||
3141 | /* | |
3142 | * By default timeout for non compute jobs is 10000. | |
3143 | * And there is no timeout enforced on compute jobs. | |
3144 | * In SR-IOV or passthrough mode, timeout for compute | |
b7b2a316 | 3145 | * jobs are 60000 by default. |
71f98027 AD |
3146 | */ |
3147 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3148 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3149 | if (amdgpu_sriov_vf(adev)) |
3150 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3151 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
3152 | else if (amdgpu_passthrough(adev)) | |
b7b2a316 | 3153 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 AD |
3154 | else |
3155 | adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; | |
3156 | ||
f440ff44 | 3157 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3158 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3159 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3160 | ret = kstrtol(timeout_setting, 0, &timeout); |
3161 | if (ret) | |
3162 | return ret; | |
3163 | ||
3164 | if (timeout == 0) { | |
3165 | index++; | |
3166 | continue; | |
3167 | } else if (timeout < 0) { | |
3168 | timeout = MAX_SCHEDULE_TIMEOUT; | |
3169 | } else { | |
3170 | timeout = msecs_to_jiffies(timeout); | |
3171 | } | |
3172 | ||
3173 | switch (index++) { | |
3174 | case 0: | |
3175 | adev->gfx_timeout = timeout; | |
3176 | break; | |
3177 | case 1: | |
3178 | adev->compute_timeout = timeout; | |
3179 | break; | |
3180 | case 2: | |
3181 | adev->sdma_timeout = timeout; | |
3182 | break; | |
3183 | case 3: | |
3184 | adev->video_timeout = timeout; | |
3185 | break; | |
3186 | default: | |
3187 | break; | |
3188 | } | |
3189 | } | |
3190 | /* | |
3191 | * There is only one value specified and | |
3192 | * it should apply to all non-compute jobs. | |
3193 | */ | |
bcccee89 | 3194 | if (index == 1) { |
71f98027 | 3195 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3196 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3197 | adev->compute_timeout = adev->gfx_timeout; | |
3198 | } | |
71f98027 AD |
3199 | } |
3200 | ||
3201 | return ret; | |
3202 | } | |
d4535e2c | 3203 | |
77f3a5cd ND |
3204 | static const struct attribute *amdgpu_dev_attributes[] = { |
3205 | &dev_attr_product_name.attr, | |
3206 | &dev_attr_product_number.attr, | |
3207 | &dev_attr_serial_number.attr, | |
3208 | &dev_attr_pcie_replay_count.attr, | |
3209 | NULL | |
3210 | }; | |
3211 | ||
c9a6b82f | 3212 | |
d38ceaf9 AD |
3213 | /** |
3214 | * amdgpu_device_init - initialize the driver | |
3215 | * | |
3216 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3217 | * @flags: driver flags |
3218 | * | |
3219 | * Initializes the driver info and hw (all asics). | |
3220 | * Returns 0 for success or an error on failure. | |
3221 | * Called at driver startup. | |
3222 | */ | |
3223 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3224 | uint32_t flags) |
3225 | { | |
8aba21b7 LT |
3226 | struct drm_device *ddev = adev_to_drm(adev); |
3227 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3228 | int r, i; |
fd496ca8 | 3229 | bool atpx = false; |
95844d20 | 3230 | u32 max_MBps; |
d38ceaf9 AD |
3231 | |
3232 | adev->shutdown = false; | |
d38ceaf9 | 3233 | adev->flags = flags; |
4e66d7d2 YZ |
3234 | |
3235 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3236 | adev->asic_type = amdgpu_force_asic_type; | |
3237 | else | |
3238 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3239 | ||
d38ceaf9 | 3240 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3241 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3242 | adev->usec_timeout *= 10; |
770d13b1 | 3243 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3244 | adev->accel_working = false; |
3245 | adev->num_rings = 0; | |
3246 | adev->mman.buffer_funcs = NULL; | |
3247 | adev->mman.buffer_funcs_ring = NULL; | |
3248 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3249 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3250 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 3251 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3252 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3253 | |
3254 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3255 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3256 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3257 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3258 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3259 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3260 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3261 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3262 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3263 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3264 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3265 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3266 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3267 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3268 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3269 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3270 | ||
3e39ab90 AD |
3271 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3272 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3273 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3274 | |
3275 | /* mutex initialization are all done here so we | |
3276 | * can recall function without having locking issues */ | |
0e5ca0d1 | 3277 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3278 | mutex_init(&adev->pm.mutex); |
3279 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3280 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3281 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3282 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3283 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3284 | mutex_init(&adev->mn_lock); |
e23b74aa | 3285 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3286 | hash_init(adev->mn_hash); |
53b3f8f4 | 3287 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 3288 | init_rwsem(&adev->reset_sem); |
32eaeae0 | 3289 | mutex_init(&adev->psp.mutex); |
bd052211 | 3290 | mutex_init(&adev->notifier_lock); |
d38ceaf9 | 3291 | |
912dfc84 EQ |
3292 | r = amdgpu_device_check_arguments(adev); |
3293 | if (r) | |
3294 | return r; | |
d38ceaf9 | 3295 | |
d38ceaf9 AD |
3296 | spin_lock_init(&adev->mmio_idx_lock); |
3297 | spin_lock_init(&adev->smc_idx_lock); | |
3298 | spin_lock_init(&adev->pcie_idx_lock); | |
3299 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3300 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3301 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3302 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3303 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3304 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3305 | |
0c4e7fa5 CZ |
3306 | INIT_LIST_HEAD(&adev->shadow_list); |
3307 | mutex_init(&adev->shadow_list_lock); | |
3308 | ||
655ce9cb | 3309 | INIT_LIST_HEAD(&adev->reset_list); |
3310 | ||
beff74bc AD |
3311 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3312 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3313 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3314 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3315 | |
d4535e2c AG |
3316 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3317 | ||
d23ee13f | 3318 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3319 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3320 | |
b265bdbd EQ |
3321 | atomic_set(&adev->throttling_logging_enabled, 1); |
3322 | /* | |
3323 | * If throttling continues, logging will be performed every minute | |
3324 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3325 | * throttling interrupt comes every second. Thus, the total logging | |
3326 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3327 | * for throttling interrupt) = 60 seconds. | |
3328 | */ | |
3329 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3330 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3331 | ||
0fa49558 AX |
3332 | /* Registers mapping */ |
3333 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3334 | if (adev->asic_type >= CHIP_BONAIRE) { |
3335 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3336 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3337 | } else { | |
3338 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3339 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3340 | } | |
d38ceaf9 | 3341 | |
d38ceaf9 AD |
3342 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3343 | if (adev->rmmio == NULL) { | |
3344 | return -ENOMEM; | |
3345 | } | |
3346 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3347 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3348 | ||
b2109d8e JX |
3349 | /* enable PCIE atomic ops */ |
3350 | r = pci_enable_atomic_ops_to_root(adev->pdev, | |
3351 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3352 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3353 | if (r) { | |
3354 | adev->have_atomics_support = false; | |
3355 | DRM_INFO("PCIE atomic ops is not supported\n"); | |
3356 | } else { | |
3357 | adev->have_atomics_support = true; | |
3358 | } | |
3359 | ||
5494d864 AD |
3360 | amdgpu_device_get_pcie_info(adev); |
3361 | ||
b239c017 JX |
3362 | if (amdgpu_mcbp) |
3363 | DRM_INFO("MCBP is enabled\n"); | |
3364 | ||
5f84cc63 JX |
3365 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
3366 | adev->enable_mes = true; | |
3367 | ||
3aa0115d ML |
3368 | /* detect hw virtualization here */ |
3369 | amdgpu_detect_virtualization(adev); | |
3370 | ||
dffa11b4 ML |
3371 | r = amdgpu_device_get_job_timeout_settings(adev); |
3372 | if (r) { | |
3373 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
4192f7b5 | 3374 | goto failed_unmap; |
a190d1c7 XY |
3375 | } |
3376 | ||
d38ceaf9 | 3377 | /* early init functions */ |
06ec9070 | 3378 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 3379 | if (r) |
4192f7b5 | 3380 | goto failed_unmap; |
d38ceaf9 | 3381 | |
6585661d OZ |
3382 | /* doorbell bar mapping and doorbell index init*/ |
3383 | amdgpu_device_doorbell_init(adev); | |
3384 | ||
d38ceaf9 AD |
3385 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3386 | /* this will fail for cards that aren't VGA class devices, just | |
3387 | * ignore it */ | |
38d6be81 AD |
3388 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
3389 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); | |
d38ceaf9 | 3390 | |
fd496ca8 AD |
3391 | if (amdgpu_device_supports_atpx(ddev)) |
3392 | atpx = true; | |
3840c5bc AD |
3393 | if (amdgpu_has_atpx() && |
3394 | (amdgpu_is_atpx_hybrid() || | |
3395 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
3396 | !pci_is_thunderbolt_attached(adev->pdev)) | |
84c8b22e | 3397 | vga_switcheroo_register_client(adev->pdev, |
fd496ca8 AD |
3398 | &amdgpu_switcheroo_ops, atpx); |
3399 | if (atpx) | |
d38ceaf9 AD |
3400 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); |
3401 | ||
9475a943 SL |
3402 | if (amdgpu_emu_mode == 1) { |
3403 | /* post the asic on emulation mode */ | |
3404 | emu_soc_asic_init(adev); | |
bfca0289 | 3405 | goto fence_driver_init; |
9475a943 | 3406 | } |
bfca0289 | 3407 | |
4e99a44e ML |
3408 | /* detect if we are with an SRIOV vbios */ |
3409 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3410 | |
95e8e59e AD |
3411 | /* check if we need to reset the asic |
3412 | * E.g., driver was not cleanly unloaded previously, etc. | |
3413 | */ | |
f14899fd | 3414 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 3415 | if (adev->gmc.xgmi.num_physical_nodes) { |
3416 | dev_info(adev->dev, "Pending hive reset.\n"); | |
3417 | adev->gmc.xgmi.pending_reset = true; | |
3418 | /* Only need to init necessary block for SMU to handle the reset */ | |
3419 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3420 | if (!adev->ip_blocks[i].status.valid) | |
3421 | continue; | |
3422 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3423 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3424 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
3425 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 3426 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 3427 | adev->ip_blocks[i].version->funcs->name); |
3428 | adev->ip_blocks[i].status.hw = true; | |
3429 | } | |
3430 | } | |
3431 | } else { | |
3432 | r = amdgpu_asic_reset(adev); | |
3433 | if (r) { | |
3434 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3435 | goto failed; | |
3436 | } | |
95e8e59e AD |
3437 | } |
3438 | } | |
3439 | ||
8f66090b | 3440 | pci_enable_pcie_error_reporting(adev->pdev); |
c9a6b82f | 3441 | |
d38ceaf9 | 3442 | /* Post card if necessary */ |
39c640c0 | 3443 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3444 | if (!adev->bios) { |
bec86378 | 3445 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3446 | r = -EINVAL; |
3447 | goto failed; | |
d38ceaf9 | 3448 | } |
bec86378 | 3449 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3450 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3451 | if (r) { |
3452 | dev_err(adev->dev, "gpu post error!\n"); | |
3453 | goto failed; | |
3454 | } | |
d38ceaf9 AD |
3455 | } |
3456 | ||
88b64e95 AD |
3457 | if (adev->is_atom_fw) { |
3458 | /* Initialize clocks */ | |
3459 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3460 | if (r) { | |
3461 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3462 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3463 | goto failed; |
3464 | } | |
3465 | } else { | |
a5bde2f9 AD |
3466 | /* Initialize clocks */ |
3467 | r = amdgpu_atombios_get_clock_info(adev); | |
3468 | if (r) { | |
3469 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3470 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3471 | goto failed; |
a5bde2f9 AD |
3472 | } |
3473 | /* init i2c buses */ | |
4562236b HW |
3474 | if (!amdgpu_device_has_dc_support(adev)) |
3475 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3476 | } |
d38ceaf9 | 3477 | |
bfca0289 | 3478 | fence_driver_init: |
d38ceaf9 AD |
3479 | /* Fence driver */ |
3480 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
3481 | if (r) { |
3482 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 3483 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3484 | goto failed; |
2c1a2784 | 3485 | } |
d38ceaf9 AD |
3486 | |
3487 | /* init the mode config */ | |
4a580877 | 3488 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3489 | |
06ec9070 | 3490 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3491 | if (r) { |
8840a387 | 3492 | /* failed in exclusive mode due to timeout */ |
3493 | if (amdgpu_sriov_vf(adev) && | |
3494 | !amdgpu_sriov_runtime(adev) && | |
3495 | amdgpu_virt_mmio_blocked(adev) && | |
3496 | !amdgpu_virt_wait_reset(adev)) { | |
3497 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3498 | /* Don't send request since VF is inactive. */ |
3499 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3500 | adev->virt.ops = NULL; | |
8840a387 | 3501 | r = -EAGAIN; |
970fd197 | 3502 | goto release_ras_con; |
8840a387 | 3503 | } |
06ec9070 | 3504 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3505 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 3506 | goto release_ras_con; |
d38ceaf9 AD |
3507 | } |
3508 | ||
d69b8971 YZ |
3509 | dev_info(adev->dev, |
3510 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3511 | adev->gfx.config.max_shader_engines, |
3512 | adev->gfx.config.max_sh_per_se, | |
3513 | adev->gfx.config.max_cu_per_sh, | |
3514 | adev->gfx.cu_info.number); | |
3515 | ||
d38ceaf9 AD |
3516 | adev->accel_working = true; |
3517 | ||
e59c0205 AX |
3518 | amdgpu_vm_check_compute_bug(adev); |
3519 | ||
95844d20 MO |
3520 | /* Initialize the buffer migration limit. */ |
3521 | if (amdgpu_moverate >= 0) | |
3522 | max_MBps = amdgpu_moverate; | |
3523 | else | |
3524 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3525 | /* Get a log2 for easy divisions. */ | |
3526 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3527 | ||
9bc92b9c ML |
3528 | amdgpu_fbdev_init(adev); |
3529 | ||
d2f52ac8 | 3530 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3531 | if (r) { |
3532 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3533 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3534 | } else |
3535 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3536 | |
5bb23532 | 3537 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3538 | if (r) { |
3539 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3540 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3541 | } else |
3542 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3543 | |
d38ceaf9 AD |
3544 | if ((amdgpu_testing & 1)) { |
3545 | if (adev->accel_working) | |
3546 | amdgpu_test_moves(adev); | |
3547 | else | |
3548 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
3549 | } | |
d38ceaf9 AD |
3550 | if (amdgpu_benchmarking) { |
3551 | if (adev->accel_working) | |
3552 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
3553 | else | |
3554 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
3555 | } | |
3556 | ||
b0adca4d EQ |
3557 | /* |
3558 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3559 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3560 | * gpu instance is counted less. | |
3561 | */ | |
3562 | amdgpu_register_gpu_instance(adev); | |
3563 | ||
d38ceaf9 AD |
3564 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3565 | * explicit gating rather than handling it automatically. | |
3566 | */ | |
e3c1b071 | 3567 | if (!adev->gmc.xgmi.pending_reset) { |
3568 | r = amdgpu_device_ip_late_init(adev); | |
3569 | if (r) { | |
3570 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
3571 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 3572 | goto release_ras_con; |
e3c1b071 | 3573 | } |
3574 | /* must succeed. */ | |
3575 | amdgpu_ras_resume(adev); | |
3576 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
3577 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 3578 | } |
d38ceaf9 | 3579 | |
2c738637 ML |
3580 | if (amdgpu_sriov_vf(adev)) |
3581 | flush_delayed_work(&adev->delayed_init_work); | |
3582 | ||
77f3a5cd | 3583 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 3584 | if (r) |
77f3a5cd | 3585 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 3586 | |
d155bef0 AB |
3587 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3588 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3589 | if (r) |
3590 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3591 | ||
c1dd4aa6 AG |
3592 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
3593 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
3594 | pci_restore_state(pdev); | |
3595 | ||
e3c1b071 | 3596 | if (adev->gmc.xgmi.pending_reset) |
3597 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
3598 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3599 | ||
d38ceaf9 | 3600 | return 0; |
83ba126a | 3601 | |
970fd197 SY |
3602 | release_ras_con: |
3603 | amdgpu_release_ras_context(adev); | |
3604 | ||
83ba126a | 3605 | failed: |
89041940 | 3606 | amdgpu_vf_error_trans_all(adev); |
fd496ca8 | 3607 | if (atpx) |
83ba126a | 3608 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
8840a387 | 3609 | |
4192f7b5 AD |
3610 | failed_unmap: |
3611 | iounmap(adev->rmmio); | |
3612 | adev->rmmio = NULL; | |
3613 | ||
83ba126a | 3614 | return r; |
d38ceaf9 AD |
3615 | } |
3616 | ||
d38ceaf9 AD |
3617 | /** |
3618 | * amdgpu_device_fini - tear down the driver | |
3619 | * | |
3620 | * @adev: amdgpu_device pointer | |
3621 | * | |
3622 | * Tear down the driver info (all asics). | |
3623 | * Called at driver shutdown. | |
3624 | */ | |
3625 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
3626 | { | |
aac89168 | 3627 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3628 | flush_delayed_work(&adev->delayed_init_work); |
bb0cd09b | 3629 | ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); |
d0d13fe8 | 3630 | adev->shutdown = true; |
9f875167 | 3631 | |
c1dd4aa6 AG |
3632 | kfree(adev->pci_state); |
3633 | ||
752c683d ML |
3634 | /* make sure IB test finished before entering exclusive mode |
3635 | * to avoid preemption on IB test | |
3636 | * */ | |
519b8b76 | 3637 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 3638 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
3639 | amdgpu_virt_fini_data_exchange(adev); |
3640 | } | |
752c683d | 3641 | |
e5b03032 ML |
3642 | /* disable all interrupts */ |
3643 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
3644 | if (adev->mode_info.mode_config_initialized){ |
3645 | if (!amdgpu_device_has_dc_support(adev)) | |
4a580877 | 3646 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3647 | else |
4a580877 | 3648 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3649 | } |
d38ceaf9 | 3650 | amdgpu_fence_driver_fini(adev); |
7c868b59 YT |
3651 | if (adev->pm_sysfs_en) |
3652 | amdgpu_pm_sysfs_fini(adev); | |
d38ceaf9 | 3653 | amdgpu_fbdev_fini(adev); |
e230ac11 | 3654 | amdgpu_device_ip_fini(adev); |
75e1658e ND |
3655 | release_firmware(adev->firmware.gpu_info_fw); |
3656 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 AD |
3657 | adev->accel_working = false; |
3658 | /* free i2c buses */ | |
4562236b HW |
3659 | if (!amdgpu_device_has_dc_support(adev)) |
3660 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3661 | |
3662 | if (amdgpu_emu_mode != 1) | |
3663 | amdgpu_atombios_fini(adev); | |
3664 | ||
d38ceaf9 AD |
3665 | kfree(adev->bios); |
3666 | adev->bios = NULL; | |
3840c5bc AD |
3667 | if (amdgpu_has_atpx() && |
3668 | (amdgpu_is_atpx_hybrid() || | |
3669 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
3670 | !pci_is_thunderbolt_attached(adev->pdev)) | |
84c8b22e | 3671 | vga_switcheroo_unregister_client(adev->pdev); |
fd496ca8 | 3672 | if (amdgpu_device_supports_atpx(adev_to_drm(adev))) |
83ba126a | 3673 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
38d6be81 AD |
3674 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
3675 | vga_client_register(adev->pdev, NULL, NULL, NULL); | |
d38ceaf9 AD |
3676 | iounmap(adev->rmmio); |
3677 | adev->rmmio = NULL; | |
06ec9070 | 3678 | amdgpu_device_doorbell_fini(adev); |
e9bc1bf7 | 3679 | |
7c868b59 YT |
3680 | if (adev->ucode_sysfs_en) |
3681 | amdgpu_ucode_sysfs_fini(adev); | |
77f3a5cd ND |
3682 | |
3683 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
d155bef0 AB |
3684 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3685 | amdgpu_pmu_fini(adev); | |
72de33f8 | 3686 | if (adev->mman.discovery_bin) |
a190d1c7 | 3687 | amdgpu_discovery_fini(adev); |
d38ceaf9 AD |
3688 | } |
3689 | ||
3690 | ||
3691 | /* | |
3692 | * Suspend & resume. | |
3693 | */ | |
3694 | /** | |
810ddc3a | 3695 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3696 | * |
87e3f136 | 3697 | * @dev: drm dev pointer |
87e3f136 | 3698 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
3699 | * |
3700 | * Puts the hw in the suspend state (all asics). | |
3701 | * Returns 0 for success or an error on failure. | |
3702 | * Called at driver suspend. | |
3703 | */ | |
de185019 | 3704 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 AD |
3705 | { |
3706 | struct amdgpu_device *adev; | |
3707 | struct drm_crtc *crtc; | |
3708 | struct drm_connector *connector; | |
f8d2d39e | 3709 | struct drm_connector_list_iter iter; |
5ceb54c6 | 3710 | int r; |
d38ceaf9 | 3711 | |
1348969a | 3712 | adev = drm_to_adev(dev); |
d38ceaf9 AD |
3713 | |
3714 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3715 | return 0; | |
3716 | ||
44779b43 | 3717 | adev->in_suspend = true; |
d38ceaf9 AD |
3718 | drm_kms_helper_poll_disable(dev); |
3719 | ||
5f818173 S |
3720 | if (fbcon) |
3721 | amdgpu_fbdev_set_suspend(adev, 1); | |
3722 | ||
beff74bc | 3723 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3724 | |
4562236b HW |
3725 | if (!amdgpu_device_has_dc_support(adev)) { |
3726 | /* turn off display hw */ | |
3727 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3728 | drm_connector_list_iter_begin(dev, &iter); |
3729 | drm_for_each_connector_iter(connector, &iter) | |
3730 | drm_helper_connector_dpms(connector, | |
3731 | DRM_MODE_DPMS_OFF); | |
3732 | drm_connector_list_iter_end(&iter); | |
4562236b | 3733 | drm_modeset_unlock_all(dev); |
fe1053b7 AD |
3734 | /* unpin the front buffers and cursors */ |
3735 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3736 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3737 | struct drm_framebuffer *fb = crtc->primary->fb; | |
3738 | struct amdgpu_bo *robj; | |
3739 | ||
91334223 | 3740 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3741 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3742 | r = amdgpu_bo_reserve(aobj, true); | |
3743 | if (r == 0) { | |
3744 | amdgpu_bo_unpin(aobj); | |
3745 | amdgpu_bo_unreserve(aobj); | |
3746 | } | |
756e6880 | 3747 | } |
756e6880 | 3748 | |
fe1053b7 AD |
3749 | if (fb == NULL || fb->obj[0] == NULL) { |
3750 | continue; | |
3751 | } | |
3752 | robj = gem_to_amdgpu_bo(fb->obj[0]); | |
3753 | /* don't unpin kernel fb objects */ | |
3754 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
3755 | r = amdgpu_bo_reserve(robj, true); | |
3756 | if (r == 0) { | |
3757 | amdgpu_bo_unpin(robj); | |
3758 | amdgpu_bo_unreserve(robj); | |
3759 | } | |
d38ceaf9 AD |
3760 | } |
3761 | } | |
3762 | } | |
fe1053b7 | 3763 | |
5e6932fe | 3764 | amdgpu_ras_suspend(adev); |
3765 | ||
fe1053b7 AD |
3766 | r = amdgpu_device_ip_suspend_phase1(adev); |
3767 | ||
ad887af9 | 3768 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); |
94fa5660 | 3769 | |
d38ceaf9 AD |
3770 | /* evict vram memory */ |
3771 | amdgpu_bo_evict_vram(adev); | |
3772 | ||
5ceb54c6 | 3773 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 3774 | |
b00978de PL |
3775 | if (adev->in_poweroff_reboot_com || |
3776 | !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) | |
628c36d7 PL |
3777 | r = amdgpu_device_ip_suspend_phase2(adev); |
3778 | else | |
3779 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); | |
a0a71e49 AD |
3780 | /* evict remaining vram memory |
3781 | * This second call to evict vram is to evict the gart page table | |
3782 | * using the CPU. | |
3783 | */ | |
d38ceaf9 AD |
3784 | amdgpu_bo_evict_vram(adev); |
3785 | ||
d38ceaf9 AD |
3786 | return 0; |
3787 | } | |
3788 | ||
3789 | /** | |
810ddc3a | 3790 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 3791 | * |
87e3f136 | 3792 | * @dev: drm dev pointer |
87e3f136 | 3793 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
3794 | * |
3795 | * Bring the hw back to operating state (all asics). | |
3796 | * Returns 0 for success or an error on failure. | |
3797 | * Called at driver resume. | |
3798 | */ | |
de185019 | 3799 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 AD |
3800 | { |
3801 | struct drm_connector *connector; | |
f8d2d39e | 3802 | struct drm_connector_list_iter iter; |
1348969a | 3803 | struct amdgpu_device *adev = drm_to_adev(dev); |
756e6880 | 3804 | struct drm_crtc *crtc; |
03161a6e | 3805 | int r = 0; |
d38ceaf9 AD |
3806 | |
3807 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3808 | return 0; | |
3809 | ||
9ca5b8a1 | 3810 | if (amdgpu_acpi_is_s0ix_supported(adev)) |
628c36d7 PL |
3811 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry); |
3812 | ||
d38ceaf9 | 3813 | /* post card */ |
39c640c0 | 3814 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 3815 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 3816 | if (r) |
aac89168 | 3817 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 3818 | } |
d38ceaf9 | 3819 | |
06ec9070 | 3820 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 3821 | if (r) { |
aac89168 | 3822 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 3823 | return r; |
e6707218 | 3824 | } |
5ceb54c6 AD |
3825 | amdgpu_fence_driver_resume(adev); |
3826 | ||
d38ceaf9 | 3827 | |
06ec9070 | 3828 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 3829 | if (r) |
4d3b9ae5 | 3830 | return r; |
d38ceaf9 | 3831 | |
beff74bc AD |
3832 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3833 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3834 | ||
fe1053b7 AD |
3835 | if (!amdgpu_device_has_dc_support(adev)) { |
3836 | /* pin cursors */ | |
3837 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3838 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
3839 | ||
91334223 | 3840 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
3841 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
3842 | r = amdgpu_bo_reserve(aobj, true); | |
3843 | if (r == 0) { | |
3844 | r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); | |
3845 | if (r != 0) | |
aac89168 | 3846 | dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); |
fe1053b7 AD |
3847 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); |
3848 | amdgpu_bo_unreserve(aobj); | |
3849 | } | |
756e6880 AD |
3850 | } |
3851 | } | |
3852 | } | |
ad887af9 | 3853 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); |
ba997709 YZ |
3854 | if (r) |
3855 | return r; | |
756e6880 | 3856 | |
96a5d8d4 | 3857 | /* Make sure IB tests flushed */ |
beff74bc | 3858 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 3859 | |
d38ceaf9 AD |
3860 | /* blat the mode back in */ |
3861 | if (fbcon) { | |
4562236b HW |
3862 | if (!amdgpu_device_has_dc_support(adev)) { |
3863 | /* pre DCE11 */ | |
3864 | drm_helper_resume_force_mode(dev); | |
3865 | ||
3866 | /* turn on display hw */ | |
3867 | drm_modeset_lock_all(dev); | |
f8d2d39e LP |
3868 | |
3869 | drm_connector_list_iter_begin(dev, &iter); | |
3870 | drm_for_each_connector_iter(connector, &iter) | |
3871 | drm_helper_connector_dpms(connector, | |
3872 | DRM_MODE_DPMS_ON); | |
3873 | drm_connector_list_iter_end(&iter); | |
3874 | ||
4562236b | 3875 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 3876 | } |
4d3b9ae5 | 3877 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
3878 | } |
3879 | ||
3880 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 3881 | |
5e6932fe | 3882 | amdgpu_ras_resume(adev); |
3883 | ||
23a1a9e5 L |
3884 | /* |
3885 | * Most of the connector probing functions try to acquire runtime pm | |
3886 | * refs to ensure that the GPU is powered on when connector polling is | |
3887 | * performed. Since we're calling this from a runtime PM callback, | |
3888 | * trying to acquire rpm refs will cause us to deadlock. | |
3889 | * | |
3890 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
3891 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
3892 | */ | |
3893 | #ifdef CONFIG_PM | |
3894 | dev->dev->power.disable_depth++; | |
3895 | #endif | |
4562236b HW |
3896 | if (!amdgpu_device_has_dc_support(adev)) |
3897 | drm_helper_hpd_irq_event(dev); | |
3898 | else | |
3899 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
3900 | #ifdef CONFIG_PM |
3901 | dev->dev->power.disable_depth--; | |
3902 | #endif | |
44779b43 RZ |
3903 | adev->in_suspend = false; |
3904 | ||
4d3b9ae5 | 3905 | return 0; |
d38ceaf9 AD |
3906 | } |
3907 | ||
e3ecdffa AD |
3908 | /** |
3909 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
3910 | * | |
3911 | * @adev: amdgpu_device pointer | |
3912 | * | |
3913 | * The list of all the hardware IPs that make up the asic is walked and | |
3914 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
3915 | * if the asic is still hung or not. | |
3916 | * Returns true if any of the IPs are still in a hung state, false if not. | |
3917 | */ | |
06ec9070 | 3918 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
3919 | { |
3920 | int i; | |
3921 | bool asic_hang = false; | |
3922 | ||
f993d628 ML |
3923 | if (amdgpu_sriov_vf(adev)) |
3924 | return true; | |
3925 | ||
8bc04c29 AD |
3926 | if (amdgpu_asic_need_full_reset(adev)) |
3927 | return true; | |
3928 | ||
63fbf42f | 3929 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3930 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 3931 | continue; |
a1255107 AD |
3932 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
3933 | adev->ip_blocks[i].status.hang = | |
3934 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
3935 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 3936 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
3937 | asic_hang = true; |
3938 | } | |
3939 | } | |
3940 | return asic_hang; | |
3941 | } | |
3942 | ||
e3ecdffa AD |
3943 | /** |
3944 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
3945 | * | |
3946 | * @adev: amdgpu_device pointer | |
3947 | * | |
3948 | * The list of all the hardware IPs that make up the asic is walked and the | |
3949 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
3950 | * handles any IP specific hardware or software state changes that are | |
3951 | * necessary for a soft reset to succeed. | |
3952 | * Returns 0 on success, negative error code on failure. | |
3953 | */ | |
06ec9070 | 3954 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
3955 | { |
3956 | int i, r = 0; | |
3957 | ||
3958 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3959 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 3960 | continue; |
a1255107 AD |
3961 | if (adev->ip_blocks[i].status.hang && |
3962 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
3963 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
3964 | if (r) |
3965 | return r; | |
3966 | } | |
3967 | } | |
3968 | ||
3969 | return 0; | |
3970 | } | |
3971 | ||
e3ecdffa AD |
3972 | /** |
3973 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
3974 | * | |
3975 | * @adev: amdgpu_device pointer | |
3976 | * | |
3977 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
3978 | * reset is necessary to recover. | |
3979 | * Returns true if a full asic reset is required, false if not. | |
3980 | */ | |
06ec9070 | 3981 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 3982 | { |
da146d3b AD |
3983 | int i; |
3984 | ||
8bc04c29 AD |
3985 | if (amdgpu_asic_need_full_reset(adev)) |
3986 | return true; | |
3987 | ||
da146d3b | 3988 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3989 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 3990 | continue; |
a1255107 AD |
3991 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
3992 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
3993 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
3994 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
3995 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 3996 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 3997 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
3998 | return true; |
3999 | } | |
4000 | } | |
35d782fe CZ |
4001 | } |
4002 | return false; | |
4003 | } | |
4004 | ||
e3ecdffa AD |
4005 | /** |
4006 | * amdgpu_device_ip_soft_reset - do a soft reset | |
4007 | * | |
4008 | * @adev: amdgpu_device pointer | |
4009 | * | |
4010 | * The list of all the hardware IPs that make up the asic is walked and the | |
4011 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
4012 | * IP specific hardware or software state changes that are necessary to soft | |
4013 | * reset the IP. | |
4014 | * Returns 0 on success, negative error code on failure. | |
4015 | */ | |
06ec9070 | 4016 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4017 | { |
4018 | int i, r = 0; | |
4019 | ||
4020 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4021 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4022 | continue; |
a1255107 AD |
4023 | if (adev->ip_blocks[i].status.hang && |
4024 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
4025 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
4026 | if (r) |
4027 | return r; | |
4028 | } | |
4029 | } | |
4030 | ||
4031 | return 0; | |
4032 | } | |
4033 | ||
e3ecdffa AD |
4034 | /** |
4035 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
4036 | * | |
4037 | * @adev: amdgpu_device pointer | |
4038 | * | |
4039 | * The list of all the hardware IPs that make up the asic is walked and the | |
4040 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
4041 | * handles any IP specific hardware or software state changes that are | |
4042 | * necessary after the IP has been soft reset. | |
4043 | * Returns 0 on success, negative error code on failure. | |
4044 | */ | |
06ec9070 | 4045 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4046 | { |
4047 | int i, r = 0; | |
4048 | ||
4049 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4050 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4051 | continue; |
a1255107 AD |
4052 | if (adev->ip_blocks[i].status.hang && |
4053 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
4054 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
4055 | if (r) |
4056 | return r; | |
4057 | } | |
4058 | ||
4059 | return 0; | |
4060 | } | |
4061 | ||
e3ecdffa | 4062 | /** |
c33adbc7 | 4063 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4064 | * |
4065 | * @adev: amdgpu_device pointer | |
4066 | * | |
4067 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4068 | * restore things like GPUVM page tables after a GPU reset where | |
4069 | * the contents of VRAM might be lost. | |
403009bf CK |
4070 | * |
4071 | * Returns: | |
4072 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4073 | */ |
c33adbc7 | 4074 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4075 | { |
c41d1cf6 | 4076 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf CK |
4077 | struct amdgpu_bo *shadow; |
4078 | long r = 1, tmo; | |
c41d1cf6 ML |
4079 | |
4080 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4081 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4082 | else |
4083 | tmo = msecs_to_jiffies(100); | |
4084 | ||
aac89168 | 4085 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4086 | mutex_lock(&adev->shadow_list_lock); |
403009bf CK |
4087 | list_for_each_entry(shadow, &adev->shadow_list, shadow_list) { |
4088 | ||
4089 | /* No need to recover an evicted BO */ | |
4090 | if (shadow->tbo.mem.mem_type != TTM_PL_TT || | |
b575f10d | 4091 | shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET || |
403009bf CK |
4092 | shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM) |
4093 | continue; | |
4094 | ||
4095 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4096 | if (r) | |
4097 | break; | |
4098 | ||
c41d1cf6 | 4099 | if (fence) { |
1712fb1a | 4100 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4101 | dma_fence_put(fence); |
4102 | fence = next; | |
1712fb1a | 4103 | if (tmo == 0) { |
4104 | r = -ETIMEDOUT; | |
c41d1cf6 | 4105 | break; |
1712fb1a | 4106 | } else if (tmo < 0) { |
4107 | r = tmo; | |
4108 | break; | |
4109 | } | |
403009bf CK |
4110 | } else { |
4111 | fence = next; | |
c41d1cf6 | 4112 | } |
c41d1cf6 ML |
4113 | } |
4114 | mutex_unlock(&adev->shadow_list_lock); | |
4115 | ||
403009bf CK |
4116 | if (fence) |
4117 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4118 | dma_fence_put(fence); |
4119 | ||
1712fb1a | 4120 | if (r < 0 || tmo <= 0) { |
aac89168 | 4121 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4122 | return -EIO; |
4123 | } | |
c41d1cf6 | 4124 | |
aac89168 | 4125 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4126 | return 0; |
c41d1cf6 ML |
4127 | } |
4128 | ||
a90ad3c2 | 4129 | |
e3ecdffa | 4130 | /** |
06ec9070 | 4131 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4132 | * |
982a820b | 4133 | * @adev: amdgpu_device pointer |
87e3f136 | 4134 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4135 | * |
4136 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4137 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4138 | */ |
4139 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4140 | bool from_hypervisor) | |
5740682e ML |
4141 | { |
4142 | int r; | |
4143 | ||
4144 | if (from_hypervisor) | |
4145 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4146 | else | |
4147 | r = amdgpu_virt_reset_gpu(adev); | |
4148 | if (r) | |
4149 | return r; | |
a90ad3c2 | 4150 | |
b639c22c JZ |
4151 | amdgpu_amdkfd_pre_reset(adev); |
4152 | ||
a90ad3c2 | 4153 | /* Resume IP prior to SMC */ |
06ec9070 | 4154 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4155 | if (r) |
4156 | goto error; | |
a90ad3c2 | 4157 | |
c9ffa427 | 4158 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4159 | /* we need recover gart prior to run SMC/CP/SDMA resume */ |
6c28aed6 | 4160 | amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); |
a90ad3c2 | 4161 | |
7a3e0bb2 RZ |
4162 | r = amdgpu_device_fw_loading(adev); |
4163 | if (r) | |
4164 | return r; | |
4165 | ||
a90ad3c2 | 4166 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4167 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4168 | if (r) |
4169 | goto error; | |
a90ad3c2 ML |
4170 | |
4171 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 4172 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 4173 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 4174 | |
abc34253 ED |
4175 | error: |
4176 | amdgpu_virt_release_full_gpu(adev, true); | |
c41d1cf6 | 4177 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 4178 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 4179 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 ML |
4180 | } |
4181 | ||
4182 | return r; | |
4183 | } | |
4184 | ||
9a1cddd6 | 4185 | /** |
4186 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
4187 | * | |
982a820b | 4188 | * @adev: amdgpu_device pointer |
9a1cddd6 | 4189 | * |
4190 | * check if there is any job in mirror list | |
4191 | */ | |
4192 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
4193 | { | |
4194 | int i; | |
4195 | struct drm_sched_job *job; | |
4196 | ||
4197 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4198 | struct amdgpu_ring *ring = adev->rings[i]; | |
4199 | ||
4200 | if (!ring || !ring->sched.thread) | |
4201 | continue; | |
4202 | ||
4203 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
4204 | job = list_first_entry_or_null(&ring->sched.pending_list, |
4205 | struct drm_sched_job, list); | |
9a1cddd6 | 4206 | spin_unlock(&ring->sched.job_list_lock); |
4207 | if (job) | |
4208 | return true; | |
4209 | } | |
4210 | return false; | |
4211 | } | |
4212 | ||
12938fad CK |
4213 | /** |
4214 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
4215 | * | |
982a820b | 4216 | * @adev: amdgpu_device pointer |
12938fad CK |
4217 | * |
4218 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
4219 | * a hung GPU. | |
4220 | */ | |
4221 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
4222 | { | |
4223 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4224 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
4225 | return false; |
4226 | } | |
4227 | ||
3ba7b418 AG |
4228 | if (amdgpu_gpu_recovery == 0) |
4229 | goto disabled; | |
4230 | ||
4231 | if (amdgpu_sriov_vf(adev)) | |
4232 | return true; | |
4233 | ||
4234 | if (amdgpu_gpu_recovery == -1) { | |
4235 | switch (adev->asic_type) { | |
fc42d47c AG |
4236 | case CHIP_BONAIRE: |
4237 | case CHIP_HAWAII: | |
3ba7b418 AG |
4238 | case CHIP_TOPAZ: |
4239 | case CHIP_TONGA: | |
4240 | case CHIP_FIJI: | |
4241 | case CHIP_POLARIS10: | |
4242 | case CHIP_POLARIS11: | |
4243 | case CHIP_POLARIS12: | |
4244 | case CHIP_VEGAM: | |
4245 | case CHIP_VEGA20: | |
4246 | case CHIP_VEGA10: | |
4247 | case CHIP_VEGA12: | |
c43b849f | 4248 | case CHIP_RAVEN: |
e9d4cf91 | 4249 | case CHIP_ARCTURUS: |
2cb44fb0 | 4250 | case CHIP_RENOIR: |
658c6639 AD |
4251 | case CHIP_NAVI10: |
4252 | case CHIP_NAVI14: | |
4253 | case CHIP_NAVI12: | |
131a3c74 | 4254 | case CHIP_SIENNA_CICHLID: |
665fe4dc | 4255 | case CHIP_NAVY_FLOUNDER: |
27859ee3 | 4256 | case CHIP_DIMGREY_CAVEFISH: |
fe68ceef | 4257 | case CHIP_VANGOGH: |
3ba7b418 AG |
4258 | break; |
4259 | default: | |
4260 | goto disabled; | |
4261 | } | |
12938fad CK |
4262 | } |
4263 | ||
4264 | return true; | |
3ba7b418 AG |
4265 | |
4266 | disabled: | |
aac89168 | 4267 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4268 | return false; |
12938fad CK |
4269 | } |
4270 | ||
5c03e584 FX |
4271 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
4272 | { | |
4273 | u32 i; | |
4274 | int ret = 0; | |
4275 | ||
4276 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
4277 | ||
4278 | dev_info(adev->dev, "GPU mode1 reset\n"); | |
4279 | ||
4280 | /* disable BM */ | |
4281 | pci_clear_master(adev->pdev); | |
4282 | ||
4283 | amdgpu_device_cache_pci_state(adev->pdev); | |
4284 | ||
4285 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
4286 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
4287 | ret = amdgpu_dpm_mode1_reset(adev); | |
4288 | } else { | |
4289 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
4290 | ret = psp_gpu_reset(adev); | |
4291 | } | |
4292 | ||
4293 | if (ret) | |
4294 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
4295 | ||
4296 | amdgpu_device_load_pci_state(adev->pdev); | |
4297 | ||
4298 | /* wait for asic to come out of reset */ | |
4299 | for (i = 0; i < adev->usec_timeout; i++) { | |
4300 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
4301 | ||
4302 | if (memsize != 0xffffffff) | |
4303 | break; | |
4304 | udelay(1); | |
4305 | } | |
4306 | ||
4307 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
4308 | return ret; | |
4309 | } | |
5c6dd71e | 4310 | |
e3c1b071 | 4311 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
4312 | struct amdgpu_job *job, | |
4313 | bool *need_full_reset_arg) | |
26bc5340 AG |
4314 | { |
4315 | int i, r = 0; | |
4316 | bool need_full_reset = *need_full_reset_arg; | |
71182665 | 4317 | |
e3c1b071 | 4318 | /* no need to dump if device is not in good state during probe period */ |
4319 | if (!adev->gmc.xgmi.pending_reset) | |
4320 | amdgpu_debugfs_wait_dump(adev); | |
728e7e0c | 4321 | |
b602ca5f TZ |
4322 | if (amdgpu_sriov_vf(adev)) { |
4323 | /* stop the data exchange thread */ | |
4324 | amdgpu_virt_fini_data_exchange(adev); | |
4325 | } | |
4326 | ||
71182665 | 4327 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4328 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4329 | struct amdgpu_ring *ring = adev->rings[i]; | |
4330 | ||
51687759 | 4331 | if (!ring || !ring->sched.thread) |
0875dc9e | 4332 | continue; |
5740682e | 4333 | |
2f9d4084 ML |
4334 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4335 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4336 | } |
d38ceaf9 | 4337 | |
222b5f04 AG |
4338 | if(job) |
4339 | drm_sched_increase_karma(&job->base); | |
4340 | ||
1d721ed6 | 4341 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4342 | if (!amdgpu_sriov_vf(adev)) { |
4343 | ||
4344 | if (!need_full_reset) | |
4345 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4346 | ||
4347 | if (!need_full_reset) { | |
4348 | amdgpu_device_ip_pre_soft_reset(adev); | |
4349 | r = amdgpu_device_ip_soft_reset(adev); | |
4350 | amdgpu_device_ip_post_soft_reset(adev); | |
4351 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4352 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4353 | need_full_reset = true; |
4354 | } | |
4355 | } | |
4356 | ||
4357 | if (need_full_reset) | |
4358 | r = amdgpu_device_ip_suspend(adev); | |
4359 | ||
4360 | *need_full_reset_arg = need_full_reset; | |
4361 | } | |
4362 | ||
4363 | return r; | |
4364 | } | |
4365 | ||
e3c1b071 | 4366 | int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, |
4367 | struct list_head *device_list_handle, | |
4368 | bool *need_full_reset_arg, | |
4369 | bool skip_hw_reset) | |
26bc5340 AG |
4370 | { |
4371 | struct amdgpu_device *tmp_adev = NULL; | |
4372 | bool need_full_reset = *need_full_reset_arg, vram_lost = false; | |
4373 | int r = 0; | |
4374 | ||
4375 | /* | |
655ce9cb | 4376 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
4377 | * to allow proper links negotiation in FW (within 1 sec) |
4378 | */ | |
7ac71382 | 4379 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 4380 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 4381 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4382 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 4383 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 4384 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4385 | r = -EALREADY; |
4386 | } else | |
4387 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4388 | |
041a62bc | 4389 | if (r) { |
aac89168 | 4390 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4391 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4392 | break; |
ce316fa5 LM |
4393 | } |
4394 | } | |
4395 | ||
041a62bc AG |
4396 | /* For XGMI wait for all resets to complete before proceed */ |
4397 | if (!r) { | |
655ce9cb | 4398 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
4399 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
4400 | flush_work(&tmp_adev->xgmi_reset_work); | |
4401 | r = tmp_adev->asic_reset_res; | |
4402 | if (r) | |
4403 | break; | |
ce316fa5 LM |
4404 | } |
4405 | } | |
4406 | } | |
ce316fa5 | 4407 | } |
26bc5340 | 4408 | |
43c4d576 | 4409 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 4410 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
43c4d576 JC |
4411 | if (tmp_adev->mmhub.funcs && |
4412 | tmp_adev->mmhub.funcs->reset_ras_error_count) | |
4413 | tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev); | |
4414 | } | |
4415 | ||
00eaa571 | 4416 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4417 | } |
00eaa571 | 4418 | |
655ce9cb | 4419 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
4420 | if (need_full_reset) { |
4421 | /* post card */ | |
e3c1b071 | 4422 | r = amdgpu_device_asic_init(tmp_adev); |
4423 | if (r) { | |
aac89168 | 4424 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 4425 | } else { |
26bc5340 AG |
4426 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
4427 | r = amdgpu_device_ip_resume_phase1(tmp_adev); | |
4428 | if (r) | |
4429 | goto out; | |
4430 | ||
4431 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
4432 | if (vram_lost) { | |
77e7f829 | 4433 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4434 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4435 | } |
4436 | ||
6c28aed6 | 4437 | r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT)); |
26bc5340 AG |
4438 | if (r) |
4439 | goto out; | |
4440 | ||
4441 | r = amdgpu_device_fw_loading(tmp_adev); | |
4442 | if (r) | |
4443 | return r; | |
4444 | ||
4445 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4446 | if (r) | |
4447 | goto out; | |
4448 | ||
4449 | if (vram_lost) | |
4450 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4451 | ||
fdafb359 EQ |
4452 | /* |
4453 | * Add this ASIC as tracked as reset was already | |
4454 | * complete successfully. | |
4455 | */ | |
4456 | amdgpu_register_gpu_instance(tmp_adev); | |
4457 | ||
e3c1b071 | 4458 | if (!hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1) |
4459 | amdgpu_xgmi_add_device(tmp_adev); | |
4460 | ||
7c04ca50 | 4461 | r = amdgpu_device_ip_late_init(tmp_adev); |
4462 | if (r) | |
4463 | goto out; | |
4464 | ||
565d1941 EQ |
4465 | amdgpu_fbdev_set_suspend(tmp_adev, 0); |
4466 | ||
e8fbaf03 GC |
4467 | /* |
4468 | * The GPU enters bad state once faulty pages | |
4469 | * by ECC has reached the threshold, and ras | |
4470 | * recovery is scheduled next. So add one check | |
4471 | * here to break recovery if it indeed exceeds | |
4472 | * bad page threshold, and remind user to | |
4473 | * retire this GPU or setting one bigger | |
4474 | * bad_page_threshold value to fix this once | |
4475 | * probing driver again. | |
4476 | */ | |
11003c68 | 4477 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
4478 | /* must succeed. */ |
4479 | amdgpu_ras_resume(tmp_adev); | |
4480 | } else { | |
4481 | r = -EINVAL; | |
4482 | goto out; | |
4483 | } | |
e79a04d5 | 4484 | |
26bc5340 AG |
4485 | /* Update PSP FW topology after reset */ |
4486 | if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4487 | r = amdgpu_xgmi_update_topology(hive, tmp_adev); | |
4488 | } | |
4489 | } | |
4490 | ||
26bc5340 AG |
4491 | out: |
4492 | if (!r) { | |
4493 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4494 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4495 | if (r) { | |
4496 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
4497 | r = amdgpu_device_ip_suspend(tmp_adev); | |
4498 | need_full_reset = true; | |
4499 | r = -EAGAIN; | |
4500 | goto end; | |
4501 | } | |
4502 | } | |
4503 | ||
4504 | if (!r) | |
4505 | r = amdgpu_device_recover_vram(tmp_adev); | |
4506 | else | |
4507 | tmp_adev->asic_reset_res = r; | |
4508 | } | |
4509 | ||
4510 | end: | |
4511 | *need_full_reset_arg = need_full_reset; | |
4512 | return r; | |
4513 | } | |
4514 | ||
08ebb485 DL |
4515 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, |
4516 | struct amdgpu_hive_info *hive) | |
26bc5340 | 4517 | { |
53b3f8f4 DL |
4518 | if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0) |
4519 | return false; | |
4520 | ||
08ebb485 DL |
4521 | if (hive) { |
4522 | down_write_nest_lock(&adev->reset_sem, &hive->hive_lock); | |
4523 | } else { | |
4524 | down_write(&adev->reset_sem); | |
4525 | } | |
5740682e | 4526 | |
a3a09142 AD |
4527 | switch (amdgpu_asic_reset_method(adev)) { |
4528 | case AMD_RESET_METHOD_MODE1: | |
4529 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4530 | break; | |
4531 | case AMD_RESET_METHOD_MODE2: | |
4532 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4533 | break; | |
4534 | default: | |
4535 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4536 | break; | |
4537 | } | |
1d721ed6 AG |
4538 | |
4539 | return true; | |
26bc5340 | 4540 | } |
d38ceaf9 | 4541 | |
26bc5340 AG |
4542 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
4543 | { | |
89041940 | 4544 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4545 | adev->mp1_state = PP_MP1_STATE_NONE; |
53b3f8f4 | 4546 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 4547 | up_write(&adev->reset_sem); |
26bc5340 AG |
4548 | } |
4549 | ||
91fb309d HC |
4550 | /* |
4551 | * to lockup a list of amdgpu devices in a hive safely, if not a hive | |
4552 | * with multiple nodes, it will be similar as amdgpu_device_lock_adev. | |
4553 | * | |
4554 | * unlock won't require roll back. | |
4555 | */ | |
4556 | static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive) | |
4557 | { | |
4558 | struct amdgpu_device *tmp_adev = NULL; | |
4559 | ||
4560 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
4561 | if (!hive) { | |
4562 | dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes"); | |
4563 | return -ENODEV; | |
4564 | } | |
4565 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4566 | if (!amdgpu_device_lock_adev(tmp_adev, hive)) | |
4567 | goto roll_back; | |
4568 | } | |
4569 | } else if (!amdgpu_device_lock_adev(adev, hive)) | |
4570 | return -EAGAIN; | |
4571 | ||
4572 | return 0; | |
4573 | roll_back: | |
4574 | if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) { | |
4575 | /* | |
4576 | * if the lockup iteration break in the middle of a hive, | |
4577 | * it may means there may has a race issue, | |
4578 | * or a hive device locked up independently. | |
4579 | * we may be in trouble and may not, so will try to roll back | |
4580 | * the lock and give out a warnning. | |
4581 | */ | |
4582 | dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock"); | |
4583 | list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4584 | amdgpu_device_unlock_adev(tmp_adev); | |
4585 | } | |
4586 | } | |
4587 | return -EAGAIN; | |
4588 | } | |
4589 | ||
3f12acc8 EQ |
4590 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4591 | { | |
4592 | struct pci_dev *p = NULL; | |
4593 | ||
4594 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4595 | adev->pdev->bus->number, 1); | |
4596 | if (p) { | |
4597 | pm_runtime_enable(&(p->dev)); | |
4598 | pm_runtime_resume(&(p->dev)); | |
4599 | } | |
4600 | } | |
4601 | ||
4602 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4603 | { | |
4604 | enum amd_reset_method reset_method; | |
4605 | struct pci_dev *p = NULL; | |
4606 | u64 expires; | |
4607 | ||
4608 | /* | |
4609 | * For now, only BACO and mode1 reset are confirmed | |
4610 | * to suffer the audio issue without proper suspended. | |
4611 | */ | |
4612 | reset_method = amdgpu_asic_reset_method(adev); | |
4613 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4614 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4615 | return -EINVAL; | |
4616 | ||
4617 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4618 | adev->pdev->bus->number, 1); | |
4619 | if (!p) | |
4620 | return -ENODEV; | |
4621 | ||
4622 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4623 | if (!expires) | |
4624 | /* | |
4625 | * If we cannot get the audio device autosuspend delay, | |
4626 | * a fixed 4S interval will be used. Considering 3S is | |
4627 | * the audio controller default autosuspend delay setting. | |
4628 | * 4S used here is guaranteed to cover that. | |
4629 | */ | |
54b7feb9 | 4630 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4631 | |
4632 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4633 | if (!pm_runtime_suspend(&(p->dev))) | |
4634 | break; | |
4635 | ||
4636 | if (expires < ktime_get_mono_fast_ns()) { | |
4637 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4638 | /* TODO: abort the succeeding gpu reset? */ | |
4639 | return -ETIMEDOUT; | |
4640 | } | |
4641 | } | |
4642 | ||
4643 | pm_runtime_disable(&(p->dev)); | |
4644 | ||
4645 | return 0; | |
4646 | } | |
4647 | ||
26bc5340 AG |
4648 | /** |
4649 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
4650 | * | |
982a820b | 4651 | * @adev: amdgpu_device pointer |
26bc5340 AG |
4652 | * @job: which job trigger hang |
4653 | * | |
4654 | * Attempt to reset the GPU if it has hung (all asics). | |
4655 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
4656 | * Returns 0 for success or an error on failure. | |
4657 | */ | |
4658 | ||
4659 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
4660 | struct amdgpu_job *job) | |
4661 | { | |
1d721ed6 | 4662 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 EQ |
4663 | bool need_full_reset = false; |
4664 | bool job_signaled = false; | |
26bc5340 | 4665 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 4666 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 4667 | int i, r = 0; |
bb5c7235 | 4668 | bool need_emergency_restart = false; |
3f12acc8 | 4669 | bool audio_suspended = false; |
26bc5340 | 4670 | |
6e3cd2a9 | 4671 | /* |
bb5c7235 WS |
4672 | * Special case: RAS triggered and full reset isn't supported |
4673 | */ | |
4674 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
4675 | ||
d5ea093e AG |
4676 | /* |
4677 | * Flush RAM to disk so that after reboot | |
4678 | * the user can read log and see why the system rebooted. | |
4679 | */ | |
bb5c7235 | 4680 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
4681 | DRM_WARN("Emergency reboot."); |
4682 | ||
4683 | ksys_sync_helper(); | |
4684 | emergency_restart(); | |
4685 | } | |
4686 | ||
b823821f | 4687 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 4688 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 AG |
4689 | |
4690 | /* | |
1d721ed6 AG |
4691 | * Here we trylock to avoid chain of resets executing from |
4692 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
4693 | * different schedulers for same device while this TO handler is running. | |
4694 | * We always reset all schedulers for device and all devices for XGMI | |
4695 | * hive so that should take care of them too. | |
26bc5340 | 4696 | */ |
d95e8e97 | 4697 | hive = amdgpu_get_xgmi_hive(adev); |
53b3f8f4 DL |
4698 | if (hive) { |
4699 | if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) { | |
4700 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
4701 | job ? job->base.id : -1, hive->hive_id); | |
d95e8e97 | 4702 | amdgpu_put_xgmi_hive(hive); |
91fb309d HC |
4703 | if (job) |
4704 | drm_sched_increase_karma(&job->base); | |
53b3f8f4 DL |
4705 | return 0; |
4706 | } | |
4707 | mutex_lock(&hive->hive_lock); | |
1d721ed6 | 4708 | } |
26bc5340 | 4709 | |
91fb309d HC |
4710 | /* |
4711 | * lock the device before we try to operate the linked list | |
4712 | * if didn't get the device lock, don't touch the linked list since | |
4713 | * others may iterating it. | |
4714 | */ | |
4715 | r = amdgpu_device_lock_hive_adev(adev, hive); | |
4716 | if (r) { | |
4717 | dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress", | |
4718 | job ? job->base.id : -1); | |
4719 | ||
4720 | /* even we skipped this reset, still need to set the job to guilty */ | |
4721 | if (job) | |
4722 | drm_sched_increase_karma(&job->base); | |
4723 | goto skip_recovery; | |
4724 | } | |
4725 | ||
9e94d22c EQ |
4726 | /* |
4727 | * Build list of devices to reset. | |
4728 | * In case we are in XGMI hive mode, resort the device list | |
4729 | * to put adev in the 1st position. | |
4730 | */ | |
4731 | INIT_LIST_HEAD(&device_list); | |
4732 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
655ce9cb | 4733 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) |
4734 | list_add_tail(&tmp_adev->reset_list, &device_list); | |
4735 | if (!list_is_first(&adev->reset_list, &device_list)) | |
4736 | list_rotate_to_front(&adev->reset_list, &device_list); | |
4737 | device_list_handle = &device_list; | |
26bc5340 | 4738 | } else { |
655ce9cb | 4739 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
4740 | device_list_handle = &device_list; |
4741 | } | |
4742 | ||
1d721ed6 | 4743 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 4744 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
3f12acc8 EQ |
4745 | /* |
4746 | * Try to put the audio codec into suspend state | |
4747 | * before gpu reset started. | |
4748 | * | |
4749 | * Due to the power domain of the graphics device | |
4750 | * is shared with AZ power domain. Without this, | |
4751 | * we may change the audio hardware from behind | |
4752 | * the audio driver's back. That will trigger | |
4753 | * some audio codec errors. | |
4754 | */ | |
4755 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
4756 | audio_suspended = true; | |
4757 | ||
9e94d22c EQ |
4758 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
4759 | ||
52fb44cf EQ |
4760 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
4761 | ||
9e94d22c EQ |
4762 | if (!amdgpu_sriov_vf(tmp_adev)) |
4763 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
4764 | ||
12ffa55d AG |
4765 | /* |
4766 | * Mark these ASICs to be reseted as untracked first | |
4767 | * And add them back after reset completed | |
4768 | */ | |
4769 | amdgpu_unregister_gpu_instance(tmp_adev); | |
4770 | ||
a2f63ee8 | 4771 | amdgpu_fbdev_set_suspend(tmp_adev, 1); |
565d1941 | 4772 | |
f1c1314b | 4773 | /* disable ras on ALL IPs */ |
bb5c7235 | 4774 | if (!need_emergency_restart && |
b823821f | 4775 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 4776 | amdgpu_ras_suspend(tmp_adev); |
4777 | ||
1d721ed6 AG |
4778 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4779 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4780 | ||
4781 | if (!ring || !ring->sched.thread) | |
4782 | continue; | |
4783 | ||
0b2d2c2e | 4784 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 4785 | |
bb5c7235 | 4786 | if (need_emergency_restart) |
7c6e68c7 | 4787 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 4788 | } |
8f8c80f4 | 4789 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
4790 | } |
4791 | ||
bb5c7235 | 4792 | if (need_emergency_restart) |
7c6e68c7 AG |
4793 | goto skip_sched_resume; |
4794 | ||
1d721ed6 AG |
4795 | /* |
4796 | * Must check guilty signal here since after this point all old | |
4797 | * HW fences are force signaled. | |
4798 | * | |
4799 | * job->base holds a reference to parent fence | |
4800 | */ | |
4801 | if (job && job->base.s_fence->parent && | |
7dd8c205 | 4802 | dma_fence_is_signaled(job->base.s_fence->parent)) { |
1d721ed6 | 4803 | job_signaled = true; |
1d721ed6 AG |
4804 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
4805 | goto skip_hw_reset; | |
4806 | } | |
4807 | ||
26bc5340 | 4808 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 4809 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 | 4810 | r = amdgpu_device_pre_asic_reset(tmp_adev, |
ded08454 | 4811 | (tmp_adev == adev) ? job : NULL, |
26bc5340 AG |
4812 | &need_full_reset); |
4813 | /*TODO Should we stop ?*/ | |
4814 | if (r) { | |
aac89168 | 4815 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 4816 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
4817 | tmp_adev->asic_reset_res = r; |
4818 | } | |
4819 | } | |
4820 | ||
4821 | /* Actual ASIC resets if needed.*/ | |
4822 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
4823 | if (amdgpu_sriov_vf(adev)) { | |
4824 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
4825 | if (r) | |
4826 | adev->asic_reset_res = r; | |
4827 | } else { | |
7ac71382 | 4828 | r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset, false); |
26bc5340 AG |
4829 | if (r && r == -EAGAIN) |
4830 | goto retry; | |
4831 | } | |
4832 | ||
1d721ed6 AG |
4833 | skip_hw_reset: |
4834 | ||
26bc5340 | 4835 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 4836 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 4837 | |
1d721ed6 AG |
4838 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4839 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4840 | ||
4841 | if (!ring || !ring->sched.thread) | |
4842 | continue; | |
4843 | ||
4844 | /* No point to resubmit jobs if we didn't HW reset*/ | |
4845 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
4846 | drm_sched_resubmit_jobs(&ring->sched); | |
4847 | ||
4848 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
4849 | } | |
4850 | ||
4851 | if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) { | |
4a580877 | 4852 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
4853 | } |
4854 | ||
4855 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
4856 | |
4857 | if (r) { | |
4858 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 4859 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
4860 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
4861 | } else { | |
12ffa55d | 4862 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 | 4863 | } |
7c6e68c7 | 4864 | } |
26bc5340 | 4865 | |
7c6e68c7 | 4866 | skip_sched_resume: |
655ce9cb | 4867 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8e2712e7 | 4868 | /* unlock kfd: SRIOV would do it separately */ |
bb5c7235 | 4869 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
7c6e68c7 | 4870 | amdgpu_amdkfd_post_reset(tmp_adev); |
8e2712e7 | 4871 | |
4872 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
4873 | * need to bring up kfd here if it's not be initialized before | |
4874 | */ | |
4875 | if (!adev->kfd.init_complete) | |
4876 | amdgpu_amdkfd_device_init(adev); | |
4877 | ||
3f12acc8 EQ |
4878 | if (audio_suspended) |
4879 | amdgpu_device_resume_display_audio(tmp_adev); | |
26bc5340 AG |
4880 | amdgpu_device_unlock_adev(tmp_adev); |
4881 | } | |
4882 | ||
cbfd17f7 | 4883 | skip_recovery: |
9e94d22c | 4884 | if (hive) { |
53b3f8f4 | 4885 | atomic_set(&hive->in_reset, 0); |
9e94d22c | 4886 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 4887 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 4888 | } |
26bc5340 | 4889 | |
91fb309d | 4890 | if (r && r != -EAGAIN) |
26bc5340 | 4891 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
d38ceaf9 AD |
4892 | return r; |
4893 | } | |
4894 | ||
e3ecdffa AD |
4895 | /** |
4896 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
4897 | * | |
4898 | * @adev: amdgpu_device pointer | |
4899 | * | |
4900 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
4901 | * and lanes) of the slot the device is in. Handles APUs and | |
4902 | * virtualized environments where PCIE config space may not be available. | |
4903 | */ | |
5494d864 | 4904 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 4905 | { |
5d9a6330 | 4906 | struct pci_dev *pdev; |
c5313457 HK |
4907 | enum pci_bus_speed speed_cap, platform_speed_cap; |
4908 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 4909 | |
cd474ba0 AD |
4910 | if (amdgpu_pcie_gen_cap) |
4911 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 4912 | |
cd474ba0 AD |
4913 | if (amdgpu_pcie_lane_cap) |
4914 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 4915 | |
cd474ba0 AD |
4916 | /* covers APUs as well */ |
4917 | if (pci_is_root_bus(adev->pdev->bus)) { | |
4918 | if (adev->pm.pcie_gen_mask == 0) | |
4919 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
4920 | if (adev->pm.pcie_mlw_mask == 0) | |
4921 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 4922 | return; |
cd474ba0 | 4923 | } |
d0dd7f0c | 4924 | |
c5313457 HK |
4925 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
4926 | return; | |
4927 | ||
dbaa922b AD |
4928 | pcie_bandwidth_available(adev->pdev, NULL, |
4929 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 4930 | |
cd474ba0 | 4931 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
4932 | /* asic caps */ |
4933 | pdev = adev->pdev; | |
4934 | speed_cap = pcie_get_speed_cap(pdev); | |
4935 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
4936 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
4937 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
4938 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 4939 | } else { |
2b3a1f51 FX |
4940 | if (speed_cap == PCIE_SPEED_32_0GT) |
4941 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4942 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4943 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4944 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
4945 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
4946 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
4947 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4948 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4949 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4950 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
4951 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
4952 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4953 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4954 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
4955 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
4956 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4957 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4958 | else | |
4959 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4960 | } | |
4961 | /* platform caps */ | |
c5313457 | 4962 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
4963 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4964 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4965 | } else { | |
2b3a1f51 FX |
4966 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
4967 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
4968 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4969 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4970 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
4971 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
4972 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
4973 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4974 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4975 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
4976 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 4977 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
4978 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4979 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
4980 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 4981 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
4982 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
4983 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
4984 | else | |
4985 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
4986 | ||
cd474ba0 AD |
4987 | } |
4988 | } | |
4989 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 4990 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
4991 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
4992 | } else { | |
c5313457 | 4993 | switch (platform_link_width) { |
5d9a6330 | 4994 | case PCIE_LNK_X32: |
cd474ba0 AD |
4995 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
4996 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
4997 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
4998 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
4999 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5000 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5001 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5002 | break; | |
5d9a6330 | 5003 | case PCIE_LNK_X16: |
cd474ba0 AD |
5004 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5005 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5006 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5007 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5008 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5009 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5010 | break; | |
5d9a6330 | 5011 | case PCIE_LNK_X12: |
cd474ba0 AD |
5012 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5013 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5014 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5015 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5016 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5017 | break; | |
5d9a6330 | 5018 | case PCIE_LNK_X8: |
cd474ba0 AD |
5019 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5020 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5021 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5022 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5023 | break; | |
5d9a6330 | 5024 | case PCIE_LNK_X4: |
cd474ba0 AD |
5025 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5026 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5027 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5028 | break; | |
5d9a6330 | 5029 | case PCIE_LNK_X2: |
cd474ba0 AD |
5030 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5031 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5032 | break; | |
5d9a6330 | 5033 | case PCIE_LNK_X1: |
cd474ba0 AD |
5034 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5035 | break; | |
5036 | default: | |
5037 | break; | |
5038 | } | |
d0dd7f0c AD |
5039 | } |
5040 | } | |
5041 | } | |
d38ceaf9 | 5042 | |
361dbd01 AD |
5043 | int amdgpu_device_baco_enter(struct drm_device *dev) |
5044 | { | |
1348969a | 5045 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5046 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 5047 | |
4a580877 | 5048 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5049 | return -ENOTSUPP; |
5050 | ||
6fb33209 | 5051 | if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5052 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
5053 | ||
9530273e | 5054 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
5055 | } |
5056 | ||
5057 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
5058 | { | |
1348969a | 5059 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5060 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 5061 | int ret = 0; |
361dbd01 | 5062 | |
4a580877 | 5063 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5064 | return -ENOTSUPP; |
5065 | ||
9530273e EQ |
5066 | ret = amdgpu_dpm_baco_exit(adev); |
5067 | if (ret) | |
5068 | return ret; | |
7a22677b | 5069 | |
6fb33209 | 5070 | if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5071 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
5072 | ||
5073 | return 0; | |
361dbd01 | 5074 | } |
c9a6b82f | 5075 | |
acd89fca AG |
5076 | static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev) |
5077 | { | |
5078 | int i; | |
5079 | ||
5080 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5081 | struct amdgpu_ring *ring = adev->rings[i]; | |
5082 | ||
5083 | if (!ring || !ring->sched.thread) | |
5084 | continue; | |
5085 | ||
5086 | cancel_delayed_work_sync(&ring->sched.work_tdr); | |
5087 | } | |
5088 | } | |
5089 | ||
c9a6b82f AG |
5090 | /** |
5091 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
5092 | * @pdev: PCI device struct | |
5093 | * @state: PCI channel state | |
5094 | * | |
5095 | * Description: Called when a PCI error is detected. | |
5096 | * | |
5097 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
5098 | */ | |
5099 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5100 | { | |
5101 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5102 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5103 | int i; |
c9a6b82f AG |
5104 | |
5105 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
5106 | ||
6894305c AG |
5107 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
5108 | DRM_WARN("No support for XGMI hive yet..."); | |
5109 | return PCI_ERS_RESULT_DISCONNECT; | |
5110 | } | |
5111 | ||
c9a6b82f AG |
5112 | switch (state) { |
5113 | case pci_channel_io_normal: | |
5114 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 5115 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
5116 | case pci_channel_io_frozen: |
5117 | /* | |
acd89fca AG |
5118 | * Cancel and wait for all TDRs in progress if failing to |
5119 | * set adev->in_gpu_reset in amdgpu_device_lock_adev | |
5120 | * | |
5121 | * Locking adev->reset_sem will prevent any external access | |
5122 | * to GPU during PCI error recovery | |
5123 | */ | |
5124 | while (!amdgpu_device_lock_adev(adev, NULL)) | |
5125 | amdgpu_cancel_all_tdr(adev); | |
5126 | ||
5127 | /* | |
5128 | * Block any work scheduling as we do for regular GPU reset | |
5129 | * for the duration of the recovery | |
5130 | */ | |
5131 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5132 | struct amdgpu_ring *ring = adev->rings[i]; | |
5133 | ||
5134 | if (!ring || !ring->sched.thread) | |
5135 | continue; | |
5136 | ||
5137 | drm_sched_stop(&ring->sched, NULL); | |
5138 | } | |
8f8c80f4 | 5139 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
5140 | return PCI_ERS_RESULT_NEED_RESET; |
5141 | case pci_channel_io_perm_failure: | |
5142 | /* Permanent error, prepare for device removal */ | |
5143 | return PCI_ERS_RESULT_DISCONNECT; | |
5144 | } | |
5145 | ||
5146 | return PCI_ERS_RESULT_NEED_RESET; | |
5147 | } | |
5148 | ||
5149 | /** | |
5150 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
5151 | * @pdev: pointer to PCI device | |
5152 | */ | |
5153 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
5154 | { | |
5155 | ||
5156 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
5157 | ||
5158 | /* TODO - dump whatever for debugging purposes */ | |
5159 | ||
5160 | /* This called only if amdgpu_pci_error_detected returns | |
5161 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
5162 | * works, no need to reset slot. | |
5163 | */ | |
5164 | ||
5165 | return PCI_ERS_RESULT_RECOVERED; | |
5166 | } | |
5167 | ||
5168 | /** | |
5169 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
5170 | * @pdev: PCI device struct | |
5171 | * | |
5172 | * Description: This routine is called by the pci error recovery | |
5173 | * code after the PCI slot has been reset, just before we | |
5174 | * should resume normal operations. | |
5175 | */ | |
5176 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
5177 | { | |
5178 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5179 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 5180 | int r, i; |
7ac71382 | 5181 | bool need_full_reset = true; |
362c7b91 | 5182 | u32 memsize; |
7ac71382 | 5183 | struct list_head device_list; |
c9a6b82f AG |
5184 | |
5185 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
5186 | ||
7ac71382 | 5187 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 5188 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 5189 | |
362c7b91 AG |
5190 | /* wait for asic to come out of reset */ |
5191 | msleep(500); | |
5192 | ||
7ac71382 | 5193 | /* Restore PCI confspace */ |
c1dd4aa6 | 5194 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 5195 | |
362c7b91 AG |
5196 | /* confirm ASIC came out of reset */ |
5197 | for (i = 0; i < adev->usec_timeout; i++) { | |
5198 | memsize = amdgpu_asic_get_config_memsize(adev); | |
5199 | ||
5200 | if (memsize != 0xffffffff) | |
5201 | break; | |
5202 | udelay(1); | |
5203 | } | |
5204 | if (memsize == 0xffffffff) { | |
5205 | r = -ETIME; | |
5206 | goto out; | |
5207 | } | |
5208 | ||
8a11d283 | 5209 | adev->in_pci_err_recovery = true; |
7ac71382 | 5210 | r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset); |
bf36b52e | 5211 | adev->in_pci_err_recovery = false; |
c9a6b82f AG |
5212 | if (r) |
5213 | goto out; | |
5214 | ||
7ac71382 | 5215 | r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true); |
c9a6b82f AG |
5216 | |
5217 | out: | |
c9a6b82f | 5218 | if (!r) { |
c1dd4aa6 AG |
5219 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
5220 | pci_restore_state(adev->pdev); | |
5221 | ||
c9a6b82f AG |
5222 | DRM_INFO("PCIe error recovery succeeded\n"); |
5223 | } else { | |
5224 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
5225 | amdgpu_device_unlock_adev(adev); | |
5226 | } | |
5227 | ||
5228 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
5229 | } | |
5230 | ||
5231 | /** | |
5232 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
5233 | * @pdev: pointer to PCI device | |
5234 | * | |
5235 | * Called when the error recovery driver tells us that its | |
505199a3 | 5236 | * OK to resume normal operation. |
c9a6b82f AG |
5237 | */ |
5238 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
5239 | { | |
5240 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5241 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5242 | int i; |
c9a6b82f | 5243 | |
c9a6b82f AG |
5244 | |
5245 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca AG |
5246 | |
5247 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5248 | struct amdgpu_ring *ring = adev->rings[i]; | |
5249 | ||
5250 | if (!ring || !ring->sched.thread) | |
5251 | continue; | |
5252 | ||
5253 | ||
5254 | drm_sched_resubmit_jobs(&ring->sched); | |
5255 | drm_sched_start(&ring->sched, true); | |
5256 | } | |
5257 | ||
5258 | amdgpu_device_unlock_adev(adev); | |
c9a6b82f | 5259 | } |
c1dd4aa6 AG |
5260 | |
5261 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
5262 | { | |
5263 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5264 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5265 | int r; | |
5266 | ||
5267 | r = pci_save_state(pdev); | |
5268 | if (!r) { | |
5269 | kfree(adev->pci_state); | |
5270 | ||
5271 | adev->pci_state = pci_store_saved_state(pdev); | |
5272 | ||
5273 | if (!adev->pci_state) { | |
5274 | DRM_ERROR("Failed to store PCI saved state"); | |
5275 | return false; | |
5276 | } | |
5277 | } else { | |
5278 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
5279 | return false; | |
5280 | } | |
5281 | ||
5282 | return true; | |
5283 | } | |
5284 | ||
5285 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
5286 | { | |
5287 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5288 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5289 | int r; | |
5290 | ||
5291 | if (!adev->pci_state) | |
5292 | return false; | |
5293 | ||
5294 | r = pci_load_saved_state(pdev, adev->pci_state); | |
5295 | ||
5296 | if (!r) { | |
5297 | pci_restore_state(pdev); | |
5298 | } else { | |
5299 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
5300 | return false; | |
5301 | } | |
5302 | ||
5303 | return true; | |
5304 | } | |
5305 | ||
5306 |