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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
d0dd7f0c | 43 | #include "amd_pcie.h" |
33f34802 KW |
44 | #ifdef CONFIG_DRM_AMDGPU_SI |
45 | #include "si.h" | |
46 | #endif | |
a2e73f56 AD |
47 | #ifdef CONFIG_DRM_AMDGPU_CIK |
48 | #include "cik.h" | |
49 | #endif | |
aaa36a97 | 50 | #include "vi.h" |
d38ceaf9 | 51 | #include "bif/bif_4_1_d.h" |
9accf2fd | 52 | #include <linux/pci.h> |
bec86378 | 53 | #include <linux/firmware.h> |
d38ceaf9 AD |
54 | |
55 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
56 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
57 | ||
58 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
59 | "TAHITI", |
60 | "PITCAIRN", | |
61 | "VERDE", | |
62 | "OLAND", | |
63 | "HAINAN", | |
d38ceaf9 AD |
64 | "BONAIRE", |
65 | "KAVERI", | |
66 | "KABINI", | |
67 | "HAWAII", | |
68 | "MULLINS", | |
69 | "TOPAZ", | |
70 | "TONGA", | |
48299f95 | 71 | "FIJI", |
d38ceaf9 | 72 | "CARRIZO", |
139f4917 | 73 | "STONEY", |
2cc0c0b5 FC |
74 | "POLARIS10", |
75 | "POLARIS11", | |
d38ceaf9 AD |
76 | "LAST", |
77 | }; | |
78 | ||
79 | bool amdgpu_device_is_px(struct drm_device *dev) | |
80 | { | |
81 | struct amdgpu_device *adev = dev->dev_private; | |
82 | ||
2f7d10b3 | 83 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
84 | return true; |
85 | return false; | |
86 | } | |
87 | ||
88 | /* | |
89 | * MMIO register access helper functions. | |
90 | */ | |
91 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
92 | bool always_indirect) | |
93 | { | |
f4b373f4 TSD |
94 | uint32_t ret; |
95 | ||
d38ceaf9 | 96 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
f4b373f4 | 97 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
98 | else { |
99 | unsigned long flags; | |
d38ceaf9 AD |
100 | |
101 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
102 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
103 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
104 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 105 | } |
f4b373f4 TSD |
106 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
107 | return ret; | |
d38ceaf9 AD |
108 | } |
109 | ||
110 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
111 | bool always_indirect) | |
112 | { | |
f4b373f4 | 113 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 114 | |
d38ceaf9 AD |
115 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
116 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
117 | else { | |
118 | unsigned long flags; | |
119 | ||
120 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
121 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
122 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
123 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
124 | } | |
125 | } | |
126 | ||
127 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
128 | { | |
129 | if ((reg * 4) < adev->rio_mem_size) | |
130 | return ioread32(adev->rio_mem + (reg * 4)); | |
131 | else { | |
132 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
133 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
134 | } | |
135 | } | |
136 | ||
137 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
138 | { | |
139 | ||
140 | if ((reg * 4) < adev->rio_mem_size) | |
141 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
142 | else { | |
143 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
144 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
145 | } | |
146 | } | |
147 | ||
148 | /** | |
149 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
150 | * | |
151 | * @adev: amdgpu_device pointer | |
152 | * @index: doorbell index | |
153 | * | |
154 | * Returns the value in the doorbell aperture at the | |
155 | * requested doorbell index (CIK). | |
156 | */ | |
157 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
158 | { | |
159 | if (index < adev->doorbell.num_doorbells) { | |
160 | return readl(adev->doorbell.ptr + index); | |
161 | } else { | |
162 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
163 | return 0; | |
164 | } | |
165 | } | |
166 | ||
167 | /** | |
168 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
169 | * | |
170 | * @adev: amdgpu_device pointer | |
171 | * @index: doorbell index | |
172 | * @v: value to write | |
173 | * | |
174 | * Writes @v to the doorbell aperture at the | |
175 | * requested doorbell index (CIK). | |
176 | */ | |
177 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
178 | { | |
179 | if (index < adev->doorbell.num_doorbells) { | |
180 | writel(v, adev->doorbell.ptr + index); | |
181 | } else { | |
182 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
183 | } | |
184 | } | |
185 | ||
186 | /** | |
187 | * amdgpu_invalid_rreg - dummy reg read function | |
188 | * | |
189 | * @adev: amdgpu device pointer | |
190 | * @reg: offset of register | |
191 | * | |
192 | * Dummy register read function. Used for register blocks | |
193 | * that certain asics don't have (all asics). | |
194 | * Returns the value in the register. | |
195 | */ | |
196 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
197 | { | |
198 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
199 | BUG(); | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /** | |
204 | * amdgpu_invalid_wreg - dummy reg write function | |
205 | * | |
206 | * @adev: amdgpu device pointer | |
207 | * @reg: offset of register | |
208 | * @v: value to write to the register | |
209 | * | |
210 | * Dummy register read function. Used for register blocks | |
211 | * that certain asics don't have (all asics). | |
212 | */ | |
213 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
214 | { | |
215 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
216 | reg, v); | |
217 | BUG(); | |
218 | } | |
219 | ||
220 | /** | |
221 | * amdgpu_block_invalid_rreg - dummy reg read function | |
222 | * | |
223 | * @adev: amdgpu device pointer | |
224 | * @block: offset of instance | |
225 | * @reg: offset of register | |
226 | * | |
227 | * Dummy register read function. Used for register blocks | |
228 | * that certain asics don't have (all asics). | |
229 | * Returns the value in the register. | |
230 | */ | |
231 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
232 | uint32_t block, uint32_t reg) | |
233 | { | |
234 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
235 | reg, block); | |
236 | BUG(); | |
237 | return 0; | |
238 | } | |
239 | ||
240 | /** | |
241 | * amdgpu_block_invalid_wreg - dummy reg write function | |
242 | * | |
243 | * @adev: amdgpu device pointer | |
244 | * @block: offset of instance | |
245 | * @reg: offset of register | |
246 | * @v: value to write to the register | |
247 | * | |
248 | * Dummy register read function. Used for register blocks | |
249 | * that certain asics don't have (all asics). | |
250 | */ | |
251 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
252 | uint32_t block, | |
253 | uint32_t reg, uint32_t v) | |
254 | { | |
255 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
256 | reg, block, v); | |
257 | BUG(); | |
258 | } | |
259 | ||
260 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
261 | { | |
262 | int r; | |
263 | ||
264 | if (adev->vram_scratch.robj == NULL) { | |
265 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d AD |
266 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
267 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 268 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
269 | if (r) { |
270 | return r; | |
271 | } | |
272 | } | |
273 | ||
274 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
275 | if (unlikely(r != 0)) | |
276 | return r; | |
277 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
278 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
279 | if (r) { | |
280 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
281 | return r; | |
282 | } | |
283 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
284 | (void **)&adev->vram_scratch.ptr); | |
285 | if (r) | |
286 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
287 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
288 | ||
289 | return r; | |
290 | } | |
291 | ||
292 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
293 | { | |
294 | int r; | |
295 | ||
296 | if (adev->vram_scratch.robj == NULL) { | |
297 | return; | |
298 | } | |
299 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
300 | if (likely(r == 0)) { | |
301 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
302 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
303 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
304 | } | |
305 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
306 | } | |
307 | ||
308 | /** | |
309 | * amdgpu_program_register_sequence - program an array of registers. | |
310 | * | |
311 | * @adev: amdgpu_device pointer | |
312 | * @registers: pointer to the register array | |
313 | * @array_size: size of the register array | |
314 | * | |
315 | * Programs an array or registers with and and or masks. | |
316 | * This is a helper for setting golden registers. | |
317 | */ | |
318 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
319 | const u32 *registers, | |
320 | const u32 array_size) | |
321 | { | |
322 | u32 tmp, reg, and_mask, or_mask; | |
323 | int i; | |
324 | ||
325 | if (array_size % 3) | |
326 | return; | |
327 | ||
328 | for (i = 0; i < array_size; i +=3) { | |
329 | reg = registers[i + 0]; | |
330 | and_mask = registers[i + 1]; | |
331 | or_mask = registers[i + 2]; | |
332 | ||
333 | if (and_mask == 0xffffffff) { | |
334 | tmp = or_mask; | |
335 | } else { | |
336 | tmp = RREG32(reg); | |
337 | tmp &= ~and_mask; | |
338 | tmp |= or_mask; | |
339 | } | |
340 | WREG32(reg, tmp); | |
341 | } | |
342 | } | |
343 | ||
344 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
345 | { | |
346 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
347 | } | |
348 | ||
349 | /* | |
350 | * GPU doorbell aperture helpers function. | |
351 | */ | |
352 | /** | |
353 | * amdgpu_doorbell_init - Init doorbell driver information. | |
354 | * | |
355 | * @adev: amdgpu_device pointer | |
356 | * | |
357 | * Init doorbell driver information (CIK) | |
358 | * Returns 0 on success, error on failure. | |
359 | */ | |
360 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
361 | { | |
362 | /* doorbell bar mapping */ | |
363 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
364 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
365 | ||
edf600da | 366 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
367 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
368 | if (adev->doorbell.num_doorbells == 0) | |
369 | return -EINVAL; | |
370 | ||
371 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
372 | if (adev->doorbell.ptr == NULL) { | |
373 | return -ENOMEM; | |
374 | } | |
375 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
376 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | /** | |
382 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
383 | * | |
384 | * @adev: amdgpu_device pointer | |
385 | * | |
386 | * Tear down doorbell driver information (CIK) | |
387 | */ | |
388 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
389 | { | |
390 | iounmap(adev->doorbell.ptr); | |
391 | adev->doorbell.ptr = NULL; | |
392 | } | |
393 | ||
394 | /** | |
395 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
396 | * setup amdkfd | |
397 | * | |
398 | * @adev: amdgpu_device pointer | |
399 | * @aperture_base: output returning doorbell aperture base physical address | |
400 | * @aperture_size: output returning doorbell aperture size in bytes | |
401 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
402 | * | |
403 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
404 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
405 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
406 | */ | |
407 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
408 | phys_addr_t *aperture_base, | |
409 | size_t *aperture_size, | |
410 | size_t *start_offset) | |
411 | { | |
412 | /* | |
413 | * The first num_doorbells are used by amdgpu. | |
414 | * amdkfd takes whatever's left in the aperture. | |
415 | */ | |
416 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
417 | *aperture_base = adev->doorbell.base; | |
418 | *aperture_size = adev->doorbell.size; | |
419 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
420 | } else { | |
421 | *aperture_base = 0; | |
422 | *aperture_size = 0; | |
423 | *start_offset = 0; | |
424 | } | |
425 | } | |
426 | ||
427 | /* | |
428 | * amdgpu_wb_*() | |
429 | * Writeback is the the method by which the the GPU updates special pages | |
430 | * in memory with the status of certain GPU events (fences, ring pointers, | |
431 | * etc.). | |
432 | */ | |
433 | ||
434 | /** | |
435 | * amdgpu_wb_fini - Disable Writeback and free memory | |
436 | * | |
437 | * @adev: amdgpu_device pointer | |
438 | * | |
439 | * Disables Writeback and frees the Writeback memory (all asics). | |
440 | * Used at driver shutdown. | |
441 | */ | |
442 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
443 | { | |
444 | if (adev->wb.wb_obj) { | |
445 | if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) { | |
446 | amdgpu_bo_kunmap(adev->wb.wb_obj); | |
447 | amdgpu_bo_unpin(adev->wb.wb_obj); | |
448 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
449 | } | |
450 | amdgpu_bo_unref(&adev->wb.wb_obj); | |
451 | adev->wb.wb = NULL; | |
452 | adev->wb.wb_obj = NULL; | |
453 | } | |
454 | } | |
455 | ||
456 | /** | |
457 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
458 | * | |
459 | * @adev: amdgpu_device pointer | |
460 | * | |
461 | * Disables Writeback and frees the Writeback memory (all asics). | |
462 | * Used at driver startup. | |
463 | * Returns 0 on success or an -error on failure. | |
464 | */ | |
465 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
466 | { | |
467 | int r; | |
468 | ||
469 | if (adev->wb.wb_obj == NULL) { | |
470 | r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true, | |
72d7668b CK |
471 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, |
472 | &adev->wb.wb_obj); | |
d38ceaf9 AD |
473 | if (r) { |
474 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
475 | return r; | |
476 | } | |
477 | r = amdgpu_bo_reserve(adev->wb.wb_obj, false); | |
478 | if (unlikely(r != 0)) { | |
479 | amdgpu_wb_fini(adev); | |
480 | return r; | |
481 | } | |
482 | r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT, | |
483 | &adev->wb.gpu_addr); | |
484 | if (r) { | |
485 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
486 | dev_warn(adev->dev, "(%d) pin WB bo failed\n", r); | |
487 | amdgpu_wb_fini(adev); | |
488 | return r; | |
489 | } | |
490 | r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb); | |
491 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
492 | if (r) { | |
493 | dev_warn(adev->dev, "(%d) map WB bo failed\n", r); | |
494 | amdgpu_wb_fini(adev); | |
495 | return r; | |
496 | } | |
497 | ||
498 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
499 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
500 | ||
501 | /* clear wb memory */ | |
502 | memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE); | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | /** | |
509 | * amdgpu_wb_get - Allocate a wb entry | |
510 | * | |
511 | * @adev: amdgpu_device pointer | |
512 | * @wb: wb index | |
513 | * | |
514 | * Allocate a wb slot for use by the driver (all asics). | |
515 | * Returns 0 on success or -EINVAL on failure. | |
516 | */ | |
517 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
518 | { | |
519 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
520 | if (offset < adev->wb.num_wb) { | |
521 | __set_bit(offset, adev->wb.used); | |
522 | *wb = offset; | |
523 | return 0; | |
524 | } else { | |
525 | return -EINVAL; | |
526 | } | |
527 | } | |
528 | ||
529 | /** | |
530 | * amdgpu_wb_free - Free a wb entry | |
531 | * | |
532 | * @adev: amdgpu_device pointer | |
533 | * @wb: wb index | |
534 | * | |
535 | * Free a wb slot allocated for use by the driver (all asics) | |
536 | */ | |
537 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
538 | { | |
539 | if (wb < adev->wb.num_wb) | |
540 | __clear_bit(wb, adev->wb.used); | |
541 | } | |
542 | ||
543 | /** | |
544 | * amdgpu_vram_location - try to find VRAM location | |
545 | * @adev: amdgpu device structure holding all necessary informations | |
546 | * @mc: memory controller structure holding memory informations | |
547 | * @base: base address at which to put VRAM | |
548 | * | |
549 | * Function will place try to place VRAM at base address provided | |
550 | * as parameter (which is so far either PCI aperture address or | |
551 | * for IGP TOM base address). | |
552 | * | |
553 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
554 | * address space then we limit the VRAM size to the aperture. | |
555 | * | |
556 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
557 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
558 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
559 | * not IGP. | |
560 | * | |
561 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
562 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
563 | * Novell bug 204882 + along with lots of ubuntu ones | |
564 | * | |
565 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
566 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
567 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
568 | * ones) | |
569 | * | |
570 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
571 | * explicitly check for that thought. | |
572 | * | |
573 | * FIXME: when reducing VRAM size align new size on power of 2. | |
574 | */ | |
575 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
576 | { | |
577 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
578 | ||
579 | mc->vram_start = base; | |
580 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
581 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
582 | mc->real_vram_size = mc->aper_size; | |
583 | mc->mc_vram_size = mc->aper_size; | |
584 | } | |
585 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
586 | if (limit && limit < mc->real_vram_size) | |
587 | mc->real_vram_size = limit; | |
588 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
589 | mc->mc_vram_size >> 20, mc->vram_start, | |
590 | mc->vram_end, mc->real_vram_size >> 20); | |
591 | } | |
592 | ||
593 | /** | |
594 | * amdgpu_gtt_location - try to find GTT location | |
595 | * @adev: amdgpu device structure holding all necessary informations | |
596 | * @mc: memory controller structure holding memory informations | |
597 | * | |
598 | * Function will place try to place GTT before or after VRAM. | |
599 | * | |
600 | * If GTT size is bigger than space left then we ajust GTT size. | |
601 | * Thus function will never fails. | |
602 | * | |
603 | * FIXME: when reducing GTT size align new size on power of 2. | |
604 | */ | |
605 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
606 | { | |
607 | u64 size_af, size_bf; | |
608 | ||
609 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
610 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
611 | if (size_bf > size_af) { | |
612 | if (mc->gtt_size > size_bf) { | |
613 | dev_warn(adev->dev, "limiting GTT\n"); | |
614 | mc->gtt_size = size_bf; | |
615 | } | |
616 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; | |
617 | } else { | |
618 | if (mc->gtt_size > size_af) { | |
619 | dev_warn(adev->dev, "limiting GTT\n"); | |
620 | mc->gtt_size = size_af; | |
621 | } | |
622 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
623 | } | |
624 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
625 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
626 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
627 | } | |
628 | ||
629 | /* | |
630 | * GPU helpers function. | |
631 | */ | |
632 | /** | |
633 | * amdgpu_card_posted - check if the hw has already been initialized | |
634 | * | |
635 | * @adev: amdgpu_device pointer | |
636 | * | |
637 | * Check if the asic has been initialized (all asics). | |
638 | * Used at driver startup. | |
639 | * Returns true if initialized or false if not. | |
640 | */ | |
641 | bool amdgpu_card_posted(struct amdgpu_device *adev) | |
642 | { | |
643 | uint32_t reg; | |
644 | ||
645 | /* then check MEM_SIZE, in case the crtcs are off */ | |
646 | reg = RREG32(mmCONFIG_MEMSIZE); | |
647 | ||
648 | if (reg) | |
649 | return true; | |
650 | ||
651 | return false; | |
652 | ||
653 | } | |
654 | ||
bec86378 ML |
655 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
656 | { | |
657 | if (amdgpu_sriov_vf(adev)) | |
658 | return false; | |
659 | ||
660 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
661 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
662 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
663 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
664 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
665 | */ |
666 | if (adev->asic_type == CHIP_FIJI) { | |
667 | int err; | |
668 | uint32_t fw_ver; | |
669 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
670 | /* force vPost if error occured */ | |
671 | if (err) | |
672 | return true; | |
673 | ||
674 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
675 | if (fw_ver < 0x00160e00) |
676 | return true; | |
bec86378 | 677 | } |
bec86378 | 678 | } |
1da2c326 | 679 | return !amdgpu_card_posted(adev); |
bec86378 ML |
680 | } |
681 | ||
d38ceaf9 AD |
682 | /** |
683 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
684 | * | |
685 | * @adev: amdgpu_device pointer | |
686 | * | |
687 | * Allocate the dummy page used by the driver (all asics). | |
688 | * This dummy page is used by the driver as a filler for gart entries | |
689 | * when pages are taken out of the GART | |
690 | * Returns 0 on sucess, -ENOMEM on failure. | |
691 | */ | |
692 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
693 | { | |
694 | if (adev->dummy_page.page) | |
695 | return 0; | |
696 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
697 | if (adev->dummy_page.page == NULL) | |
698 | return -ENOMEM; | |
699 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
700 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
701 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
702 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
703 | __free_page(adev->dummy_page.page); | |
704 | adev->dummy_page.page = NULL; | |
705 | return -ENOMEM; | |
706 | } | |
707 | return 0; | |
708 | } | |
709 | ||
710 | /** | |
711 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
712 | * | |
713 | * @adev: amdgpu_device pointer | |
714 | * | |
715 | * Frees the dummy page used by the driver (all asics). | |
716 | */ | |
717 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
718 | { | |
719 | if (adev->dummy_page.page == NULL) | |
720 | return; | |
721 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
722 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
723 | __free_page(adev->dummy_page.page); | |
724 | adev->dummy_page.page = NULL; | |
725 | } | |
726 | ||
727 | ||
728 | /* ATOM accessor methods */ | |
729 | /* | |
730 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
731 | * driver registers callbacks to access registers and the interpreter | |
732 | * in the driver parses the tables and executes then to program specific | |
733 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
734 | * atombios.h, and atom.c | |
735 | */ | |
736 | ||
737 | /** | |
738 | * cail_pll_read - read PLL register | |
739 | * | |
740 | * @info: atom card_info pointer | |
741 | * @reg: PLL register offset | |
742 | * | |
743 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
744 | * Returns the value of the PLL register. | |
745 | */ | |
746 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
747 | { | |
748 | return 0; | |
749 | } | |
750 | ||
751 | /** | |
752 | * cail_pll_write - write PLL register | |
753 | * | |
754 | * @info: atom card_info pointer | |
755 | * @reg: PLL register offset | |
756 | * @val: value to write to the pll register | |
757 | * | |
758 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
759 | */ | |
760 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
761 | { | |
762 | ||
763 | } | |
764 | ||
765 | /** | |
766 | * cail_mc_read - read MC (Memory Controller) register | |
767 | * | |
768 | * @info: atom card_info pointer | |
769 | * @reg: MC register offset | |
770 | * | |
771 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
772 | * Returns the value of the MC register. | |
773 | */ | |
774 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
775 | { | |
776 | return 0; | |
777 | } | |
778 | ||
779 | /** | |
780 | * cail_mc_write - write MC (Memory Controller) register | |
781 | * | |
782 | * @info: atom card_info pointer | |
783 | * @reg: MC register offset | |
784 | * @val: value to write to the pll register | |
785 | * | |
786 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
787 | */ | |
788 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
789 | { | |
790 | ||
791 | } | |
792 | ||
793 | /** | |
794 | * cail_reg_write - write MMIO register | |
795 | * | |
796 | * @info: atom card_info pointer | |
797 | * @reg: MMIO register offset | |
798 | * @val: value to write to the pll register | |
799 | * | |
800 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
801 | */ | |
802 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
803 | { | |
804 | struct amdgpu_device *adev = info->dev->dev_private; | |
805 | ||
806 | WREG32(reg, val); | |
807 | } | |
808 | ||
809 | /** | |
810 | * cail_reg_read - read MMIO register | |
811 | * | |
812 | * @info: atom card_info pointer | |
813 | * @reg: MMIO register offset | |
814 | * | |
815 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
816 | * Returns the value of the MMIO register. | |
817 | */ | |
818 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
819 | { | |
820 | struct amdgpu_device *adev = info->dev->dev_private; | |
821 | uint32_t r; | |
822 | ||
823 | r = RREG32(reg); | |
824 | return r; | |
825 | } | |
826 | ||
827 | /** | |
828 | * cail_ioreg_write - write IO register | |
829 | * | |
830 | * @info: atom card_info pointer | |
831 | * @reg: IO register offset | |
832 | * @val: value to write to the pll register | |
833 | * | |
834 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
835 | */ | |
836 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
837 | { | |
838 | struct amdgpu_device *adev = info->dev->dev_private; | |
839 | ||
840 | WREG32_IO(reg, val); | |
841 | } | |
842 | ||
843 | /** | |
844 | * cail_ioreg_read - read IO register | |
845 | * | |
846 | * @info: atom card_info pointer | |
847 | * @reg: IO register offset | |
848 | * | |
849 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
850 | * Returns the value of the IO register. | |
851 | */ | |
852 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
853 | { | |
854 | struct amdgpu_device *adev = info->dev->dev_private; | |
855 | uint32_t r; | |
856 | ||
857 | r = RREG32_IO(reg); | |
858 | return r; | |
859 | } | |
860 | ||
861 | /** | |
862 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
863 | * | |
864 | * @adev: amdgpu_device pointer | |
865 | * | |
866 | * Frees the driver info and register access callbacks for the ATOM | |
867 | * interpreter (r4xx+). | |
868 | * Called at driver shutdown. | |
869 | */ | |
870 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
871 | { | |
89e0ec9f | 872 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 873 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
874 | kfree(adev->mode_info.atom_context->iio); |
875 | } | |
d38ceaf9 AD |
876 | kfree(adev->mode_info.atom_context); |
877 | adev->mode_info.atom_context = NULL; | |
878 | kfree(adev->mode_info.atom_card_info); | |
879 | adev->mode_info.atom_card_info = NULL; | |
880 | } | |
881 | ||
882 | /** | |
883 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
884 | * | |
885 | * @adev: amdgpu_device pointer | |
886 | * | |
887 | * Initializes the driver info and register access callbacks for the | |
888 | * ATOM interpreter (r4xx+). | |
889 | * Returns 0 on sucess, -ENOMEM on failure. | |
890 | * Called at driver startup. | |
891 | */ | |
892 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
893 | { | |
894 | struct card_info *atom_card_info = | |
895 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
896 | ||
897 | if (!atom_card_info) | |
898 | return -ENOMEM; | |
899 | ||
900 | adev->mode_info.atom_card_info = atom_card_info; | |
901 | atom_card_info->dev = adev->ddev; | |
902 | atom_card_info->reg_read = cail_reg_read; | |
903 | atom_card_info->reg_write = cail_reg_write; | |
904 | /* needed for iio ops */ | |
905 | if (adev->rio_mem) { | |
906 | atom_card_info->ioreg_read = cail_ioreg_read; | |
907 | atom_card_info->ioreg_write = cail_ioreg_write; | |
908 | } else { | |
909 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
910 | atom_card_info->ioreg_read = cail_reg_read; | |
911 | atom_card_info->ioreg_write = cail_reg_write; | |
912 | } | |
913 | atom_card_info->mc_read = cail_mc_read; | |
914 | atom_card_info->mc_write = cail_mc_write; | |
915 | atom_card_info->pll_read = cail_pll_read; | |
916 | atom_card_info->pll_write = cail_pll_write; | |
917 | ||
918 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
919 | if (!adev->mode_info.atom_context) { | |
920 | amdgpu_atombios_fini(adev); | |
921 | return -ENOMEM; | |
922 | } | |
923 | ||
924 | mutex_init(&adev->mode_info.atom_context->mutex); | |
925 | amdgpu_atombios_scratch_regs_init(adev); | |
926 | amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); | |
927 | return 0; | |
928 | } | |
929 | ||
930 | /* if we get transitioned to only one device, take VGA back */ | |
931 | /** | |
932 | * amdgpu_vga_set_decode - enable/disable vga decode | |
933 | * | |
934 | * @cookie: amdgpu_device pointer | |
935 | * @state: enable/disable vga decode | |
936 | * | |
937 | * Enable/disable vga decode (all asics). | |
938 | * Returns VGA resource flags. | |
939 | */ | |
940 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
941 | { | |
942 | struct amdgpu_device *adev = cookie; | |
943 | amdgpu_asic_set_vga_state(adev, state); | |
944 | if (state) | |
945 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
946 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
947 | else | |
948 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
949 | } | |
950 | ||
951 | /** | |
952 | * amdgpu_check_pot_argument - check that argument is a power of two | |
953 | * | |
954 | * @arg: value to check | |
955 | * | |
956 | * Validates that a certain argument is a power of two (all asics). | |
957 | * Returns true if argument is valid. | |
958 | */ | |
959 | static bool amdgpu_check_pot_argument(int arg) | |
960 | { | |
961 | return (arg & (arg - 1)) == 0; | |
962 | } | |
963 | ||
964 | /** | |
965 | * amdgpu_check_arguments - validate module params | |
966 | * | |
967 | * @adev: amdgpu_device pointer | |
968 | * | |
969 | * Validates certain module parameters and updates | |
970 | * the associated values used by the driver (all asics). | |
971 | */ | |
972 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
973 | { | |
5b011235 CZ |
974 | if (amdgpu_sched_jobs < 4) { |
975 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
976 | amdgpu_sched_jobs); | |
977 | amdgpu_sched_jobs = 4; | |
978 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
979 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
980 | amdgpu_sched_jobs); | |
981 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
982 | } | |
d38ceaf9 AD |
983 | |
984 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 985 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
986 | if (amdgpu_gart_size < 32) { |
987 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
988 | amdgpu_gart_size); | |
989 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
990 | } |
991 | } | |
992 | ||
993 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
994 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
995 | amdgpu_vm_size); | |
8dacc127 | 996 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
997 | } |
998 | ||
999 | if (amdgpu_vm_size < 1) { | |
1000 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1001 | amdgpu_vm_size); | |
8dacc127 | 1002 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1003 | } |
1004 | ||
1005 | /* | |
1006 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
1007 | */ | |
1008 | if (amdgpu_vm_size > 1024) { | |
1009 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1010 | amdgpu_vm_size); | |
8dacc127 | 1011 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1012 | } |
1013 | ||
1014 | /* defines number of bits in page table versus page directory, | |
1015 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1016 | * page table and the remaining bits are in the page directory */ | |
1017 | if (amdgpu_vm_block_size == -1) { | |
1018 | ||
1019 | /* Total bits covered by PD + PTs */ | |
1020 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
1021 | ||
1022 | /* Make sure the PD is 4K in size up to 8GB address space. | |
1023 | Above that split equal between PD and PTs */ | |
1024 | if (amdgpu_vm_size <= 8) | |
1025 | amdgpu_vm_block_size = bits - 9; | |
1026 | else | |
1027 | amdgpu_vm_block_size = (bits + 3) / 2; | |
1028 | ||
1029 | } else if (amdgpu_vm_block_size < 9) { | |
1030 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
1031 | amdgpu_vm_block_size); | |
1032 | amdgpu_vm_block_size = 9; | |
1033 | } | |
1034 | ||
1035 | if (amdgpu_vm_block_size > 24 || | |
1036 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1037 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1038 | amdgpu_vm_block_size); | |
1039 | amdgpu_vm_block_size = 9; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /** | |
1044 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1045 | * | |
1046 | * @pdev: pci dev pointer | |
1694467b | 1047 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1048 | * |
1049 | * Callback for the switcheroo driver. Suspends or resumes the | |
1050 | * the asics before or after it is powered up using ACPI methods. | |
1051 | */ | |
1052 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1053 | { | |
1054 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1055 | ||
1056 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1057 | return; | |
1058 | ||
1059 | if (state == VGA_SWITCHEROO_ON) { | |
1060 | unsigned d3_delay = dev->pdev->d3_delay; | |
1061 | ||
1062 | printk(KERN_INFO "amdgpu: switched on\n"); | |
1063 | /* don't suspend or resume card normally */ | |
1064 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1065 | ||
810ddc3a | 1066 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1067 | |
1068 | dev->pdev->d3_delay = d3_delay; | |
1069 | ||
1070 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1071 | drm_kms_helper_poll_enable(dev); | |
1072 | } else { | |
1073 | printk(KERN_INFO "amdgpu: switched off\n"); | |
1074 | drm_kms_helper_poll_disable(dev); | |
1075 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1076 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1077 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1078 | } | |
1079 | } | |
1080 | ||
1081 | /** | |
1082 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1083 | * | |
1084 | * @pdev: pci dev pointer | |
1085 | * | |
1086 | * Callback for the switcheroo driver. Check of the switcheroo | |
1087 | * state can be changed. | |
1088 | * Returns true if the state can be changed, false if not. | |
1089 | */ | |
1090 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1091 | { | |
1092 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1093 | ||
1094 | /* | |
1095 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1096 | * locking inversion with the driver load path. And the access here is | |
1097 | * completely racy anyway. So don't bother with locking for now. | |
1098 | */ | |
1099 | return dev->open_count == 0; | |
1100 | } | |
1101 | ||
1102 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1103 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1104 | .reprobe = NULL, | |
1105 | .can_switch = amdgpu_switcheroo_can_switch, | |
1106 | }; | |
1107 | ||
1108 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1109 | enum amd_ip_block_type block_type, |
1110 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1111 | { |
1112 | int i, r = 0; | |
1113 | ||
1114 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1115 | if (!adev->ip_block_status[i].valid) |
1116 | continue; | |
d38ceaf9 | 1117 | if (adev->ip_blocks[i].type == block_type) { |
5fc3aeeb | 1118 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
d38ceaf9 AD |
1119 | state); |
1120 | if (r) | |
1121 | return r; | |
a225bf1c | 1122 | break; |
d38ceaf9 AD |
1123 | } |
1124 | } | |
1125 | return r; | |
1126 | } | |
1127 | ||
1128 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1129 | enum amd_ip_block_type block_type, |
1130 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1131 | { |
1132 | int i, r = 0; | |
1133 | ||
1134 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1135 | if (!adev->ip_block_status[i].valid) |
1136 | continue; | |
d38ceaf9 | 1137 | if (adev->ip_blocks[i].type == block_type) { |
5fc3aeeb | 1138 | r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev, |
d38ceaf9 AD |
1139 | state); |
1140 | if (r) | |
1141 | return r; | |
a225bf1c | 1142 | break; |
d38ceaf9 AD |
1143 | } |
1144 | } | |
1145 | return r; | |
1146 | } | |
1147 | ||
5dbbb60b AD |
1148 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1149 | enum amd_ip_block_type block_type) | |
1150 | { | |
1151 | int i, r; | |
1152 | ||
1153 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1154 | if (!adev->ip_block_status[i].valid) |
1155 | continue; | |
5dbbb60b AD |
1156 | if (adev->ip_blocks[i].type == block_type) { |
1157 | r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev); | |
1158 | if (r) | |
1159 | return r; | |
1160 | break; | |
1161 | } | |
1162 | } | |
1163 | return 0; | |
1164 | ||
1165 | } | |
1166 | ||
1167 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1168 | enum amd_ip_block_type block_type) | |
1169 | { | |
1170 | int i; | |
1171 | ||
1172 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1173 | if (!adev->ip_block_status[i].valid) |
1174 | continue; | |
5dbbb60b AD |
1175 | if (adev->ip_blocks[i].type == block_type) |
1176 | return adev->ip_blocks[i].funcs->is_idle((void *)adev); | |
1177 | } | |
1178 | return true; | |
1179 | ||
1180 | } | |
1181 | ||
d38ceaf9 AD |
1182 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( |
1183 | struct amdgpu_device *adev, | |
5fc3aeeb | 1184 | enum amd_ip_block_type type) |
d38ceaf9 AD |
1185 | { |
1186 | int i; | |
1187 | ||
1188 | for (i = 0; i < adev->num_ip_blocks; i++) | |
1189 | if (adev->ip_blocks[i].type == type) | |
1190 | return &adev->ip_blocks[i]; | |
1191 | ||
1192 | return NULL; | |
1193 | } | |
1194 | ||
1195 | /** | |
1196 | * amdgpu_ip_block_version_cmp | |
1197 | * | |
1198 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1199 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1200 | * @major: major version |
1201 | * @minor: minor version | |
1202 | * | |
1203 | * return 0 if equal or greater | |
1204 | * return 1 if smaller or the ip_block doesn't exist | |
1205 | */ | |
1206 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1207 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1208 | u32 major, u32 minor) |
1209 | { | |
1210 | const struct amdgpu_ip_block_version *ip_block; | |
1211 | ip_block = amdgpu_get_ip_block(adev, type); | |
1212 | ||
1213 | if (ip_block && ((ip_block->major > major) || | |
1214 | ((ip_block->major == major) && | |
1215 | (ip_block->minor >= minor)))) | |
1216 | return 0; | |
1217 | ||
1218 | return 1; | |
1219 | } | |
1220 | ||
9accf2fd ED |
1221 | static void amdgpu_whether_enable_virtual_display(struct amdgpu_device *adev) |
1222 | { | |
1223 | adev->enable_virtual_display = false; | |
1224 | ||
1225 | if (amdgpu_virtual_display) { | |
1226 | struct drm_device *ddev = adev->ddev; | |
1227 | const char *pci_address_name = pci_name(ddev->pdev); | |
1228 | char *pciaddstr, *pciaddstr_tmp, *pciaddname; | |
1229 | ||
1230 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1231 | pciaddstr_tmp = pciaddstr; | |
1232 | while ((pciaddname = strsep(&pciaddstr_tmp, ";"))) { | |
1233 | if (!strcmp(pci_address_name, pciaddname)) { | |
1234 | adev->enable_virtual_display = true; | |
1235 | break; | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d\n", | |
1240 | amdgpu_virtual_display, pci_address_name, | |
1241 | adev->enable_virtual_display); | |
1242 | ||
1243 | kfree(pciaddstr); | |
1244 | } | |
1245 | } | |
1246 | ||
d38ceaf9 AD |
1247 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1248 | { | |
aaa36a97 | 1249 | int i, r; |
d38ceaf9 | 1250 | |
9accf2fd | 1251 | amdgpu_whether_enable_virtual_display(adev); |
a6be7570 | 1252 | |
d38ceaf9 | 1253 | switch (adev->asic_type) { |
aaa36a97 AD |
1254 | case CHIP_TOPAZ: |
1255 | case CHIP_TONGA: | |
48299f95 | 1256 | case CHIP_FIJI: |
2cc0c0b5 FC |
1257 | case CHIP_POLARIS11: |
1258 | case CHIP_POLARIS10: | |
aaa36a97 | 1259 | case CHIP_CARRIZO: |
39bb0c92 SL |
1260 | case CHIP_STONEY: |
1261 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1262 | adev->family = AMDGPU_FAMILY_CZ; |
1263 | else | |
1264 | adev->family = AMDGPU_FAMILY_VI; | |
1265 | ||
1266 | r = vi_set_ip_blocks(adev); | |
1267 | if (r) | |
1268 | return r; | |
1269 | break; | |
33f34802 KW |
1270 | #ifdef CONFIG_DRM_AMDGPU_SI |
1271 | case CHIP_VERDE: | |
1272 | case CHIP_TAHITI: | |
1273 | case CHIP_PITCAIRN: | |
1274 | case CHIP_OLAND: | |
1275 | case CHIP_HAINAN: | |
295d0daf | 1276 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1277 | r = si_set_ip_blocks(adev); |
1278 | if (r) | |
1279 | return r; | |
1280 | break; | |
1281 | #endif | |
a2e73f56 AD |
1282 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1283 | case CHIP_BONAIRE: | |
1284 | case CHIP_HAWAII: | |
1285 | case CHIP_KAVERI: | |
1286 | case CHIP_KABINI: | |
1287 | case CHIP_MULLINS: | |
1288 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1289 | adev->family = AMDGPU_FAMILY_CI; | |
1290 | else | |
1291 | adev->family = AMDGPU_FAMILY_KV; | |
1292 | ||
1293 | r = cik_set_ip_blocks(adev); | |
1294 | if (r) | |
1295 | return r; | |
1296 | break; | |
1297 | #endif | |
d38ceaf9 AD |
1298 | default: |
1299 | /* FIXME: not supported yet */ | |
1300 | return -EINVAL; | |
1301 | } | |
1302 | ||
8faf0e08 AD |
1303 | adev->ip_block_status = kcalloc(adev->num_ip_blocks, |
1304 | sizeof(struct amdgpu_ip_block_status), GFP_KERNEL); | |
1305 | if (adev->ip_block_status == NULL) | |
d8d090b7 | 1306 | return -ENOMEM; |
d38ceaf9 AD |
1307 | |
1308 | if (adev->ip_blocks == NULL) { | |
1309 | DRM_ERROR("No IP blocks found!\n"); | |
1310 | return r; | |
1311 | } | |
1312 | ||
1313 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1314 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1315 | DRM_ERROR("disabled ip block: %d\n", i); | |
8faf0e08 | 1316 | adev->ip_block_status[i].valid = false; |
d38ceaf9 AD |
1317 | } else { |
1318 | if (adev->ip_blocks[i].funcs->early_init) { | |
5fc3aeeb | 1319 | r = adev->ip_blocks[i].funcs->early_init((void *)adev); |
2c1a2784 | 1320 | if (r == -ENOENT) { |
8faf0e08 | 1321 | adev->ip_block_status[i].valid = false; |
2c1a2784 | 1322 | } else if (r) { |
88a907d6 | 1323 | DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1324 | return r; |
2c1a2784 | 1325 | } else { |
8faf0e08 | 1326 | adev->ip_block_status[i].valid = true; |
2c1a2784 | 1327 | } |
974e6b64 | 1328 | } else { |
8faf0e08 | 1329 | adev->ip_block_status[i].valid = true; |
d38ceaf9 | 1330 | } |
d38ceaf9 AD |
1331 | } |
1332 | } | |
1333 | ||
395d1fb9 NH |
1334 | adev->cg_flags &= amdgpu_cg_mask; |
1335 | adev->pg_flags &= amdgpu_pg_mask; | |
1336 | ||
d38ceaf9 AD |
1337 | return 0; |
1338 | } | |
1339 | ||
1340 | static int amdgpu_init(struct amdgpu_device *adev) | |
1341 | { | |
1342 | int i, r; | |
1343 | ||
1344 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1345 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 | 1346 | continue; |
5fc3aeeb | 1347 | r = adev->ip_blocks[i].funcs->sw_init((void *)adev); |
2c1a2784 | 1348 | if (r) { |
822b2cef | 1349 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1350 | return r; |
2c1a2784 | 1351 | } |
8faf0e08 | 1352 | adev->ip_block_status[i].sw = true; |
d38ceaf9 | 1353 | /* need to do gmc hw init early so we can allocate gpu mem */ |
5fc3aeeb | 1354 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1355 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1356 | if (r) { |
1357 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1358 | return r; |
2c1a2784 | 1359 | } |
5fc3aeeb | 1360 | r = adev->ip_blocks[i].funcs->hw_init((void *)adev); |
2c1a2784 AD |
1361 | if (r) { |
1362 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1363 | return r; |
2c1a2784 | 1364 | } |
d38ceaf9 | 1365 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1366 | if (r) { |
1367 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1368 | return r; |
2c1a2784 | 1369 | } |
8faf0e08 | 1370 | adev->ip_block_status[i].hw = true; |
d38ceaf9 AD |
1371 | } |
1372 | } | |
1373 | ||
1374 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1375 | if (!adev->ip_block_status[i].sw) |
d38ceaf9 AD |
1376 | continue; |
1377 | /* gmc hw init is done early */ | |
5fc3aeeb | 1378 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1379 | continue; |
5fc3aeeb | 1380 | r = adev->ip_blocks[i].funcs->hw_init((void *)adev); |
2c1a2784 | 1381 | if (r) { |
822b2cef | 1382 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1383 | return r; |
2c1a2784 | 1384 | } |
8faf0e08 | 1385 | adev->ip_block_status[i].hw = true; |
d38ceaf9 AD |
1386 | } |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1392 | { | |
1393 | int i = 0, r; | |
1394 | ||
1395 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1396 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 | 1397 | continue; |
d38ceaf9 | 1398 | if (adev->ip_blocks[i].funcs->late_init) { |
5fc3aeeb | 1399 | r = adev->ip_blocks[i].funcs->late_init((void *)adev); |
2c1a2784 | 1400 | if (r) { |
822b2cef | 1401 | DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1402 | return r; |
2c1a2784 | 1403 | } |
8a2eef1d | 1404 | adev->ip_block_status[i].late_initialized = true; |
d38ceaf9 | 1405 | } |
4a446d55 AD |
1406 | /* skip CG for VCE/UVD, it's handled specially */ |
1407 | if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD && | |
1408 | adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) { | |
1409 | /* enable clockgating to save power */ | |
1410 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, | |
1411 | AMD_CG_STATE_GATE); | |
1412 | if (r) { | |
1413 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
1414 | adev->ip_blocks[i].funcs->name, r); | |
1415 | return r; | |
1416 | } | |
b0b00ff1 | 1417 | } |
d38ceaf9 AD |
1418 | } |
1419 | ||
1420 | return 0; | |
1421 | } | |
1422 | ||
1423 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1424 | { | |
1425 | int i, r; | |
1426 | ||
3e96dbfd AD |
1427 | /* need to disable SMC first */ |
1428 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1429 | if (!adev->ip_block_status[i].hw) | |
1430 | continue; | |
1431 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) { | |
1432 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1433 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, | |
1434 | AMD_CG_STATE_UNGATE); | |
1435 | if (r) { | |
1436 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1437 | adev->ip_blocks[i].funcs->name, r); | |
1438 | return r; | |
1439 | } | |
1440 | r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); | |
1441 | /* XXX handle errors */ | |
1442 | if (r) { | |
1443 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
1444 | adev->ip_blocks[i].funcs->name, r); | |
1445 | } | |
1446 | adev->ip_block_status[i].hw = false; | |
1447 | break; | |
1448 | } | |
1449 | } | |
1450 | ||
d38ceaf9 | 1451 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
8faf0e08 | 1452 | if (!adev->ip_block_status[i].hw) |
d38ceaf9 | 1453 | continue; |
5fc3aeeb | 1454 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1455 | amdgpu_wb_fini(adev); |
1456 | amdgpu_vram_scratch_fini(adev); | |
1457 | } | |
1458 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
5fc3aeeb | 1459 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
1460 | AMD_CG_STATE_UNGATE); | |
2c1a2784 | 1461 | if (r) { |
822b2cef | 1462 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1463 | return r; |
2c1a2784 | 1464 | } |
5fc3aeeb | 1465 | r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); |
d38ceaf9 | 1466 | /* XXX handle errors */ |
2c1a2784 | 1467 | if (r) { |
822b2cef | 1468 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1469 | } |
8faf0e08 | 1470 | adev->ip_block_status[i].hw = false; |
d38ceaf9 AD |
1471 | } |
1472 | ||
1473 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
8faf0e08 | 1474 | if (!adev->ip_block_status[i].sw) |
d38ceaf9 | 1475 | continue; |
5fc3aeeb | 1476 | r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); |
d38ceaf9 | 1477 | /* XXX handle errors */ |
2c1a2784 | 1478 | if (r) { |
822b2cef | 1479 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1480 | } |
8faf0e08 AD |
1481 | adev->ip_block_status[i].sw = false; |
1482 | adev->ip_block_status[i].valid = false; | |
d38ceaf9 AD |
1483 | } |
1484 | ||
a6dcfd9c | 1485 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
8a2eef1d GI |
1486 | if (!adev->ip_block_status[i].late_initialized) |
1487 | continue; | |
a6dcfd9c ML |
1488 | if (adev->ip_blocks[i].funcs->late_fini) |
1489 | adev->ip_blocks[i].funcs->late_fini((void *)adev); | |
8a2eef1d | 1490 | adev->ip_block_status[i].late_initialized = false; |
a6dcfd9c ML |
1491 | } |
1492 | ||
d38ceaf9 AD |
1493 | return 0; |
1494 | } | |
1495 | ||
1496 | static int amdgpu_suspend(struct amdgpu_device *adev) | |
1497 | { | |
1498 | int i, r; | |
1499 | ||
c5a93a28 FC |
1500 | /* ungate SMC block first */ |
1501 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1502 | AMD_CG_STATE_UNGATE); | |
1503 | if (r) { | |
1504 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1505 | } | |
1506 | ||
d38ceaf9 | 1507 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
8faf0e08 | 1508 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1509 | continue; |
1510 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 FC |
1511 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
1512 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, | |
1513 | AMD_CG_STATE_UNGATE); | |
1514 | if (r) { | |
822b2cef | 1515 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
c5a93a28 | 1516 | } |
2c1a2784 | 1517 | } |
d38ceaf9 AD |
1518 | /* XXX handle errors */ |
1519 | r = adev->ip_blocks[i].funcs->suspend(adev); | |
1520 | /* XXX handle errors */ | |
2c1a2784 | 1521 | if (r) { |
822b2cef | 1522 | DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1523 | } |
d38ceaf9 AD |
1524 | } |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | static int amdgpu_resume(struct amdgpu_device *adev) | |
1530 | { | |
1531 | int i, r; | |
1532 | ||
1533 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1534 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1535 | continue; |
1536 | r = adev->ip_blocks[i].funcs->resume(adev); | |
2c1a2784 | 1537 | if (r) { |
822b2cef | 1538 | DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1539 | return r; |
2c1a2784 | 1540 | } |
d38ceaf9 AD |
1541 | } |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
4e99a44e | 1546 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1547 | { |
4e99a44e ML |
1548 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) |
1549 | adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
048765ad AR |
1550 | } |
1551 | ||
d38ceaf9 AD |
1552 | /** |
1553 | * amdgpu_device_init - initialize the driver | |
1554 | * | |
1555 | * @adev: amdgpu_device pointer | |
1556 | * @pdev: drm dev pointer | |
1557 | * @pdev: pci dev pointer | |
1558 | * @flags: driver flags | |
1559 | * | |
1560 | * Initializes the driver info and hw (all asics). | |
1561 | * Returns 0 for success or an error on failure. | |
1562 | * Called at driver startup. | |
1563 | */ | |
1564 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1565 | struct drm_device *ddev, | |
1566 | struct pci_dev *pdev, | |
1567 | uint32_t flags) | |
1568 | { | |
1569 | int r, i; | |
1570 | bool runtime = false; | |
95844d20 | 1571 | u32 max_MBps; |
d38ceaf9 AD |
1572 | |
1573 | adev->shutdown = false; | |
1574 | adev->dev = &pdev->dev; | |
1575 | adev->ddev = ddev; | |
1576 | adev->pdev = pdev; | |
1577 | adev->flags = flags; | |
2f7d10b3 | 1578 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1579 | adev->is_atom_bios = false; |
1580 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; | |
1581 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1582 | adev->accel_working = false; | |
1583 | adev->num_rings = 0; | |
1584 | adev->mman.buffer_funcs = NULL; | |
1585 | adev->mman.buffer_funcs_ring = NULL; | |
1586 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1587 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 AD |
1588 | adev->gart.gart_funcs = NULL; |
1589 | adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); | |
1590 | ||
1591 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1592 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1593 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1594 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
1595 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
1596 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1597 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
1598 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1599 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1600 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
1601 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
1602 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1603 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
1604 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1605 | ||
ccdbb20a | 1606 | |
3e39ab90 AD |
1607 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1608 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1609 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1610 | |
1611 | /* mutex initialization are all done here so we | |
1612 | * can recall function without having locking issues */ | |
8d0a7cea | 1613 | mutex_init(&adev->vm_manager.lock); |
d38ceaf9 | 1614 | atomic_set(&adev->irq.ih.lock, 0); |
d38ceaf9 AD |
1615 | mutex_init(&adev->pm.mutex); |
1616 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1617 | mutex_init(&adev->srbm_mutex); | |
1618 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
1619 | mutex_init(&adev->mn_lock); |
1620 | hash_init(adev->mn_hash); | |
1621 | ||
1622 | amdgpu_check_arguments(adev); | |
1623 | ||
1624 | /* Registers mapping */ | |
1625 | /* TODO: block userspace mapping of io register */ | |
1626 | spin_lock_init(&adev->mmio_idx_lock); | |
1627 | spin_lock_init(&adev->smc_idx_lock); | |
1628 | spin_lock_init(&adev->pcie_idx_lock); | |
1629 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1630 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 1631 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 1632 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 1633 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 1634 | |
0c4e7fa5 CZ |
1635 | INIT_LIST_HEAD(&adev->shadow_list); |
1636 | mutex_init(&adev->shadow_list_lock); | |
1637 | ||
5c1354bd CZ |
1638 | INIT_LIST_HEAD(&adev->gtt_list); |
1639 | spin_lock_init(&adev->gtt_list_lock); | |
1640 | ||
da69c161 KW |
1641 | if (adev->asic_type >= CHIP_BONAIRE) { |
1642 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1643 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1644 | } else { | |
1645 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
1646 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
1647 | } | |
d38ceaf9 | 1648 | |
d38ceaf9 AD |
1649 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
1650 | if (adev->rmmio == NULL) { | |
1651 | return -ENOMEM; | |
1652 | } | |
1653 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1654 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1655 | ||
da69c161 KW |
1656 | if (adev->asic_type >= CHIP_BONAIRE) |
1657 | /* doorbell bar mapping */ | |
1658 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
1659 | |
1660 | /* io port mapping */ | |
1661 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1662 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1663 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1664 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1665 | break; | |
1666 | } | |
1667 | } | |
1668 | if (adev->rio_mem == NULL) | |
1669 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
1670 | ||
1671 | /* early init functions */ | |
1672 | r = amdgpu_early_init(adev); | |
1673 | if (r) | |
1674 | return r; | |
1675 | ||
1676 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1677 | /* this will fail for cards that aren't VGA class devices, just | |
1678 | * ignore it */ | |
1679 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1680 | ||
1681 | if (amdgpu_runtime_pm == 1) | |
1682 | runtime = true; | |
e9bef455 | 1683 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 AD |
1684 | runtime = true; |
1685 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1686 | if (runtime) | |
1687 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1688 | ||
1689 | /* Read BIOS */ | |
83ba126a AD |
1690 | if (!amdgpu_get_bios(adev)) { |
1691 | r = -EINVAL; | |
1692 | goto failed; | |
1693 | } | |
d38ceaf9 AD |
1694 | /* Must be an ATOMBIOS */ |
1695 | if (!adev->is_atom_bios) { | |
1696 | dev_err(adev->dev, "Expecting atombios for GPU\n"); | |
83ba126a AD |
1697 | r = -EINVAL; |
1698 | goto failed; | |
d38ceaf9 AD |
1699 | } |
1700 | r = amdgpu_atombios_init(adev); | |
2c1a2784 AD |
1701 | if (r) { |
1702 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 1703 | goto failed; |
2c1a2784 | 1704 | } |
d38ceaf9 | 1705 | |
4e99a44e ML |
1706 | /* detect if we are with an SRIOV vbios */ |
1707 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 1708 | |
d38ceaf9 | 1709 | /* Post card if necessary */ |
bec86378 | 1710 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 1711 | if (!adev->bios) { |
bec86378 | 1712 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
1713 | r = -EINVAL; |
1714 | goto failed; | |
d38ceaf9 | 1715 | } |
bec86378 | 1716 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
1717 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
1718 | if (r) { | |
1719 | dev_err(adev->dev, "gpu post error!\n"); | |
1720 | goto failed; | |
1721 | } | |
1722 | } else { | |
1723 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
1724 | } |
1725 | ||
1726 | /* Initialize clocks */ | |
1727 | r = amdgpu_atombios_get_clock_info(adev); | |
2c1a2784 AD |
1728 | if (r) { |
1729 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
83ba126a | 1730 | goto failed; |
2c1a2784 | 1731 | } |
d38ceaf9 AD |
1732 | /* init i2c buses */ |
1733 | amdgpu_atombios_i2c_init(adev); | |
1734 | ||
1735 | /* Fence driver */ | |
1736 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1737 | if (r) { |
1738 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 1739 | goto failed; |
2c1a2784 | 1740 | } |
d38ceaf9 AD |
1741 | |
1742 | /* init the mode config */ | |
1743 | drm_mode_config_init(adev->ddev); | |
1744 | ||
1745 | r = amdgpu_init(adev); | |
1746 | if (r) { | |
2c1a2784 | 1747 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 1748 | amdgpu_fini(adev); |
83ba126a | 1749 | goto failed; |
d38ceaf9 AD |
1750 | } |
1751 | ||
1752 | adev->accel_working = true; | |
1753 | ||
95844d20 MO |
1754 | /* Initialize the buffer migration limit. */ |
1755 | if (amdgpu_moverate >= 0) | |
1756 | max_MBps = amdgpu_moverate; | |
1757 | else | |
1758 | max_MBps = 8; /* Allow 8 MB/s. */ | |
1759 | /* Get a log2 for easy divisions. */ | |
1760 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
1761 | ||
d38ceaf9 AD |
1762 | amdgpu_fbdev_init(adev); |
1763 | ||
1764 | r = amdgpu_ib_pool_init(adev); | |
1765 | if (r) { | |
1766 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 1767 | goto failed; |
d38ceaf9 AD |
1768 | } |
1769 | ||
1770 | r = amdgpu_ib_ring_tests(adev); | |
1771 | if (r) | |
1772 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1773 | ||
1774 | r = amdgpu_gem_debugfs_init(adev); | |
1775 | if (r) { | |
1776 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); | |
1777 | } | |
1778 | ||
1779 | r = amdgpu_debugfs_regs_init(adev); | |
1780 | if (r) { | |
1781 | DRM_ERROR("registering register debugfs failed (%d).\n", r); | |
1782 | } | |
1783 | ||
50ab2533 HR |
1784 | r = amdgpu_debugfs_firmware_init(adev); |
1785 | if (r) { | |
1786 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); | |
1787 | return r; | |
1788 | } | |
1789 | ||
d38ceaf9 AD |
1790 | if ((amdgpu_testing & 1)) { |
1791 | if (adev->accel_working) | |
1792 | amdgpu_test_moves(adev); | |
1793 | else | |
1794 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
1795 | } | |
1796 | if ((amdgpu_testing & 2)) { | |
1797 | if (adev->accel_working) | |
1798 | amdgpu_test_syncing(adev); | |
1799 | else | |
1800 | DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); | |
1801 | } | |
1802 | if (amdgpu_benchmarking) { | |
1803 | if (adev->accel_working) | |
1804 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
1805 | else | |
1806 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
1807 | } | |
1808 | ||
1809 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
1810 | * explicit gating rather than handling it automatically. | |
1811 | */ | |
1812 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
1813 | if (r) { |
1814 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 1815 | goto failed; |
2c1a2784 | 1816 | } |
d38ceaf9 AD |
1817 | |
1818 | return 0; | |
83ba126a AD |
1819 | |
1820 | failed: | |
1821 | if (runtime) | |
1822 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
1823 | return r; | |
d38ceaf9 AD |
1824 | } |
1825 | ||
1826 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev); | |
1827 | ||
1828 | /** | |
1829 | * amdgpu_device_fini - tear down the driver | |
1830 | * | |
1831 | * @adev: amdgpu_device pointer | |
1832 | * | |
1833 | * Tear down the driver info (all asics). | |
1834 | * Called at driver shutdown. | |
1835 | */ | |
1836 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
1837 | { | |
1838 | int r; | |
1839 | ||
1840 | DRM_INFO("amdgpu: finishing device.\n"); | |
1841 | adev->shutdown = true; | |
a951ed85 | 1842 | drm_crtc_force_disable_all(adev->ddev); |
d38ceaf9 AD |
1843 | /* evict vram memory */ |
1844 | amdgpu_bo_evict_vram(adev); | |
1845 | amdgpu_ib_pool_fini(adev); | |
1846 | amdgpu_fence_driver_fini(adev); | |
1847 | amdgpu_fbdev_fini(adev); | |
1848 | r = amdgpu_fini(adev); | |
8faf0e08 AD |
1849 | kfree(adev->ip_block_status); |
1850 | adev->ip_block_status = NULL; | |
d38ceaf9 AD |
1851 | adev->accel_working = false; |
1852 | /* free i2c buses */ | |
1853 | amdgpu_i2c_fini(adev); | |
1854 | amdgpu_atombios_fini(adev); | |
1855 | kfree(adev->bios); | |
1856 | adev->bios = NULL; | |
1857 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
1858 | if (adev->flags & AMD_IS_PX) |
1859 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
1860 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
1861 | if (adev->rio_mem) | |
1862 | pci_iounmap(adev->pdev, adev->rio_mem); | |
1863 | adev->rio_mem = NULL; | |
1864 | iounmap(adev->rmmio); | |
1865 | adev->rmmio = NULL; | |
da69c161 KW |
1866 | if (adev->asic_type >= CHIP_BONAIRE) |
1867 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 AD |
1868 | amdgpu_debugfs_regs_cleanup(adev); |
1869 | amdgpu_debugfs_remove_files(adev); | |
1870 | } | |
1871 | ||
1872 | ||
1873 | /* | |
1874 | * Suspend & resume. | |
1875 | */ | |
1876 | /** | |
810ddc3a | 1877 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
1878 | * |
1879 | * @pdev: drm dev pointer | |
1880 | * @state: suspend state | |
1881 | * | |
1882 | * Puts the hw in the suspend state (all asics). | |
1883 | * Returns 0 for success or an error on failure. | |
1884 | * Called at driver suspend. | |
1885 | */ | |
810ddc3a | 1886 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
1887 | { |
1888 | struct amdgpu_device *adev; | |
1889 | struct drm_crtc *crtc; | |
1890 | struct drm_connector *connector; | |
5ceb54c6 | 1891 | int r; |
d38ceaf9 AD |
1892 | |
1893 | if (dev == NULL || dev->dev_private == NULL) { | |
1894 | return -ENODEV; | |
1895 | } | |
1896 | ||
1897 | adev = dev->dev_private; | |
1898 | ||
1899 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1900 | return 0; | |
1901 | ||
1902 | drm_kms_helper_poll_disable(dev); | |
1903 | ||
1904 | /* turn off display hw */ | |
4c7fbc39 | 1905 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
1906 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1907 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
1908 | } | |
4c7fbc39 | 1909 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 1910 | |
756e6880 | 1911 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 1912 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 1913 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
1914 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
1915 | struct amdgpu_bo *robj; | |
1916 | ||
756e6880 AD |
1917 | if (amdgpu_crtc->cursor_bo) { |
1918 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
1919 | r = amdgpu_bo_reserve(aobj, false); | |
1920 | if (r == 0) { | |
1921 | amdgpu_bo_unpin(aobj); | |
1922 | amdgpu_bo_unreserve(aobj); | |
1923 | } | |
1924 | } | |
1925 | ||
d38ceaf9 AD |
1926 | if (rfb == NULL || rfb->obj == NULL) { |
1927 | continue; | |
1928 | } | |
1929 | robj = gem_to_amdgpu_bo(rfb->obj); | |
1930 | /* don't unpin kernel fb objects */ | |
1931 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
1932 | r = amdgpu_bo_reserve(robj, false); | |
1933 | if (r == 0) { | |
1934 | amdgpu_bo_unpin(robj); | |
1935 | amdgpu_bo_unreserve(robj); | |
1936 | } | |
1937 | } | |
1938 | } | |
1939 | /* evict vram memory */ | |
1940 | amdgpu_bo_evict_vram(adev); | |
1941 | ||
5ceb54c6 | 1942 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
1943 | |
1944 | r = amdgpu_suspend(adev); | |
1945 | ||
1946 | /* evict remaining vram memory */ | |
1947 | amdgpu_bo_evict_vram(adev); | |
1948 | ||
e695e77c | 1949 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
1950 | pci_save_state(dev->pdev); |
1951 | if (suspend) { | |
1952 | /* Shut down the device */ | |
1953 | pci_disable_device(dev->pdev); | |
1954 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 1955 | } else { |
1956 | r = amdgpu_asic_reset(adev); | |
1957 | if (r) | |
1958 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
1959 | } |
1960 | ||
1961 | if (fbcon) { | |
1962 | console_lock(); | |
1963 | amdgpu_fbdev_set_suspend(adev, 1); | |
1964 | console_unlock(); | |
1965 | } | |
1966 | return 0; | |
1967 | } | |
1968 | ||
1969 | /** | |
810ddc3a | 1970 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
1971 | * |
1972 | * @pdev: drm dev pointer | |
1973 | * | |
1974 | * Bring the hw back to operating state (all asics). | |
1975 | * Returns 0 for success or an error on failure. | |
1976 | * Called at driver resume. | |
1977 | */ | |
810ddc3a | 1978 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
1979 | { |
1980 | struct drm_connector *connector; | |
1981 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 1982 | struct drm_crtc *crtc; |
d38ceaf9 AD |
1983 | int r; |
1984 | ||
1985 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1986 | return 0; | |
1987 | ||
74b0b157 | 1988 | if (fbcon) |
d38ceaf9 | 1989 | console_lock(); |
74b0b157 | 1990 | |
d38ceaf9 AD |
1991 | if (resume) { |
1992 | pci_set_power_state(dev->pdev, PCI_D0); | |
1993 | pci_restore_state(dev->pdev); | |
74b0b157 | 1994 | r = pci_enable_device(dev->pdev); |
1995 | if (r) { | |
d38ceaf9 AD |
1996 | if (fbcon) |
1997 | console_unlock(); | |
74b0b157 | 1998 | return r; |
d38ceaf9 AD |
1999 | } |
2000 | } | |
e695e77c | 2001 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2002 | |
2003 | /* post card */ | |
74b0b157 | 2004 | if (!amdgpu_card_posted(adev) || !resume) { |
2005 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2006 | if (r) | |
2007 | DRM_ERROR("amdgpu asic init failed\n"); | |
2008 | } | |
d38ceaf9 AD |
2009 | |
2010 | r = amdgpu_resume(adev); | |
ca198528 FC |
2011 | if (r) |
2012 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); | |
d38ceaf9 | 2013 | |
5ceb54c6 AD |
2014 | amdgpu_fence_driver_resume(adev); |
2015 | ||
ca198528 FC |
2016 | if (resume) { |
2017 | r = amdgpu_ib_ring_tests(adev); | |
2018 | if (r) | |
2019 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2020 | } | |
d38ceaf9 AD |
2021 | |
2022 | r = amdgpu_late_init(adev); | |
2023 | if (r) | |
2024 | return r; | |
2025 | ||
756e6880 AD |
2026 | /* pin cursors */ |
2027 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2028 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2029 | ||
2030 | if (amdgpu_crtc->cursor_bo) { | |
2031 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2032 | r = amdgpu_bo_reserve(aobj, false); | |
2033 | if (r == 0) { | |
2034 | r = amdgpu_bo_pin(aobj, | |
2035 | AMDGPU_GEM_DOMAIN_VRAM, | |
2036 | &amdgpu_crtc->cursor_addr); | |
2037 | if (r != 0) | |
2038 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2039 | amdgpu_bo_unreserve(aobj); | |
2040 | } | |
2041 | } | |
2042 | } | |
2043 | ||
d38ceaf9 AD |
2044 | /* blat the mode back in */ |
2045 | if (fbcon) { | |
2046 | drm_helper_resume_force_mode(dev); | |
2047 | /* turn on display hw */ | |
4c7fbc39 | 2048 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2049 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2050 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2051 | } | |
4c7fbc39 | 2052 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2053 | } |
2054 | ||
2055 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2056 | |
2057 | /* | |
2058 | * Most of the connector probing functions try to acquire runtime pm | |
2059 | * refs to ensure that the GPU is powered on when connector polling is | |
2060 | * performed. Since we're calling this from a runtime PM callback, | |
2061 | * trying to acquire rpm refs will cause us to deadlock. | |
2062 | * | |
2063 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2064 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2065 | */ | |
2066 | #ifdef CONFIG_PM | |
2067 | dev->dev->power.disable_depth++; | |
2068 | #endif | |
54fb2a5c | 2069 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2070 | #ifdef CONFIG_PM |
2071 | dev->dev->power.disable_depth--; | |
2072 | #endif | |
d38ceaf9 AD |
2073 | |
2074 | if (fbcon) { | |
2075 | amdgpu_fbdev_set_suspend(adev, 0); | |
2076 | console_unlock(); | |
2077 | } | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
63fbf42f CZ |
2082 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2083 | { | |
2084 | int i; | |
2085 | bool asic_hang = false; | |
2086 | ||
2087 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2088 | if (!adev->ip_block_status[i].valid) | |
2089 | continue; | |
2090 | if (adev->ip_blocks[i].funcs->check_soft_reset) | |
da146d3b AD |
2091 | adev->ip_block_status[i].hang = |
2092 | adev->ip_blocks[i].funcs->check_soft_reset(adev); | |
63fbf42f CZ |
2093 | if (adev->ip_block_status[i].hang) { |
2094 | DRM_INFO("IP block:%d is hang!\n", i); | |
2095 | asic_hang = true; | |
2096 | } | |
2097 | } | |
2098 | return asic_hang; | |
2099 | } | |
2100 | ||
4d446656 | 2101 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2102 | { |
2103 | int i, r = 0; | |
2104 | ||
2105 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2106 | if (!adev->ip_block_status[i].valid) | |
2107 | continue; | |
35d782fe CZ |
2108 | if (adev->ip_block_status[i].hang && |
2109 | adev->ip_blocks[i].funcs->pre_soft_reset) { | |
d31a501e CZ |
2110 | r = adev->ip_blocks[i].funcs->pre_soft_reset(adev); |
2111 | if (r) | |
2112 | return r; | |
2113 | } | |
2114 | } | |
2115 | ||
2116 | return 0; | |
2117 | } | |
2118 | ||
35d782fe CZ |
2119 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2120 | { | |
da146d3b AD |
2121 | int i; |
2122 | ||
2123 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2124 | if (!adev->ip_block_status[i].valid) | |
2125 | continue; | |
2126 | if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) || | |
2127 | (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) || | |
2128 | (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) || | |
2129 | (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2130 | if (adev->ip_block_status[i].hang) { | |
2131 | DRM_INFO("Some block need full reset!\n"); | |
2132 | return true; | |
2133 | } | |
2134 | } | |
35d782fe CZ |
2135 | } |
2136 | return false; | |
2137 | } | |
2138 | ||
2139 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2140 | { | |
2141 | int i, r = 0; | |
2142 | ||
2143 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2144 | if (!adev->ip_block_status[i].valid) | |
2145 | continue; | |
2146 | if (adev->ip_block_status[i].hang && | |
2147 | adev->ip_blocks[i].funcs->soft_reset) { | |
2148 | r = adev->ip_blocks[i].funcs->soft_reset(adev); | |
2149 | if (r) | |
2150 | return r; | |
2151 | } | |
2152 | } | |
2153 | ||
2154 | return 0; | |
2155 | } | |
2156 | ||
2157 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2158 | { | |
2159 | int i, r = 0; | |
2160 | ||
2161 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2162 | if (!adev->ip_block_status[i].valid) | |
2163 | continue; | |
2164 | if (adev->ip_block_status[i].hang && | |
2165 | adev->ip_blocks[i].funcs->post_soft_reset) | |
2166 | r = adev->ip_blocks[i].funcs->post_soft_reset(adev); | |
2167 | if (r) | |
2168 | return r; | |
2169 | } | |
2170 | ||
2171 | return 0; | |
2172 | } | |
2173 | ||
3ad81f16 CZ |
2174 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2175 | { | |
2176 | if (adev->flags & AMD_IS_APU) | |
2177 | return false; | |
2178 | ||
2179 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2180 | } | |
2181 | ||
53cdccd5 CZ |
2182 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2183 | struct amdgpu_ring *ring, | |
2184 | struct amdgpu_bo *bo, | |
2185 | struct fence **fence) | |
2186 | { | |
2187 | uint32_t domain; | |
2188 | int r; | |
2189 | ||
2190 | if (!bo->shadow) | |
2191 | return 0; | |
2192 | ||
2193 | r = amdgpu_bo_reserve(bo, false); | |
2194 | if (r) | |
2195 | return r; | |
2196 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2197 | /* if bo has been evicted, then no need to recover */ | |
2198 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
2199 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, | |
2200 | NULL, fence, true); | |
2201 | if (r) { | |
2202 | DRM_ERROR("recover page table failed!\n"); | |
2203 | goto err; | |
2204 | } | |
2205 | } | |
2206 | err: | |
2207 | amdgpu_bo_unreserve(bo); | |
2208 | return r; | |
2209 | } | |
2210 | ||
d38ceaf9 AD |
2211 | /** |
2212 | * amdgpu_gpu_reset - reset the asic | |
2213 | * | |
2214 | * @adev: amdgpu device pointer | |
2215 | * | |
2216 | * Attempt the reset the GPU if it has hung (all asics). | |
2217 | * Returns 0 for success or an error on failure. | |
2218 | */ | |
2219 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2220 | { | |
d38ceaf9 AD |
2221 | int i, r; |
2222 | int resched; | |
35d782fe | 2223 | bool need_full_reset; |
d38ceaf9 | 2224 | |
63fbf42f CZ |
2225 | if (!amdgpu_check_soft_reset(adev)) { |
2226 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2227 | return 0; | |
2228 | } | |
d38ceaf9 | 2229 | |
d94aed5a | 2230 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2231 | |
a3c47d6b CZ |
2232 | /* block TTM */ |
2233 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2234 | ||
0875dc9e CZ |
2235 | /* block scheduler */ |
2236 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2237 | struct amdgpu_ring *ring = adev->rings[i]; | |
2238 | ||
2239 | if (!ring) | |
2240 | continue; | |
2241 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2242 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2243 | } |
2200edac CZ |
2244 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2245 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2246 | |
35d782fe | 2247 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2248 | |
35d782fe CZ |
2249 | if (!need_full_reset) { |
2250 | amdgpu_pre_soft_reset(adev); | |
2251 | r = amdgpu_soft_reset(adev); | |
2252 | amdgpu_post_soft_reset(adev); | |
2253 | if (r || amdgpu_check_soft_reset(adev)) { | |
2254 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2255 | need_full_reset = true; | |
2256 | } | |
f1aa7e08 CZ |
2257 | } |
2258 | ||
35d782fe | 2259 | if (need_full_reset) { |
35d782fe | 2260 | r = amdgpu_suspend(adev); |
bfa99269 | 2261 | |
35d782fe CZ |
2262 | retry: |
2263 | /* Disable fb access */ | |
2264 | if (adev->mode_info.num_crtc) { | |
2265 | struct amdgpu_mode_mc_save save; | |
2266 | amdgpu_display_stop_mc_access(adev, &save); | |
2267 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
2268 | } | |
e695e77c | 2269 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2270 | r = amdgpu_asic_reset(adev); |
e695e77c | 2271 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2272 | /* post card */ |
2273 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2274 | ||
2275 | if (!r) { | |
2276 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
2277 | r = amdgpu_resume(adev); | |
2278 | } | |
d38ceaf9 | 2279 | } |
d38ceaf9 | 2280 | if (!r) { |
e72cfd58 | 2281 | amdgpu_irq_gpu_reset_resume_helper(adev); |
2c0d7318 CZ |
2282 | if (need_full_reset && amdgpu_need_backup(adev)) { |
2283 | r = amdgpu_ttm_recover_gart(adev); | |
2284 | if (r) | |
2285 | DRM_ERROR("gart recovery failed!!!\n"); | |
2286 | } | |
1f465087 CZ |
2287 | r = amdgpu_ib_ring_tests(adev); |
2288 | if (r) { | |
2289 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2290 | r = amdgpu_suspend(adev); |
53cdccd5 | 2291 | need_full_reset = true; |
40019dc4 | 2292 | goto retry; |
1f465087 | 2293 | } |
53cdccd5 CZ |
2294 | /** |
2295 | * recovery vm page tables, since we cannot depend on VRAM is | |
2296 | * consistent after gpu full reset. | |
2297 | */ | |
2298 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2299 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2300 | struct amdgpu_bo *bo, *tmp; | |
2301 | struct fence *fence = NULL, *next = NULL; | |
2302 | ||
2303 | DRM_INFO("recover vram bo from shadow\n"); | |
2304 | mutex_lock(&adev->shadow_list_lock); | |
2305 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2306 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); | |
2307 | if (fence) { | |
2308 | r = fence_wait(fence, false); | |
2309 | if (r) { | |
2310 | WARN(r, "recovery from shadow isn't comleted\n"); | |
2311 | break; | |
2312 | } | |
2313 | } | |
1f465087 | 2314 | |
53cdccd5 CZ |
2315 | fence_put(fence); |
2316 | fence = next; | |
2317 | } | |
2318 | mutex_unlock(&adev->shadow_list_lock); | |
2319 | if (fence) { | |
2320 | r = fence_wait(fence, false); | |
2321 | if (r) | |
2322 | WARN(r, "recovery from shadow isn't comleted\n"); | |
2323 | } | |
2324 | fence_put(fence); | |
2325 | } | |
d38ceaf9 AD |
2326 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2327 | struct amdgpu_ring *ring = adev->rings[i]; | |
2328 | if (!ring) | |
2329 | continue; | |
53cdccd5 | 2330 | |
aa1c8900 | 2331 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2332 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2333 | } |
d38ceaf9 | 2334 | } else { |
2200edac | 2335 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2336 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
0875dc9e CZ |
2337 | if (adev->rings[i]) { |
2338 | kthread_unpark(adev->rings[i]->sched.thread); | |
0875dc9e | 2339 | } |
d38ceaf9 AD |
2340 | } |
2341 | } | |
2342 | ||
2343 | drm_helper_resume_force_mode(adev->ddev); | |
2344 | ||
2345 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2346 | if (r) { | |
2347 | /* bad news, how to tell it to userspace ? */ | |
2348 | dev_info(adev->dev, "GPU reset failed\n"); | |
2349 | } | |
2350 | ||
d38ceaf9 AD |
2351 | return r; |
2352 | } | |
2353 | ||
d0dd7f0c AD |
2354 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2355 | { | |
2356 | u32 mask; | |
2357 | int ret; | |
2358 | ||
cd474ba0 AD |
2359 | if (amdgpu_pcie_gen_cap) |
2360 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2361 | |
cd474ba0 AD |
2362 | if (amdgpu_pcie_lane_cap) |
2363 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2364 | |
cd474ba0 AD |
2365 | /* covers APUs as well */ |
2366 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2367 | if (adev->pm.pcie_gen_mask == 0) | |
2368 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2369 | if (adev->pm.pcie_mlw_mask == 0) | |
2370 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2371 | return; |
cd474ba0 | 2372 | } |
d0dd7f0c | 2373 | |
cd474ba0 AD |
2374 | if (adev->pm.pcie_gen_mask == 0) { |
2375 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2376 | if (!ret) { | |
2377 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2378 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2379 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2380 | ||
2381 | if (mask & DRM_PCIE_SPEED_25) | |
2382 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2383 | if (mask & DRM_PCIE_SPEED_50) | |
2384 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2385 | if (mask & DRM_PCIE_SPEED_80) | |
2386 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2387 | } else { | |
2388 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2389 | } | |
2390 | } | |
2391 | if (adev->pm.pcie_mlw_mask == 0) { | |
2392 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2393 | if (!ret) { | |
2394 | switch (mask) { | |
2395 | case 32: | |
2396 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2397 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2398 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2399 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2400 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2401 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2402 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2403 | break; | |
2404 | case 16: | |
2405 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2406 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2407 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2408 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2409 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2410 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2411 | break; | |
2412 | case 12: | |
2413 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2414 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2415 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2416 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2417 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2418 | break; | |
2419 | case 8: | |
2420 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2421 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2422 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2423 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2424 | break; | |
2425 | case 4: | |
2426 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2427 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2428 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2429 | break; | |
2430 | case 2: | |
2431 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2432 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2433 | break; | |
2434 | case 1: | |
2435 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2436 | break; | |
2437 | default: | |
2438 | break; | |
2439 | } | |
2440 | } else { | |
2441 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2442 | } |
2443 | } | |
2444 | } | |
d38ceaf9 AD |
2445 | |
2446 | /* | |
2447 | * Debugfs | |
2448 | */ | |
2449 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 2450 | const struct drm_info_list *files, |
d38ceaf9 AD |
2451 | unsigned nfiles) |
2452 | { | |
2453 | unsigned i; | |
2454 | ||
2455 | for (i = 0; i < adev->debugfs_count; i++) { | |
2456 | if (adev->debugfs[i].files == files) { | |
2457 | /* Already registered */ | |
2458 | return 0; | |
2459 | } | |
2460 | } | |
2461 | ||
2462 | i = adev->debugfs_count + 1; | |
2463 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
2464 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
2465 | DRM_ERROR("Report so we increase " | |
2466 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
2467 | return -EINVAL; | |
2468 | } | |
2469 | adev->debugfs[adev->debugfs_count].files = files; | |
2470 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
2471 | adev->debugfs_count = i; | |
2472 | #if defined(CONFIG_DEBUG_FS) | |
2473 | drm_debugfs_create_files(files, nfiles, | |
2474 | adev->ddev->control->debugfs_root, | |
2475 | adev->ddev->control); | |
2476 | drm_debugfs_create_files(files, nfiles, | |
2477 | adev->ddev->primary->debugfs_root, | |
2478 | adev->ddev->primary); | |
2479 | #endif | |
2480 | return 0; | |
2481 | } | |
2482 | ||
2483 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) | |
2484 | { | |
2485 | #if defined(CONFIG_DEBUG_FS) | |
2486 | unsigned i; | |
2487 | ||
2488 | for (i = 0; i < adev->debugfs_count; i++) { | |
2489 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2490 | adev->debugfs[i].num_files, | |
2491 | adev->ddev->control); | |
2492 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2493 | adev->debugfs[i].num_files, | |
2494 | adev->ddev->primary); | |
2495 | } | |
2496 | #endif | |
2497 | } | |
2498 | ||
2499 | #if defined(CONFIG_DEBUG_FS) | |
2500 | ||
2501 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
2502 | size_t size, loff_t *pos) | |
2503 | { | |
2504 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2505 | ssize_t result = 0; | |
2506 | int r; | |
bd12267d | 2507 | bool pm_pg_lock, use_bank; |
56628159 | 2508 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
2509 | |
2510 | if (size & 0x3 || *pos & 0x3) | |
2511 | return -EINVAL; | |
2512 | ||
bd12267d TSD |
2513 | /* are we reading registers for which a PG lock is necessary? */ |
2514 | pm_pg_lock = (*pos >> 23) & 1; | |
2515 | ||
56628159 TSD |
2516 | if (*pos & (1ULL << 62)) { |
2517 | se_bank = (*pos >> 24) & 0x3FF; | |
2518 | sh_bank = (*pos >> 34) & 0x3FF; | |
2519 | instance_bank = (*pos >> 44) & 0x3FF; | |
2520 | use_bank = 1; | |
56628159 TSD |
2521 | } else { |
2522 | use_bank = 0; | |
2523 | } | |
2524 | ||
bd12267d TSD |
2525 | *pos &= 0x3FFFF; |
2526 | ||
56628159 TSD |
2527 | if (use_bank) { |
2528 | if (sh_bank >= adev->gfx.config.max_sh_per_se || | |
2529 | se_bank >= adev->gfx.config.max_shader_engines) | |
2530 | return -EINVAL; | |
2531 | mutex_lock(&adev->grbm_idx_mutex); | |
2532 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2533 | sh_bank, instance_bank); | |
2534 | } | |
2535 | ||
bd12267d TSD |
2536 | if (pm_pg_lock) |
2537 | mutex_lock(&adev->pm.mutex); | |
2538 | ||
d38ceaf9 AD |
2539 | while (size) { |
2540 | uint32_t value; | |
2541 | ||
2542 | if (*pos > adev->rmmio_size) | |
56628159 | 2543 | goto end; |
d38ceaf9 AD |
2544 | |
2545 | value = RREG32(*pos >> 2); | |
2546 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
2547 | if (r) { |
2548 | result = r; | |
2549 | goto end; | |
2550 | } | |
d38ceaf9 AD |
2551 | |
2552 | result += 4; | |
2553 | buf += 4; | |
2554 | *pos += 4; | |
2555 | size -= 4; | |
2556 | } | |
2557 | ||
56628159 TSD |
2558 | end: |
2559 | if (use_bank) { | |
2560 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2561 | mutex_unlock(&adev->grbm_idx_mutex); | |
2562 | } | |
2563 | ||
bd12267d TSD |
2564 | if (pm_pg_lock) |
2565 | mutex_unlock(&adev->pm.mutex); | |
2566 | ||
d38ceaf9 AD |
2567 | return result; |
2568 | } | |
2569 | ||
2570 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
2571 | size_t size, loff_t *pos) | |
2572 | { | |
2573 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2574 | ssize_t result = 0; | |
2575 | int r; | |
2576 | ||
2577 | if (size & 0x3 || *pos & 0x3) | |
2578 | return -EINVAL; | |
2579 | ||
2580 | while (size) { | |
2581 | uint32_t value; | |
2582 | ||
2583 | if (*pos > adev->rmmio_size) | |
2584 | return result; | |
2585 | ||
2586 | r = get_user(value, (uint32_t *)buf); | |
2587 | if (r) | |
2588 | return r; | |
2589 | ||
2590 | WREG32(*pos >> 2, value); | |
2591 | ||
2592 | result += 4; | |
2593 | buf += 4; | |
2594 | *pos += 4; | |
2595 | size -= 4; | |
2596 | } | |
2597 | ||
2598 | return result; | |
2599 | } | |
2600 | ||
adcec288 TSD |
2601 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
2602 | size_t size, loff_t *pos) | |
2603 | { | |
2604 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2605 | ssize_t result = 0; | |
2606 | int r; | |
2607 | ||
2608 | if (size & 0x3 || *pos & 0x3) | |
2609 | return -EINVAL; | |
2610 | ||
2611 | while (size) { | |
2612 | uint32_t value; | |
2613 | ||
2614 | value = RREG32_PCIE(*pos >> 2); | |
2615 | r = put_user(value, (uint32_t *)buf); | |
2616 | if (r) | |
2617 | return r; | |
2618 | ||
2619 | result += 4; | |
2620 | buf += 4; | |
2621 | *pos += 4; | |
2622 | size -= 4; | |
2623 | } | |
2624 | ||
2625 | return result; | |
2626 | } | |
2627 | ||
2628 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
2629 | size_t size, loff_t *pos) | |
2630 | { | |
2631 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2632 | ssize_t result = 0; | |
2633 | int r; | |
2634 | ||
2635 | if (size & 0x3 || *pos & 0x3) | |
2636 | return -EINVAL; | |
2637 | ||
2638 | while (size) { | |
2639 | uint32_t value; | |
2640 | ||
2641 | r = get_user(value, (uint32_t *)buf); | |
2642 | if (r) | |
2643 | return r; | |
2644 | ||
2645 | WREG32_PCIE(*pos >> 2, value); | |
2646 | ||
2647 | result += 4; | |
2648 | buf += 4; | |
2649 | *pos += 4; | |
2650 | size -= 4; | |
2651 | } | |
2652 | ||
2653 | return result; | |
2654 | } | |
2655 | ||
2656 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
2657 | size_t size, loff_t *pos) | |
2658 | { | |
2659 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2660 | ssize_t result = 0; | |
2661 | int r; | |
2662 | ||
2663 | if (size & 0x3 || *pos & 0x3) | |
2664 | return -EINVAL; | |
2665 | ||
2666 | while (size) { | |
2667 | uint32_t value; | |
2668 | ||
2669 | value = RREG32_DIDT(*pos >> 2); | |
2670 | r = put_user(value, (uint32_t *)buf); | |
2671 | if (r) | |
2672 | return r; | |
2673 | ||
2674 | result += 4; | |
2675 | buf += 4; | |
2676 | *pos += 4; | |
2677 | size -= 4; | |
2678 | } | |
2679 | ||
2680 | return result; | |
2681 | } | |
2682 | ||
2683 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
2684 | size_t size, loff_t *pos) | |
2685 | { | |
2686 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2687 | ssize_t result = 0; | |
2688 | int r; | |
2689 | ||
2690 | if (size & 0x3 || *pos & 0x3) | |
2691 | return -EINVAL; | |
2692 | ||
2693 | while (size) { | |
2694 | uint32_t value; | |
2695 | ||
2696 | r = get_user(value, (uint32_t *)buf); | |
2697 | if (r) | |
2698 | return r; | |
2699 | ||
2700 | WREG32_DIDT(*pos >> 2, value); | |
2701 | ||
2702 | result += 4; | |
2703 | buf += 4; | |
2704 | *pos += 4; | |
2705 | size -= 4; | |
2706 | } | |
2707 | ||
2708 | return result; | |
2709 | } | |
2710 | ||
2711 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
2712 | size_t size, loff_t *pos) | |
2713 | { | |
2714 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2715 | ssize_t result = 0; | |
2716 | int r; | |
2717 | ||
2718 | if (size & 0x3 || *pos & 0x3) | |
2719 | return -EINVAL; | |
2720 | ||
2721 | while (size) { | |
2722 | uint32_t value; | |
2723 | ||
6fc0deaf | 2724 | value = RREG32_SMC(*pos); |
adcec288 TSD |
2725 | r = put_user(value, (uint32_t *)buf); |
2726 | if (r) | |
2727 | return r; | |
2728 | ||
2729 | result += 4; | |
2730 | buf += 4; | |
2731 | *pos += 4; | |
2732 | size -= 4; | |
2733 | } | |
2734 | ||
2735 | return result; | |
2736 | } | |
2737 | ||
2738 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
2739 | size_t size, loff_t *pos) | |
2740 | { | |
2741 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2742 | ssize_t result = 0; | |
2743 | int r; | |
2744 | ||
2745 | if (size & 0x3 || *pos & 0x3) | |
2746 | return -EINVAL; | |
2747 | ||
2748 | while (size) { | |
2749 | uint32_t value; | |
2750 | ||
2751 | r = get_user(value, (uint32_t *)buf); | |
2752 | if (r) | |
2753 | return r; | |
2754 | ||
6fc0deaf | 2755 | WREG32_SMC(*pos, value); |
adcec288 TSD |
2756 | |
2757 | result += 4; | |
2758 | buf += 4; | |
2759 | *pos += 4; | |
2760 | size -= 4; | |
2761 | } | |
2762 | ||
2763 | return result; | |
2764 | } | |
2765 | ||
1e051413 TSD |
2766 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
2767 | size_t size, loff_t *pos) | |
2768 | { | |
2769 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2770 | ssize_t result = 0; | |
2771 | int r; | |
2772 | uint32_t *config, no_regs = 0; | |
2773 | ||
2774 | if (size & 0x3 || *pos & 0x3) | |
2775 | return -EINVAL; | |
2776 | ||
ecab7668 | 2777 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
2778 | if (!config) |
2779 | return -ENOMEM; | |
2780 | ||
2781 | /* version, increment each time something is added */ | |
e9f11dc8 | 2782 | config[no_regs++] = 2; |
1e051413 TSD |
2783 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
2784 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
2785 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
2786 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
2787 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
2788 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
2789 | config[no_regs++] = adev->gfx.config.max_gprs; | |
2790 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
2791 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
2792 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
2793 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
2794 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
2795 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
2796 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
2797 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
2798 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
2799 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
2800 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
2801 | config[no_regs++] = adev->gfx.config.num_gpus; | |
2802 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
2803 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
2804 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
2805 | config[no_regs++] = adev->gfx.config.num_rbs; | |
2806 | ||
89a8f309 TSD |
2807 | /* rev==1 */ |
2808 | config[no_regs++] = adev->rev_id; | |
2809 | config[no_regs++] = adev->pg_flags; | |
2810 | config[no_regs++] = adev->cg_flags; | |
2811 | ||
e9f11dc8 TSD |
2812 | /* rev==2 */ |
2813 | config[no_regs++] = adev->family; | |
2814 | config[no_regs++] = adev->external_rev_id; | |
2815 | ||
1e051413 TSD |
2816 | while (size && (*pos < no_regs * 4)) { |
2817 | uint32_t value; | |
2818 | ||
2819 | value = config[*pos >> 2]; | |
2820 | r = put_user(value, (uint32_t *)buf); | |
2821 | if (r) { | |
2822 | kfree(config); | |
2823 | return r; | |
2824 | } | |
2825 | ||
2826 | result += 4; | |
2827 | buf += 4; | |
2828 | *pos += 4; | |
2829 | size -= 4; | |
2830 | } | |
2831 | ||
2832 | kfree(config); | |
2833 | return result; | |
2834 | } | |
2835 | ||
f2cdaf20 TSD |
2836 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
2837 | size_t size, loff_t *pos) | |
2838 | { | |
2839 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2840 | int idx, r; | |
2841 | int32_t value; | |
2842 | ||
2843 | if (size != 4 || *pos & 0x3) | |
2844 | return -EINVAL; | |
2845 | ||
2846 | /* convert offset to sensor number */ | |
2847 | idx = *pos >> 2; | |
2848 | ||
2849 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) | |
2850 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value); | |
2851 | else | |
2852 | return -EINVAL; | |
2853 | ||
2854 | if (!r) | |
2855 | r = put_user(value, (int32_t *)buf); | |
2856 | ||
2857 | return !r ? 4 : r; | |
2858 | } | |
1e051413 | 2859 | |
d38ceaf9 AD |
2860 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
2861 | .owner = THIS_MODULE, | |
2862 | .read = amdgpu_debugfs_regs_read, | |
2863 | .write = amdgpu_debugfs_regs_write, | |
2864 | .llseek = default_llseek | |
2865 | }; | |
adcec288 TSD |
2866 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
2867 | .owner = THIS_MODULE, | |
2868 | .read = amdgpu_debugfs_regs_didt_read, | |
2869 | .write = amdgpu_debugfs_regs_didt_write, | |
2870 | .llseek = default_llseek | |
2871 | }; | |
2872 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
2873 | .owner = THIS_MODULE, | |
2874 | .read = amdgpu_debugfs_regs_pcie_read, | |
2875 | .write = amdgpu_debugfs_regs_pcie_write, | |
2876 | .llseek = default_llseek | |
2877 | }; | |
2878 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
2879 | .owner = THIS_MODULE, | |
2880 | .read = amdgpu_debugfs_regs_smc_read, | |
2881 | .write = amdgpu_debugfs_regs_smc_write, | |
2882 | .llseek = default_llseek | |
2883 | }; | |
2884 | ||
1e051413 TSD |
2885 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
2886 | .owner = THIS_MODULE, | |
2887 | .read = amdgpu_debugfs_gca_config_read, | |
2888 | .llseek = default_llseek | |
2889 | }; | |
2890 | ||
f2cdaf20 TSD |
2891 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
2892 | .owner = THIS_MODULE, | |
2893 | .read = amdgpu_debugfs_sensor_read, | |
2894 | .llseek = default_llseek | |
2895 | }; | |
2896 | ||
adcec288 TSD |
2897 | static const struct file_operations *debugfs_regs[] = { |
2898 | &amdgpu_debugfs_regs_fops, | |
2899 | &amdgpu_debugfs_regs_didt_fops, | |
2900 | &amdgpu_debugfs_regs_pcie_fops, | |
2901 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 2902 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 2903 | &amdgpu_debugfs_sensors_fops, |
adcec288 TSD |
2904 | }; |
2905 | ||
2906 | static const char *debugfs_regs_names[] = { | |
2907 | "amdgpu_regs", | |
2908 | "amdgpu_regs_didt", | |
2909 | "amdgpu_regs_pcie", | |
2910 | "amdgpu_regs_smc", | |
1e051413 | 2911 | "amdgpu_gca_config", |
f2cdaf20 | 2912 | "amdgpu_sensors", |
adcec288 | 2913 | }; |
d38ceaf9 AD |
2914 | |
2915 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
2916 | { | |
2917 | struct drm_minor *minor = adev->ddev->primary; | |
2918 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
2919 | unsigned i, j; |
2920 | ||
2921 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
2922 | ent = debugfs_create_file(debugfs_regs_names[i], | |
2923 | S_IFREG | S_IRUGO, root, | |
2924 | adev, debugfs_regs[i]); | |
2925 | if (IS_ERR(ent)) { | |
2926 | for (j = 0; j < i; j++) { | |
2927 | debugfs_remove(adev->debugfs_regs[i]); | |
2928 | adev->debugfs_regs[i] = NULL; | |
2929 | } | |
2930 | return PTR_ERR(ent); | |
2931 | } | |
d38ceaf9 | 2932 | |
adcec288 TSD |
2933 | if (!i) |
2934 | i_size_write(ent->d_inode, adev->rmmio_size); | |
2935 | adev->debugfs_regs[i] = ent; | |
2936 | } | |
d38ceaf9 AD |
2937 | |
2938 | return 0; | |
2939 | } | |
2940 | ||
2941 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
2942 | { | |
adcec288 TSD |
2943 | unsigned i; |
2944 | ||
2945 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
2946 | if (adev->debugfs_regs[i]) { | |
2947 | debugfs_remove(adev->debugfs_regs[i]); | |
2948 | adev->debugfs_regs[i] = NULL; | |
2949 | } | |
2950 | } | |
d38ceaf9 AD |
2951 | } |
2952 | ||
2953 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
2954 | { | |
2955 | return 0; | |
2956 | } | |
2957 | ||
2958 | void amdgpu_debugfs_cleanup(struct drm_minor *minor) | |
2959 | { | |
2960 | } | |
7cebc728 AK |
2961 | #else |
2962 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
2963 | { | |
2964 | return 0; | |
2965 | } | |
2966 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 2967 | #endif |