Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
ba997709 | 58 | #include "amdgpu_amdkfd.h" |
d38ceaf9 | 59 | |
e2a75f88 | 60 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 61 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 62 | |
2dc80b00 S |
63 | #define AMDGPU_RESUME_MS 2000 |
64 | ||
d38ceaf9 AD |
65 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
66 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
4f0955fc | 67 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); |
d38ceaf9 AD |
68 | |
69 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
70 | "TAHITI", |
71 | "PITCAIRN", | |
72 | "VERDE", | |
73 | "OLAND", | |
74 | "HAINAN", | |
d38ceaf9 AD |
75 | "BONAIRE", |
76 | "KAVERI", | |
77 | "KABINI", | |
78 | "HAWAII", | |
79 | "MULLINS", | |
80 | "TOPAZ", | |
81 | "TONGA", | |
48299f95 | 82 | "FIJI", |
d38ceaf9 | 83 | "CARRIZO", |
139f4917 | 84 | "STONEY", |
2cc0c0b5 FC |
85 | "POLARIS10", |
86 | "POLARIS11", | |
c4642a47 | 87 | "POLARIS12", |
d4196f01 | 88 | "VEGA10", |
2ca8a5d2 | 89 | "RAVEN", |
d38ceaf9 AD |
90 | "LAST", |
91 | }; | |
92 | ||
93 | bool amdgpu_device_is_px(struct drm_device *dev) | |
94 | { | |
95 | struct amdgpu_device *adev = dev->dev_private; | |
96 | ||
2f7d10b3 | 97 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
98 | return true; |
99 | return false; | |
100 | } | |
101 | ||
102 | /* | |
103 | * MMIO register access helper functions. | |
104 | */ | |
105 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 106 | uint32_t acc_flags) |
d38ceaf9 | 107 | { |
f4b373f4 TSD |
108 | uint32_t ret; |
109 | ||
15d72fd7 | 110 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
111 | BUG_ON(in_interrupt()); |
112 | return amdgpu_virt_kiq_rreg(adev, reg); | |
113 | } | |
114 | ||
15d72fd7 | 115 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 116 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
117 | else { |
118 | unsigned long flags; | |
d38ceaf9 AD |
119 | |
120 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
121 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
122 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
123 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 124 | } |
f4b373f4 TSD |
125 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
126 | return ret; | |
d38ceaf9 AD |
127 | } |
128 | ||
129 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 130 | uint32_t acc_flags) |
d38ceaf9 | 131 | { |
f4b373f4 | 132 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 133 | |
47ed4e1c KW |
134 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
135 | adev->last_mm_index = v; | |
136 | } | |
137 | ||
15d72fd7 | 138 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
139 | BUG_ON(in_interrupt()); |
140 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
141 | } | |
142 | ||
15d72fd7 | 143 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
144 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
145 | else { | |
146 | unsigned long flags; | |
147 | ||
148 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
149 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
150 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
151 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
152 | } | |
47ed4e1c KW |
153 | |
154 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
155 | udelay(500); | |
156 | } | |
d38ceaf9 AD |
157 | } |
158 | ||
159 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
160 | { | |
161 | if ((reg * 4) < adev->rio_mem_size) | |
162 | return ioread32(adev->rio_mem + (reg * 4)); | |
163 | else { | |
164 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
165 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
166 | } | |
167 | } | |
168 | ||
169 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
170 | { | |
47ed4e1c KW |
171 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
172 | adev->last_mm_index = v; | |
173 | } | |
d38ceaf9 AD |
174 | |
175 | if ((reg * 4) < adev->rio_mem_size) | |
176 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
177 | else { | |
178 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
179 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
180 | } | |
47ed4e1c KW |
181 | |
182 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
183 | udelay(500); | |
184 | } | |
d38ceaf9 AD |
185 | } |
186 | ||
187 | /** | |
188 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
189 | * | |
190 | * @adev: amdgpu_device pointer | |
191 | * @index: doorbell index | |
192 | * | |
193 | * Returns the value in the doorbell aperture at the | |
194 | * requested doorbell index (CIK). | |
195 | */ | |
196 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
197 | { | |
198 | if (index < adev->doorbell.num_doorbells) { | |
199 | return readl(adev->doorbell.ptr + index); | |
200 | } else { | |
201 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
202 | return 0; | |
203 | } | |
204 | } | |
205 | ||
206 | /** | |
207 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
208 | * | |
209 | * @adev: amdgpu_device pointer | |
210 | * @index: doorbell index | |
211 | * @v: value to write | |
212 | * | |
213 | * Writes @v to the doorbell aperture at the | |
214 | * requested doorbell index (CIK). | |
215 | */ | |
216 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
217 | { | |
218 | if (index < adev->doorbell.num_doorbells) { | |
219 | writel(v, adev->doorbell.ptr + index); | |
220 | } else { | |
221 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
222 | } | |
223 | } | |
224 | ||
832be404 KW |
225 | /** |
226 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
227 | * | |
228 | * @adev: amdgpu_device pointer | |
229 | * @index: doorbell index | |
230 | * | |
231 | * Returns the value in the doorbell aperture at the | |
232 | * requested doorbell index (VEGA10+). | |
233 | */ | |
234 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
235 | { | |
236 | if (index < adev->doorbell.num_doorbells) { | |
237 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
238 | } else { | |
239 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
240 | return 0; | |
241 | } | |
242 | } | |
243 | ||
244 | /** | |
245 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
246 | * | |
247 | * @adev: amdgpu_device pointer | |
248 | * @index: doorbell index | |
249 | * @v: value to write | |
250 | * | |
251 | * Writes @v to the doorbell aperture at the | |
252 | * requested doorbell index (VEGA10+). | |
253 | */ | |
254 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
255 | { | |
256 | if (index < adev->doorbell.num_doorbells) { | |
257 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
258 | } else { | |
259 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
260 | } | |
261 | } | |
262 | ||
d38ceaf9 AD |
263 | /** |
264 | * amdgpu_invalid_rreg - dummy reg read function | |
265 | * | |
266 | * @adev: amdgpu device pointer | |
267 | * @reg: offset of register | |
268 | * | |
269 | * Dummy register read function. Used for register blocks | |
270 | * that certain asics don't have (all asics). | |
271 | * Returns the value in the register. | |
272 | */ | |
273 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
274 | { | |
275 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
276 | BUG(); | |
277 | return 0; | |
278 | } | |
279 | ||
280 | /** | |
281 | * amdgpu_invalid_wreg - dummy reg write function | |
282 | * | |
283 | * @adev: amdgpu device pointer | |
284 | * @reg: offset of register | |
285 | * @v: value to write to the register | |
286 | * | |
287 | * Dummy register read function. Used for register blocks | |
288 | * that certain asics don't have (all asics). | |
289 | */ | |
290 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
291 | { | |
292 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
293 | reg, v); | |
294 | BUG(); | |
295 | } | |
296 | ||
297 | /** | |
298 | * amdgpu_block_invalid_rreg - dummy reg read function | |
299 | * | |
300 | * @adev: amdgpu device pointer | |
301 | * @block: offset of instance | |
302 | * @reg: offset of register | |
303 | * | |
304 | * Dummy register read function. Used for register blocks | |
305 | * that certain asics don't have (all asics). | |
306 | * Returns the value in the register. | |
307 | */ | |
308 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
309 | uint32_t block, uint32_t reg) | |
310 | { | |
311 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
312 | reg, block); | |
313 | BUG(); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | /** | |
318 | * amdgpu_block_invalid_wreg - dummy reg write function | |
319 | * | |
320 | * @adev: amdgpu device pointer | |
321 | * @block: offset of instance | |
322 | * @reg: offset of register | |
323 | * @v: value to write to the register | |
324 | * | |
325 | * Dummy register read function. Used for register blocks | |
326 | * that certain asics don't have (all asics). | |
327 | */ | |
328 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
329 | uint32_t block, | |
330 | uint32_t reg, uint32_t v) | |
331 | { | |
332 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
333 | reg, block, v); | |
334 | BUG(); | |
335 | } | |
336 | ||
337 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
338 | { | |
339 | int r; | |
340 | ||
341 | if (adev->vram_scratch.robj == NULL) { | |
342 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 343 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
344 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
345 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 346 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
347 | if (r) { |
348 | return r; | |
349 | } | |
350 | } | |
351 | ||
352 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
353 | if (unlikely(r != 0)) | |
354 | return r; | |
355 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
356 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
357 | if (r) { | |
358 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
359 | return r; | |
360 | } | |
361 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
362 | (void **)&adev->vram_scratch.ptr); | |
363 | if (r) | |
364 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
365 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
366 | ||
367 | return r; | |
368 | } | |
369 | ||
370 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
371 | { | |
372 | int r; | |
373 | ||
374 | if (adev->vram_scratch.robj == NULL) { | |
375 | return; | |
376 | } | |
8ab25b4f | 377 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, true); |
d38ceaf9 AD |
378 | if (likely(r == 0)) { |
379 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
380 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
381 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
382 | } | |
383 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
384 | } | |
385 | ||
386 | /** | |
387 | * amdgpu_program_register_sequence - program an array of registers. | |
388 | * | |
389 | * @adev: amdgpu_device pointer | |
390 | * @registers: pointer to the register array | |
391 | * @array_size: size of the register array | |
392 | * | |
393 | * Programs an array or registers with and and or masks. | |
394 | * This is a helper for setting golden registers. | |
395 | */ | |
396 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
397 | const u32 *registers, | |
398 | const u32 array_size) | |
399 | { | |
400 | u32 tmp, reg, and_mask, or_mask; | |
401 | int i; | |
402 | ||
403 | if (array_size % 3) | |
404 | return; | |
405 | ||
406 | for (i = 0; i < array_size; i +=3) { | |
407 | reg = registers[i + 0]; | |
408 | and_mask = registers[i + 1]; | |
409 | or_mask = registers[i + 2]; | |
410 | ||
411 | if (and_mask == 0xffffffff) { | |
412 | tmp = or_mask; | |
413 | } else { | |
414 | tmp = RREG32(reg); | |
415 | tmp &= ~and_mask; | |
416 | tmp |= or_mask; | |
417 | } | |
418 | WREG32(reg, tmp); | |
419 | } | |
420 | } | |
421 | ||
422 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
423 | { | |
424 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
425 | } | |
426 | ||
427 | /* | |
428 | * GPU doorbell aperture helpers function. | |
429 | */ | |
430 | /** | |
431 | * amdgpu_doorbell_init - Init doorbell driver information. | |
432 | * | |
433 | * @adev: amdgpu_device pointer | |
434 | * | |
435 | * Init doorbell driver information (CIK) | |
436 | * Returns 0 on success, error on failure. | |
437 | */ | |
438 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
439 | { | |
440 | /* doorbell bar mapping */ | |
441 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
442 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
443 | ||
edf600da | 444 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
445 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
446 | if (adev->doorbell.num_doorbells == 0) | |
447 | return -EINVAL; | |
448 | ||
8972e5d2 CK |
449 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
450 | adev->doorbell.num_doorbells * | |
451 | sizeof(u32)); | |
452 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 453 | return -ENOMEM; |
d38ceaf9 AD |
454 | |
455 | return 0; | |
456 | } | |
457 | ||
458 | /** | |
459 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
460 | * | |
461 | * @adev: amdgpu_device pointer | |
462 | * | |
463 | * Tear down doorbell driver information (CIK) | |
464 | */ | |
465 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
466 | { | |
467 | iounmap(adev->doorbell.ptr); | |
468 | adev->doorbell.ptr = NULL; | |
469 | } | |
470 | ||
471 | /** | |
472 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
473 | * setup amdkfd | |
474 | * | |
475 | * @adev: amdgpu_device pointer | |
476 | * @aperture_base: output returning doorbell aperture base physical address | |
477 | * @aperture_size: output returning doorbell aperture size in bytes | |
478 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
479 | * | |
480 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
481 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
482 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
483 | */ | |
484 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
485 | phys_addr_t *aperture_base, | |
486 | size_t *aperture_size, | |
487 | size_t *start_offset) | |
488 | { | |
489 | /* | |
490 | * The first num_doorbells are used by amdgpu. | |
491 | * amdkfd takes whatever's left in the aperture. | |
492 | */ | |
493 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
494 | *aperture_base = adev->doorbell.base; | |
495 | *aperture_size = adev->doorbell.size; | |
496 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
497 | } else { | |
498 | *aperture_base = 0; | |
499 | *aperture_size = 0; | |
500 | *start_offset = 0; | |
501 | } | |
502 | } | |
503 | ||
504 | /* | |
505 | * amdgpu_wb_*() | |
455a7bc2 | 506 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 507 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
508 | */ |
509 | ||
510 | /** | |
511 | * amdgpu_wb_fini - Disable Writeback and free memory | |
512 | * | |
513 | * @adev: amdgpu_device pointer | |
514 | * | |
515 | * Disables Writeback and frees the Writeback memory (all asics). | |
516 | * Used at driver shutdown. | |
517 | */ | |
518 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
519 | { | |
520 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
521 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
522 | &adev->wb.gpu_addr, | |
523 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
524 | adev->wb.wb_obj = NULL; |
525 | } | |
526 | } | |
527 | ||
528 | /** | |
529 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
530 | * | |
531 | * @adev: amdgpu_device pointer | |
532 | * | |
455a7bc2 | 533 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
534 | * Used at driver startup. |
535 | * Returns 0 on success or an -error on failure. | |
536 | */ | |
537 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
538 | { | |
539 | int r; | |
540 | ||
541 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 542 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
543 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
544 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
545 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
546 | if (r) { |
547 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
548 | return r; | |
549 | } | |
d38ceaf9 AD |
550 | |
551 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
552 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
553 | ||
554 | /* clear wb memory */ | |
60a970a6 | 555 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
556 | } |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | /** | |
562 | * amdgpu_wb_get - Allocate a wb entry | |
563 | * | |
564 | * @adev: amdgpu_device pointer | |
565 | * @wb: wb index | |
566 | * | |
567 | * Allocate a wb slot for use by the driver (all asics). | |
568 | * Returns 0 on success or -EINVAL on failure. | |
569 | */ | |
570 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
571 | { | |
572 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
573 | if (offset < adev->wb.num_wb) { | |
574 | __set_bit(offset, adev->wb.used); | |
575 | *wb = offset; | |
576 | return 0; | |
577 | } else { | |
578 | return -EINVAL; | |
579 | } | |
580 | } | |
581 | ||
7014285a KW |
582 | /** |
583 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
584 | * | |
585 | * @adev: amdgpu_device pointer | |
586 | * @wb: wb index | |
587 | * | |
588 | * Allocate a wb slot for use by the driver (all asics). | |
589 | * Returns 0 on success or -EINVAL on failure. | |
590 | */ | |
591 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
592 | { | |
593 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
594 | adev->wb.num_wb, 0, 2, 7, 0); | |
595 | if ((offset + 1) < adev->wb.num_wb) { | |
596 | __set_bit(offset, adev->wb.used); | |
597 | __set_bit(offset + 1, adev->wb.used); | |
598 | *wb = offset; | |
599 | return 0; | |
600 | } else { | |
601 | return -EINVAL; | |
602 | } | |
603 | } | |
604 | ||
0915fdbc ML |
605 | int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb) |
606 | { | |
607 | int i = 0; | |
608 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
609 | adev->wb.num_wb, 0, 8, 63, 0); | |
610 | if ((offset + 7) < adev->wb.num_wb) { | |
611 | for (i = 0; i < 8; i++) | |
612 | __set_bit(offset + i, adev->wb.used); | |
613 | *wb = offset; | |
614 | return 0; | |
615 | } else { | |
616 | return -EINVAL; | |
617 | } | |
618 | } | |
619 | ||
d38ceaf9 AD |
620 | /** |
621 | * amdgpu_wb_free - Free a wb entry | |
622 | * | |
623 | * @adev: amdgpu_device pointer | |
624 | * @wb: wb index | |
625 | * | |
626 | * Free a wb slot allocated for use by the driver (all asics) | |
627 | */ | |
628 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
629 | { | |
630 | if (wb < adev->wb.num_wb) | |
631 | __clear_bit(wb, adev->wb.used); | |
632 | } | |
633 | ||
7014285a KW |
634 | /** |
635 | * amdgpu_wb_free_64bit - Free a wb entry | |
636 | * | |
637 | * @adev: amdgpu_device pointer | |
638 | * @wb: wb index | |
639 | * | |
640 | * Free a wb slot allocated for use by the driver (all asics) | |
641 | */ | |
642 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
643 | { | |
644 | if ((wb + 1) < adev->wb.num_wb) { | |
645 | __clear_bit(wb, adev->wb.used); | |
646 | __clear_bit(wb + 1, adev->wb.used); | |
647 | } | |
648 | } | |
649 | ||
0915fdbc ML |
650 | /** |
651 | * amdgpu_wb_free_256bit - Free a wb entry | |
652 | * | |
653 | * @adev: amdgpu_device pointer | |
654 | * @wb: wb index | |
655 | * | |
656 | * Free a wb slot allocated for use by the driver (all asics) | |
657 | */ | |
658 | void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb) | |
659 | { | |
660 | int i = 0; | |
661 | ||
662 | if ((wb + 7) < adev->wb.num_wb) | |
663 | for (i = 0; i < 8; i++) | |
664 | __clear_bit(wb + i, adev->wb.used); | |
665 | } | |
666 | ||
d38ceaf9 AD |
667 | /** |
668 | * amdgpu_vram_location - try to find VRAM location | |
669 | * @adev: amdgpu device structure holding all necessary informations | |
670 | * @mc: memory controller structure holding memory informations | |
671 | * @base: base address at which to put VRAM | |
672 | * | |
455a7bc2 | 673 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
674 | * as parameter (which is so far either PCI aperture address or |
675 | * for IGP TOM base address). | |
676 | * | |
677 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
678 | * address space then we limit the VRAM size to the aperture. | |
679 | * | |
680 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
681 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
682 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
683 | * not IGP. | |
684 | * | |
685 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
686 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
687 | * Novell bug 204882 + along with lots of ubuntu ones | |
688 | * | |
689 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
690 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
691 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
692 | * ones) | |
693 | * | |
694 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 695 | * explicitly check for that though. |
d38ceaf9 AD |
696 | * |
697 | * FIXME: when reducing VRAM size align new size on power of 2. | |
698 | */ | |
699 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
700 | { | |
701 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
702 | ||
703 | mc->vram_start = base; | |
704 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
705 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
706 | mc->real_vram_size = mc->aper_size; | |
707 | mc->mc_vram_size = mc->aper_size; | |
708 | } | |
709 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
710 | if (limit && limit < mc->real_vram_size) | |
711 | mc->real_vram_size = limit; | |
712 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
713 | mc->mc_vram_size >> 20, mc->vram_start, | |
714 | mc->vram_end, mc->real_vram_size >> 20); | |
715 | } | |
716 | ||
717 | /** | |
6f02a696 | 718 | * amdgpu_gart_location - try to find GTT location |
d38ceaf9 AD |
719 | * @adev: amdgpu device structure holding all necessary informations |
720 | * @mc: memory controller structure holding memory informations | |
721 | * | |
722 | * Function will place try to place GTT before or after VRAM. | |
723 | * | |
724 | * If GTT size is bigger than space left then we ajust GTT size. | |
725 | * Thus function will never fails. | |
726 | * | |
727 | * FIXME: when reducing GTT size align new size on power of 2. | |
728 | */ | |
6f02a696 | 729 | void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) |
d38ceaf9 AD |
730 | { |
731 | u64 size_af, size_bf; | |
732 | ||
ed21c047 CK |
733 | size_af = adev->mc.mc_mask - mc->vram_end; |
734 | size_bf = mc->vram_start; | |
d38ceaf9 | 735 | if (size_bf > size_af) { |
6f02a696 | 736 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 737 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 738 | mc->gart_size = size_bf; |
d38ceaf9 | 739 | } |
6f02a696 | 740 | mc->gart_start = 0; |
d38ceaf9 | 741 | } else { |
6f02a696 | 742 | if (mc->gart_size > size_af) { |
d38ceaf9 | 743 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 744 | mc->gart_size = size_af; |
d38ceaf9 | 745 | } |
6f02a696 | 746 | mc->gart_start = mc->vram_end + 1; |
d38ceaf9 | 747 | } |
6f02a696 | 748 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 749 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 750 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
751 | } |
752 | ||
753 | /* | |
754 | * GPU helpers function. | |
755 | */ | |
756 | /** | |
c836fec5 | 757 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
758 | * |
759 | * @adev: amdgpu_device pointer | |
760 | * | |
c836fec5 JQ |
761 | * Check if the asic has been initialized (all asics) at driver startup |
762 | * or post is needed if hw reset is performed. | |
763 | * Returns true if need or false if not. | |
d38ceaf9 | 764 | */ |
c836fec5 | 765 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
766 | { |
767 | uint32_t reg; | |
768 | ||
c836fec5 JQ |
769 | if (adev->has_hw_reset) { |
770 | adev->has_hw_reset = false; | |
771 | return true; | |
772 | } | |
70d17a25 AD |
773 | |
774 | /* bios scratch used on CIK+ */ | |
775 | if (adev->asic_type >= CHIP_BONAIRE) | |
776 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
777 | ||
778 | /* check MEM_SIZE for older asics */ | |
bbf282d8 | 779 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 | 780 | |
f2713e8c | 781 | if ((reg != 0) && (reg != 0xffffffff)) |
c836fec5 | 782 | return false; |
d38ceaf9 | 783 | |
c836fec5 | 784 | return true; |
d38ceaf9 AD |
785 | |
786 | } | |
787 | ||
bec86378 ML |
788 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
789 | { | |
790 | if (amdgpu_sriov_vf(adev)) | |
791 | return false; | |
792 | ||
793 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
794 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
795 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
796 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
797 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
798 | */ |
799 | if (adev->asic_type == CHIP_FIJI) { | |
800 | int err; | |
801 | uint32_t fw_ver; | |
802 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
803 | /* force vPost if error occured */ | |
804 | if (err) | |
805 | return true; | |
806 | ||
807 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
808 | if (fw_ver < 0x00160e00) |
809 | return true; | |
bec86378 | 810 | } |
bec86378 | 811 | } |
c836fec5 | 812 | return amdgpu_need_post(adev); |
bec86378 ML |
813 | } |
814 | ||
d38ceaf9 AD |
815 | /** |
816 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
817 | * | |
818 | * @adev: amdgpu_device pointer | |
819 | * | |
820 | * Allocate the dummy page used by the driver (all asics). | |
821 | * This dummy page is used by the driver as a filler for gart entries | |
822 | * when pages are taken out of the GART | |
823 | * Returns 0 on sucess, -ENOMEM on failure. | |
824 | */ | |
825 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
826 | { | |
827 | if (adev->dummy_page.page) | |
828 | return 0; | |
829 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
830 | if (adev->dummy_page.page == NULL) | |
831 | return -ENOMEM; | |
832 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
833 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
834 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
835 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
836 | __free_page(adev->dummy_page.page); | |
837 | adev->dummy_page.page = NULL; | |
838 | return -ENOMEM; | |
839 | } | |
840 | return 0; | |
841 | } | |
842 | ||
843 | /** | |
844 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
845 | * | |
846 | * @adev: amdgpu_device pointer | |
847 | * | |
848 | * Frees the dummy page used by the driver (all asics). | |
849 | */ | |
850 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
851 | { | |
852 | if (adev->dummy_page.page == NULL) | |
853 | return; | |
854 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
855 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
856 | __free_page(adev->dummy_page.page); | |
857 | adev->dummy_page.page = NULL; | |
858 | } | |
859 | ||
860 | ||
861 | /* ATOM accessor methods */ | |
862 | /* | |
863 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
864 | * driver registers callbacks to access registers and the interpreter | |
865 | * in the driver parses the tables and executes then to program specific | |
866 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
867 | * atombios.h, and atom.c | |
868 | */ | |
869 | ||
870 | /** | |
871 | * cail_pll_read - read PLL register | |
872 | * | |
873 | * @info: atom card_info pointer | |
874 | * @reg: PLL register offset | |
875 | * | |
876 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
877 | * Returns the value of the PLL register. | |
878 | */ | |
879 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
880 | { | |
881 | return 0; | |
882 | } | |
883 | ||
884 | /** | |
885 | * cail_pll_write - write PLL register | |
886 | * | |
887 | * @info: atom card_info pointer | |
888 | * @reg: PLL register offset | |
889 | * @val: value to write to the pll register | |
890 | * | |
891 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
892 | */ | |
893 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
894 | { | |
895 | ||
896 | } | |
897 | ||
898 | /** | |
899 | * cail_mc_read - read MC (Memory Controller) register | |
900 | * | |
901 | * @info: atom card_info pointer | |
902 | * @reg: MC register offset | |
903 | * | |
904 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
905 | * Returns the value of the MC register. | |
906 | */ | |
907 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
908 | { | |
909 | return 0; | |
910 | } | |
911 | ||
912 | /** | |
913 | * cail_mc_write - write MC (Memory Controller) register | |
914 | * | |
915 | * @info: atom card_info pointer | |
916 | * @reg: MC register offset | |
917 | * @val: value to write to the pll register | |
918 | * | |
919 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
920 | */ | |
921 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
922 | { | |
923 | ||
924 | } | |
925 | ||
926 | /** | |
927 | * cail_reg_write - write MMIO register | |
928 | * | |
929 | * @info: atom card_info pointer | |
930 | * @reg: MMIO register offset | |
931 | * @val: value to write to the pll register | |
932 | * | |
933 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
934 | */ | |
935 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
936 | { | |
937 | struct amdgpu_device *adev = info->dev->dev_private; | |
938 | ||
939 | WREG32(reg, val); | |
940 | } | |
941 | ||
942 | /** | |
943 | * cail_reg_read - read MMIO register | |
944 | * | |
945 | * @info: atom card_info pointer | |
946 | * @reg: MMIO register offset | |
947 | * | |
948 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
949 | * Returns the value of the MMIO register. | |
950 | */ | |
951 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
952 | { | |
953 | struct amdgpu_device *adev = info->dev->dev_private; | |
954 | uint32_t r; | |
955 | ||
956 | r = RREG32(reg); | |
957 | return r; | |
958 | } | |
959 | ||
960 | /** | |
961 | * cail_ioreg_write - write IO register | |
962 | * | |
963 | * @info: atom card_info pointer | |
964 | * @reg: IO register offset | |
965 | * @val: value to write to the pll register | |
966 | * | |
967 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
968 | */ | |
969 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
970 | { | |
971 | struct amdgpu_device *adev = info->dev->dev_private; | |
972 | ||
973 | WREG32_IO(reg, val); | |
974 | } | |
975 | ||
976 | /** | |
977 | * cail_ioreg_read - read IO register | |
978 | * | |
979 | * @info: atom card_info pointer | |
980 | * @reg: IO register offset | |
981 | * | |
982 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
983 | * Returns the value of the IO register. | |
984 | */ | |
985 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
986 | { | |
987 | struct amdgpu_device *adev = info->dev->dev_private; | |
988 | uint32_t r; | |
989 | ||
990 | r = RREG32_IO(reg); | |
991 | return r; | |
992 | } | |
993 | ||
994 | /** | |
995 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
996 | * | |
997 | * @adev: amdgpu_device pointer | |
998 | * | |
999 | * Frees the driver info and register access callbacks for the ATOM | |
1000 | * interpreter (r4xx+). | |
1001 | * Called at driver shutdown. | |
1002 | */ | |
1003 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
1004 | { | |
89e0ec9f | 1005 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 1006 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
1007 | kfree(adev->mode_info.atom_context->iio); |
1008 | } | |
d38ceaf9 AD |
1009 | kfree(adev->mode_info.atom_context); |
1010 | adev->mode_info.atom_context = NULL; | |
1011 | kfree(adev->mode_info.atom_card_info); | |
1012 | adev->mode_info.atom_card_info = NULL; | |
1013 | } | |
1014 | ||
1015 | /** | |
1016 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
1017 | * | |
1018 | * @adev: amdgpu_device pointer | |
1019 | * | |
1020 | * Initializes the driver info and register access callbacks for the | |
1021 | * ATOM interpreter (r4xx+). | |
1022 | * Returns 0 on sucess, -ENOMEM on failure. | |
1023 | * Called at driver startup. | |
1024 | */ | |
1025 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
1026 | { | |
1027 | struct card_info *atom_card_info = | |
1028 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
1029 | ||
1030 | if (!atom_card_info) | |
1031 | return -ENOMEM; | |
1032 | ||
1033 | adev->mode_info.atom_card_info = atom_card_info; | |
1034 | atom_card_info->dev = adev->ddev; | |
1035 | atom_card_info->reg_read = cail_reg_read; | |
1036 | atom_card_info->reg_write = cail_reg_write; | |
1037 | /* needed for iio ops */ | |
1038 | if (adev->rio_mem) { | |
1039 | atom_card_info->ioreg_read = cail_ioreg_read; | |
1040 | atom_card_info->ioreg_write = cail_ioreg_write; | |
1041 | } else { | |
b64a18c5 | 1042 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
1043 | atom_card_info->ioreg_read = cail_reg_read; |
1044 | atom_card_info->ioreg_write = cail_reg_write; | |
1045 | } | |
1046 | atom_card_info->mc_read = cail_mc_read; | |
1047 | atom_card_info->mc_write = cail_mc_write; | |
1048 | atom_card_info->pll_read = cail_pll_read; | |
1049 | atom_card_info->pll_write = cail_pll_write; | |
1050 | ||
1051 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
1052 | if (!adev->mode_info.atom_context) { | |
1053 | amdgpu_atombios_fini(adev); | |
1054 | return -ENOMEM; | |
1055 | } | |
1056 | ||
1057 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1058 | if (adev->is_atom_fw) { |
1059 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1060 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1061 | } else { | |
1062 | amdgpu_atombios_scratch_regs_init(adev); | |
1063 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1064 | } | |
d38ceaf9 AD |
1065 | return 0; |
1066 | } | |
1067 | ||
1068 | /* if we get transitioned to only one device, take VGA back */ | |
1069 | /** | |
1070 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1071 | * | |
1072 | * @cookie: amdgpu_device pointer | |
1073 | * @state: enable/disable vga decode | |
1074 | * | |
1075 | * Enable/disable vga decode (all asics). | |
1076 | * Returns VGA resource flags. | |
1077 | */ | |
1078 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1079 | { | |
1080 | struct amdgpu_device *adev = cookie; | |
1081 | amdgpu_asic_set_vga_state(adev, state); | |
1082 | if (state) | |
1083 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1084 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1085 | else | |
1086 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1087 | } | |
1088 | ||
bab4fee7 | 1089 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1090 | { |
1091 | /* defines number of bits in page table versus page directory, | |
1092 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1093 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1094 | if (amdgpu_vm_block_size == -1) |
1095 | return; | |
a1adf8be | 1096 | |
bab4fee7 | 1097 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1098 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1099 | amdgpu_vm_block_size); | |
bab4fee7 | 1100 | goto def_value; |
a1adf8be CZ |
1101 | } |
1102 | ||
1103 | if (amdgpu_vm_block_size > 24 || | |
1104 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1105 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1106 | amdgpu_vm_block_size); | |
bab4fee7 | 1107 | goto def_value; |
a1adf8be | 1108 | } |
bab4fee7 JZ |
1109 | |
1110 | return; | |
1111 | ||
1112 | def_value: | |
1113 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1114 | } |
1115 | ||
83ca145d ZJ |
1116 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1117 | { | |
64dab074 AD |
1118 | /* no need to check the default value */ |
1119 | if (amdgpu_vm_size == -1) | |
1120 | return; | |
1121 | ||
76117507 | 1122 | if (!is_power_of_2(amdgpu_vm_size)) { |
83ca145d ZJ |
1123 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", |
1124 | amdgpu_vm_size); | |
1125 | goto def_value; | |
1126 | } | |
1127 | ||
1128 | if (amdgpu_vm_size < 1) { | |
1129 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1130 | amdgpu_vm_size); | |
1131 | goto def_value; | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1136 | */ | |
1137 | if (amdgpu_vm_size > 1024) { | |
1138 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1139 | amdgpu_vm_size); | |
1140 | goto def_value; | |
1141 | } | |
1142 | ||
1143 | return; | |
1144 | ||
1145 | def_value: | |
bab4fee7 | 1146 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1147 | } |
1148 | ||
d38ceaf9 AD |
1149 | /** |
1150 | * amdgpu_check_arguments - validate module params | |
1151 | * | |
1152 | * @adev: amdgpu_device pointer | |
1153 | * | |
1154 | * Validates certain module parameters and updates | |
1155 | * the associated values used by the driver (all asics). | |
1156 | */ | |
1157 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1158 | { | |
5b011235 CZ |
1159 | if (amdgpu_sched_jobs < 4) { |
1160 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1161 | amdgpu_sched_jobs); | |
1162 | amdgpu_sched_jobs = 4; | |
76117507 | 1163 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1164 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1165 | amdgpu_sched_jobs); | |
1166 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1167 | } | |
d38ceaf9 | 1168 | |
f9321cc4 CK |
1169 | if (amdgpu_gart_size < 32) { |
1170 | /* gart size must be greater or equal to 32M */ | |
1171 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1172 | amdgpu_gart_size); | |
1173 | amdgpu_gart_size = 32; | |
d38ceaf9 AD |
1174 | } |
1175 | ||
36d38372 | 1176 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1177 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1178 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1179 | amdgpu_gtt_size); | |
1180 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1181 | } |
1182 | ||
83ca145d | 1183 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1184 | |
bab4fee7 | 1185 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1186 | |
526bae37 | 1187 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1188 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1189 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1190 | amdgpu_vram_page_split); | |
1191 | amdgpu_vram_page_split = 1024; | |
1192 | } | |
d38ceaf9 AD |
1193 | } |
1194 | ||
1195 | /** | |
1196 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1197 | * | |
1198 | * @pdev: pci dev pointer | |
1694467b | 1199 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1200 | * |
1201 | * Callback for the switcheroo driver. Suspends or resumes the | |
1202 | * the asics before or after it is powered up using ACPI methods. | |
1203 | */ | |
1204 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1205 | { | |
1206 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1207 | ||
1208 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1209 | return; | |
1210 | ||
1211 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1212 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1213 | /* don't suspend or resume card normally */ |
1214 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1215 | ||
810ddc3a | 1216 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1217 | |
d38ceaf9 AD |
1218 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1219 | drm_kms_helper_poll_enable(dev); | |
1220 | } else { | |
7ca85295 | 1221 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1222 | drm_kms_helper_poll_disable(dev); |
1223 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1224 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1225 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1226 | } | |
1227 | } | |
1228 | ||
1229 | /** | |
1230 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1231 | * | |
1232 | * @pdev: pci dev pointer | |
1233 | * | |
1234 | * Callback for the switcheroo driver. Check of the switcheroo | |
1235 | * state can be changed. | |
1236 | * Returns true if the state can be changed, false if not. | |
1237 | */ | |
1238 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1239 | { | |
1240 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1241 | ||
1242 | /* | |
1243 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1244 | * locking inversion with the driver load path. And the access here is | |
1245 | * completely racy anyway. So don't bother with locking for now. | |
1246 | */ | |
1247 | return dev->open_count == 0; | |
1248 | } | |
1249 | ||
1250 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1251 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1252 | .reprobe = NULL, | |
1253 | .can_switch = amdgpu_switcheroo_can_switch, | |
1254 | }; | |
1255 | ||
1256 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1257 | enum amd_ip_block_type block_type, |
1258 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1259 | { |
1260 | int i, r = 0; | |
1261 | ||
1262 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1263 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1264 | continue; |
c722865a RZ |
1265 | if (adev->ip_blocks[i].version->type != block_type) |
1266 | continue; | |
1267 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1268 | continue; | |
1269 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1270 | (void *)adev, state); | |
1271 | if (r) | |
1272 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1273 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1274 | } |
1275 | return r; | |
1276 | } | |
1277 | ||
1278 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1279 | enum amd_ip_block_type block_type, |
1280 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1281 | { |
1282 | int i, r = 0; | |
1283 | ||
1284 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1285 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1286 | continue; |
c722865a RZ |
1287 | if (adev->ip_blocks[i].version->type != block_type) |
1288 | continue; | |
1289 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1290 | continue; | |
1291 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1292 | (void *)adev, state); | |
1293 | if (r) | |
1294 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1295 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1296 | } |
1297 | return r; | |
1298 | } | |
1299 | ||
6cb2d4e4 HR |
1300 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1301 | { | |
1302 | int i; | |
1303 | ||
1304 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1305 | if (!adev->ip_blocks[i].status.valid) | |
1306 | continue; | |
1307 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1308 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1309 | } | |
1310 | } | |
1311 | ||
5dbbb60b AD |
1312 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1313 | enum amd_ip_block_type block_type) | |
1314 | { | |
1315 | int i, r; | |
1316 | ||
1317 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1318 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1319 | continue; |
a1255107 AD |
1320 | if (adev->ip_blocks[i].version->type == block_type) { |
1321 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1322 | if (r) |
1323 | return r; | |
1324 | break; | |
1325 | } | |
1326 | } | |
1327 | return 0; | |
1328 | ||
1329 | } | |
1330 | ||
1331 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1332 | enum amd_ip_block_type block_type) | |
1333 | { | |
1334 | int i; | |
1335 | ||
1336 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1337 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1338 | continue; |
a1255107 AD |
1339 | if (adev->ip_blocks[i].version->type == block_type) |
1340 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1341 | } |
1342 | return true; | |
1343 | ||
1344 | } | |
1345 | ||
a1255107 AD |
1346 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1347 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1348 | { |
1349 | int i; | |
1350 | ||
1351 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1352 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1353 | return &adev->ip_blocks[i]; |
1354 | ||
1355 | return NULL; | |
1356 | } | |
1357 | ||
1358 | /** | |
1359 | * amdgpu_ip_block_version_cmp | |
1360 | * | |
1361 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1362 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1363 | * @major: major version |
1364 | * @minor: minor version | |
1365 | * | |
1366 | * return 0 if equal or greater | |
1367 | * return 1 if smaller or the ip_block doesn't exist | |
1368 | */ | |
1369 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1370 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1371 | u32 major, u32 minor) |
1372 | { | |
a1255107 | 1373 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1374 | |
a1255107 AD |
1375 | if (ip_block && ((ip_block->version->major > major) || |
1376 | ((ip_block->version->major == major) && | |
1377 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1378 | return 0; |
1379 | ||
1380 | return 1; | |
1381 | } | |
1382 | ||
a1255107 AD |
1383 | /** |
1384 | * amdgpu_ip_block_add | |
1385 | * | |
1386 | * @adev: amdgpu_device pointer | |
1387 | * @ip_block_version: pointer to the IP to add | |
1388 | * | |
1389 | * Adds the IP block driver information to the collection of IPs | |
1390 | * on the asic. | |
1391 | */ | |
1392 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1393 | const struct amdgpu_ip_block_version *ip_block_version) | |
1394 | { | |
1395 | if (!ip_block_version) | |
1396 | return -EINVAL; | |
1397 | ||
a0bae357 HR |
1398 | DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, |
1399 | ip_block_version->funcs->name); | |
1400 | ||
a1255107 AD |
1401 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
483ef985 | 1406 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1407 | { |
1408 | adev->enable_virtual_display = false; | |
1409 | ||
1410 | if (amdgpu_virtual_display) { | |
1411 | struct drm_device *ddev = adev->ddev; | |
1412 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1413 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1414 | |
1415 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1416 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1417 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1418 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1419 | if (!strcmp("all", pciaddname) |
1420 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1421 | long num_crtc; |
1422 | int res = -1; | |
1423 | ||
9accf2fd | 1424 | adev->enable_virtual_display = true; |
0f66356d ED |
1425 | |
1426 | if (pciaddname_tmp) | |
1427 | res = kstrtol(pciaddname_tmp, 10, | |
1428 | &num_crtc); | |
1429 | ||
1430 | if (!res) { | |
1431 | if (num_crtc < 1) | |
1432 | num_crtc = 1; | |
1433 | if (num_crtc > 6) | |
1434 | num_crtc = 6; | |
1435 | adev->mode_info.num_crtc = num_crtc; | |
1436 | } else { | |
1437 | adev->mode_info.num_crtc = 1; | |
1438 | } | |
9accf2fd ED |
1439 | break; |
1440 | } | |
1441 | } | |
1442 | ||
0f66356d ED |
1443 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1444 | amdgpu_virtual_display, pci_address_name, | |
1445 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1446 | |
1447 | kfree(pciaddstr); | |
1448 | } | |
1449 | } | |
1450 | ||
e2a75f88 AD |
1451 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1452 | { | |
e2a75f88 AD |
1453 | const char *chip_name; |
1454 | char fw_name[30]; | |
1455 | int err; | |
1456 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1457 | ||
ab4fe3e1 HR |
1458 | adev->firmware.gpu_info_fw = NULL; |
1459 | ||
e2a75f88 AD |
1460 | switch (adev->asic_type) { |
1461 | case CHIP_TOPAZ: | |
1462 | case CHIP_TONGA: | |
1463 | case CHIP_FIJI: | |
1464 | case CHIP_POLARIS11: | |
1465 | case CHIP_POLARIS10: | |
1466 | case CHIP_POLARIS12: | |
1467 | case CHIP_CARRIZO: | |
1468 | case CHIP_STONEY: | |
1469 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1470 | case CHIP_VERDE: | |
1471 | case CHIP_TAHITI: | |
1472 | case CHIP_PITCAIRN: | |
1473 | case CHIP_OLAND: | |
1474 | case CHIP_HAINAN: | |
1475 | #endif | |
1476 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1477 | case CHIP_BONAIRE: | |
1478 | case CHIP_HAWAII: | |
1479 | case CHIP_KAVERI: | |
1480 | case CHIP_KABINI: | |
1481 | case CHIP_MULLINS: | |
1482 | #endif | |
1483 | default: | |
1484 | return 0; | |
1485 | case CHIP_VEGA10: | |
1486 | chip_name = "vega10"; | |
1487 | break; | |
2d2e5e7e AD |
1488 | case CHIP_RAVEN: |
1489 | chip_name = "raven"; | |
1490 | break; | |
e2a75f88 AD |
1491 | } |
1492 | ||
1493 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1494 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1495 | if (err) { |
1496 | dev_err(adev->dev, | |
1497 | "Failed to load gpu_info firmware \"%s\"\n", | |
1498 | fw_name); | |
1499 | goto out; | |
1500 | } | |
ab4fe3e1 | 1501 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1502 | if (err) { |
1503 | dev_err(adev->dev, | |
1504 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1505 | fw_name); | |
1506 | goto out; | |
1507 | } | |
1508 | ||
ab4fe3e1 | 1509 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1510 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1511 | ||
1512 | switch (hdr->version_major) { | |
1513 | case 1: | |
1514 | { | |
1515 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1516 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1517 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1518 | ||
b5ab16bf AD |
1519 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1520 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1521 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1522 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1523 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1524 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1525 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1526 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1527 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1528 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1529 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1530 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1531 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1532 | adev->gfx.cu_info.max_waves_per_simd = |
1533 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1534 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1535 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1536 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1537 | break; |
1538 | } | |
1539 | default: | |
1540 | dev_err(adev->dev, | |
1541 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1542 | err = -EINVAL; | |
1543 | goto out; | |
1544 | } | |
1545 | out: | |
e2a75f88 AD |
1546 | return err; |
1547 | } | |
1548 | ||
d38ceaf9 AD |
1549 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1550 | { | |
aaa36a97 | 1551 | int i, r; |
d38ceaf9 | 1552 | |
483ef985 | 1553 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1554 | |
d38ceaf9 | 1555 | switch (adev->asic_type) { |
aaa36a97 AD |
1556 | case CHIP_TOPAZ: |
1557 | case CHIP_TONGA: | |
48299f95 | 1558 | case CHIP_FIJI: |
2cc0c0b5 FC |
1559 | case CHIP_POLARIS11: |
1560 | case CHIP_POLARIS10: | |
c4642a47 | 1561 | case CHIP_POLARIS12: |
aaa36a97 | 1562 | case CHIP_CARRIZO: |
39bb0c92 SL |
1563 | case CHIP_STONEY: |
1564 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1565 | adev->family = AMDGPU_FAMILY_CZ; |
1566 | else | |
1567 | adev->family = AMDGPU_FAMILY_VI; | |
1568 | ||
1569 | r = vi_set_ip_blocks(adev); | |
1570 | if (r) | |
1571 | return r; | |
1572 | break; | |
33f34802 KW |
1573 | #ifdef CONFIG_DRM_AMDGPU_SI |
1574 | case CHIP_VERDE: | |
1575 | case CHIP_TAHITI: | |
1576 | case CHIP_PITCAIRN: | |
1577 | case CHIP_OLAND: | |
1578 | case CHIP_HAINAN: | |
295d0daf | 1579 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1580 | r = si_set_ip_blocks(adev); |
1581 | if (r) | |
1582 | return r; | |
1583 | break; | |
1584 | #endif | |
a2e73f56 AD |
1585 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1586 | case CHIP_BONAIRE: | |
1587 | case CHIP_HAWAII: | |
1588 | case CHIP_KAVERI: | |
1589 | case CHIP_KABINI: | |
1590 | case CHIP_MULLINS: | |
1591 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1592 | adev->family = AMDGPU_FAMILY_CI; | |
1593 | else | |
1594 | adev->family = AMDGPU_FAMILY_KV; | |
1595 | ||
1596 | r = cik_set_ip_blocks(adev); | |
1597 | if (r) | |
1598 | return r; | |
1599 | break; | |
1600 | #endif | |
2ca8a5d2 CZ |
1601 | case CHIP_VEGA10: |
1602 | case CHIP_RAVEN: | |
1603 | if (adev->asic_type == CHIP_RAVEN) | |
1604 | adev->family = AMDGPU_FAMILY_RV; | |
1605 | else | |
1606 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1607 | |
1608 | r = soc15_set_ip_blocks(adev); | |
1609 | if (r) | |
1610 | return r; | |
1611 | break; | |
d38ceaf9 AD |
1612 | default: |
1613 | /* FIXME: not supported yet */ | |
1614 | return -EINVAL; | |
1615 | } | |
1616 | ||
e2a75f88 AD |
1617 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1618 | if (r) | |
1619 | return r; | |
1620 | ||
3149d9da XY |
1621 | if (amdgpu_sriov_vf(adev)) { |
1622 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1623 | if (r) | |
1624 | return r; | |
1625 | } | |
1626 | ||
d38ceaf9 AD |
1627 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1628 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1629 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1630 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1631 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1632 | } else { |
a1255107 AD |
1633 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1634 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1635 | if (r == -ENOENT) { |
a1255107 | 1636 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1637 | } else if (r) { |
a1255107 AD |
1638 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1639 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1640 | return r; |
2c1a2784 | 1641 | } else { |
a1255107 | 1642 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1643 | } |
974e6b64 | 1644 | } else { |
a1255107 | 1645 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1646 | } |
d38ceaf9 AD |
1647 | } |
1648 | } | |
1649 | ||
395d1fb9 NH |
1650 | adev->cg_flags &= amdgpu_cg_mask; |
1651 | adev->pg_flags &= amdgpu_pg_mask; | |
1652 | ||
d38ceaf9 AD |
1653 | return 0; |
1654 | } | |
1655 | ||
1656 | static int amdgpu_init(struct amdgpu_device *adev) | |
1657 | { | |
1658 | int i, r; | |
1659 | ||
1660 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1661 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1662 | continue; |
a1255107 | 1663 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1664 | if (r) { |
a1255107 AD |
1665 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1666 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1667 | return r; |
2c1a2784 | 1668 | } |
a1255107 | 1669 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1670 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1671 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1672 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1673 | if (r) { |
1674 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1675 | return r; |
2c1a2784 | 1676 | } |
a1255107 | 1677 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1678 | if (r) { |
1679 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1680 | return r; |
2c1a2784 | 1681 | } |
d38ceaf9 | 1682 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1683 | if (r) { |
1684 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1685 | return r; |
2c1a2784 | 1686 | } |
a1255107 | 1687 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1688 | |
1689 | /* right after GMC hw init, we create CSA */ | |
1690 | if (amdgpu_sriov_vf(adev)) { | |
1691 | r = amdgpu_allocate_static_csa(adev); | |
1692 | if (r) { | |
1693 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1694 | return r; | |
1695 | } | |
1696 | } | |
d38ceaf9 AD |
1697 | } |
1698 | } | |
1699 | ||
1700 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1701 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1702 | continue; |
1703 | /* gmc hw init is done early */ | |
a1255107 | 1704 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1705 | continue; |
a1255107 | 1706 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1707 | if (r) { |
a1255107 AD |
1708 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1709 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1710 | return r; |
2c1a2784 | 1711 | } |
a1255107 | 1712 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1713 | } |
1714 | ||
1715 | return 0; | |
1716 | } | |
1717 | ||
0c49e0b8 CZ |
1718 | static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) |
1719 | { | |
1720 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1721 | } | |
1722 | ||
1723 | static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) | |
1724 | { | |
1725 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1726 | AMDGPU_RESET_MAGIC_NUM); | |
1727 | } | |
1728 | ||
2dc80b00 | 1729 | static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1730 | { |
1731 | int i = 0, r; | |
1732 | ||
1733 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1734 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1735 | continue; |
4a446d55 | 1736 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1737 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1738 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1739 | /* enable clockgating to save power */ |
a1255107 AD |
1740 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1741 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1742 | if (r) { |
1743 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1744 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1745 | return r; |
1746 | } | |
b0b00ff1 | 1747 | } |
d38ceaf9 | 1748 | } |
2dc80b00 S |
1749 | return 0; |
1750 | } | |
1751 | ||
1752 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1753 | { | |
1754 | int i = 0, r; | |
1755 | ||
1756 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1757 | if (!adev->ip_blocks[i].status.valid) | |
1758 | continue; | |
1759 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1760 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1761 | if (r) { | |
1762 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1763 | adev->ip_blocks[i].version->funcs->name, r); | |
1764 | return r; | |
1765 | } | |
1766 | adev->ip_blocks[i].status.late_initialized = true; | |
1767 | } | |
1768 | } | |
1769 | ||
1770 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1771 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1772 | |
0c49e0b8 | 1773 | amdgpu_fill_reset_magic(adev); |
d38ceaf9 AD |
1774 | |
1775 | return 0; | |
1776 | } | |
1777 | ||
1778 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1779 | { | |
1780 | int i, r; | |
1781 | ||
3e96dbfd AD |
1782 | /* need to disable SMC first */ |
1783 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1784 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1785 | continue; |
a1255107 | 1786 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1787 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1788 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1789 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1790 | if (r) { |
1791 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1792 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1793 | return r; |
1794 | } | |
a1255107 | 1795 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1796 | /* XXX handle errors */ |
1797 | if (r) { | |
1798 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1799 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1800 | } |
a1255107 | 1801 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1802 | break; |
1803 | } | |
1804 | } | |
1805 | ||
d38ceaf9 | 1806 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1807 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1808 | continue; |
a1255107 | 1809 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1810 | amdgpu_wb_fini(adev); |
1811 | amdgpu_vram_scratch_fini(adev); | |
1812 | } | |
8201a67a RZ |
1813 | |
1814 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1815 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1816 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1817 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1818 | AMD_CG_STATE_UNGATE); | |
1819 | if (r) { | |
1820 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1821 | adev->ip_blocks[i].version->funcs->name, r); | |
1822 | return r; | |
1823 | } | |
2c1a2784 | 1824 | } |
8201a67a | 1825 | |
a1255107 | 1826 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1827 | /* XXX handle errors */ |
2c1a2784 | 1828 | if (r) { |
a1255107 AD |
1829 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1830 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1831 | } |
8201a67a | 1832 | |
a1255107 | 1833 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1834 | } |
1835 | ||
1836 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1837 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1838 | continue; |
a1255107 | 1839 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1840 | /* XXX handle errors */ |
2c1a2784 | 1841 | if (r) { |
a1255107 AD |
1842 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1843 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1844 | } |
a1255107 AD |
1845 | adev->ip_blocks[i].status.sw = false; |
1846 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1847 | } |
1848 | ||
a6dcfd9c | 1849 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1850 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1851 | continue; |
a1255107 AD |
1852 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1853 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1854 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1855 | } |
1856 | ||
3149d9da | 1857 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1858 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1859 | amdgpu_virt_release_full_gpu(adev, false); |
1860 | } | |
2493664f | 1861 | |
d38ceaf9 AD |
1862 | return 0; |
1863 | } | |
1864 | ||
2dc80b00 S |
1865 | static void amdgpu_late_init_func_handler(struct work_struct *work) |
1866 | { | |
1867 | struct amdgpu_device *adev = | |
1868 | container_of(work, struct amdgpu_device, late_init_work.work); | |
1869 | amdgpu_late_set_cg_state(adev); | |
1870 | } | |
1871 | ||
faefba95 | 1872 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1873 | { |
1874 | int i, r; | |
1875 | ||
e941ea99 XY |
1876 | if (amdgpu_sriov_vf(adev)) |
1877 | amdgpu_virt_request_full_gpu(adev, false); | |
1878 | ||
c5a93a28 FC |
1879 | /* ungate SMC block first */ |
1880 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1881 | AMD_CG_STATE_UNGATE); | |
1882 | if (r) { | |
1883 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1884 | } | |
1885 | ||
d38ceaf9 | 1886 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1887 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1888 | continue; |
1889 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1890 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1891 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1892 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1893 | if (r) { |
a1255107 AD |
1894 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1895 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1896 | } |
2c1a2784 | 1897 | } |
d38ceaf9 | 1898 | /* XXX handle errors */ |
a1255107 | 1899 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1900 | /* XXX handle errors */ |
2c1a2784 | 1901 | if (r) { |
a1255107 AD |
1902 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1903 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1904 | } |
d38ceaf9 AD |
1905 | } |
1906 | ||
e941ea99 XY |
1907 | if (amdgpu_sriov_vf(adev)) |
1908 | amdgpu_virt_release_full_gpu(adev, false); | |
1909 | ||
d38ceaf9 AD |
1910 | return 0; |
1911 | } | |
1912 | ||
e4f0fdcc | 1913 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1914 | { |
1915 | int i, r; | |
1916 | ||
2cb681b6 ML |
1917 | static enum amd_ip_block_type ip_order[] = { |
1918 | AMD_IP_BLOCK_TYPE_GMC, | |
1919 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1920 | AMD_IP_BLOCK_TYPE_IH, |
1921 | }; | |
a90ad3c2 | 1922 | |
2cb681b6 ML |
1923 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1924 | int j; | |
1925 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1926 | |
2cb681b6 ML |
1927 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1928 | block = &adev->ip_blocks[j]; | |
1929 | ||
1930 | if (block->version->type != ip_order[i] || | |
1931 | !block->status.valid) | |
1932 | continue; | |
1933 | ||
1934 | r = block->version->funcs->hw_init(adev); | |
1935 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1936 | } |
1937 | } | |
1938 | ||
1939 | return 0; | |
1940 | } | |
1941 | ||
e4f0fdcc | 1942 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1943 | { |
1944 | int i, r; | |
1945 | ||
2cb681b6 ML |
1946 | static enum amd_ip_block_type ip_order[] = { |
1947 | AMD_IP_BLOCK_TYPE_SMC, | |
1948 | AMD_IP_BLOCK_TYPE_DCE, | |
1949 | AMD_IP_BLOCK_TYPE_GFX, | |
1950 | AMD_IP_BLOCK_TYPE_SDMA, | |
1951 | AMD_IP_BLOCK_TYPE_VCE, | |
1952 | }; | |
a90ad3c2 | 1953 | |
2cb681b6 ML |
1954 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1955 | int j; | |
1956 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1957 | |
2cb681b6 ML |
1958 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1959 | block = &adev->ip_blocks[j]; | |
1960 | ||
1961 | if (block->version->type != ip_order[i] || | |
1962 | !block->status.valid) | |
1963 | continue; | |
1964 | ||
1965 | r = block->version->funcs->hw_init(adev); | |
1966 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1967 | } |
1968 | } | |
1969 | ||
1970 | return 0; | |
1971 | } | |
1972 | ||
fcf0649f | 1973 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1974 | { |
1975 | int i, r; | |
1976 | ||
a90ad3c2 ML |
1977 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1978 | if (!adev->ip_blocks[i].status.valid) | |
1979 | continue; | |
a90ad3c2 ML |
1980 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1981 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
fcf0649f CZ |
1982 | adev->ip_blocks[i].version->type == |
1983 | AMD_IP_BLOCK_TYPE_IH) { | |
1984 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1985 | if (r) { | |
1986 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1987 | adev->ip_blocks[i].version->funcs->name, r); | |
1988 | return r; | |
1989 | } | |
a90ad3c2 ML |
1990 | } |
1991 | } | |
1992 | ||
1993 | return 0; | |
1994 | } | |
1995 | ||
fcf0649f | 1996 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
1997 | { |
1998 | int i, r; | |
1999 | ||
2000 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2001 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2002 | continue; |
fcf0649f CZ |
2003 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
2004 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2005 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
2006 | continue; | |
a1255107 | 2007 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2008 | if (r) { |
a1255107 AD |
2009 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2010 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2011 | return r; |
2c1a2784 | 2012 | } |
d38ceaf9 AD |
2013 | } |
2014 | ||
2015 | return 0; | |
2016 | } | |
2017 | ||
fcf0649f CZ |
2018 | static int amdgpu_resume(struct amdgpu_device *adev) |
2019 | { | |
2020 | int r; | |
2021 | ||
2022 | r = amdgpu_resume_phase1(adev); | |
2023 | if (r) | |
2024 | return r; | |
2025 | r = amdgpu_resume_phase2(adev); | |
2026 | ||
2027 | return r; | |
2028 | } | |
2029 | ||
4e99a44e | 2030 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2031 | { |
a5bde2f9 AD |
2032 | if (adev->is_atom_fw) { |
2033 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2034 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2035 | } else { | |
2036 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2037 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2038 | } | |
048765ad AR |
2039 | } |
2040 | ||
d38ceaf9 AD |
2041 | /** |
2042 | * amdgpu_device_init - initialize the driver | |
2043 | * | |
2044 | * @adev: amdgpu_device pointer | |
2045 | * @pdev: drm dev pointer | |
2046 | * @pdev: pci dev pointer | |
2047 | * @flags: driver flags | |
2048 | * | |
2049 | * Initializes the driver info and hw (all asics). | |
2050 | * Returns 0 for success or an error on failure. | |
2051 | * Called at driver startup. | |
2052 | */ | |
2053 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2054 | struct drm_device *ddev, | |
2055 | struct pci_dev *pdev, | |
2056 | uint32_t flags) | |
2057 | { | |
2058 | int r, i; | |
2059 | bool runtime = false; | |
95844d20 | 2060 | u32 max_MBps; |
d38ceaf9 AD |
2061 | |
2062 | adev->shutdown = false; | |
2063 | adev->dev = &pdev->dev; | |
2064 | adev->ddev = ddev; | |
2065 | adev->pdev = pdev; | |
2066 | adev->flags = flags; | |
2f7d10b3 | 2067 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2068 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
6f02a696 | 2069 | adev->mc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2070 | adev->accel_working = false; |
2071 | adev->num_rings = 0; | |
2072 | adev->mman.buffer_funcs = NULL; | |
2073 | adev->mman.buffer_funcs_ring = NULL; | |
2074 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2075 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 2076 | adev->gart.gart_funcs = NULL; |
f54d1867 | 2077 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
2078 | |
2079 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2080 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2081 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2082 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2083 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2084 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2085 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2086 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2087 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2088 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2089 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2090 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2091 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2092 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2093 | ||
ccdbb20a | 2094 | |
3e39ab90 AD |
2095 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2096 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2097 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2098 | |
2099 | /* mutex initialization are all done here so we | |
2100 | * can recall function without having locking issues */ | |
d38ceaf9 | 2101 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2102 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2103 | mutex_init(&adev->pm.mutex); |
2104 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2105 | mutex_init(&adev->srbm_mutex); | |
2106 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
2107 | mutex_init(&adev->mn_lock); |
2108 | hash_init(adev->mn_hash); | |
2109 | ||
2110 | amdgpu_check_arguments(adev); | |
2111 | ||
d38ceaf9 AD |
2112 | spin_lock_init(&adev->mmio_idx_lock); |
2113 | spin_lock_init(&adev->smc_idx_lock); | |
2114 | spin_lock_init(&adev->pcie_idx_lock); | |
2115 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2116 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2117 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2118 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2119 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2120 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2121 | |
0c4e7fa5 CZ |
2122 | INIT_LIST_HEAD(&adev->shadow_list); |
2123 | mutex_init(&adev->shadow_list_lock); | |
2124 | ||
5c1354bd CZ |
2125 | INIT_LIST_HEAD(&adev->gtt_list); |
2126 | spin_lock_init(&adev->gtt_list_lock); | |
2127 | ||
795f2813 AR |
2128 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2129 | spin_lock_init(&adev->ring_lru_list_lock); | |
2130 | ||
2dc80b00 S |
2131 | INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); |
2132 | ||
0fa49558 AX |
2133 | /* Registers mapping */ |
2134 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2135 | if (adev->asic_type >= CHIP_BONAIRE) { |
2136 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2137 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2138 | } else { | |
2139 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2140 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2141 | } | |
d38ceaf9 | 2142 | |
d38ceaf9 AD |
2143 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2144 | if (adev->rmmio == NULL) { | |
2145 | return -ENOMEM; | |
2146 | } | |
2147 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2148 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2149 | ||
da69c161 KW |
2150 | if (adev->asic_type >= CHIP_BONAIRE) |
2151 | /* doorbell bar mapping */ | |
2152 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2153 | |
2154 | /* io port mapping */ | |
2155 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2156 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2157 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2158 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2159 | break; | |
2160 | } | |
2161 | } | |
2162 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2163 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2164 | |
2165 | /* early init functions */ | |
2166 | r = amdgpu_early_init(adev); | |
2167 | if (r) | |
2168 | return r; | |
2169 | ||
2170 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2171 | /* this will fail for cards that aren't VGA class devices, just | |
2172 | * ignore it */ | |
2173 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2174 | ||
2175 | if (amdgpu_runtime_pm == 1) | |
2176 | runtime = true; | |
e9bef455 | 2177 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2178 | runtime = true; |
84c8b22e LW |
2179 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2180 | vga_switcheroo_register_client(adev->pdev, | |
2181 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2182 | if (runtime) |
2183 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2184 | ||
2185 | /* Read BIOS */ | |
83ba126a AD |
2186 | if (!amdgpu_get_bios(adev)) { |
2187 | r = -EINVAL; | |
2188 | goto failed; | |
2189 | } | |
f7e9e9fe | 2190 | |
d38ceaf9 | 2191 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2192 | if (r) { |
2193 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
89041940 | 2194 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2195 | goto failed; |
2c1a2784 | 2196 | } |
d38ceaf9 | 2197 | |
4e99a44e ML |
2198 | /* detect if we are with an SRIOV vbios */ |
2199 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2200 | |
d38ceaf9 | 2201 | /* Post card if necessary */ |
bec86378 | 2202 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 2203 | if (!adev->bios) { |
bec86378 | 2204 | dev_err(adev->dev, "no vBIOS found\n"); |
89041940 | 2205 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); |
83ba126a AD |
2206 | r = -EINVAL; |
2207 | goto failed; | |
d38ceaf9 | 2208 | } |
bec86378 | 2209 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2210 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2211 | if (r) { | |
2212 | dev_err(adev->dev, "gpu post error!\n"); | |
89041940 | 2213 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0); |
4e99a44e ML |
2214 | goto failed; |
2215 | } | |
2216 | } else { | |
2217 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
2218 | } |
2219 | ||
88b64e95 AD |
2220 | if (adev->is_atom_fw) { |
2221 | /* Initialize clocks */ | |
2222 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2223 | if (r) { | |
2224 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
2225 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); | |
2226 | goto failed; | |
2227 | } | |
2228 | } else { | |
a5bde2f9 AD |
2229 | /* Initialize clocks */ |
2230 | r = amdgpu_atombios_get_clock_info(adev); | |
2231 | if (r) { | |
2232 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
89041940 GW |
2233 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
2234 | goto failed; | |
a5bde2f9 AD |
2235 | } |
2236 | /* init i2c buses */ | |
2237 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2238 | } |
d38ceaf9 AD |
2239 | |
2240 | /* Fence driver */ | |
2241 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2242 | if (r) { |
2243 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
89041940 | 2244 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2245 | goto failed; |
2c1a2784 | 2246 | } |
d38ceaf9 AD |
2247 | |
2248 | /* init the mode config */ | |
2249 | drm_mode_config_init(adev->ddev); | |
2250 | ||
2251 | r = amdgpu_init(adev); | |
2252 | if (r) { | |
2c1a2784 | 2253 | dev_err(adev->dev, "amdgpu_init failed\n"); |
89041940 | 2254 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
d38ceaf9 | 2255 | amdgpu_fini(adev); |
83ba126a | 2256 | goto failed; |
d38ceaf9 AD |
2257 | } |
2258 | ||
2259 | adev->accel_working = true; | |
2260 | ||
e59c0205 AX |
2261 | amdgpu_vm_check_compute_bug(adev); |
2262 | ||
95844d20 MO |
2263 | /* Initialize the buffer migration limit. */ |
2264 | if (amdgpu_moverate >= 0) | |
2265 | max_MBps = amdgpu_moverate; | |
2266 | else | |
2267 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2268 | /* Get a log2 for easy divisions. */ | |
2269 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2270 | ||
d38ceaf9 AD |
2271 | r = amdgpu_ib_pool_init(adev); |
2272 | if (r) { | |
2273 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
89041940 | 2274 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2275 | goto failed; |
d38ceaf9 AD |
2276 | } |
2277 | ||
2278 | r = amdgpu_ib_ring_tests(adev); | |
2279 | if (r) | |
2280 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2281 | ||
9bc92b9c ML |
2282 | amdgpu_fbdev_init(adev); |
2283 | ||
d38ceaf9 | 2284 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2285 | if (r) |
d38ceaf9 | 2286 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2287 | |
2288 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2289 | if (r) |
d38ceaf9 | 2290 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2291 | |
4f0955fc HR |
2292 | r = amdgpu_debugfs_test_ib_ring_init(adev); |
2293 | if (r) | |
2294 | DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); | |
2295 | ||
50ab2533 | 2296 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2297 | if (r) |
50ab2533 | 2298 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2299 | |
d38ceaf9 AD |
2300 | if ((amdgpu_testing & 1)) { |
2301 | if (adev->accel_working) | |
2302 | amdgpu_test_moves(adev); | |
2303 | else | |
2304 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2305 | } | |
d38ceaf9 AD |
2306 | if (amdgpu_benchmarking) { |
2307 | if (adev->accel_working) | |
2308 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2309 | else | |
2310 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2311 | } | |
2312 | ||
2313 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2314 | * explicit gating rather than handling it automatically. | |
2315 | */ | |
2316 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2317 | if (r) { |
2318 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
89041940 | 2319 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2320 | goto failed; |
2c1a2784 | 2321 | } |
d38ceaf9 AD |
2322 | |
2323 | return 0; | |
83ba126a AD |
2324 | |
2325 | failed: | |
89041940 | 2326 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2327 | if (runtime) |
2328 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2329 | return r; | |
d38ceaf9 AD |
2330 | } |
2331 | ||
d38ceaf9 AD |
2332 | /** |
2333 | * amdgpu_device_fini - tear down the driver | |
2334 | * | |
2335 | * @adev: amdgpu_device pointer | |
2336 | * | |
2337 | * Tear down the driver info (all asics). | |
2338 | * Called at driver shutdown. | |
2339 | */ | |
2340 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2341 | { | |
2342 | int r; | |
2343 | ||
2344 | DRM_INFO("amdgpu: finishing device.\n"); | |
2345 | adev->shutdown = true; | |
db2c2a97 PD |
2346 | if (adev->mode_info.mode_config_initialized) |
2347 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2348 | /* evict vram memory */ |
2349 | amdgpu_bo_evict_vram(adev); | |
2350 | amdgpu_ib_pool_fini(adev); | |
2351 | amdgpu_fence_driver_fini(adev); | |
2352 | amdgpu_fbdev_fini(adev); | |
2353 | r = amdgpu_fini(adev); | |
ab4fe3e1 HR |
2354 | if (adev->firmware.gpu_info_fw) { |
2355 | release_firmware(adev->firmware.gpu_info_fw); | |
2356 | adev->firmware.gpu_info_fw = NULL; | |
2357 | } | |
d38ceaf9 | 2358 | adev->accel_working = false; |
2dc80b00 | 2359 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 AD |
2360 | /* free i2c buses */ |
2361 | amdgpu_i2c_fini(adev); | |
2362 | amdgpu_atombios_fini(adev); | |
2363 | kfree(adev->bios); | |
2364 | adev->bios = NULL; | |
84c8b22e LW |
2365 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2366 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2367 | if (adev->flags & AMD_IS_PX) |
2368 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2369 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2370 | if (adev->rio_mem) | |
2371 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2372 | adev->rio_mem = NULL; | |
2373 | iounmap(adev->rmmio); | |
2374 | adev->rmmio = NULL; | |
da69c161 KW |
2375 | if (adev->asic_type >= CHIP_BONAIRE) |
2376 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2377 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2378 | } |
2379 | ||
2380 | ||
2381 | /* | |
2382 | * Suspend & resume. | |
2383 | */ | |
2384 | /** | |
810ddc3a | 2385 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2386 | * |
2387 | * @pdev: drm dev pointer | |
2388 | * @state: suspend state | |
2389 | * | |
2390 | * Puts the hw in the suspend state (all asics). | |
2391 | * Returns 0 for success or an error on failure. | |
2392 | * Called at driver suspend. | |
2393 | */ | |
810ddc3a | 2394 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2395 | { |
2396 | struct amdgpu_device *adev; | |
2397 | struct drm_crtc *crtc; | |
2398 | struct drm_connector *connector; | |
5ceb54c6 | 2399 | int r; |
d38ceaf9 AD |
2400 | |
2401 | if (dev == NULL || dev->dev_private == NULL) { | |
2402 | return -ENODEV; | |
2403 | } | |
2404 | ||
2405 | adev = dev->dev_private; | |
2406 | ||
2407 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2408 | return 0; | |
2409 | ||
2410 | drm_kms_helper_poll_disable(dev); | |
2411 | ||
2412 | /* turn off display hw */ | |
4c7fbc39 | 2413 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2414 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2415 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2416 | } | |
4c7fbc39 | 2417 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2418 | |
ba997709 YZ |
2419 | amdgpu_amdkfd_suspend(adev); |
2420 | ||
756e6880 | 2421 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2422 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2423 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2424 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2425 | struct amdgpu_bo *robj; | |
2426 | ||
756e6880 AD |
2427 | if (amdgpu_crtc->cursor_bo) { |
2428 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2429 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2430 | if (r == 0) { |
2431 | amdgpu_bo_unpin(aobj); | |
2432 | amdgpu_bo_unreserve(aobj); | |
2433 | } | |
2434 | } | |
2435 | ||
d38ceaf9 AD |
2436 | if (rfb == NULL || rfb->obj == NULL) { |
2437 | continue; | |
2438 | } | |
2439 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2440 | /* don't unpin kernel fb objects */ | |
2441 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2442 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2443 | if (r == 0) { |
2444 | amdgpu_bo_unpin(robj); | |
2445 | amdgpu_bo_unreserve(robj); | |
2446 | } | |
2447 | } | |
2448 | } | |
2449 | /* evict vram memory */ | |
2450 | amdgpu_bo_evict_vram(adev); | |
2451 | ||
5ceb54c6 | 2452 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2453 | |
2454 | r = amdgpu_suspend(adev); | |
2455 | ||
a0a71e49 AD |
2456 | /* evict remaining vram memory |
2457 | * This second call to evict vram is to evict the gart page table | |
2458 | * using the CPU. | |
2459 | */ | |
d38ceaf9 AD |
2460 | amdgpu_bo_evict_vram(adev); |
2461 | ||
d05da0e2 | 2462 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
2463 | pci_save_state(dev->pdev); |
2464 | if (suspend) { | |
2465 | /* Shut down the device */ | |
2466 | pci_disable_device(dev->pdev); | |
2467 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2468 | } else { |
2469 | r = amdgpu_asic_reset(adev); | |
2470 | if (r) | |
2471 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2472 | } |
2473 | ||
2474 | if (fbcon) { | |
2475 | console_lock(); | |
2476 | amdgpu_fbdev_set_suspend(adev, 1); | |
2477 | console_unlock(); | |
2478 | } | |
2479 | return 0; | |
2480 | } | |
2481 | ||
2482 | /** | |
810ddc3a | 2483 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2484 | * |
2485 | * @pdev: drm dev pointer | |
2486 | * | |
2487 | * Bring the hw back to operating state (all asics). | |
2488 | * Returns 0 for success or an error on failure. | |
2489 | * Called at driver resume. | |
2490 | */ | |
810ddc3a | 2491 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2492 | { |
2493 | struct drm_connector *connector; | |
2494 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2495 | struct drm_crtc *crtc; |
03161a6e | 2496 | int r = 0; |
d38ceaf9 AD |
2497 | |
2498 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2499 | return 0; | |
2500 | ||
74b0b157 | 2501 | if (fbcon) |
d38ceaf9 | 2502 | console_lock(); |
74b0b157 | 2503 | |
d38ceaf9 AD |
2504 | if (resume) { |
2505 | pci_set_power_state(dev->pdev, PCI_D0); | |
2506 | pci_restore_state(dev->pdev); | |
74b0b157 | 2507 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2508 | if (r) |
2509 | goto unlock; | |
d38ceaf9 | 2510 | } |
d05da0e2 | 2511 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2512 | |
2513 | /* post card */ | |
c836fec5 | 2514 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2515 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2516 | if (r) | |
2517 | DRM_ERROR("amdgpu asic init failed\n"); | |
2518 | } | |
d38ceaf9 AD |
2519 | |
2520 | r = amdgpu_resume(adev); | |
e6707218 | 2521 | if (r) { |
ca198528 | 2522 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2523 | goto unlock; |
e6707218 | 2524 | } |
5ceb54c6 AD |
2525 | amdgpu_fence_driver_resume(adev); |
2526 | ||
ca198528 FC |
2527 | if (resume) { |
2528 | r = amdgpu_ib_ring_tests(adev); | |
2529 | if (r) | |
2530 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2531 | } | |
d38ceaf9 AD |
2532 | |
2533 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2534 | if (r) |
2535 | goto unlock; | |
d38ceaf9 | 2536 | |
756e6880 AD |
2537 | /* pin cursors */ |
2538 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2539 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2540 | ||
2541 | if (amdgpu_crtc->cursor_bo) { | |
2542 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2543 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2544 | if (r == 0) { |
2545 | r = amdgpu_bo_pin(aobj, | |
2546 | AMDGPU_GEM_DOMAIN_VRAM, | |
2547 | &amdgpu_crtc->cursor_addr); | |
2548 | if (r != 0) | |
2549 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2550 | amdgpu_bo_unreserve(aobj); | |
2551 | } | |
2552 | } | |
2553 | } | |
ba997709 YZ |
2554 | r = amdgpu_amdkfd_resume(adev); |
2555 | if (r) | |
2556 | return r; | |
756e6880 | 2557 | |
d38ceaf9 AD |
2558 | /* blat the mode back in */ |
2559 | if (fbcon) { | |
2560 | drm_helper_resume_force_mode(dev); | |
2561 | /* turn on display hw */ | |
4c7fbc39 | 2562 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2563 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2564 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2565 | } | |
4c7fbc39 | 2566 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2567 | } |
2568 | ||
2569 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2570 | |
2571 | /* | |
2572 | * Most of the connector probing functions try to acquire runtime pm | |
2573 | * refs to ensure that the GPU is powered on when connector polling is | |
2574 | * performed. Since we're calling this from a runtime PM callback, | |
2575 | * trying to acquire rpm refs will cause us to deadlock. | |
2576 | * | |
2577 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2578 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2579 | */ | |
2580 | #ifdef CONFIG_PM | |
2581 | dev->dev->power.disable_depth++; | |
2582 | #endif | |
54fb2a5c | 2583 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2584 | #ifdef CONFIG_PM |
2585 | dev->dev->power.disable_depth--; | |
2586 | #endif | |
d38ceaf9 | 2587 | |
03161a6e | 2588 | if (fbcon) |
d38ceaf9 | 2589 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2590 | |
2591 | unlock: | |
2592 | if (fbcon) | |
d38ceaf9 | 2593 | console_unlock(); |
d38ceaf9 | 2594 | |
03161a6e | 2595 | return r; |
d38ceaf9 AD |
2596 | } |
2597 | ||
63fbf42f CZ |
2598 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2599 | { | |
2600 | int i; | |
2601 | bool asic_hang = false; | |
2602 | ||
2603 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2604 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2605 | continue; |
a1255107 AD |
2606 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2607 | adev->ip_blocks[i].status.hang = | |
2608 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2609 | if (adev->ip_blocks[i].status.hang) { | |
2610 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2611 | asic_hang = true; |
2612 | } | |
2613 | } | |
2614 | return asic_hang; | |
2615 | } | |
2616 | ||
4d446656 | 2617 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2618 | { |
2619 | int i, r = 0; | |
2620 | ||
2621 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2622 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2623 | continue; |
a1255107 AD |
2624 | if (adev->ip_blocks[i].status.hang && |
2625 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2626 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2627 | if (r) |
2628 | return r; | |
2629 | } | |
2630 | } | |
2631 | ||
2632 | return 0; | |
2633 | } | |
2634 | ||
35d782fe CZ |
2635 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2636 | { | |
da146d3b AD |
2637 | int i; |
2638 | ||
2639 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2640 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2641 | continue; |
a1255107 AD |
2642 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2643 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2644 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2645 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2646 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2647 | DRM_INFO("Some block need full reset!\n"); |
2648 | return true; | |
2649 | } | |
2650 | } | |
35d782fe CZ |
2651 | } |
2652 | return false; | |
2653 | } | |
2654 | ||
2655 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2656 | { | |
2657 | int i, r = 0; | |
2658 | ||
2659 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2660 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2661 | continue; |
a1255107 AD |
2662 | if (adev->ip_blocks[i].status.hang && |
2663 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2664 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2665 | if (r) |
2666 | return r; | |
2667 | } | |
2668 | } | |
2669 | ||
2670 | return 0; | |
2671 | } | |
2672 | ||
2673 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2674 | { | |
2675 | int i, r = 0; | |
2676 | ||
2677 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2678 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2679 | continue; |
a1255107 AD |
2680 | if (adev->ip_blocks[i].status.hang && |
2681 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2682 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2683 | if (r) |
2684 | return r; | |
2685 | } | |
2686 | ||
2687 | return 0; | |
2688 | } | |
2689 | ||
3ad81f16 CZ |
2690 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2691 | { | |
2692 | if (adev->flags & AMD_IS_APU) | |
2693 | return false; | |
2694 | ||
2695 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2696 | } | |
2697 | ||
53cdccd5 CZ |
2698 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2699 | struct amdgpu_ring *ring, | |
2700 | struct amdgpu_bo *bo, | |
f54d1867 | 2701 | struct dma_fence **fence) |
53cdccd5 CZ |
2702 | { |
2703 | uint32_t domain; | |
2704 | int r; | |
2705 | ||
23d2e504 RH |
2706 | if (!bo->shadow) |
2707 | return 0; | |
2708 | ||
1d284797 | 2709 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2710 | if (r) |
2711 | return r; | |
2712 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2713 | /* if bo has been evicted, then no need to recover */ | |
2714 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2715 | r = amdgpu_bo_validate(bo->shadow); |
2716 | if (r) { | |
2717 | DRM_ERROR("bo validate failed!\n"); | |
2718 | goto err; | |
2719 | } | |
2720 | ||
2721 | r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem); | |
2722 | if (r) { | |
2723 | DRM_ERROR("%p bind failed\n", bo->shadow); | |
2724 | goto err; | |
2725 | } | |
2726 | ||
23d2e504 | 2727 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2728 | NULL, fence, true); |
23d2e504 RH |
2729 | if (r) { |
2730 | DRM_ERROR("recover page table failed!\n"); | |
2731 | goto err; | |
2732 | } | |
2733 | } | |
53cdccd5 | 2734 | err: |
23d2e504 RH |
2735 | amdgpu_bo_unreserve(bo); |
2736 | return r; | |
53cdccd5 CZ |
2737 | } |
2738 | ||
a90ad3c2 ML |
2739 | /** |
2740 | * amdgpu_sriov_gpu_reset - reset the asic | |
2741 | * | |
2742 | * @adev: amdgpu device pointer | |
7225f873 | 2743 | * @job: which job trigger hang |
a90ad3c2 ML |
2744 | * |
2745 | * Attempt the reset the GPU if it has hung (all asics). | |
2746 | * for SRIOV case. | |
2747 | * Returns 0 for success or an error on failure. | |
2748 | */ | |
7225f873 | 2749 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) |
a90ad3c2 | 2750 | { |
65781c78 | 2751 | int i, j, r = 0; |
a90ad3c2 ML |
2752 | int resched; |
2753 | struct amdgpu_bo *bo, *tmp; | |
2754 | struct amdgpu_ring *ring; | |
2755 | struct dma_fence *fence = NULL, *next = NULL; | |
2756 | ||
147b5983 | 2757 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2758 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2759 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2760 | |
2761 | /* block TTM */ | |
2762 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2763 | ||
65781c78 ML |
2764 | /* we start from the ring trigger GPU hang */ |
2765 | j = job ? job->ring->idx : 0; | |
a90ad3c2 | 2766 | |
65781c78 ML |
2767 | /* block scheduler */ |
2768 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { | |
2769 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2770 | if (!ring || !ring->sched.thread) |
2771 | continue; | |
2772 | ||
2773 | kthread_park(ring->sched.thread); | |
65781c78 ML |
2774 | |
2775 | if (job && j != i) | |
2776 | continue; | |
2777 | ||
4f059ecd | 2778 | /* here give the last chance to check if job removed from mirror-list |
65781c78 | 2779 | * since we already pay some time on kthread_park */ |
4f059ecd | 2780 | if (job && list_empty(&job->base.node)) { |
65781c78 ML |
2781 | kthread_unpark(ring->sched.thread); |
2782 | goto give_up_reset; | |
2783 | } | |
2784 | ||
2785 | if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) | |
2786 | amd_sched_job_kickout(&job->base); | |
2787 | ||
2788 | /* only do job_reset on the hang ring if @job not NULL */ | |
a90ad3c2 | 2789 | amd_sched_hw_job_reset(&ring->sched); |
a90ad3c2 | 2790 | |
65781c78 ML |
2791 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2792 | amdgpu_fence_driver_force_completion_ring(ring); | |
2793 | } | |
a90ad3c2 ML |
2794 | |
2795 | /* request to take full control of GPU before re-initialization */ | |
7225f873 | 2796 | if (job) |
a90ad3c2 ML |
2797 | amdgpu_virt_reset_gpu(adev); |
2798 | else | |
2799 | amdgpu_virt_request_full_gpu(adev, true); | |
2800 | ||
2801 | ||
2802 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2803 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2804 | |
2805 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2806 | amdgpu_ttm_recover_gart(adev); | |
2807 | ||
2808 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2809 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2810 | |
2811 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2812 | ||
2813 | if (amdgpu_ib_ring_tests(adev)) | |
2814 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2815 | ||
2816 | /* release full control of GPU after ib test */ | |
2817 | amdgpu_virt_release_full_gpu(adev, true); | |
2818 | ||
2819 | DRM_INFO("recover vram bo from shadow\n"); | |
2820 | ||
2821 | ring = adev->mman.buffer_funcs_ring; | |
2822 | mutex_lock(&adev->shadow_list_lock); | |
2823 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2824 | next = NULL; |
a90ad3c2 ML |
2825 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2826 | if (fence) { | |
2827 | r = dma_fence_wait(fence, false); | |
2828 | if (r) { | |
2829 | WARN(r, "recovery from shadow isn't completed\n"); | |
2830 | break; | |
2831 | } | |
2832 | } | |
2833 | ||
2834 | dma_fence_put(fence); | |
2835 | fence = next; | |
2836 | } | |
2837 | mutex_unlock(&adev->shadow_list_lock); | |
2838 | ||
2839 | if (fence) { | |
2840 | r = dma_fence_wait(fence, false); | |
2841 | if (r) | |
2842 | WARN(r, "recovery from shadow isn't completed\n"); | |
2843 | } | |
2844 | dma_fence_put(fence); | |
2845 | ||
65781c78 ML |
2846 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { |
2847 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2848 | if (!ring || !ring->sched.thread) |
2849 | continue; | |
2850 | ||
65781c78 ML |
2851 | if (job && j != i) { |
2852 | kthread_unpark(ring->sched.thread); | |
2853 | continue; | |
2854 | } | |
2855 | ||
a90ad3c2 ML |
2856 | amd_sched_job_recovery(&ring->sched); |
2857 | kthread_unpark(ring->sched.thread); | |
2858 | } | |
2859 | ||
2860 | drm_helper_resume_force_mode(adev->ddev); | |
65781c78 | 2861 | give_up_reset: |
a90ad3c2 ML |
2862 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); |
2863 | if (r) { | |
2864 | /* bad news, how to tell it to userspace ? */ | |
2865 | dev_info(adev->dev, "GPU reset failed\n"); | |
65781c78 ML |
2866 | } else { |
2867 | dev_info(adev->dev, "GPU reset successed!\n"); | |
a90ad3c2 ML |
2868 | } |
2869 | ||
1fb37a3d | 2870 | adev->gfx.in_reset = false; |
147b5983 | 2871 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2872 | return r; |
2873 | } | |
2874 | ||
d38ceaf9 AD |
2875 | /** |
2876 | * amdgpu_gpu_reset - reset the asic | |
2877 | * | |
2878 | * @adev: amdgpu device pointer | |
2879 | * | |
2880 | * Attempt the reset the GPU if it has hung (all asics). | |
2881 | * Returns 0 for success or an error on failure. | |
2882 | */ | |
2883 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2884 | { | |
d38ceaf9 AD |
2885 | int i, r; |
2886 | int resched; | |
0c49e0b8 | 2887 | bool need_full_reset, vram_lost = false; |
fb140b29 | 2888 | |
63fbf42f CZ |
2889 | if (!amdgpu_check_soft_reset(adev)) { |
2890 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2891 | return 0; | |
2892 | } | |
d38ceaf9 | 2893 | |
d94aed5a | 2894 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2895 | |
a3c47d6b CZ |
2896 | /* block TTM */ |
2897 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2898 | ||
0875dc9e CZ |
2899 | /* block scheduler */ |
2900 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2901 | struct amdgpu_ring *ring = adev->rings[i]; | |
2902 | ||
51687759 | 2903 | if (!ring || !ring->sched.thread) |
0875dc9e CZ |
2904 | continue; |
2905 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2906 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2907 | } |
2200edac CZ |
2908 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2909 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2910 | |
35d782fe | 2911 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2912 | |
35d782fe CZ |
2913 | if (!need_full_reset) { |
2914 | amdgpu_pre_soft_reset(adev); | |
2915 | r = amdgpu_soft_reset(adev); | |
2916 | amdgpu_post_soft_reset(adev); | |
2917 | if (r || amdgpu_check_soft_reset(adev)) { | |
2918 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2919 | need_full_reset = true; | |
2920 | } | |
f1aa7e08 CZ |
2921 | } |
2922 | ||
35d782fe | 2923 | if (need_full_reset) { |
35d782fe | 2924 | r = amdgpu_suspend(adev); |
bfa99269 | 2925 | |
35d782fe | 2926 | retry: |
d05da0e2 | 2927 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2928 | r = amdgpu_asic_reset(adev); |
d05da0e2 | 2929 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2930 | /* post card */ |
2931 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2932 | ||
2933 | if (!r) { | |
2934 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
fcf0649f CZ |
2935 | r = amdgpu_resume_phase1(adev); |
2936 | if (r) | |
2937 | goto out; | |
0c49e0b8 | 2938 | vram_lost = amdgpu_check_vram_lost(adev); |
f1892138 | 2939 | if (vram_lost) { |
0c49e0b8 | 2940 | DRM_ERROR("VRAM is lost!\n"); |
f1892138 CZ |
2941 | atomic_inc(&adev->vram_lost_counter); |
2942 | } | |
fcf0649f CZ |
2943 | r = amdgpu_ttm_recover_gart(adev); |
2944 | if (r) | |
2945 | goto out; | |
2946 | r = amdgpu_resume_phase2(adev); | |
2947 | if (r) | |
2948 | goto out; | |
0c49e0b8 CZ |
2949 | if (vram_lost) |
2950 | amdgpu_fill_reset_magic(adev); | |
35d782fe | 2951 | } |
d38ceaf9 | 2952 | } |
fcf0649f | 2953 | out: |
d38ceaf9 | 2954 | if (!r) { |
e72cfd58 | 2955 | amdgpu_irq_gpu_reset_resume_helper(adev); |
1f465087 CZ |
2956 | r = amdgpu_ib_ring_tests(adev); |
2957 | if (r) { | |
2958 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2959 | r = amdgpu_suspend(adev); |
53cdccd5 | 2960 | need_full_reset = true; |
40019dc4 | 2961 | goto retry; |
1f465087 | 2962 | } |
53cdccd5 CZ |
2963 | /** |
2964 | * recovery vm page tables, since we cannot depend on VRAM is | |
2965 | * consistent after gpu full reset. | |
2966 | */ | |
2967 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2968 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2969 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2970 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2971 | |
2972 | DRM_INFO("recover vram bo from shadow\n"); | |
2973 | mutex_lock(&adev->shadow_list_lock); | |
2974 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2975 | next = NULL; |
53cdccd5 CZ |
2976 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2977 | if (fence) { | |
f54d1867 | 2978 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2979 | if (r) { |
1d7b17b0 | 2980 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2981 | break; |
2982 | } | |
2983 | } | |
1f465087 | 2984 | |
f54d1867 | 2985 | dma_fence_put(fence); |
53cdccd5 CZ |
2986 | fence = next; |
2987 | } | |
2988 | mutex_unlock(&adev->shadow_list_lock); | |
2989 | if (fence) { | |
f54d1867 | 2990 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2991 | if (r) |
1d7b17b0 | 2992 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2993 | } |
f54d1867 | 2994 | dma_fence_put(fence); |
53cdccd5 | 2995 | } |
d38ceaf9 AD |
2996 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2997 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
2998 | |
2999 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 3000 | continue; |
53cdccd5 | 3001 | |
aa1c8900 | 3002 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 3003 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 3004 | } |
d38ceaf9 | 3005 | } else { |
2200edac | 3006 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
89041940 | 3007 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r); |
d38ceaf9 | 3008 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
51687759 | 3009 | if (adev->rings[i] && adev->rings[i]->sched.thread) { |
0875dc9e | 3010 | kthread_unpark(adev->rings[i]->sched.thread); |
0875dc9e | 3011 | } |
d38ceaf9 AD |
3012 | } |
3013 | } | |
3014 | ||
3015 | drm_helper_resume_force_mode(adev->ddev); | |
3016 | ||
3017 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
89041940 | 3018 | if (r) { |
d38ceaf9 AD |
3019 | /* bad news, how to tell it to userspace ? */ |
3020 | dev_info(adev->dev, "GPU reset failed\n"); | |
89041940 GW |
3021 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
3022 | } | |
3023 | else { | |
6643be65 | 3024 | dev_info(adev->dev, "GPU reset successed!\n"); |
89041940 | 3025 | } |
d38ceaf9 | 3026 | |
89041940 | 3027 | amdgpu_vf_error_trans_all(adev); |
d38ceaf9 AD |
3028 | return r; |
3029 | } | |
3030 | ||
d0dd7f0c AD |
3031 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
3032 | { | |
3033 | u32 mask; | |
3034 | int ret; | |
3035 | ||
cd474ba0 AD |
3036 | if (amdgpu_pcie_gen_cap) |
3037 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3038 | |
cd474ba0 AD |
3039 | if (amdgpu_pcie_lane_cap) |
3040 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3041 | |
cd474ba0 AD |
3042 | /* covers APUs as well */ |
3043 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3044 | if (adev->pm.pcie_gen_mask == 0) | |
3045 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3046 | if (adev->pm.pcie_mlw_mask == 0) | |
3047 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3048 | return; |
cd474ba0 | 3049 | } |
d0dd7f0c | 3050 | |
cd474ba0 AD |
3051 | if (adev->pm.pcie_gen_mask == 0) { |
3052 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
3053 | if (!ret) { | |
3054 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3055 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3056 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3057 | ||
3058 | if (mask & DRM_PCIE_SPEED_25) | |
3059 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3060 | if (mask & DRM_PCIE_SPEED_50) | |
3061 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3062 | if (mask & DRM_PCIE_SPEED_80) | |
3063 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3064 | } else { | |
3065 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3066 | } | |
3067 | } | |
3068 | if (adev->pm.pcie_mlw_mask == 0) { | |
3069 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3070 | if (!ret) { | |
3071 | switch (mask) { | |
3072 | case 32: | |
3073 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3074 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3075 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3076 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3077 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3078 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3079 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3080 | break; | |
3081 | case 16: | |
3082 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3083 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3084 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3085 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3086 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3087 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3088 | break; | |
3089 | case 12: | |
3090 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3091 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3092 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3093 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3094 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3095 | break; | |
3096 | case 8: | |
3097 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3098 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3099 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3100 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3101 | break; | |
3102 | case 4: | |
3103 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3104 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3105 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3106 | break; | |
3107 | case 2: | |
3108 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3109 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3110 | break; | |
3111 | case 1: | |
3112 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3113 | break; | |
3114 | default: | |
3115 | break; | |
3116 | } | |
3117 | } else { | |
3118 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3119 | } |
3120 | } | |
3121 | } | |
d38ceaf9 AD |
3122 | |
3123 | /* | |
3124 | * Debugfs | |
3125 | */ | |
3126 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3127 | const struct drm_info_list *files, |
d38ceaf9 AD |
3128 | unsigned nfiles) |
3129 | { | |
3130 | unsigned i; | |
3131 | ||
3132 | for (i = 0; i < adev->debugfs_count; i++) { | |
3133 | if (adev->debugfs[i].files == files) { | |
3134 | /* Already registered */ | |
3135 | return 0; | |
3136 | } | |
3137 | } | |
3138 | ||
3139 | i = adev->debugfs_count + 1; | |
3140 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3141 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3142 | DRM_ERROR("Report so we increase " | |
3143 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3144 | return -EINVAL; | |
3145 | } | |
3146 | adev->debugfs[adev->debugfs_count].files = files; | |
3147 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3148 | adev->debugfs_count = i; | |
3149 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3150 | drm_debugfs_create_files(files, nfiles, |
3151 | adev->ddev->primary->debugfs_root, | |
3152 | adev->ddev->primary); | |
3153 | #endif | |
3154 | return 0; | |
3155 | } | |
3156 | ||
d38ceaf9 AD |
3157 | #if defined(CONFIG_DEBUG_FS) |
3158 | ||
3159 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3160 | size_t size, loff_t *pos) | |
3161 | { | |
45063097 | 3162 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3163 | ssize_t result = 0; |
3164 | int r; | |
bd12267d | 3165 | bool pm_pg_lock, use_bank; |
56628159 | 3166 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3167 | |
3168 | if (size & 0x3 || *pos & 0x3) | |
3169 | return -EINVAL; | |
3170 | ||
bd12267d TSD |
3171 | /* are we reading registers for which a PG lock is necessary? */ |
3172 | pm_pg_lock = (*pos >> 23) & 1; | |
3173 | ||
56628159 TSD |
3174 | if (*pos & (1ULL << 62)) { |
3175 | se_bank = (*pos >> 24) & 0x3FF; | |
3176 | sh_bank = (*pos >> 34) & 0x3FF; | |
3177 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
3178 | |
3179 | if (se_bank == 0x3FF) | |
3180 | se_bank = 0xFFFFFFFF; | |
3181 | if (sh_bank == 0x3FF) | |
3182 | sh_bank = 0xFFFFFFFF; | |
3183 | if (instance_bank == 0x3FF) | |
3184 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3185 | use_bank = 1; |
56628159 TSD |
3186 | } else { |
3187 | use_bank = 0; | |
3188 | } | |
3189 | ||
801a6aa9 | 3190 | *pos &= (1UL << 22) - 1; |
bd12267d | 3191 | |
56628159 | 3192 | if (use_bank) { |
32977f93 TSD |
3193 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3194 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3195 | return -EINVAL; |
3196 | mutex_lock(&adev->grbm_idx_mutex); | |
3197 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3198 | sh_bank, instance_bank); | |
3199 | } | |
3200 | ||
bd12267d TSD |
3201 | if (pm_pg_lock) |
3202 | mutex_lock(&adev->pm.mutex); | |
3203 | ||
d38ceaf9 AD |
3204 | while (size) { |
3205 | uint32_t value; | |
3206 | ||
3207 | if (*pos > adev->rmmio_size) | |
56628159 | 3208 | goto end; |
d38ceaf9 AD |
3209 | |
3210 | value = RREG32(*pos >> 2); | |
3211 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3212 | if (r) { |
3213 | result = r; | |
3214 | goto end; | |
3215 | } | |
d38ceaf9 AD |
3216 | |
3217 | result += 4; | |
3218 | buf += 4; | |
3219 | *pos += 4; | |
3220 | size -= 4; | |
3221 | } | |
3222 | ||
56628159 TSD |
3223 | end: |
3224 | if (use_bank) { | |
3225 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3226 | mutex_unlock(&adev->grbm_idx_mutex); | |
3227 | } | |
3228 | ||
bd12267d TSD |
3229 | if (pm_pg_lock) |
3230 | mutex_unlock(&adev->pm.mutex); | |
3231 | ||
d38ceaf9 AD |
3232 | return result; |
3233 | } | |
3234 | ||
3235 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3236 | size_t size, loff_t *pos) | |
3237 | { | |
45063097 | 3238 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3239 | ssize_t result = 0; |
3240 | int r; | |
394fdde2 TSD |
3241 | bool pm_pg_lock, use_bank; |
3242 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3243 | |
3244 | if (size & 0x3 || *pos & 0x3) | |
3245 | return -EINVAL; | |
3246 | ||
394fdde2 TSD |
3247 | /* are we reading registers for which a PG lock is necessary? */ |
3248 | pm_pg_lock = (*pos >> 23) & 1; | |
3249 | ||
3250 | if (*pos & (1ULL << 62)) { | |
3251 | se_bank = (*pos >> 24) & 0x3FF; | |
3252 | sh_bank = (*pos >> 34) & 0x3FF; | |
3253 | instance_bank = (*pos >> 44) & 0x3FF; | |
3254 | ||
3255 | if (se_bank == 0x3FF) | |
3256 | se_bank = 0xFFFFFFFF; | |
3257 | if (sh_bank == 0x3FF) | |
3258 | sh_bank = 0xFFFFFFFF; | |
3259 | if (instance_bank == 0x3FF) | |
3260 | instance_bank = 0xFFFFFFFF; | |
3261 | use_bank = 1; | |
3262 | } else { | |
3263 | use_bank = 0; | |
3264 | } | |
3265 | ||
801a6aa9 | 3266 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3267 | |
3268 | if (use_bank) { | |
3269 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3270 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3271 | return -EINVAL; | |
3272 | mutex_lock(&adev->grbm_idx_mutex); | |
3273 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3274 | sh_bank, instance_bank); | |
3275 | } | |
3276 | ||
3277 | if (pm_pg_lock) | |
3278 | mutex_lock(&adev->pm.mutex); | |
3279 | ||
d38ceaf9 AD |
3280 | while (size) { |
3281 | uint32_t value; | |
3282 | ||
3283 | if (*pos > adev->rmmio_size) | |
3284 | return result; | |
3285 | ||
3286 | r = get_user(value, (uint32_t *)buf); | |
3287 | if (r) | |
3288 | return r; | |
3289 | ||
3290 | WREG32(*pos >> 2, value); | |
3291 | ||
3292 | result += 4; | |
3293 | buf += 4; | |
3294 | *pos += 4; | |
3295 | size -= 4; | |
3296 | } | |
3297 | ||
394fdde2 TSD |
3298 | if (use_bank) { |
3299 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3300 | mutex_unlock(&adev->grbm_idx_mutex); | |
3301 | } | |
3302 | ||
3303 | if (pm_pg_lock) | |
3304 | mutex_unlock(&adev->pm.mutex); | |
3305 | ||
d38ceaf9 AD |
3306 | return result; |
3307 | } | |
3308 | ||
adcec288 TSD |
3309 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3310 | size_t size, loff_t *pos) | |
3311 | { | |
45063097 | 3312 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3313 | ssize_t result = 0; |
3314 | int r; | |
3315 | ||
3316 | if (size & 0x3 || *pos & 0x3) | |
3317 | return -EINVAL; | |
3318 | ||
3319 | while (size) { | |
3320 | uint32_t value; | |
3321 | ||
3322 | value = RREG32_PCIE(*pos >> 2); | |
3323 | r = put_user(value, (uint32_t *)buf); | |
3324 | if (r) | |
3325 | return r; | |
3326 | ||
3327 | result += 4; | |
3328 | buf += 4; | |
3329 | *pos += 4; | |
3330 | size -= 4; | |
3331 | } | |
3332 | ||
3333 | return result; | |
3334 | } | |
3335 | ||
3336 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3337 | size_t size, loff_t *pos) | |
3338 | { | |
45063097 | 3339 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3340 | ssize_t result = 0; |
3341 | int r; | |
3342 | ||
3343 | if (size & 0x3 || *pos & 0x3) | |
3344 | return -EINVAL; | |
3345 | ||
3346 | while (size) { | |
3347 | uint32_t value; | |
3348 | ||
3349 | r = get_user(value, (uint32_t *)buf); | |
3350 | if (r) | |
3351 | return r; | |
3352 | ||
3353 | WREG32_PCIE(*pos >> 2, value); | |
3354 | ||
3355 | result += 4; | |
3356 | buf += 4; | |
3357 | *pos += 4; | |
3358 | size -= 4; | |
3359 | } | |
3360 | ||
3361 | return result; | |
3362 | } | |
3363 | ||
3364 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3365 | size_t size, loff_t *pos) | |
3366 | { | |
45063097 | 3367 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3368 | ssize_t result = 0; |
3369 | int r; | |
3370 | ||
3371 | if (size & 0x3 || *pos & 0x3) | |
3372 | return -EINVAL; | |
3373 | ||
3374 | while (size) { | |
3375 | uint32_t value; | |
3376 | ||
3377 | value = RREG32_DIDT(*pos >> 2); | |
3378 | r = put_user(value, (uint32_t *)buf); | |
3379 | if (r) | |
3380 | return r; | |
3381 | ||
3382 | result += 4; | |
3383 | buf += 4; | |
3384 | *pos += 4; | |
3385 | size -= 4; | |
3386 | } | |
3387 | ||
3388 | return result; | |
3389 | } | |
3390 | ||
3391 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3392 | size_t size, loff_t *pos) | |
3393 | { | |
45063097 | 3394 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3395 | ssize_t result = 0; |
3396 | int r; | |
3397 | ||
3398 | if (size & 0x3 || *pos & 0x3) | |
3399 | return -EINVAL; | |
3400 | ||
3401 | while (size) { | |
3402 | uint32_t value; | |
3403 | ||
3404 | r = get_user(value, (uint32_t *)buf); | |
3405 | if (r) | |
3406 | return r; | |
3407 | ||
3408 | WREG32_DIDT(*pos >> 2, value); | |
3409 | ||
3410 | result += 4; | |
3411 | buf += 4; | |
3412 | *pos += 4; | |
3413 | size -= 4; | |
3414 | } | |
3415 | ||
3416 | return result; | |
3417 | } | |
3418 | ||
3419 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3420 | size_t size, loff_t *pos) | |
3421 | { | |
45063097 | 3422 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3423 | ssize_t result = 0; |
3424 | int r; | |
3425 | ||
3426 | if (size & 0x3 || *pos & 0x3) | |
3427 | return -EINVAL; | |
3428 | ||
3429 | while (size) { | |
3430 | uint32_t value; | |
3431 | ||
6fc0deaf | 3432 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3433 | r = put_user(value, (uint32_t *)buf); |
3434 | if (r) | |
3435 | return r; | |
3436 | ||
3437 | result += 4; | |
3438 | buf += 4; | |
3439 | *pos += 4; | |
3440 | size -= 4; | |
3441 | } | |
3442 | ||
3443 | return result; | |
3444 | } | |
3445 | ||
3446 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3447 | size_t size, loff_t *pos) | |
3448 | { | |
45063097 | 3449 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3450 | ssize_t result = 0; |
3451 | int r; | |
3452 | ||
3453 | if (size & 0x3 || *pos & 0x3) | |
3454 | return -EINVAL; | |
3455 | ||
3456 | while (size) { | |
3457 | uint32_t value; | |
3458 | ||
3459 | r = get_user(value, (uint32_t *)buf); | |
3460 | if (r) | |
3461 | return r; | |
3462 | ||
6fc0deaf | 3463 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3464 | |
3465 | result += 4; | |
3466 | buf += 4; | |
3467 | *pos += 4; | |
3468 | size -= 4; | |
3469 | } | |
3470 | ||
3471 | return result; | |
3472 | } | |
3473 | ||
1e051413 TSD |
3474 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3475 | size_t size, loff_t *pos) | |
3476 | { | |
45063097 | 3477 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3478 | ssize_t result = 0; |
3479 | int r; | |
3480 | uint32_t *config, no_regs = 0; | |
3481 | ||
3482 | if (size & 0x3 || *pos & 0x3) | |
3483 | return -EINVAL; | |
3484 | ||
ecab7668 | 3485 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3486 | if (!config) |
3487 | return -ENOMEM; | |
3488 | ||
3489 | /* version, increment each time something is added */ | |
9a999359 | 3490 | config[no_regs++] = 3; |
1e051413 TSD |
3491 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3492 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3493 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3494 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3495 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3496 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3497 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3498 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3499 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3500 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3501 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3502 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3503 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3504 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3505 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3506 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3507 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3508 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3509 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3510 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3511 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3512 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3513 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3514 | ||
89a8f309 TSD |
3515 | /* rev==1 */ |
3516 | config[no_regs++] = adev->rev_id; | |
3517 | config[no_regs++] = adev->pg_flags; | |
3518 | config[no_regs++] = adev->cg_flags; | |
3519 | ||
e9f11dc8 TSD |
3520 | /* rev==2 */ |
3521 | config[no_regs++] = adev->family; | |
3522 | config[no_regs++] = adev->external_rev_id; | |
3523 | ||
9a999359 TSD |
3524 | /* rev==3 */ |
3525 | config[no_regs++] = adev->pdev->device; | |
3526 | config[no_regs++] = adev->pdev->revision; | |
3527 | config[no_regs++] = adev->pdev->subsystem_device; | |
3528 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3529 | ||
1e051413 TSD |
3530 | while (size && (*pos < no_regs * 4)) { |
3531 | uint32_t value; | |
3532 | ||
3533 | value = config[*pos >> 2]; | |
3534 | r = put_user(value, (uint32_t *)buf); | |
3535 | if (r) { | |
3536 | kfree(config); | |
3537 | return r; | |
3538 | } | |
3539 | ||
3540 | result += 4; | |
3541 | buf += 4; | |
3542 | *pos += 4; | |
3543 | size -= 4; | |
3544 | } | |
3545 | ||
3546 | kfree(config); | |
3547 | return result; | |
3548 | } | |
3549 | ||
f2cdaf20 TSD |
3550 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3551 | size_t size, loff_t *pos) | |
3552 | { | |
45063097 | 3553 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3554 | int idx, x, outsize, r, valuesize; |
3555 | uint32_t values[16]; | |
f2cdaf20 | 3556 | |
9f8df7d7 | 3557 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3558 | return -EINVAL; |
3559 | ||
3cbc614f SP |
3560 | if (amdgpu_dpm == 0) |
3561 | return -EINVAL; | |
3562 | ||
f2cdaf20 TSD |
3563 | /* convert offset to sensor number */ |
3564 | idx = *pos >> 2; | |
3565 | ||
9f8df7d7 | 3566 | valuesize = sizeof(values); |
f2cdaf20 | 3567 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3568 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3569 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3570 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3571 | &valuesize); | |
f2cdaf20 TSD |
3572 | else |
3573 | return -EINVAL; | |
3574 | ||
9f8df7d7 TSD |
3575 | if (size > valuesize) |
3576 | return -EINVAL; | |
3577 | ||
3578 | outsize = 0; | |
3579 | x = 0; | |
3580 | if (!r) { | |
3581 | while (size) { | |
3582 | r = put_user(values[x++], (int32_t *)buf); | |
3583 | buf += 4; | |
3584 | size -= 4; | |
3585 | outsize += 4; | |
3586 | } | |
3587 | } | |
f2cdaf20 | 3588 | |
9f8df7d7 | 3589 | return !r ? outsize : r; |
f2cdaf20 | 3590 | } |
1e051413 | 3591 | |
273d7aa1 TSD |
3592 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3593 | size_t size, loff_t *pos) | |
3594 | { | |
3595 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3596 | int r, x; | |
3597 | ssize_t result=0; | |
472259f0 | 3598 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3599 | |
3600 | if (size & 3 || *pos & 3) | |
3601 | return -EINVAL; | |
3602 | ||
3603 | /* decode offset */ | |
3604 | offset = (*pos & 0x7F); | |
3605 | se = ((*pos >> 7) & 0xFF); | |
3606 | sh = ((*pos >> 15) & 0xFF); | |
3607 | cu = ((*pos >> 23) & 0xFF); | |
3608 | wave = ((*pos >> 31) & 0xFF); | |
3609 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3610 | |
3611 | /* switch to the specific se/sh/cu */ | |
3612 | mutex_lock(&adev->grbm_idx_mutex); | |
3613 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3614 | ||
3615 | x = 0; | |
472259f0 TSD |
3616 | if (adev->gfx.funcs->read_wave_data) |
3617 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3618 | |
3619 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3620 | mutex_unlock(&adev->grbm_idx_mutex); | |
3621 | ||
5ecfb3b8 TSD |
3622 | if (!x) |
3623 | return -EINVAL; | |
3624 | ||
472259f0 | 3625 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3626 | uint32_t value; |
3627 | ||
472259f0 | 3628 | value = data[offset >> 2]; |
273d7aa1 TSD |
3629 | r = put_user(value, (uint32_t *)buf); |
3630 | if (r) | |
3631 | return r; | |
3632 | ||
3633 | result += 4; | |
3634 | buf += 4; | |
472259f0 | 3635 | offset += 4; |
273d7aa1 TSD |
3636 | size -= 4; |
3637 | } | |
3638 | ||
3639 | return result; | |
3640 | } | |
3641 | ||
c5a60ce8 TSD |
3642 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3643 | size_t size, loff_t *pos) | |
3644 | { | |
3645 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3646 | int r; | |
3647 | ssize_t result = 0; | |
3648 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3649 | ||
3650 | if (size & 3 || *pos & 3) | |
3651 | return -EINVAL; | |
3652 | ||
3653 | /* decode offset */ | |
3654 | offset = (*pos & 0xFFF); /* in dwords */ | |
3655 | se = ((*pos >> 12) & 0xFF); | |
3656 | sh = ((*pos >> 20) & 0xFF); | |
3657 | cu = ((*pos >> 28) & 0xFF); | |
3658 | wave = ((*pos >> 36) & 0xFF); | |
3659 | simd = ((*pos >> 44) & 0xFF); | |
3660 | thread = ((*pos >> 52) & 0xFF); | |
3661 | bank = ((*pos >> 60) & 1); | |
3662 | ||
3663 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3664 | if (!data) | |
3665 | return -ENOMEM; | |
3666 | ||
3667 | /* switch to the specific se/sh/cu */ | |
3668 | mutex_lock(&adev->grbm_idx_mutex); | |
3669 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3670 | ||
3671 | if (bank == 0) { | |
3672 | if (adev->gfx.funcs->read_wave_vgprs) | |
3673 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3674 | } else { | |
3675 | if (adev->gfx.funcs->read_wave_sgprs) | |
3676 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3677 | } | |
3678 | ||
3679 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3680 | mutex_unlock(&adev->grbm_idx_mutex); | |
3681 | ||
3682 | while (size) { | |
3683 | uint32_t value; | |
3684 | ||
3685 | value = data[offset++]; | |
3686 | r = put_user(value, (uint32_t *)buf); | |
3687 | if (r) { | |
3688 | result = r; | |
3689 | goto err; | |
3690 | } | |
3691 | ||
3692 | result += 4; | |
3693 | buf += 4; | |
3694 | size -= 4; | |
3695 | } | |
3696 | ||
3697 | err: | |
3698 | kfree(data); | |
3699 | return result; | |
3700 | } | |
3701 | ||
d38ceaf9 AD |
3702 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3703 | .owner = THIS_MODULE, | |
3704 | .read = amdgpu_debugfs_regs_read, | |
3705 | .write = amdgpu_debugfs_regs_write, | |
3706 | .llseek = default_llseek | |
3707 | }; | |
adcec288 TSD |
3708 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3709 | .owner = THIS_MODULE, | |
3710 | .read = amdgpu_debugfs_regs_didt_read, | |
3711 | .write = amdgpu_debugfs_regs_didt_write, | |
3712 | .llseek = default_llseek | |
3713 | }; | |
3714 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3715 | .owner = THIS_MODULE, | |
3716 | .read = amdgpu_debugfs_regs_pcie_read, | |
3717 | .write = amdgpu_debugfs_regs_pcie_write, | |
3718 | .llseek = default_llseek | |
3719 | }; | |
3720 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3721 | .owner = THIS_MODULE, | |
3722 | .read = amdgpu_debugfs_regs_smc_read, | |
3723 | .write = amdgpu_debugfs_regs_smc_write, | |
3724 | .llseek = default_llseek | |
3725 | }; | |
3726 | ||
1e051413 TSD |
3727 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3728 | .owner = THIS_MODULE, | |
3729 | .read = amdgpu_debugfs_gca_config_read, | |
3730 | .llseek = default_llseek | |
3731 | }; | |
3732 | ||
f2cdaf20 TSD |
3733 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3734 | .owner = THIS_MODULE, | |
3735 | .read = amdgpu_debugfs_sensor_read, | |
3736 | .llseek = default_llseek | |
3737 | }; | |
3738 | ||
273d7aa1 TSD |
3739 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3740 | .owner = THIS_MODULE, | |
3741 | .read = amdgpu_debugfs_wave_read, | |
3742 | .llseek = default_llseek | |
3743 | }; | |
c5a60ce8 TSD |
3744 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3745 | .owner = THIS_MODULE, | |
3746 | .read = amdgpu_debugfs_gpr_read, | |
3747 | .llseek = default_llseek | |
3748 | }; | |
273d7aa1 | 3749 | |
adcec288 TSD |
3750 | static const struct file_operations *debugfs_regs[] = { |
3751 | &amdgpu_debugfs_regs_fops, | |
3752 | &amdgpu_debugfs_regs_didt_fops, | |
3753 | &amdgpu_debugfs_regs_pcie_fops, | |
3754 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3755 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3756 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3757 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3758 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3759 | }; |
3760 | ||
3761 | static const char *debugfs_regs_names[] = { | |
3762 | "amdgpu_regs", | |
3763 | "amdgpu_regs_didt", | |
3764 | "amdgpu_regs_pcie", | |
3765 | "amdgpu_regs_smc", | |
1e051413 | 3766 | "amdgpu_gca_config", |
f2cdaf20 | 3767 | "amdgpu_sensors", |
273d7aa1 | 3768 | "amdgpu_wave", |
c5a60ce8 | 3769 | "amdgpu_gpr", |
adcec288 | 3770 | }; |
d38ceaf9 AD |
3771 | |
3772 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3773 | { | |
3774 | struct drm_minor *minor = adev->ddev->primary; | |
3775 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3776 | unsigned i, j; |
3777 | ||
3778 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3779 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3780 | S_IFREG | S_IRUGO, root, | |
3781 | adev, debugfs_regs[i]); | |
3782 | if (IS_ERR(ent)) { | |
3783 | for (j = 0; j < i; j++) { | |
3784 | debugfs_remove(adev->debugfs_regs[i]); | |
3785 | adev->debugfs_regs[i] = NULL; | |
3786 | } | |
3787 | return PTR_ERR(ent); | |
3788 | } | |
d38ceaf9 | 3789 | |
adcec288 TSD |
3790 | if (!i) |
3791 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3792 | adev->debugfs_regs[i] = ent; | |
3793 | } | |
d38ceaf9 AD |
3794 | |
3795 | return 0; | |
3796 | } | |
3797 | ||
3798 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3799 | { | |
adcec288 TSD |
3800 | unsigned i; |
3801 | ||
3802 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3803 | if (adev->debugfs_regs[i]) { | |
3804 | debugfs_remove(adev->debugfs_regs[i]); | |
3805 | adev->debugfs_regs[i] = NULL; | |
3806 | } | |
3807 | } | |
d38ceaf9 AD |
3808 | } |
3809 | ||
4f0955fc HR |
3810 | static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) |
3811 | { | |
3812 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3813 | struct drm_device *dev = node->minor->dev; | |
3814 | struct amdgpu_device *adev = dev->dev_private; | |
3815 | int r = 0, i; | |
3816 | ||
3817 | /* hold on the scheduler */ | |
3818 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3819 | struct amdgpu_ring *ring = adev->rings[i]; | |
3820 | ||
3821 | if (!ring || !ring->sched.thread) | |
3822 | continue; | |
3823 | kthread_park(ring->sched.thread); | |
3824 | } | |
3825 | ||
3826 | seq_printf(m, "run ib test:\n"); | |
3827 | r = amdgpu_ib_ring_tests(adev); | |
3828 | if (r) | |
3829 | seq_printf(m, "ib ring tests failed (%d).\n", r); | |
3830 | else | |
3831 | seq_printf(m, "ib ring tests passed.\n"); | |
3832 | ||
3833 | /* go on the scheduler */ | |
3834 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3835 | struct amdgpu_ring *ring = adev->rings[i]; | |
3836 | ||
3837 | if (!ring || !ring->sched.thread) | |
3838 | continue; | |
3839 | kthread_unpark(ring->sched.thread); | |
3840 | } | |
3841 | ||
3842 | return 0; | |
3843 | } | |
3844 | ||
3845 | static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { | |
3846 | {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} | |
3847 | }; | |
3848 | ||
3849 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) | |
3850 | { | |
3851 | return amdgpu_debugfs_add_files(adev, | |
3852 | amdgpu_debugfs_test_ib_ring_list, 1); | |
3853 | } | |
3854 | ||
d38ceaf9 AD |
3855 | int amdgpu_debugfs_init(struct drm_minor *minor) |
3856 | { | |
3857 | return 0; | |
3858 | } | |
7cebc728 | 3859 | #else |
27bad5b9 | 3860 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) |
4f0955fc HR |
3861 | { |
3862 | return 0; | |
3863 | } | |
7cebc728 AK |
3864 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) |
3865 | { | |
3866 | return 0; | |
3867 | } | |
3868 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3869 | #endif |