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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
e2a75f88 | 58 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 59 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 60 | |
2dc80b00 S |
61 | #define AMDGPU_RESUME_MS 2000 |
62 | ||
d38ceaf9 AD |
63 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
64 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
4f0955fc | 65 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); |
d38ceaf9 AD |
66 | |
67 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
68 | "TAHITI", |
69 | "PITCAIRN", | |
70 | "VERDE", | |
71 | "OLAND", | |
72 | "HAINAN", | |
d38ceaf9 AD |
73 | "BONAIRE", |
74 | "KAVERI", | |
75 | "KABINI", | |
76 | "HAWAII", | |
77 | "MULLINS", | |
78 | "TOPAZ", | |
79 | "TONGA", | |
48299f95 | 80 | "FIJI", |
d38ceaf9 | 81 | "CARRIZO", |
139f4917 | 82 | "STONEY", |
2cc0c0b5 FC |
83 | "POLARIS10", |
84 | "POLARIS11", | |
c4642a47 | 85 | "POLARIS12", |
d4196f01 | 86 | "VEGA10", |
2ca8a5d2 | 87 | "RAVEN", |
d38ceaf9 AD |
88 | "LAST", |
89 | }; | |
90 | ||
91 | bool amdgpu_device_is_px(struct drm_device *dev) | |
92 | { | |
93 | struct amdgpu_device *adev = dev->dev_private; | |
94 | ||
2f7d10b3 | 95 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
96 | return true; |
97 | return false; | |
98 | } | |
99 | ||
100 | /* | |
101 | * MMIO register access helper functions. | |
102 | */ | |
103 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 104 | uint32_t acc_flags) |
d38ceaf9 | 105 | { |
f4b373f4 TSD |
106 | uint32_t ret; |
107 | ||
15d72fd7 | 108 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
109 | BUG_ON(in_interrupt()); |
110 | return amdgpu_virt_kiq_rreg(adev, reg); | |
111 | } | |
112 | ||
15d72fd7 | 113 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 114 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
115 | else { |
116 | unsigned long flags; | |
d38ceaf9 AD |
117 | |
118 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
119 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
120 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
121 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 122 | } |
f4b373f4 TSD |
123 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
124 | return ret; | |
d38ceaf9 AD |
125 | } |
126 | ||
127 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 128 | uint32_t acc_flags) |
d38ceaf9 | 129 | { |
f4b373f4 | 130 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 131 | |
47ed4e1c KW |
132 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
133 | adev->last_mm_index = v; | |
134 | } | |
135 | ||
15d72fd7 | 136 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
137 | BUG_ON(in_interrupt()); |
138 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
139 | } | |
140 | ||
15d72fd7 | 141 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
142 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
143 | else { | |
144 | unsigned long flags; | |
145 | ||
146 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
147 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
148 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
149 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
150 | } | |
47ed4e1c KW |
151 | |
152 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
153 | udelay(500); | |
154 | } | |
d38ceaf9 AD |
155 | } |
156 | ||
157 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
158 | { | |
159 | if ((reg * 4) < adev->rio_mem_size) | |
160 | return ioread32(adev->rio_mem + (reg * 4)); | |
161 | else { | |
162 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
163 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
164 | } | |
165 | } | |
166 | ||
167 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
168 | { | |
47ed4e1c KW |
169 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
170 | adev->last_mm_index = v; | |
171 | } | |
d38ceaf9 AD |
172 | |
173 | if ((reg * 4) < adev->rio_mem_size) | |
174 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
175 | else { | |
176 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
177 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
178 | } | |
47ed4e1c KW |
179 | |
180 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
181 | udelay(500); | |
182 | } | |
d38ceaf9 AD |
183 | } |
184 | ||
185 | /** | |
186 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
187 | * | |
188 | * @adev: amdgpu_device pointer | |
189 | * @index: doorbell index | |
190 | * | |
191 | * Returns the value in the doorbell aperture at the | |
192 | * requested doorbell index (CIK). | |
193 | */ | |
194 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
195 | { | |
196 | if (index < adev->doorbell.num_doorbells) { | |
197 | return readl(adev->doorbell.ptr + index); | |
198 | } else { | |
199 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
200 | return 0; | |
201 | } | |
202 | } | |
203 | ||
204 | /** | |
205 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
206 | * | |
207 | * @adev: amdgpu_device pointer | |
208 | * @index: doorbell index | |
209 | * @v: value to write | |
210 | * | |
211 | * Writes @v to the doorbell aperture at the | |
212 | * requested doorbell index (CIK). | |
213 | */ | |
214 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
215 | { | |
216 | if (index < adev->doorbell.num_doorbells) { | |
217 | writel(v, adev->doorbell.ptr + index); | |
218 | } else { | |
219 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
220 | } | |
221 | } | |
222 | ||
832be404 KW |
223 | /** |
224 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
225 | * | |
226 | * @adev: amdgpu_device pointer | |
227 | * @index: doorbell index | |
228 | * | |
229 | * Returns the value in the doorbell aperture at the | |
230 | * requested doorbell index (VEGA10+). | |
231 | */ | |
232 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
233 | { | |
234 | if (index < adev->doorbell.num_doorbells) { | |
235 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
236 | } else { | |
237 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
238 | return 0; | |
239 | } | |
240 | } | |
241 | ||
242 | /** | |
243 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
244 | * | |
245 | * @adev: amdgpu_device pointer | |
246 | * @index: doorbell index | |
247 | * @v: value to write | |
248 | * | |
249 | * Writes @v to the doorbell aperture at the | |
250 | * requested doorbell index (VEGA10+). | |
251 | */ | |
252 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
253 | { | |
254 | if (index < adev->doorbell.num_doorbells) { | |
255 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
256 | } else { | |
257 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
258 | } | |
259 | } | |
260 | ||
d38ceaf9 AD |
261 | /** |
262 | * amdgpu_invalid_rreg - dummy reg read function | |
263 | * | |
264 | * @adev: amdgpu device pointer | |
265 | * @reg: offset of register | |
266 | * | |
267 | * Dummy register read function. Used for register blocks | |
268 | * that certain asics don't have (all asics). | |
269 | * Returns the value in the register. | |
270 | */ | |
271 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
272 | { | |
273 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
274 | BUG(); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /** | |
279 | * amdgpu_invalid_wreg - dummy reg write function | |
280 | * | |
281 | * @adev: amdgpu device pointer | |
282 | * @reg: offset of register | |
283 | * @v: value to write to the register | |
284 | * | |
285 | * Dummy register read function. Used for register blocks | |
286 | * that certain asics don't have (all asics). | |
287 | */ | |
288 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
289 | { | |
290 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
291 | reg, v); | |
292 | BUG(); | |
293 | } | |
294 | ||
295 | /** | |
296 | * amdgpu_block_invalid_rreg - dummy reg read function | |
297 | * | |
298 | * @adev: amdgpu device pointer | |
299 | * @block: offset of instance | |
300 | * @reg: offset of register | |
301 | * | |
302 | * Dummy register read function. Used for register blocks | |
303 | * that certain asics don't have (all asics). | |
304 | * Returns the value in the register. | |
305 | */ | |
306 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
307 | uint32_t block, uint32_t reg) | |
308 | { | |
309 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
310 | reg, block); | |
311 | BUG(); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | /** | |
316 | * amdgpu_block_invalid_wreg - dummy reg write function | |
317 | * | |
318 | * @adev: amdgpu device pointer | |
319 | * @block: offset of instance | |
320 | * @reg: offset of register | |
321 | * @v: value to write to the register | |
322 | * | |
323 | * Dummy register read function. Used for register blocks | |
324 | * that certain asics don't have (all asics). | |
325 | */ | |
326 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
327 | uint32_t block, | |
328 | uint32_t reg, uint32_t v) | |
329 | { | |
330 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
331 | reg, block, v); | |
332 | BUG(); | |
333 | } | |
334 | ||
335 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
336 | { | |
337 | int r; | |
338 | ||
339 | if (adev->vram_scratch.robj == NULL) { | |
340 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 341 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
342 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
343 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 344 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
345 | if (r) { |
346 | return r; | |
347 | } | |
348 | } | |
349 | ||
350 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
351 | if (unlikely(r != 0)) | |
352 | return r; | |
353 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
354 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
355 | if (r) { | |
356 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
357 | return r; | |
358 | } | |
359 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
360 | (void **)&adev->vram_scratch.ptr); | |
361 | if (r) | |
362 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
363 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
364 | ||
365 | return r; | |
366 | } | |
367 | ||
368 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
369 | { | |
370 | int r; | |
371 | ||
372 | if (adev->vram_scratch.robj == NULL) { | |
373 | return; | |
374 | } | |
8ab25b4f | 375 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, true); |
d38ceaf9 AD |
376 | if (likely(r == 0)) { |
377 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
378 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
379 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
380 | } | |
381 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
382 | } | |
383 | ||
384 | /** | |
385 | * amdgpu_program_register_sequence - program an array of registers. | |
386 | * | |
387 | * @adev: amdgpu_device pointer | |
388 | * @registers: pointer to the register array | |
389 | * @array_size: size of the register array | |
390 | * | |
391 | * Programs an array or registers with and and or masks. | |
392 | * This is a helper for setting golden registers. | |
393 | */ | |
394 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
395 | const u32 *registers, | |
396 | const u32 array_size) | |
397 | { | |
398 | u32 tmp, reg, and_mask, or_mask; | |
399 | int i; | |
400 | ||
401 | if (array_size % 3) | |
402 | return; | |
403 | ||
404 | for (i = 0; i < array_size; i +=3) { | |
405 | reg = registers[i + 0]; | |
406 | and_mask = registers[i + 1]; | |
407 | or_mask = registers[i + 2]; | |
408 | ||
409 | if (and_mask == 0xffffffff) { | |
410 | tmp = or_mask; | |
411 | } else { | |
412 | tmp = RREG32(reg); | |
413 | tmp &= ~and_mask; | |
414 | tmp |= or_mask; | |
415 | } | |
416 | WREG32(reg, tmp); | |
417 | } | |
418 | } | |
419 | ||
420 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
421 | { | |
422 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
423 | } | |
424 | ||
425 | /* | |
426 | * GPU doorbell aperture helpers function. | |
427 | */ | |
428 | /** | |
429 | * amdgpu_doorbell_init - Init doorbell driver information. | |
430 | * | |
431 | * @adev: amdgpu_device pointer | |
432 | * | |
433 | * Init doorbell driver information (CIK) | |
434 | * Returns 0 on success, error on failure. | |
435 | */ | |
436 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
437 | { | |
438 | /* doorbell bar mapping */ | |
439 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
440 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
441 | ||
edf600da | 442 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
443 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
444 | if (adev->doorbell.num_doorbells == 0) | |
445 | return -EINVAL; | |
446 | ||
8972e5d2 CK |
447 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
448 | adev->doorbell.num_doorbells * | |
449 | sizeof(u32)); | |
450 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 451 | return -ENOMEM; |
d38ceaf9 AD |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
456 | /** | |
457 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
458 | * | |
459 | * @adev: amdgpu_device pointer | |
460 | * | |
461 | * Tear down doorbell driver information (CIK) | |
462 | */ | |
463 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
464 | { | |
465 | iounmap(adev->doorbell.ptr); | |
466 | adev->doorbell.ptr = NULL; | |
467 | } | |
468 | ||
469 | /** | |
470 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
471 | * setup amdkfd | |
472 | * | |
473 | * @adev: amdgpu_device pointer | |
474 | * @aperture_base: output returning doorbell aperture base physical address | |
475 | * @aperture_size: output returning doorbell aperture size in bytes | |
476 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
477 | * | |
478 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
479 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
480 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
481 | */ | |
482 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
483 | phys_addr_t *aperture_base, | |
484 | size_t *aperture_size, | |
485 | size_t *start_offset) | |
486 | { | |
487 | /* | |
488 | * The first num_doorbells are used by amdgpu. | |
489 | * amdkfd takes whatever's left in the aperture. | |
490 | */ | |
491 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
492 | *aperture_base = adev->doorbell.base; | |
493 | *aperture_size = adev->doorbell.size; | |
494 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
495 | } else { | |
496 | *aperture_base = 0; | |
497 | *aperture_size = 0; | |
498 | *start_offset = 0; | |
499 | } | |
500 | } | |
501 | ||
502 | /* | |
503 | * amdgpu_wb_*() | |
455a7bc2 | 504 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 505 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
506 | */ |
507 | ||
508 | /** | |
509 | * amdgpu_wb_fini - Disable Writeback and free memory | |
510 | * | |
511 | * @adev: amdgpu_device pointer | |
512 | * | |
513 | * Disables Writeback and frees the Writeback memory (all asics). | |
514 | * Used at driver shutdown. | |
515 | */ | |
516 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
517 | { | |
518 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
519 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
520 | &adev->wb.gpu_addr, | |
521 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
522 | adev->wb.wb_obj = NULL; |
523 | } | |
524 | } | |
525 | ||
526 | /** | |
527 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
528 | * | |
529 | * @adev: amdgpu_device pointer | |
530 | * | |
455a7bc2 | 531 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
532 | * Used at driver startup. |
533 | * Returns 0 on success or an -error on failure. | |
534 | */ | |
535 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
536 | { | |
537 | int r; | |
538 | ||
539 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 540 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
541 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
542 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
543 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
544 | if (r) { |
545 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
546 | return r; | |
547 | } | |
d38ceaf9 AD |
548 | |
549 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
550 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
551 | ||
552 | /* clear wb memory */ | |
60a970a6 | 553 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
554 | } |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
559 | /** | |
560 | * amdgpu_wb_get - Allocate a wb entry | |
561 | * | |
562 | * @adev: amdgpu_device pointer | |
563 | * @wb: wb index | |
564 | * | |
565 | * Allocate a wb slot for use by the driver (all asics). | |
566 | * Returns 0 on success or -EINVAL on failure. | |
567 | */ | |
568 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
569 | { | |
570 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
571 | if (offset < adev->wb.num_wb) { | |
572 | __set_bit(offset, adev->wb.used); | |
573 | *wb = offset; | |
574 | return 0; | |
575 | } else { | |
576 | return -EINVAL; | |
577 | } | |
578 | } | |
579 | ||
7014285a KW |
580 | /** |
581 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
582 | * | |
583 | * @adev: amdgpu_device pointer | |
584 | * @wb: wb index | |
585 | * | |
586 | * Allocate a wb slot for use by the driver (all asics). | |
587 | * Returns 0 on success or -EINVAL on failure. | |
588 | */ | |
589 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
590 | { | |
591 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
592 | adev->wb.num_wb, 0, 2, 7, 0); | |
593 | if ((offset + 1) < adev->wb.num_wb) { | |
594 | __set_bit(offset, adev->wb.used); | |
595 | __set_bit(offset + 1, adev->wb.used); | |
596 | *wb = offset; | |
597 | return 0; | |
598 | } else { | |
599 | return -EINVAL; | |
600 | } | |
601 | } | |
602 | ||
d38ceaf9 AD |
603 | /** |
604 | * amdgpu_wb_free - Free a wb entry | |
605 | * | |
606 | * @adev: amdgpu_device pointer | |
607 | * @wb: wb index | |
608 | * | |
609 | * Free a wb slot allocated for use by the driver (all asics) | |
610 | */ | |
611 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
612 | { | |
613 | if (wb < adev->wb.num_wb) | |
614 | __clear_bit(wb, adev->wb.used); | |
615 | } | |
616 | ||
7014285a KW |
617 | /** |
618 | * amdgpu_wb_free_64bit - Free a wb entry | |
619 | * | |
620 | * @adev: amdgpu_device pointer | |
621 | * @wb: wb index | |
622 | * | |
623 | * Free a wb slot allocated for use by the driver (all asics) | |
624 | */ | |
625 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
626 | { | |
627 | if ((wb + 1) < adev->wb.num_wb) { | |
628 | __clear_bit(wb, adev->wb.used); | |
629 | __clear_bit(wb + 1, adev->wb.used); | |
630 | } | |
631 | } | |
632 | ||
d38ceaf9 AD |
633 | /** |
634 | * amdgpu_vram_location - try to find VRAM location | |
635 | * @adev: amdgpu device structure holding all necessary informations | |
636 | * @mc: memory controller structure holding memory informations | |
637 | * @base: base address at which to put VRAM | |
638 | * | |
455a7bc2 | 639 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
640 | * as parameter (which is so far either PCI aperture address or |
641 | * for IGP TOM base address). | |
642 | * | |
643 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
644 | * address space then we limit the VRAM size to the aperture. | |
645 | * | |
646 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
647 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
648 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
649 | * not IGP. | |
650 | * | |
651 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
652 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
653 | * Novell bug 204882 + along with lots of ubuntu ones | |
654 | * | |
655 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
656 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
657 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
658 | * ones) | |
659 | * | |
660 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 661 | * explicitly check for that though. |
d38ceaf9 AD |
662 | * |
663 | * FIXME: when reducing VRAM size align new size on power of 2. | |
664 | */ | |
665 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
666 | { | |
667 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
668 | ||
669 | mc->vram_start = base; | |
670 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
671 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
672 | mc->real_vram_size = mc->aper_size; | |
673 | mc->mc_vram_size = mc->aper_size; | |
674 | } | |
675 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
676 | if (limit && limit < mc->real_vram_size) | |
677 | mc->real_vram_size = limit; | |
678 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
679 | mc->mc_vram_size >> 20, mc->vram_start, | |
680 | mc->vram_end, mc->real_vram_size >> 20); | |
681 | } | |
682 | ||
683 | /** | |
6f02a696 | 684 | * amdgpu_gart_location - try to find GTT location |
d38ceaf9 AD |
685 | * @adev: amdgpu device structure holding all necessary informations |
686 | * @mc: memory controller structure holding memory informations | |
687 | * | |
688 | * Function will place try to place GTT before or after VRAM. | |
689 | * | |
690 | * If GTT size is bigger than space left then we ajust GTT size. | |
691 | * Thus function will never fails. | |
692 | * | |
693 | * FIXME: when reducing GTT size align new size on power of 2. | |
694 | */ | |
6f02a696 | 695 | void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) |
d38ceaf9 AD |
696 | { |
697 | u64 size_af, size_bf; | |
698 | ||
ed21c047 CK |
699 | size_af = adev->mc.mc_mask - mc->vram_end; |
700 | size_bf = mc->vram_start; | |
d38ceaf9 | 701 | if (size_bf > size_af) { |
6f02a696 | 702 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 703 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 704 | mc->gart_size = size_bf; |
d38ceaf9 | 705 | } |
6f02a696 | 706 | mc->gart_start = 0; |
d38ceaf9 | 707 | } else { |
6f02a696 | 708 | if (mc->gart_size > size_af) { |
d38ceaf9 | 709 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 710 | mc->gart_size = size_af; |
d38ceaf9 | 711 | } |
6f02a696 | 712 | mc->gart_start = mc->vram_end + 1; |
d38ceaf9 | 713 | } |
6f02a696 | 714 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 715 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 716 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
717 | } |
718 | ||
719 | /* | |
720 | * GPU helpers function. | |
721 | */ | |
722 | /** | |
c836fec5 | 723 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
724 | * |
725 | * @adev: amdgpu_device pointer | |
726 | * | |
c836fec5 JQ |
727 | * Check if the asic has been initialized (all asics) at driver startup |
728 | * or post is needed if hw reset is performed. | |
729 | * Returns true if need or false if not. | |
d38ceaf9 | 730 | */ |
c836fec5 | 731 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
732 | { |
733 | uint32_t reg; | |
734 | ||
c836fec5 JQ |
735 | if (adev->has_hw_reset) { |
736 | adev->has_hw_reset = false; | |
737 | return true; | |
738 | } | |
70d17a25 AD |
739 | |
740 | /* bios scratch used on CIK+ */ | |
741 | if (adev->asic_type >= CHIP_BONAIRE) | |
742 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
743 | ||
744 | /* check MEM_SIZE for older asics */ | |
bbf282d8 | 745 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 | 746 | |
f2713e8c | 747 | if ((reg != 0) && (reg != 0xffffffff)) |
c836fec5 | 748 | return false; |
d38ceaf9 | 749 | |
c836fec5 | 750 | return true; |
d38ceaf9 AD |
751 | |
752 | } | |
753 | ||
bec86378 ML |
754 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
755 | { | |
756 | if (amdgpu_sriov_vf(adev)) | |
757 | return false; | |
758 | ||
759 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
760 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
761 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
762 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
763 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
764 | */ |
765 | if (adev->asic_type == CHIP_FIJI) { | |
766 | int err; | |
767 | uint32_t fw_ver; | |
768 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
769 | /* force vPost if error occured */ | |
770 | if (err) | |
771 | return true; | |
772 | ||
773 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
774 | if (fw_ver < 0x00160e00) |
775 | return true; | |
bec86378 | 776 | } |
bec86378 | 777 | } |
c836fec5 | 778 | return amdgpu_need_post(adev); |
bec86378 ML |
779 | } |
780 | ||
d38ceaf9 AD |
781 | /** |
782 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
783 | * | |
784 | * @adev: amdgpu_device pointer | |
785 | * | |
786 | * Allocate the dummy page used by the driver (all asics). | |
787 | * This dummy page is used by the driver as a filler for gart entries | |
788 | * when pages are taken out of the GART | |
789 | * Returns 0 on sucess, -ENOMEM on failure. | |
790 | */ | |
791 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
792 | { | |
793 | if (adev->dummy_page.page) | |
794 | return 0; | |
795 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
796 | if (adev->dummy_page.page == NULL) | |
797 | return -ENOMEM; | |
798 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
799 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
800 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
801 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
802 | __free_page(adev->dummy_page.page); | |
803 | adev->dummy_page.page = NULL; | |
804 | return -ENOMEM; | |
805 | } | |
806 | return 0; | |
807 | } | |
808 | ||
809 | /** | |
810 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
811 | * | |
812 | * @adev: amdgpu_device pointer | |
813 | * | |
814 | * Frees the dummy page used by the driver (all asics). | |
815 | */ | |
816 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
817 | { | |
818 | if (adev->dummy_page.page == NULL) | |
819 | return; | |
820 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
821 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
822 | __free_page(adev->dummy_page.page); | |
823 | adev->dummy_page.page = NULL; | |
824 | } | |
825 | ||
826 | ||
827 | /* ATOM accessor methods */ | |
828 | /* | |
829 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
830 | * driver registers callbacks to access registers and the interpreter | |
831 | * in the driver parses the tables and executes then to program specific | |
832 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
833 | * atombios.h, and atom.c | |
834 | */ | |
835 | ||
836 | /** | |
837 | * cail_pll_read - read PLL register | |
838 | * | |
839 | * @info: atom card_info pointer | |
840 | * @reg: PLL register offset | |
841 | * | |
842 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
843 | * Returns the value of the PLL register. | |
844 | */ | |
845 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
846 | { | |
847 | return 0; | |
848 | } | |
849 | ||
850 | /** | |
851 | * cail_pll_write - write PLL register | |
852 | * | |
853 | * @info: atom card_info pointer | |
854 | * @reg: PLL register offset | |
855 | * @val: value to write to the pll register | |
856 | * | |
857 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
858 | */ | |
859 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
860 | { | |
861 | ||
862 | } | |
863 | ||
864 | /** | |
865 | * cail_mc_read - read MC (Memory Controller) register | |
866 | * | |
867 | * @info: atom card_info pointer | |
868 | * @reg: MC register offset | |
869 | * | |
870 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
871 | * Returns the value of the MC register. | |
872 | */ | |
873 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
874 | { | |
875 | return 0; | |
876 | } | |
877 | ||
878 | /** | |
879 | * cail_mc_write - write MC (Memory Controller) register | |
880 | * | |
881 | * @info: atom card_info pointer | |
882 | * @reg: MC register offset | |
883 | * @val: value to write to the pll register | |
884 | * | |
885 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
886 | */ | |
887 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
888 | { | |
889 | ||
890 | } | |
891 | ||
892 | /** | |
893 | * cail_reg_write - write MMIO register | |
894 | * | |
895 | * @info: atom card_info pointer | |
896 | * @reg: MMIO register offset | |
897 | * @val: value to write to the pll register | |
898 | * | |
899 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
900 | */ | |
901 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
902 | { | |
903 | struct amdgpu_device *adev = info->dev->dev_private; | |
904 | ||
905 | WREG32(reg, val); | |
906 | } | |
907 | ||
908 | /** | |
909 | * cail_reg_read - read MMIO register | |
910 | * | |
911 | * @info: atom card_info pointer | |
912 | * @reg: MMIO register offset | |
913 | * | |
914 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
915 | * Returns the value of the MMIO register. | |
916 | */ | |
917 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
918 | { | |
919 | struct amdgpu_device *adev = info->dev->dev_private; | |
920 | uint32_t r; | |
921 | ||
922 | r = RREG32(reg); | |
923 | return r; | |
924 | } | |
925 | ||
926 | /** | |
927 | * cail_ioreg_write - write IO register | |
928 | * | |
929 | * @info: atom card_info pointer | |
930 | * @reg: IO register offset | |
931 | * @val: value to write to the pll register | |
932 | * | |
933 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
934 | */ | |
935 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
936 | { | |
937 | struct amdgpu_device *adev = info->dev->dev_private; | |
938 | ||
939 | WREG32_IO(reg, val); | |
940 | } | |
941 | ||
942 | /** | |
943 | * cail_ioreg_read - read IO register | |
944 | * | |
945 | * @info: atom card_info pointer | |
946 | * @reg: IO register offset | |
947 | * | |
948 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
949 | * Returns the value of the IO register. | |
950 | */ | |
951 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
952 | { | |
953 | struct amdgpu_device *adev = info->dev->dev_private; | |
954 | uint32_t r; | |
955 | ||
956 | r = RREG32_IO(reg); | |
957 | return r; | |
958 | } | |
959 | ||
960 | /** | |
961 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
962 | * | |
963 | * @adev: amdgpu_device pointer | |
964 | * | |
965 | * Frees the driver info and register access callbacks for the ATOM | |
966 | * interpreter (r4xx+). | |
967 | * Called at driver shutdown. | |
968 | */ | |
969 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
970 | { | |
89e0ec9f | 971 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 972 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
973 | kfree(adev->mode_info.atom_context->iio); |
974 | } | |
d38ceaf9 AD |
975 | kfree(adev->mode_info.atom_context); |
976 | adev->mode_info.atom_context = NULL; | |
977 | kfree(adev->mode_info.atom_card_info); | |
978 | adev->mode_info.atom_card_info = NULL; | |
979 | } | |
980 | ||
981 | /** | |
982 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
983 | * | |
984 | * @adev: amdgpu_device pointer | |
985 | * | |
986 | * Initializes the driver info and register access callbacks for the | |
987 | * ATOM interpreter (r4xx+). | |
988 | * Returns 0 on sucess, -ENOMEM on failure. | |
989 | * Called at driver startup. | |
990 | */ | |
991 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
992 | { | |
993 | struct card_info *atom_card_info = | |
994 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
995 | ||
996 | if (!atom_card_info) | |
997 | return -ENOMEM; | |
998 | ||
999 | adev->mode_info.atom_card_info = atom_card_info; | |
1000 | atom_card_info->dev = adev->ddev; | |
1001 | atom_card_info->reg_read = cail_reg_read; | |
1002 | atom_card_info->reg_write = cail_reg_write; | |
1003 | /* needed for iio ops */ | |
1004 | if (adev->rio_mem) { | |
1005 | atom_card_info->ioreg_read = cail_ioreg_read; | |
1006 | atom_card_info->ioreg_write = cail_ioreg_write; | |
1007 | } else { | |
b64a18c5 | 1008 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
1009 | atom_card_info->ioreg_read = cail_reg_read; |
1010 | atom_card_info->ioreg_write = cail_reg_write; | |
1011 | } | |
1012 | atom_card_info->mc_read = cail_mc_read; | |
1013 | atom_card_info->mc_write = cail_mc_write; | |
1014 | atom_card_info->pll_read = cail_pll_read; | |
1015 | atom_card_info->pll_write = cail_pll_write; | |
1016 | ||
1017 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
1018 | if (!adev->mode_info.atom_context) { | |
1019 | amdgpu_atombios_fini(adev); | |
1020 | return -ENOMEM; | |
1021 | } | |
1022 | ||
1023 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1024 | if (adev->is_atom_fw) { |
1025 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1026 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1027 | } else { | |
1028 | amdgpu_atombios_scratch_regs_init(adev); | |
1029 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1030 | } | |
d38ceaf9 AD |
1031 | return 0; |
1032 | } | |
1033 | ||
1034 | /* if we get transitioned to only one device, take VGA back */ | |
1035 | /** | |
1036 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1037 | * | |
1038 | * @cookie: amdgpu_device pointer | |
1039 | * @state: enable/disable vga decode | |
1040 | * | |
1041 | * Enable/disable vga decode (all asics). | |
1042 | * Returns VGA resource flags. | |
1043 | */ | |
1044 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1045 | { | |
1046 | struct amdgpu_device *adev = cookie; | |
1047 | amdgpu_asic_set_vga_state(adev, state); | |
1048 | if (state) | |
1049 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1050 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1051 | else | |
1052 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1053 | } | |
1054 | ||
bab4fee7 | 1055 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1056 | { |
1057 | /* defines number of bits in page table versus page directory, | |
1058 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1059 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1060 | if (amdgpu_vm_block_size == -1) |
1061 | return; | |
a1adf8be | 1062 | |
bab4fee7 | 1063 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1064 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1065 | amdgpu_vm_block_size); | |
bab4fee7 | 1066 | goto def_value; |
a1adf8be CZ |
1067 | } |
1068 | ||
1069 | if (amdgpu_vm_block_size > 24 || | |
1070 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1071 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1072 | amdgpu_vm_block_size); | |
bab4fee7 | 1073 | goto def_value; |
a1adf8be | 1074 | } |
bab4fee7 JZ |
1075 | |
1076 | return; | |
1077 | ||
1078 | def_value: | |
1079 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1080 | } |
1081 | ||
83ca145d ZJ |
1082 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1083 | { | |
64dab074 AD |
1084 | /* no need to check the default value */ |
1085 | if (amdgpu_vm_size == -1) | |
1086 | return; | |
1087 | ||
76117507 | 1088 | if (!is_power_of_2(amdgpu_vm_size)) { |
83ca145d ZJ |
1089 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", |
1090 | amdgpu_vm_size); | |
1091 | goto def_value; | |
1092 | } | |
1093 | ||
1094 | if (amdgpu_vm_size < 1) { | |
1095 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1096 | amdgpu_vm_size); | |
1097 | goto def_value; | |
1098 | } | |
1099 | ||
1100 | /* | |
1101 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1102 | */ | |
1103 | if (amdgpu_vm_size > 1024) { | |
1104 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1105 | amdgpu_vm_size); | |
1106 | goto def_value; | |
1107 | } | |
1108 | ||
1109 | return; | |
1110 | ||
1111 | def_value: | |
bab4fee7 | 1112 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1113 | } |
1114 | ||
d38ceaf9 AD |
1115 | /** |
1116 | * amdgpu_check_arguments - validate module params | |
1117 | * | |
1118 | * @adev: amdgpu_device pointer | |
1119 | * | |
1120 | * Validates certain module parameters and updates | |
1121 | * the associated values used by the driver (all asics). | |
1122 | */ | |
1123 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1124 | { | |
5b011235 CZ |
1125 | if (amdgpu_sched_jobs < 4) { |
1126 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1127 | amdgpu_sched_jobs); | |
1128 | amdgpu_sched_jobs = 4; | |
76117507 | 1129 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1130 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1131 | amdgpu_sched_jobs); | |
1132 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1133 | } | |
d38ceaf9 | 1134 | |
f9321cc4 CK |
1135 | if (amdgpu_gart_size < 32) { |
1136 | /* gart size must be greater or equal to 32M */ | |
1137 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1138 | amdgpu_gart_size); | |
1139 | amdgpu_gart_size = 32; | |
d38ceaf9 AD |
1140 | } |
1141 | ||
36d38372 CK |
1142 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
1143 | /* gtt size must be greater or equal to 32M */ | |
1144 | dev_warn(adev->dev, "gtt size (%d) too small\n", | |
1145 | amdgpu_gtt_size); | |
1146 | amdgpu_gtt_size = -1; | |
1147 | } | |
1148 | ||
83ca145d | 1149 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1150 | |
bab4fee7 | 1151 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1152 | |
526bae37 | 1153 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1154 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1155 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1156 | amdgpu_vram_page_split); | |
1157 | amdgpu_vram_page_split = 1024; | |
1158 | } | |
d38ceaf9 AD |
1159 | } |
1160 | ||
1161 | /** | |
1162 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1163 | * | |
1164 | * @pdev: pci dev pointer | |
1694467b | 1165 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1166 | * |
1167 | * Callback for the switcheroo driver. Suspends or resumes the | |
1168 | * the asics before or after it is powered up using ACPI methods. | |
1169 | */ | |
1170 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1171 | { | |
1172 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1173 | ||
1174 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1175 | return; | |
1176 | ||
1177 | if (state == VGA_SWITCHEROO_ON) { | |
1178 | unsigned d3_delay = dev->pdev->d3_delay; | |
1179 | ||
7ca85295 | 1180 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1181 | /* don't suspend or resume card normally */ |
1182 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1183 | ||
810ddc3a | 1184 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1185 | |
1186 | dev->pdev->d3_delay = d3_delay; | |
1187 | ||
1188 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1189 | drm_kms_helper_poll_enable(dev); | |
1190 | } else { | |
7ca85295 | 1191 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1192 | drm_kms_helper_poll_disable(dev); |
1193 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1194 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1195 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1196 | } | |
1197 | } | |
1198 | ||
1199 | /** | |
1200 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1201 | * | |
1202 | * @pdev: pci dev pointer | |
1203 | * | |
1204 | * Callback for the switcheroo driver. Check of the switcheroo | |
1205 | * state can be changed. | |
1206 | * Returns true if the state can be changed, false if not. | |
1207 | */ | |
1208 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1209 | { | |
1210 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1211 | ||
1212 | /* | |
1213 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1214 | * locking inversion with the driver load path. And the access here is | |
1215 | * completely racy anyway. So don't bother with locking for now. | |
1216 | */ | |
1217 | return dev->open_count == 0; | |
1218 | } | |
1219 | ||
1220 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1221 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1222 | .reprobe = NULL, | |
1223 | .can_switch = amdgpu_switcheroo_can_switch, | |
1224 | }; | |
1225 | ||
1226 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1227 | enum amd_ip_block_type block_type, |
1228 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1229 | { |
1230 | int i, r = 0; | |
1231 | ||
1232 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1233 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1234 | continue; |
c722865a RZ |
1235 | if (adev->ip_blocks[i].version->type != block_type) |
1236 | continue; | |
1237 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1238 | continue; | |
1239 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1240 | (void *)adev, state); | |
1241 | if (r) | |
1242 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1243 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1244 | } |
1245 | return r; | |
1246 | } | |
1247 | ||
1248 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1249 | enum amd_ip_block_type block_type, |
1250 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1251 | { |
1252 | int i, r = 0; | |
1253 | ||
1254 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1255 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1256 | continue; |
c722865a RZ |
1257 | if (adev->ip_blocks[i].version->type != block_type) |
1258 | continue; | |
1259 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1260 | continue; | |
1261 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1262 | (void *)adev, state); | |
1263 | if (r) | |
1264 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1265 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1266 | } |
1267 | return r; | |
1268 | } | |
1269 | ||
6cb2d4e4 HR |
1270 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1271 | { | |
1272 | int i; | |
1273 | ||
1274 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1275 | if (!adev->ip_blocks[i].status.valid) | |
1276 | continue; | |
1277 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1278 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1279 | } | |
1280 | } | |
1281 | ||
5dbbb60b AD |
1282 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1283 | enum amd_ip_block_type block_type) | |
1284 | { | |
1285 | int i, r; | |
1286 | ||
1287 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1288 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1289 | continue; |
a1255107 AD |
1290 | if (adev->ip_blocks[i].version->type == block_type) { |
1291 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1292 | if (r) |
1293 | return r; | |
1294 | break; | |
1295 | } | |
1296 | } | |
1297 | return 0; | |
1298 | ||
1299 | } | |
1300 | ||
1301 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1302 | enum amd_ip_block_type block_type) | |
1303 | { | |
1304 | int i; | |
1305 | ||
1306 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1307 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1308 | continue; |
a1255107 AD |
1309 | if (adev->ip_blocks[i].version->type == block_type) |
1310 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1311 | } |
1312 | return true; | |
1313 | ||
1314 | } | |
1315 | ||
a1255107 AD |
1316 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1317 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1318 | { |
1319 | int i; | |
1320 | ||
1321 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1322 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1323 | return &adev->ip_blocks[i]; |
1324 | ||
1325 | return NULL; | |
1326 | } | |
1327 | ||
1328 | /** | |
1329 | * amdgpu_ip_block_version_cmp | |
1330 | * | |
1331 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1332 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1333 | * @major: major version |
1334 | * @minor: minor version | |
1335 | * | |
1336 | * return 0 if equal or greater | |
1337 | * return 1 if smaller or the ip_block doesn't exist | |
1338 | */ | |
1339 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1340 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1341 | u32 major, u32 minor) |
1342 | { | |
a1255107 | 1343 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1344 | |
a1255107 AD |
1345 | if (ip_block && ((ip_block->version->major > major) || |
1346 | ((ip_block->version->major == major) && | |
1347 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1348 | return 0; |
1349 | ||
1350 | return 1; | |
1351 | } | |
1352 | ||
a1255107 AD |
1353 | /** |
1354 | * amdgpu_ip_block_add | |
1355 | * | |
1356 | * @adev: amdgpu_device pointer | |
1357 | * @ip_block_version: pointer to the IP to add | |
1358 | * | |
1359 | * Adds the IP block driver information to the collection of IPs | |
1360 | * on the asic. | |
1361 | */ | |
1362 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1363 | const struct amdgpu_ip_block_version *ip_block_version) | |
1364 | { | |
1365 | if (!ip_block_version) | |
1366 | return -EINVAL; | |
1367 | ||
a0bae357 HR |
1368 | DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, |
1369 | ip_block_version->funcs->name); | |
1370 | ||
a1255107 AD |
1371 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
483ef985 | 1376 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1377 | { |
1378 | adev->enable_virtual_display = false; | |
1379 | ||
1380 | if (amdgpu_virtual_display) { | |
1381 | struct drm_device *ddev = adev->ddev; | |
1382 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1383 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1384 | |
1385 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1386 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1387 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1388 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1389 | if (!strcmp("all", pciaddname) |
1390 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1391 | long num_crtc; |
1392 | int res = -1; | |
1393 | ||
9accf2fd | 1394 | adev->enable_virtual_display = true; |
0f66356d ED |
1395 | |
1396 | if (pciaddname_tmp) | |
1397 | res = kstrtol(pciaddname_tmp, 10, | |
1398 | &num_crtc); | |
1399 | ||
1400 | if (!res) { | |
1401 | if (num_crtc < 1) | |
1402 | num_crtc = 1; | |
1403 | if (num_crtc > 6) | |
1404 | num_crtc = 6; | |
1405 | adev->mode_info.num_crtc = num_crtc; | |
1406 | } else { | |
1407 | adev->mode_info.num_crtc = 1; | |
1408 | } | |
9accf2fd ED |
1409 | break; |
1410 | } | |
1411 | } | |
1412 | ||
0f66356d ED |
1413 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1414 | amdgpu_virtual_display, pci_address_name, | |
1415 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1416 | |
1417 | kfree(pciaddstr); | |
1418 | } | |
1419 | } | |
1420 | ||
e2a75f88 AD |
1421 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1422 | { | |
e2a75f88 AD |
1423 | const char *chip_name; |
1424 | char fw_name[30]; | |
1425 | int err; | |
1426 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1427 | ||
ab4fe3e1 HR |
1428 | adev->firmware.gpu_info_fw = NULL; |
1429 | ||
e2a75f88 AD |
1430 | switch (adev->asic_type) { |
1431 | case CHIP_TOPAZ: | |
1432 | case CHIP_TONGA: | |
1433 | case CHIP_FIJI: | |
1434 | case CHIP_POLARIS11: | |
1435 | case CHIP_POLARIS10: | |
1436 | case CHIP_POLARIS12: | |
1437 | case CHIP_CARRIZO: | |
1438 | case CHIP_STONEY: | |
1439 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1440 | case CHIP_VERDE: | |
1441 | case CHIP_TAHITI: | |
1442 | case CHIP_PITCAIRN: | |
1443 | case CHIP_OLAND: | |
1444 | case CHIP_HAINAN: | |
1445 | #endif | |
1446 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1447 | case CHIP_BONAIRE: | |
1448 | case CHIP_HAWAII: | |
1449 | case CHIP_KAVERI: | |
1450 | case CHIP_KABINI: | |
1451 | case CHIP_MULLINS: | |
1452 | #endif | |
1453 | default: | |
1454 | return 0; | |
1455 | case CHIP_VEGA10: | |
1456 | chip_name = "vega10"; | |
1457 | break; | |
2d2e5e7e AD |
1458 | case CHIP_RAVEN: |
1459 | chip_name = "raven"; | |
1460 | break; | |
e2a75f88 AD |
1461 | } |
1462 | ||
1463 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1464 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1465 | if (err) { |
1466 | dev_err(adev->dev, | |
1467 | "Failed to load gpu_info firmware \"%s\"\n", | |
1468 | fw_name); | |
1469 | goto out; | |
1470 | } | |
ab4fe3e1 | 1471 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1472 | if (err) { |
1473 | dev_err(adev->dev, | |
1474 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1475 | fw_name); | |
1476 | goto out; | |
1477 | } | |
1478 | ||
ab4fe3e1 | 1479 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1480 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1481 | ||
1482 | switch (hdr->version_major) { | |
1483 | case 1: | |
1484 | { | |
1485 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1486 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1487 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1488 | ||
b5ab16bf AD |
1489 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1490 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1491 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1492 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1493 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1494 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1495 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1496 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1497 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1498 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1499 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1500 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1501 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1502 | adev->gfx.cu_info.max_waves_per_simd = |
1503 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1504 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1505 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1506 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1507 | break; |
1508 | } | |
1509 | default: | |
1510 | dev_err(adev->dev, | |
1511 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1512 | err = -EINVAL; | |
1513 | goto out; | |
1514 | } | |
1515 | out: | |
e2a75f88 AD |
1516 | return err; |
1517 | } | |
1518 | ||
d38ceaf9 AD |
1519 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1520 | { | |
aaa36a97 | 1521 | int i, r; |
d38ceaf9 | 1522 | |
483ef985 | 1523 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1524 | |
d38ceaf9 | 1525 | switch (adev->asic_type) { |
aaa36a97 AD |
1526 | case CHIP_TOPAZ: |
1527 | case CHIP_TONGA: | |
48299f95 | 1528 | case CHIP_FIJI: |
2cc0c0b5 FC |
1529 | case CHIP_POLARIS11: |
1530 | case CHIP_POLARIS10: | |
c4642a47 | 1531 | case CHIP_POLARIS12: |
aaa36a97 | 1532 | case CHIP_CARRIZO: |
39bb0c92 SL |
1533 | case CHIP_STONEY: |
1534 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1535 | adev->family = AMDGPU_FAMILY_CZ; |
1536 | else | |
1537 | adev->family = AMDGPU_FAMILY_VI; | |
1538 | ||
1539 | r = vi_set_ip_blocks(adev); | |
1540 | if (r) | |
1541 | return r; | |
1542 | break; | |
33f34802 KW |
1543 | #ifdef CONFIG_DRM_AMDGPU_SI |
1544 | case CHIP_VERDE: | |
1545 | case CHIP_TAHITI: | |
1546 | case CHIP_PITCAIRN: | |
1547 | case CHIP_OLAND: | |
1548 | case CHIP_HAINAN: | |
295d0daf | 1549 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1550 | r = si_set_ip_blocks(adev); |
1551 | if (r) | |
1552 | return r; | |
1553 | break; | |
1554 | #endif | |
a2e73f56 AD |
1555 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1556 | case CHIP_BONAIRE: | |
1557 | case CHIP_HAWAII: | |
1558 | case CHIP_KAVERI: | |
1559 | case CHIP_KABINI: | |
1560 | case CHIP_MULLINS: | |
1561 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1562 | adev->family = AMDGPU_FAMILY_CI; | |
1563 | else | |
1564 | adev->family = AMDGPU_FAMILY_KV; | |
1565 | ||
1566 | r = cik_set_ip_blocks(adev); | |
1567 | if (r) | |
1568 | return r; | |
1569 | break; | |
1570 | #endif | |
2ca8a5d2 CZ |
1571 | case CHIP_VEGA10: |
1572 | case CHIP_RAVEN: | |
1573 | if (adev->asic_type == CHIP_RAVEN) | |
1574 | adev->family = AMDGPU_FAMILY_RV; | |
1575 | else | |
1576 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1577 | |
1578 | r = soc15_set_ip_blocks(adev); | |
1579 | if (r) | |
1580 | return r; | |
1581 | break; | |
d38ceaf9 AD |
1582 | default: |
1583 | /* FIXME: not supported yet */ | |
1584 | return -EINVAL; | |
1585 | } | |
1586 | ||
e2a75f88 AD |
1587 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1588 | if (r) | |
1589 | return r; | |
1590 | ||
3149d9da XY |
1591 | if (amdgpu_sriov_vf(adev)) { |
1592 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1593 | if (r) | |
1594 | return r; | |
1595 | } | |
1596 | ||
d38ceaf9 AD |
1597 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1598 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1599 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1600 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1601 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1602 | } else { |
a1255107 AD |
1603 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1604 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1605 | if (r == -ENOENT) { |
a1255107 | 1606 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1607 | } else if (r) { |
a1255107 AD |
1608 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1609 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1610 | return r; |
2c1a2784 | 1611 | } else { |
a1255107 | 1612 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1613 | } |
974e6b64 | 1614 | } else { |
a1255107 | 1615 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1616 | } |
d38ceaf9 AD |
1617 | } |
1618 | } | |
1619 | ||
395d1fb9 NH |
1620 | adev->cg_flags &= amdgpu_cg_mask; |
1621 | adev->pg_flags &= amdgpu_pg_mask; | |
1622 | ||
d38ceaf9 AD |
1623 | return 0; |
1624 | } | |
1625 | ||
1626 | static int amdgpu_init(struct amdgpu_device *adev) | |
1627 | { | |
1628 | int i, r; | |
1629 | ||
1630 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1631 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1632 | continue; |
a1255107 | 1633 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1634 | if (r) { |
a1255107 AD |
1635 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1636 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1637 | return r; |
2c1a2784 | 1638 | } |
a1255107 | 1639 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1640 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1641 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1642 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1643 | if (r) { |
1644 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1645 | return r; |
2c1a2784 | 1646 | } |
a1255107 | 1647 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1648 | if (r) { |
1649 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1650 | return r; |
2c1a2784 | 1651 | } |
d38ceaf9 | 1652 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1653 | if (r) { |
1654 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1655 | return r; |
2c1a2784 | 1656 | } |
a1255107 | 1657 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1658 | |
1659 | /* right after GMC hw init, we create CSA */ | |
1660 | if (amdgpu_sriov_vf(adev)) { | |
1661 | r = amdgpu_allocate_static_csa(adev); | |
1662 | if (r) { | |
1663 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1664 | return r; | |
1665 | } | |
1666 | } | |
d38ceaf9 AD |
1667 | } |
1668 | } | |
1669 | ||
1670 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1671 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1672 | continue; |
1673 | /* gmc hw init is done early */ | |
a1255107 | 1674 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1675 | continue; |
a1255107 | 1676 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1677 | if (r) { |
a1255107 AD |
1678 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1679 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1680 | return r; |
2c1a2784 | 1681 | } |
a1255107 | 1682 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1683 | } |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
0c49e0b8 CZ |
1688 | static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) |
1689 | { | |
1690 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1691 | } | |
1692 | ||
1693 | static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) | |
1694 | { | |
1695 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1696 | AMDGPU_RESET_MAGIC_NUM); | |
1697 | } | |
1698 | ||
2dc80b00 | 1699 | static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1700 | { |
1701 | int i = 0, r; | |
1702 | ||
1703 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1704 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1705 | continue; |
4a446d55 | 1706 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1707 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1708 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1709 | /* enable clockgating to save power */ |
a1255107 AD |
1710 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1711 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1712 | if (r) { |
1713 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1714 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1715 | return r; |
1716 | } | |
b0b00ff1 | 1717 | } |
d38ceaf9 | 1718 | } |
2dc80b00 S |
1719 | return 0; |
1720 | } | |
1721 | ||
1722 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1723 | { | |
1724 | int i = 0, r; | |
1725 | ||
1726 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1727 | if (!adev->ip_blocks[i].status.valid) | |
1728 | continue; | |
1729 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1730 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1731 | if (r) { | |
1732 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1733 | adev->ip_blocks[i].version->funcs->name, r); | |
1734 | return r; | |
1735 | } | |
1736 | adev->ip_blocks[i].status.late_initialized = true; | |
1737 | } | |
1738 | } | |
1739 | ||
1740 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1741 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1742 | |
0c49e0b8 CZ |
1743 | amdgpu_fill_reset_magic(adev); |
1744 | ||
d38ceaf9 AD |
1745 | return 0; |
1746 | } | |
1747 | ||
1748 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1749 | { | |
1750 | int i, r; | |
1751 | ||
3e96dbfd AD |
1752 | /* need to disable SMC first */ |
1753 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1754 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1755 | continue; |
a1255107 | 1756 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1757 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1758 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1759 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1760 | if (r) { |
1761 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1762 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1763 | return r; |
1764 | } | |
a1255107 | 1765 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1766 | /* XXX handle errors */ |
1767 | if (r) { | |
1768 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1769 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1770 | } |
a1255107 | 1771 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1772 | break; |
1773 | } | |
1774 | } | |
1775 | ||
d38ceaf9 | 1776 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1777 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1778 | continue; |
a1255107 | 1779 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1780 | amdgpu_wb_fini(adev); |
1781 | amdgpu_vram_scratch_fini(adev); | |
1782 | } | |
8201a67a RZ |
1783 | |
1784 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1785 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1786 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1787 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1788 | AMD_CG_STATE_UNGATE); | |
1789 | if (r) { | |
1790 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1791 | adev->ip_blocks[i].version->funcs->name, r); | |
1792 | return r; | |
1793 | } | |
2c1a2784 | 1794 | } |
8201a67a | 1795 | |
a1255107 | 1796 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1797 | /* XXX handle errors */ |
2c1a2784 | 1798 | if (r) { |
a1255107 AD |
1799 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1800 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1801 | } |
8201a67a | 1802 | |
a1255107 | 1803 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1804 | } |
1805 | ||
1806 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1807 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1808 | continue; |
a1255107 | 1809 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1810 | /* XXX handle errors */ |
2c1a2784 | 1811 | if (r) { |
a1255107 AD |
1812 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1813 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1814 | } |
a1255107 AD |
1815 | adev->ip_blocks[i].status.sw = false; |
1816 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1817 | } |
1818 | ||
a6dcfd9c | 1819 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1820 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1821 | continue; |
a1255107 AD |
1822 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1823 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1824 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1825 | } |
1826 | ||
3149d9da | 1827 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1828 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1829 | amdgpu_virt_release_full_gpu(adev, false); |
1830 | } | |
2493664f | 1831 | |
d38ceaf9 AD |
1832 | return 0; |
1833 | } | |
1834 | ||
2dc80b00 S |
1835 | static void amdgpu_late_init_func_handler(struct work_struct *work) |
1836 | { | |
1837 | struct amdgpu_device *adev = | |
1838 | container_of(work, struct amdgpu_device, late_init_work.work); | |
1839 | amdgpu_late_set_cg_state(adev); | |
1840 | } | |
1841 | ||
faefba95 | 1842 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1843 | { |
1844 | int i, r; | |
1845 | ||
e941ea99 XY |
1846 | if (amdgpu_sriov_vf(adev)) |
1847 | amdgpu_virt_request_full_gpu(adev, false); | |
1848 | ||
c5a93a28 FC |
1849 | /* ungate SMC block first */ |
1850 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1851 | AMD_CG_STATE_UNGATE); | |
1852 | if (r) { | |
1853 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1854 | } | |
1855 | ||
d38ceaf9 | 1856 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1857 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1858 | continue; |
1859 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1860 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1861 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1862 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1863 | if (r) { |
a1255107 AD |
1864 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1865 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1866 | } |
2c1a2784 | 1867 | } |
d38ceaf9 | 1868 | /* XXX handle errors */ |
a1255107 | 1869 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1870 | /* XXX handle errors */ |
2c1a2784 | 1871 | if (r) { |
a1255107 AD |
1872 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1873 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1874 | } |
d38ceaf9 AD |
1875 | } |
1876 | ||
e941ea99 XY |
1877 | if (amdgpu_sriov_vf(adev)) |
1878 | amdgpu_virt_release_full_gpu(adev, false); | |
1879 | ||
d38ceaf9 AD |
1880 | return 0; |
1881 | } | |
1882 | ||
e4f0fdcc | 1883 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1884 | { |
1885 | int i, r; | |
1886 | ||
2cb681b6 ML |
1887 | static enum amd_ip_block_type ip_order[] = { |
1888 | AMD_IP_BLOCK_TYPE_GMC, | |
1889 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1890 | AMD_IP_BLOCK_TYPE_IH, |
1891 | }; | |
1892 | ||
1893 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { | |
1894 | int j; | |
1895 | struct amdgpu_ip_block *block; | |
1896 | ||
1897 | for (j = 0; j < adev->num_ip_blocks; j++) { | |
1898 | block = &adev->ip_blocks[j]; | |
1899 | ||
1900 | if (block->version->type != ip_order[i] || | |
1901 | !block->status.valid) | |
1902 | continue; | |
1903 | ||
1904 | r = block->version->funcs->hw_init(adev); | |
1905 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1906 | } |
1907 | } | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
e4f0fdcc | 1912 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1913 | { |
1914 | int i, r; | |
1915 | ||
2cb681b6 ML |
1916 | static enum amd_ip_block_type ip_order[] = { |
1917 | AMD_IP_BLOCK_TYPE_SMC, | |
1918 | AMD_IP_BLOCK_TYPE_DCE, | |
1919 | AMD_IP_BLOCK_TYPE_GFX, | |
1920 | AMD_IP_BLOCK_TYPE_SDMA, | |
1921 | AMD_IP_BLOCK_TYPE_VCE, | |
1922 | }; | |
a90ad3c2 | 1923 | |
2cb681b6 ML |
1924 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1925 | int j; | |
1926 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1927 | |
2cb681b6 ML |
1928 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1929 | block = &adev->ip_blocks[j]; | |
1930 | ||
1931 | if (block->version->type != ip_order[i] || | |
1932 | !block->status.valid) | |
1933 | continue; | |
1934 | ||
1935 | r = block->version->funcs->hw_init(adev); | |
1936 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1937 | } |
1938 | } | |
1939 | ||
1940 | return 0; | |
1941 | } | |
1942 | ||
fcf0649f | 1943 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1944 | { |
1945 | int i, r; | |
1946 | ||
1947 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1948 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1949 | continue; |
fcf0649f CZ |
1950 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1951 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1952 | adev->ip_blocks[i].version->type == | |
1953 | AMD_IP_BLOCK_TYPE_IH) { | |
1954 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1955 | if (r) { | |
1956 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1957 | adev->ip_blocks[i].version->funcs->name, r); | |
1958 | return r; | |
1959 | } | |
1960 | } | |
1961 | } | |
1962 | ||
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) | |
1967 | { | |
1968 | int i, r; | |
1969 | ||
1970 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1971 | if (!adev->ip_blocks[i].status.valid) | |
1972 | continue; | |
1973 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1974 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1975 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1976 | continue; | |
a1255107 | 1977 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1978 | if (r) { |
a1255107 AD |
1979 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1980 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1981 | return r; |
2c1a2784 | 1982 | } |
d38ceaf9 AD |
1983 | } |
1984 | ||
1985 | return 0; | |
1986 | } | |
1987 | ||
fcf0649f CZ |
1988 | static int amdgpu_resume(struct amdgpu_device *adev) |
1989 | { | |
1990 | int r; | |
1991 | ||
1992 | r = amdgpu_resume_phase1(adev); | |
1993 | if (r) | |
1994 | return r; | |
1995 | r = amdgpu_resume_phase2(adev); | |
1996 | ||
1997 | return r; | |
1998 | } | |
1999 | ||
4e99a44e | 2000 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2001 | { |
a5bde2f9 AD |
2002 | if (adev->is_atom_fw) { |
2003 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2004 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2005 | } else { | |
2006 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2007 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2008 | } | |
048765ad AR |
2009 | } |
2010 | ||
d38ceaf9 AD |
2011 | /** |
2012 | * amdgpu_device_init - initialize the driver | |
2013 | * | |
2014 | * @adev: amdgpu_device pointer | |
2015 | * @pdev: drm dev pointer | |
2016 | * @pdev: pci dev pointer | |
2017 | * @flags: driver flags | |
2018 | * | |
2019 | * Initializes the driver info and hw (all asics). | |
2020 | * Returns 0 for success or an error on failure. | |
2021 | * Called at driver startup. | |
2022 | */ | |
2023 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2024 | struct drm_device *ddev, | |
2025 | struct pci_dev *pdev, | |
2026 | uint32_t flags) | |
2027 | { | |
2028 | int r, i; | |
2029 | bool runtime = false; | |
95844d20 | 2030 | u32 max_MBps; |
d38ceaf9 AD |
2031 | |
2032 | adev->shutdown = false; | |
2033 | adev->dev = &pdev->dev; | |
2034 | adev->ddev = ddev; | |
2035 | adev->pdev = pdev; | |
2036 | adev->flags = flags; | |
2f7d10b3 | 2037 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2038 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
6f02a696 | 2039 | adev->mc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2040 | adev->accel_working = false; |
2041 | adev->num_rings = 0; | |
2042 | adev->mman.buffer_funcs = NULL; | |
2043 | adev->mman.buffer_funcs_ring = NULL; | |
2044 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2045 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 2046 | adev->gart.gart_funcs = NULL; |
f54d1867 | 2047 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
2048 | |
2049 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2050 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2051 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2052 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2053 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2054 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2055 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2056 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2057 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2058 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2059 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2060 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2061 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2062 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2063 | ||
ccdbb20a | 2064 | |
3e39ab90 AD |
2065 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2066 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2067 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2068 | |
2069 | /* mutex initialization are all done here so we | |
2070 | * can recall function without having locking issues */ | |
d38ceaf9 | 2071 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2072 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2073 | mutex_init(&adev->pm.mutex); |
2074 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2075 | mutex_init(&adev->srbm_mutex); | |
2076 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
2077 | mutex_init(&adev->mn_lock); |
2078 | hash_init(adev->mn_hash); | |
2079 | ||
2080 | amdgpu_check_arguments(adev); | |
2081 | ||
d38ceaf9 AD |
2082 | spin_lock_init(&adev->mmio_idx_lock); |
2083 | spin_lock_init(&adev->smc_idx_lock); | |
2084 | spin_lock_init(&adev->pcie_idx_lock); | |
2085 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2086 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2087 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2088 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2089 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2090 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2091 | |
0c4e7fa5 CZ |
2092 | INIT_LIST_HEAD(&adev->shadow_list); |
2093 | mutex_init(&adev->shadow_list_lock); | |
2094 | ||
5c1354bd CZ |
2095 | INIT_LIST_HEAD(&adev->gtt_list); |
2096 | spin_lock_init(&adev->gtt_list_lock); | |
2097 | ||
795f2813 AR |
2098 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2099 | spin_lock_init(&adev->ring_lru_list_lock); | |
2100 | ||
2dc80b00 S |
2101 | INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); |
2102 | ||
0fa49558 AX |
2103 | /* Registers mapping */ |
2104 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2105 | if (adev->asic_type >= CHIP_BONAIRE) { |
2106 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2107 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2108 | } else { | |
2109 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2110 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2111 | } | |
d38ceaf9 | 2112 | |
d38ceaf9 AD |
2113 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2114 | if (adev->rmmio == NULL) { | |
2115 | return -ENOMEM; | |
2116 | } | |
2117 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2118 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2119 | ||
da69c161 KW |
2120 | if (adev->asic_type >= CHIP_BONAIRE) |
2121 | /* doorbell bar mapping */ | |
2122 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2123 | |
2124 | /* io port mapping */ | |
2125 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2126 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2127 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2128 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2129 | break; | |
2130 | } | |
2131 | } | |
2132 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2133 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2134 | |
2135 | /* early init functions */ | |
2136 | r = amdgpu_early_init(adev); | |
2137 | if (r) | |
2138 | return r; | |
2139 | ||
2140 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2141 | /* this will fail for cards that aren't VGA class devices, just | |
2142 | * ignore it */ | |
2143 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2144 | ||
2145 | if (amdgpu_runtime_pm == 1) | |
2146 | runtime = true; | |
e9bef455 | 2147 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2148 | runtime = true; |
84c8b22e LW |
2149 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2150 | vga_switcheroo_register_client(adev->pdev, | |
2151 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2152 | if (runtime) |
2153 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2154 | ||
2155 | /* Read BIOS */ | |
83ba126a AD |
2156 | if (!amdgpu_get_bios(adev)) { |
2157 | r = -EINVAL; | |
2158 | goto failed; | |
2159 | } | |
f7e9e9fe | 2160 | |
d38ceaf9 | 2161 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2162 | if (r) { |
2163 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
89041940 | 2164 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2165 | goto failed; |
2c1a2784 | 2166 | } |
d38ceaf9 | 2167 | |
4e99a44e ML |
2168 | /* detect if we are with an SRIOV vbios */ |
2169 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2170 | |
d38ceaf9 | 2171 | /* Post card if necessary */ |
bec86378 | 2172 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 2173 | if (!adev->bios) { |
bec86378 | 2174 | dev_err(adev->dev, "no vBIOS found\n"); |
89041940 | 2175 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); |
83ba126a AD |
2176 | r = -EINVAL; |
2177 | goto failed; | |
d38ceaf9 | 2178 | } |
bec86378 | 2179 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2180 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2181 | if (r) { | |
2182 | dev_err(adev->dev, "gpu post error!\n"); | |
89041940 | 2183 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0); |
4e99a44e ML |
2184 | goto failed; |
2185 | } | |
2186 | } else { | |
2187 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
2188 | } |
2189 | ||
a5bde2f9 AD |
2190 | if (!adev->is_atom_fw) { |
2191 | /* Initialize clocks */ | |
2192 | r = amdgpu_atombios_get_clock_info(adev); | |
2193 | if (r) { | |
2194 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
89041940 GW |
2195 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
2196 | goto failed; | |
a5bde2f9 AD |
2197 | } |
2198 | /* init i2c buses */ | |
2199 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2200 | } |
d38ceaf9 AD |
2201 | |
2202 | /* Fence driver */ | |
2203 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2204 | if (r) { |
2205 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
89041940 | 2206 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2207 | goto failed; |
2c1a2784 | 2208 | } |
d38ceaf9 AD |
2209 | |
2210 | /* init the mode config */ | |
2211 | drm_mode_config_init(adev->ddev); | |
2212 | ||
2213 | r = amdgpu_init(adev); | |
2214 | if (r) { | |
2c1a2784 | 2215 | dev_err(adev->dev, "amdgpu_init failed\n"); |
89041940 | 2216 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
d38ceaf9 | 2217 | amdgpu_fini(adev); |
83ba126a | 2218 | goto failed; |
d38ceaf9 AD |
2219 | } |
2220 | ||
2221 | adev->accel_working = true; | |
2222 | ||
e59c0205 AX |
2223 | amdgpu_vm_check_compute_bug(adev); |
2224 | ||
95844d20 MO |
2225 | /* Initialize the buffer migration limit. */ |
2226 | if (amdgpu_moverate >= 0) | |
2227 | max_MBps = amdgpu_moverate; | |
2228 | else | |
2229 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2230 | /* Get a log2 for easy divisions. */ | |
2231 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2232 | ||
d38ceaf9 AD |
2233 | r = amdgpu_ib_pool_init(adev); |
2234 | if (r) { | |
2235 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
89041940 | 2236 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2237 | goto failed; |
d38ceaf9 AD |
2238 | } |
2239 | ||
2240 | r = amdgpu_ib_ring_tests(adev); | |
2241 | if (r) | |
2242 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2243 | ||
9bc92b9c ML |
2244 | amdgpu_fbdev_init(adev); |
2245 | ||
d38ceaf9 | 2246 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2247 | if (r) |
d38ceaf9 | 2248 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2249 | |
2250 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2251 | if (r) |
d38ceaf9 | 2252 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2253 | |
4f0955fc HR |
2254 | r = amdgpu_debugfs_test_ib_ring_init(adev); |
2255 | if (r) | |
2256 | DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); | |
2257 | ||
50ab2533 | 2258 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2259 | if (r) |
50ab2533 | 2260 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2261 | |
d38ceaf9 AD |
2262 | if ((amdgpu_testing & 1)) { |
2263 | if (adev->accel_working) | |
2264 | amdgpu_test_moves(adev); | |
2265 | else | |
2266 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2267 | } | |
d38ceaf9 AD |
2268 | if (amdgpu_benchmarking) { |
2269 | if (adev->accel_working) | |
2270 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2271 | else | |
2272 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2273 | } | |
2274 | ||
2275 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2276 | * explicit gating rather than handling it automatically. | |
2277 | */ | |
2278 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2279 | if (r) { |
2280 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
89041940 | 2281 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2282 | goto failed; |
2c1a2784 | 2283 | } |
d38ceaf9 AD |
2284 | |
2285 | return 0; | |
83ba126a AD |
2286 | |
2287 | failed: | |
89041940 | 2288 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2289 | if (runtime) |
2290 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2291 | return r; | |
d38ceaf9 AD |
2292 | } |
2293 | ||
d38ceaf9 AD |
2294 | /** |
2295 | * amdgpu_device_fini - tear down the driver | |
2296 | * | |
2297 | * @adev: amdgpu_device pointer | |
2298 | * | |
2299 | * Tear down the driver info (all asics). | |
2300 | * Called at driver shutdown. | |
2301 | */ | |
2302 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2303 | { | |
2304 | int r; | |
2305 | ||
2306 | DRM_INFO("amdgpu: finishing device.\n"); | |
2307 | adev->shutdown = true; | |
db2c2a97 PD |
2308 | if (adev->mode_info.mode_config_initialized) |
2309 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2310 | /* evict vram memory */ |
2311 | amdgpu_bo_evict_vram(adev); | |
2312 | amdgpu_ib_pool_fini(adev); | |
2313 | amdgpu_fence_driver_fini(adev); | |
2314 | amdgpu_fbdev_fini(adev); | |
2315 | r = amdgpu_fini(adev); | |
ab4fe3e1 HR |
2316 | if (adev->firmware.gpu_info_fw) { |
2317 | release_firmware(adev->firmware.gpu_info_fw); | |
2318 | adev->firmware.gpu_info_fw = NULL; | |
2319 | } | |
d38ceaf9 | 2320 | adev->accel_working = false; |
2dc80b00 | 2321 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 AD |
2322 | /* free i2c buses */ |
2323 | amdgpu_i2c_fini(adev); | |
2324 | amdgpu_atombios_fini(adev); | |
2325 | kfree(adev->bios); | |
2326 | adev->bios = NULL; | |
84c8b22e LW |
2327 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2328 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2329 | if (adev->flags & AMD_IS_PX) |
2330 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2331 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2332 | if (adev->rio_mem) | |
2333 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2334 | adev->rio_mem = NULL; | |
2335 | iounmap(adev->rmmio); | |
2336 | adev->rmmio = NULL; | |
da69c161 KW |
2337 | if (adev->asic_type >= CHIP_BONAIRE) |
2338 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2339 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2340 | } |
2341 | ||
2342 | ||
2343 | /* | |
2344 | * Suspend & resume. | |
2345 | */ | |
2346 | /** | |
810ddc3a | 2347 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2348 | * |
2349 | * @pdev: drm dev pointer | |
2350 | * @state: suspend state | |
2351 | * | |
2352 | * Puts the hw in the suspend state (all asics). | |
2353 | * Returns 0 for success or an error on failure. | |
2354 | * Called at driver suspend. | |
2355 | */ | |
810ddc3a | 2356 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2357 | { |
2358 | struct amdgpu_device *adev; | |
2359 | struct drm_crtc *crtc; | |
2360 | struct drm_connector *connector; | |
5ceb54c6 | 2361 | int r; |
d38ceaf9 AD |
2362 | |
2363 | if (dev == NULL || dev->dev_private == NULL) { | |
2364 | return -ENODEV; | |
2365 | } | |
2366 | ||
2367 | adev = dev->dev_private; | |
2368 | ||
2369 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2370 | return 0; | |
2371 | ||
2372 | drm_kms_helper_poll_disable(dev); | |
2373 | ||
2374 | /* turn off display hw */ | |
4c7fbc39 | 2375 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2376 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2377 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2378 | } | |
4c7fbc39 | 2379 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2380 | |
756e6880 | 2381 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2382 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2383 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2384 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2385 | struct amdgpu_bo *robj; | |
2386 | ||
756e6880 AD |
2387 | if (amdgpu_crtc->cursor_bo) { |
2388 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2389 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2390 | if (r == 0) { |
2391 | amdgpu_bo_unpin(aobj); | |
2392 | amdgpu_bo_unreserve(aobj); | |
2393 | } | |
2394 | } | |
2395 | ||
d38ceaf9 AD |
2396 | if (rfb == NULL || rfb->obj == NULL) { |
2397 | continue; | |
2398 | } | |
2399 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2400 | /* don't unpin kernel fb objects */ | |
2401 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2402 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2403 | if (r == 0) { |
2404 | amdgpu_bo_unpin(robj); | |
2405 | amdgpu_bo_unreserve(robj); | |
2406 | } | |
2407 | } | |
2408 | } | |
2409 | /* evict vram memory */ | |
2410 | amdgpu_bo_evict_vram(adev); | |
2411 | ||
5ceb54c6 | 2412 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2413 | |
2414 | r = amdgpu_suspend(adev); | |
2415 | ||
a0a71e49 AD |
2416 | /* evict remaining vram memory |
2417 | * This second call to evict vram is to evict the gart page table | |
2418 | * using the CPU. | |
2419 | */ | |
d38ceaf9 AD |
2420 | amdgpu_bo_evict_vram(adev); |
2421 | ||
d05da0e2 | 2422 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
2423 | pci_save_state(dev->pdev); |
2424 | if (suspend) { | |
2425 | /* Shut down the device */ | |
2426 | pci_disable_device(dev->pdev); | |
2427 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2428 | } else { |
2429 | r = amdgpu_asic_reset(adev); | |
2430 | if (r) | |
2431 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2432 | } |
2433 | ||
2434 | if (fbcon) { | |
2435 | console_lock(); | |
2436 | amdgpu_fbdev_set_suspend(adev, 1); | |
2437 | console_unlock(); | |
2438 | } | |
2439 | return 0; | |
2440 | } | |
2441 | ||
2442 | /** | |
810ddc3a | 2443 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2444 | * |
2445 | * @pdev: drm dev pointer | |
2446 | * | |
2447 | * Bring the hw back to operating state (all asics). | |
2448 | * Returns 0 for success or an error on failure. | |
2449 | * Called at driver resume. | |
2450 | */ | |
810ddc3a | 2451 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2452 | { |
2453 | struct drm_connector *connector; | |
2454 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2455 | struct drm_crtc *crtc; |
03161a6e | 2456 | int r = 0; |
d38ceaf9 AD |
2457 | |
2458 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2459 | return 0; | |
2460 | ||
74b0b157 | 2461 | if (fbcon) |
d38ceaf9 | 2462 | console_lock(); |
74b0b157 | 2463 | |
d38ceaf9 AD |
2464 | if (resume) { |
2465 | pci_set_power_state(dev->pdev, PCI_D0); | |
2466 | pci_restore_state(dev->pdev); | |
74b0b157 | 2467 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2468 | if (r) |
2469 | goto unlock; | |
d38ceaf9 | 2470 | } |
d05da0e2 | 2471 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2472 | |
2473 | /* post card */ | |
c836fec5 | 2474 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2475 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2476 | if (r) | |
2477 | DRM_ERROR("amdgpu asic init failed\n"); | |
2478 | } | |
d38ceaf9 AD |
2479 | |
2480 | r = amdgpu_resume(adev); | |
e6707218 | 2481 | if (r) { |
ca198528 | 2482 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2483 | goto unlock; |
e6707218 | 2484 | } |
5ceb54c6 AD |
2485 | amdgpu_fence_driver_resume(adev); |
2486 | ||
ca198528 FC |
2487 | if (resume) { |
2488 | r = amdgpu_ib_ring_tests(adev); | |
2489 | if (r) | |
2490 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2491 | } | |
d38ceaf9 AD |
2492 | |
2493 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2494 | if (r) |
2495 | goto unlock; | |
d38ceaf9 | 2496 | |
756e6880 AD |
2497 | /* pin cursors */ |
2498 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2499 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2500 | ||
2501 | if (amdgpu_crtc->cursor_bo) { | |
2502 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2503 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2504 | if (r == 0) { |
2505 | r = amdgpu_bo_pin(aobj, | |
2506 | AMDGPU_GEM_DOMAIN_VRAM, | |
2507 | &amdgpu_crtc->cursor_addr); | |
2508 | if (r != 0) | |
2509 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2510 | amdgpu_bo_unreserve(aobj); | |
2511 | } | |
2512 | } | |
2513 | } | |
2514 | ||
d38ceaf9 AD |
2515 | /* blat the mode back in */ |
2516 | if (fbcon) { | |
2517 | drm_helper_resume_force_mode(dev); | |
2518 | /* turn on display hw */ | |
4c7fbc39 | 2519 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2520 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2521 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2522 | } | |
4c7fbc39 | 2523 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2524 | } |
2525 | ||
2526 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2527 | |
2528 | /* | |
2529 | * Most of the connector probing functions try to acquire runtime pm | |
2530 | * refs to ensure that the GPU is powered on when connector polling is | |
2531 | * performed. Since we're calling this from a runtime PM callback, | |
2532 | * trying to acquire rpm refs will cause us to deadlock. | |
2533 | * | |
2534 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2535 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2536 | */ | |
2537 | #ifdef CONFIG_PM | |
2538 | dev->dev->power.disable_depth++; | |
2539 | #endif | |
54fb2a5c | 2540 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2541 | #ifdef CONFIG_PM |
2542 | dev->dev->power.disable_depth--; | |
2543 | #endif | |
d38ceaf9 | 2544 | |
03161a6e | 2545 | if (fbcon) |
d38ceaf9 | 2546 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2547 | |
2548 | unlock: | |
2549 | if (fbcon) | |
d38ceaf9 | 2550 | console_unlock(); |
d38ceaf9 | 2551 | |
03161a6e | 2552 | return r; |
d38ceaf9 AD |
2553 | } |
2554 | ||
63fbf42f CZ |
2555 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2556 | { | |
2557 | int i; | |
2558 | bool asic_hang = false; | |
2559 | ||
2560 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2561 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2562 | continue; |
a1255107 AD |
2563 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2564 | adev->ip_blocks[i].status.hang = | |
2565 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2566 | if (adev->ip_blocks[i].status.hang) { | |
2567 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2568 | asic_hang = true; |
2569 | } | |
2570 | } | |
2571 | return asic_hang; | |
2572 | } | |
2573 | ||
4d446656 | 2574 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2575 | { |
2576 | int i, r = 0; | |
2577 | ||
2578 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2579 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2580 | continue; |
a1255107 AD |
2581 | if (adev->ip_blocks[i].status.hang && |
2582 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2583 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2584 | if (r) |
2585 | return r; | |
2586 | } | |
2587 | } | |
2588 | ||
2589 | return 0; | |
2590 | } | |
2591 | ||
35d782fe CZ |
2592 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2593 | { | |
da146d3b AD |
2594 | int i; |
2595 | ||
2596 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2597 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2598 | continue; |
a1255107 AD |
2599 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2600 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2601 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2602 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2603 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2604 | DRM_INFO("Some block need full reset!\n"); |
2605 | return true; | |
2606 | } | |
2607 | } | |
35d782fe CZ |
2608 | } |
2609 | return false; | |
2610 | } | |
2611 | ||
2612 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2613 | { | |
2614 | int i, r = 0; | |
2615 | ||
2616 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2617 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2618 | continue; |
a1255107 AD |
2619 | if (adev->ip_blocks[i].status.hang && |
2620 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2621 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2622 | if (r) |
2623 | return r; | |
2624 | } | |
2625 | } | |
2626 | ||
2627 | return 0; | |
2628 | } | |
2629 | ||
2630 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2631 | { | |
2632 | int i, r = 0; | |
2633 | ||
2634 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2635 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2636 | continue; |
a1255107 AD |
2637 | if (adev->ip_blocks[i].status.hang && |
2638 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2639 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2640 | if (r) |
2641 | return r; | |
2642 | } | |
2643 | ||
2644 | return 0; | |
2645 | } | |
2646 | ||
3ad81f16 CZ |
2647 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2648 | { | |
2649 | if (adev->flags & AMD_IS_APU) | |
2650 | return false; | |
2651 | ||
2652 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2653 | } | |
2654 | ||
53cdccd5 CZ |
2655 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2656 | struct amdgpu_ring *ring, | |
2657 | struct amdgpu_bo *bo, | |
f54d1867 | 2658 | struct dma_fence **fence) |
53cdccd5 CZ |
2659 | { |
2660 | uint32_t domain; | |
2661 | int r; | |
2662 | ||
23d2e504 RH |
2663 | if (!bo->shadow) |
2664 | return 0; | |
2665 | ||
1d284797 | 2666 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2667 | if (r) |
2668 | return r; | |
2669 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2670 | /* if bo has been evicted, then no need to recover */ | |
2671 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2672 | r = amdgpu_bo_validate(bo->shadow); |
2673 | if (r) { | |
2674 | DRM_ERROR("bo validate failed!\n"); | |
2675 | goto err; | |
2676 | } | |
2677 | ||
2678 | r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem); | |
2679 | if (r) { | |
2680 | DRM_ERROR("%p bind failed\n", bo->shadow); | |
2681 | goto err; | |
2682 | } | |
2683 | ||
23d2e504 | 2684 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2685 | NULL, fence, true); |
23d2e504 RH |
2686 | if (r) { |
2687 | DRM_ERROR("recover page table failed!\n"); | |
2688 | goto err; | |
2689 | } | |
2690 | } | |
53cdccd5 | 2691 | err: |
23d2e504 RH |
2692 | amdgpu_bo_unreserve(bo); |
2693 | return r; | |
53cdccd5 CZ |
2694 | } |
2695 | ||
a90ad3c2 ML |
2696 | /** |
2697 | * amdgpu_sriov_gpu_reset - reset the asic | |
2698 | * | |
2699 | * @adev: amdgpu device pointer | |
7225f873 | 2700 | * @job: which job trigger hang |
a90ad3c2 ML |
2701 | * |
2702 | * Attempt the reset the GPU if it has hung (all asics). | |
2703 | * for SRIOV case. | |
2704 | * Returns 0 for success or an error on failure. | |
2705 | */ | |
7225f873 | 2706 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) |
a90ad3c2 | 2707 | { |
65781c78 | 2708 | int i, j, r = 0; |
a90ad3c2 ML |
2709 | int resched; |
2710 | struct amdgpu_bo *bo, *tmp; | |
2711 | struct amdgpu_ring *ring; | |
2712 | struct dma_fence *fence = NULL, *next = NULL; | |
2713 | ||
147b5983 | 2714 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2715 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2716 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2717 | |
2718 | /* block TTM */ | |
2719 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2720 | ||
65781c78 ML |
2721 | /* we start from the ring trigger GPU hang */ |
2722 | j = job ? job->ring->idx : 0; | |
a90ad3c2 | 2723 | |
65781c78 ML |
2724 | /* block scheduler */ |
2725 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { | |
2726 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2727 | if (!ring || !ring->sched.thread) |
2728 | continue; | |
2729 | ||
2730 | kthread_park(ring->sched.thread); | |
65781c78 ML |
2731 | |
2732 | if (job && j != i) | |
2733 | continue; | |
2734 | ||
4f059ecd | 2735 | /* here give the last chance to check if job removed from mirror-list |
65781c78 | 2736 | * since we already pay some time on kthread_park */ |
4f059ecd | 2737 | if (job && list_empty(&job->base.node)) { |
65781c78 ML |
2738 | kthread_unpark(ring->sched.thread); |
2739 | goto give_up_reset; | |
2740 | } | |
2741 | ||
2742 | if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) | |
2743 | amd_sched_job_kickout(&job->base); | |
2744 | ||
2745 | /* only do job_reset on the hang ring if @job not NULL */ | |
a90ad3c2 | 2746 | amd_sched_hw_job_reset(&ring->sched); |
a90ad3c2 | 2747 | |
65781c78 ML |
2748 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2749 | amdgpu_fence_driver_force_completion_ring(ring); | |
2750 | } | |
a90ad3c2 ML |
2751 | |
2752 | /* request to take full control of GPU before re-initialization */ | |
7225f873 | 2753 | if (job) |
a90ad3c2 ML |
2754 | amdgpu_virt_reset_gpu(adev); |
2755 | else | |
2756 | amdgpu_virt_request_full_gpu(adev, true); | |
2757 | ||
2758 | ||
2759 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2760 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2761 | |
2762 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2763 | amdgpu_ttm_recover_gart(adev); | |
2764 | ||
2765 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2766 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2767 | |
2768 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2769 | ||
2770 | if (amdgpu_ib_ring_tests(adev)) | |
2771 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2772 | ||
2773 | /* release full control of GPU after ib test */ | |
2774 | amdgpu_virt_release_full_gpu(adev, true); | |
2775 | ||
2776 | DRM_INFO("recover vram bo from shadow\n"); | |
2777 | ||
2778 | ring = adev->mman.buffer_funcs_ring; | |
2779 | mutex_lock(&adev->shadow_list_lock); | |
2780 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2781 | next = NULL; |
a90ad3c2 ML |
2782 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2783 | if (fence) { | |
2784 | r = dma_fence_wait(fence, false); | |
2785 | if (r) { | |
2786 | WARN(r, "recovery from shadow isn't completed\n"); | |
2787 | break; | |
2788 | } | |
2789 | } | |
2790 | ||
2791 | dma_fence_put(fence); | |
2792 | fence = next; | |
2793 | } | |
2794 | mutex_unlock(&adev->shadow_list_lock); | |
2795 | ||
2796 | if (fence) { | |
2797 | r = dma_fence_wait(fence, false); | |
2798 | if (r) | |
2799 | WARN(r, "recovery from shadow isn't completed\n"); | |
2800 | } | |
2801 | dma_fence_put(fence); | |
2802 | ||
65781c78 ML |
2803 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { |
2804 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2805 | if (!ring || !ring->sched.thread) |
2806 | continue; | |
2807 | ||
65781c78 ML |
2808 | if (job && j != i) { |
2809 | kthread_unpark(ring->sched.thread); | |
2810 | continue; | |
2811 | } | |
2812 | ||
a90ad3c2 ML |
2813 | amd_sched_job_recovery(&ring->sched); |
2814 | kthread_unpark(ring->sched.thread); | |
2815 | } | |
2816 | ||
2817 | drm_helper_resume_force_mode(adev->ddev); | |
65781c78 | 2818 | give_up_reset: |
a90ad3c2 ML |
2819 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); |
2820 | if (r) { | |
2821 | /* bad news, how to tell it to userspace ? */ | |
2822 | dev_info(adev->dev, "GPU reset failed\n"); | |
65781c78 ML |
2823 | } else { |
2824 | dev_info(adev->dev, "GPU reset successed!\n"); | |
a90ad3c2 ML |
2825 | } |
2826 | ||
1fb37a3d | 2827 | adev->gfx.in_reset = false; |
147b5983 | 2828 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2829 | return r; |
2830 | } | |
2831 | ||
d38ceaf9 AD |
2832 | /** |
2833 | * amdgpu_gpu_reset - reset the asic | |
2834 | * | |
2835 | * @adev: amdgpu device pointer | |
2836 | * | |
2837 | * Attempt the reset the GPU if it has hung (all asics). | |
2838 | * Returns 0 for success or an error on failure. | |
2839 | */ | |
2840 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2841 | { | |
d38ceaf9 AD |
2842 | int i, r; |
2843 | int resched; | |
0c49e0b8 | 2844 | bool need_full_reset, vram_lost = false; |
d38ceaf9 | 2845 | |
63fbf42f CZ |
2846 | if (!amdgpu_check_soft_reset(adev)) { |
2847 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2848 | return 0; | |
2849 | } | |
d38ceaf9 | 2850 | |
d94aed5a | 2851 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2852 | |
a3c47d6b CZ |
2853 | /* block TTM */ |
2854 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2855 | ||
0875dc9e CZ |
2856 | /* block scheduler */ |
2857 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2858 | struct amdgpu_ring *ring = adev->rings[i]; | |
2859 | ||
51687759 | 2860 | if (!ring || !ring->sched.thread) |
0875dc9e CZ |
2861 | continue; |
2862 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2863 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2864 | } |
2200edac CZ |
2865 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2866 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2867 | |
35d782fe | 2868 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2869 | |
35d782fe CZ |
2870 | if (!need_full_reset) { |
2871 | amdgpu_pre_soft_reset(adev); | |
2872 | r = amdgpu_soft_reset(adev); | |
2873 | amdgpu_post_soft_reset(adev); | |
2874 | if (r || amdgpu_check_soft_reset(adev)) { | |
2875 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2876 | need_full_reset = true; | |
2877 | } | |
f1aa7e08 CZ |
2878 | } |
2879 | ||
35d782fe | 2880 | if (need_full_reset) { |
35d782fe | 2881 | r = amdgpu_suspend(adev); |
bfa99269 | 2882 | |
35d782fe | 2883 | retry: |
d05da0e2 | 2884 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2885 | r = amdgpu_asic_reset(adev); |
d05da0e2 | 2886 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2887 | /* post card */ |
2888 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2889 | ||
2890 | if (!r) { | |
2891 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
fcf0649f CZ |
2892 | r = amdgpu_resume_phase1(adev); |
2893 | if (r) | |
2894 | goto out; | |
0c49e0b8 | 2895 | vram_lost = amdgpu_check_vram_lost(adev); |
f1892138 | 2896 | if (vram_lost) { |
0c49e0b8 | 2897 | DRM_ERROR("VRAM is lost!\n"); |
f1892138 CZ |
2898 | atomic_inc(&adev->vram_lost_counter); |
2899 | } | |
fcf0649f CZ |
2900 | r = amdgpu_ttm_recover_gart(adev); |
2901 | if (r) | |
2902 | goto out; | |
2903 | r = amdgpu_resume_phase2(adev); | |
2904 | if (r) | |
2905 | goto out; | |
0c49e0b8 CZ |
2906 | if (vram_lost) |
2907 | amdgpu_fill_reset_magic(adev); | |
35d782fe | 2908 | } |
d38ceaf9 | 2909 | } |
fcf0649f | 2910 | out: |
d38ceaf9 | 2911 | if (!r) { |
e72cfd58 | 2912 | amdgpu_irq_gpu_reset_resume_helper(adev); |
1f465087 CZ |
2913 | r = amdgpu_ib_ring_tests(adev); |
2914 | if (r) { | |
2915 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2916 | r = amdgpu_suspend(adev); |
53cdccd5 | 2917 | need_full_reset = true; |
40019dc4 | 2918 | goto retry; |
1f465087 | 2919 | } |
53cdccd5 CZ |
2920 | /** |
2921 | * recovery vm page tables, since we cannot depend on VRAM is | |
2922 | * consistent after gpu full reset. | |
2923 | */ | |
2924 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2925 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2926 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2927 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2928 | |
2929 | DRM_INFO("recover vram bo from shadow\n"); | |
2930 | mutex_lock(&adev->shadow_list_lock); | |
2931 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2932 | next = NULL; |
53cdccd5 CZ |
2933 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2934 | if (fence) { | |
f54d1867 | 2935 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2936 | if (r) { |
1d7b17b0 | 2937 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2938 | break; |
2939 | } | |
2940 | } | |
1f465087 | 2941 | |
f54d1867 | 2942 | dma_fence_put(fence); |
53cdccd5 CZ |
2943 | fence = next; |
2944 | } | |
2945 | mutex_unlock(&adev->shadow_list_lock); | |
2946 | if (fence) { | |
f54d1867 | 2947 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2948 | if (r) |
1d7b17b0 | 2949 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2950 | } |
f54d1867 | 2951 | dma_fence_put(fence); |
53cdccd5 | 2952 | } |
d38ceaf9 AD |
2953 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2954 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
2955 | |
2956 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 2957 | continue; |
53cdccd5 | 2958 | |
aa1c8900 | 2959 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2960 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2961 | } |
d38ceaf9 | 2962 | } else { |
2200edac | 2963 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
89041940 | 2964 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r); |
d38ceaf9 | 2965 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
51687759 | 2966 | if (adev->rings[i] && adev->rings[i]->sched.thread) { |
0875dc9e | 2967 | kthread_unpark(adev->rings[i]->sched.thread); |
0875dc9e | 2968 | } |
d38ceaf9 AD |
2969 | } |
2970 | } | |
2971 | ||
2972 | drm_helper_resume_force_mode(adev->ddev); | |
2973 | ||
2974 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
89041940 | 2975 | if (r) { |
d38ceaf9 AD |
2976 | /* bad news, how to tell it to userspace ? */ |
2977 | dev_info(adev->dev, "GPU reset failed\n"); | |
89041940 GW |
2978 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
2979 | } | |
2980 | else { | |
6643be65 | 2981 | dev_info(adev->dev, "GPU reset successed!\n"); |
89041940 | 2982 | } |
d38ceaf9 | 2983 | |
89041940 | 2984 | amdgpu_vf_error_trans_all(adev); |
d38ceaf9 AD |
2985 | return r; |
2986 | } | |
2987 | ||
d0dd7f0c AD |
2988 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2989 | { | |
2990 | u32 mask; | |
2991 | int ret; | |
2992 | ||
cd474ba0 AD |
2993 | if (amdgpu_pcie_gen_cap) |
2994 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2995 | |
cd474ba0 AD |
2996 | if (amdgpu_pcie_lane_cap) |
2997 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2998 | |
cd474ba0 AD |
2999 | /* covers APUs as well */ |
3000 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3001 | if (adev->pm.pcie_gen_mask == 0) | |
3002 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3003 | if (adev->pm.pcie_mlw_mask == 0) | |
3004 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3005 | return; |
cd474ba0 | 3006 | } |
d0dd7f0c | 3007 | |
cd474ba0 AD |
3008 | if (adev->pm.pcie_gen_mask == 0) { |
3009 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
3010 | if (!ret) { | |
3011 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3012 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3013 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3014 | ||
3015 | if (mask & DRM_PCIE_SPEED_25) | |
3016 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3017 | if (mask & DRM_PCIE_SPEED_50) | |
3018 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3019 | if (mask & DRM_PCIE_SPEED_80) | |
3020 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3021 | } else { | |
3022 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3023 | } | |
3024 | } | |
3025 | if (adev->pm.pcie_mlw_mask == 0) { | |
3026 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3027 | if (!ret) { | |
3028 | switch (mask) { | |
3029 | case 32: | |
3030 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3031 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3032 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3033 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3034 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3035 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3036 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3037 | break; | |
3038 | case 16: | |
3039 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3040 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3041 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3042 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3043 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3044 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3045 | break; | |
3046 | case 12: | |
3047 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3048 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3049 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3050 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3051 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3052 | break; | |
3053 | case 8: | |
3054 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3055 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3056 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3057 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3058 | break; | |
3059 | case 4: | |
3060 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3061 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3062 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3063 | break; | |
3064 | case 2: | |
3065 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3066 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3067 | break; | |
3068 | case 1: | |
3069 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3070 | break; | |
3071 | default: | |
3072 | break; | |
3073 | } | |
3074 | } else { | |
3075 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3076 | } |
3077 | } | |
3078 | } | |
d38ceaf9 AD |
3079 | |
3080 | /* | |
3081 | * Debugfs | |
3082 | */ | |
3083 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3084 | const struct drm_info_list *files, |
d38ceaf9 AD |
3085 | unsigned nfiles) |
3086 | { | |
3087 | unsigned i; | |
3088 | ||
3089 | for (i = 0; i < adev->debugfs_count; i++) { | |
3090 | if (adev->debugfs[i].files == files) { | |
3091 | /* Already registered */ | |
3092 | return 0; | |
3093 | } | |
3094 | } | |
3095 | ||
3096 | i = adev->debugfs_count + 1; | |
3097 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3098 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3099 | DRM_ERROR("Report so we increase " | |
3100 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3101 | return -EINVAL; | |
3102 | } | |
3103 | adev->debugfs[adev->debugfs_count].files = files; | |
3104 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3105 | adev->debugfs_count = i; | |
3106 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3107 | drm_debugfs_create_files(files, nfiles, |
3108 | adev->ddev->primary->debugfs_root, | |
3109 | adev->ddev->primary); | |
3110 | #endif | |
3111 | return 0; | |
3112 | } | |
3113 | ||
d38ceaf9 AD |
3114 | #if defined(CONFIG_DEBUG_FS) |
3115 | ||
3116 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3117 | size_t size, loff_t *pos) | |
3118 | { | |
45063097 | 3119 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3120 | ssize_t result = 0; |
3121 | int r; | |
bd12267d | 3122 | bool pm_pg_lock, use_bank; |
56628159 | 3123 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3124 | |
3125 | if (size & 0x3 || *pos & 0x3) | |
3126 | return -EINVAL; | |
3127 | ||
bd12267d TSD |
3128 | /* are we reading registers for which a PG lock is necessary? */ |
3129 | pm_pg_lock = (*pos >> 23) & 1; | |
3130 | ||
56628159 TSD |
3131 | if (*pos & (1ULL << 62)) { |
3132 | se_bank = (*pos >> 24) & 0x3FF; | |
3133 | sh_bank = (*pos >> 34) & 0x3FF; | |
3134 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
3135 | |
3136 | if (se_bank == 0x3FF) | |
3137 | se_bank = 0xFFFFFFFF; | |
3138 | if (sh_bank == 0x3FF) | |
3139 | sh_bank = 0xFFFFFFFF; | |
3140 | if (instance_bank == 0x3FF) | |
3141 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3142 | use_bank = 1; |
56628159 TSD |
3143 | } else { |
3144 | use_bank = 0; | |
3145 | } | |
3146 | ||
801a6aa9 | 3147 | *pos &= (1UL << 22) - 1; |
bd12267d | 3148 | |
56628159 | 3149 | if (use_bank) { |
32977f93 TSD |
3150 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3151 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3152 | return -EINVAL; |
3153 | mutex_lock(&adev->grbm_idx_mutex); | |
3154 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3155 | sh_bank, instance_bank); | |
3156 | } | |
3157 | ||
bd12267d TSD |
3158 | if (pm_pg_lock) |
3159 | mutex_lock(&adev->pm.mutex); | |
3160 | ||
d38ceaf9 AD |
3161 | while (size) { |
3162 | uint32_t value; | |
3163 | ||
3164 | if (*pos > adev->rmmio_size) | |
56628159 | 3165 | goto end; |
d38ceaf9 AD |
3166 | |
3167 | value = RREG32(*pos >> 2); | |
3168 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3169 | if (r) { |
3170 | result = r; | |
3171 | goto end; | |
3172 | } | |
d38ceaf9 AD |
3173 | |
3174 | result += 4; | |
3175 | buf += 4; | |
3176 | *pos += 4; | |
3177 | size -= 4; | |
3178 | } | |
3179 | ||
56628159 TSD |
3180 | end: |
3181 | if (use_bank) { | |
3182 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3183 | mutex_unlock(&adev->grbm_idx_mutex); | |
3184 | } | |
3185 | ||
bd12267d TSD |
3186 | if (pm_pg_lock) |
3187 | mutex_unlock(&adev->pm.mutex); | |
3188 | ||
d38ceaf9 AD |
3189 | return result; |
3190 | } | |
3191 | ||
3192 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3193 | size_t size, loff_t *pos) | |
3194 | { | |
45063097 | 3195 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3196 | ssize_t result = 0; |
3197 | int r; | |
394fdde2 TSD |
3198 | bool pm_pg_lock, use_bank; |
3199 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3200 | |
3201 | if (size & 0x3 || *pos & 0x3) | |
3202 | return -EINVAL; | |
3203 | ||
394fdde2 TSD |
3204 | /* are we reading registers for which a PG lock is necessary? */ |
3205 | pm_pg_lock = (*pos >> 23) & 1; | |
3206 | ||
3207 | if (*pos & (1ULL << 62)) { | |
3208 | se_bank = (*pos >> 24) & 0x3FF; | |
3209 | sh_bank = (*pos >> 34) & 0x3FF; | |
3210 | instance_bank = (*pos >> 44) & 0x3FF; | |
3211 | ||
3212 | if (se_bank == 0x3FF) | |
3213 | se_bank = 0xFFFFFFFF; | |
3214 | if (sh_bank == 0x3FF) | |
3215 | sh_bank = 0xFFFFFFFF; | |
3216 | if (instance_bank == 0x3FF) | |
3217 | instance_bank = 0xFFFFFFFF; | |
3218 | use_bank = 1; | |
3219 | } else { | |
3220 | use_bank = 0; | |
3221 | } | |
3222 | ||
801a6aa9 | 3223 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3224 | |
3225 | if (use_bank) { | |
3226 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3227 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3228 | return -EINVAL; | |
3229 | mutex_lock(&adev->grbm_idx_mutex); | |
3230 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3231 | sh_bank, instance_bank); | |
3232 | } | |
3233 | ||
3234 | if (pm_pg_lock) | |
3235 | mutex_lock(&adev->pm.mutex); | |
3236 | ||
d38ceaf9 AD |
3237 | while (size) { |
3238 | uint32_t value; | |
3239 | ||
3240 | if (*pos > adev->rmmio_size) | |
3241 | return result; | |
3242 | ||
3243 | r = get_user(value, (uint32_t *)buf); | |
3244 | if (r) | |
3245 | return r; | |
3246 | ||
3247 | WREG32(*pos >> 2, value); | |
3248 | ||
3249 | result += 4; | |
3250 | buf += 4; | |
3251 | *pos += 4; | |
3252 | size -= 4; | |
3253 | } | |
3254 | ||
394fdde2 TSD |
3255 | if (use_bank) { |
3256 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3257 | mutex_unlock(&adev->grbm_idx_mutex); | |
3258 | } | |
3259 | ||
3260 | if (pm_pg_lock) | |
3261 | mutex_unlock(&adev->pm.mutex); | |
3262 | ||
d38ceaf9 AD |
3263 | return result; |
3264 | } | |
3265 | ||
adcec288 TSD |
3266 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3267 | size_t size, loff_t *pos) | |
3268 | { | |
45063097 | 3269 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3270 | ssize_t result = 0; |
3271 | int r; | |
3272 | ||
3273 | if (size & 0x3 || *pos & 0x3) | |
3274 | return -EINVAL; | |
3275 | ||
3276 | while (size) { | |
3277 | uint32_t value; | |
3278 | ||
3279 | value = RREG32_PCIE(*pos >> 2); | |
3280 | r = put_user(value, (uint32_t *)buf); | |
3281 | if (r) | |
3282 | return r; | |
3283 | ||
3284 | result += 4; | |
3285 | buf += 4; | |
3286 | *pos += 4; | |
3287 | size -= 4; | |
3288 | } | |
3289 | ||
3290 | return result; | |
3291 | } | |
3292 | ||
3293 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3294 | size_t size, loff_t *pos) | |
3295 | { | |
45063097 | 3296 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3297 | ssize_t result = 0; |
3298 | int r; | |
3299 | ||
3300 | if (size & 0x3 || *pos & 0x3) | |
3301 | return -EINVAL; | |
3302 | ||
3303 | while (size) { | |
3304 | uint32_t value; | |
3305 | ||
3306 | r = get_user(value, (uint32_t *)buf); | |
3307 | if (r) | |
3308 | return r; | |
3309 | ||
3310 | WREG32_PCIE(*pos >> 2, value); | |
3311 | ||
3312 | result += 4; | |
3313 | buf += 4; | |
3314 | *pos += 4; | |
3315 | size -= 4; | |
3316 | } | |
3317 | ||
3318 | return result; | |
3319 | } | |
3320 | ||
3321 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3322 | size_t size, loff_t *pos) | |
3323 | { | |
45063097 | 3324 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3325 | ssize_t result = 0; |
3326 | int r; | |
3327 | ||
3328 | if (size & 0x3 || *pos & 0x3) | |
3329 | return -EINVAL; | |
3330 | ||
3331 | while (size) { | |
3332 | uint32_t value; | |
3333 | ||
3334 | value = RREG32_DIDT(*pos >> 2); | |
3335 | r = put_user(value, (uint32_t *)buf); | |
3336 | if (r) | |
3337 | return r; | |
3338 | ||
3339 | result += 4; | |
3340 | buf += 4; | |
3341 | *pos += 4; | |
3342 | size -= 4; | |
3343 | } | |
3344 | ||
3345 | return result; | |
3346 | } | |
3347 | ||
3348 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3349 | size_t size, loff_t *pos) | |
3350 | { | |
45063097 | 3351 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3352 | ssize_t result = 0; |
3353 | int r; | |
3354 | ||
3355 | if (size & 0x3 || *pos & 0x3) | |
3356 | return -EINVAL; | |
3357 | ||
3358 | while (size) { | |
3359 | uint32_t value; | |
3360 | ||
3361 | r = get_user(value, (uint32_t *)buf); | |
3362 | if (r) | |
3363 | return r; | |
3364 | ||
3365 | WREG32_DIDT(*pos >> 2, value); | |
3366 | ||
3367 | result += 4; | |
3368 | buf += 4; | |
3369 | *pos += 4; | |
3370 | size -= 4; | |
3371 | } | |
3372 | ||
3373 | return result; | |
3374 | } | |
3375 | ||
3376 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3377 | size_t size, loff_t *pos) | |
3378 | { | |
45063097 | 3379 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3380 | ssize_t result = 0; |
3381 | int r; | |
3382 | ||
3383 | if (size & 0x3 || *pos & 0x3) | |
3384 | return -EINVAL; | |
3385 | ||
3386 | while (size) { | |
3387 | uint32_t value; | |
3388 | ||
6fc0deaf | 3389 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3390 | r = put_user(value, (uint32_t *)buf); |
3391 | if (r) | |
3392 | return r; | |
3393 | ||
3394 | result += 4; | |
3395 | buf += 4; | |
3396 | *pos += 4; | |
3397 | size -= 4; | |
3398 | } | |
3399 | ||
3400 | return result; | |
3401 | } | |
3402 | ||
3403 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3404 | size_t size, loff_t *pos) | |
3405 | { | |
45063097 | 3406 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3407 | ssize_t result = 0; |
3408 | int r; | |
3409 | ||
3410 | if (size & 0x3 || *pos & 0x3) | |
3411 | return -EINVAL; | |
3412 | ||
3413 | while (size) { | |
3414 | uint32_t value; | |
3415 | ||
3416 | r = get_user(value, (uint32_t *)buf); | |
3417 | if (r) | |
3418 | return r; | |
3419 | ||
6fc0deaf | 3420 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3421 | |
3422 | result += 4; | |
3423 | buf += 4; | |
3424 | *pos += 4; | |
3425 | size -= 4; | |
3426 | } | |
3427 | ||
3428 | return result; | |
3429 | } | |
3430 | ||
1e051413 TSD |
3431 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3432 | size_t size, loff_t *pos) | |
3433 | { | |
45063097 | 3434 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3435 | ssize_t result = 0; |
3436 | int r; | |
3437 | uint32_t *config, no_regs = 0; | |
3438 | ||
3439 | if (size & 0x3 || *pos & 0x3) | |
3440 | return -EINVAL; | |
3441 | ||
ecab7668 | 3442 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3443 | if (!config) |
3444 | return -ENOMEM; | |
3445 | ||
3446 | /* version, increment each time something is added */ | |
9a999359 | 3447 | config[no_regs++] = 3; |
1e051413 TSD |
3448 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3449 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3450 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3451 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3452 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3453 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3454 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3455 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3456 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3457 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3458 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3459 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3460 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3461 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3462 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3463 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3464 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3465 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3466 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3467 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3468 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3469 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3470 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3471 | ||
89a8f309 TSD |
3472 | /* rev==1 */ |
3473 | config[no_regs++] = adev->rev_id; | |
3474 | config[no_regs++] = adev->pg_flags; | |
3475 | config[no_regs++] = adev->cg_flags; | |
3476 | ||
e9f11dc8 TSD |
3477 | /* rev==2 */ |
3478 | config[no_regs++] = adev->family; | |
3479 | config[no_regs++] = adev->external_rev_id; | |
3480 | ||
9a999359 TSD |
3481 | /* rev==3 */ |
3482 | config[no_regs++] = adev->pdev->device; | |
3483 | config[no_regs++] = adev->pdev->revision; | |
3484 | config[no_regs++] = adev->pdev->subsystem_device; | |
3485 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3486 | ||
1e051413 TSD |
3487 | while (size && (*pos < no_regs * 4)) { |
3488 | uint32_t value; | |
3489 | ||
3490 | value = config[*pos >> 2]; | |
3491 | r = put_user(value, (uint32_t *)buf); | |
3492 | if (r) { | |
3493 | kfree(config); | |
3494 | return r; | |
3495 | } | |
3496 | ||
3497 | result += 4; | |
3498 | buf += 4; | |
3499 | *pos += 4; | |
3500 | size -= 4; | |
3501 | } | |
3502 | ||
3503 | kfree(config); | |
3504 | return result; | |
3505 | } | |
3506 | ||
f2cdaf20 TSD |
3507 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3508 | size_t size, loff_t *pos) | |
3509 | { | |
45063097 | 3510 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3511 | int idx, x, outsize, r, valuesize; |
3512 | uint32_t values[16]; | |
f2cdaf20 | 3513 | |
9f8df7d7 | 3514 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3515 | return -EINVAL; |
3516 | ||
3cbc614f SP |
3517 | if (amdgpu_dpm == 0) |
3518 | return -EINVAL; | |
3519 | ||
f2cdaf20 TSD |
3520 | /* convert offset to sensor number */ |
3521 | idx = *pos >> 2; | |
3522 | ||
9f8df7d7 | 3523 | valuesize = sizeof(values); |
f2cdaf20 | 3524 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3525 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3526 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3527 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3528 | &valuesize); | |
f2cdaf20 TSD |
3529 | else |
3530 | return -EINVAL; | |
3531 | ||
9f8df7d7 TSD |
3532 | if (size > valuesize) |
3533 | return -EINVAL; | |
3534 | ||
3535 | outsize = 0; | |
3536 | x = 0; | |
3537 | if (!r) { | |
3538 | while (size) { | |
3539 | r = put_user(values[x++], (int32_t *)buf); | |
3540 | buf += 4; | |
3541 | size -= 4; | |
3542 | outsize += 4; | |
3543 | } | |
3544 | } | |
f2cdaf20 | 3545 | |
9f8df7d7 | 3546 | return !r ? outsize : r; |
f2cdaf20 | 3547 | } |
1e051413 | 3548 | |
273d7aa1 TSD |
3549 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3550 | size_t size, loff_t *pos) | |
3551 | { | |
3552 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3553 | int r, x; | |
3554 | ssize_t result=0; | |
472259f0 | 3555 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3556 | |
3557 | if (size & 3 || *pos & 3) | |
3558 | return -EINVAL; | |
3559 | ||
3560 | /* decode offset */ | |
3561 | offset = (*pos & 0x7F); | |
3562 | se = ((*pos >> 7) & 0xFF); | |
3563 | sh = ((*pos >> 15) & 0xFF); | |
3564 | cu = ((*pos >> 23) & 0xFF); | |
3565 | wave = ((*pos >> 31) & 0xFF); | |
3566 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3567 | |
3568 | /* switch to the specific se/sh/cu */ | |
3569 | mutex_lock(&adev->grbm_idx_mutex); | |
3570 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3571 | ||
3572 | x = 0; | |
472259f0 TSD |
3573 | if (adev->gfx.funcs->read_wave_data) |
3574 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3575 | |
3576 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3577 | mutex_unlock(&adev->grbm_idx_mutex); | |
3578 | ||
5ecfb3b8 TSD |
3579 | if (!x) |
3580 | return -EINVAL; | |
3581 | ||
472259f0 | 3582 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3583 | uint32_t value; |
3584 | ||
472259f0 | 3585 | value = data[offset >> 2]; |
273d7aa1 TSD |
3586 | r = put_user(value, (uint32_t *)buf); |
3587 | if (r) | |
3588 | return r; | |
3589 | ||
3590 | result += 4; | |
3591 | buf += 4; | |
472259f0 | 3592 | offset += 4; |
273d7aa1 TSD |
3593 | size -= 4; |
3594 | } | |
3595 | ||
3596 | return result; | |
3597 | } | |
3598 | ||
c5a60ce8 TSD |
3599 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3600 | size_t size, loff_t *pos) | |
3601 | { | |
3602 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3603 | int r; | |
3604 | ssize_t result = 0; | |
3605 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3606 | ||
3607 | if (size & 3 || *pos & 3) | |
3608 | return -EINVAL; | |
3609 | ||
3610 | /* decode offset */ | |
3611 | offset = (*pos & 0xFFF); /* in dwords */ | |
3612 | se = ((*pos >> 12) & 0xFF); | |
3613 | sh = ((*pos >> 20) & 0xFF); | |
3614 | cu = ((*pos >> 28) & 0xFF); | |
3615 | wave = ((*pos >> 36) & 0xFF); | |
3616 | simd = ((*pos >> 44) & 0xFF); | |
3617 | thread = ((*pos >> 52) & 0xFF); | |
3618 | bank = ((*pos >> 60) & 1); | |
3619 | ||
3620 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3621 | if (!data) | |
3622 | return -ENOMEM; | |
3623 | ||
3624 | /* switch to the specific se/sh/cu */ | |
3625 | mutex_lock(&adev->grbm_idx_mutex); | |
3626 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3627 | ||
3628 | if (bank == 0) { | |
3629 | if (adev->gfx.funcs->read_wave_vgprs) | |
3630 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3631 | } else { | |
3632 | if (adev->gfx.funcs->read_wave_sgprs) | |
3633 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3634 | } | |
3635 | ||
3636 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3637 | mutex_unlock(&adev->grbm_idx_mutex); | |
3638 | ||
3639 | while (size) { | |
3640 | uint32_t value; | |
3641 | ||
3642 | value = data[offset++]; | |
3643 | r = put_user(value, (uint32_t *)buf); | |
3644 | if (r) { | |
3645 | result = r; | |
3646 | goto err; | |
3647 | } | |
3648 | ||
3649 | result += 4; | |
3650 | buf += 4; | |
3651 | size -= 4; | |
3652 | } | |
3653 | ||
3654 | err: | |
3655 | kfree(data); | |
3656 | return result; | |
3657 | } | |
3658 | ||
d38ceaf9 AD |
3659 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3660 | .owner = THIS_MODULE, | |
3661 | .read = amdgpu_debugfs_regs_read, | |
3662 | .write = amdgpu_debugfs_regs_write, | |
3663 | .llseek = default_llseek | |
3664 | }; | |
adcec288 TSD |
3665 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3666 | .owner = THIS_MODULE, | |
3667 | .read = amdgpu_debugfs_regs_didt_read, | |
3668 | .write = amdgpu_debugfs_regs_didt_write, | |
3669 | .llseek = default_llseek | |
3670 | }; | |
3671 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3672 | .owner = THIS_MODULE, | |
3673 | .read = amdgpu_debugfs_regs_pcie_read, | |
3674 | .write = amdgpu_debugfs_regs_pcie_write, | |
3675 | .llseek = default_llseek | |
3676 | }; | |
3677 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3678 | .owner = THIS_MODULE, | |
3679 | .read = amdgpu_debugfs_regs_smc_read, | |
3680 | .write = amdgpu_debugfs_regs_smc_write, | |
3681 | .llseek = default_llseek | |
3682 | }; | |
3683 | ||
1e051413 TSD |
3684 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3685 | .owner = THIS_MODULE, | |
3686 | .read = amdgpu_debugfs_gca_config_read, | |
3687 | .llseek = default_llseek | |
3688 | }; | |
3689 | ||
f2cdaf20 TSD |
3690 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3691 | .owner = THIS_MODULE, | |
3692 | .read = amdgpu_debugfs_sensor_read, | |
3693 | .llseek = default_llseek | |
3694 | }; | |
3695 | ||
273d7aa1 TSD |
3696 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3697 | .owner = THIS_MODULE, | |
3698 | .read = amdgpu_debugfs_wave_read, | |
3699 | .llseek = default_llseek | |
3700 | }; | |
c5a60ce8 TSD |
3701 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3702 | .owner = THIS_MODULE, | |
3703 | .read = amdgpu_debugfs_gpr_read, | |
3704 | .llseek = default_llseek | |
3705 | }; | |
273d7aa1 | 3706 | |
adcec288 TSD |
3707 | static const struct file_operations *debugfs_regs[] = { |
3708 | &amdgpu_debugfs_regs_fops, | |
3709 | &amdgpu_debugfs_regs_didt_fops, | |
3710 | &amdgpu_debugfs_regs_pcie_fops, | |
3711 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3712 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3713 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3714 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3715 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3716 | }; |
3717 | ||
3718 | static const char *debugfs_regs_names[] = { | |
3719 | "amdgpu_regs", | |
3720 | "amdgpu_regs_didt", | |
3721 | "amdgpu_regs_pcie", | |
3722 | "amdgpu_regs_smc", | |
1e051413 | 3723 | "amdgpu_gca_config", |
f2cdaf20 | 3724 | "amdgpu_sensors", |
273d7aa1 | 3725 | "amdgpu_wave", |
c5a60ce8 | 3726 | "amdgpu_gpr", |
adcec288 | 3727 | }; |
d38ceaf9 AD |
3728 | |
3729 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3730 | { | |
3731 | struct drm_minor *minor = adev->ddev->primary; | |
3732 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3733 | unsigned i, j; |
3734 | ||
3735 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3736 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3737 | S_IFREG | S_IRUGO, root, | |
3738 | adev, debugfs_regs[i]); | |
3739 | if (IS_ERR(ent)) { | |
3740 | for (j = 0; j < i; j++) { | |
3741 | debugfs_remove(adev->debugfs_regs[i]); | |
3742 | adev->debugfs_regs[i] = NULL; | |
3743 | } | |
3744 | return PTR_ERR(ent); | |
3745 | } | |
d38ceaf9 | 3746 | |
adcec288 TSD |
3747 | if (!i) |
3748 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3749 | adev->debugfs_regs[i] = ent; | |
3750 | } | |
d38ceaf9 AD |
3751 | |
3752 | return 0; | |
3753 | } | |
3754 | ||
3755 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3756 | { | |
adcec288 TSD |
3757 | unsigned i; |
3758 | ||
3759 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3760 | if (adev->debugfs_regs[i]) { | |
3761 | debugfs_remove(adev->debugfs_regs[i]); | |
3762 | adev->debugfs_regs[i] = NULL; | |
3763 | } | |
3764 | } | |
d38ceaf9 AD |
3765 | } |
3766 | ||
4f0955fc HR |
3767 | static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) |
3768 | { | |
3769 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3770 | struct drm_device *dev = node->minor->dev; | |
3771 | struct amdgpu_device *adev = dev->dev_private; | |
3772 | int r = 0, i; | |
3773 | ||
3774 | /* hold on the scheduler */ | |
3775 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3776 | struct amdgpu_ring *ring = adev->rings[i]; | |
3777 | ||
3778 | if (!ring || !ring->sched.thread) | |
3779 | continue; | |
3780 | kthread_park(ring->sched.thread); | |
3781 | } | |
3782 | ||
3783 | seq_printf(m, "run ib test:\n"); | |
3784 | r = amdgpu_ib_ring_tests(adev); | |
3785 | if (r) | |
3786 | seq_printf(m, "ib ring tests failed (%d).\n", r); | |
3787 | else | |
3788 | seq_printf(m, "ib ring tests passed.\n"); | |
3789 | ||
3790 | /* go on the scheduler */ | |
3791 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3792 | struct amdgpu_ring *ring = adev->rings[i]; | |
3793 | ||
3794 | if (!ring || !ring->sched.thread) | |
3795 | continue; | |
3796 | kthread_unpark(ring->sched.thread); | |
3797 | } | |
3798 | ||
3799 | return 0; | |
3800 | } | |
3801 | ||
3802 | static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { | |
3803 | {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} | |
3804 | }; | |
3805 | ||
3806 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) | |
3807 | { | |
3808 | return amdgpu_debugfs_add_files(adev, | |
3809 | amdgpu_debugfs_test_ib_ring_list, 1); | |
3810 | } | |
3811 | ||
d38ceaf9 AD |
3812 | int amdgpu_debugfs_init(struct drm_minor *minor) |
3813 | { | |
3814 | return 0; | |
3815 | } | |
7cebc728 | 3816 | #else |
27bad5b9 | 3817 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) |
4f0955fc HR |
3818 | { |
3819 | return 0; | |
3820 | } | |
7cebc728 AK |
3821 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) |
3822 | { | |
3823 | return 0; | |
3824 | } | |
3825 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3826 | #endif |