Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
fdf2f6c5 | 33 | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 35 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
36 | #include <drm/amdgpu_drm.h> |
37 | #include <linux/vgaarb.h> | |
38 | #include <linux/vga_switcheroo.h> | |
39 | #include <linux/efi.h> | |
40 | #include "amdgpu.h" | |
f4b373f4 | 41 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
42 | #include "amdgpu_i2c.h" |
43 | #include "atom.h" | |
44 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 45 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 46 | #include "amd_pcie.h" |
33f34802 KW |
47 | #ifdef CONFIG_DRM_AMDGPU_SI |
48 | #include "si.h" | |
49 | #endif | |
a2e73f56 AD |
50 | #ifdef CONFIG_DRM_AMDGPU_CIK |
51 | #include "cik.h" | |
52 | #endif | |
aaa36a97 | 53 | #include "vi.h" |
460826e6 | 54 | #include "soc15.h" |
0a5b8c7b | 55 | #include "nv.h" |
d38ceaf9 | 56 | #include "bif/bif_4_1_d.h" |
9accf2fd | 57 | #include <linux/pci.h> |
bec86378 | 58 | #include <linux/firmware.h> |
89041940 | 59 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 60 | |
ba997709 | 61 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 62 | #include "amdgpu_pm.h" |
d38ceaf9 | 63 | |
5183411b | 64 | #include "amdgpu_xgmi.h" |
c030f2e4 | 65 | #include "amdgpu_ras.h" |
9c7c85f7 | 66 | #include "amdgpu_pmu.h" |
bd607166 | 67 | #include "amdgpu_fru_eeprom.h" |
04442bf7 | 68 | #include "amdgpu_reset.h" |
5183411b | 69 | |
d5ea093e | 70 | #include <linux/suspend.h> |
c6a6e2db | 71 | #include <drm/task_barrier.h> |
3f12acc8 | 72 | #include <linux/pm_runtime.h> |
d5ea093e | 73 | |
f89f8c6b AG |
74 | #include <drm/drm_drv.h> |
75 | ||
e2a75f88 | 76 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 77 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 78 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 79 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 80 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 81 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 82 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 83 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 84 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 85 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
4e52a9f8 | 86 | MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin"); |
8bf84f60 | 87 | MODULE_FIRMWARE("amdgpu/yellow_carp_gpu_info.bin"); |
e2a75f88 | 88 | |
2dc80b00 S |
89 | #define AMDGPU_RESUME_MS 2000 |
90 | ||
050091ab | 91 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
92 | "TAHITI", |
93 | "PITCAIRN", | |
94 | "VERDE", | |
95 | "OLAND", | |
96 | "HAINAN", | |
d38ceaf9 AD |
97 | "BONAIRE", |
98 | "KAVERI", | |
99 | "KABINI", | |
100 | "HAWAII", | |
101 | "MULLINS", | |
102 | "TOPAZ", | |
103 | "TONGA", | |
48299f95 | 104 | "FIJI", |
d38ceaf9 | 105 | "CARRIZO", |
139f4917 | 106 | "STONEY", |
2cc0c0b5 FC |
107 | "POLARIS10", |
108 | "POLARIS11", | |
c4642a47 | 109 | "POLARIS12", |
48ff108d | 110 | "VEGAM", |
d4196f01 | 111 | "VEGA10", |
8fab806a | 112 | "VEGA12", |
956fcddc | 113 | "VEGA20", |
2ca8a5d2 | 114 | "RAVEN", |
d6c3b24e | 115 | "ARCTURUS", |
1eee4228 | 116 | "RENOIR", |
d46b417a | 117 | "ALDEBARAN", |
852a6626 | 118 | "NAVI10", |
d0f56dc2 | 119 | "CYAN_SKILLFISH", |
87dbad02 | 120 | "NAVI14", |
9802f5d7 | 121 | "NAVI12", |
ccaf72d3 | 122 | "SIENNA_CICHLID", |
ddd8fbe7 | 123 | "NAVY_FLOUNDER", |
4f1e9a76 | 124 | "VANGOGH", |
a2468e04 | 125 | "DIMGREY_CAVEFISH", |
6f169591 | 126 | "BEIGE_GOBY", |
ee9236b7 | 127 | "YELLOW_CARP", |
d38ceaf9 AD |
128 | "LAST", |
129 | }; | |
130 | ||
dcea6e65 KR |
131 | /** |
132 | * DOC: pcie_replay_count | |
133 | * | |
134 | * The amdgpu driver provides a sysfs API for reporting the total number | |
135 | * of PCIe replays (NAKs) | |
136 | * The file pcie_replay_count is used for this and returns the total | |
137 | * number of replays as a sum of the NAKs generated and NAKs received | |
138 | */ | |
139 | ||
140 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
141 | struct device_attribute *attr, char *buf) | |
142 | { | |
143 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 144 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
145 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
146 | ||
36000c7a | 147 | return sysfs_emit(buf, "%llu\n", cnt); |
dcea6e65 KR |
148 | } |
149 | ||
150 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
151 | amdgpu_device_get_pcie_replay_count, NULL); | |
152 | ||
5494d864 AD |
153 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
154 | ||
bd607166 KR |
155 | /** |
156 | * DOC: product_name | |
157 | * | |
158 | * The amdgpu driver provides a sysfs API for reporting the product name | |
159 | * for the device | |
160 | * The file serial_number is used for this and returns the product name | |
161 | * as returned from the FRU. | |
162 | * NOTE: This is only available for certain server cards | |
163 | */ | |
164 | ||
165 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
166 | struct device_attribute *attr, char *buf) | |
167 | { | |
168 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 169 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 170 | |
36000c7a | 171 | return sysfs_emit(buf, "%s\n", adev->product_name); |
bd607166 KR |
172 | } |
173 | ||
174 | static DEVICE_ATTR(product_name, S_IRUGO, | |
175 | amdgpu_device_get_product_name, NULL); | |
176 | ||
177 | /** | |
178 | * DOC: product_number | |
179 | * | |
180 | * The amdgpu driver provides a sysfs API for reporting the part number | |
181 | * for the device | |
182 | * The file serial_number is used for this and returns the part number | |
183 | * as returned from the FRU. | |
184 | * NOTE: This is only available for certain server cards | |
185 | */ | |
186 | ||
187 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
188 | struct device_attribute *attr, char *buf) | |
189 | { | |
190 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 191 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 192 | |
36000c7a | 193 | return sysfs_emit(buf, "%s\n", adev->product_number); |
bd607166 KR |
194 | } |
195 | ||
196 | static DEVICE_ATTR(product_number, S_IRUGO, | |
197 | amdgpu_device_get_product_number, NULL); | |
198 | ||
199 | /** | |
200 | * DOC: serial_number | |
201 | * | |
202 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
203 | * for the device | |
204 | * The file serial_number is used for this and returns the serial number | |
205 | * as returned from the FRU. | |
206 | * NOTE: This is only available for certain server cards | |
207 | */ | |
208 | ||
209 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
210 | struct device_attribute *attr, char *buf) | |
211 | { | |
212 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 213 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 214 | |
36000c7a | 215 | return sysfs_emit(buf, "%s\n", adev->serial); |
bd607166 KR |
216 | } |
217 | ||
218 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
219 | amdgpu_device_get_serial_number, NULL); | |
220 | ||
fd496ca8 | 221 | /** |
b98c6299 | 222 | * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control |
fd496ca8 AD |
223 | * |
224 | * @dev: drm_device pointer | |
225 | * | |
b98c6299 | 226 | * Returns true if the device is a dGPU with ATPX power control, |
fd496ca8 AD |
227 | * otherwise return false. |
228 | */ | |
b98c6299 | 229 | bool amdgpu_device_supports_px(struct drm_device *dev) |
fd496ca8 AD |
230 | { |
231 | struct amdgpu_device *adev = drm_to_adev(dev); | |
232 | ||
b98c6299 | 233 | if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid()) |
fd496ca8 AD |
234 | return true; |
235 | return false; | |
236 | } | |
237 | ||
e3ecdffa | 238 | /** |
0330b848 | 239 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
240 | * |
241 | * @dev: drm_device pointer | |
242 | * | |
b98c6299 | 243 | * Returns true if the device is a dGPU with ACPI power control, |
e3ecdffa AD |
244 | * otherwise return false. |
245 | */ | |
31af062a | 246 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 247 | { |
1348969a | 248 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 249 | |
b98c6299 AD |
250 | if (adev->has_pr3 || |
251 | ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid())) | |
d38ceaf9 AD |
252 | return true; |
253 | return false; | |
254 | } | |
255 | ||
a69cba42 AD |
256 | /** |
257 | * amdgpu_device_supports_baco - Does the device support BACO | |
258 | * | |
259 | * @dev: drm_device pointer | |
260 | * | |
261 | * Returns true if the device supporte BACO, | |
262 | * otherwise return false. | |
263 | */ | |
264 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
265 | { | |
1348969a | 266 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
267 | |
268 | return amdgpu_asic_supports_baco(adev); | |
269 | } | |
270 | ||
3fa8f89d S |
271 | /** |
272 | * amdgpu_device_supports_smart_shift - Is the device dGPU with | |
273 | * smart shift support | |
274 | * | |
275 | * @dev: drm_device pointer | |
276 | * | |
277 | * Returns true if the device is a dGPU with Smart Shift support, | |
278 | * otherwise returns false. | |
279 | */ | |
280 | bool amdgpu_device_supports_smart_shift(struct drm_device *dev) | |
281 | { | |
282 | return (amdgpu_device_supports_boco(dev) && | |
283 | amdgpu_acpi_is_power_shift_control_supported()); | |
284 | } | |
285 | ||
6e3cd2a9 MCC |
286 | /* |
287 | * VRAM access helper functions | |
288 | */ | |
289 | ||
e35e2b11 | 290 | /** |
048af66b | 291 | * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA |
e35e2b11 TY |
292 | * |
293 | * @adev: amdgpu_device pointer | |
294 | * @pos: offset of the buffer in vram | |
295 | * @buf: virtual address of the buffer in system memory | |
296 | * @size: read/write size, sizeof(@buf) must > @size | |
297 | * @write: true - write to vram, otherwise - read from vram | |
298 | */ | |
048af66b KW |
299 | void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, |
300 | void *buf, size_t size, bool write) | |
e35e2b11 | 301 | { |
e35e2b11 | 302 | unsigned long flags; |
048af66b KW |
303 | uint32_t hi = ~0, tmp = 0; |
304 | uint32_t *data = buf; | |
ce05ac56 | 305 | uint64_t last; |
f89f8c6b | 306 | int idx; |
ce05ac56 | 307 | |
f89f8c6b AG |
308 | if (!drm_dev_enter(&adev->ddev, &idx)) |
309 | return; | |
9d11eb0d | 310 | |
048af66b KW |
311 | BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4)); |
312 | ||
313 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
314 | for (last = pos + size; pos < last; pos += 4) { | |
315 | tmp = pos >> 31; | |
316 | ||
317 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); | |
318 | if (tmp != hi) { | |
319 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
320 | hi = tmp; | |
321 | } | |
322 | if (write) | |
323 | WREG32_NO_KIQ(mmMM_DATA, *data++); | |
324 | else | |
325 | *data++ = RREG32_NO_KIQ(mmMM_DATA); | |
326 | } | |
327 | ||
328 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
329 | drm_dev_exit(idx); | |
330 | } | |
331 | ||
332 | /** | |
333 | * amdgpu_device_vram_access - access vram by vram aperature | |
334 | * | |
335 | * @adev: amdgpu_device pointer | |
336 | * @pos: offset of the buffer in vram | |
337 | * @buf: virtual address of the buffer in system memory | |
338 | * @size: read/write size, sizeof(@buf) must > @size | |
339 | * @write: true - write to vram, otherwise - read from vram | |
340 | * | |
341 | * The return value means how many bytes have been transferred. | |
342 | */ | |
343 | size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, | |
344 | void *buf, size_t size, bool write) | |
345 | { | |
9d11eb0d | 346 | #ifdef CONFIG_64BIT |
048af66b KW |
347 | void __iomem *addr; |
348 | size_t count = 0; | |
349 | uint64_t last; | |
350 | ||
351 | if (!adev->mman.aper_base_kaddr) | |
352 | return 0; | |
353 | ||
9d11eb0d CK |
354 | last = min(pos + size, adev->gmc.visible_vram_size); |
355 | if (last > pos) { | |
048af66b KW |
356 | addr = adev->mman.aper_base_kaddr + pos; |
357 | count = last - pos; | |
9d11eb0d CK |
358 | |
359 | if (write) { | |
360 | memcpy_toio(addr, buf, count); | |
361 | mb(); | |
810085dd | 362 | amdgpu_device_flush_hdp(adev, NULL); |
9d11eb0d | 363 | } else { |
810085dd | 364 | amdgpu_device_invalidate_hdp(adev, NULL); |
9d11eb0d CK |
365 | mb(); |
366 | memcpy_fromio(buf, addr, count); | |
367 | } | |
368 | ||
9d11eb0d | 369 | } |
048af66b KW |
370 | |
371 | return count; | |
372 | #else | |
373 | return 0; | |
9d11eb0d | 374 | #endif |
048af66b | 375 | } |
9d11eb0d | 376 | |
048af66b KW |
377 | /** |
378 | * amdgpu_device_vram_access - read/write a buffer in vram | |
379 | * | |
380 | * @adev: amdgpu_device pointer | |
381 | * @pos: offset of the buffer in vram | |
382 | * @buf: virtual address of the buffer in system memory | |
383 | * @size: read/write size, sizeof(@buf) must > @size | |
384 | * @write: true - write to vram, otherwise - read from vram | |
385 | */ | |
386 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
387 | void *buf, size_t size, bool write) | |
388 | { | |
389 | size_t count; | |
e35e2b11 | 390 | |
048af66b KW |
391 | /* try to using vram apreature to access vram first */ |
392 | count = amdgpu_device_aper_access(adev, pos, buf, size, write); | |
393 | size -= count; | |
394 | if (size) { | |
395 | /* using MM to access rest vram */ | |
396 | pos += count; | |
397 | buf += count; | |
398 | amdgpu_device_mm_access(adev, pos, buf, size, write); | |
e35e2b11 TY |
399 | } |
400 | } | |
401 | ||
d38ceaf9 | 402 | /* |
f7ee1874 | 403 | * register access helper functions. |
d38ceaf9 | 404 | */ |
56b53c0b DL |
405 | |
406 | /* Check if hw access should be skipped because of hotplug or device error */ | |
407 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
408 | { | |
7afefb81 | 409 | if (adev->no_hw_access) |
56b53c0b DL |
410 | return true; |
411 | ||
412 | #ifdef CONFIG_LOCKDEP | |
413 | /* | |
414 | * This is a bit complicated to understand, so worth a comment. What we assert | |
415 | * here is that the GPU reset is not running on another thread in parallel. | |
416 | * | |
417 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
418 | * we know that the reset is not running in paralell. | |
419 | * | |
420 | * If the trylock fails we assert that we are either already holding the read | |
421 | * side of the lock or are the reset thread itself and hold the write side of | |
422 | * the lock. | |
423 | */ | |
424 | if (in_task()) { | |
425 | if (down_read_trylock(&adev->reset_sem)) | |
426 | up_read(&adev->reset_sem); | |
427 | else | |
428 | lockdep_assert_held(&adev->reset_sem); | |
429 | } | |
430 | #endif | |
431 | return false; | |
432 | } | |
433 | ||
e3ecdffa | 434 | /** |
f7ee1874 | 435 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
436 | * |
437 | * @adev: amdgpu_device pointer | |
438 | * @reg: dword aligned register offset | |
439 | * @acc_flags: access flags which require special behavior | |
440 | * | |
441 | * Returns the 32 bit value from the offset specified. | |
442 | */ | |
f7ee1874 HZ |
443 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
444 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 445 | { |
f4b373f4 TSD |
446 | uint32_t ret; |
447 | ||
56b53c0b | 448 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
449 | return 0; |
450 | ||
f7ee1874 HZ |
451 | if ((reg * 4) < adev->rmmio_size) { |
452 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
453 | amdgpu_sriov_runtime(adev) && | |
454 | down_read_trylock(&adev->reset_sem)) { | |
455 | ret = amdgpu_kiq_rreg(adev, reg); | |
456 | up_read(&adev->reset_sem); | |
457 | } else { | |
458 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
459 | } | |
460 | } else { | |
461 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 462 | } |
bc992ba5 | 463 | |
f7ee1874 | 464 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 465 | |
f4b373f4 | 466 | return ret; |
d38ceaf9 AD |
467 | } |
468 | ||
421a2a30 ML |
469 | /* |
470 | * MMIO register read with bytes helper functions | |
471 | * @offset:bytes offset from MMIO start | |
472 | * | |
473 | */ | |
474 | ||
e3ecdffa AD |
475 | /** |
476 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
477 | * | |
478 | * @adev: amdgpu_device pointer | |
479 | * @offset: byte aligned register offset | |
480 | * | |
481 | * Returns the 8 bit value from the offset specified. | |
482 | */ | |
7cbbc745 AG |
483 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
484 | { | |
56b53c0b | 485 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
486 | return 0; |
487 | ||
421a2a30 ML |
488 | if (offset < adev->rmmio_size) |
489 | return (readb(adev->rmmio + offset)); | |
490 | BUG(); | |
491 | } | |
492 | ||
493 | /* | |
494 | * MMIO register write with bytes helper functions | |
495 | * @offset:bytes offset from MMIO start | |
496 | * @value: the value want to be written to the register | |
497 | * | |
498 | */ | |
e3ecdffa AD |
499 | /** |
500 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
501 | * | |
502 | * @adev: amdgpu_device pointer | |
503 | * @offset: byte aligned register offset | |
504 | * @value: 8 bit value to write | |
505 | * | |
506 | * Writes the value specified to the offset specified. | |
507 | */ | |
7cbbc745 AG |
508 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
509 | { | |
56b53c0b | 510 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
511 | return; |
512 | ||
421a2a30 ML |
513 | if (offset < adev->rmmio_size) |
514 | writeb(value, adev->rmmio + offset); | |
515 | else | |
516 | BUG(); | |
517 | } | |
518 | ||
e3ecdffa | 519 | /** |
f7ee1874 | 520 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
521 | * |
522 | * @adev: amdgpu_device pointer | |
523 | * @reg: dword aligned register offset | |
524 | * @v: 32 bit value to write to the register | |
525 | * @acc_flags: access flags which require special behavior | |
526 | * | |
527 | * Writes the value specified to the offset specified. | |
528 | */ | |
f7ee1874 HZ |
529 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
530 | uint32_t reg, uint32_t v, | |
531 | uint32_t acc_flags) | |
d38ceaf9 | 532 | { |
56b53c0b | 533 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
534 | return; |
535 | ||
f7ee1874 HZ |
536 | if ((reg * 4) < adev->rmmio_size) { |
537 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
538 | amdgpu_sriov_runtime(adev) && | |
539 | down_read_trylock(&adev->reset_sem)) { | |
540 | amdgpu_kiq_wreg(adev, reg, v); | |
541 | up_read(&adev->reset_sem); | |
542 | } else { | |
543 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
544 | } | |
545 | } else { | |
546 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 547 | } |
bc992ba5 | 548 | |
f7ee1874 | 549 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 550 | } |
d38ceaf9 | 551 | |
2e0cc4d4 ML |
552 | /* |
553 | * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range | |
554 | * | |
555 | * this function is invoked only the debugfs register access | |
556 | * */ | |
f7ee1874 HZ |
557 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
558 | uint32_t reg, uint32_t v) | |
2e0cc4d4 | 559 | { |
56b53c0b | 560 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
561 | return; |
562 | ||
2e0cc4d4 | 563 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
564 | adev->gfx.rlc.funcs && |
565 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 | 566 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
1a4772d9 | 567 | return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 0); |
f7ee1874 HZ |
568 | } else { |
569 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 570 | } |
d38ceaf9 AD |
571 | } |
572 | ||
d38ceaf9 AD |
573 | /** |
574 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
575 | * | |
576 | * @adev: amdgpu_device pointer | |
577 | * @index: doorbell index | |
578 | * | |
579 | * Returns the value in the doorbell aperture at the | |
580 | * requested doorbell index (CIK). | |
581 | */ | |
582 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
583 | { | |
56b53c0b | 584 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
585 | return 0; |
586 | ||
d38ceaf9 AD |
587 | if (index < adev->doorbell.num_doorbells) { |
588 | return readl(adev->doorbell.ptr + index); | |
589 | } else { | |
590 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
591 | return 0; | |
592 | } | |
593 | } | |
594 | ||
595 | /** | |
596 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
597 | * | |
598 | * @adev: amdgpu_device pointer | |
599 | * @index: doorbell index | |
600 | * @v: value to write | |
601 | * | |
602 | * Writes @v to the doorbell aperture at the | |
603 | * requested doorbell index (CIK). | |
604 | */ | |
605 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
606 | { | |
56b53c0b | 607 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
608 | return; |
609 | ||
d38ceaf9 AD |
610 | if (index < adev->doorbell.num_doorbells) { |
611 | writel(v, adev->doorbell.ptr + index); | |
612 | } else { | |
613 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
614 | } | |
615 | } | |
616 | ||
832be404 KW |
617 | /** |
618 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
619 | * | |
620 | * @adev: amdgpu_device pointer | |
621 | * @index: doorbell index | |
622 | * | |
623 | * Returns the value in the doorbell aperture at the | |
624 | * requested doorbell index (VEGA10+). | |
625 | */ | |
626 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
627 | { | |
56b53c0b | 628 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
629 | return 0; |
630 | ||
832be404 KW |
631 | if (index < adev->doorbell.num_doorbells) { |
632 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
633 | } else { | |
634 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
635 | return 0; | |
636 | } | |
637 | } | |
638 | ||
639 | /** | |
640 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
641 | * | |
642 | * @adev: amdgpu_device pointer | |
643 | * @index: doorbell index | |
644 | * @v: value to write | |
645 | * | |
646 | * Writes @v to the doorbell aperture at the | |
647 | * requested doorbell index (VEGA10+). | |
648 | */ | |
649 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
650 | { | |
56b53c0b | 651 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
652 | return; |
653 | ||
832be404 KW |
654 | if (index < adev->doorbell.num_doorbells) { |
655 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
656 | } else { | |
657 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
658 | } | |
659 | } | |
660 | ||
1bba3683 HZ |
661 | /** |
662 | * amdgpu_device_indirect_rreg - read an indirect register | |
663 | * | |
664 | * @adev: amdgpu_device pointer | |
665 | * @pcie_index: mmio register offset | |
666 | * @pcie_data: mmio register offset | |
22f453fb | 667 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
668 | * |
669 | * Returns the value of indirect register @reg_addr | |
670 | */ | |
671 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
672 | u32 pcie_index, u32 pcie_data, | |
673 | u32 reg_addr) | |
674 | { | |
675 | unsigned long flags; | |
676 | u32 r; | |
677 | void __iomem *pcie_index_offset; | |
678 | void __iomem *pcie_data_offset; | |
679 | ||
680 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
681 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
682 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
683 | ||
684 | writel(reg_addr, pcie_index_offset); | |
685 | readl(pcie_index_offset); | |
686 | r = readl(pcie_data_offset); | |
687 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
688 | ||
689 | return r; | |
690 | } | |
691 | ||
692 | /** | |
693 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
694 | * | |
695 | * @adev: amdgpu_device pointer | |
696 | * @pcie_index: mmio register offset | |
697 | * @pcie_data: mmio register offset | |
22f453fb | 698 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
699 | * |
700 | * Returns the value of indirect register @reg_addr | |
701 | */ | |
702 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
703 | u32 pcie_index, u32 pcie_data, | |
704 | u32 reg_addr) | |
705 | { | |
706 | unsigned long flags; | |
707 | u64 r; | |
708 | void __iomem *pcie_index_offset; | |
709 | void __iomem *pcie_data_offset; | |
710 | ||
711 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
712 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
713 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
714 | ||
715 | /* read low 32 bits */ | |
716 | writel(reg_addr, pcie_index_offset); | |
717 | readl(pcie_index_offset); | |
718 | r = readl(pcie_data_offset); | |
719 | /* read high 32 bits */ | |
720 | writel(reg_addr + 4, pcie_index_offset); | |
721 | readl(pcie_index_offset); | |
722 | r |= ((u64)readl(pcie_data_offset) << 32); | |
723 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
724 | ||
725 | return r; | |
726 | } | |
727 | ||
728 | /** | |
729 | * amdgpu_device_indirect_wreg - write an indirect register address | |
730 | * | |
731 | * @adev: amdgpu_device pointer | |
732 | * @pcie_index: mmio register offset | |
733 | * @pcie_data: mmio register offset | |
734 | * @reg_addr: indirect register offset | |
735 | * @reg_data: indirect register data | |
736 | * | |
737 | */ | |
738 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
739 | u32 pcie_index, u32 pcie_data, | |
740 | u32 reg_addr, u32 reg_data) | |
741 | { | |
742 | unsigned long flags; | |
743 | void __iomem *pcie_index_offset; | |
744 | void __iomem *pcie_data_offset; | |
745 | ||
746 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
747 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
748 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
749 | ||
750 | writel(reg_addr, pcie_index_offset); | |
751 | readl(pcie_index_offset); | |
752 | writel(reg_data, pcie_data_offset); | |
753 | readl(pcie_data_offset); | |
754 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
755 | } | |
756 | ||
757 | /** | |
758 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
759 | * | |
760 | * @adev: amdgpu_device pointer | |
761 | * @pcie_index: mmio register offset | |
762 | * @pcie_data: mmio register offset | |
763 | * @reg_addr: indirect register offset | |
764 | * @reg_data: indirect register data | |
765 | * | |
766 | */ | |
767 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
768 | u32 pcie_index, u32 pcie_data, | |
769 | u32 reg_addr, u64 reg_data) | |
770 | { | |
771 | unsigned long flags; | |
772 | void __iomem *pcie_index_offset; | |
773 | void __iomem *pcie_data_offset; | |
774 | ||
775 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
776 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
777 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
778 | ||
779 | /* write low 32 bits */ | |
780 | writel(reg_addr, pcie_index_offset); | |
781 | readl(pcie_index_offset); | |
782 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
783 | readl(pcie_data_offset); | |
784 | /* write high 32 bits */ | |
785 | writel(reg_addr + 4, pcie_index_offset); | |
786 | readl(pcie_index_offset); | |
787 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
788 | readl(pcie_data_offset); | |
789 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
790 | } | |
791 | ||
d38ceaf9 AD |
792 | /** |
793 | * amdgpu_invalid_rreg - dummy reg read function | |
794 | * | |
982a820b | 795 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
796 | * @reg: offset of register |
797 | * | |
798 | * Dummy register read function. Used for register blocks | |
799 | * that certain asics don't have (all asics). | |
800 | * Returns the value in the register. | |
801 | */ | |
802 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
803 | { | |
804 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
805 | BUG(); | |
806 | return 0; | |
807 | } | |
808 | ||
809 | /** | |
810 | * amdgpu_invalid_wreg - dummy reg write function | |
811 | * | |
982a820b | 812 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
813 | * @reg: offset of register |
814 | * @v: value to write to the register | |
815 | * | |
816 | * Dummy register read function. Used for register blocks | |
817 | * that certain asics don't have (all asics). | |
818 | */ | |
819 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
820 | { | |
821 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
822 | reg, v); | |
823 | BUG(); | |
824 | } | |
825 | ||
4fa1c6a6 TZ |
826 | /** |
827 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
828 | * | |
982a820b | 829 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
830 | * @reg: offset of register |
831 | * | |
832 | * Dummy register read function. Used for register blocks | |
833 | * that certain asics don't have (all asics). | |
834 | * Returns the value in the register. | |
835 | */ | |
836 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
837 | { | |
838 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
839 | BUG(); | |
840 | return 0; | |
841 | } | |
842 | ||
843 | /** | |
844 | * amdgpu_invalid_wreg64 - dummy reg write function | |
845 | * | |
982a820b | 846 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
847 | * @reg: offset of register |
848 | * @v: value to write to the register | |
849 | * | |
850 | * Dummy register read function. Used for register blocks | |
851 | * that certain asics don't have (all asics). | |
852 | */ | |
853 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
854 | { | |
855 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
856 | reg, v); | |
857 | BUG(); | |
858 | } | |
859 | ||
d38ceaf9 AD |
860 | /** |
861 | * amdgpu_block_invalid_rreg - dummy reg read function | |
862 | * | |
982a820b | 863 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
864 | * @block: offset of instance |
865 | * @reg: offset of register | |
866 | * | |
867 | * Dummy register read function. Used for register blocks | |
868 | * that certain asics don't have (all asics). | |
869 | * Returns the value in the register. | |
870 | */ | |
871 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
872 | uint32_t block, uint32_t reg) | |
873 | { | |
874 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
875 | reg, block); | |
876 | BUG(); | |
877 | return 0; | |
878 | } | |
879 | ||
880 | /** | |
881 | * amdgpu_block_invalid_wreg - dummy reg write function | |
882 | * | |
982a820b | 883 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
884 | * @block: offset of instance |
885 | * @reg: offset of register | |
886 | * @v: value to write to the register | |
887 | * | |
888 | * Dummy register read function. Used for register blocks | |
889 | * that certain asics don't have (all asics). | |
890 | */ | |
891 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
892 | uint32_t block, | |
893 | uint32_t reg, uint32_t v) | |
894 | { | |
895 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
896 | reg, block, v); | |
897 | BUG(); | |
898 | } | |
899 | ||
4d2997ab AD |
900 | /** |
901 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
902 | * | |
982a820b | 903 | * @adev: amdgpu_device pointer |
4d2997ab AD |
904 | * |
905 | * Does any asic specific work and then calls atom asic init. | |
906 | */ | |
907 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
908 | { | |
909 | amdgpu_asic_pre_asic_init(adev); | |
910 | ||
911 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
912 | } | |
913 | ||
e3ecdffa AD |
914 | /** |
915 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
916 | * | |
982a820b | 917 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
918 | * |
919 | * Allocates a scratch page of VRAM for use by various things in the | |
920 | * driver. | |
921 | */ | |
06ec9070 | 922 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 923 | { |
a4a02777 CK |
924 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
925 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
926 | &adev->vram_scratch.robj, | |
927 | &adev->vram_scratch.gpu_addr, | |
928 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
929 | } |
930 | ||
e3ecdffa AD |
931 | /** |
932 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
933 | * | |
982a820b | 934 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
935 | * |
936 | * Frees the VRAM scratch page. | |
937 | */ | |
06ec9070 | 938 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 939 | { |
078af1a3 | 940 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
941 | } |
942 | ||
943 | /** | |
9c3f2b54 | 944 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
945 | * |
946 | * @adev: amdgpu_device pointer | |
947 | * @registers: pointer to the register array | |
948 | * @array_size: size of the register array | |
949 | * | |
950 | * Programs an array or registers with and and or masks. | |
951 | * This is a helper for setting golden registers. | |
952 | */ | |
9c3f2b54 AD |
953 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
954 | const u32 *registers, | |
955 | const u32 array_size) | |
d38ceaf9 AD |
956 | { |
957 | u32 tmp, reg, and_mask, or_mask; | |
958 | int i; | |
959 | ||
960 | if (array_size % 3) | |
961 | return; | |
962 | ||
963 | for (i = 0; i < array_size; i +=3) { | |
964 | reg = registers[i + 0]; | |
965 | and_mask = registers[i + 1]; | |
966 | or_mask = registers[i + 2]; | |
967 | ||
968 | if (and_mask == 0xffffffff) { | |
969 | tmp = or_mask; | |
970 | } else { | |
971 | tmp = RREG32(reg); | |
972 | tmp &= ~and_mask; | |
e0d07657 HZ |
973 | if (adev->family >= AMDGPU_FAMILY_AI) |
974 | tmp |= (or_mask & and_mask); | |
975 | else | |
976 | tmp |= or_mask; | |
d38ceaf9 AD |
977 | } |
978 | WREG32(reg, tmp); | |
979 | } | |
980 | } | |
981 | ||
e3ecdffa AD |
982 | /** |
983 | * amdgpu_device_pci_config_reset - reset the GPU | |
984 | * | |
985 | * @adev: amdgpu_device pointer | |
986 | * | |
987 | * Resets the GPU using the pci config reset sequence. | |
988 | * Only applicable to asics prior to vega10. | |
989 | */ | |
8111c387 | 990 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
991 | { |
992 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
993 | } | |
994 | ||
af484df8 AD |
995 | /** |
996 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
997 | * | |
998 | * @adev: amdgpu_device pointer | |
999 | * | |
1000 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
1001 | */ | |
1002 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
1003 | { | |
1004 | return pci_reset_function(adev->pdev); | |
1005 | } | |
1006 | ||
d38ceaf9 AD |
1007 | /* |
1008 | * GPU doorbell aperture helpers function. | |
1009 | */ | |
1010 | /** | |
06ec9070 | 1011 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
1012 | * |
1013 | * @adev: amdgpu_device pointer | |
1014 | * | |
1015 | * Init doorbell driver information (CIK) | |
1016 | * Returns 0 on success, error on failure. | |
1017 | */ | |
06ec9070 | 1018 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 1019 | { |
6585661d | 1020 | |
705e519e CK |
1021 | /* No doorbell on SI hardware generation */ |
1022 | if (adev->asic_type < CHIP_BONAIRE) { | |
1023 | adev->doorbell.base = 0; | |
1024 | adev->doorbell.size = 0; | |
1025 | adev->doorbell.num_doorbells = 0; | |
1026 | adev->doorbell.ptr = NULL; | |
1027 | return 0; | |
1028 | } | |
1029 | ||
d6895ad3 CK |
1030 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
1031 | return -EINVAL; | |
1032 | ||
22357775 AD |
1033 | amdgpu_asic_init_doorbell_index(adev); |
1034 | ||
d38ceaf9 AD |
1035 | /* doorbell bar mapping */ |
1036 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
1037 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
1038 | ||
edf600da | 1039 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 1040 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
1041 | if (adev->doorbell.num_doorbells == 0) |
1042 | return -EINVAL; | |
1043 | ||
ec3db8a6 | 1044 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
1045 | * paging queue doorbell use the second page. The |
1046 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
1047 | * doorbells are in the first page. So with paging queue enabled, | |
1048 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
1049 | */ |
1050 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 1051 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 1052 | |
8972e5d2 CK |
1053 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
1054 | adev->doorbell.num_doorbells * | |
1055 | sizeof(u32)); | |
1056 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 1057 | return -ENOMEM; |
d38ceaf9 AD |
1058 | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | /** | |
06ec9070 | 1063 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
1064 | * |
1065 | * @adev: amdgpu_device pointer | |
1066 | * | |
1067 | * Tear down doorbell driver information (CIK) | |
1068 | */ | |
06ec9070 | 1069 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1070 | { |
1071 | iounmap(adev->doorbell.ptr); | |
1072 | adev->doorbell.ptr = NULL; | |
1073 | } | |
1074 | ||
22cb0164 | 1075 | |
d38ceaf9 AD |
1076 | |
1077 | /* | |
06ec9070 | 1078 | * amdgpu_device_wb_*() |
455a7bc2 | 1079 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1080 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1081 | */ |
1082 | ||
1083 | /** | |
06ec9070 | 1084 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1085 | * |
1086 | * @adev: amdgpu_device pointer | |
1087 | * | |
1088 | * Disables Writeback and frees the Writeback memory (all asics). | |
1089 | * Used at driver shutdown. | |
1090 | */ | |
06ec9070 | 1091 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1092 | { |
1093 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1094 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1095 | &adev->wb.gpu_addr, | |
1096 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1097 | adev->wb.wb_obj = NULL; |
1098 | } | |
1099 | } | |
1100 | ||
1101 | /** | |
06ec9070 | 1102 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1103 | * |
1104 | * @adev: amdgpu_device pointer | |
1105 | * | |
455a7bc2 | 1106 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1107 | * Used at driver startup. |
1108 | * Returns 0 on success or an -error on failure. | |
1109 | */ | |
06ec9070 | 1110 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1111 | { |
1112 | int r; | |
1113 | ||
1114 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1115 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1116 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1117 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1118 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1119 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1120 | if (r) { |
1121 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1122 | return r; | |
1123 | } | |
d38ceaf9 AD |
1124 | |
1125 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1126 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1127 | ||
1128 | /* clear wb memory */ | |
73469585 | 1129 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1130 | } |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | /** | |
131b4b36 | 1136 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1137 | * |
1138 | * @adev: amdgpu_device pointer | |
1139 | * @wb: wb index | |
1140 | * | |
1141 | * Allocate a wb slot for use by the driver (all asics). | |
1142 | * Returns 0 on success or -EINVAL on failure. | |
1143 | */ | |
131b4b36 | 1144 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1145 | { |
1146 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1147 | |
97407b63 | 1148 | if (offset < adev->wb.num_wb) { |
7014285a | 1149 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1150 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1151 | return 0; |
1152 | } else { | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | } | |
1156 | ||
d38ceaf9 | 1157 | /** |
131b4b36 | 1158 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1159 | * |
1160 | * @adev: amdgpu_device pointer | |
1161 | * @wb: wb index | |
1162 | * | |
1163 | * Free a wb slot allocated for use by the driver (all asics) | |
1164 | */ | |
131b4b36 | 1165 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1166 | { |
73469585 | 1167 | wb >>= 3; |
d38ceaf9 | 1168 | if (wb < adev->wb.num_wb) |
73469585 | 1169 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1170 | } |
1171 | ||
d6895ad3 CK |
1172 | /** |
1173 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1174 | * | |
1175 | * @adev: amdgpu_device pointer | |
1176 | * | |
1177 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1178 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1179 | * driver loading by returning -ENODEV. | |
1180 | */ | |
1181 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1182 | { | |
453f617a | 1183 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1184 | struct pci_bus *root; |
1185 | struct resource *res; | |
1186 | unsigned i; | |
d6895ad3 CK |
1187 | u16 cmd; |
1188 | int r; | |
1189 | ||
0c03b912 | 1190 | /* Bypass for VF */ |
1191 | if (amdgpu_sriov_vf(adev)) | |
1192 | return 0; | |
1193 | ||
b7221f2b AD |
1194 | /* skip if the bios has already enabled large BAR */ |
1195 | if (adev->gmc.real_vram_size && | |
1196 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1197 | return 0; | |
1198 | ||
31b8adab CK |
1199 | /* Check if the root BUS has 64bit memory resources */ |
1200 | root = adev->pdev->bus; | |
1201 | while (root->parent) | |
1202 | root = root->parent; | |
1203 | ||
1204 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1205 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1206 | res->start > 0x100000000ull) |
1207 | break; | |
1208 | } | |
1209 | ||
1210 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1211 | if (!res) | |
1212 | return 0; | |
1213 | ||
453f617a ND |
1214 | /* Limit the BAR size to what is available */ |
1215 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1216 | rbar_size); | |
1217 | ||
d6895ad3 CK |
1218 | /* Disable memory decoding while we change the BAR addresses and size */ |
1219 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1220 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1221 | cmd & ~PCI_COMMAND_MEMORY); | |
1222 | ||
1223 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 1224 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
1225 | if (adev->asic_type >= CHIP_BONAIRE) |
1226 | pci_release_resource(adev->pdev, 2); | |
1227 | ||
1228 | pci_release_resource(adev->pdev, 0); | |
1229 | ||
1230 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1231 | if (r == -ENOSPC) | |
1232 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1233 | else if (r && r != -ENOTSUPP) | |
1234 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1235 | ||
1236 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1237 | ||
1238 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1239 | * using the device. | |
1240 | */ | |
06ec9070 | 1241 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
1242 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1243 | return -ENODEV; | |
1244 | ||
1245 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
a05502e5 | 1249 | |
d38ceaf9 AD |
1250 | /* |
1251 | * GPU helpers function. | |
1252 | */ | |
1253 | /** | |
39c640c0 | 1254 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1255 | * |
1256 | * @adev: amdgpu_device pointer | |
1257 | * | |
c836fec5 JQ |
1258 | * Check if the asic has been initialized (all asics) at driver startup |
1259 | * or post is needed if hw reset is performed. | |
1260 | * Returns true if need or false if not. | |
d38ceaf9 | 1261 | */ |
39c640c0 | 1262 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1263 | { |
1264 | uint32_t reg; | |
1265 | ||
bec86378 ML |
1266 | if (amdgpu_sriov_vf(adev)) |
1267 | return false; | |
1268 | ||
1269 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1270 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1271 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1272 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1273 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1274 | */ |
1275 | if (adev->asic_type == CHIP_FIJI) { | |
1276 | int err; | |
1277 | uint32_t fw_ver; | |
1278 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1279 | /* force vPost if error occured */ | |
1280 | if (err) | |
1281 | return true; | |
1282 | ||
1283 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1284 | if (fw_ver < 0x00160e00) |
1285 | return true; | |
bec86378 | 1286 | } |
bec86378 | 1287 | } |
91fe77eb | 1288 | |
e3c1b071 | 1289 | /* Don't post if we need to reset whole hive on init */ |
1290 | if (adev->gmc.xgmi.pending_reset) | |
1291 | return false; | |
1292 | ||
91fe77eb | 1293 | if (adev->has_hw_reset) { |
1294 | adev->has_hw_reset = false; | |
1295 | return true; | |
1296 | } | |
1297 | ||
1298 | /* bios scratch used on CIK+ */ | |
1299 | if (adev->asic_type >= CHIP_BONAIRE) | |
1300 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1301 | ||
1302 | /* check MEM_SIZE for older asics */ | |
1303 | reg = amdgpu_asic_get_config_memsize(adev); | |
1304 | ||
1305 | if ((reg != 0) && (reg != 0xffffffff)) | |
1306 | return false; | |
1307 | ||
1308 | return true; | |
bec86378 ML |
1309 | } |
1310 | ||
d38ceaf9 AD |
1311 | /* if we get transitioned to only one device, take VGA back */ |
1312 | /** | |
06ec9070 | 1313 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 | 1314 | * |
bf44e8ce | 1315 | * @pdev: PCI device pointer |
d38ceaf9 AD |
1316 | * @state: enable/disable vga decode |
1317 | * | |
1318 | * Enable/disable vga decode (all asics). | |
1319 | * Returns VGA resource flags. | |
1320 | */ | |
bf44e8ce CH |
1321 | static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, |
1322 | bool state) | |
d38ceaf9 | 1323 | { |
bf44e8ce | 1324 | struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); |
d38ceaf9 AD |
1325 | amdgpu_asic_set_vga_state(adev, state); |
1326 | if (state) | |
1327 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1328 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1329 | else | |
1330 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1331 | } | |
1332 | ||
e3ecdffa AD |
1333 | /** |
1334 | * amdgpu_device_check_block_size - validate the vm block size | |
1335 | * | |
1336 | * @adev: amdgpu_device pointer | |
1337 | * | |
1338 | * Validates the vm block size specified via module parameter. | |
1339 | * The vm block size defines number of bits in page table versus page directory, | |
1340 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1341 | * page table and the remaining bits are in the page directory. | |
1342 | */ | |
06ec9070 | 1343 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1344 | { |
1345 | /* defines number of bits in page table versus page directory, | |
1346 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1347 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1348 | if (amdgpu_vm_block_size == -1) |
1349 | return; | |
a1adf8be | 1350 | |
bab4fee7 | 1351 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1352 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1353 | amdgpu_vm_block_size); | |
97489129 | 1354 | amdgpu_vm_block_size = -1; |
a1adf8be | 1355 | } |
a1adf8be CZ |
1356 | } |
1357 | ||
e3ecdffa AD |
1358 | /** |
1359 | * amdgpu_device_check_vm_size - validate the vm size | |
1360 | * | |
1361 | * @adev: amdgpu_device pointer | |
1362 | * | |
1363 | * Validates the vm size in GB specified via module parameter. | |
1364 | * The VM size is the size of the GPU virtual memory space in GB. | |
1365 | */ | |
06ec9070 | 1366 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1367 | { |
64dab074 AD |
1368 | /* no need to check the default value */ |
1369 | if (amdgpu_vm_size == -1) | |
1370 | return; | |
1371 | ||
83ca145d ZJ |
1372 | if (amdgpu_vm_size < 1) { |
1373 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1374 | amdgpu_vm_size); | |
f3368128 | 1375 | amdgpu_vm_size = -1; |
83ca145d | 1376 | } |
83ca145d ZJ |
1377 | } |
1378 | ||
7951e376 RZ |
1379 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1380 | { | |
1381 | struct sysinfo si; | |
a9d4fe2f | 1382 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1383 | uint64_t total_memory; |
1384 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1385 | uint64_t dram_size_three_GB = 0xB8000000; | |
1386 | ||
1387 | if (amdgpu_smu_memory_pool_size == 0) | |
1388 | return; | |
1389 | ||
1390 | if (!is_os_64) { | |
1391 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1392 | goto def_value; | |
1393 | } | |
1394 | si_meminfo(&si); | |
1395 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1396 | ||
1397 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1398 | (amdgpu_smu_memory_pool_size == 2)) { | |
1399 | if (total_memory < dram_size_three_GB) | |
1400 | goto def_value1; | |
1401 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1402 | (amdgpu_smu_memory_pool_size == 8)) { | |
1403 | if (total_memory < dram_size_seven_GB) | |
1404 | goto def_value1; | |
1405 | } else { | |
1406 | DRM_WARN("Smu memory pool size not supported\n"); | |
1407 | goto def_value; | |
1408 | } | |
1409 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1410 | ||
1411 | return; | |
1412 | ||
1413 | def_value1: | |
1414 | DRM_WARN("No enough system memory\n"); | |
1415 | def_value: | |
1416 | adev->pm.smu_prv_buffer_size = 0; | |
1417 | } | |
1418 | ||
9f6a7857 HR |
1419 | static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) |
1420 | { | |
1421 | if (!(adev->flags & AMD_IS_APU) || | |
1422 | adev->asic_type < CHIP_RAVEN) | |
1423 | return 0; | |
1424 | ||
1425 | switch (adev->asic_type) { | |
1426 | case CHIP_RAVEN: | |
1427 | if (adev->pdev->device == 0x15dd) | |
1428 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1429 | if (adev->pdev->device == 0x15d8) | |
1430 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
1431 | break; | |
1432 | case CHIP_RENOIR: | |
1433 | if ((adev->pdev->device == 0x1636) || | |
1434 | (adev->pdev->device == 0x164c)) | |
1435 | adev->apu_flags |= AMD_APU_IS_RENOIR; | |
1436 | else | |
1437 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1438 | break; | |
1439 | case CHIP_VANGOGH: | |
1440 | adev->apu_flags |= AMD_APU_IS_VANGOGH; | |
1441 | break; | |
1442 | case CHIP_YELLOW_CARP: | |
1443 | break; | |
d0f56dc2 TZ |
1444 | case CHIP_CYAN_SKILLFISH: |
1445 | if (adev->pdev->device == 0x13FE) | |
1446 | adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2; | |
1447 | break; | |
9f6a7857 HR |
1448 | default: |
1449 | return -EINVAL; | |
1450 | } | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
d38ceaf9 | 1455 | /** |
06ec9070 | 1456 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1457 | * |
1458 | * @adev: amdgpu_device pointer | |
1459 | * | |
1460 | * Validates certain module parameters and updates | |
1461 | * the associated values used by the driver (all asics). | |
1462 | */ | |
912dfc84 | 1463 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1464 | { |
5b011235 CZ |
1465 | if (amdgpu_sched_jobs < 4) { |
1466 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1467 | amdgpu_sched_jobs); | |
1468 | amdgpu_sched_jobs = 4; | |
76117507 | 1469 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1470 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1471 | amdgpu_sched_jobs); | |
1472 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1473 | } | |
d38ceaf9 | 1474 | |
83e74db6 | 1475 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1476 | /* gart size must be greater or equal to 32M */ |
1477 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1478 | amdgpu_gart_size); | |
83e74db6 | 1479 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1480 | } |
1481 | ||
36d38372 | 1482 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1483 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1484 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1485 | amdgpu_gtt_size); | |
1486 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1487 | } |
1488 | ||
d07f14be RH |
1489 | /* valid range is between 4 and 9 inclusive */ |
1490 | if (amdgpu_vm_fragment_size != -1 && | |
1491 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1492 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1493 | amdgpu_vm_fragment_size = -1; | |
1494 | } | |
1495 | ||
5d5bd5e3 KW |
1496 | if (amdgpu_sched_hw_submission < 2) { |
1497 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1498 | amdgpu_sched_hw_submission); | |
1499 | amdgpu_sched_hw_submission = 2; | |
1500 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1501 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1502 | amdgpu_sched_hw_submission); | |
1503 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1504 | } | |
1505 | ||
7951e376 RZ |
1506 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1507 | ||
06ec9070 | 1508 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1509 | |
06ec9070 | 1510 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1511 | |
19aede77 | 1512 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1513 | |
c6252390 | 1514 | amdgpu_gmc_tmz_set(adev); |
01a8dcec | 1515 | |
9b498efa AD |
1516 | amdgpu_gmc_noretry_set(adev); |
1517 | ||
e3c00faa | 1518 | return 0; |
d38ceaf9 AD |
1519 | } |
1520 | ||
1521 | /** | |
1522 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1523 | * | |
1524 | * @pdev: pci dev pointer | |
1694467b | 1525 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1526 | * |
1527 | * Callback for the switcheroo driver. Suspends or resumes the | |
1528 | * the asics before or after it is powered up using ACPI methods. | |
1529 | */ | |
8aba21b7 LT |
1530 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1531 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1532 | { |
1533 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1534 | int r; |
d38ceaf9 | 1535 | |
b98c6299 | 1536 | if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1537 | return; |
1538 | ||
1539 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1540 | pr_info("switched on\n"); |
d38ceaf9 AD |
1541 | /* don't suspend or resume card normally */ |
1542 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1543 | ||
8f66090b TZ |
1544 | pci_set_power_state(pdev, PCI_D0); |
1545 | amdgpu_device_load_pci_state(pdev); | |
1546 | r = pci_enable_device(pdev); | |
de185019 AD |
1547 | if (r) |
1548 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1549 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1550 | |
d38ceaf9 | 1551 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1552 | } else { |
dd4fa6c1 | 1553 | pr_info("switched off\n"); |
d38ceaf9 | 1554 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
de185019 | 1555 | amdgpu_device_suspend(dev, true); |
8f66090b | 1556 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1557 | /* Shut down the device */ |
8f66090b TZ |
1558 | pci_disable_device(pdev); |
1559 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1560 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1561 | } | |
1562 | } | |
1563 | ||
1564 | /** | |
1565 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1566 | * | |
1567 | * @pdev: pci dev pointer | |
1568 | * | |
1569 | * Callback for the switcheroo driver. Check of the switcheroo | |
1570 | * state can be changed. | |
1571 | * Returns true if the state can be changed, false if not. | |
1572 | */ | |
1573 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1574 | { | |
1575 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1576 | ||
1577 | /* | |
1578 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1579 | * locking inversion with the driver load path. And the access here is | |
1580 | * completely racy anyway. So don't bother with locking for now. | |
1581 | */ | |
7e13ad89 | 1582 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1583 | } |
1584 | ||
1585 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1586 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1587 | .reprobe = NULL, | |
1588 | .can_switch = amdgpu_switcheroo_can_switch, | |
1589 | }; | |
1590 | ||
e3ecdffa AD |
1591 | /** |
1592 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1593 | * | |
87e3f136 | 1594 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1595 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1596 | * @state: clockgating state (gate or ungate) | |
1597 | * | |
1598 | * Sets the requested clockgating state for all instances of | |
1599 | * the hardware IP specified. | |
1600 | * Returns the error code from the last instance. | |
1601 | */ | |
43fa561f | 1602 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1603 | enum amd_ip_block_type block_type, |
1604 | enum amd_clockgating_state state) | |
d38ceaf9 | 1605 | { |
43fa561f | 1606 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1607 | int i, r = 0; |
1608 | ||
1609 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1610 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1611 | continue; |
c722865a RZ |
1612 | if (adev->ip_blocks[i].version->type != block_type) |
1613 | continue; | |
1614 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1615 | continue; | |
1616 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1617 | (void *)adev, state); | |
1618 | if (r) | |
1619 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1620 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1621 | } |
1622 | return r; | |
1623 | } | |
1624 | ||
e3ecdffa AD |
1625 | /** |
1626 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1627 | * | |
87e3f136 | 1628 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1629 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1630 | * @state: powergating state (gate or ungate) | |
1631 | * | |
1632 | * Sets the requested powergating state for all instances of | |
1633 | * the hardware IP specified. | |
1634 | * Returns the error code from the last instance. | |
1635 | */ | |
43fa561f | 1636 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1637 | enum amd_ip_block_type block_type, |
1638 | enum amd_powergating_state state) | |
d38ceaf9 | 1639 | { |
43fa561f | 1640 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1641 | int i, r = 0; |
1642 | ||
1643 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1644 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1645 | continue; |
c722865a RZ |
1646 | if (adev->ip_blocks[i].version->type != block_type) |
1647 | continue; | |
1648 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1649 | continue; | |
1650 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1651 | (void *)adev, state); | |
1652 | if (r) | |
1653 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1654 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1655 | } |
1656 | return r; | |
1657 | } | |
1658 | ||
e3ecdffa AD |
1659 | /** |
1660 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1661 | * | |
1662 | * @adev: amdgpu_device pointer | |
1663 | * @flags: clockgating feature flags | |
1664 | * | |
1665 | * Walks the list of IPs on the device and updates the clockgating | |
1666 | * flags for each IP. | |
1667 | * Updates @flags with the feature flags for each hardware IP where | |
1668 | * clockgating is enabled. | |
1669 | */ | |
2990a1fc AD |
1670 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1671 | u32 *flags) | |
6cb2d4e4 HR |
1672 | { |
1673 | int i; | |
1674 | ||
1675 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1676 | if (!adev->ip_blocks[i].status.valid) | |
1677 | continue; | |
1678 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1679 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1680 | } | |
1681 | } | |
1682 | ||
e3ecdffa AD |
1683 | /** |
1684 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1685 | * | |
1686 | * @adev: amdgpu_device pointer | |
1687 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1688 | * | |
1689 | * Waits for the request hardware IP to be idle. | |
1690 | * Returns 0 for success or a negative error code on failure. | |
1691 | */ | |
2990a1fc AD |
1692 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1693 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1694 | { |
1695 | int i, r; | |
1696 | ||
1697 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1698 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1699 | continue; |
a1255107 AD |
1700 | if (adev->ip_blocks[i].version->type == block_type) { |
1701 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1702 | if (r) |
1703 | return r; | |
1704 | break; | |
1705 | } | |
1706 | } | |
1707 | return 0; | |
1708 | ||
1709 | } | |
1710 | ||
e3ecdffa AD |
1711 | /** |
1712 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1713 | * | |
1714 | * @adev: amdgpu_device pointer | |
1715 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1716 | * | |
1717 | * Check if the hardware IP is idle or not. | |
1718 | * Returns true if it the IP is idle, false if not. | |
1719 | */ | |
2990a1fc AD |
1720 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1721 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1722 | { |
1723 | int i; | |
1724 | ||
1725 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1726 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1727 | continue; |
a1255107 AD |
1728 | if (adev->ip_blocks[i].version->type == block_type) |
1729 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1730 | } |
1731 | return true; | |
1732 | ||
1733 | } | |
1734 | ||
e3ecdffa AD |
1735 | /** |
1736 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1737 | * | |
1738 | * @adev: amdgpu_device pointer | |
87e3f136 | 1739 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1740 | * |
1741 | * Returns a pointer to the hardware IP block structure | |
1742 | * if it exists for the asic, otherwise NULL. | |
1743 | */ | |
2990a1fc AD |
1744 | struct amdgpu_ip_block * |
1745 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1746 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1747 | { |
1748 | int i; | |
1749 | ||
1750 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1751 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1752 | return &adev->ip_blocks[i]; |
1753 | ||
1754 | return NULL; | |
1755 | } | |
1756 | ||
1757 | /** | |
2990a1fc | 1758 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1759 | * |
1760 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1761 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1762 | * @major: major version |
1763 | * @minor: minor version | |
1764 | * | |
1765 | * return 0 if equal or greater | |
1766 | * return 1 if smaller or the ip_block doesn't exist | |
1767 | */ | |
2990a1fc AD |
1768 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1769 | enum amd_ip_block_type type, | |
1770 | u32 major, u32 minor) | |
d38ceaf9 | 1771 | { |
2990a1fc | 1772 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1773 | |
a1255107 AD |
1774 | if (ip_block && ((ip_block->version->major > major) || |
1775 | ((ip_block->version->major == major) && | |
1776 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1777 | return 0; |
1778 | ||
1779 | return 1; | |
1780 | } | |
1781 | ||
a1255107 | 1782 | /** |
2990a1fc | 1783 | * amdgpu_device_ip_block_add |
a1255107 AD |
1784 | * |
1785 | * @adev: amdgpu_device pointer | |
1786 | * @ip_block_version: pointer to the IP to add | |
1787 | * | |
1788 | * Adds the IP block driver information to the collection of IPs | |
1789 | * on the asic. | |
1790 | */ | |
2990a1fc AD |
1791 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1792 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1793 | { |
1794 | if (!ip_block_version) | |
1795 | return -EINVAL; | |
1796 | ||
7bd939d0 LG |
1797 | switch (ip_block_version->type) { |
1798 | case AMD_IP_BLOCK_TYPE_VCN: | |
1799 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) | |
1800 | return 0; | |
1801 | break; | |
1802 | case AMD_IP_BLOCK_TYPE_JPEG: | |
1803 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) | |
1804 | return 0; | |
1805 | break; | |
1806 | default: | |
1807 | break; | |
1808 | } | |
1809 | ||
e966a725 | 1810 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1811 | ip_block_version->funcs->name); |
1812 | ||
a1255107 AD |
1813 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1814 | ||
1815 | return 0; | |
1816 | } | |
1817 | ||
e3ecdffa AD |
1818 | /** |
1819 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1820 | * | |
1821 | * @adev: amdgpu_device pointer | |
1822 | * | |
1823 | * Enabled the virtual display feature if the user has enabled it via | |
1824 | * the module parameter virtual_display. This feature provides a virtual | |
1825 | * display hardware on headless boards or in virtualized environments. | |
1826 | * This function parses and validates the configuration string specified by | |
1827 | * the user and configues the virtual display configuration (number of | |
1828 | * virtual connectors, crtcs, etc.) specified. | |
1829 | */ | |
483ef985 | 1830 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1831 | { |
1832 | adev->enable_virtual_display = false; | |
1833 | ||
1834 | if (amdgpu_virtual_display) { | |
8f66090b | 1835 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 1836 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1837 | |
1838 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1839 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1840 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1841 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1842 | if (!strcmp("all", pciaddname) |
1843 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1844 | long num_crtc; |
1845 | int res = -1; | |
1846 | ||
9accf2fd | 1847 | adev->enable_virtual_display = true; |
0f66356d ED |
1848 | |
1849 | if (pciaddname_tmp) | |
1850 | res = kstrtol(pciaddname_tmp, 10, | |
1851 | &num_crtc); | |
1852 | ||
1853 | if (!res) { | |
1854 | if (num_crtc < 1) | |
1855 | num_crtc = 1; | |
1856 | if (num_crtc > 6) | |
1857 | num_crtc = 6; | |
1858 | adev->mode_info.num_crtc = num_crtc; | |
1859 | } else { | |
1860 | adev->mode_info.num_crtc = 1; | |
1861 | } | |
9accf2fd ED |
1862 | break; |
1863 | } | |
1864 | } | |
1865 | ||
0f66356d ED |
1866 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1867 | amdgpu_virtual_display, pci_address_name, | |
1868 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1869 | |
1870 | kfree(pciaddstr); | |
1871 | } | |
1872 | } | |
1873 | ||
e3ecdffa AD |
1874 | /** |
1875 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1876 | * | |
1877 | * @adev: amdgpu_device pointer | |
1878 | * | |
1879 | * Parses the asic configuration parameters specified in the gpu info | |
1880 | * firmware and makes them availale to the driver for use in configuring | |
1881 | * the asic. | |
1882 | * Returns 0 on success, -EINVAL on failure. | |
1883 | */ | |
e2a75f88 AD |
1884 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1885 | { | |
e2a75f88 | 1886 | const char *chip_name; |
c0a43457 | 1887 | char fw_name[40]; |
e2a75f88 AD |
1888 | int err; |
1889 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1890 | ||
ab4fe3e1 HR |
1891 | adev->firmware.gpu_info_fw = NULL; |
1892 | ||
72de33f8 | 1893 | if (adev->mman.discovery_bin) { |
258620d0 | 1894 | amdgpu_discovery_get_gfx_info(adev); |
cc375d8c TY |
1895 | |
1896 | /* | |
1897 | * FIXME: The bounding box is still needed by Navi12, so | |
1898 | * temporarily read it from gpu_info firmware. Should be droped | |
1899 | * when DAL no longer needs it. | |
1900 | */ | |
1901 | if (adev->asic_type != CHIP_NAVI12) | |
1902 | return 0; | |
258620d0 AD |
1903 | } |
1904 | ||
e2a75f88 | 1905 | switch (adev->asic_type) { |
e2a75f88 AD |
1906 | #ifdef CONFIG_DRM_AMDGPU_SI |
1907 | case CHIP_VERDE: | |
1908 | case CHIP_TAHITI: | |
1909 | case CHIP_PITCAIRN: | |
1910 | case CHIP_OLAND: | |
1911 | case CHIP_HAINAN: | |
1912 | #endif | |
1913 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1914 | case CHIP_BONAIRE: | |
1915 | case CHIP_HAWAII: | |
1916 | case CHIP_KAVERI: | |
1917 | case CHIP_KABINI: | |
1918 | case CHIP_MULLINS: | |
1919 | #endif | |
da87c30b AD |
1920 | case CHIP_TOPAZ: |
1921 | case CHIP_TONGA: | |
1922 | case CHIP_FIJI: | |
1923 | case CHIP_POLARIS10: | |
1924 | case CHIP_POLARIS11: | |
1925 | case CHIP_POLARIS12: | |
1926 | case CHIP_VEGAM: | |
1927 | case CHIP_CARRIZO: | |
1928 | case CHIP_STONEY: | |
27c0bc71 | 1929 | case CHIP_VEGA20: |
44b3253a | 1930 | case CHIP_ALDEBARAN: |
84d244a3 JC |
1931 | case CHIP_SIENNA_CICHLID: |
1932 | case CHIP_NAVY_FLOUNDER: | |
eac88a5f | 1933 | case CHIP_DIMGREY_CAVEFISH: |
0e5f4b09 | 1934 | case CHIP_BEIGE_GOBY: |
e2a75f88 AD |
1935 | default: |
1936 | return 0; | |
1937 | case CHIP_VEGA10: | |
1938 | chip_name = "vega10"; | |
1939 | break; | |
3f76dced AD |
1940 | case CHIP_VEGA12: |
1941 | chip_name = "vega12"; | |
1942 | break; | |
2d2e5e7e | 1943 | case CHIP_RAVEN: |
54f78a76 | 1944 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1945 | chip_name = "raven2"; |
54f78a76 | 1946 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1947 | chip_name = "picasso"; |
54c4d17e FX |
1948 | else |
1949 | chip_name = "raven"; | |
2d2e5e7e | 1950 | break; |
65e60f6e LM |
1951 | case CHIP_ARCTURUS: |
1952 | chip_name = "arcturus"; | |
1953 | break; | |
b51a26a0 | 1954 | case CHIP_RENOIR: |
2e62f0b5 PL |
1955 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
1956 | chip_name = "renoir"; | |
1957 | else | |
1958 | chip_name = "green_sardine"; | |
b51a26a0 | 1959 | break; |
23c6268e HR |
1960 | case CHIP_NAVI10: |
1961 | chip_name = "navi10"; | |
1962 | break; | |
ed42cfe1 XY |
1963 | case CHIP_NAVI14: |
1964 | chip_name = "navi14"; | |
1965 | break; | |
42b325e5 XY |
1966 | case CHIP_NAVI12: |
1967 | chip_name = "navi12"; | |
1968 | break; | |
4e52a9f8 HR |
1969 | case CHIP_VANGOGH: |
1970 | chip_name = "vangogh"; | |
1971 | break; | |
8bf84f60 AL |
1972 | case CHIP_YELLOW_CARP: |
1973 | chip_name = "yellow_carp"; | |
1974 | break; | |
e2a75f88 AD |
1975 | } |
1976 | ||
1977 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1978 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1979 | if (err) { |
1980 | dev_err(adev->dev, | |
1981 | "Failed to load gpu_info firmware \"%s\"\n", | |
1982 | fw_name); | |
1983 | goto out; | |
1984 | } | |
ab4fe3e1 | 1985 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1986 | if (err) { |
1987 | dev_err(adev->dev, | |
1988 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1989 | fw_name); | |
1990 | goto out; | |
1991 | } | |
1992 | ||
ab4fe3e1 | 1993 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1994 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1995 | ||
1996 | switch (hdr->version_major) { | |
1997 | case 1: | |
1998 | { | |
1999 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 2000 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
2001 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
2002 | ||
cc375d8c TY |
2003 | /* |
2004 | * Should be droped when DAL no longer needs it. | |
2005 | */ | |
2006 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
2007 | goto parse_soc_bounding_box; |
2008 | ||
b5ab16bf AD |
2009 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
2010 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
2011 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
2012 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 2013 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
2014 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
2015 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
2016 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
2017 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
2018 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 2019 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
2020 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
2021 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
2022 | adev->gfx.cu_info.max_waves_per_simd = |
2023 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
2024 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
2025 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
2026 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 2027 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
2028 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
2029 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
2030 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2031 | adev->gfx.config.num_sc_per_sh = | |
2032 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
2033 | adev->gfx.config.num_packer_per_sc = | |
2034 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
2035 | } | |
ec51d3fa XY |
2036 | |
2037 | parse_soc_bounding_box: | |
ec51d3fa XY |
2038 | /* |
2039 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 2040 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 2041 | */ |
48321c3d HW |
2042 | if (hdr->version_minor == 2) { |
2043 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
2044 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
2045 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2046 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
2047 | } | |
e2a75f88 AD |
2048 | break; |
2049 | } | |
2050 | default: | |
2051 | dev_err(adev->dev, | |
2052 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
2053 | err = -EINVAL; | |
2054 | goto out; | |
2055 | } | |
2056 | out: | |
e2a75f88 AD |
2057 | return err; |
2058 | } | |
2059 | ||
e3ecdffa AD |
2060 | /** |
2061 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
2062 | * | |
2063 | * @adev: amdgpu_device pointer | |
2064 | * | |
2065 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
2066 | * up each asic are discovered each IP's early_init callback is run. This | |
2067 | * is the first stage in initializing the asic. | |
2068 | * Returns 0 on success, negative error code on failure. | |
2069 | */ | |
06ec9070 | 2070 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 2071 | { |
aaa36a97 | 2072 | int i, r; |
d38ceaf9 | 2073 | |
483ef985 | 2074 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 2075 | |
00a979f3 | 2076 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 2077 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
2078 | if (r) |
2079 | return r; | |
00a979f3 WS |
2080 | } |
2081 | ||
d38ceaf9 | 2082 | switch (adev->asic_type) { |
33f34802 KW |
2083 | #ifdef CONFIG_DRM_AMDGPU_SI |
2084 | case CHIP_VERDE: | |
2085 | case CHIP_TAHITI: | |
2086 | case CHIP_PITCAIRN: | |
2087 | case CHIP_OLAND: | |
2088 | case CHIP_HAINAN: | |
295d0daf | 2089 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
2090 | r = si_set_ip_blocks(adev); |
2091 | if (r) | |
2092 | return r; | |
2093 | break; | |
2094 | #endif | |
a2e73f56 AD |
2095 | #ifdef CONFIG_DRM_AMDGPU_CIK |
2096 | case CHIP_BONAIRE: | |
2097 | case CHIP_HAWAII: | |
2098 | case CHIP_KAVERI: | |
2099 | case CHIP_KABINI: | |
2100 | case CHIP_MULLINS: | |
e1ad2d53 | 2101 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 2102 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
2103 | else |
2104 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
2105 | |
2106 | r = cik_set_ip_blocks(adev); | |
2107 | if (r) | |
2108 | return r; | |
2109 | break; | |
2110 | #endif | |
da87c30b AD |
2111 | case CHIP_TOPAZ: |
2112 | case CHIP_TONGA: | |
2113 | case CHIP_FIJI: | |
2114 | case CHIP_POLARIS10: | |
2115 | case CHIP_POLARIS11: | |
2116 | case CHIP_POLARIS12: | |
2117 | case CHIP_VEGAM: | |
2118 | case CHIP_CARRIZO: | |
2119 | case CHIP_STONEY: | |
2120 | if (adev->flags & AMD_IS_APU) | |
2121 | adev->family = AMDGPU_FAMILY_CZ; | |
2122 | else | |
2123 | adev->family = AMDGPU_FAMILY_VI; | |
2124 | ||
2125 | r = vi_set_ip_blocks(adev); | |
2126 | if (r) | |
2127 | return r; | |
2128 | break; | |
e48a3cd9 AD |
2129 | case CHIP_VEGA10: |
2130 | case CHIP_VEGA12: | |
e4bd8170 | 2131 | case CHIP_VEGA20: |
e48a3cd9 | 2132 | case CHIP_RAVEN: |
61cf44c1 | 2133 | case CHIP_ARCTURUS: |
b51a26a0 | 2134 | case CHIP_RENOIR: |
c00a18ec | 2135 | case CHIP_ALDEBARAN: |
70534d1e | 2136 | if (adev->flags & AMD_IS_APU) |
2ca8a5d2 CZ |
2137 | adev->family = AMDGPU_FAMILY_RV; |
2138 | else | |
2139 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
2140 | |
2141 | r = soc15_set_ip_blocks(adev); | |
2142 | if (r) | |
2143 | return r; | |
2144 | break; | |
0a5b8c7b | 2145 | case CHIP_NAVI10: |
7ecb5cd4 | 2146 | case CHIP_NAVI14: |
4808cf9c | 2147 | case CHIP_NAVI12: |
11e8aef5 | 2148 | case CHIP_SIENNA_CICHLID: |
41f446bf | 2149 | case CHIP_NAVY_FLOUNDER: |
144722fa | 2150 | case CHIP_DIMGREY_CAVEFISH: |
b41f5b7a | 2151 | case CHIP_BEIGE_GOBY: |
4e52a9f8 | 2152 | case CHIP_VANGOGH: |
8bf84f60 | 2153 | case CHIP_YELLOW_CARP: |
6e80eacd | 2154 | case CHIP_CYAN_SKILLFISH: |
4e52a9f8 HR |
2155 | if (adev->asic_type == CHIP_VANGOGH) |
2156 | adev->family = AMDGPU_FAMILY_VGH; | |
8bf84f60 AL |
2157 | else if (adev->asic_type == CHIP_YELLOW_CARP) |
2158 | adev->family = AMDGPU_FAMILY_YC; | |
4e52a9f8 HR |
2159 | else |
2160 | adev->family = AMDGPU_FAMILY_NV; | |
0a5b8c7b HR |
2161 | |
2162 | r = nv_set_ip_blocks(adev); | |
2163 | if (r) | |
2164 | return r; | |
2165 | break; | |
d38ceaf9 AD |
2166 | default: |
2167 | /* FIXME: not supported yet */ | |
2168 | return -EINVAL; | |
2169 | } | |
2170 | ||
1884734a | 2171 | amdgpu_amdkfd_device_probe(adev); |
2172 | ||
3b94fb10 | 2173 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2174 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2175 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2176 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2177 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
00f54b97 | 2178 | |
d38ceaf9 AD |
2179 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2180 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
2181 | DRM_ERROR("disabled ip block: %d <%s>\n", |
2182 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 2183 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2184 | } else { |
a1255107 AD |
2185 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2186 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2187 | if (r == -ENOENT) { |
a1255107 | 2188 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2189 | } else if (r) { |
a1255107 AD |
2190 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2191 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2192 | return r; |
2c1a2784 | 2193 | } else { |
a1255107 | 2194 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2195 | } |
974e6b64 | 2196 | } else { |
a1255107 | 2197 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2198 | } |
d38ceaf9 | 2199 | } |
21a249ca AD |
2200 | /* get the vbios after the asic_funcs are set up */ |
2201 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2202 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2203 | if (r) | |
2204 | return r; | |
2205 | ||
21a249ca AD |
2206 | /* Read BIOS */ |
2207 | if (!amdgpu_get_bios(adev)) | |
2208 | return -EINVAL; | |
2209 | ||
2210 | r = amdgpu_atombios_init(adev); | |
2211 | if (r) { | |
2212 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2213 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2214 | return r; | |
2215 | } | |
77eabc6f PJZ |
2216 | |
2217 | /*get pf2vf msg info at it's earliest time*/ | |
2218 | if (amdgpu_sriov_vf(adev)) | |
2219 | amdgpu_virt_init_data_exchange(adev); | |
2220 | ||
21a249ca | 2221 | } |
d38ceaf9 AD |
2222 | } |
2223 | ||
395d1fb9 NH |
2224 | adev->cg_flags &= amdgpu_cg_mask; |
2225 | adev->pg_flags &= amdgpu_pg_mask; | |
2226 | ||
d38ceaf9 AD |
2227 | return 0; |
2228 | } | |
2229 | ||
0a4f2520 RZ |
2230 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2231 | { | |
2232 | int i, r; | |
2233 | ||
2234 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2235 | if (!adev->ip_blocks[i].status.sw) | |
2236 | continue; | |
2237 | if (adev->ip_blocks[i].status.hw) | |
2238 | continue; | |
2239 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2240 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2241 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2242 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2243 | if (r) { | |
2244 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2245 | adev->ip_blocks[i].version->funcs->name, r); | |
2246 | return r; | |
2247 | } | |
2248 | adev->ip_blocks[i].status.hw = true; | |
2249 | } | |
2250 | } | |
2251 | ||
2252 | return 0; | |
2253 | } | |
2254 | ||
2255 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2256 | { | |
2257 | int i, r; | |
2258 | ||
2259 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2260 | if (!adev->ip_blocks[i].status.sw) | |
2261 | continue; | |
2262 | if (adev->ip_blocks[i].status.hw) | |
2263 | continue; | |
2264 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2265 | if (r) { | |
2266 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2267 | adev->ip_blocks[i].version->funcs->name, r); | |
2268 | return r; | |
2269 | } | |
2270 | adev->ip_blocks[i].status.hw = true; | |
2271 | } | |
2272 | ||
2273 | return 0; | |
2274 | } | |
2275 | ||
7a3e0bb2 RZ |
2276 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2277 | { | |
2278 | int r = 0; | |
2279 | int i; | |
80f41f84 | 2280 | uint32_t smu_version; |
7a3e0bb2 RZ |
2281 | |
2282 | if (adev->asic_type >= CHIP_VEGA10) { | |
2283 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2284 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2285 | continue; | |
2286 | ||
e3c1b071 | 2287 | if (!adev->ip_blocks[i].status.sw) |
2288 | continue; | |
2289 | ||
482f0e53 ML |
2290 | /* no need to do the fw loading again if already done*/ |
2291 | if (adev->ip_blocks[i].status.hw == true) | |
2292 | break; | |
2293 | ||
53b3f8f4 | 2294 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2295 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2296 | if (r) { | |
2297 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2298 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2299 | return r; |
2300 | } | |
2301 | } else { | |
2302 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2303 | if (r) { | |
2304 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2305 | adev->ip_blocks[i].version->funcs->name, r); | |
2306 | return r; | |
7a3e0bb2 | 2307 | } |
7a3e0bb2 | 2308 | } |
482f0e53 ML |
2309 | |
2310 | adev->ip_blocks[i].status.hw = true; | |
2311 | break; | |
7a3e0bb2 RZ |
2312 | } |
2313 | } | |
482f0e53 | 2314 | |
8973d9ec ED |
2315 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2316 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2317 | |
80f41f84 | 2318 | return r; |
7a3e0bb2 RZ |
2319 | } |
2320 | ||
e3ecdffa AD |
2321 | /** |
2322 | * amdgpu_device_ip_init - run init for hardware IPs | |
2323 | * | |
2324 | * @adev: amdgpu_device pointer | |
2325 | * | |
2326 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2327 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2328 | * are run. sw_init initializes the software state associated with each IP | |
2329 | * and hw_init initializes the hardware associated with each IP. | |
2330 | * Returns 0 on success, negative error code on failure. | |
2331 | */ | |
06ec9070 | 2332 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2333 | { |
2334 | int i, r; | |
2335 | ||
c030f2e4 | 2336 | r = amdgpu_ras_init(adev); |
2337 | if (r) | |
2338 | return r; | |
2339 | ||
d38ceaf9 | 2340 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2341 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2342 | continue; |
a1255107 | 2343 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2344 | if (r) { |
a1255107 AD |
2345 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2346 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2347 | goto init_failed; |
2c1a2784 | 2348 | } |
a1255107 | 2349 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2350 | |
d38ceaf9 | 2351 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2352 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 2353 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2354 | if (r) { |
2355 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2356 | goto init_failed; |
2c1a2784 | 2357 | } |
a1255107 | 2358 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2359 | if (r) { |
2360 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2361 | goto init_failed; |
2c1a2784 | 2362 | } |
06ec9070 | 2363 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2364 | if (r) { |
06ec9070 | 2365 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2366 | goto init_failed; |
2c1a2784 | 2367 | } |
a1255107 | 2368 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2369 | |
2370 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2371 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2372 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2373 | AMDGPU_GEM_DOMAIN_VRAM, | |
2374 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2375 | if (r) { |
2376 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2377 | goto init_failed; |
2493664f ML |
2378 | } |
2379 | } | |
d38ceaf9 AD |
2380 | } |
2381 | } | |
2382 | ||
c9ffa427 YT |
2383 | if (amdgpu_sriov_vf(adev)) |
2384 | amdgpu_virt_init_data_exchange(adev); | |
2385 | ||
533aed27 AG |
2386 | r = amdgpu_ib_pool_init(adev); |
2387 | if (r) { | |
2388 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2389 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2390 | goto init_failed; | |
2391 | } | |
2392 | ||
c8963ea4 RZ |
2393 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2394 | if (r) | |
72d3f592 | 2395 | goto init_failed; |
0a4f2520 RZ |
2396 | |
2397 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2398 | if (r) | |
72d3f592 | 2399 | goto init_failed; |
0a4f2520 | 2400 | |
7a3e0bb2 RZ |
2401 | r = amdgpu_device_fw_loading(adev); |
2402 | if (r) | |
72d3f592 | 2403 | goto init_failed; |
7a3e0bb2 | 2404 | |
0a4f2520 RZ |
2405 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2406 | if (r) | |
72d3f592 | 2407 | goto init_failed; |
d38ceaf9 | 2408 | |
121a2bc6 AG |
2409 | /* |
2410 | * retired pages will be loaded from eeprom and reserved here, | |
2411 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2412 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2413 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2414 | * |
2415 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2416 | * failure from bad gpu situation and stop amdgpu init process | |
2417 | * accordingly. For other failed cases, it will still release all | |
2418 | * the resource and print error message, rather than returning one | |
2419 | * negative value to upper level. | |
121a2bc6 AG |
2420 | * |
2421 | * Note: theoretically, this should be called before all vram allocations | |
2422 | * to protect retired page from abusing | |
2423 | */ | |
b82e65a9 GC |
2424 | r = amdgpu_ras_recovery_init(adev); |
2425 | if (r) | |
2426 | goto init_failed; | |
121a2bc6 | 2427 | |
3e2e2ab5 HZ |
2428 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2429 | amdgpu_xgmi_add_device(adev); | |
e3c1b071 | 2430 | |
2431 | /* Don't init kfd if whole hive need to be reset during init */ | |
2432 | if (!adev->gmc.xgmi.pending_reset) | |
2433 | amdgpu_amdkfd_device_init(adev); | |
c6332b97 | 2434 | |
bd607166 KR |
2435 | amdgpu_fru_get_product_info(adev); |
2436 | ||
72d3f592 | 2437 | init_failed: |
c9ffa427 | 2438 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2439 | amdgpu_virt_release_full_gpu(adev, true); |
2440 | ||
72d3f592 | 2441 | return r; |
d38ceaf9 AD |
2442 | } |
2443 | ||
e3ecdffa AD |
2444 | /** |
2445 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2446 | * | |
2447 | * @adev: amdgpu_device pointer | |
2448 | * | |
2449 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2450 | * this function before a GPU reset. If the value is retained after a | |
2451 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2452 | */ | |
06ec9070 | 2453 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2454 | { |
2455 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2456 | } | |
2457 | ||
e3ecdffa AD |
2458 | /** |
2459 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2460 | * | |
2461 | * @adev: amdgpu_device pointer | |
2462 | * | |
2463 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2464 | * The driver calls this after a GPU reset to see if the contents of | |
2465 | * VRAM is lost or now. | |
2466 | * returns true if vram is lost, false if not. | |
2467 | */ | |
06ec9070 | 2468 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2469 | { |
dadce777 EQ |
2470 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2471 | AMDGPU_RESET_MAGIC_NUM)) | |
2472 | return true; | |
2473 | ||
53b3f8f4 | 2474 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2475 | return false; |
2476 | ||
2477 | /* | |
2478 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2479 | * always assumed to be lost. | |
2480 | */ | |
2481 | switch (amdgpu_asic_reset_method(adev)) { | |
2482 | case AMD_RESET_METHOD_BACO: | |
2483 | case AMD_RESET_METHOD_MODE1: | |
2484 | return true; | |
2485 | default: | |
2486 | return false; | |
2487 | } | |
0c49e0b8 CZ |
2488 | } |
2489 | ||
e3ecdffa | 2490 | /** |
1112a46b | 2491 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2492 | * |
2493 | * @adev: amdgpu_device pointer | |
b8b72130 | 2494 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2495 | * |
e3ecdffa | 2496 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2497 | * set_clockgating_state callbacks are run. |
2498 | * Late initialization pass enabling clockgating for hardware IPs. | |
2499 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2500 | * Returns 0 on success, negative error code on failure. |
2501 | */ | |
fdd34271 | 2502 | |
5d89bb2d LL |
2503 | int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2504 | enum amd_clockgating_state state) | |
d38ceaf9 | 2505 | { |
1112a46b | 2506 | int i, j, r; |
d38ceaf9 | 2507 | |
4a2ba394 SL |
2508 | if (amdgpu_emu_mode == 1) |
2509 | return 0; | |
2510 | ||
1112a46b RZ |
2511 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2512 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2513 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2514 | continue; |
5d70a549 PV |
2515 | /* skip CG for GFX on S0ix */ |
2516 | if (adev->in_s0ix && | |
2517 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2518 | continue; | |
4a446d55 | 2519 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2520 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2521 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2522 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2523 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2524 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2525 | /* enable clockgating to save power */ |
a1255107 | 2526 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2527 | state); |
4a446d55 AD |
2528 | if (r) { |
2529 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2530 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2531 | return r; |
2532 | } | |
b0b00ff1 | 2533 | } |
d38ceaf9 | 2534 | } |
06b18f61 | 2535 | |
c9f96fd5 RZ |
2536 | return 0; |
2537 | } | |
2538 | ||
5d89bb2d LL |
2539 | int amdgpu_device_set_pg_state(struct amdgpu_device *adev, |
2540 | enum amd_powergating_state state) | |
c9f96fd5 | 2541 | { |
1112a46b | 2542 | int i, j, r; |
06b18f61 | 2543 | |
c9f96fd5 RZ |
2544 | if (amdgpu_emu_mode == 1) |
2545 | return 0; | |
2546 | ||
1112a46b RZ |
2547 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2548 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2549 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 | 2550 | continue; |
5d70a549 PV |
2551 | /* skip PG for GFX on S0ix */ |
2552 | if (adev->in_s0ix && | |
2553 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2554 | continue; | |
c9f96fd5 RZ |
2555 | /* skip CG for VCE/UVD, it's handled specially */ |
2556 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2557 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2558 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2559 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2560 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2561 | /* enable powergating to save power */ | |
2562 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2563 | state); |
c9f96fd5 RZ |
2564 | if (r) { |
2565 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2566 | adev->ip_blocks[i].version->funcs->name, r); | |
2567 | return r; | |
2568 | } | |
2569 | } | |
2570 | } | |
2dc80b00 S |
2571 | return 0; |
2572 | } | |
2573 | ||
beff74bc AD |
2574 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2575 | { | |
2576 | struct amdgpu_gpu_instance *gpu_ins; | |
2577 | struct amdgpu_device *adev; | |
2578 | int i, ret = 0; | |
2579 | ||
2580 | mutex_lock(&mgpu_info.mutex); | |
2581 | ||
2582 | /* | |
2583 | * MGPU fan boost feature should be enabled | |
2584 | * only when there are two or more dGPUs in | |
2585 | * the system | |
2586 | */ | |
2587 | if (mgpu_info.num_dgpu < 2) | |
2588 | goto out; | |
2589 | ||
2590 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2591 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2592 | adev = gpu_ins->adev; | |
2593 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2594 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2595 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2596 | if (ret) | |
2597 | break; | |
2598 | ||
2599 | gpu_ins->mgpu_fan_enabled = 1; | |
2600 | } | |
2601 | } | |
2602 | ||
2603 | out: | |
2604 | mutex_unlock(&mgpu_info.mutex); | |
2605 | ||
2606 | return ret; | |
2607 | } | |
2608 | ||
e3ecdffa AD |
2609 | /** |
2610 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2611 | * | |
2612 | * @adev: amdgpu_device pointer | |
2613 | * | |
2614 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2615 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2616 | * late_init covers any special initialization that an IP requires | |
2617 | * after all of the have been initialized or something that needs to happen | |
2618 | * late in the init process. | |
2619 | * Returns 0 on success, negative error code on failure. | |
2620 | */ | |
06ec9070 | 2621 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2622 | { |
60599a03 | 2623 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2624 | int i = 0, r; |
2625 | ||
2626 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2627 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2628 | continue; |
2629 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2630 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2631 | if (r) { | |
2632 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2633 | adev->ip_blocks[i].version->funcs->name, r); | |
2634 | return r; | |
2635 | } | |
2dc80b00 | 2636 | } |
73f847db | 2637 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2638 | } |
2639 | ||
a891d239 DL |
2640 | amdgpu_ras_set_error_query_ready(adev, true); |
2641 | ||
1112a46b RZ |
2642 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2643 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2644 | |
06ec9070 | 2645 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2646 | |
beff74bc AD |
2647 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2648 | if (r) | |
2649 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2650 | ||
2d02893f | 2651 | /* For XGMI + passthrough configuration on arcturus, enable light SBR */ |
2652 | if (adev->asic_type == CHIP_ARCTURUS && | |
2653 | amdgpu_passthrough(adev) && | |
2654 | adev->gmc.xgmi.num_physical_nodes > 1) | |
2655 | smu_set_light_sbr(&adev->smu, true); | |
60599a03 EQ |
2656 | |
2657 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2658 | mutex_lock(&mgpu_info.mutex); | |
2659 | ||
2660 | /* | |
2661 | * Reset device p-state to low as this was booted with high. | |
2662 | * | |
2663 | * This should be performed only after all devices from the same | |
2664 | * hive get initialized. | |
2665 | * | |
2666 | * However, it's unknown how many device in the hive in advance. | |
2667 | * As this is counted one by one during devices initializations. | |
2668 | * | |
2669 | * So, we wait for all XGMI interlinked devices initialized. | |
2670 | * This may bring some delays as those devices may come from | |
2671 | * different hives. But that should be OK. | |
2672 | */ | |
2673 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2674 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2675 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2676 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2677 | continue; | |
2678 | ||
d84a430d JK |
2679 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2680 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2681 | if (r) { |
2682 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2683 | break; | |
2684 | } | |
2685 | } | |
2686 | } | |
2687 | ||
2688 | mutex_unlock(&mgpu_info.mutex); | |
2689 | } | |
2690 | ||
d38ceaf9 AD |
2691 | return 0; |
2692 | } | |
2693 | ||
e9669fb7 | 2694 | static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) |
d38ceaf9 AD |
2695 | { |
2696 | int i, r; | |
2697 | ||
e9669fb7 AG |
2698 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2699 | if (!adev->ip_blocks[i].version->funcs->early_fini) | |
2700 | continue; | |
5278a159 | 2701 | |
e9669fb7 AG |
2702 | r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); |
2703 | if (r) { | |
2704 | DRM_DEBUG("early_fini of IP block <%s> failed %d\n", | |
2705 | adev->ip_blocks[i].version->funcs->name, r); | |
2706 | } | |
2707 | } | |
c030f2e4 | 2708 | |
e9669fb7 | 2709 | amdgpu_amdkfd_suspend(adev, false); |
a82400b5 | 2710 | |
05df1f01 | 2711 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
2712 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2713 | ||
3e96dbfd AD |
2714 | /* need to disable SMC first */ |
2715 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2716 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 2717 | continue; |
fdd34271 | 2718 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 2719 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
2720 | /* XXX handle errors */ |
2721 | if (r) { | |
2722 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 2723 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 2724 | } |
a1255107 | 2725 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
2726 | break; |
2727 | } | |
2728 | } | |
2729 | ||
d38ceaf9 | 2730 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2731 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2732 | continue; |
8201a67a | 2733 | |
a1255107 | 2734 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2735 | /* XXX handle errors */ |
2c1a2784 | 2736 | if (r) { |
a1255107 AD |
2737 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2738 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2739 | } |
8201a67a | 2740 | |
a1255107 | 2741 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2742 | } |
2743 | ||
e9669fb7 AG |
2744 | return 0; |
2745 | } | |
2746 | ||
2747 | /** | |
2748 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2749 | * | |
2750 | * @adev: amdgpu_device pointer | |
2751 | * | |
2752 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2753 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2754 | * are run. hw_fini tears down the hardware associated with each IP | |
2755 | * and sw_fini tears down any software state associated with each IP. | |
2756 | * Returns 0 on success, negative error code on failure. | |
2757 | */ | |
2758 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |
2759 | { | |
2760 | int i, r; | |
2761 | ||
2762 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) | |
2763 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2764 | ||
2765 | amdgpu_ras_pre_fini(adev); | |
2766 | ||
2767 | if (adev->gmc.xgmi.num_physical_nodes > 1) | |
2768 | amdgpu_xgmi_remove_device(adev); | |
2769 | ||
2770 | amdgpu_amdkfd_device_fini_sw(adev); | |
9950cda2 | 2771 | |
d38ceaf9 | 2772 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2773 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2774 | continue; |
c12aba3a ML |
2775 | |
2776 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2777 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2778 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2779 | amdgpu_device_wb_fini(adev); |
2780 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2781 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2782 | } |
2783 | ||
a1255107 | 2784 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2785 | /* XXX handle errors */ |
2c1a2784 | 2786 | if (r) { |
a1255107 AD |
2787 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2788 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2789 | } |
a1255107 AD |
2790 | adev->ip_blocks[i].status.sw = false; |
2791 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2792 | } |
2793 | ||
a6dcfd9c | 2794 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2795 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2796 | continue; |
a1255107 AD |
2797 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2798 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2799 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2800 | } |
2801 | ||
c030f2e4 | 2802 | amdgpu_ras_fini(adev); |
2803 | ||
030308fc | 2804 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
2805 | if (amdgpu_virt_release_full_gpu(adev, false)) |
2806 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 2807 | |
d38ceaf9 AD |
2808 | return 0; |
2809 | } | |
2810 | ||
e3ecdffa | 2811 | /** |
beff74bc | 2812 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2813 | * |
1112a46b | 2814 | * @work: work_struct. |
e3ecdffa | 2815 | */ |
beff74bc | 2816 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2817 | { |
2818 | struct amdgpu_device *adev = | |
beff74bc | 2819 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2820 | int r; |
2821 | ||
2822 | r = amdgpu_ib_ring_tests(adev); | |
2823 | if (r) | |
2824 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2825 | } |
2826 | ||
1e317b99 RZ |
2827 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2828 | { | |
2829 | struct amdgpu_device *adev = | |
2830 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2831 | ||
2832 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
2833 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
2834 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2835 | adev->gfx.gfx_off_state = true; | |
2836 | } | |
2837 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
2838 | } | |
2839 | ||
e3ecdffa | 2840 | /** |
e7854a03 | 2841 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2842 | * |
2843 | * @adev: amdgpu_device pointer | |
2844 | * | |
2845 | * Main suspend function for hardware IPs. The list of all the hardware | |
2846 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2847 | * suspend callbacks are run. suspend puts the hardware and software state | |
2848 | * in each IP into a state suitable for suspend. | |
2849 | * Returns 0 on success, negative error code on failure. | |
2850 | */ | |
e7854a03 AD |
2851 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2852 | { | |
2853 | int i, r; | |
2854 | ||
50ec83f0 AD |
2855 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2856 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2857 | |
e7854a03 AD |
2858 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2859 | if (!adev->ip_blocks[i].status.valid) | |
2860 | continue; | |
2b9f7848 | 2861 | |
e7854a03 | 2862 | /* displays are handled separately */ |
2b9f7848 ND |
2863 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2864 | continue; | |
2865 | ||
2866 | /* XXX handle errors */ | |
2867 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2868 | /* XXX handle errors */ | |
2869 | if (r) { | |
2870 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2871 | adev->ip_blocks[i].version->funcs->name, r); | |
2872 | return r; | |
e7854a03 | 2873 | } |
2b9f7848 ND |
2874 | |
2875 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2876 | } |
2877 | ||
e7854a03 AD |
2878 | return 0; |
2879 | } | |
2880 | ||
2881 | /** | |
2882 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2883 | * | |
2884 | * @adev: amdgpu_device pointer | |
2885 | * | |
2886 | * Main suspend function for hardware IPs. The list of all the hardware | |
2887 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2888 | * suspend callbacks are run. suspend puts the hardware and software state | |
2889 | * in each IP into a state suitable for suspend. | |
2890 | * Returns 0 on success, negative error code on failure. | |
2891 | */ | |
2892 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2893 | { |
2894 | int i, r; | |
2895 | ||
557f42a2 | 2896 | if (adev->in_s0ix) |
34416931 | 2897 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); |
34416931 | 2898 | |
d38ceaf9 | 2899 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2900 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2901 | continue; |
e7854a03 AD |
2902 | /* displays are handled in phase1 */ |
2903 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2904 | continue; | |
bff77e86 LM |
2905 | /* PSP lost connection when err_event_athub occurs */ |
2906 | if (amdgpu_ras_intr_triggered() && | |
2907 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2908 | adev->ip_blocks[i].status.hw = false; | |
2909 | continue; | |
2910 | } | |
e3c1b071 | 2911 | |
2912 | /* skip unnecessary suspend if we do not initialize them yet */ | |
2913 | if (adev->gmc.xgmi.pending_reset && | |
2914 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2915 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
2916 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2917 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
2918 | adev->ip_blocks[i].status.hw = false; | |
2919 | continue; | |
2920 | } | |
557f42a2 | 2921 | |
32ff160d AD |
2922 | /* skip suspend of gfx and psp for S0ix |
2923 | * gfx is in gfxoff state, so on resume it will exit gfxoff just | |
2924 | * like at runtime. PSP is also part of the always on hardware | |
2925 | * so no need to suspend it. | |
2926 | */ | |
557f42a2 | 2927 | if (adev->in_s0ix && |
32ff160d AD |
2928 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || |
2929 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)) | |
557f42a2 AD |
2930 | continue; |
2931 | ||
d38ceaf9 | 2932 | /* XXX handle errors */ |
a1255107 | 2933 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2934 | /* XXX handle errors */ |
2c1a2784 | 2935 | if (r) { |
a1255107 AD |
2936 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2937 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2938 | } |
876923fb | 2939 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 2940 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
2941 | if(!amdgpu_sriov_vf(adev)){ |
2942 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2943 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
2944 | if (r) { | |
2945 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2946 | adev->mp1_state, r); | |
2947 | return r; | |
2948 | } | |
a3a09142 AD |
2949 | } |
2950 | } | |
d38ceaf9 AD |
2951 | } |
2952 | ||
2953 | return 0; | |
2954 | } | |
2955 | ||
e7854a03 AD |
2956 | /** |
2957 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2958 | * | |
2959 | * @adev: amdgpu_device pointer | |
2960 | * | |
2961 | * Main suspend function for hardware IPs. The list of all the hardware | |
2962 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2963 | * suspend callbacks are run. suspend puts the hardware and software state | |
2964 | * in each IP into a state suitable for suspend. | |
2965 | * Returns 0 on success, negative error code on failure. | |
2966 | */ | |
2967 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2968 | { | |
2969 | int r; | |
2970 | ||
3c73683c JC |
2971 | if (amdgpu_sriov_vf(adev)) { |
2972 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 2973 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 2974 | } |
e7819644 | 2975 | |
e7854a03 AD |
2976 | r = amdgpu_device_ip_suspend_phase1(adev); |
2977 | if (r) | |
2978 | return r; | |
2979 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2980 | ||
e7819644 YT |
2981 | if (amdgpu_sriov_vf(adev)) |
2982 | amdgpu_virt_release_full_gpu(adev, false); | |
2983 | ||
e7854a03 AD |
2984 | return r; |
2985 | } | |
2986 | ||
06ec9070 | 2987 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2988 | { |
2989 | int i, r; | |
2990 | ||
2cb681b6 ML |
2991 | static enum amd_ip_block_type ip_order[] = { |
2992 | AMD_IP_BLOCK_TYPE_GMC, | |
2993 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2994 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2995 | AMD_IP_BLOCK_TYPE_IH, |
2996 | }; | |
a90ad3c2 | 2997 | |
95ea3dbc | 2998 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2cb681b6 ML |
2999 | int j; |
3000 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3001 | |
4cd2a96d J |
3002 | block = &adev->ip_blocks[i]; |
3003 | block->status.hw = false; | |
2cb681b6 | 3004 | |
4cd2a96d | 3005 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 3006 | |
4cd2a96d | 3007 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
3008 | !block->status.valid) |
3009 | continue; | |
3010 | ||
3011 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 3012 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3013 | if (r) |
3014 | return r; | |
482f0e53 | 3015 | block->status.hw = true; |
a90ad3c2 ML |
3016 | } |
3017 | } | |
3018 | ||
3019 | return 0; | |
3020 | } | |
3021 | ||
06ec9070 | 3022 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3023 | { |
3024 | int i, r; | |
3025 | ||
2cb681b6 ML |
3026 | static enum amd_ip_block_type ip_order[] = { |
3027 | AMD_IP_BLOCK_TYPE_SMC, | |
3028 | AMD_IP_BLOCK_TYPE_DCE, | |
3029 | AMD_IP_BLOCK_TYPE_GFX, | |
3030 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 3031 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
3032 | AMD_IP_BLOCK_TYPE_VCE, |
3033 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 3034 | }; |
a90ad3c2 | 3035 | |
2cb681b6 ML |
3036 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
3037 | int j; | |
3038 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3039 | |
2cb681b6 ML |
3040 | for (j = 0; j < adev->num_ip_blocks; j++) { |
3041 | block = &adev->ip_blocks[j]; | |
3042 | ||
3043 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
3044 | !block->status.valid || |
3045 | block->status.hw) | |
2cb681b6 ML |
3046 | continue; |
3047 | ||
895bd048 JZ |
3048 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
3049 | r = block->version->funcs->resume(adev); | |
3050 | else | |
3051 | r = block->version->funcs->hw_init(adev); | |
3052 | ||
0aaeefcc | 3053 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3054 | if (r) |
3055 | return r; | |
482f0e53 | 3056 | block->status.hw = true; |
a90ad3c2 ML |
3057 | } |
3058 | } | |
3059 | ||
3060 | return 0; | |
3061 | } | |
3062 | ||
e3ecdffa AD |
3063 | /** |
3064 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
3065 | * | |
3066 | * @adev: amdgpu_device pointer | |
3067 | * | |
3068 | * First resume function for hardware IPs. The list of all the hardware | |
3069 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3070 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
3071 | * after a suspend and updates the software state as necessary. This | |
3072 | * function is also used for restoring the GPU after a GPU reset. | |
3073 | * Returns 0 on success, negative error code on failure. | |
3074 | */ | |
06ec9070 | 3075 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
3076 | { |
3077 | int i, r; | |
3078 | ||
a90ad3c2 | 3079 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 3080 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 3081 | continue; |
a90ad3c2 | 3082 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
3083 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
3084 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 3085 | |
fcf0649f CZ |
3086 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
3087 | if (r) { | |
3088 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
3089 | adev->ip_blocks[i].version->funcs->name, r); | |
3090 | return r; | |
3091 | } | |
482f0e53 | 3092 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
3093 | } |
3094 | } | |
3095 | ||
3096 | return 0; | |
3097 | } | |
3098 | ||
e3ecdffa AD |
3099 | /** |
3100 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
3101 | * | |
3102 | * @adev: amdgpu_device pointer | |
3103 | * | |
3104 | * First resume function for hardware IPs. The list of all the hardware | |
3105 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3106 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
3107 | * functional state after a suspend and updates the software state as | |
3108 | * necessary. This function is also used for restoring the GPU after a GPU | |
3109 | * reset. | |
3110 | * Returns 0 on success, negative error code on failure. | |
3111 | */ | |
06ec9070 | 3112 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
3113 | { |
3114 | int i, r; | |
3115 | ||
3116 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 3117 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 3118 | continue; |
fcf0649f | 3119 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3120 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
3121 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3122 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 3123 | continue; |
a1255107 | 3124 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 3125 | if (r) { |
a1255107 AD |
3126 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
3127 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 3128 | return r; |
2c1a2784 | 3129 | } |
482f0e53 | 3130 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
3131 | } |
3132 | ||
3133 | return 0; | |
3134 | } | |
3135 | ||
e3ecdffa AD |
3136 | /** |
3137 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
3138 | * | |
3139 | * @adev: amdgpu_device pointer | |
3140 | * | |
3141 | * Main resume function for hardware IPs. The hardware IPs | |
3142 | * are split into two resume functions because they are | |
3143 | * are also used in in recovering from a GPU reset and some additional | |
3144 | * steps need to be take between them. In this case (S3/S4) they are | |
3145 | * run sequentially. | |
3146 | * Returns 0 on success, negative error code on failure. | |
3147 | */ | |
06ec9070 | 3148 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
3149 | { |
3150 | int r; | |
3151 | ||
06ec9070 | 3152 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
3153 | if (r) |
3154 | return r; | |
7a3e0bb2 RZ |
3155 | |
3156 | r = amdgpu_device_fw_loading(adev); | |
3157 | if (r) | |
3158 | return r; | |
3159 | ||
06ec9070 | 3160 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
3161 | |
3162 | return r; | |
3163 | } | |
3164 | ||
e3ecdffa AD |
3165 | /** |
3166 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
3167 | * | |
3168 | * @adev: amdgpu_device pointer | |
3169 | * | |
3170 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
3171 | */ | |
4e99a44e | 3172 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 3173 | { |
6867e1b5 ML |
3174 | if (amdgpu_sriov_vf(adev)) { |
3175 | if (adev->is_atom_fw) { | |
58ff791a | 3176 | if (amdgpu_atomfirmware_gpu_virtualization_supported(adev)) |
6867e1b5 ML |
3177 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; |
3178 | } else { | |
3179 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3180 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3181 | } | |
3182 | ||
3183 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3184 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3185 | } |
048765ad AR |
3186 | } |
3187 | ||
e3ecdffa AD |
3188 | /** |
3189 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3190 | * | |
3191 | * @asic_type: AMD asic type | |
3192 | * | |
3193 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3194 | * returns true if DC has support, false if not. | |
3195 | */ | |
4562236b HW |
3196 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3197 | { | |
3198 | switch (asic_type) { | |
3199 | #if defined(CONFIG_DRM_AMD_DC) | |
64200c46 MR |
3200 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3201 | case CHIP_TAHITI: | |
3202 | case CHIP_PITCAIRN: | |
3203 | case CHIP_VERDE: | |
3204 | case CHIP_OLAND: | |
3205 | #endif | |
4562236b | 3206 | case CHIP_BONAIRE: |
0d6fbccb | 3207 | case CHIP_KAVERI: |
367e6687 AD |
3208 | case CHIP_KABINI: |
3209 | case CHIP_MULLINS: | |
d9fda248 HW |
3210 | /* |
3211 | * We have systems in the wild with these ASICs that require | |
3212 | * LVDS and VGA support which is not supported with DC. | |
3213 | * | |
3214 | * Fallback to the non-DC driver here by default so as not to | |
3215 | * cause regressions. | |
3216 | */ | |
3217 | return amdgpu_dc > 0; | |
3218 | case CHIP_HAWAII: | |
4562236b HW |
3219 | case CHIP_CARRIZO: |
3220 | case CHIP_STONEY: | |
4562236b | 3221 | case CHIP_POLARIS10: |
675fd32b | 3222 | case CHIP_POLARIS11: |
2c8ad2d5 | 3223 | case CHIP_POLARIS12: |
675fd32b | 3224 | case CHIP_VEGAM: |
4562236b HW |
3225 | case CHIP_TONGA: |
3226 | case CHIP_FIJI: | |
42f8ffa1 | 3227 | case CHIP_VEGA10: |
dca7b401 | 3228 | case CHIP_VEGA12: |
c6034aa2 | 3229 | case CHIP_VEGA20: |
b86a1aa3 | 3230 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
fd187853 | 3231 | case CHIP_RAVEN: |
b4f199c7 | 3232 | case CHIP_NAVI10: |
8fceceb6 | 3233 | case CHIP_NAVI14: |
078655d9 | 3234 | case CHIP_NAVI12: |
e1c14c43 | 3235 | case CHIP_RENOIR: |
81d9bfb8 | 3236 | case CHIP_SIENNA_CICHLID: |
a6c5308f | 3237 | case CHIP_NAVY_FLOUNDER: |
7cc656e2 | 3238 | case CHIP_DIMGREY_CAVEFISH: |
ddaed58b | 3239 | case CHIP_BEIGE_GOBY: |
84b934bc | 3240 | case CHIP_VANGOGH: |
c8b73f7f | 3241 | case CHIP_YELLOW_CARP: |
42f8ffa1 | 3242 | #endif |
fd187853 | 3243 | return amdgpu_dc != 0; |
4562236b HW |
3244 | #endif |
3245 | default: | |
93b09a9a | 3246 | if (amdgpu_dc > 0) |
044a48f4 | 3247 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter " |
93b09a9a | 3248 | "but isn't supported by ASIC, ignoring\n"); |
4562236b HW |
3249 | return false; |
3250 | } | |
3251 | } | |
3252 | ||
3253 | /** | |
3254 | * amdgpu_device_has_dc_support - check if dc is supported | |
3255 | * | |
982a820b | 3256 | * @adev: amdgpu_device pointer |
4562236b HW |
3257 | * |
3258 | * Returns true for supported, false for not supported | |
3259 | */ | |
3260 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3261 | { | |
abaf210c AS |
3262 | if (amdgpu_sriov_vf(adev) || |
3263 | adev->enable_virtual_display || | |
3264 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) | |
2555039d XY |
3265 | return false; |
3266 | ||
4562236b HW |
3267 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3268 | } | |
3269 | ||
d4535e2c AG |
3270 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) |
3271 | { | |
3272 | struct amdgpu_device *adev = | |
3273 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3274 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3275 | |
c6a6e2db AG |
3276 | /* It's a bug to not have a hive within this function */ |
3277 | if (WARN_ON(!hive)) | |
3278 | return; | |
3279 | ||
3280 | /* | |
3281 | * Use task barrier to synchronize all xgmi reset works across the | |
3282 | * hive. task_barrier_enter and task_barrier_exit will block | |
3283 | * until all the threads running the xgmi reset works reach | |
3284 | * those points. task_barrier_full will do both blocks. | |
3285 | */ | |
3286 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3287 | ||
3288 | task_barrier_enter(&hive->tb); | |
4a580877 | 3289 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3290 | |
3291 | if (adev->asic_reset_res) | |
3292 | goto fail; | |
3293 | ||
3294 | task_barrier_exit(&hive->tb); | |
4a580877 | 3295 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3296 | |
3297 | if (adev->asic_reset_res) | |
3298 | goto fail; | |
43c4d576 | 3299 | |
8bc7b360 HZ |
3300 | if (adev->mmhub.ras_funcs && |
3301 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
3302 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
c6a6e2db AG |
3303 | } else { |
3304 | ||
3305 | task_barrier_full(&hive->tb); | |
3306 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3307 | } | |
ce316fa5 | 3308 | |
c6a6e2db | 3309 | fail: |
d4535e2c | 3310 | if (adev->asic_reset_res) |
fed184e9 | 3311 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3312 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3313 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3314 | } |
3315 | ||
71f98027 AD |
3316 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3317 | { | |
3318 | char *input = amdgpu_lockup_timeout; | |
3319 | char *timeout_setting = NULL; | |
3320 | int index = 0; | |
3321 | long timeout; | |
3322 | int ret = 0; | |
3323 | ||
3324 | /* | |
67387dfe AD |
3325 | * By default timeout for non compute jobs is 10000 |
3326 | * and 60000 for compute jobs. | |
71f98027 | 3327 | * In SR-IOV or passthrough mode, timeout for compute |
b7b2a316 | 3328 | * jobs are 60000 by default. |
71f98027 AD |
3329 | */ |
3330 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3331 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3332 | if (amdgpu_sriov_vf(adev)) |
3333 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3334 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
71f98027 | 3335 | else |
67387dfe | 3336 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 | 3337 | |
f440ff44 | 3338 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3339 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3340 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3341 | ret = kstrtol(timeout_setting, 0, &timeout); |
3342 | if (ret) | |
3343 | return ret; | |
3344 | ||
3345 | if (timeout == 0) { | |
3346 | index++; | |
3347 | continue; | |
3348 | } else if (timeout < 0) { | |
3349 | timeout = MAX_SCHEDULE_TIMEOUT; | |
3350 | } else { | |
3351 | timeout = msecs_to_jiffies(timeout); | |
3352 | } | |
3353 | ||
3354 | switch (index++) { | |
3355 | case 0: | |
3356 | adev->gfx_timeout = timeout; | |
3357 | break; | |
3358 | case 1: | |
3359 | adev->compute_timeout = timeout; | |
3360 | break; | |
3361 | case 2: | |
3362 | adev->sdma_timeout = timeout; | |
3363 | break; | |
3364 | case 3: | |
3365 | adev->video_timeout = timeout; | |
3366 | break; | |
3367 | default: | |
3368 | break; | |
3369 | } | |
3370 | } | |
3371 | /* | |
3372 | * There is only one value specified and | |
3373 | * it should apply to all non-compute jobs. | |
3374 | */ | |
bcccee89 | 3375 | if (index == 1) { |
71f98027 | 3376 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3377 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3378 | adev->compute_timeout = adev->gfx_timeout; | |
3379 | } | |
71f98027 AD |
3380 | } |
3381 | ||
3382 | return ret; | |
3383 | } | |
d4535e2c | 3384 | |
77f3a5cd ND |
3385 | static const struct attribute *amdgpu_dev_attributes[] = { |
3386 | &dev_attr_product_name.attr, | |
3387 | &dev_attr_product_number.attr, | |
3388 | &dev_attr_serial_number.attr, | |
3389 | &dev_attr_pcie_replay_count.attr, | |
3390 | NULL | |
3391 | }; | |
3392 | ||
d38ceaf9 AD |
3393 | /** |
3394 | * amdgpu_device_init - initialize the driver | |
3395 | * | |
3396 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3397 | * @flags: driver flags |
3398 | * | |
3399 | * Initializes the driver info and hw (all asics). | |
3400 | * Returns 0 for success or an error on failure. | |
3401 | * Called at driver startup. | |
3402 | */ | |
3403 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3404 | uint32_t flags) |
3405 | { | |
8aba21b7 LT |
3406 | struct drm_device *ddev = adev_to_drm(adev); |
3407 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3408 | int r, i; |
b98c6299 | 3409 | bool px = false; |
95844d20 | 3410 | u32 max_MBps; |
d38ceaf9 AD |
3411 | |
3412 | adev->shutdown = false; | |
d38ceaf9 | 3413 | adev->flags = flags; |
4e66d7d2 YZ |
3414 | |
3415 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3416 | adev->asic_type = amdgpu_force_asic_type; | |
3417 | else | |
3418 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3419 | ||
d38ceaf9 | 3420 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3421 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3422 | adev->usec_timeout *= 10; |
770d13b1 | 3423 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3424 | adev->accel_working = false; |
3425 | adev->num_rings = 0; | |
3426 | adev->mman.buffer_funcs = NULL; | |
3427 | adev->mman.buffer_funcs_ring = NULL; | |
3428 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3429 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3430 | adev->gmc.gmc_funcs = NULL; |
7bd939d0 | 3431 | adev->harvest_ip_mask = 0x0; |
f54d1867 | 3432 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3433 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3434 | |
3435 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3436 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3437 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3438 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3439 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3440 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3441 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3442 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3443 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3444 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3445 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3446 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3447 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3448 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3449 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3450 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3451 | ||
3e39ab90 AD |
3452 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3453 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3454 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3455 | |
3456 | /* mutex initialization are all done here so we | |
3457 | * can recall function without having locking issues */ | |
0e5ca0d1 | 3458 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3459 | mutex_init(&adev->pm.mutex); |
3460 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3461 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3462 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3463 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3464 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3465 | mutex_init(&adev->mn_lock); |
e23b74aa | 3466 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3467 | hash_init(adev->mn_hash); |
53b3f8f4 | 3468 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 3469 | init_rwsem(&adev->reset_sem); |
32eaeae0 | 3470 | mutex_init(&adev->psp.mutex); |
bd052211 | 3471 | mutex_init(&adev->notifier_lock); |
d38ceaf9 | 3472 | |
9f6a7857 HR |
3473 | r = amdgpu_device_init_apu_flags(adev); |
3474 | if (r) | |
3475 | return r; | |
3476 | ||
912dfc84 EQ |
3477 | r = amdgpu_device_check_arguments(adev); |
3478 | if (r) | |
3479 | return r; | |
d38ceaf9 | 3480 | |
d38ceaf9 AD |
3481 | spin_lock_init(&adev->mmio_idx_lock); |
3482 | spin_lock_init(&adev->smc_idx_lock); | |
3483 | spin_lock_init(&adev->pcie_idx_lock); | |
3484 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3485 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3486 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3487 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3488 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3489 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3490 | |
0c4e7fa5 CZ |
3491 | INIT_LIST_HEAD(&adev->shadow_list); |
3492 | mutex_init(&adev->shadow_list_lock); | |
3493 | ||
655ce9cb | 3494 | INIT_LIST_HEAD(&adev->reset_list); |
3495 | ||
beff74bc AD |
3496 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3497 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3498 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3499 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3500 | |
d4535e2c AG |
3501 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3502 | ||
d23ee13f | 3503 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3504 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3505 | |
b265bdbd EQ |
3506 | atomic_set(&adev->throttling_logging_enabled, 1); |
3507 | /* | |
3508 | * If throttling continues, logging will be performed every minute | |
3509 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3510 | * throttling interrupt comes every second. Thus, the total logging | |
3511 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3512 | * for throttling interrupt) = 60 seconds. | |
3513 | */ | |
3514 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3515 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3516 | ||
0fa49558 AX |
3517 | /* Registers mapping */ |
3518 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3519 | if (adev->asic_type >= CHIP_BONAIRE) { |
3520 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3521 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3522 | } else { | |
3523 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3524 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3525 | } | |
d38ceaf9 | 3526 | |
d38ceaf9 AD |
3527 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3528 | if (adev->rmmio == NULL) { | |
3529 | return -ENOMEM; | |
3530 | } | |
3531 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3532 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3533 | ||
b2109d8e JX |
3534 | /* enable PCIE atomic ops */ |
3535 | r = pci_enable_atomic_ops_to_root(adev->pdev, | |
3536 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3537 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3538 | if (r) { | |
3539 | adev->have_atomics_support = false; | |
3540 | DRM_INFO("PCIE atomic ops is not supported\n"); | |
3541 | } else { | |
3542 | adev->have_atomics_support = true; | |
3543 | } | |
3544 | ||
5494d864 AD |
3545 | amdgpu_device_get_pcie_info(adev); |
3546 | ||
b239c017 JX |
3547 | if (amdgpu_mcbp) |
3548 | DRM_INFO("MCBP is enabled\n"); | |
3549 | ||
5f84cc63 JX |
3550 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
3551 | adev->enable_mes = true; | |
3552 | ||
3aa0115d ML |
3553 | /* detect hw virtualization here */ |
3554 | amdgpu_detect_virtualization(adev); | |
3555 | ||
dffa11b4 ML |
3556 | r = amdgpu_device_get_job_timeout_settings(adev); |
3557 | if (r) { | |
3558 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
4ef87d8f | 3559 | return r; |
a190d1c7 XY |
3560 | } |
3561 | ||
d38ceaf9 | 3562 | /* early init functions */ |
06ec9070 | 3563 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 3564 | if (r) |
4ef87d8f | 3565 | return r; |
d38ceaf9 | 3566 | |
6585661d OZ |
3567 | /* doorbell bar mapping and doorbell index init*/ |
3568 | amdgpu_device_doorbell_init(adev); | |
3569 | ||
9475a943 SL |
3570 | if (amdgpu_emu_mode == 1) { |
3571 | /* post the asic on emulation mode */ | |
3572 | emu_soc_asic_init(adev); | |
bfca0289 | 3573 | goto fence_driver_init; |
9475a943 | 3574 | } |
bfca0289 | 3575 | |
04442bf7 LL |
3576 | amdgpu_reset_init(adev); |
3577 | ||
4e99a44e ML |
3578 | /* detect if we are with an SRIOV vbios */ |
3579 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3580 | |
95e8e59e AD |
3581 | /* check if we need to reset the asic |
3582 | * E.g., driver was not cleanly unloaded previously, etc. | |
3583 | */ | |
f14899fd | 3584 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 3585 | if (adev->gmc.xgmi.num_physical_nodes) { |
3586 | dev_info(adev->dev, "Pending hive reset.\n"); | |
3587 | adev->gmc.xgmi.pending_reset = true; | |
3588 | /* Only need to init necessary block for SMU to handle the reset */ | |
3589 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3590 | if (!adev->ip_blocks[i].status.valid) | |
3591 | continue; | |
3592 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3593 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3594 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
3595 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 3596 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 3597 | adev->ip_blocks[i].version->funcs->name); |
3598 | adev->ip_blocks[i].status.hw = true; | |
3599 | } | |
3600 | } | |
3601 | } else { | |
3602 | r = amdgpu_asic_reset(adev); | |
3603 | if (r) { | |
3604 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3605 | goto failed; | |
3606 | } | |
95e8e59e AD |
3607 | } |
3608 | } | |
3609 | ||
8f66090b | 3610 | pci_enable_pcie_error_reporting(adev->pdev); |
c9a6b82f | 3611 | |
d38ceaf9 | 3612 | /* Post card if necessary */ |
39c640c0 | 3613 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3614 | if (!adev->bios) { |
bec86378 | 3615 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3616 | r = -EINVAL; |
3617 | goto failed; | |
d38ceaf9 | 3618 | } |
bec86378 | 3619 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3620 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3621 | if (r) { |
3622 | dev_err(adev->dev, "gpu post error!\n"); | |
3623 | goto failed; | |
3624 | } | |
d38ceaf9 AD |
3625 | } |
3626 | ||
88b64e95 AD |
3627 | if (adev->is_atom_fw) { |
3628 | /* Initialize clocks */ | |
3629 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3630 | if (r) { | |
3631 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3632 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3633 | goto failed; |
3634 | } | |
3635 | } else { | |
a5bde2f9 AD |
3636 | /* Initialize clocks */ |
3637 | r = amdgpu_atombios_get_clock_info(adev); | |
3638 | if (r) { | |
3639 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3640 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3641 | goto failed; |
a5bde2f9 AD |
3642 | } |
3643 | /* init i2c buses */ | |
4562236b HW |
3644 | if (!amdgpu_device_has_dc_support(adev)) |
3645 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3646 | } |
d38ceaf9 | 3647 | |
bfca0289 | 3648 | fence_driver_init: |
d38ceaf9 AD |
3649 | /* Fence driver */ |
3650 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
3651 | if (r) { |
3652 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 3653 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3654 | goto failed; |
2c1a2784 | 3655 | } |
d38ceaf9 AD |
3656 | |
3657 | /* init the mode config */ | |
4a580877 | 3658 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3659 | |
06ec9070 | 3660 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3661 | if (r) { |
8840a387 | 3662 | /* failed in exclusive mode due to timeout */ |
3663 | if (amdgpu_sriov_vf(adev) && | |
3664 | !amdgpu_sriov_runtime(adev) && | |
3665 | amdgpu_virt_mmio_blocked(adev) && | |
3666 | !amdgpu_virt_wait_reset(adev)) { | |
3667 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3668 | /* Don't send request since VF is inactive. */ |
3669 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3670 | adev->virt.ops = NULL; | |
8840a387 | 3671 | r = -EAGAIN; |
970fd197 | 3672 | goto release_ras_con; |
8840a387 | 3673 | } |
06ec9070 | 3674 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3675 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 3676 | goto release_ras_con; |
d38ceaf9 AD |
3677 | } |
3678 | ||
8d35a259 LG |
3679 | amdgpu_fence_driver_hw_init(adev); |
3680 | ||
d69b8971 YZ |
3681 | dev_info(adev->dev, |
3682 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3683 | adev->gfx.config.max_shader_engines, |
3684 | adev->gfx.config.max_sh_per_se, | |
3685 | adev->gfx.config.max_cu_per_sh, | |
3686 | adev->gfx.cu_info.number); | |
3687 | ||
d38ceaf9 AD |
3688 | adev->accel_working = true; |
3689 | ||
e59c0205 AX |
3690 | amdgpu_vm_check_compute_bug(adev); |
3691 | ||
95844d20 MO |
3692 | /* Initialize the buffer migration limit. */ |
3693 | if (amdgpu_moverate >= 0) | |
3694 | max_MBps = amdgpu_moverate; | |
3695 | else | |
3696 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3697 | /* Get a log2 for easy divisions. */ | |
3698 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3699 | ||
9bc92b9c ML |
3700 | amdgpu_fbdev_init(adev); |
3701 | ||
d2f52ac8 | 3702 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3703 | if (r) { |
3704 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3705 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3706 | } else |
3707 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3708 | |
5bb23532 | 3709 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3710 | if (r) { |
3711 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3712 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3713 | } else |
3714 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3715 | |
d38ceaf9 AD |
3716 | if ((amdgpu_testing & 1)) { |
3717 | if (adev->accel_working) | |
3718 | amdgpu_test_moves(adev); | |
3719 | else | |
3720 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
3721 | } | |
d38ceaf9 AD |
3722 | if (amdgpu_benchmarking) { |
3723 | if (adev->accel_working) | |
3724 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
3725 | else | |
3726 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
3727 | } | |
3728 | ||
b0adca4d EQ |
3729 | /* |
3730 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3731 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3732 | * gpu instance is counted less. | |
3733 | */ | |
3734 | amdgpu_register_gpu_instance(adev); | |
3735 | ||
d38ceaf9 AD |
3736 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3737 | * explicit gating rather than handling it automatically. | |
3738 | */ | |
e3c1b071 | 3739 | if (!adev->gmc.xgmi.pending_reset) { |
3740 | r = amdgpu_device_ip_late_init(adev); | |
3741 | if (r) { | |
3742 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
3743 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 3744 | goto release_ras_con; |
e3c1b071 | 3745 | } |
3746 | /* must succeed. */ | |
3747 | amdgpu_ras_resume(adev); | |
3748 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
3749 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 3750 | } |
d38ceaf9 | 3751 | |
2c738637 ML |
3752 | if (amdgpu_sriov_vf(adev)) |
3753 | flush_delayed_work(&adev->delayed_init_work); | |
3754 | ||
77f3a5cd | 3755 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 3756 | if (r) |
77f3a5cd | 3757 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 3758 | |
d155bef0 AB |
3759 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3760 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3761 | if (r) |
3762 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3763 | ||
c1dd4aa6 AG |
3764 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
3765 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
3766 | pci_restore_state(pdev); | |
3767 | ||
8c3dd61c KHF |
3768 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3769 | /* this will fail for cards that aren't VGA class devices, just | |
3770 | * ignore it */ | |
3771 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) | |
bf44e8ce | 3772 | vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); |
8c3dd61c KHF |
3773 | |
3774 | if (amdgpu_device_supports_px(ddev)) { | |
3775 | px = true; | |
3776 | vga_switcheroo_register_client(adev->pdev, | |
3777 | &amdgpu_switcheroo_ops, px); | |
3778 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
3779 | } | |
3780 | ||
e3c1b071 | 3781 | if (adev->gmc.xgmi.pending_reset) |
3782 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
3783 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3784 | ||
d38ceaf9 | 3785 | return 0; |
83ba126a | 3786 | |
970fd197 SY |
3787 | release_ras_con: |
3788 | amdgpu_release_ras_context(adev); | |
3789 | ||
83ba126a | 3790 | failed: |
89041940 | 3791 | amdgpu_vf_error_trans_all(adev); |
8840a387 | 3792 | |
83ba126a | 3793 | return r; |
d38ceaf9 AD |
3794 | } |
3795 | ||
07775fc1 AG |
3796 | static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) |
3797 | { | |
3798 | /* Clear all CPU mappings pointing to this device */ | |
3799 | unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); | |
3800 | ||
3801 | /* Unmap all mapped bars - Doorbell, registers and VRAM */ | |
3802 | amdgpu_device_doorbell_fini(adev); | |
3803 | ||
3804 | iounmap(adev->rmmio); | |
3805 | adev->rmmio = NULL; | |
3806 | if (adev->mman.aper_base_kaddr) | |
3807 | iounmap(adev->mman.aper_base_kaddr); | |
3808 | adev->mman.aper_base_kaddr = NULL; | |
3809 | ||
3810 | /* Memory manager related */ | |
3811 | if (!adev->gmc.xgmi.connected_to_cpu) { | |
3812 | arch_phys_wc_del(adev->gmc.vram_mtrr); | |
3813 | arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); | |
3814 | } | |
3815 | } | |
3816 | ||
d38ceaf9 AD |
3817 | /** |
3818 | * amdgpu_device_fini - tear down the driver | |
3819 | * | |
3820 | * @adev: amdgpu_device pointer | |
3821 | * | |
3822 | * Tear down the driver info (all asics). | |
3823 | * Called at driver shutdown. | |
3824 | */ | |
72c8c97b | 3825 | void amdgpu_device_fini_hw(struct amdgpu_device *adev) |
d38ceaf9 | 3826 | { |
aac89168 | 3827 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3828 | flush_delayed_work(&adev->delayed_init_work); |
bb0cd09b | 3829 | ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); |
d0d13fe8 | 3830 | adev->shutdown = true; |
9f875167 | 3831 | |
752c683d ML |
3832 | /* make sure IB test finished before entering exclusive mode |
3833 | * to avoid preemption on IB test | |
3834 | * */ | |
519b8b76 | 3835 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 3836 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
3837 | amdgpu_virt_fini_data_exchange(adev); |
3838 | } | |
752c683d | 3839 | |
e5b03032 ML |
3840 | /* disable all interrupts */ |
3841 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
3842 | if (adev->mode_info.mode_config_initialized){ |
3843 | if (!amdgpu_device_has_dc_support(adev)) | |
4a580877 | 3844 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3845 | else |
4a580877 | 3846 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3847 | } |
8d35a259 | 3848 | amdgpu_fence_driver_hw_fini(adev); |
72c8c97b | 3849 | |
7c868b59 YT |
3850 | if (adev->pm_sysfs_en) |
3851 | amdgpu_pm_sysfs_fini(adev); | |
72c8c97b AG |
3852 | if (adev->ucode_sysfs_en) |
3853 | amdgpu_ucode_sysfs_fini(adev); | |
3854 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
3855 | ||
d38ceaf9 | 3856 | amdgpu_fbdev_fini(adev); |
72c8c97b AG |
3857 | |
3858 | amdgpu_irq_fini_hw(adev); | |
e9669fb7 AG |
3859 | |
3860 | amdgpu_device_ip_fini_early(adev); | |
d10d0daa AG |
3861 | |
3862 | amdgpu_gart_dummy_page_fini(adev); | |
07775fc1 AG |
3863 | |
3864 | amdgpu_device_unmap_mmio(adev); | |
72c8c97b AG |
3865 | } |
3866 | ||
3867 | void amdgpu_device_fini_sw(struct amdgpu_device *adev) | |
3868 | { | |
e230ac11 | 3869 | amdgpu_device_ip_fini(adev); |
8d35a259 | 3870 | amdgpu_fence_driver_sw_fini(adev); |
75e1658e ND |
3871 | release_firmware(adev->firmware.gpu_info_fw); |
3872 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 | 3873 | adev->accel_working = false; |
04442bf7 LL |
3874 | |
3875 | amdgpu_reset_fini(adev); | |
3876 | ||
d38ceaf9 | 3877 | /* free i2c buses */ |
4562236b HW |
3878 | if (!amdgpu_device_has_dc_support(adev)) |
3879 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3880 | |
3881 | if (amdgpu_emu_mode != 1) | |
3882 | amdgpu_atombios_fini(adev); | |
3883 | ||
d38ceaf9 AD |
3884 | kfree(adev->bios); |
3885 | adev->bios = NULL; | |
b98c6299 | 3886 | if (amdgpu_device_supports_px(adev_to_drm(adev))) { |
84c8b22e | 3887 | vga_switcheroo_unregister_client(adev->pdev); |
83ba126a | 3888 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
b98c6299 | 3889 | } |
38d6be81 | 3890 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
b8779475 | 3891 | vga_client_unregister(adev->pdev); |
e9bc1bf7 | 3892 | |
d155bef0 AB |
3893 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3894 | amdgpu_pmu_fini(adev); | |
72de33f8 | 3895 | if (adev->mman.discovery_bin) |
a190d1c7 | 3896 | amdgpu_discovery_fini(adev); |
72c8c97b AG |
3897 | |
3898 | kfree(adev->pci_state); | |
3899 | ||
d38ceaf9 AD |
3900 | } |
3901 | ||
3902 | ||
3903 | /* | |
3904 | * Suspend & resume. | |
3905 | */ | |
3906 | /** | |
810ddc3a | 3907 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3908 | * |
87e3f136 | 3909 | * @dev: drm dev pointer |
87e3f136 | 3910 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
3911 | * |
3912 | * Puts the hw in the suspend state (all asics). | |
3913 | * Returns 0 for success or an error on failure. | |
3914 | * Called at driver suspend. | |
3915 | */ | |
de185019 | 3916 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 3917 | { |
a2e15b0e | 3918 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 3919 | |
d38ceaf9 AD |
3920 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
3921 | return 0; | |
3922 | ||
44779b43 | 3923 | adev->in_suspend = true; |
3fa8f89d S |
3924 | |
3925 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3)) | |
3926 | DRM_WARN("smart shift update failed\n"); | |
3927 | ||
d38ceaf9 AD |
3928 | drm_kms_helper_poll_disable(dev); |
3929 | ||
5f818173 S |
3930 | if (fbcon) |
3931 | amdgpu_fbdev_set_suspend(adev, 1); | |
3932 | ||
beff74bc | 3933 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3934 | |
5e6932fe | 3935 | amdgpu_ras_suspend(adev); |
3936 | ||
2196927b | 3937 | amdgpu_device_ip_suspend_phase1(adev); |
fe1053b7 | 3938 | |
5d3a2d95 AD |
3939 | if (!adev->in_s0ix) |
3940 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); | |
94fa5660 | 3941 | |
d38ceaf9 AD |
3942 | /* evict vram memory */ |
3943 | amdgpu_bo_evict_vram(adev); | |
3944 | ||
8d35a259 | 3945 | amdgpu_fence_driver_hw_fini(adev); |
d38ceaf9 | 3946 | |
2196927b | 3947 | amdgpu_device_ip_suspend_phase2(adev); |
a0a71e49 AD |
3948 | /* evict remaining vram memory |
3949 | * This second call to evict vram is to evict the gart page table | |
3950 | * using the CPU. | |
3951 | */ | |
d38ceaf9 AD |
3952 | amdgpu_bo_evict_vram(adev); |
3953 | ||
d38ceaf9 AD |
3954 | return 0; |
3955 | } | |
3956 | ||
3957 | /** | |
810ddc3a | 3958 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 3959 | * |
87e3f136 | 3960 | * @dev: drm dev pointer |
87e3f136 | 3961 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
3962 | * |
3963 | * Bring the hw back to operating state (all asics). | |
3964 | * Returns 0 for success or an error on failure. | |
3965 | * Called at driver resume. | |
3966 | */ | |
de185019 | 3967 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 3968 | { |
1348969a | 3969 | struct amdgpu_device *adev = drm_to_adev(dev); |
03161a6e | 3970 | int r = 0; |
d38ceaf9 AD |
3971 | |
3972 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3973 | return 0; | |
3974 | ||
62498733 | 3975 | if (adev->in_s0ix) |
628c36d7 PL |
3976 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry); |
3977 | ||
d38ceaf9 | 3978 | /* post card */ |
39c640c0 | 3979 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 3980 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 3981 | if (r) |
aac89168 | 3982 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 3983 | } |
d38ceaf9 | 3984 | |
06ec9070 | 3985 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 3986 | if (r) { |
aac89168 | 3987 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 3988 | return r; |
e6707218 | 3989 | } |
8d35a259 | 3990 | amdgpu_fence_driver_hw_init(adev); |
5ceb54c6 | 3991 | |
d38ceaf9 | 3992 | |
06ec9070 | 3993 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 3994 | if (r) |
4d3b9ae5 | 3995 | return r; |
d38ceaf9 | 3996 | |
beff74bc AD |
3997 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3998 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3999 | ||
5d3a2d95 AD |
4000 | if (!adev->in_s0ix) { |
4001 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); | |
4002 | if (r) | |
4003 | return r; | |
4004 | } | |
756e6880 | 4005 | |
96a5d8d4 | 4006 | /* Make sure IB tests flushed */ |
beff74bc | 4007 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 4008 | |
a2e15b0e | 4009 | if (fbcon) |
4d3b9ae5 | 4010 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
4011 | |
4012 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 4013 | |
5e6932fe | 4014 | amdgpu_ras_resume(adev); |
4015 | ||
23a1a9e5 L |
4016 | /* |
4017 | * Most of the connector probing functions try to acquire runtime pm | |
4018 | * refs to ensure that the GPU is powered on when connector polling is | |
4019 | * performed. Since we're calling this from a runtime PM callback, | |
4020 | * trying to acquire rpm refs will cause us to deadlock. | |
4021 | * | |
4022 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
4023 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
4024 | */ | |
4025 | #ifdef CONFIG_PM | |
4026 | dev->dev->power.disable_depth++; | |
4027 | #endif | |
4562236b HW |
4028 | if (!amdgpu_device_has_dc_support(adev)) |
4029 | drm_helper_hpd_irq_event(dev); | |
4030 | else | |
4031 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
4032 | #ifdef CONFIG_PM |
4033 | dev->dev->power.disable_depth--; | |
4034 | #endif | |
44779b43 RZ |
4035 | adev->in_suspend = false; |
4036 | ||
3fa8f89d S |
4037 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0)) |
4038 | DRM_WARN("smart shift update failed\n"); | |
4039 | ||
4d3b9ae5 | 4040 | return 0; |
d38ceaf9 AD |
4041 | } |
4042 | ||
e3ecdffa AD |
4043 | /** |
4044 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
4045 | * | |
4046 | * @adev: amdgpu_device pointer | |
4047 | * | |
4048 | * The list of all the hardware IPs that make up the asic is walked and | |
4049 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
4050 | * if the asic is still hung or not. | |
4051 | * Returns true if any of the IPs are still in a hung state, false if not. | |
4052 | */ | |
06ec9070 | 4053 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
4054 | { |
4055 | int i; | |
4056 | bool asic_hang = false; | |
4057 | ||
f993d628 ML |
4058 | if (amdgpu_sriov_vf(adev)) |
4059 | return true; | |
4060 | ||
8bc04c29 AD |
4061 | if (amdgpu_asic_need_full_reset(adev)) |
4062 | return true; | |
4063 | ||
63fbf42f | 4064 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4065 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 4066 | continue; |
a1255107 AD |
4067 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
4068 | adev->ip_blocks[i].status.hang = | |
4069 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
4070 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 4071 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
4072 | asic_hang = true; |
4073 | } | |
4074 | } | |
4075 | return asic_hang; | |
4076 | } | |
4077 | ||
e3ecdffa AD |
4078 | /** |
4079 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
4080 | * | |
4081 | * @adev: amdgpu_device pointer | |
4082 | * | |
4083 | * The list of all the hardware IPs that make up the asic is walked and the | |
4084 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
4085 | * handles any IP specific hardware or software state changes that are | |
4086 | * necessary for a soft reset to succeed. | |
4087 | * Returns 0 on success, negative error code on failure. | |
4088 | */ | |
06ec9070 | 4089 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
4090 | { |
4091 | int i, r = 0; | |
4092 | ||
4093 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4094 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 4095 | continue; |
a1255107 AD |
4096 | if (adev->ip_blocks[i].status.hang && |
4097 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
4098 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
4099 | if (r) |
4100 | return r; | |
4101 | } | |
4102 | } | |
4103 | ||
4104 | return 0; | |
4105 | } | |
4106 | ||
e3ecdffa AD |
4107 | /** |
4108 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
4109 | * | |
4110 | * @adev: amdgpu_device pointer | |
4111 | * | |
4112 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
4113 | * reset is necessary to recover. | |
4114 | * Returns true if a full asic reset is required, false if not. | |
4115 | */ | |
06ec9070 | 4116 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 4117 | { |
da146d3b AD |
4118 | int i; |
4119 | ||
8bc04c29 AD |
4120 | if (amdgpu_asic_need_full_reset(adev)) |
4121 | return true; | |
4122 | ||
da146d3b | 4123 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4124 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 4125 | continue; |
a1255107 AD |
4126 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
4127 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
4128 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
4129 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
4130 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 4131 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 4132 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
4133 | return true; |
4134 | } | |
4135 | } | |
35d782fe CZ |
4136 | } |
4137 | return false; | |
4138 | } | |
4139 | ||
e3ecdffa AD |
4140 | /** |
4141 | * amdgpu_device_ip_soft_reset - do a soft reset | |
4142 | * | |
4143 | * @adev: amdgpu_device pointer | |
4144 | * | |
4145 | * The list of all the hardware IPs that make up the asic is walked and the | |
4146 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
4147 | * IP specific hardware or software state changes that are necessary to soft | |
4148 | * reset the IP. | |
4149 | * Returns 0 on success, negative error code on failure. | |
4150 | */ | |
06ec9070 | 4151 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4152 | { |
4153 | int i, r = 0; | |
4154 | ||
4155 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4156 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4157 | continue; |
a1255107 AD |
4158 | if (adev->ip_blocks[i].status.hang && |
4159 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
4160 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
4161 | if (r) |
4162 | return r; | |
4163 | } | |
4164 | } | |
4165 | ||
4166 | return 0; | |
4167 | } | |
4168 | ||
e3ecdffa AD |
4169 | /** |
4170 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
4171 | * | |
4172 | * @adev: amdgpu_device pointer | |
4173 | * | |
4174 | * The list of all the hardware IPs that make up the asic is walked and the | |
4175 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
4176 | * handles any IP specific hardware or software state changes that are | |
4177 | * necessary after the IP has been soft reset. | |
4178 | * Returns 0 on success, negative error code on failure. | |
4179 | */ | |
06ec9070 | 4180 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4181 | { |
4182 | int i, r = 0; | |
4183 | ||
4184 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4185 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4186 | continue; |
a1255107 AD |
4187 | if (adev->ip_blocks[i].status.hang && |
4188 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
4189 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
4190 | if (r) |
4191 | return r; | |
4192 | } | |
4193 | ||
4194 | return 0; | |
4195 | } | |
4196 | ||
e3ecdffa | 4197 | /** |
c33adbc7 | 4198 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4199 | * |
4200 | * @adev: amdgpu_device pointer | |
4201 | * | |
4202 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4203 | * restore things like GPUVM page tables after a GPU reset where | |
4204 | * the contents of VRAM might be lost. | |
403009bf CK |
4205 | * |
4206 | * Returns: | |
4207 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4208 | */ |
c33adbc7 | 4209 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4210 | { |
c41d1cf6 | 4211 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf | 4212 | struct amdgpu_bo *shadow; |
e18aaea7 | 4213 | struct amdgpu_bo_vm *vmbo; |
403009bf | 4214 | long r = 1, tmo; |
c41d1cf6 ML |
4215 | |
4216 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4217 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4218 | else |
4219 | tmo = msecs_to_jiffies(100); | |
4220 | ||
aac89168 | 4221 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4222 | mutex_lock(&adev->shadow_list_lock); |
e18aaea7 ND |
4223 | list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { |
4224 | shadow = &vmbo->bo; | |
403009bf | 4225 | /* No need to recover an evicted BO */ |
d3116756 CK |
4226 | if (shadow->tbo.resource->mem_type != TTM_PL_TT || |
4227 | shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || | |
4228 | shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) | |
403009bf CK |
4229 | continue; |
4230 | ||
4231 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4232 | if (r) | |
4233 | break; | |
4234 | ||
c41d1cf6 | 4235 | if (fence) { |
1712fb1a | 4236 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4237 | dma_fence_put(fence); |
4238 | fence = next; | |
1712fb1a | 4239 | if (tmo == 0) { |
4240 | r = -ETIMEDOUT; | |
c41d1cf6 | 4241 | break; |
1712fb1a | 4242 | } else if (tmo < 0) { |
4243 | r = tmo; | |
4244 | break; | |
4245 | } | |
403009bf CK |
4246 | } else { |
4247 | fence = next; | |
c41d1cf6 | 4248 | } |
c41d1cf6 ML |
4249 | } |
4250 | mutex_unlock(&adev->shadow_list_lock); | |
4251 | ||
403009bf CK |
4252 | if (fence) |
4253 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4254 | dma_fence_put(fence); |
4255 | ||
1712fb1a | 4256 | if (r < 0 || tmo <= 0) { |
aac89168 | 4257 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4258 | return -EIO; |
4259 | } | |
c41d1cf6 | 4260 | |
aac89168 | 4261 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4262 | return 0; |
c41d1cf6 ML |
4263 | } |
4264 | ||
a90ad3c2 | 4265 | |
e3ecdffa | 4266 | /** |
06ec9070 | 4267 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4268 | * |
982a820b | 4269 | * @adev: amdgpu_device pointer |
87e3f136 | 4270 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4271 | * |
4272 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4273 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4274 | */ |
4275 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4276 | bool from_hypervisor) | |
5740682e ML |
4277 | { |
4278 | int r; | |
4279 | ||
4280 | if (from_hypervisor) | |
4281 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4282 | else | |
4283 | r = amdgpu_virt_reset_gpu(adev); | |
4284 | if (r) | |
4285 | return r; | |
a90ad3c2 | 4286 | |
b639c22c JZ |
4287 | amdgpu_amdkfd_pre_reset(adev); |
4288 | ||
a90ad3c2 | 4289 | /* Resume IP prior to SMC */ |
06ec9070 | 4290 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4291 | if (r) |
4292 | goto error; | |
a90ad3c2 | 4293 | |
c9ffa427 | 4294 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4295 | /* we need recover gart prior to run SMC/CP/SDMA resume */ |
6c28aed6 | 4296 | amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); |
a90ad3c2 | 4297 | |
7a3e0bb2 RZ |
4298 | r = amdgpu_device_fw_loading(adev); |
4299 | if (r) | |
4300 | return r; | |
4301 | ||
a90ad3c2 | 4302 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4303 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4304 | if (r) |
4305 | goto error; | |
a90ad3c2 ML |
4306 | |
4307 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 4308 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 4309 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 4310 | |
abc34253 | 4311 | error: |
c41d1cf6 | 4312 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 4313 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 4314 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 | 4315 | } |
437f3e0b | 4316 | amdgpu_virt_release_full_gpu(adev, true); |
a90ad3c2 ML |
4317 | |
4318 | return r; | |
4319 | } | |
4320 | ||
9a1cddd6 | 4321 | /** |
4322 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
4323 | * | |
982a820b | 4324 | * @adev: amdgpu_device pointer |
9a1cddd6 | 4325 | * |
4326 | * check if there is any job in mirror list | |
4327 | */ | |
4328 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
4329 | { | |
4330 | int i; | |
4331 | struct drm_sched_job *job; | |
4332 | ||
4333 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4334 | struct amdgpu_ring *ring = adev->rings[i]; | |
4335 | ||
4336 | if (!ring || !ring->sched.thread) | |
4337 | continue; | |
4338 | ||
4339 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
4340 | job = list_first_entry_or_null(&ring->sched.pending_list, |
4341 | struct drm_sched_job, list); | |
9a1cddd6 | 4342 | spin_unlock(&ring->sched.job_list_lock); |
4343 | if (job) | |
4344 | return true; | |
4345 | } | |
4346 | return false; | |
4347 | } | |
4348 | ||
12938fad CK |
4349 | /** |
4350 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
4351 | * | |
982a820b | 4352 | * @adev: amdgpu_device pointer |
12938fad CK |
4353 | * |
4354 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
4355 | * a hung GPU. | |
4356 | */ | |
4357 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
4358 | { | |
4359 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4360 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
4361 | return false; |
4362 | } | |
4363 | ||
3ba7b418 AG |
4364 | if (amdgpu_gpu_recovery == 0) |
4365 | goto disabled; | |
4366 | ||
4367 | if (amdgpu_sriov_vf(adev)) | |
4368 | return true; | |
4369 | ||
4370 | if (amdgpu_gpu_recovery == -1) { | |
4371 | switch (adev->asic_type) { | |
fc42d47c AG |
4372 | case CHIP_BONAIRE: |
4373 | case CHIP_HAWAII: | |
3ba7b418 AG |
4374 | case CHIP_TOPAZ: |
4375 | case CHIP_TONGA: | |
4376 | case CHIP_FIJI: | |
4377 | case CHIP_POLARIS10: | |
4378 | case CHIP_POLARIS11: | |
4379 | case CHIP_POLARIS12: | |
4380 | case CHIP_VEGAM: | |
4381 | case CHIP_VEGA20: | |
4382 | case CHIP_VEGA10: | |
4383 | case CHIP_VEGA12: | |
c43b849f | 4384 | case CHIP_RAVEN: |
e9d4cf91 | 4385 | case CHIP_ARCTURUS: |
2cb44fb0 | 4386 | case CHIP_RENOIR: |
658c6639 AD |
4387 | case CHIP_NAVI10: |
4388 | case CHIP_NAVI14: | |
4389 | case CHIP_NAVI12: | |
131a3c74 | 4390 | case CHIP_SIENNA_CICHLID: |
665fe4dc | 4391 | case CHIP_NAVY_FLOUNDER: |
27859ee3 | 4392 | case CHIP_DIMGREY_CAVEFISH: |
a2f55040 | 4393 | case CHIP_BEIGE_GOBY: |
fe68ceef | 4394 | case CHIP_VANGOGH: |
ea4e96a7 | 4395 | case CHIP_ALDEBARAN: |
3ba7b418 AG |
4396 | break; |
4397 | default: | |
4398 | goto disabled; | |
4399 | } | |
12938fad CK |
4400 | } |
4401 | ||
4402 | return true; | |
3ba7b418 AG |
4403 | |
4404 | disabled: | |
aac89168 | 4405 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4406 | return false; |
12938fad CK |
4407 | } |
4408 | ||
5c03e584 FX |
4409 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
4410 | { | |
4411 | u32 i; | |
4412 | int ret = 0; | |
4413 | ||
4414 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
4415 | ||
4416 | dev_info(adev->dev, "GPU mode1 reset\n"); | |
4417 | ||
4418 | /* disable BM */ | |
4419 | pci_clear_master(adev->pdev); | |
4420 | ||
4421 | amdgpu_device_cache_pci_state(adev->pdev); | |
4422 | ||
4423 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
4424 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
4425 | ret = amdgpu_dpm_mode1_reset(adev); | |
4426 | } else { | |
4427 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
4428 | ret = psp_gpu_reset(adev); | |
4429 | } | |
4430 | ||
4431 | if (ret) | |
4432 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
4433 | ||
4434 | amdgpu_device_load_pci_state(adev->pdev); | |
4435 | ||
4436 | /* wait for asic to come out of reset */ | |
4437 | for (i = 0; i < adev->usec_timeout; i++) { | |
4438 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
4439 | ||
4440 | if (memsize != 0xffffffff) | |
4441 | break; | |
4442 | udelay(1); | |
4443 | } | |
4444 | ||
4445 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
4446 | return ret; | |
4447 | } | |
5c6dd71e | 4448 | |
e3c1b071 | 4449 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
04442bf7 | 4450 | struct amdgpu_reset_context *reset_context) |
26bc5340 AG |
4451 | { |
4452 | int i, r = 0; | |
04442bf7 LL |
4453 | struct amdgpu_job *job = NULL; |
4454 | bool need_full_reset = | |
4455 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4456 | ||
4457 | if (reset_context->reset_req_dev == adev) | |
4458 | job = reset_context->job; | |
71182665 | 4459 | |
e3c1b071 | 4460 | /* no need to dump if device is not in good state during probe period */ |
4461 | if (!adev->gmc.xgmi.pending_reset) | |
4462 | amdgpu_debugfs_wait_dump(adev); | |
728e7e0c | 4463 | |
b602ca5f TZ |
4464 | if (amdgpu_sriov_vf(adev)) { |
4465 | /* stop the data exchange thread */ | |
4466 | amdgpu_virt_fini_data_exchange(adev); | |
4467 | } | |
4468 | ||
71182665 | 4469 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4470 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4471 | struct amdgpu_ring *ring = adev->rings[i]; | |
4472 | ||
51687759 | 4473 | if (!ring || !ring->sched.thread) |
0875dc9e | 4474 | continue; |
5740682e | 4475 | |
2f9d4084 ML |
4476 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4477 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4478 | } |
d38ceaf9 | 4479 | |
ff99849b | 4480 | if (job && job->vm) |
222b5f04 AG |
4481 | drm_sched_increase_karma(&job->base); |
4482 | ||
04442bf7 | 4483 | r = amdgpu_reset_prepare_hwcontext(adev, reset_context); |
404b277b LL |
4484 | /* If reset handler not implemented, continue; otherwise return */ |
4485 | if (r == -ENOSYS) | |
4486 | r = 0; | |
4487 | else | |
04442bf7 LL |
4488 | return r; |
4489 | ||
1d721ed6 | 4490 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4491 | if (!amdgpu_sriov_vf(adev)) { |
4492 | ||
4493 | if (!need_full_reset) | |
4494 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4495 | ||
4496 | if (!need_full_reset) { | |
4497 | amdgpu_device_ip_pre_soft_reset(adev); | |
4498 | r = amdgpu_device_ip_soft_reset(adev); | |
4499 | amdgpu_device_ip_post_soft_reset(adev); | |
4500 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4501 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4502 | need_full_reset = true; |
4503 | } | |
4504 | } | |
4505 | ||
4506 | if (need_full_reset) | |
4507 | r = amdgpu_device_ip_suspend(adev); | |
04442bf7 LL |
4508 | if (need_full_reset) |
4509 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4510 | else | |
4511 | clear_bit(AMDGPU_NEED_FULL_RESET, | |
4512 | &reset_context->flags); | |
26bc5340 AG |
4513 | } |
4514 | ||
4515 | return r; | |
4516 | } | |
4517 | ||
04442bf7 LL |
4518 | int amdgpu_do_asic_reset(struct list_head *device_list_handle, |
4519 | struct amdgpu_reset_context *reset_context) | |
26bc5340 AG |
4520 | { |
4521 | struct amdgpu_device *tmp_adev = NULL; | |
04442bf7 | 4522 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
26bc5340 AG |
4523 | int r = 0; |
4524 | ||
04442bf7 LL |
4525 | /* Try reset handler method first */ |
4526 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
4527 | reset_list); | |
4528 | r = amdgpu_reset_perform_reset(tmp_adev, reset_context); | |
404b277b LL |
4529 | /* If reset handler not implemented, continue; otherwise return */ |
4530 | if (r == -ENOSYS) | |
4531 | r = 0; | |
4532 | else | |
04442bf7 LL |
4533 | return r; |
4534 | ||
4535 | /* Reset handler not implemented, use the default method */ | |
4536 | need_full_reset = | |
4537 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4538 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); | |
4539 | ||
26bc5340 | 4540 | /* |
655ce9cb | 4541 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
4542 | * to allow proper links negotiation in FW (within 1 sec) |
4543 | */ | |
7ac71382 | 4544 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 4545 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 4546 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4547 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 4548 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 4549 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4550 | r = -EALREADY; |
4551 | } else | |
4552 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4553 | |
041a62bc | 4554 | if (r) { |
aac89168 | 4555 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4556 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4557 | break; |
ce316fa5 LM |
4558 | } |
4559 | } | |
4560 | ||
041a62bc AG |
4561 | /* For XGMI wait for all resets to complete before proceed */ |
4562 | if (!r) { | |
655ce9cb | 4563 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
4564 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
4565 | flush_work(&tmp_adev->xgmi_reset_work); | |
4566 | r = tmp_adev->asic_reset_res; | |
4567 | if (r) | |
4568 | break; | |
ce316fa5 LM |
4569 | } |
4570 | } | |
4571 | } | |
ce316fa5 | 4572 | } |
26bc5340 | 4573 | |
43c4d576 | 4574 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 4575 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8bc7b360 HZ |
4576 | if (tmp_adev->mmhub.ras_funcs && |
4577 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count) | |
4578 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count(tmp_adev); | |
43c4d576 JC |
4579 | } |
4580 | ||
00eaa571 | 4581 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4582 | } |
00eaa571 | 4583 | |
655ce9cb | 4584 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
4585 | if (need_full_reset) { |
4586 | /* post card */ | |
e3c1b071 | 4587 | r = amdgpu_device_asic_init(tmp_adev); |
4588 | if (r) { | |
aac89168 | 4589 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 4590 | } else { |
26bc5340 AG |
4591 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
4592 | r = amdgpu_device_ip_resume_phase1(tmp_adev); | |
4593 | if (r) | |
4594 | goto out; | |
4595 | ||
4596 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
4597 | if (vram_lost) { | |
77e7f829 | 4598 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4599 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4600 | } |
4601 | ||
6c28aed6 | 4602 | r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT)); |
26bc5340 AG |
4603 | if (r) |
4604 | goto out; | |
4605 | ||
4606 | r = amdgpu_device_fw_loading(tmp_adev); | |
4607 | if (r) | |
4608 | return r; | |
4609 | ||
4610 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4611 | if (r) | |
4612 | goto out; | |
4613 | ||
4614 | if (vram_lost) | |
4615 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4616 | ||
fdafb359 EQ |
4617 | /* |
4618 | * Add this ASIC as tracked as reset was already | |
4619 | * complete successfully. | |
4620 | */ | |
4621 | amdgpu_register_gpu_instance(tmp_adev); | |
4622 | ||
04442bf7 LL |
4623 | if (!reset_context->hive && |
4624 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
e3c1b071 | 4625 | amdgpu_xgmi_add_device(tmp_adev); |
4626 | ||
7c04ca50 | 4627 | r = amdgpu_device_ip_late_init(tmp_adev); |
4628 | if (r) | |
4629 | goto out; | |
4630 | ||
565d1941 EQ |
4631 | amdgpu_fbdev_set_suspend(tmp_adev, 0); |
4632 | ||
e8fbaf03 GC |
4633 | /* |
4634 | * The GPU enters bad state once faulty pages | |
4635 | * by ECC has reached the threshold, and ras | |
4636 | * recovery is scheduled next. So add one check | |
4637 | * here to break recovery if it indeed exceeds | |
4638 | * bad page threshold, and remind user to | |
4639 | * retire this GPU or setting one bigger | |
4640 | * bad_page_threshold value to fix this once | |
4641 | * probing driver again. | |
4642 | */ | |
11003c68 | 4643 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
4644 | /* must succeed. */ |
4645 | amdgpu_ras_resume(tmp_adev); | |
4646 | } else { | |
4647 | r = -EINVAL; | |
4648 | goto out; | |
4649 | } | |
e79a04d5 | 4650 | |
26bc5340 | 4651 | /* Update PSP FW topology after reset */ |
04442bf7 LL |
4652 | if (reset_context->hive && |
4653 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4654 | r = amdgpu_xgmi_update_topology( | |
4655 | reset_context->hive, tmp_adev); | |
26bc5340 AG |
4656 | } |
4657 | } | |
4658 | ||
26bc5340 AG |
4659 | out: |
4660 | if (!r) { | |
4661 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4662 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4663 | if (r) { | |
4664 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
26bc5340 AG |
4665 | need_full_reset = true; |
4666 | r = -EAGAIN; | |
4667 | goto end; | |
4668 | } | |
4669 | } | |
4670 | ||
4671 | if (!r) | |
4672 | r = amdgpu_device_recover_vram(tmp_adev); | |
4673 | else | |
4674 | tmp_adev->asic_reset_res = r; | |
4675 | } | |
4676 | ||
4677 | end: | |
04442bf7 LL |
4678 | if (need_full_reset) |
4679 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4680 | else | |
4681 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 AG |
4682 | return r; |
4683 | } | |
4684 | ||
08ebb485 DL |
4685 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, |
4686 | struct amdgpu_hive_info *hive) | |
26bc5340 | 4687 | { |
53b3f8f4 DL |
4688 | if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0) |
4689 | return false; | |
4690 | ||
08ebb485 DL |
4691 | if (hive) { |
4692 | down_write_nest_lock(&adev->reset_sem, &hive->hive_lock); | |
4693 | } else { | |
4694 | down_write(&adev->reset_sem); | |
4695 | } | |
5740682e | 4696 | |
a3a09142 AD |
4697 | switch (amdgpu_asic_reset_method(adev)) { |
4698 | case AMD_RESET_METHOD_MODE1: | |
4699 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4700 | break; | |
4701 | case AMD_RESET_METHOD_MODE2: | |
4702 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4703 | break; | |
4704 | default: | |
4705 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4706 | break; | |
4707 | } | |
1d721ed6 AG |
4708 | |
4709 | return true; | |
26bc5340 | 4710 | } |
d38ceaf9 | 4711 | |
26bc5340 AG |
4712 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
4713 | { | |
89041940 | 4714 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4715 | adev->mp1_state = PP_MP1_STATE_NONE; |
53b3f8f4 | 4716 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 4717 | up_write(&adev->reset_sem); |
26bc5340 AG |
4718 | } |
4719 | ||
91fb309d HC |
4720 | /* |
4721 | * to lockup a list of amdgpu devices in a hive safely, if not a hive | |
4722 | * with multiple nodes, it will be similar as amdgpu_device_lock_adev. | |
4723 | * | |
4724 | * unlock won't require roll back. | |
4725 | */ | |
4726 | static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive) | |
4727 | { | |
4728 | struct amdgpu_device *tmp_adev = NULL; | |
4729 | ||
4730 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
4731 | if (!hive) { | |
4732 | dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes"); | |
4733 | return -ENODEV; | |
4734 | } | |
4735 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4736 | if (!amdgpu_device_lock_adev(tmp_adev, hive)) | |
4737 | goto roll_back; | |
4738 | } | |
4739 | } else if (!amdgpu_device_lock_adev(adev, hive)) | |
4740 | return -EAGAIN; | |
4741 | ||
4742 | return 0; | |
4743 | roll_back: | |
4744 | if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) { | |
4745 | /* | |
4746 | * if the lockup iteration break in the middle of a hive, | |
4747 | * it may means there may has a race issue, | |
4748 | * or a hive device locked up independently. | |
4749 | * we may be in trouble and may not, so will try to roll back | |
4750 | * the lock and give out a warnning. | |
4751 | */ | |
4752 | dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock"); | |
4753 | list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4754 | amdgpu_device_unlock_adev(tmp_adev); | |
4755 | } | |
4756 | } | |
4757 | return -EAGAIN; | |
4758 | } | |
4759 | ||
3f12acc8 EQ |
4760 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4761 | { | |
4762 | struct pci_dev *p = NULL; | |
4763 | ||
4764 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4765 | adev->pdev->bus->number, 1); | |
4766 | if (p) { | |
4767 | pm_runtime_enable(&(p->dev)); | |
4768 | pm_runtime_resume(&(p->dev)); | |
4769 | } | |
4770 | } | |
4771 | ||
4772 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4773 | { | |
4774 | enum amd_reset_method reset_method; | |
4775 | struct pci_dev *p = NULL; | |
4776 | u64 expires; | |
4777 | ||
4778 | /* | |
4779 | * For now, only BACO and mode1 reset are confirmed | |
4780 | * to suffer the audio issue without proper suspended. | |
4781 | */ | |
4782 | reset_method = amdgpu_asic_reset_method(adev); | |
4783 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4784 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4785 | return -EINVAL; | |
4786 | ||
4787 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4788 | adev->pdev->bus->number, 1); | |
4789 | if (!p) | |
4790 | return -ENODEV; | |
4791 | ||
4792 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4793 | if (!expires) | |
4794 | /* | |
4795 | * If we cannot get the audio device autosuspend delay, | |
4796 | * a fixed 4S interval will be used. Considering 3S is | |
4797 | * the audio controller default autosuspend delay setting. | |
4798 | * 4S used here is guaranteed to cover that. | |
4799 | */ | |
54b7feb9 | 4800 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4801 | |
4802 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4803 | if (!pm_runtime_suspend(&(p->dev))) | |
4804 | break; | |
4805 | ||
4806 | if (expires < ktime_get_mono_fast_ns()) { | |
4807 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4808 | /* TODO: abort the succeeding gpu reset? */ | |
4809 | return -ETIMEDOUT; | |
4810 | } | |
4811 | } | |
4812 | ||
4813 | pm_runtime_disable(&(p->dev)); | |
4814 | ||
4815 | return 0; | |
4816 | } | |
4817 | ||
9d8d96be | 4818 | static void amdgpu_device_recheck_guilty_jobs( |
04442bf7 LL |
4819 | struct amdgpu_device *adev, struct list_head *device_list_handle, |
4820 | struct amdgpu_reset_context *reset_context) | |
e6c6338f JZ |
4821 | { |
4822 | int i, r = 0; | |
4823 | ||
4824 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4825 | struct amdgpu_ring *ring = adev->rings[i]; | |
4826 | int ret = 0; | |
4827 | struct drm_sched_job *s_job; | |
4828 | ||
4829 | if (!ring || !ring->sched.thread) | |
4830 | continue; | |
4831 | ||
4832 | s_job = list_first_entry_or_null(&ring->sched.pending_list, | |
4833 | struct drm_sched_job, list); | |
4834 | if (s_job == NULL) | |
4835 | continue; | |
4836 | ||
4837 | /* clear job's guilty and depend the folowing step to decide the real one */ | |
4838 | drm_sched_reset_karma(s_job); | |
4839 | drm_sched_resubmit_jobs_ext(&ring->sched, 1); | |
4840 | ||
4841 | ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout); | |
4842 | if (ret == 0) { /* timeout */ | |
4843 | DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n", | |
4844 | ring->sched.name, s_job->id); | |
4845 | ||
4846 | /* set guilty */ | |
4847 | drm_sched_increase_karma(s_job); | |
4848 | retry: | |
4849 | /* do hw reset */ | |
4850 | if (amdgpu_sriov_vf(adev)) { | |
4851 | amdgpu_virt_fini_data_exchange(adev); | |
4852 | r = amdgpu_device_reset_sriov(adev, false); | |
4853 | if (r) | |
4854 | adev->asic_reset_res = r; | |
4855 | } else { | |
04442bf7 LL |
4856 | clear_bit(AMDGPU_SKIP_HW_RESET, |
4857 | &reset_context->flags); | |
4858 | r = amdgpu_do_asic_reset(device_list_handle, | |
4859 | reset_context); | |
e6c6338f JZ |
4860 | if (r && r == -EAGAIN) |
4861 | goto retry; | |
4862 | } | |
4863 | ||
4864 | /* | |
4865 | * add reset counter so that the following | |
4866 | * resubmitted job could flush vmid | |
4867 | */ | |
4868 | atomic_inc(&adev->gpu_reset_counter); | |
4869 | continue; | |
4870 | } | |
4871 | ||
4872 | /* got the hw fence, signal finished fence */ | |
4873 | atomic_dec(ring->sched.score); | |
4874 | dma_fence_get(&s_job->s_fence->finished); | |
4875 | dma_fence_signal(&s_job->s_fence->finished); | |
4876 | dma_fence_put(&s_job->s_fence->finished); | |
4877 | ||
4878 | /* remove node from list and free the job */ | |
4879 | spin_lock(&ring->sched.job_list_lock); | |
4880 | list_del_init(&s_job->list); | |
4881 | spin_unlock(&ring->sched.job_list_lock); | |
4882 | ring->sched.ops->free_job(s_job); | |
4883 | } | |
4884 | } | |
4885 | ||
26bc5340 AG |
4886 | /** |
4887 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
4888 | * | |
982a820b | 4889 | * @adev: amdgpu_device pointer |
26bc5340 AG |
4890 | * @job: which job trigger hang |
4891 | * | |
4892 | * Attempt to reset the GPU if it has hung (all asics). | |
4893 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
4894 | * Returns 0 for success or an error on failure. | |
4895 | */ | |
4896 | ||
4897 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
4898 | struct amdgpu_job *job) | |
4899 | { | |
1d721ed6 | 4900 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 | 4901 | bool job_signaled = false; |
26bc5340 | 4902 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 4903 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 4904 | int i, r = 0; |
bb5c7235 | 4905 | bool need_emergency_restart = false; |
3f12acc8 | 4906 | bool audio_suspended = false; |
e6c6338f | 4907 | int tmp_vram_lost_counter; |
04442bf7 LL |
4908 | struct amdgpu_reset_context reset_context; |
4909 | ||
4910 | memset(&reset_context, 0, sizeof(reset_context)); | |
26bc5340 | 4911 | |
6e3cd2a9 | 4912 | /* |
bb5c7235 WS |
4913 | * Special case: RAS triggered and full reset isn't supported |
4914 | */ | |
4915 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
4916 | ||
d5ea093e AG |
4917 | /* |
4918 | * Flush RAM to disk so that after reboot | |
4919 | * the user can read log and see why the system rebooted. | |
4920 | */ | |
bb5c7235 | 4921 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
4922 | DRM_WARN("Emergency reboot."); |
4923 | ||
4924 | ksys_sync_helper(); | |
4925 | emergency_restart(); | |
4926 | } | |
4927 | ||
b823821f | 4928 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 4929 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 AG |
4930 | |
4931 | /* | |
1d721ed6 AG |
4932 | * Here we trylock to avoid chain of resets executing from |
4933 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
4934 | * different schedulers for same device while this TO handler is running. | |
4935 | * We always reset all schedulers for device and all devices for XGMI | |
4936 | * hive so that should take care of them too. | |
26bc5340 | 4937 | */ |
d95e8e97 | 4938 | hive = amdgpu_get_xgmi_hive(adev); |
53b3f8f4 DL |
4939 | if (hive) { |
4940 | if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) { | |
4941 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
4942 | job ? job->base.id : -1, hive->hive_id); | |
d95e8e97 | 4943 | amdgpu_put_xgmi_hive(hive); |
ff99849b | 4944 | if (job && job->vm) |
91fb309d | 4945 | drm_sched_increase_karma(&job->base); |
53b3f8f4 DL |
4946 | return 0; |
4947 | } | |
4948 | mutex_lock(&hive->hive_lock); | |
1d721ed6 | 4949 | } |
26bc5340 | 4950 | |
04442bf7 LL |
4951 | reset_context.method = AMD_RESET_METHOD_NONE; |
4952 | reset_context.reset_req_dev = adev; | |
4953 | reset_context.job = job; | |
4954 | reset_context.hive = hive; | |
4955 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
4956 | ||
91fb309d HC |
4957 | /* |
4958 | * lock the device before we try to operate the linked list | |
4959 | * if didn't get the device lock, don't touch the linked list since | |
4960 | * others may iterating it. | |
4961 | */ | |
4962 | r = amdgpu_device_lock_hive_adev(adev, hive); | |
4963 | if (r) { | |
4964 | dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress", | |
4965 | job ? job->base.id : -1); | |
4966 | ||
4967 | /* even we skipped this reset, still need to set the job to guilty */ | |
ff99849b | 4968 | if (job && job->vm) |
91fb309d HC |
4969 | drm_sched_increase_karma(&job->base); |
4970 | goto skip_recovery; | |
4971 | } | |
4972 | ||
9e94d22c EQ |
4973 | /* |
4974 | * Build list of devices to reset. | |
4975 | * In case we are in XGMI hive mode, resort the device list | |
4976 | * to put adev in the 1st position. | |
4977 | */ | |
4978 | INIT_LIST_HEAD(&device_list); | |
4979 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
655ce9cb | 4980 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) |
4981 | list_add_tail(&tmp_adev->reset_list, &device_list); | |
4982 | if (!list_is_first(&adev->reset_list, &device_list)) | |
4983 | list_rotate_to_front(&adev->reset_list, &device_list); | |
4984 | device_list_handle = &device_list; | |
26bc5340 | 4985 | } else { |
655ce9cb | 4986 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
4987 | device_list_handle = &device_list; |
4988 | } | |
4989 | ||
1d721ed6 | 4990 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 4991 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
3f12acc8 EQ |
4992 | /* |
4993 | * Try to put the audio codec into suspend state | |
4994 | * before gpu reset started. | |
4995 | * | |
4996 | * Due to the power domain of the graphics device | |
4997 | * is shared with AZ power domain. Without this, | |
4998 | * we may change the audio hardware from behind | |
4999 | * the audio driver's back. That will trigger | |
5000 | * some audio codec errors. | |
5001 | */ | |
5002 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
5003 | audio_suspended = true; | |
5004 | ||
9e94d22c EQ |
5005 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
5006 | ||
52fb44cf EQ |
5007 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
5008 | ||
9e94d22c EQ |
5009 | if (!amdgpu_sriov_vf(tmp_adev)) |
5010 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
5011 | ||
12ffa55d AG |
5012 | /* |
5013 | * Mark these ASICs to be reseted as untracked first | |
5014 | * And add them back after reset completed | |
5015 | */ | |
5016 | amdgpu_unregister_gpu_instance(tmp_adev); | |
5017 | ||
a2f63ee8 | 5018 | amdgpu_fbdev_set_suspend(tmp_adev, 1); |
565d1941 | 5019 | |
f1c1314b | 5020 | /* disable ras on ALL IPs */ |
bb5c7235 | 5021 | if (!need_emergency_restart && |
b823821f | 5022 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 5023 | amdgpu_ras_suspend(tmp_adev); |
5024 | ||
1d721ed6 AG |
5025 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5026 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5027 | ||
5028 | if (!ring || !ring->sched.thread) | |
5029 | continue; | |
5030 | ||
0b2d2c2e | 5031 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 5032 | |
bb5c7235 | 5033 | if (need_emergency_restart) |
7c6e68c7 | 5034 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 5035 | } |
8f8c80f4 | 5036 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
5037 | } |
5038 | ||
bb5c7235 | 5039 | if (need_emergency_restart) |
7c6e68c7 AG |
5040 | goto skip_sched_resume; |
5041 | ||
1d721ed6 AG |
5042 | /* |
5043 | * Must check guilty signal here since after this point all old | |
5044 | * HW fences are force signaled. | |
5045 | * | |
5046 | * job->base holds a reference to parent fence | |
5047 | */ | |
5048 | if (job && job->base.s_fence->parent && | |
7dd8c205 | 5049 | dma_fence_is_signaled(job->base.s_fence->parent)) { |
1d721ed6 | 5050 | job_signaled = true; |
1d721ed6 AG |
5051 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
5052 | goto skip_hw_reset; | |
5053 | } | |
5054 | ||
26bc5340 | 5055 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 5056 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
04442bf7 | 5057 | r = amdgpu_device_pre_asic_reset(tmp_adev, &reset_context); |
26bc5340 AG |
5058 | /*TODO Should we stop ?*/ |
5059 | if (r) { | |
aac89168 | 5060 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 5061 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
5062 | tmp_adev->asic_reset_res = r; |
5063 | } | |
5064 | } | |
5065 | ||
e6c6338f | 5066 | tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); |
26bc5340 AG |
5067 | /* Actual ASIC resets if needed.*/ |
5068 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
5069 | if (amdgpu_sriov_vf(adev)) { | |
5070 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
5071 | if (r) | |
5072 | adev->asic_reset_res = r; | |
5073 | } else { | |
04442bf7 | 5074 | r = amdgpu_do_asic_reset(device_list_handle, &reset_context); |
26bc5340 AG |
5075 | if (r && r == -EAGAIN) |
5076 | goto retry; | |
5077 | } | |
5078 | ||
1d721ed6 AG |
5079 | skip_hw_reset: |
5080 | ||
26bc5340 | 5081 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 5082 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 5083 | |
e6c6338f JZ |
5084 | /* |
5085 | * Sometimes a later bad compute job can block a good gfx job as gfx | |
5086 | * and compute ring share internal GC HW mutually. We add an additional | |
5087 | * guilty jobs recheck step to find the real guilty job, it synchronously | |
5088 | * submits and pends for the first job being signaled. If it gets timeout, | |
5089 | * we identify it as a real guilty job. | |
5090 | */ | |
5091 | if (amdgpu_gpu_recovery == 2 && | |
5092 | !(tmp_vram_lost_counter < atomic_read(&adev->vram_lost_counter))) | |
04442bf7 LL |
5093 | amdgpu_device_recheck_guilty_jobs( |
5094 | tmp_adev, device_list_handle, &reset_context); | |
e6c6338f | 5095 | |
1d721ed6 AG |
5096 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5097 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5098 | ||
5099 | if (!ring || !ring->sched.thread) | |
5100 | continue; | |
5101 | ||
5102 | /* No point to resubmit jobs if we didn't HW reset*/ | |
5103 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
5104 | drm_sched_resubmit_jobs(&ring->sched); | |
5105 | ||
5106 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
5107 | } | |
5108 | ||
5109 | if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) { | |
4a580877 | 5110 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
5111 | } |
5112 | ||
5113 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
5114 | |
5115 | if (r) { | |
5116 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 5117 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
5118 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
5119 | } else { | |
12ffa55d | 5120 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
3fa8f89d S |
5121 | if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0)) |
5122 | DRM_WARN("smart shift update failed\n"); | |
26bc5340 | 5123 | } |
7c6e68c7 | 5124 | } |
26bc5340 | 5125 | |
7c6e68c7 | 5126 | skip_sched_resume: |
655ce9cb | 5127 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8e2712e7 | 5128 | /* unlock kfd: SRIOV would do it separately */ |
bb5c7235 | 5129 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
7c6e68c7 | 5130 | amdgpu_amdkfd_post_reset(tmp_adev); |
8e2712e7 | 5131 | |
5132 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
5133 | * need to bring up kfd here if it's not be initialized before | |
5134 | */ | |
5135 | if (!adev->kfd.init_complete) | |
5136 | amdgpu_amdkfd_device_init(adev); | |
5137 | ||
3f12acc8 EQ |
5138 | if (audio_suspended) |
5139 | amdgpu_device_resume_display_audio(tmp_adev); | |
26bc5340 AG |
5140 | amdgpu_device_unlock_adev(tmp_adev); |
5141 | } | |
5142 | ||
cbfd17f7 | 5143 | skip_recovery: |
9e94d22c | 5144 | if (hive) { |
53b3f8f4 | 5145 | atomic_set(&hive->in_reset, 0); |
9e94d22c | 5146 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 5147 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 5148 | } |
26bc5340 | 5149 | |
91fb309d | 5150 | if (r && r != -EAGAIN) |
26bc5340 | 5151 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
d38ceaf9 AD |
5152 | return r; |
5153 | } | |
5154 | ||
e3ecdffa AD |
5155 | /** |
5156 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
5157 | * | |
5158 | * @adev: amdgpu_device pointer | |
5159 | * | |
5160 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
5161 | * and lanes) of the slot the device is in. Handles APUs and | |
5162 | * virtualized environments where PCIE config space may not be available. | |
5163 | */ | |
5494d864 | 5164 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 5165 | { |
5d9a6330 | 5166 | struct pci_dev *pdev; |
c5313457 HK |
5167 | enum pci_bus_speed speed_cap, platform_speed_cap; |
5168 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 5169 | |
cd474ba0 AD |
5170 | if (amdgpu_pcie_gen_cap) |
5171 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 5172 | |
cd474ba0 AD |
5173 | if (amdgpu_pcie_lane_cap) |
5174 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 5175 | |
cd474ba0 AD |
5176 | /* covers APUs as well */ |
5177 | if (pci_is_root_bus(adev->pdev->bus)) { | |
5178 | if (adev->pm.pcie_gen_mask == 0) | |
5179 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
5180 | if (adev->pm.pcie_mlw_mask == 0) | |
5181 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 5182 | return; |
cd474ba0 | 5183 | } |
d0dd7f0c | 5184 | |
c5313457 HK |
5185 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
5186 | return; | |
5187 | ||
dbaa922b AD |
5188 | pcie_bandwidth_available(adev->pdev, NULL, |
5189 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 5190 | |
cd474ba0 | 5191 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
5192 | /* asic caps */ |
5193 | pdev = adev->pdev; | |
5194 | speed_cap = pcie_get_speed_cap(pdev); | |
5195 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
5196 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
5197 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
5198 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 5199 | } else { |
2b3a1f51 FX |
5200 | if (speed_cap == PCIE_SPEED_32_0GT) |
5201 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5202 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5203 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5204 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5205 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5206 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5207 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5208 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5209 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5210 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
5211 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
5212 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5213 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5214 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
5215 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
5216 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5217 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5218 | else | |
5219 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5220 | } | |
5221 | /* platform caps */ | |
c5313457 | 5222 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
5223 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5224 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5225 | } else { | |
2b3a1f51 FX |
5226 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
5227 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5228 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5229 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5230 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5231 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5232 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5233 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5234 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5235 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5236 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 5237 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
5238 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5239 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5240 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 5241 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
5242 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5243 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5244 | else | |
5245 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5246 | ||
cd474ba0 AD |
5247 | } |
5248 | } | |
5249 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 5250 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
5251 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
5252 | } else { | |
c5313457 | 5253 | switch (platform_link_width) { |
5d9a6330 | 5254 | case PCIE_LNK_X32: |
cd474ba0 AD |
5255 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
5256 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
5257 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5258 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5259 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5260 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5261 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5262 | break; | |
5d9a6330 | 5263 | case PCIE_LNK_X16: |
cd474ba0 AD |
5264 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5265 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5266 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5267 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5268 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5269 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5270 | break; | |
5d9a6330 | 5271 | case PCIE_LNK_X12: |
cd474ba0 AD |
5272 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5273 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5274 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5275 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5276 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5277 | break; | |
5d9a6330 | 5278 | case PCIE_LNK_X8: |
cd474ba0 AD |
5279 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5280 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5281 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5282 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5283 | break; | |
5d9a6330 | 5284 | case PCIE_LNK_X4: |
cd474ba0 AD |
5285 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5286 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5287 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5288 | break; | |
5d9a6330 | 5289 | case PCIE_LNK_X2: |
cd474ba0 AD |
5290 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5291 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5292 | break; | |
5d9a6330 | 5293 | case PCIE_LNK_X1: |
cd474ba0 AD |
5294 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5295 | break; | |
5296 | default: | |
5297 | break; | |
5298 | } | |
d0dd7f0c AD |
5299 | } |
5300 | } | |
5301 | } | |
d38ceaf9 | 5302 | |
361dbd01 AD |
5303 | int amdgpu_device_baco_enter(struct drm_device *dev) |
5304 | { | |
1348969a | 5305 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5306 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 5307 | |
4a580877 | 5308 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5309 | return -ENOTSUPP; |
5310 | ||
8ab0d6f0 | 5311 | if (ras && adev->ras_enabled && |
acdae216 | 5312 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5313 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
5314 | ||
9530273e | 5315 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
5316 | } |
5317 | ||
5318 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
5319 | { | |
1348969a | 5320 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5321 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 5322 | int ret = 0; |
361dbd01 | 5323 | |
4a580877 | 5324 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5325 | return -ENOTSUPP; |
5326 | ||
9530273e EQ |
5327 | ret = amdgpu_dpm_baco_exit(adev); |
5328 | if (ret) | |
5329 | return ret; | |
7a22677b | 5330 | |
8ab0d6f0 | 5331 | if (ras && adev->ras_enabled && |
acdae216 | 5332 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5333 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
5334 | ||
1bece222 CL |
5335 | if (amdgpu_passthrough(adev) && |
5336 | adev->nbio.funcs->clear_doorbell_interrupt) | |
5337 | adev->nbio.funcs->clear_doorbell_interrupt(adev); | |
5338 | ||
7a22677b | 5339 | return 0; |
361dbd01 | 5340 | } |
c9a6b82f | 5341 | |
acd89fca AG |
5342 | static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev) |
5343 | { | |
5344 | int i; | |
5345 | ||
5346 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5347 | struct amdgpu_ring *ring = adev->rings[i]; | |
5348 | ||
5349 | if (!ring || !ring->sched.thread) | |
5350 | continue; | |
5351 | ||
5352 | cancel_delayed_work_sync(&ring->sched.work_tdr); | |
5353 | } | |
5354 | } | |
5355 | ||
c9a6b82f AG |
5356 | /** |
5357 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
5358 | * @pdev: PCI device struct | |
5359 | * @state: PCI channel state | |
5360 | * | |
5361 | * Description: Called when a PCI error is detected. | |
5362 | * | |
5363 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
5364 | */ | |
5365 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5366 | { | |
5367 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5368 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5369 | int i; |
c9a6b82f AG |
5370 | |
5371 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
5372 | ||
6894305c AG |
5373 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
5374 | DRM_WARN("No support for XGMI hive yet..."); | |
5375 | return PCI_ERS_RESULT_DISCONNECT; | |
5376 | } | |
5377 | ||
c9a6b82f AG |
5378 | switch (state) { |
5379 | case pci_channel_io_normal: | |
5380 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 5381 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
5382 | case pci_channel_io_frozen: |
5383 | /* | |
acd89fca AG |
5384 | * Cancel and wait for all TDRs in progress if failing to |
5385 | * set adev->in_gpu_reset in amdgpu_device_lock_adev | |
5386 | * | |
5387 | * Locking adev->reset_sem will prevent any external access | |
5388 | * to GPU during PCI error recovery | |
5389 | */ | |
5390 | while (!amdgpu_device_lock_adev(adev, NULL)) | |
5391 | amdgpu_cancel_all_tdr(adev); | |
5392 | ||
5393 | /* | |
5394 | * Block any work scheduling as we do for regular GPU reset | |
5395 | * for the duration of the recovery | |
5396 | */ | |
5397 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5398 | struct amdgpu_ring *ring = adev->rings[i]; | |
5399 | ||
5400 | if (!ring || !ring->sched.thread) | |
5401 | continue; | |
5402 | ||
5403 | drm_sched_stop(&ring->sched, NULL); | |
5404 | } | |
8f8c80f4 | 5405 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
5406 | return PCI_ERS_RESULT_NEED_RESET; |
5407 | case pci_channel_io_perm_failure: | |
5408 | /* Permanent error, prepare for device removal */ | |
5409 | return PCI_ERS_RESULT_DISCONNECT; | |
5410 | } | |
5411 | ||
5412 | return PCI_ERS_RESULT_NEED_RESET; | |
5413 | } | |
5414 | ||
5415 | /** | |
5416 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
5417 | * @pdev: pointer to PCI device | |
5418 | */ | |
5419 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
5420 | { | |
5421 | ||
5422 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
5423 | ||
5424 | /* TODO - dump whatever for debugging purposes */ | |
5425 | ||
5426 | /* This called only if amdgpu_pci_error_detected returns | |
5427 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
5428 | * works, no need to reset slot. | |
5429 | */ | |
5430 | ||
5431 | return PCI_ERS_RESULT_RECOVERED; | |
5432 | } | |
5433 | ||
5434 | /** | |
5435 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
5436 | * @pdev: PCI device struct | |
5437 | * | |
5438 | * Description: This routine is called by the pci error recovery | |
5439 | * code after the PCI slot has been reset, just before we | |
5440 | * should resume normal operations. | |
5441 | */ | |
5442 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
5443 | { | |
5444 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5445 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 5446 | int r, i; |
04442bf7 | 5447 | struct amdgpu_reset_context reset_context; |
362c7b91 | 5448 | u32 memsize; |
7ac71382 | 5449 | struct list_head device_list; |
c9a6b82f AG |
5450 | |
5451 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
5452 | ||
04442bf7 LL |
5453 | memset(&reset_context, 0, sizeof(reset_context)); |
5454 | ||
7ac71382 | 5455 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 5456 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 5457 | |
362c7b91 AG |
5458 | /* wait for asic to come out of reset */ |
5459 | msleep(500); | |
5460 | ||
7ac71382 | 5461 | /* Restore PCI confspace */ |
c1dd4aa6 | 5462 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 5463 | |
362c7b91 AG |
5464 | /* confirm ASIC came out of reset */ |
5465 | for (i = 0; i < adev->usec_timeout; i++) { | |
5466 | memsize = amdgpu_asic_get_config_memsize(adev); | |
5467 | ||
5468 | if (memsize != 0xffffffff) | |
5469 | break; | |
5470 | udelay(1); | |
5471 | } | |
5472 | if (memsize == 0xffffffff) { | |
5473 | r = -ETIME; | |
5474 | goto out; | |
5475 | } | |
5476 | ||
04442bf7 LL |
5477 | reset_context.method = AMD_RESET_METHOD_NONE; |
5478 | reset_context.reset_req_dev = adev; | |
5479 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5480 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); | |
5481 | ||
7afefb81 | 5482 | adev->no_hw_access = true; |
04442bf7 | 5483 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
7afefb81 | 5484 | adev->no_hw_access = false; |
c9a6b82f AG |
5485 | if (r) |
5486 | goto out; | |
5487 | ||
04442bf7 | 5488 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
c9a6b82f AG |
5489 | |
5490 | out: | |
c9a6b82f | 5491 | if (!r) { |
c1dd4aa6 AG |
5492 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
5493 | pci_restore_state(adev->pdev); | |
5494 | ||
c9a6b82f AG |
5495 | DRM_INFO("PCIe error recovery succeeded\n"); |
5496 | } else { | |
5497 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
5498 | amdgpu_device_unlock_adev(adev); | |
5499 | } | |
5500 | ||
5501 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
5502 | } | |
5503 | ||
5504 | /** | |
5505 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
5506 | * @pdev: pointer to PCI device | |
5507 | * | |
5508 | * Called when the error recovery driver tells us that its | |
505199a3 | 5509 | * OK to resume normal operation. |
c9a6b82f AG |
5510 | */ |
5511 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
5512 | { | |
5513 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5514 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5515 | int i; |
c9a6b82f | 5516 | |
c9a6b82f AG |
5517 | |
5518 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca AG |
5519 | |
5520 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5521 | struct amdgpu_ring *ring = adev->rings[i]; | |
5522 | ||
5523 | if (!ring || !ring->sched.thread) | |
5524 | continue; | |
5525 | ||
5526 | ||
5527 | drm_sched_resubmit_jobs(&ring->sched); | |
5528 | drm_sched_start(&ring->sched, true); | |
5529 | } | |
5530 | ||
5531 | amdgpu_device_unlock_adev(adev); | |
c9a6b82f | 5532 | } |
c1dd4aa6 AG |
5533 | |
5534 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
5535 | { | |
5536 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5537 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5538 | int r; | |
5539 | ||
5540 | r = pci_save_state(pdev); | |
5541 | if (!r) { | |
5542 | kfree(adev->pci_state); | |
5543 | ||
5544 | adev->pci_state = pci_store_saved_state(pdev); | |
5545 | ||
5546 | if (!adev->pci_state) { | |
5547 | DRM_ERROR("Failed to store PCI saved state"); | |
5548 | return false; | |
5549 | } | |
5550 | } else { | |
5551 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
5552 | return false; | |
5553 | } | |
5554 | ||
5555 | return true; | |
5556 | } | |
5557 | ||
5558 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
5559 | { | |
5560 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5561 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5562 | int r; | |
5563 | ||
5564 | if (!adev->pci_state) | |
5565 | return false; | |
5566 | ||
5567 | r = pci_load_saved_state(pdev, adev->pci_state); | |
5568 | ||
5569 | if (!r) { | |
5570 | pci_restore_state(pdev); | |
5571 | } else { | |
5572 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
5573 | return false; | |
5574 | } | |
5575 | ||
5576 | return true; | |
5577 | } | |
5578 | ||
810085dd EH |
5579 | void amdgpu_device_flush_hdp(struct amdgpu_device *adev, |
5580 | struct amdgpu_ring *ring) | |
5581 | { | |
5582 | #ifdef CONFIG_X86_64 | |
5583 | if (adev->flags & AMD_IS_APU) | |
5584 | return; | |
5585 | #endif | |
5586 | if (adev->gmc.xgmi.connected_to_cpu) | |
5587 | return; | |
5588 | ||
5589 | if (ring && ring->funcs->emit_hdp_flush) | |
5590 | amdgpu_ring_emit_hdp_flush(ring); | |
5591 | else | |
5592 | amdgpu_asic_flush_hdp(adev, ring); | |
5593 | } | |
c1dd4aa6 | 5594 | |
810085dd EH |
5595 | void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, |
5596 | struct amdgpu_ring *ring) | |
5597 | { | |
5598 | #ifdef CONFIG_X86_64 | |
5599 | if (adev->flags & AMD_IS_APU) | |
5600 | return; | |
5601 | #endif | |
5602 | if (adev->gmc.xgmi.connected_to_cpu) | |
5603 | return; | |
c1dd4aa6 | 5604 | |
810085dd EH |
5605 | amdgpu_asic_invalidate_hdp(adev, ring); |
5606 | } |