Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
4562236b | 33 | #include <drm/drm_atomic_helper.h> |
d38ceaf9 AD |
34 | #include <drm/amdgpu_drm.h> |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
ba997709 | 58 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 59 | #include "amdgpu_pm.h" |
d38ceaf9 | 60 | |
e2a75f88 | 61 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 62 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 63 | |
2dc80b00 S |
64 | #define AMDGPU_RESUME_MS 2000 |
65 | ||
d38ceaf9 | 66 | static const char *amdgpu_asic_name[] = { |
da69c161 KW |
67 | "TAHITI", |
68 | "PITCAIRN", | |
69 | "VERDE", | |
70 | "OLAND", | |
71 | "HAINAN", | |
d38ceaf9 AD |
72 | "BONAIRE", |
73 | "KAVERI", | |
74 | "KABINI", | |
75 | "HAWAII", | |
76 | "MULLINS", | |
77 | "TOPAZ", | |
78 | "TONGA", | |
48299f95 | 79 | "FIJI", |
d38ceaf9 | 80 | "CARRIZO", |
139f4917 | 81 | "STONEY", |
2cc0c0b5 FC |
82 | "POLARIS10", |
83 | "POLARIS11", | |
c4642a47 | 84 | "POLARIS12", |
d4196f01 | 85 | "VEGA10", |
2ca8a5d2 | 86 | "RAVEN", |
d38ceaf9 AD |
87 | "LAST", |
88 | }; | |
89 | ||
5494d864 AD |
90 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
91 | ||
d38ceaf9 AD |
92 | bool amdgpu_device_is_px(struct drm_device *dev) |
93 | { | |
94 | struct amdgpu_device *adev = dev->dev_private; | |
95 | ||
2f7d10b3 | 96 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
97 | return true; |
98 | return false; | |
99 | } | |
100 | ||
101 | /* | |
102 | * MMIO register access helper functions. | |
103 | */ | |
104 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 105 | uint32_t acc_flags) |
d38ceaf9 | 106 | { |
f4b373f4 TSD |
107 | uint32_t ret; |
108 | ||
43ca8efa | 109 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 110 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 111 | |
15d72fd7 | 112 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 113 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
114 | else { |
115 | unsigned long flags; | |
d38ceaf9 AD |
116 | |
117 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
118 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
119 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
120 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 121 | } |
f4b373f4 TSD |
122 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
123 | return ret; | |
d38ceaf9 AD |
124 | } |
125 | ||
421a2a30 ML |
126 | /* |
127 | * MMIO register read with bytes helper functions | |
128 | * @offset:bytes offset from MMIO start | |
129 | * | |
130 | */ | |
131 | ||
132 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { | |
133 | if (offset < adev->rmmio_size) | |
134 | return (readb(adev->rmmio + offset)); | |
135 | BUG(); | |
136 | } | |
137 | ||
138 | /* | |
139 | * MMIO register write with bytes helper functions | |
140 | * @offset:bytes offset from MMIO start | |
141 | * @value: the value want to be written to the register | |
142 | * | |
143 | */ | |
144 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { | |
145 | if (offset < adev->rmmio_size) | |
146 | writeb(value, adev->rmmio + offset); | |
147 | else | |
148 | BUG(); | |
149 | } | |
150 | ||
151 | ||
d38ceaf9 | 152 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 153 | uint32_t acc_flags) |
d38ceaf9 | 154 | { |
f4b373f4 | 155 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 156 | |
47ed4e1c KW |
157 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
158 | adev->last_mm_index = v; | |
159 | } | |
160 | ||
43ca8efa | 161 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 162 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 163 | |
15d72fd7 | 164 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
165 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
166 | else { | |
167 | unsigned long flags; | |
168 | ||
169 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
170 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
171 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
172 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
173 | } | |
47ed4e1c KW |
174 | |
175 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
176 | udelay(500); | |
177 | } | |
d38ceaf9 AD |
178 | } |
179 | ||
180 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
181 | { | |
182 | if ((reg * 4) < adev->rio_mem_size) | |
183 | return ioread32(adev->rio_mem + (reg * 4)); | |
184 | else { | |
185 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
186 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
187 | } | |
188 | } | |
189 | ||
190 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
191 | { | |
47ed4e1c KW |
192 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
193 | adev->last_mm_index = v; | |
194 | } | |
d38ceaf9 AD |
195 | |
196 | if ((reg * 4) < adev->rio_mem_size) | |
197 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
198 | else { | |
199 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
200 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
201 | } | |
47ed4e1c KW |
202 | |
203 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
204 | udelay(500); | |
205 | } | |
d38ceaf9 AD |
206 | } |
207 | ||
208 | /** | |
209 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
210 | * | |
211 | * @adev: amdgpu_device pointer | |
212 | * @index: doorbell index | |
213 | * | |
214 | * Returns the value in the doorbell aperture at the | |
215 | * requested doorbell index (CIK). | |
216 | */ | |
217 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
218 | { | |
219 | if (index < adev->doorbell.num_doorbells) { | |
220 | return readl(adev->doorbell.ptr + index); | |
221 | } else { | |
222 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
223 | return 0; | |
224 | } | |
225 | } | |
226 | ||
227 | /** | |
228 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
229 | * | |
230 | * @adev: amdgpu_device pointer | |
231 | * @index: doorbell index | |
232 | * @v: value to write | |
233 | * | |
234 | * Writes @v to the doorbell aperture at the | |
235 | * requested doorbell index (CIK). | |
236 | */ | |
237 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
238 | { | |
239 | if (index < adev->doorbell.num_doorbells) { | |
240 | writel(v, adev->doorbell.ptr + index); | |
241 | } else { | |
242 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
243 | } | |
244 | } | |
245 | ||
832be404 KW |
246 | /** |
247 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
248 | * | |
249 | * @adev: amdgpu_device pointer | |
250 | * @index: doorbell index | |
251 | * | |
252 | * Returns the value in the doorbell aperture at the | |
253 | * requested doorbell index (VEGA10+). | |
254 | */ | |
255 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
256 | { | |
257 | if (index < adev->doorbell.num_doorbells) { | |
258 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
259 | } else { | |
260 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
261 | return 0; | |
262 | } | |
263 | } | |
264 | ||
265 | /** | |
266 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
267 | * | |
268 | * @adev: amdgpu_device pointer | |
269 | * @index: doorbell index | |
270 | * @v: value to write | |
271 | * | |
272 | * Writes @v to the doorbell aperture at the | |
273 | * requested doorbell index (VEGA10+). | |
274 | */ | |
275 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
276 | { | |
277 | if (index < adev->doorbell.num_doorbells) { | |
278 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
279 | } else { | |
280 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
281 | } | |
282 | } | |
283 | ||
d38ceaf9 AD |
284 | /** |
285 | * amdgpu_invalid_rreg - dummy reg read function | |
286 | * | |
287 | * @adev: amdgpu device pointer | |
288 | * @reg: offset of register | |
289 | * | |
290 | * Dummy register read function. Used for register blocks | |
291 | * that certain asics don't have (all asics). | |
292 | * Returns the value in the register. | |
293 | */ | |
294 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
295 | { | |
296 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
297 | BUG(); | |
298 | return 0; | |
299 | } | |
300 | ||
301 | /** | |
302 | * amdgpu_invalid_wreg - dummy reg write function | |
303 | * | |
304 | * @adev: amdgpu device pointer | |
305 | * @reg: offset of register | |
306 | * @v: value to write to the register | |
307 | * | |
308 | * Dummy register read function. Used for register blocks | |
309 | * that certain asics don't have (all asics). | |
310 | */ | |
311 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
312 | { | |
313 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
314 | reg, v); | |
315 | BUG(); | |
316 | } | |
317 | ||
318 | /** | |
319 | * amdgpu_block_invalid_rreg - dummy reg read function | |
320 | * | |
321 | * @adev: amdgpu device pointer | |
322 | * @block: offset of instance | |
323 | * @reg: offset of register | |
324 | * | |
325 | * Dummy register read function. Used for register blocks | |
326 | * that certain asics don't have (all asics). | |
327 | * Returns the value in the register. | |
328 | */ | |
329 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
330 | uint32_t block, uint32_t reg) | |
331 | { | |
332 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
333 | reg, block); | |
334 | BUG(); | |
335 | return 0; | |
336 | } | |
337 | ||
338 | /** | |
339 | * amdgpu_block_invalid_wreg - dummy reg write function | |
340 | * | |
341 | * @adev: amdgpu device pointer | |
342 | * @block: offset of instance | |
343 | * @reg: offset of register | |
344 | * @v: value to write to the register | |
345 | * | |
346 | * Dummy register read function. Used for register blocks | |
347 | * that certain asics don't have (all asics). | |
348 | */ | |
349 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
350 | uint32_t block, | |
351 | uint32_t reg, uint32_t v) | |
352 | { | |
353 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
354 | reg, block, v); | |
355 | BUG(); | |
356 | } | |
357 | ||
06ec9070 | 358 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 359 | { |
a4a02777 CK |
360 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
361 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
362 | &adev->vram_scratch.robj, | |
363 | &adev->vram_scratch.gpu_addr, | |
364 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
365 | } |
366 | ||
06ec9070 | 367 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 368 | { |
078af1a3 | 369 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
370 | } |
371 | ||
372 | /** | |
9c3f2b54 | 373 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
374 | * |
375 | * @adev: amdgpu_device pointer | |
376 | * @registers: pointer to the register array | |
377 | * @array_size: size of the register array | |
378 | * | |
379 | * Programs an array or registers with and and or masks. | |
380 | * This is a helper for setting golden registers. | |
381 | */ | |
9c3f2b54 AD |
382 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
383 | const u32 *registers, | |
384 | const u32 array_size) | |
d38ceaf9 AD |
385 | { |
386 | u32 tmp, reg, and_mask, or_mask; | |
387 | int i; | |
388 | ||
389 | if (array_size % 3) | |
390 | return; | |
391 | ||
392 | for (i = 0; i < array_size; i +=3) { | |
393 | reg = registers[i + 0]; | |
394 | and_mask = registers[i + 1]; | |
395 | or_mask = registers[i + 2]; | |
396 | ||
397 | if (and_mask == 0xffffffff) { | |
398 | tmp = or_mask; | |
399 | } else { | |
400 | tmp = RREG32(reg); | |
401 | tmp &= ~and_mask; | |
402 | tmp |= or_mask; | |
403 | } | |
404 | WREG32(reg, tmp); | |
405 | } | |
406 | } | |
407 | ||
8111c387 | 408 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
409 | { |
410 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
411 | } | |
412 | ||
413 | /* | |
414 | * GPU doorbell aperture helpers function. | |
415 | */ | |
416 | /** | |
06ec9070 | 417 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
418 | * |
419 | * @adev: amdgpu_device pointer | |
420 | * | |
421 | * Init doorbell driver information (CIK) | |
422 | * Returns 0 on success, error on failure. | |
423 | */ | |
06ec9070 | 424 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 425 | { |
705e519e CK |
426 | /* No doorbell on SI hardware generation */ |
427 | if (adev->asic_type < CHIP_BONAIRE) { | |
428 | adev->doorbell.base = 0; | |
429 | adev->doorbell.size = 0; | |
430 | adev->doorbell.num_doorbells = 0; | |
431 | adev->doorbell.ptr = NULL; | |
432 | return 0; | |
433 | } | |
434 | ||
d6895ad3 CK |
435 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
436 | return -EINVAL; | |
437 | ||
d38ceaf9 AD |
438 | /* doorbell bar mapping */ |
439 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
440 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
441 | ||
edf600da | 442 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
443 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
444 | if (adev->doorbell.num_doorbells == 0) | |
445 | return -EINVAL; | |
446 | ||
8972e5d2 CK |
447 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
448 | adev->doorbell.num_doorbells * | |
449 | sizeof(u32)); | |
450 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 451 | return -ENOMEM; |
d38ceaf9 AD |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
456 | /** | |
06ec9070 | 457 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
458 | * |
459 | * @adev: amdgpu_device pointer | |
460 | * | |
461 | * Tear down doorbell driver information (CIK) | |
462 | */ | |
06ec9070 | 463 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
464 | { |
465 | iounmap(adev->doorbell.ptr); | |
466 | adev->doorbell.ptr = NULL; | |
467 | } | |
468 | ||
22cb0164 | 469 | |
d38ceaf9 AD |
470 | |
471 | /* | |
06ec9070 | 472 | * amdgpu_device_wb_*() |
455a7bc2 | 473 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 474 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
475 | */ |
476 | ||
477 | /** | |
06ec9070 | 478 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
479 | * |
480 | * @adev: amdgpu_device pointer | |
481 | * | |
482 | * Disables Writeback and frees the Writeback memory (all asics). | |
483 | * Used at driver shutdown. | |
484 | */ | |
06ec9070 | 485 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
486 | { |
487 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
488 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
489 | &adev->wb.gpu_addr, | |
490 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
491 | adev->wb.wb_obj = NULL; |
492 | } | |
493 | } | |
494 | ||
495 | /** | |
06ec9070 | 496 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
497 | * |
498 | * @adev: amdgpu_device pointer | |
499 | * | |
455a7bc2 | 500 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
501 | * Used at driver startup. |
502 | * Returns 0 on success or an -error on failure. | |
503 | */ | |
06ec9070 | 504 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
505 | { |
506 | int r; | |
507 | ||
508 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
509 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
510 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
511 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
512 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
513 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
514 | if (r) { |
515 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
516 | return r; | |
517 | } | |
d38ceaf9 AD |
518 | |
519 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
520 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
521 | ||
522 | /* clear wb memory */ | |
73469585 | 523 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
524 | } |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
529 | /** | |
131b4b36 | 530 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
531 | * |
532 | * @adev: amdgpu_device pointer | |
533 | * @wb: wb index | |
534 | * | |
535 | * Allocate a wb slot for use by the driver (all asics). | |
536 | * Returns 0 on success or -EINVAL on failure. | |
537 | */ | |
131b4b36 | 538 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
539 | { |
540 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 541 | |
97407b63 | 542 | if (offset < adev->wb.num_wb) { |
7014285a | 543 | __set_bit(offset, adev->wb.used); |
63ae07ca | 544 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
545 | return 0; |
546 | } else { | |
547 | return -EINVAL; | |
548 | } | |
549 | } | |
550 | ||
d38ceaf9 | 551 | /** |
131b4b36 | 552 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
553 | * |
554 | * @adev: amdgpu_device pointer | |
555 | * @wb: wb index | |
556 | * | |
557 | * Free a wb slot allocated for use by the driver (all asics) | |
558 | */ | |
131b4b36 | 559 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 560 | { |
73469585 | 561 | wb >>= 3; |
d38ceaf9 | 562 | if (wb < adev->wb.num_wb) |
73469585 | 563 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
564 | } |
565 | ||
566 | /** | |
2543e28a | 567 | * amdgpu_device_vram_location - try to find VRAM location |
d38ceaf9 AD |
568 | * @adev: amdgpu device structure holding all necessary informations |
569 | * @mc: memory controller structure holding memory informations | |
570 | * @base: base address at which to put VRAM | |
571 | * | |
455a7bc2 | 572 | * Function will try to place VRAM at base address provided |
3d647c8f | 573 | * as parameter. |
d38ceaf9 | 574 | */ |
2543e28a | 575 | void amdgpu_device_vram_location(struct amdgpu_device *adev, |
770d13b1 | 576 | struct amdgpu_gmc *mc, u64 base) |
d38ceaf9 AD |
577 | { |
578 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
579 | ||
580 | mc->vram_start = base; | |
d38ceaf9 AD |
581 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
582 | if (limit && limit < mc->real_vram_size) | |
583 | mc->real_vram_size = limit; | |
584 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
585 | mc->mc_vram_size >> 20, mc->vram_start, | |
586 | mc->vram_end, mc->real_vram_size >> 20); | |
587 | } | |
588 | ||
589 | /** | |
2543e28a | 590 | * amdgpu_device_gart_location - try to find GTT location |
d38ceaf9 AD |
591 | * @adev: amdgpu device structure holding all necessary informations |
592 | * @mc: memory controller structure holding memory informations | |
593 | * | |
594 | * Function will place try to place GTT before or after VRAM. | |
595 | * | |
596 | * If GTT size is bigger than space left then we ajust GTT size. | |
597 | * Thus function will never fails. | |
598 | * | |
599 | * FIXME: when reducing GTT size align new size on power of 2. | |
600 | */ | |
2543e28a | 601 | void amdgpu_device_gart_location(struct amdgpu_device *adev, |
770d13b1 | 602 | struct amdgpu_gmc *mc) |
d38ceaf9 AD |
603 | { |
604 | u64 size_af, size_bf; | |
605 | ||
770d13b1 | 606 | size_af = adev->gmc.mc_mask - mc->vram_end; |
ed21c047 | 607 | size_bf = mc->vram_start; |
d38ceaf9 | 608 | if (size_bf > size_af) { |
6f02a696 | 609 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 610 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 611 | mc->gart_size = size_bf; |
d38ceaf9 | 612 | } |
6f02a696 | 613 | mc->gart_start = 0; |
d38ceaf9 | 614 | } else { |
6f02a696 | 615 | if (mc->gart_size > size_af) { |
d38ceaf9 | 616 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 617 | mc->gart_size = size_af; |
d38ceaf9 | 618 | } |
b98f1b9e CK |
619 | /* VCE doesn't like it when BOs cross a 4GB segment, so align |
620 | * the GART base on a 4GB boundary as well. | |
621 | */ | |
622 | mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL); | |
d38ceaf9 | 623 | } |
6f02a696 | 624 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 625 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 626 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
627 | } |
628 | ||
d6895ad3 CK |
629 | /** |
630 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
631 | * | |
632 | * @adev: amdgpu_device pointer | |
633 | * | |
634 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
635 | * to fail, but if any of the BARs is not accessible after the size we abort | |
636 | * driver loading by returning -ENODEV. | |
637 | */ | |
638 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
639 | { | |
770d13b1 | 640 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 641 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
642 | struct pci_bus *root; |
643 | struct resource *res; | |
644 | unsigned i; | |
d6895ad3 CK |
645 | u16 cmd; |
646 | int r; | |
647 | ||
0c03b912 | 648 | /* Bypass for VF */ |
649 | if (amdgpu_sriov_vf(adev)) | |
650 | return 0; | |
651 | ||
31b8adab CK |
652 | /* Check if the root BUS has 64bit memory resources */ |
653 | root = adev->pdev->bus; | |
654 | while (root->parent) | |
655 | root = root->parent; | |
656 | ||
657 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 658 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
659 | res->start > 0x100000000ull) |
660 | break; | |
661 | } | |
662 | ||
663 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
664 | if (!res) | |
665 | return 0; | |
666 | ||
d6895ad3 CK |
667 | /* Disable memory decoding while we change the BAR addresses and size */ |
668 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
669 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
670 | cmd & ~PCI_COMMAND_MEMORY); | |
671 | ||
672 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 673 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
674 | if (adev->asic_type >= CHIP_BONAIRE) |
675 | pci_release_resource(adev->pdev, 2); | |
676 | ||
677 | pci_release_resource(adev->pdev, 0); | |
678 | ||
679 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
680 | if (r == -ENOSPC) | |
681 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
682 | else if (r && r != -ENOTSUPP) | |
683 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
684 | ||
685 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
686 | ||
687 | /* When the doorbell or fb BAR isn't available we have no chance of | |
688 | * using the device. | |
689 | */ | |
06ec9070 | 690 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
691 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
692 | return -ENODEV; | |
693 | ||
694 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
695 | ||
696 | return 0; | |
697 | } | |
a05502e5 | 698 | |
d38ceaf9 AD |
699 | /* |
700 | * GPU helpers function. | |
701 | */ | |
702 | /** | |
39c640c0 | 703 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
704 | * |
705 | * @adev: amdgpu_device pointer | |
706 | * | |
c836fec5 JQ |
707 | * Check if the asic has been initialized (all asics) at driver startup |
708 | * or post is needed if hw reset is performed. | |
709 | * Returns true if need or false if not. | |
d38ceaf9 | 710 | */ |
39c640c0 | 711 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
712 | { |
713 | uint32_t reg; | |
714 | ||
bec86378 ML |
715 | if (amdgpu_sriov_vf(adev)) |
716 | return false; | |
717 | ||
718 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
719 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
720 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
721 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
722 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
723 | */ |
724 | if (adev->asic_type == CHIP_FIJI) { | |
725 | int err; | |
726 | uint32_t fw_ver; | |
727 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
728 | /* force vPost if error occured */ | |
729 | if (err) | |
730 | return true; | |
731 | ||
732 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
733 | if (fw_ver < 0x00160e00) |
734 | return true; | |
bec86378 | 735 | } |
bec86378 | 736 | } |
91fe77eb | 737 | |
738 | if (adev->has_hw_reset) { | |
739 | adev->has_hw_reset = false; | |
740 | return true; | |
741 | } | |
742 | ||
743 | /* bios scratch used on CIK+ */ | |
744 | if (adev->asic_type >= CHIP_BONAIRE) | |
745 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
746 | ||
747 | /* check MEM_SIZE for older asics */ | |
748 | reg = amdgpu_asic_get_config_memsize(adev); | |
749 | ||
750 | if ((reg != 0) && (reg != 0xffffffff)) | |
751 | return false; | |
752 | ||
753 | return true; | |
bec86378 ML |
754 | } |
755 | ||
d38ceaf9 AD |
756 | /* if we get transitioned to only one device, take VGA back */ |
757 | /** | |
06ec9070 | 758 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
759 | * |
760 | * @cookie: amdgpu_device pointer | |
761 | * @state: enable/disable vga decode | |
762 | * | |
763 | * Enable/disable vga decode (all asics). | |
764 | * Returns VGA resource flags. | |
765 | */ | |
06ec9070 | 766 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
767 | { |
768 | struct amdgpu_device *adev = cookie; | |
769 | amdgpu_asic_set_vga_state(adev, state); | |
770 | if (state) | |
771 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
772 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
773 | else | |
774 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
775 | } | |
776 | ||
06ec9070 | 777 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
778 | { |
779 | /* defines number of bits in page table versus page directory, | |
780 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
781 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
782 | if (amdgpu_vm_block_size == -1) |
783 | return; | |
a1adf8be | 784 | |
bab4fee7 | 785 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
786 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
787 | amdgpu_vm_block_size); | |
97489129 | 788 | amdgpu_vm_block_size = -1; |
a1adf8be | 789 | } |
a1adf8be CZ |
790 | } |
791 | ||
06ec9070 | 792 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 793 | { |
64dab074 AD |
794 | /* no need to check the default value */ |
795 | if (amdgpu_vm_size == -1) | |
796 | return; | |
797 | ||
83ca145d ZJ |
798 | if (amdgpu_vm_size < 1) { |
799 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
800 | amdgpu_vm_size); | |
f3368128 | 801 | amdgpu_vm_size = -1; |
83ca145d | 802 | } |
83ca145d ZJ |
803 | } |
804 | ||
d38ceaf9 | 805 | /** |
06ec9070 | 806 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
807 | * |
808 | * @adev: amdgpu_device pointer | |
809 | * | |
810 | * Validates certain module parameters and updates | |
811 | * the associated values used by the driver (all asics). | |
812 | */ | |
06ec9070 | 813 | static void amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 814 | { |
5b011235 CZ |
815 | if (amdgpu_sched_jobs < 4) { |
816 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
817 | amdgpu_sched_jobs); | |
818 | amdgpu_sched_jobs = 4; | |
76117507 | 819 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
820 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
821 | amdgpu_sched_jobs); | |
822 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
823 | } | |
d38ceaf9 | 824 | |
83e74db6 | 825 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
826 | /* gart size must be greater or equal to 32M */ |
827 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
828 | amdgpu_gart_size); | |
83e74db6 | 829 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
830 | } |
831 | ||
36d38372 | 832 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 833 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
834 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
835 | amdgpu_gtt_size); | |
836 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
837 | } |
838 | ||
d07f14be RH |
839 | /* valid range is between 4 and 9 inclusive */ |
840 | if (amdgpu_vm_fragment_size != -1 && | |
841 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
842 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
843 | amdgpu_vm_fragment_size = -1; | |
844 | } | |
845 | ||
06ec9070 | 846 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 847 | |
06ec9070 | 848 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 849 | |
526bae37 | 850 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 851 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
852 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
853 | amdgpu_vram_page_split); | |
854 | amdgpu_vram_page_split = 1024; | |
855 | } | |
8854695a AG |
856 | |
857 | if (amdgpu_lockup_timeout == 0) { | |
858 | dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n"); | |
859 | amdgpu_lockup_timeout = 10000; | |
860 | } | |
19aede77 AD |
861 | |
862 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); | |
d38ceaf9 AD |
863 | } |
864 | ||
865 | /** | |
866 | * amdgpu_switcheroo_set_state - set switcheroo state | |
867 | * | |
868 | * @pdev: pci dev pointer | |
1694467b | 869 | * @state: vga_switcheroo state |
d38ceaf9 AD |
870 | * |
871 | * Callback for the switcheroo driver. Suspends or resumes the | |
872 | * the asics before or after it is powered up using ACPI methods. | |
873 | */ | |
874 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
875 | { | |
876 | struct drm_device *dev = pci_get_drvdata(pdev); | |
877 | ||
878 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
879 | return; | |
880 | ||
881 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 882 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
883 | /* don't suspend or resume card normally */ |
884 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
885 | ||
810ddc3a | 886 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 887 | |
d38ceaf9 AD |
888 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
889 | drm_kms_helper_poll_enable(dev); | |
890 | } else { | |
7ca85295 | 891 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
892 | drm_kms_helper_poll_disable(dev); |
893 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 894 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
895 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
896 | } | |
897 | } | |
898 | ||
899 | /** | |
900 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
901 | * | |
902 | * @pdev: pci dev pointer | |
903 | * | |
904 | * Callback for the switcheroo driver. Check of the switcheroo | |
905 | * state can be changed. | |
906 | * Returns true if the state can be changed, false if not. | |
907 | */ | |
908 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
909 | { | |
910 | struct drm_device *dev = pci_get_drvdata(pdev); | |
911 | ||
912 | /* | |
913 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
914 | * locking inversion with the driver load path. And the access here is | |
915 | * completely racy anyway. So don't bother with locking for now. | |
916 | */ | |
917 | return dev->open_count == 0; | |
918 | } | |
919 | ||
920 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
921 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
922 | .reprobe = NULL, | |
923 | .can_switch = amdgpu_switcheroo_can_switch, | |
924 | }; | |
925 | ||
2990a1fc AD |
926 | int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, |
927 | enum amd_ip_block_type block_type, | |
928 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
929 | { |
930 | int i, r = 0; | |
931 | ||
932 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 933 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 934 | continue; |
c722865a RZ |
935 | if (adev->ip_blocks[i].version->type != block_type) |
936 | continue; | |
937 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
938 | continue; | |
939 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
940 | (void *)adev, state); | |
941 | if (r) | |
942 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
943 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
944 | } |
945 | return r; | |
946 | } | |
947 | ||
2990a1fc AD |
948 | int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, |
949 | enum amd_ip_block_type block_type, | |
950 | enum amd_powergating_state state) | |
d38ceaf9 AD |
951 | { |
952 | int i, r = 0; | |
953 | ||
954 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 955 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 956 | continue; |
c722865a RZ |
957 | if (adev->ip_blocks[i].version->type != block_type) |
958 | continue; | |
959 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
960 | continue; | |
961 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
962 | (void *)adev, state); | |
963 | if (r) | |
964 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
965 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
966 | } |
967 | return r; | |
968 | } | |
969 | ||
2990a1fc AD |
970 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
971 | u32 *flags) | |
6cb2d4e4 HR |
972 | { |
973 | int i; | |
974 | ||
975 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
976 | if (!adev->ip_blocks[i].status.valid) | |
977 | continue; | |
978 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
979 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
980 | } | |
981 | } | |
982 | ||
2990a1fc AD |
983 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
984 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
985 | { |
986 | int i, r; | |
987 | ||
988 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 989 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 990 | continue; |
a1255107 AD |
991 | if (adev->ip_blocks[i].version->type == block_type) { |
992 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
993 | if (r) |
994 | return r; | |
995 | break; | |
996 | } | |
997 | } | |
998 | return 0; | |
999 | ||
1000 | } | |
1001 | ||
2990a1fc AD |
1002 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1003 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1004 | { |
1005 | int i; | |
1006 | ||
1007 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1008 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1009 | continue; |
a1255107 AD |
1010 | if (adev->ip_blocks[i].version->type == block_type) |
1011 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1012 | } |
1013 | return true; | |
1014 | ||
1015 | } | |
1016 | ||
2990a1fc AD |
1017 | struct amdgpu_ip_block * |
1018 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1019 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1020 | { |
1021 | int i; | |
1022 | ||
1023 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1024 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1025 | return &adev->ip_blocks[i]; |
1026 | ||
1027 | return NULL; | |
1028 | } | |
1029 | ||
1030 | /** | |
2990a1fc | 1031 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1032 | * |
1033 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1034 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1035 | * @major: major version |
1036 | * @minor: minor version | |
1037 | * | |
1038 | * return 0 if equal or greater | |
1039 | * return 1 if smaller or the ip_block doesn't exist | |
1040 | */ | |
2990a1fc AD |
1041 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1042 | enum amd_ip_block_type type, | |
1043 | u32 major, u32 minor) | |
d38ceaf9 | 1044 | { |
2990a1fc | 1045 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1046 | |
a1255107 AD |
1047 | if (ip_block && ((ip_block->version->major > major) || |
1048 | ((ip_block->version->major == major) && | |
1049 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1050 | return 0; |
1051 | ||
1052 | return 1; | |
1053 | } | |
1054 | ||
a1255107 | 1055 | /** |
2990a1fc | 1056 | * amdgpu_device_ip_block_add |
a1255107 AD |
1057 | * |
1058 | * @adev: amdgpu_device pointer | |
1059 | * @ip_block_version: pointer to the IP to add | |
1060 | * | |
1061 | * Adds the IP block driver information to the collection of IPs | |
1062 | * on the asic. | |
1063 | */ | |
2990a1fc AD |
1064 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1065 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1066 | { |
1067 | if (!ip_block_version) | |
1068 | return -EINVAL; | |
1069 | ||
e966a725 | 1070 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1071 | ip_block_version->funcs->name); |
1072 | ||
a1255107 AD |
1073 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
483ef985 | 1078 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1079 | { |
1080 | adev->enable_virtual_display = false; | |
1081 | ||
1082 | if (amdgpu_virtual_display) { | |
1083 | struct drm_device *ddev = adev->ddev; | |
1084 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1085 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1086 | |
1087 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1088 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1089 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1090 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1091 | if (!strcmp("all", pciaddname) |
1092 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1093 | long num_crtc; |
1094 | int res = -1; | |
1095 | ||
9accf2fd | 1096 | adev->enable_virtual_display = true; |
0f66356d ED |
1097 | |
1098 | if (pciaddname_tmp) | |
1099 | res = kstrtol(pciaddname_tmp, 10, | |
1100 | &num_crtc); | |
1101 | ||
1102 | if (!res) { | |
1103 | if (num_crtc < 1) | |
1104 | num_crtc = 1; | |
1105 | if (num_crtc > 6) | |
1106 | num_crtc = 6; | |
1107 | adev->mode_info.num_crtc = num_crtc; | |
1108 | } else { | |
1109 | adev->mode_info.num_crtc = 1; | |
1110 | } | |
9accf2fd ED |
1111 | break; |
1112 | } | |
1113 | } | |
1114 | ||
0f66356d ED |
1115 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1116 | amdgpu_virtual_display, pci_address_name, | |
1117 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1118 | |
1119 | kfree(pciaddstr); | |
1120 | } | |
1121 | } | |
1122 | ||
e2a75f88 AD |
1123 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1124 | { | |
e2a75f88 AD |
1125 | const char *chip_name; |
1126 | char fw_name[30]; | |
1127 | int err; | |
1128 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1129 | ||
ab4fe3e1 HR |
1130 | adev->firmware.gpu_info_fw = NULL; |
1131 | ||
e2a75f88 AD |
1132 | switch (adev->asic_type) { |
1133 | case CHIP_TOPAZ: | |
1134 | case CHIP_TONGA: | |
1135 | case CHIP_FIJI: | |
1136 | case CHIP_POLARIS11: | |
1137 | case CHIP_POLARIS10: | |
1138 | case CHIP_POLARIS12: | |
1139 | case CHIP_CARRIZO: | |
1140 | case CHIP_STONEY: | |
1141 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1142 | case CHIP_VERDE: | |
1143 | case CHIP_TAHITI: | |
1144 | case CHIP_PITCAIRN: | |
1145 | case CHIP_OLAND: | |
1146 | case CHIP_HAINAN: | |
1147 | #endif | |
1148 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1149 | case CHIP_BONAIRE: | |
1150 | case CHIP_HAWAII: | |
1151 | case CHIP_KAVERI: | |
1152 | case CHIP_KABINI: | |
1153 | case CHIP_MULLINS: | |
1154 | #endif | |
1155 | default: | |
1156 | return 0; | |
1157 | case CHIP_VEGA10: | |
1158 | chip_name = "vega10"; | |
1159 | break; | |
2d2e5e7e AD |
1160 | case CHIP_RAVEN: |
1161 | chip_name = "raven"; | |
1162 | break; | |
e2a75f88 AD |
1163 | } |
1164 | ||
1165 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1166 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1167 | if (err) { |
1168 | dev_err(adev->dev, | |
1169 | "Failed to load gpu_info firmware \"%s\"\n", | |
1170 | fw_name); | |
1171 | goto out; | |
1172 | } | |
ab4fe3e1 | 1173 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1174 | if (err) { |
1175 | dev_err(adev->dev, | |
1176 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1177 | fw_name); | |
1178 | goto out; | |
1179 | } | |
1180 | ||
ab4fe3e1 | 1181 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1182 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1183 | ||
1184 | switch (hdr->version_major) { | |
1185 | case 1: | |
1186 | { | |
1187 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1188 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1189 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1190 | ||
b5ab16bf AD |
1191 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1192 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1193 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1194 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1195 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1196 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1197 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1198 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1199 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1200 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1201 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1202 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1203 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1204 | adev->gfx.cu_info.max_waves_per_simd = |
1205 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1206 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1207 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1208 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1209 | break; |
1210 | } | |
1211 | default: | |
1212 | dev_err(adev->dev, | |
1213 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1214 | err = -EINVAL; | |
1215 | goto out; | |
1216 | } | |
1217 | out: | |
e2a75f88 AD |
1218 | return err; |
1219 | } | |
1220 | ||
06ec9070 | 1221 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1222 | { |
aaa36a97 | 1223 | int i, r; |
d38ceaf9 | 1224 | |
483ef985 | 1225 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1226 | |
d38ceaf9 | 1227 | switch (adev->asic_type) { |
aaa36a97 AD |
1228 | case CHIP_TOPAZ: |
1229 | case CHIP_TONGA: | |
48299f95 | 1230 | case CHIP_FIJI: |
2cc0c0b5 FC |
1231 | case CHIP_POLARIS11: |
1232 | case CHIP_POLARIS10: | |
c4642a47 | 1233 | case CHIP_POLARIS12: |
aaa36a97 | 1234 | case CHIP_CARRIZO: |
39bb0c92 SL |
1235 | case CHIP_STONEY: |
1236 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1237 | adev->family = AMDGPU_FAMILY_CZ; |
1238 | else | |
1239 | adev->family = AMDGPU_FAMILY_VI; | |
1240 | ||
1241 | r = vi_set_ip_blocks(adev); | |
1242 | if (r) | |
1243 | return r; | |
1244 | break; | |
33f34802 KW |
1245 | #ifdef CONFIG_DRM_AMDGPU_SI |
1246 | case CHIP_VERDE: | |
1247 | case CHIP_TAHITI: | |
1248 | case CHIP_PITCAIRN: | |
1249 | case CHIP_OLAND: | |
1250 | case CHIP_HAINAN: | |
295d0daf | 1251 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1252 | r = si_set_ip_blocks(adev); |
1253 | if (r) | |
1254 | return r; | |
1255 | break; | |
1256 | #endif | |
a2e73f56 AD |
1257 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1258 | case CHIP_BONAIRE: | |
1259 | case CHIP_HAWAII: | |
1260 | case CHIP_KAVERI: | |
1261 | case CHIP_KABINI: | |
1262 | case CHIP_MULLINS: | |
1263 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1264 | adev->family = AMDGPU_FAMILY_CI; | |
1265 | else | |
1266 | adev->family = AMDGPU_FAMILY_KV; | |
1267 | ||
1268 | r = cik_set_ip_blocks(adev); | |
1269 | if (r) | |
1270 | return r; | |
1271 | break; | |
1272 | #endif | |
2ca8a5d2 CZ |
1273 | case CHIP_VEGA10: |
1274 | case CHIP_RAVEN: | |
1275 | if (adev->asic_type == CHIP_RAVEN) | |
1276 | adev->family = AMDGPU_FAMILY_RV; | |
1277 | else | |
1278 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1279 | |
1280 | r = soc15_set_ip_blocks(adev); | |
1281 | if (r) | |
1282 | return r; | |
1283 | break; | |
d38ceaf9 AD |
1284 | default: |
1285 | /* FIXME: not supported yet */ | |
1286 | return -EINVAL; | |
1287 | } | |
1288 | ||
e2a75f88 AD |
1289 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1290 | if (r) | |
1291 | return r; | |
1292 | ||
1884734a | 1293 | amdgpu_amdkfd_device_probe(adev); |
1294 | ||
3149d9da XY |
1295 | if (amdgpu_sriov_vf(adev)) { |
1296 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1297 | if (r) | |
5ffa61c1 | 1298 | return -EAGAIN; |
3149d9da XY |
1299 | } |
1300 | ||
d38ceaf9 AD |
1301 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1302 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1303 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1304 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1305 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1306 | } else { |
a1255107 AD |
1307 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1308 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1309 | if (r == -ENOENT) { |
a1255107 | 1310 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1311 | } else if (r) { |
a1255107 AD |
1312 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1313 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1314 | return r; |
2c1a2784 | 1315 | } else { |
a1255107 | 1316 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1317 | } |
974e6b64 | 1318 | } else { |
a1255107 | 1319 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1320 | } |
d38ceaf9 AD |
1321 | } |
1322 | } | |
1323 | ||
395d1fb9 NH |
1324 | adev->cg_flags &= amdgpu_cg_mask; |
1325 | adev->pg_flags &= amdgpu_pg_mask; | |
1326 | ||
d38ceaf9 AD |
1327 | return 0; |
1328 | } | |
1329 | ||
06ec9070 | 1330 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1331 | { |
1332 | int i, r; | |
1333 | ||
1334 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1335 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1336 | continue; |
a1255107 | 1337 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1338 | if (r) { |
a1255107 AD |
1339 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1340 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1341 | return r; |
2c1a2784 | 1342 | } |
a1255107 | 1343 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 1344 | |
d38ceaf9 | 1345 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1346 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 1347 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
1348 | if (r) { |
1349 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1350 | return r; |
2c1a2784 | 1351 | } |
a1255107 | 1352 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1353 | if (r) { |
1354 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1355 | return r; |
2c1a2784 | 1356 | } |
06ec9070 | 1357 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 1358 | if (r) { |
06ec9070 | 1359 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
d38ceaf9 | 1360 | return r; |
2c1a2784 | 1361 | } |
a1255107 | 1362 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1363 | |
1364 | /* right after GMC hw init, we create CSA */ | |
1365 | if (amdgpu_sriov_vf(adev)) { | |
1366 | r = amdgpu_allocate_static_csa(adev); | |
1367 | if (r) { | |
1368 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1369 | return r; | |
1370 | } | |
1371 | } | |
d38ceaf9 AD |
1372 | } |
1373 | } | |
1374 | ||
1375 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1376 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1377 | continue; |
bfca0289 | 1378 | if (adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1379 | continue; |
a1255107 | 1380 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1381 | if (r) { |
a1255107 AD |
1382 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1383 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1384 | return r; |
2c1a2784 | 1385 | } |
a1255107 | 1386 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1387 | } |
1388 | ||
1884734a | 1389 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1390 | |
1391 | if (amdgpu_sriov_vf(adev)) | |
1392 | amdgpu_virt_release_full_gpu(adev, true); | |
1393 | ||
d38ceaf9 AD |
1394 | return 0; |
1395 | } | |
1396 | ||
06ec9070 | 1397 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1398 | { |
1399 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1400 | } | |
1401 | ||
06ec9070 | 1402 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1403 | { |
1404 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1405 | AMDGPU_RESET_MAGIC_NUM); | |
1406 | } | |
1407 | ||
06ec9070 | 1408 | static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1409 | { |
1410 | int i = 0, r; | |
1411 | ||
4a2ba394 SL |
1412 | if (amdgpu_emu_mode == 1) |
1413 | return 0; | |
1414 | ||
d38ceaf9 | 1415 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 1416 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1417 | continue; |
4a446d55 | 1418 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1419 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1420 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1421 | /* enable clockgating to save power */ |
a1255107 AD |
1422 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1423 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1424 | if (r) { |
1425 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1426 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1427 | return r; |
1428 | } | |
b0b00ff1 | 1429 | } |
d38ceaf9 | 1430 | } |
2dc80b00 S |
1431 | return 0; |
1432 | } | |
1433 | ||
06ec9070 | 1434 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 S |
1435 | { |
1436 | int i = 0, r; | |
1437 | ||
1438 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1439 | if (!adev->ip_blocks[i].status.valid) | |
1440 | continue; | |
1441 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1442 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1443 | if (r) { | |
1444 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1445 | adev->ip_blocks[i].version->funcs->name, r); | |
1446 | return r; | |
1447 | } | |
1448 | adev->ip_blocks[i].status.late_initialized = true; | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1453 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1454 | |
06ec9070 | 1455 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 AD |
1456 | |
1457 | return 0; | |
1458 | } | |
1459 | ||
06ec9070 | 1460 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1461 | { |
1462 | int i, r; | |
1463 | ||
1884734a | 1464 | amdgpu_amdkfd_device_fini(adev); |
3e96dbfd AD |
1465 | /* need to disable SMC first */ |
1466 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1467 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1468 | continue; |
a1255107 | 1469 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1470 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1471 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1472 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1473 | if (r) { |
1474 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1475 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1476 | return r; |
1477 | } | |
a1255107 | 1478 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1479 | /* XXX handle errors */ |
1480 | if (r) { | |
1481 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1482 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1483 | } |
a1255107 | 1484 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1485 | break; |
1486 | } | |
1487 | } | |
1488 | ||
d38ceaf9 | 1489 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
edc3d27c ED |
1490 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC && |
1491 | adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) | |
1492 | amdgpu_ucode_fini_bo(adev); | |
a1255107 | 1493 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1494 | continue; |
8201a67a RZ |
1495 | |
1496 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1497 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1498 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1499 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1500 | AMD_CG_STATE_UNGATE); | |
1501 | if (r) { | |
1502 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1503 | adev->ip_blocks[i].version->funcs->name, r); | |
1504 | return r; | |
1505 | } | |
2c1a2784 | 1506 | } |
8201a67a | 1507 | |
a1255107 | 1508 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1509 | /* XXX handle errors */ |
2c1a2784 | 1510 | if (r) { |
a1255107 AD |
1511 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1512 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1513 | } |
8201a67a | 1514 | |
a1255107 | 1515 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1516 | } |
1517 | ||
9950cda2 AD |
1518 | /* disable all interrupts */ |
1519 | amdgpu_irq_disable_all(adev); | |
1520 | ||
d38ceaf9 | 1521 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1522 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1523 | continue; |
c12aba3a ML |
1524 | |
1525 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
1526 | amdgpu_free_static_csa(adev); | |
1527 | amdgpu_device_wb_fini(adev); | |
1528 | amdgpu_device_vram_scratch_fini(adev); | |
1529 | } | |
1530 | ||
a1255107 | 1531 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1532 | /* XXX handle errors */ |
2c1a2784 | 1533 | if (r) { |
a1255107 AD |
1534 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1535 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1536 | } |
a1255107 AD |
1537 | adev->ip_blocks[i].status.sw = false; |
1538 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1539 | } |
1540 | ||
a6dcfd9c | 1541 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1542 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1543 | continue; |
a1255107 AD |
1544 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1545 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1546 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1547 | } |
1548 | ||
030308fc | 1549 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
1550 | if (amdgpu_virt_release_full_gpu(adev, false)) |
1551 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 1552 | |
d38ceaf9 AD |
1553 | return 0; |
1554 | } | |
1555 | ||
06ec9070 | 1556 | static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) |
2dc80b00 S |
1557 | { |
1558 | struct amdgpu_device *adev = | |
1559 | container_of(work, struct amdgpu_device, late_init_work.work); | |
06ec9070 | 1560 | amdgpu_device_ip_late_set_cg_state(adev); |
2dc80b00 S |
1561 | } |
1562 | ||
cdd61df6 | 1563 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1564 | { |
1565 | int i, r; | |
1566 | ||
e941ea99 XY |
1567 | if (amdgpu_sriov_vf(adev)) |
1568 | amdgpu_virt_request_full_gpu(adev, false); | |
1569 | ||
c5a93a28 | 1570 | /* ungate SMC block first */ |
2990a1fc AD |
1571 | r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, |
1572 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1573 | if (r) { |
2990a1fc | 1574 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r); |
c5a93a28 FC |
1575 | } |
1576 | ||
d38ceaf9 | 1577 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1578 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1579 | continue; |
1580 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1581 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1582 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1583 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1584 | if (r) { |
a1255107 AD |
1585 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1586 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1587 | } |
2c1a2784 | 1588 | } |
d38ceaf9 | 1589 | /* XXX handle errors */ |
a1255107 | 1590 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1591 | /* XXX handle errors */ |
2c1a2784 | 1592 | if (r) { |
a1255107 AD |
1593 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1594 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1595 | } |
d38ceaf9 AD |
1596 | } |
1597 | ||
e941ea99 XY |
1598 | if (amdgpu_sriov_vf(adev)) |
1599 | amdgpu_virt_release_full_gpu(adev, false); | |
1600 | ||
d38ceaf9 AD |
1601 | return 0; |
1602 | } | |
1603 | ||
06ec9070 | 1604 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1605 | { |
1606 | int i, r; | |
1607 | ||
2cb681b6 ML |
1608 | static enum amd_ip_block_type ip_order[] = { |
1609 | AMD_IP_BLOCK_TYPE_GMC, | |
1610 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1611 | AMD_IP_BLOCK_TYPE_IH, |
1612 | }; | |
a90ad3c2 | 1613 | |
2cb681b6 ML |
1614 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1615 | int j; | |
1616 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1617 | |
2cb681b6 ML |
1618 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1619 | block = &adev->ip_blocks[j]; | |
1620 | ||
1621 | if (block->version->type != ip_order[i] || | |
1622 | !block->status.valid) | |
1623 | continue; | |
1624 | ||
1625 | r = block->version->funcs->hw_init(adev); | |
1626 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
c41d1cf6 ML |
1627 | if (r) |
1628 | return r; | |
a90ad3c2 ML |
1629 | } |
1630 | } | |
1631 | ||
1632 | return 0; | |
1633 | } | |
1634 | ||
06ec9070 | 1635 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1636 | { |
1637 | int i, r; | |
1638 | ||
2cb681b6 ML |
1639 | static enum amd_ip_block_type ip_order[] = { |
1640 | AMD_IP_BLOCK_TYPE_SMC, | |
ef4c166d | 1641 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
1642 | AMD_IP_BLOCK_TYPE_DCE, |
1643 | AMD_IP_BLOCK_TYPE_GFX, | |
1644 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
1645 | AMD_IP_BLOCK_TYPE_UVD, |
1646 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 1647 | }; |
a90ad3c2 | 1648 | |
2cb681b6 ML |
1649 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1650 | int j; | |
1651 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1652 | |
2cb681b6 ML |
1653 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1654 | block = &adev->ip_blocks[j]; | |
1655 | ||
1656 | if (block->version->type != ip_order[i] || | |
1657 | !block->status.valid) | |
1658 | continue; | |
1659 | ||
1660 | r = block->version->funcs->hw_init(adev); | |
1661 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
c41d1cf6 ML |
1662 | if (r) |
1663 | return r; | |
a90ad3c2 ML |
1664 | } |
1665 | } | |
1666 | ||
1667 | return 0; | |
1668 | } | |
1669 | ||
06ec9070 | 1670 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1671 | { |
1672 | int i, r; | |
1673 | ||
a90ad3c2 ML |
1674 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1675 | if (!adev->ip_blocks[i].status.valid) | |
1676 | continue; | |
a90ad3c2 ML |
1677 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1678 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
fcf0649f CZ |
1679 | adev->ip_blocks[i].version->type == |
1680 | AMD_IP_BLOCK_TYPE_IH) { | |
1681 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1682 | if (r) { | |
1683 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1684 | adev->ip_blocks[i].version->funcs->name, r); | |
1685 | return r; | |
1686 | } | |
a90ad3c2 ML |
1687 | } |
1688 | } | |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
06ec9070 | 1693 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
1694 | { |
1695 | int i, r; | |
1696 | ||
1697 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1698 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1699 | continue; |
fcf0649f CZ |
1700 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1701 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1702 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1703 | continue; | |
a1255107 | 1704 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1705 | if (r) { |
a1255107 AD |
1706 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1707 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1708 | return r; |
2c1a2784 | 1709 | } |
d38ceaf9 AD |
1710 | } |
1711 | ||
1712 | return 0; | |
1713 | } | |
1714 | ||
06ec9070 | 1715 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
1716 | { |
1717 | int r; | |
1718 | ||
06ec9070 | 1719 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
1720 | if (r) |
1721 | return r; | |
06ec9070 | 1722 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
1723 | |
1724 | return r; | |
1725 | } | |
1726 | ||
4e99a44e | 1727 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1728 | { |
6867e1b5 ML |
1729 | if (amdgpu_sriov_vf(adev)) { |
1730 | if (adev->is_atom_fw) { | |
1731 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
1732 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1733 | } else { | |
1734 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
1735 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1736 | } | |
1737 | ||
1738 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
1739 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 1740 | } |
048765ad AR |
1741 | } |
1742 | ||
4562236b HW |
1743 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
1744 | { | |
1745 | switch (asic_type) { | |
1746 | #if defined(CONFIG_DRM_AMD_DC) | |
1747 | case CHIP_BONAIRE: | |
1748 | case CHIP_HAWAII: | |
0d6fbccb | 1749 | case CHIP_KAVERI: |
367e6687 AD |
1750 | case CHIP_KABINI: |
1751 | case CHIP_MULLINS: | |
4562236b HW |
1752 | case CHIP_CARRIZO: |
1753 | case CHIP_STONEY: | |
1754 | case CHIP_POLARIS11: | |
1755 | case CHIP_POLARIS10: | |
2c8ad2d5 | 1756 | case CHIP_POLARIS12: |
4562236b HW |
1757 | case CHIP_TONGA: |
1758 | case CHIP_FIJI: | |
1759 | #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) | |
1760 | return amdgpu_dc != 0; | |
4562236b | 1761 | #endif |
42f8ffa1 HW |
1762 | case CHIP_VEGA10: |
1763 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | |
fd187853 | 1764 | case CHIP_RAVEN: |
42f8ffa1 | 1765 | #endif |
fd187853 | 1766 | return amdgpu_dc != 0; |
4562236b HW |
1767 | #endif |
1768 | default: | |
1769 | return false; | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | /** | |
1774 | * amdgpu_device_has_dc_support - check if dc is supported | |
1775 | * | |
1776 | * @adev: amdgpu_device_pointer | |
1777 | * | |
1778 | * Returns true for supported, false for not supported | |
1779 | */ | |
1780 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
1781 | { | |
2555039d XY |
1782 | if (amdgpu_sriov_vf(adev)) |
1783 | return false; | |
1784 | ||
4562236b HW |
1785 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
1786 | } | |
1787 | ||
d38ceaf9 AD |
1788 | /** |
1789 | * amdgpu_device_init - initialize the driver | |
1790 | * | |
1791 | * @adev: amdgpu_device pointer | |
1792 | * @pdev: drm dev pointer | |
1793 | * @pdev: pci dev pointer | |
1794 | * @flags: driver flags | |
1795 | * | |
1796 | * Initializes the driver info and hw (all asics). | |
1797 | * Returns 0 for success or an error on failure. | |
1798 | * Called at driver startup. | |
1799 | */ | |
1800 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1801 | struct drm_device *ddev, | |
1802 | struct pci_dev *pdev, | |
1803 | uint32_t flags) | |
1804 | { | |
1805 | int r, i; | |
1806 | bool runtime = false; | |
95844d20 | 1807 | u32 max_MBps; |
d38ceaf9 AD |
1808 | |
1809 | adev->shutdown = false; | |
1810 | adev->dev = &pdev->dev; | |
1811 | adev->ddev = ddev; | |
1812 | adev->pdev = pdev; | |
1813 | adev->flags = flags; | |
2f7d10b3 | 1814 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 1815 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 SL |
1816 | if (amdgpu_emu_mode == 1) |
1817 | adev->usec_timeout *= 2; | |
770d13b1 | 1818 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
1819 | adev->accel_working = false; |
1820 | adev->num_rings = 0; | |
1821 | adev->mman.buffer_funcs = NULL; | |
1822 | adev->mman.buffer_funcs_ring = NULL; | |
1823 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1824 | adev->vm_manager.vm_pte_num_rings = 0; |
132f34e4 | 1825 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 1826 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 1827 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
1828 | |
1829 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1830 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1831 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1832 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
1833 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
1834 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1835 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
1836 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1837 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1838 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
1839 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
1840 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1841 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
1842 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1843 | ||
3e39ab90 AD |
1844 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1845 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1846 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1847 | |
1848 | /* mutex initialization are all done here so we | |
1849 | * can recall function without having locking issues */ | |
d38ceaf9 | 1850 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 1851 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
1852 | mutex_init(&adev->pm.mutex); |
1853 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1854 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 1855 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d38ceaf9 | 1856 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 1857 | mutex_init(&adev->mn_lock); |
e23b74aa | 1858 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 1859 | hash_init(adev->mn_hash); |
13a752e3 | 1860 | mutex_init(&adev->lock_reset); |
d38ceaf9 | 1861 | |
06ec9070 | 1862 | amdgpu_device_check_arguments(adev); |
d38ceaf9 | 1863 | |
d38ceaf9 AD |
1864 | spin_lock_init(&adev->mmio_idx_lock); |
1865 | spin_lock_init(&adev->smc_idx_lock); | |
1866 | spin_lock_init(&adev->pcie_idx_lock); | |
1867 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1868 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 1869 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 1870 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 1871 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 1872 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 1873 | |
0c4e7fa5 CZ |
1874 | INIT_LIST_HEAD(&adev->shadow_list); |
1875 | mutex_init(&adev->shadow_list_lock); | |
1876 | ||
795f2813 AR |
1877 | INIT_LIST_HEAD(&adev->ring_lru_list); |
1878 | spin_lock_init(&adev->ring_lru_list_lock); | |
1879 | ||
06ec9070 AD |
1880 | INIT_DELAYED_WORK(&adev->late_init_work, |
1881 | amdgpu_device_ip_late_init_func_handler); | |
2dc80b00 | 1882 | |
0fa49558 AX |
1883 | /* Registers mapping */ |
1884 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
1885 | if (adev->asic_type >= CHIP_BONAIRE) { |
1886 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1887 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1888 | } else { | |
1889 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
1890 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
1891 | } | |
d38ceaf9 | 1892 | |
d38ceaf9 AD |
1893 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
1894 | if (adev->rmmio == NULL) { | |
1895 | return -ENOMEM; | |
1896 | } | |
1897 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1898 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1899 | ||
705e519e | 1900 | /* doorbell bar mapping */ |
06ec9070 | 1901 | amdgpu_device_doorbell_init(adev); |
d38ceaf9 AD |
1902 | |
1903 | /* io port mapping */ | |
1904 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1905 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1906 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1907 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1908 | break; | |
1909 | } | |
1910 | } | |
1911 | if (adev->rio_mem == NULL) | |
b64a18c5 | 1912 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 1913 | |
5494d864 AD |
1914 | amdgpu_device_get_pcie_info(adev); |
1915 | ||
d38ceaf9 | 1916 | /* early init functions */ |
06ec9070 | 1917 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
1918 | if (r) |
1919 | return r; | |
1920 | ||
1921 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1922 | /* this will fail for cards that aren't VGA class devices, just | |
1923 | * ignore it */ | |
06ec9070 | 1924 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 1925 | |
e9bef455 | 1926 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 1927 | runtime = true; |
84c8b22e LW |
1928 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
1929 | vga_switcheroo_register_client(adev->pdev, | |
1930 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
1931 | if (runtime) |
1932 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1933 | ||
9475a943 SL |
1934 | if (amdgpu_emu_mode == 1) { |
1935 | /* post the asic on emulation mode */ | |
1936 | emu_soc_asic_init(adev); | |
bfca0289 | 1937 | goto fence_driver_init; |
9475a943 | 1938 | } |
bfca0289 | 1939 | |
d38ceaf9 | 1940 | /* Read BIOS */ |
83ba126a AD |
1941 | if (!amdgpu_get_bios(adev)) { |
1942 | r = -EINVAL; | |
1943 | goto failed; | |
1944 | } | |
f7e9e9fe | 1945 | |
d38ceaf9 | 1946 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
1947 | if (r) { |
1948 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
e23b74aa | 1949 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 1950 | goto failed; |
2c1a2784 | 1951 | } |
d38ceaf9 | 1952 | |
4e99a44e ML |
1953 | /* detect if we are with an SRIOV vbios */ |
1954 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 1955 | |
d38ceaf9 | 1956 | /* Post card if necessary */ |
39c640c0 | 1957 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 1958 | if (!adev->bios) { |
bec86378 | 1959 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
1960 | r = -EINVAL; |
1961 | goto failed; | |
d38ceaf9 | 1962 | } |
bec86378 | 1963 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
1964 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
1965 | if (r) { | |
1966 | dev_err(adev->dev, "gpu post error!\n"); | |
1967 | goto failed; | |
1968 | } | |
d38ceaf9 AD |
1969 | } |
1970 | ||
88b64e95 AD |
1971 | if (adev->is_atom_fw) { |
1972 | /* Initialize clocks */ | |
1973 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
1974 | if (r) { | |
1975 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 1976 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
1977 | goto failed; |
1978 | } | |
1979 | } else { | |
a5bde2f9 AD |
1980 | /* Initialize clocks */ |
1981 | r = amdgpu_atombios_get_clock_info(adev); | |
1982 | if (r) { | |
1983 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 1984 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 1985 | goto failed; |
a5bde2f9 AD |
1986 | } |
1987 | /* init i2c buses */ | |
4562236b HW |
1988 | if (!amdgpu_device_has_dc_support(adev)) |
1989 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 1990 | } |
d38ceaf9 | 1991 | |
bfca0289 | 1992 | fence_driver_init: |
d38ceaf9 AD |
1993 | /* Fence driver */ |
1994 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1995 | if (r) { |
1996 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 1997 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 1998 | goto failed; |
2c1a2784 | 1999 | } |
d38ceaf9 AD |
2000 | |
2001 | /* init the mode config */ | |
2002 | drm_mode_config_init(adev->ddev); | |
2003 | ||
06ec9070 | 2004 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 2005 | if (r) { |
8840a387 | 2006 | /* failed in exclusive mode due to timeout */ |
2007 | if (amdgpu_sriov_vf(adev) && | |
2008 | !amdgpu_sriov_runtime(adev) && | |
2009 | amdgpu_virt_mmio_blocked(adev) && | |
2010 | !amdgpu_virt_wait_reset(adev)) { | |
2011 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
2012 | /* Don't send request since VF is inactive. */ |
2013 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
2014 | adev->virt.ops = NULL; | |
8840a387 | 2015 | r = -EAGAIN; |
2016 | goto failed; | |
2017 | } | |
06ec9070 | 2018 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 2019 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
06ec9070 | 2020 | amdgpu_device_ip_fini(adev); |
83ba126a | 2021 | goto failed; |
d38ceaf9 AD |
2022 | } |
2023 | ||
2024 | adev->accel_working = true; | |
2025 | ||
e59c0205 AX |
2026 | amdgpu_vm_check_compute_bug(adev); |
2027 | ||
95844d20 MO |
2028 | /* Initialize the buffer migration limit. */ |
2029 | if (amdgpu_moverate >= 0) | |
2030 | max_MBps = amdgpu_moverate; | |
2031 | else | |
2032 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2033 | /* Get a log2 for easy divisions. */ | |
2034 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2035 | ||
d38ceaf9 AD |
2036 | r = amdgpu_ib_pool_init(adev); |
2037 | if (r) { | |
2038 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
e23b74aa | 2039 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2040 | goto failed; |
d38ceaf9 AD |
2041 | } |
2042 | ||
2043 | r = amdgpu_ib_ring_tests(adev); | |
2044 | if (r) | |
2045 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2046 | ||
2dc8f81e HC |
2047 | if (amdgpu_sriov_vf(adev)) |
2048 | amdgpu_virt_init_data_exchange(adev); | |
2049 | ||
9bc92b9c ML |
2050 | amdgpu_fbdev_init(adev); |
2051 | ||
d2f52ac8 RZ |
2052 | r = amdgpu_pm_sysfs_init(adev); |
2053 | if (r) | |
2054 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2055 | ||
75758255 | 2056 | r = amdgpu_debugfs_gem_init(adev); |
3f14e623 | 2057 | if (r) |
d38ceaf9 | 2058 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2059 | |
2060 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2061 | if (r) |
d38ceaf9 | 2062 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2063 | |
50ab2533 | 2064 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2065 | if (r) |
50ab2533 | 2066 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2067 | |
763efb6c | 2068 | r = amdgpu_debugfs_init(adev); |
db95e218 | 2069 | if (r) |
763efb6c | 2070 | DRM_ERROR("Creating debugfs files failed (%d).\n", r); |
db95e218 | 2071 | |
d38ceaf9 AD |
2072 | if ((amdgpu_testing & 1)) { |
2073 | if (adev->accel_working) | |
2074 | amdgpu_test_moves(adev); | |
2075 | else | |
2076 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2077 | } | |
d38ceaf9 AD |
2078 | if (amdgpu_benchmarking) { |
2079 | if (adev->accel_working) | |
2080 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2081 | else | |
2082 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2083 | } | |
2084 | ||
2085 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2086 | * explicit gating rather than handling it automatically. | |
2087 | */ | |
06ec9070 | 2088 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 2089 | if (r) { |
06ec9070 | 2090 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 2091 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2092 | goto failed; |
2c1a2784 | 2093 | } |
d38ceaf9 AD |
2094 | |
2095 | return 0; | |
83ba126a AD |
2096 | |
2097 | failed: | |
89041940 | 2098 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2099 | if (runtime) |
2100 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 2101 | |
83ba126a | 2102 | return r; |
d38ceaf9 AD |
2103 | } |
2104 | ||
d38ceaf9 AD |
2105 | /** |
2106 | * amdgpu_device_fini - tear down the driver | |
2107 | * | |
2108 | * @adev: amdgpu_device pointer | |
2109 | * | |
2110 | * Tear down the driver info (all asics). | |
2111 | * Called at driver shutdown. | |
2112 | */ | |
2113 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2114 | { | |
2115 | int r; | |
2116 | ||
2117 | DRM_INFO("amdgpu: finishing device.\n"); | |
2118 | adev->shutdown = true; | |
db2c2a97 PD |
2119 | if (adev->mode_info.mode_config_initialized) |
2120 | drm_crtc_force_disable_all(adev->ddev); | |
b9141cd3 | 2121 | |
d38ceaf9 AD |
2122 | amdgpu_ib_pool_fini(adev); |
2123 | amdgpu_fence_driver_fini(adev); | |
58e955d9 | 2124 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2125 | amdgpu_fbdev_fini(adev); |
06ec9070 | 2126 | r = amdgpu_device_ip_fini(adev); |
ab4fe3e1 HR |
2127 | if (adev->firmware.gpu_info_fw) { |
2128 | release_firmware(adev->firmware.gpu_info_fw); | |
2129 | adev->firmware.gpu_info_fw = NULL; | |
2130 | } | |
d38ceaf9 | 2131 | adev->accel_working = false; |
2dc80b00 | 2132 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 | 2133 | /* free i2c buses */ |
4562236b HW |
2134 | if (!amdgpu_device_has_dc_support(adev)) |
2135 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
2136 | |
2137 | if (amdgpu_emu_mode != 1) | |
2138 | amdgpu_atombios_fini(adev); | |
2139 | ||
d38ceaf9 AD |
2140 | kfree(adev->bios); |
2141 | adev->bios = NULL; | |
84c8b22e LW |
2142 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2143 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2144 | if (adev->flags & AMD_IS_PX) |
2145 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2146 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2147 | if (adev->rio_mem) | |
2148 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2149 | adev->rio_mem = NULL; | |
2150 | iounmap(adev->rmmio); | |
2151 | adev->rmmio = NULL; | |
06ec9070 | 2152 | amdgpu_device_doorbell_fini(adev); |
d38ceaf9 | 2153 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2154 | } |
2155 | ||
2156 | ||
2157 | /* | |
2158 | * Suspend & resume. | |
2159 | */ | |
2160 | /** | |
810ddc3a | 2161 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2162 | * |
2163 | * @pdev: drm dev pointer | |
2164 | * @state: suspend state | |
2165 | * | |
2166 | * Puts the hw in the suspend state (all asics). | |
2167 | * Returns 0 for success or an error on failure. | |
2168 | * Called at driver suspend. | |
2169 | */ | |
810ddc3a | 2170 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2171 | { |
2172 | struct amdgpu_device *adev; | |
2173 | struct drm_crtc *crtc; | |
2174 | struct drm_connector *connector; | |
5ceb54c6 | 2175 | int r; |
d38ceaf9 AD |
2176 | |
2177 | if (dev == NULL || dev->dev_private == NULL) { | |
2178 | return -ENODEV; | |
2179 | } | |
2180 | ||
2181 | adev = dev->dev_private; | |
2182 | ||
2183 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2184 | return 0; | |
2185 | ||
2186 | drm_kms_helper_poll_disable(dev); | |
2187 | ||
4562236b HW |
2188 | if (!amdgpu_device_has_dc_support(adev)) { |
2189 | /* turn off display hw */ | |
2190 | drm_modeset_lock_all(dev); | |
2191 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2192 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2193 | } | |
2194 | drm_modeset_unlock_all(dev); | |
d38ceaf9 AD |
2195 | } |
2196 | ||
ba997709 YZ |
2197 | amdgpu_amdkfd_suspend(adev); |
2198 | ||
756e6880 | 2199 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2200 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2201 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2202 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2203 | struct amdgpu_bo *robj; | |
2204 | ||
756e6880 AD |
2205 | if (amdgpu_crtc->cursor_bo) { |
2206 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2207 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2208 | if (r == 0) { |
2209 | amdgpu_bo_unpin(aobj); | |
2210 | amdgpu_bo_unreserve(aobj); | |
2211 | } | |
2212 | } | |
2213 | ||
d38ceaf9 AD |
2214 | if (rfb == NULL || rfb->obj == NULL) { |
2215 | continue; | |
2216 | } | |
2217 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2218 | /* don't unpin kernel fb objects */ | |
2219 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2220 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2221 | if (r == 0) { |
2222 | amdgpu_bo_unpin(robj); | |
2223 | amdgpu_bo_unreserve(robj); | |
2224 | } | |
2225 | } | |
2226 | } | |
2227 | /* evict vram memory */ | |
2228 | amdgpu_bo_evict_vram(adev); | |
2229 | ||
5ceb54c6 | 2230 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 2231 | |
cdd61df6 | 2232 | r = amdgpu_device_ip_suspend(adev); |
d38ceaf9 | 2233 | |
a0a71e49 AD |
2234 | /* evict remaining vram memory |
2235 | * This second call to evict vram is to evict the gart page table | |
2236 | * using the CPU. | |
2237 | */ | |
d38ceaf9 AD |
2238 | amdgpu_bo_evict_vram(adev); |
2239 | ||
2240 | pci_save_state(dev->pdev); | |
2241 | if (suspend) { | |
2242 | /* Shut down the device */ | |
2243 | pci_disable_device(dev->pdev); | |
2244 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2245 | } else { |
2246 | r = amdgpu_asic_reset(adev); | |
2247 | if (r) | |
2248 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2249 | } |
2250 | ||
2251 | if (fbcon) { | |
2252 | console_lock(); | |
2253 | amdgpu_fbdev_set_suspend(adev, 1); | |
2254 | console_unlock(); | |
2255 | } | |
2256 | return 0; | |
2257 | } | |
2258 | ||
2259 | /** | |
810ddc3a | 2260 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2261 | * |
2262 | * @pdev: drm dev pointer | |
2263 | * | |
2264 | * Bring the hw back to operating state (all asics). | |
2265 | * Returns 0 for success or an error on failure. | |
2266 | * Called at driver resume. | |
2267 | */ | |
810ddc3a | 2268 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2269 | { |
2270 | struct drm_connector *connector; | |
2271 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2272 | struct drm_crtc *crtc; |
03161a6e | 2273 | int r = 0; |
d38ceaf9 AD |
2274 | |
2275 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2276 | return 0; | |
2277 | ||
74b0b157 | 2278 | if (fbcon) |
d38ceaf9 | 2279 | console_lock(); |
74b0b157 | 2280 | |
d38ceaf9 AD |
2281 | if (resume) { |
2282 | pci_set_power_state(dev->pdev, PCI_D0); | |
2283 | pci_restore_state(dev->pdev); | |
74b0b157 | 2284 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2285 | if (r) |
2286 | goto unlock; | |
d38ceaf9 AD |
2287 | } |
2288 | ||
2289 | /* post card */ | |
39c640c0 | 2290 | if (amdgpu_device_need_post(adev)) { |
74b0b157 | 2291 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2292 | if (r) | |
2293 | DRM_ERROR("amdgpu asic init failed\n"); | |
2294 | } | |
d38ceaf9 | 2295 | |
06ec9070 | 2296 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 2297 | if (r) { |
06ec9070 | 2298 | DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); |
03161a6e | 2299 | goto unlock; |
e6707218 | 2300 | } |
5ceb54c6 AD |
2301 | amdgpu_fence_driver_resume(adev); |
2302 | ||
ca198528 FC |
2303 | if (resume) { |
2304 | r = amdgpu_ib_ring_tests(adev); | |
2305 | if (r) | |
2306 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2307 | } | |
d38ceaf9 | 2308 | |
06ec9070 | 2309 | r = amdgpu_device_ip_late_init(adev); |
03161a6e HR |
2310 | if (r) |
2311 | goto unlock; | |
d38ceaf9 | 2312 | |
756e6880 AD |
2313 | /* pin cursors */ |
2314 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2315 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2316 | ||
2317 | if (amdgpu_crtc->cursor_bo) { | |
2318 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2319 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2320 | if (r == 0) { |
2321 | r = amdgpu_bo_pin(aobj, | |
2322 | AMDGPU_GEM_DOMAIN_VRAM, | |
2323 | &amdgpu_crtc->cursor_addr); | |
2324 | if (r != 0) | |
2325 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2326 | amdgpu_bo_unreserve(aobj); | |
2327 | } | |
2328 | } | |
2329 | } | |
ba997709 YZ |
2330 | r = amdgpu_amdkfd_resume(adev); |
2331 | if (r) | |
2332 | return r; | |
756e6880 | 2333 | |
d38ceaf9 AD |
2334 | /* blat the mode back in */ |
2335 | if (fbcon) { | |
4562236b HW |
2336 | if (!amdgpu_device_has_dc_support(adev)) { |
2337 | /* pre DCE11 */ | |
2338 | drm_helper_resume_force_mode(dev); | |
2339 | ||
2340 | /* turn on display hw */ | |
2341 | drm_modeset_lock_all(dev); | |
2342 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2343 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2344 | } | |
2345 | drm_modeset_unlock_all(dev); | |
d38ceaf9 AD |
2346 | } |
2347 | } | |
2348 | ||
2349 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2350 | |
2351 | /* | |
2352 | * Most of the connector probing functions try to acquire runtime pm | |
2353 | * refs to ensure that the GPU is powered on when connector polling is | |
2354 | * performed. Since we're calling this from a runtime PM callback, | |
2355 | * trying to acquire rpm refs will cause us to deadlock. | |
2356 | * | |
2357 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2358 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2359 | */ | |
2360 | #ifdef CONFIG_PM | |
2361 | dev->dev->power.disable_depth++; | |
2362 | #endif | |
4562236b HW |
2363 | if (!amdgpu_device_has_dc_support(adev)) |
2364 | drm_helper_hpd_irq_event(dev); | |
2365 | else | |
2366 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
2367 | #ifdef CONFIG_PM |
2368 | dev->dev->power.disable_depth--; | |
2369 | #endif | |
d38ceaf9 | 2370 | |
03161a6e | 2371 | if (fbcon) |
d38ceaf9 | 2372 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2373 | |
2374 | unlock: | |
2375 | if (fbcon) | |
d38ceaf9 | 2376 | console_unlock(); |
d38ceaf9 | 2377 | |
03161a6e | 2378 | return r; |
d38ceaf9 AD |
2379 | } |
2380 | ||
06ec9070 | 2381 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
2382 | { |
2383 | int i; | |
2384 | bool asic_hang = false; | |
2385 | ||
f993d628 ML |
2386 | if (amdgpu_sriov_vf(adev)) |
2387 | return true; | |
2388 | ||
63fbf42f | 2389 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2390 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2391 | continue; |
a1255107 AD |
2392 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2393 | adev->ip_blocks[i].status.hang = | |
2394 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2395 | if (adev->ip_blocks[i].status.hang) { | |
2396 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2397 | asic_hang = true; |
2398 | } | |
2399 | } | |
2400 | return asic_hang; | |
2401 | } | |
2402 | ||
06ec9070 | 2403 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2404 | { |
2405 | int i, r = 0; | |
2406 | ||
2407 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2408 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2409 | continue; |
a1255107 AD |
2410 | if (adev->ip_blocks[i].status.hang && |
2411 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2412 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2413 | if (r) |
2414 | return r; | |
2415 | } | |
2416 | } | |
2417 | ||
2418 | return 0; | |
2419 | } | |
2420 | ||
06ec9070 | 2421 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 2422 | { |
da146d3b AD |
2423 | int i; |
2424 | ||
2425 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2426 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2427 | continue; |
a1255107 AD |
2428 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2429 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2430 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
2431 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
2432 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 2433 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
2434 | DRM_INFO("Some block need full reset!\n"); |
2435 | return true; | |
2436 | } | |
2437 | } | |
35d782fe CZ |
2438 | } |
2439 | return false; | |
2440 | } | |
2441 | ||
06ec9070 | 2442 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2443 | { |
2444 | int i, r = 0; | |
2445 | ||
2446 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2447 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2448 | continue; |
a1255107 AD |
2449 | if (adev->ip_blocks[i].status.hang && |
2450 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2451 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2452 | if (r) |
2453 | return r; | |
2454 | } | |
2455 | } | |
2456 | ||
2457 | return 0; | |
2458 | } | |
2459 | ||
06ec9070 | 2460 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2461 | { |
2462 | int i, r = 0; | |
2463 | ||
2464 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2465 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2466 | continue; |
a1255107 AD |
2467 | if (adev->ip_blocks[i].status.hang && |
2468 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2469 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2470 | if (r) |
2471 | return r; | |
2472 | } | |
2473 | ||
2474 | return 0; | |
2475 | } | |
2476 | ||
06ec9070 AD |
2477 | static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev, |
2478 | struct amdgpu_ring *ring, | |
2479 | struct amdgpu_bo *bo, | |
2480 | struct dma_fence **fence) | |
53cdccd5 CZ |
2481 | { |
2482 | uint32_t domain; | |
2483 | int r; | |
2484 | ||
23d2e504 RH |
2485 | if (!bo->shadow) |
2486 | return 0; | |
2487 | ||
1d284797 | 2488 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2489 | if (r) |
2490 | return r; | |
2491 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2492 | /* if bo has been evicted, then no need to recover */ | |
2493 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2494 | r = amdgpu_bo_validate(bo->shadow); |
2495 | if (r) { | |
2496 | DRM_ERROR("bo validate failed!\n"); | |
2497 | goto err; | |
2498 | } | |
2499 | ||
23d2e504 | 2500 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2501 | NULL, fence, true); |
23d2e504 RH |
2502 | if (r) { |
2503 | DRM_ERROR("recover page table failed!\n"); | |
2504 | goto err; | |
2505 | } | |
2506 | } | |
53cdccd5 | 2507 | err: |
23d2e504 RH |
2508 | amdgpu_bo_unreserve(bo); |
2509 | return r; | |
53cdccd5 CZ |
2510 | } |
2511 | ||
c41d1cf6 ML |
2512 | static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev) |
2513 | { | |
2514 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2515 | struct amdgpu_bo *bo, *tmp; | |
2516 | struct dma_fence *fence = NULL, *next = NULL; | |
2517 | long r = 1; | |
2518 | int i = 0; | |
2519 | long tmo; | |
2520 | ||
2521 | if (amdgpu_sriov_runtime(adev)) | |
2522 | tmo = msecs_to_jiffies(amdgpu_lockup_timeout); | |
2523 | else | |
2524 | tmo = msecs_to_jiffies(100); | |
2525 | ||
2526 | DRM_INFO("recover vram bo from shadow start\n"); | |
2527 | mutex_lock(&adev->shadow_list_lock); | |
2528 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2529 | next = NULL; | |
2530 | amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next); | |
2531 | if (fence) { | |
2532 | r = dma_fence_wait_timeout(fence, false, tmo); | |
2533 | if (r == 0) | |
2534 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
2535 | else if (r < 0) | |
2536 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
2537 | if (r < 1) { | |
2538 | dma_fence_put(fence); | |
2539 | fence = next; | |
2540 | break; | |
2541 | } | |
2542 | i++; | |
2543 | } | |
2544 | ||
2545 | dma_fence_put(fence); | |
2546 | fence = next; | |
2547 | } | |
2548 | mutex_unlock(&adev->shadow_list_lock); | |
2549 | ||
2550 | if (fence) { | |
2551 | r = dma_fence_wait_timeout(fence, false, tmo); | |
2552 | if (r == 0) | |
2553 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
2554 | else if (r < 0) | |
2555 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
2556 | ||
2557 | } | |
2558 | dma_fence_put(fence); | |
2559 | ||
2560 | if (r > 0) | |
2561 | DRM_INFO("recover vram bo from shadow done\n"); | |
2562 | else | |
2563 | DRM_ERROR("recover vram bo from shadow failed\n"); | |
2564 | ||
2565 | return (r > 0?0:1); | |
2566 | } | |
2567 | ||
5740682e | 2568 | /* |
06ec9070 | 2569 | * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough |
a90ad3c2 ML |
2570 | * |
2571 | * @adev: amdgpu device pointer | |
a90ad3c2 | 2572 | * |
5740682e ML |
2573 | * attempt to do soft-reset or full-reset and reinitialize Asic |
2574 | * return 0 means successed otherwise failed | |
2575 | */ | |
c41d1cf6 | 2576 | static int amdgpu_device_reset(struct amdgpu_device *adev) |
a90ad3c2 | 2577 | { |
5740682e ML |
2578 | bool need_full_reset, vram_lost = 0; |
2579 | int r; | |
a90ad3c2 | 2580 | |
06ec9070 | 2581 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); |
a90ad3c2 | 2582 | |
5740682e | 2583 | if (!need_full_reset) { |
06ec9070 AD |
2584 | amdgpu_device_ip_pre_soft_reset(adev); |
2585 | r = amdgpu_device_ip_soft_reset(adev); | |
2586 | amdgpu_device_ip_post_soft_reset(adev); | |
2587 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
5740682e ML |
2588 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); |
2589 | need_full_reset = true; | |
2590 | } | |
5740682e | 2591 | } |
a90ad3c2 | 2592 | |
5740682e | 2593 | if (need_full_reset) { |
cdd61df6 | 2594 | r = amdgpu_device_ip_suspend(adev); |
a90ad3c2 | 2595 | |
5740682e | 2596 | retry: |
5740682e | 2597 | r = amdgpu_asic_reset(adev); |
5740682e ML |
2598 | /* post card */ |
2599 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
65781c78 | 2600 | |
5740682e ML |
2601 | if (!r) { |
2602 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
06ec9070 | 2603 | r = amdgpu_device_ip_resume_phase1(adev); |
5740682e ML |
2604 | if (r) |
2605 | goto out; | |
65781c78 | 2606 | |
06ec9070 | 2607 | vram_lost = amdgpu_device_check_vram_lost(adev); |
5740682e ML |
2608 | if (vram_lost) { |
2609 | DRM_ERROR("VRAM is lost!\n"); | |
2610 | atomic_inc(&adev->vram_lost_counter); | |
2611 | } | |
2612 | ||
c1c7ce8f CK |
2613 | r = amdgpu_gtt_mgr_recover( |
2614 | &adev->mman.bdev.man[TTM_PL_TT]); | |
5740682e ML |
2615 | if (r) |
2616 | goto out; | |
2617 | ||
06ec9070 | 2618 | r = amdgpu_device_ip_resume_phase2(adev); |
5740682e ML |
2619 | if (r) |
2620 | goto out; | |
2621 | ||
2622 | if (vram_lost) | |
06ec9070 | 2623 | amdgpu_device_fill_reset_magic(adev); |
65781c78 | 2624 | } |
5740682e | 2625 | } |
65781c78 | 2626 | |
5740682e ML |
2627 | out: |
2628 | if (!r) { | |
2629 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2630 | r = amdgpu_ib_ring_tests(adev); | |
2631 | if (r) { | |
2632 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
cdd61df6 | 2633 | r = amdgpu_device_ip_suspend(adev); |
5740682e ML |
2634 | need_full_reset = true; |
2635 | goto retry; | |
2636 | } | |
2637 | } | |
65781c78 | 2638 | |
c41d1cf6 ML |
2639 | if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost)) |
2640 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 | 2641 | |
5740682e ML |
2642 | return r; |
2643 | } | |
a90ad3c2 | 2644 | |
5740682e | 2645 | /* |
06ec9070 | 2646 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
2647 | * |
2648 | * @adev: amdgpu device pointer | |
5740682e ML |
2649 | * |
2650 | * do VF FLR and reinitialize Asic | |
2651 | * return 0 means successed otherwise failed | |
2652 | */ | |
c41d1cf6 | 2653 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, bool from_hypervisor) |
5740682e ML |
2654 | { |
2655 | int r; | |
2656 | ||
2657 | if (from_hypervisor) | |
2658 | r = amdgpu_virt_request_full_gpu(adev, true); | |
2659 | else | |
2660 | r = amdgpu_virt_reset_gpu(adev); | |
2661 | if (r) | |
2662 | return r; | |
a90ad3c2 ML |
2663 | |
2664 | /* Resume IP prior to SMC */ | |
06ec9070 | 2665 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
2666 | if (r) |
2667 | goto error; | |
a90ad3c2 ML |
2668 | |
2669 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 2670 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 ML |
2671 | |
2672 | /* now we are okay to resume SMC/CP/SDMA */ | |
06ec9070 | 2673 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
c41d1cf6 | 2674 | amdgpu_virt_release_full_gpu(adev, true); |
5740682e ML |
2675 | if (r) |
2676 | goto error; | |
a90ad3c2 ML |
2677 | |
2678 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 2679 | r = amdgpu_ib_ring_tests(adev); |
a90ad3c2 | 2680 | |
c41d1cf6 ML |
2681 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
2682 | atomic_inc(&adev->vram_lost_counter); | |
2683 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 ML |
2684 | } |
2685 | ||
c41d1cf6 ML |
2686 | error: |
2687 | ||
a90ad3c2 ML |
2688 | return r; |
2689 | } | |
2690 | ||
d38ceaf9 | 2691 | /** |
5f152b5e | 2692 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler |
d38ceaf9 AD |
2693 | * |
2694 | * @adev: amdgpu device pointer | |
5740682e | 2695 | * @job: which job trigger hang |
dcebf026 | 2696 | * @force forces reset regardless of amdgpu_gpu_recovery |
d38ceaf9 | 2697 | * |
5740682e | 2698 | * Attempt to reset the GPU if it has hung (all asics). |
d38ceaf9 AD |
2699 | * Returns 0 for success or an error on failure. |
2700 | */ | |
5f152b5e AD |
2701 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
2702 | struct amdgpu_job *job, bool force) | |
d38ceaf9 | 2703 | { |
4562236b | 2704 | struct drm_atomic_state *state = NULL; |
5740682e | 2705 | int i, r, resched; |
fb140b29 | 2706 | |
54bc1398 | 2707 | if (!force && !amdgpu_device_ip_check_soft_reset(adev)) { |
63fbf42f CZ |
2708 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); |
2709 | return 0; | |
2710 | } | |
d38ceaf9 | 2711 | |
dcebf026 AG |
2712 | if (!force && (amdgpu_gpu_recovery == 0 || |
2713 | (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) { | |
2714 | DRM_INFO("GPU recovery disabled.\n"); | |
2715 | return 0; | |
2716 | } | |
2717 | ||
5740682e ML |
2718 | dev_info(adev->dev, "GPU reset begin!\n"); |
2719 | ||
13a752e3 | 2720 | mutex_lock(&adev->lock_reset); |
d94aed5a | 2721 | atomic_inc(&adev->gpu_reset_counter); |
13a752e3 | 2722 | adev->in_gpu_reset = 1; |
d38ceaf9 | 2723 | |
a3c47d6b CZ |
2724 | /* block TTM */ |
2725 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
71182665 | 2726 | |
4562236b HW |
2727 | /* store modesetting */ |
2728 | if (amdgpu_device_has_dc_support(adev)) | |
2729 | state = drm_atomic_helper_suspend(adev->ddev); | |
a3c47d6b | 2730 | |
71182665 | 2731 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
2732 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2733 | struct amdgpu_ring *ring = adev->rings[i]; | |
2734 | ||
51687759 | 2735 | if (!ring || !ring->sched.thread) |
0875dc9e | 2736 | continue; |
5740682e | 2737 | |
71182665 ML |
2738 | kthread_park(ring->sched.thread); |
2739 | ||
5740682e ML |
2740 | if (job && job->ring->idx != i) |
2741 | continue; | |
2742 | ||
1b1f42d8 | 2743 | drm_sched_hw_job_reset(&ring->sched, &job->base); |
5740682e | 2744 | |
2f9d4084 ML |
2745 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2746 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 2747 | } |
d38ceaf9 | 2748 | |
5740682e | 2749 | if (amdgpu_sriov_vf(adev)) |
c41d1cf6 | 2750 | r = amdgpu_device_reset_sriov(adev, job ? false : true); |
5740682e | 2751 | else |
c41d1cf6 | 2752 | r = amdgpu_device_reset(adev); |
5740682e | 2753 | |
71182665 ML |
2754 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2755 | struct amdgpu_ring *ring = adev->rings[i]; | |
53cdccd5 | 2756 | |
71182665 ML |
2757 | if (!ring || !ring->sched.thread) |
2758 | continue; | |
5740682e | 2759 | |
71182665 ML |
2760 | /* only need recovery sched of the given job's ring |
2761 | * or all rings (in the case @job is NULL) | |
2762 | * after above amdgpu_reset accomplished | |
2763 | */ | |
2764 | if ((!job || job->ring->idx == i) && !r) | |
1b1f42d8 | 2765 | drm_sched_job_recovery(&ring->sched); |
5740682e | 2766 | |
71182665 | 2767 | kthread_unpark(ring->sched.thread); |
d38ceaf9 AD |
2768 | } |
2769 | ||
4562236b | 2770 | if (amdgpu_device_has_dc_support(adev)) { |
5740682e ML |
2771 | if (drm_atomic_helper_resume(adev->ddev, state)) |
2772 | dev_info(adev->dev, "drm resume failed:%d\n", r); | |
5740682e | 2773 | } else { |
4562236b | 2774 | drm_helper_resume_force_mode(adev->ddev); |
5740682e | 2775 | } |
d38ceaf9 AD |
2776 | |
2777 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
5740682e | 2778 | |
89041940 | 2779 | if (r) { |
d38ceaf9 | 2780 | /* bad news, how to tell it to userspace ? */ |
5740682e ML |
2781 | dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); |
2782 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); | |
2783 | } else { | |
2784 | dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter)); | |
89041940 | 2785 | } |
d38ceaf9 | 2786 | |
89041940 | 2787 | amdgpu_vf_error_trans_all(adev); |
13a752e3 ML |
2788 | adev->in_gpu_reset = 0; |
2789 | mutex_unlock(&adev->lock_reset); | |
d38ceaf9 AD |
2790 | return r; |
2791 | } | |
2792 | ||
5494d864 | 2793 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c AD |
2794 | { |
2795 | u32 mask; | |
2796 | int ret; | |
2797 | ||
cd474ba0 AD |
2798 | if (amdgpu_pcie_gen_cap) |
2799 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2800 | |
cd474ba0 AD |
2801 | if (amdgpu_pcie_lane_cap) |
2802 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2803 | |
cd474ba0 AD |
2804 | /* covers APUs as well */ |
2805 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2806 | if (adev->pm.pcie_gen_mask == 0) | |
2807 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2808 | if (adev->pm.pcie_mlw_mask == 0) | |
2809 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2810 | return; |
cd474ba0 | 2811 | } |
d0dd7f0c | 2812 | |
cd474ba0 AD |
2813 | if (adev->pm.pcie_gen_mask == 0) { |
2814 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2815 | if (!ret) { | |
2816 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2817 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2818 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2819 | ||
2820 | if (mask & DRM_PCIE_SPEED_25) | |
2821 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2822 | if (mask & DRM_PCIE_SPEED_50) | |
2823 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2824 | if (mask & DRM_PCIE_SPEED_80) | |
2825 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2826 | } else { | |
2827 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2828 | } | |
2829 | } | |
2830 | if (adev->pm.pcie_mlw_mask == 0) { | |
2831 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2832 | if (!ret) { | |
2833 | switch (mask) { | |
2834 | case 32: | |
2835 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2836 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2837 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2838 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2839 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2840 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2841 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2842 | break; | |
2843 | case 16: | |
2844 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2845 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2846 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2847 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2848 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2849 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2850 | break; | |
2851 | case 12: | |
2852 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2853 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2854 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2855 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2856 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2857 | break; | |
2858 | case 8: | |
2859 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2860 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2861 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2862 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2863 | break; | |
2864 | case 4: | |
2865 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2866 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2867 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2868 | break; | |
2869 | case 2: | |
2870 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2871 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2872 | break; | |
2873 | case 1: | |
2874 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2875 | break; | |
2876 | default: | |
2877 | break; | |
2878 | } | |
2879 | } else { | |
2880 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2881 | } |
2882 | } | |
2883 | } | |
d38ceaf9 | 2884 |