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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
d38ceaf9 | 52 | #include "bif/bif_4_1_d.h" |
9accf2fd | 53 | #include <linux/pci.h> |
bec86378 | 54 | #include <linux/firmware.h> |
d1aff8ec | 55 | #include "amdgpu_pm.h" |
d38ceaf9 AD |
56 | |
57 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
58 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
59 | ||
60 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
61 | "TAHITI", |
62 | "PITCAIRN", | |
63 | "VERDE", | |
64 | "OLAND", | |
65 | "HAINAN", | |
d38ceaf9 AD |
66 | "BONAIRE", |
67 | "KAVERI", | |
68 | "KABINI", | |
69 | "HAWAII", | |
70 | "MULLINS", | |
71 | "TOPAZ", | |
72 | "TONGA", | |
48299f95 | 73 | "FIJI", |
d38ceaf9 | 74 | "CARRIZO", |
139f4917 | 75 | "STONEY", |
2cc0c0b5 FC |
76 | "POLARIS10", |
77 | "POLARIS11", | |
c4642a47 | 78 | "POLARIS12", |
d38ceaf9 AD |
79 | "LAST", |
80 | }; | |
81 | ||
82 | bool amdgpu_device_is_px(struct drm_device *dev) | |
83 | { | |
84 | struct amdgpu_device *adev = dev->dev_private; | |
85 | ||
2f7d10b3 | 86 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
87 | return true; |
88 | return false; | |
89 | } | |
90 | ||
91 | /* | |
92 | * MMIO register access helper functions. | |
93 | */ | |
94 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 95 | uint32_t acc_flags) |
d38ceaf9 | 96 | { |
f4b373f4 TSD |
97 | uint32_t ret; |
98 | ||
15d72fd7 | 99 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
100 | BUG_ON(in_interrupt()); |
101 | return amdgpu_virt_kiq_rreg(adev, reg); | |
102 | } | |
103 | ||
15d72fd7 | 104 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 105 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
106 | else { |
107 | unsigned long flags; | |
d38ceaf9 AD |
108 | |
109 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
110 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
111 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
112 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 113 | } |
f4b373f4 TSD |
114 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
115 | return ret; | |
d38ceaf9 AD |
116 | } |
117 | ||
118 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 119 | uint32_t acc_flags) |
d38ceaf9 | 120 | { |
f4b373f4 | 121 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 122 | |
15d72fd7 | 123 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
124 | BUG_ON(in_interrupt()); |
125 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
126 | } | |
127 | ||
15d72fd7 | 128 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
129 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
130 | else { | |
131 | unsigned long flags; | |
132 | ||
133 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
134 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
135 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
136 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
137 | } | |
138 | } | |
139 | ||
140 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
141 | { | |
142 | if ((reg * 4) < adev->rio_mem_size) | |
143 | return ioread32(adev->rio_mem + (reg * 4)); | |
144 | else { | |
145 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
146 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
147 | } | |
148 | } | |
149 | ||
150 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
151 | { | |
152 | ||
153 | if ((reg * 4) < adev->rio_mem_size) | |
154 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
155 | else { | |
156 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
157 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
158 | } | |
159 | } | |
160 | ||
161 | /** | |
162 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
163 | * | |
164 | * @adev: amdgpu_device pointer | |
165 | * @index: doorbell index | |
166 | * | |
167 | * Returns the value in the doorbell aperture at the | |
168 | * requested doorbell index (CIK). | |
169 | */ | |
170 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
171 | { | |
172 | if (index < adev->doorbell.num_doorbells) { | |
173 | return readl(adev->doorbell.ptr + index); | |
174 | } else { | |
175 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
176 | return 0; | |
177 | } | |
178 | } | |
179 | ||
180 | /** | |
181 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
182 | * | |
183 | * @adev: amdgpu_device pointer | |
184 | * @index: doorbell index | |
185 | * @v: value to write | |
186 | * | |
187 | * Writes @v to the doorbell aperture at the | |
188 | * requested doorbell index (CIK). | |
189 | */ | |
190 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
191 | { | |
192 | if (index < adev->doorbell.num_doorbells) { | |
193 | writel(v, adev->doorbell.ptr + index); | |
194 | } else { | |
195 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
196 | } | |
197 | } | |
198 | ||
832be404 KW |
199 | /** |
200 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
201 | * | |
202 | * @adev: amdgpu_device pointer | |
203 | * @index: doorbell index | |
204 | * | |
205 | * Returns the value in the doorbell aperture at the | |
206 | * requested doorbell index (VEGA10+). | |
207 | */ | |
208 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
209 | { | |
210 | if (index < adev->doorbell.num_doorbells) { | |
211 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
212 | } else { | |
213 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
214 | return 0; | |
215 | } | |
216 | } | |
217 | ||
218 | /** | |
219 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
220 | * | |
221 | * @adev: amdgpu_device pointer | |
222 | * @index: doorbell index | |
223 | * @v: value to write | |
224 | * | |
225 | * Writes @v to the doorbell aperture at the | |
226 | * requested doorbell index (VEGA10+). | |
227 | */ | |
228 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
229 | { | |
230 | if (index < adev->doorbell.num_doorbells) { | |
231 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
232 | } else { | |
233 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
234 | } | |
235 | } | |
236 | ||
d38ceaf9 AD |
237 | /** |
238 | * amdgpu_invalid_rreg - dummy reg read function | |
239 | * | |
240 | * @adev: amdgpu device pointer | |
241 | * @reg: offset of register | |
242 | * | |
243 | * Dummy register read function. Used for register blocks | |
244 | * that certain asics don't have (all asics). | |
245 | * Returns the value in the register. | |
246 | */ | |
247 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
248 | { | |
249 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
250 | BUG(); | |
251 | return 0; | |
252 | } | |
253 | ||
254 | /** | |
255 | * amdgpu_invalid_wreg - dummy reg write function | |
256 | * | |
257 | * @adev: amdgpu device pointer | |
258 | * @reg: offset of register | |
259 | * @v: value to write to the register | |
260 | * | |
261 | * Dummy register read function. Used for register blocks | |
262 | * that certain asics don't have (all asics). | |
263 | */ | |
264 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
265 | { | |
266 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
267 | reg, v); | |
268 | BUG(); | |
269 | } | |
270 | ||
271 | /** | |
272 | * amdgpu_block_invalid_rreg - dummy reg read function | |
273 | * | |
274 | * @adev: amdgpu device pointer | |
275 | * @block: offset of instance | |
276 | * @reg: offset of register | |
277 | * | |
278 | * Dummy register read function. Used for register blocks | |
279 | * that certain asics don't have (all asics). | |
280 | * Returns the value in the register. | |
281 | */ | |
282 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
283 | uint32_t block, uint32_t reg) | |
284 | { | |
285 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
286 | reg, block); | |
287 | BUG(); | |
288 | return 0; | |
289 | } | |
290 | ||
291 | /** | |
292 | * amdgpu_block_invalid_wreg - dummy reg write function | |
293 | * | |
294 | * @adev: amdgpu device pointer | |
295 | * @block: offset of instance | |
296 | * @reg: offset of register | |
297 | * @v: value to write to the register | |
298 | * | |
299 | * Dummy register read function. Used for register blocks | |
300 | * that certain asics don't have (all asics). | |
301 | */ | |
302 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
303 | uint32_t block, | |
304 | uint32_t reg, uint32_t v) | |
305 | { | |
306 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
307 | reg, block, v); | |
308 | BUG(); | |
309 | } | |
310 | ||
311 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
312 | { | |
313 | int r; | |
314 | ||
315 | if (adev->vram_scratch.robj == NULL) { | |
316 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 317 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
318 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
319 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 320 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
321 | if (r) { |
322 | return r; | |
323 | } | |
324 | } | |
325 | ||
326 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
327 | if (unlikely(r != 0)) | |
328 | return r; | |
329 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
330 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
331 | if (r) { | |
332 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
333 | return r; | |
334 | } | |
335 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
336 | (void **)&adev->vram_scratch.ptr); | |
337 | if (r) | |
338 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
339 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
340 | ||
341 | return r; | |
342 | } | |
343 | ||
344 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
345 | { | |
346 | int r; | |
347 | ||
348 | if (adev->vram_scratch.robj == NULL) { | |
349 | return; | |
350 | } | |
351 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
352 | if (likely(r == 0)) { | |
353 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
354 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
355 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
356 | } | |
357 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
358 | } | |
359 | ||
360 | /** | |
361 | * amdgpu_program_register_sequence - program an array of registers. | |
362 | * | |
363 | * @adev: amdgpu_device pointer | |
364 | * @registers: pointer to the register array | |
365 | * @array_size: size of the register array | |
366 | * | |
367 | * Programs an array or registers with and and or masks. | |
368 | * This is a helper for setting golden registers. | |
369 | */ | |
370 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
371 | const u32 *registers, | |
372 | const u32 array_size) | |
373 | { | |
374 | u32 tmp, reg, and_mask, or_mask; | |
375 | int i; | |
376 | ||
377 | if (array_size % 3) | |
378 | return; | |
379 | ||
380 | for (i = 0; i < array_size; i +=3) { | |
381 | reg = registers[i + 0]; | |
382 | and_mask = registers[i + 1]; | |
383 | or_mask = registers[i + 2]; | |
384 | ||
385 | if (and_mask == 0xffffffff) { | |
386 | tmp = or_mask; | |
387 | } else { | |
388 | tmp = RREG32(reg); | |
389 | tmp &= ~and_mask; | |
390 | tmp |= or_mask; | |
391 | } | |
392 | WREG32(reg, tmp); | |
393 | } | |
394 | } | |
395 | ||
396 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
397 | { | |
398 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
399 | } | |
400 | ||
401 | /* | |
402 | * GPU doorbell aperture helpers function. | |
403 | */ | |
404 | /** | |
405 | * amdgpu_doorbell_init - Init doorbell driver information. | |
406 | * | |
407 | * @adev: amdgpu_device pointer | |
408 | * | |
409 | * Init doorbell driver information (CIK) | |
410 | * Returns 0 on success, error on failure. | |
411 | */ | |
412 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
413 | { | |
414 | /* doorbell bar mapping */ | |
415 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
416 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
417 | ||
edf600da | 418 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
419 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
420 | if (adev->doorbell.num_doorbells == 0) | |
421 | return -EINVAL; | |
422 | ||
423 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
424 | if (adev->doorbell.ptr == NULL) { | |
425 | return -ENOMEM; | |
426 | } | |
427 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
428 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | /** | |
434 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
435 | * | |
436 | * @adev: amdgpu_device pointer | |
437 | * | |
438 | * Tear down doorbell driver information (CIK) | |
439 | */ | |
440 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
441 | { | |
442 | iounmap(adev->doorbell.ptr); | |
443 | adev->doorbell.ptr = NULL; | |
444 | } | |
445 | ||
446 | /** | |
447 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
448 | * setup amdkfd | |
449 | * | |
450 | * @adev: amdgpu_device pointer | |
451 | * @aperture_base: output returning doorbell aperture base physical address | |
452 | * @aperture_size: output returning doorbell aperture size in bytes | |
453 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
454 | * | |
455 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
456 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
457 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
458 | */ | |
459 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
460 | phys_addr_t *aperture_base, | |
461 | size_t *aperture_size, | |
462 | size_t *start_offset) | |
463 | { | |
464 | /* | |
465 | * The first num_doorbells are used by amdgpu. | |
466 | * amdkfd takes whatever's left in the aperture. | |
467 | */ | |
468 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
469 | *aperture_base = adev->doorbell.base; | |
470 | *aperture_size = adev->doorbell.size; | |
471 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
472 | } else { | |
473 | *aperture_base = 0; | |
474 | *aperture_size = 0; | |
475 | *start_offset = 0; | |
476 | } | |
477 | } | |
478 | ||
479 | /* | |
480 | * amdgpu_wb_*() | |
481 | * Writeback is the the method by which the the GPU updates special pages | |
482 | * in memory with the status of certain GPU events (fences, ring pointers, | |
483 | * etc.). | |
484 | */ | |
485 | ||
486 | /** | |
487 | * amdgpu_wb_fini - Disable Writeback and free memory | |
488 | * | |
489 | * @adev: amdgpu_device pointer | |
490 | * | |
491 | * Disables Writeback and frees the Writeback memory (all asics). | |
492 | * Used at driver shutdown. | |
493 | */ | |
494 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
495 | { | |
496 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
497 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
498 | &adev->wb.gpu_addr, | |
499 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
500 | adev->wb.wb_obj = NULL; |
501 | } | |
502 | } | |
503 | ||
504 | /** | |
505 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
506 | * | |
507 | * @adev: amdgpu_device pointer | |
508 | * | |
509 | * Disables Writeback and frees the Writeback memory (all asics). | |
510 | * Used at driver startup. | |
511 | * Returns 0 on success or an -error on failure. | |
512 | */ | |
513 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
514 | { | |
515 | int r; | |
516 | ||
517 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 518 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
519 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
520 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
521 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
522 | if (r) { |
523 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
524 | return r; | |
525 | } | |
d38ceaf9 AD |
526 | |
527 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
528 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
529 | ||
530 | /* clear wb memory */ | |
60a970a6 | 531 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
532 | } |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | /** | |
538 | * amdgpu_wb_get - Allocate a wb entry | |
539 | * | |
540 | * @adev: amdgpu_device pointer | |
541 | * @wb: wb index | |
542 | * | |
543 | * Allocate a wb slot for use by the driver (all asics). | |
544 | * Returns 0 on success or -EINVAL on failure. | |
545 | */ | |
546 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
547 | { | |
548 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
549 | if (offset < adev->wb.num_wb) { | |
550 | __set_bit(offset, adev->wb.used); | |
551 | *wb = offset; | |
552 | return 0; | |
553 | } else { | |
554 | return -EINVAL; | |
555 | } | |
556 | } | |
557 | ||
7014285a KW |
558 | /** |
559 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
560 | * | |
561 | * @adev: amdgpu_device pointer | |
562 | * @wb: wb index | |
563 | * | |
564 | * Allocate a wb slot for use by the driver (all asics). | |
565 | * Returns 0 on success or -EINVAL on failure. | |
566 | */ | |
567 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
568 | { | |
569 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
570 | adev->wb.num_wb, 0, 2, 7, 0); | |
571 | if ((offset + 1) < adev->wb.num_wb) { | |
572 | __set_bit(offset, adev->wb.used); | |
573 | __set_bit(offset + 1, adev->wb.used); | |
574 | *wb = offset; | |
575 | return 0; | |
576 | } else { | |
577 | return -EINVAL; | |
578 | } | |
579 | } | |
580 | ||
d38ceaf9 AD |
581 | /** |
582 | * amdgpu_wb_free - Free a wb entry | |
583 | * | |
584 | * @adev: amdgpu_device pointer | |
585 | * @wb: wb index | |
586 | * | |
587 | * Free a wb slot allocated for use by the driver (all asics) | |
588 | */ | |
589 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
590 | { | |
591 | if (wb < adev->wb.num_wb) | |
592 | __clear_bit(wb, adev->wb.used); | |
593 | } | |
594 | ||
7014285a KW |
595 | /** |
596 | * amdgpu_wb_free_64bit - Free a wb entry | |
597 | * | |
598 | * @adev: amdgpu_device pointer | |
599 | * @wb: wb index | |
600 | * | |
601 | * Free a wb slot allocated for use by the driver (all asics) | |
602 | */ | |
603 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
604 | { | |
605 | if ((wb + 1) < adev->wb.num_wb) { | |
606 | __clear_bit(wb, adev->wb.used); | |
607 | __clear_bit(wb + 1, adev->wb.used); | |
608 | } | |
609 | } | |
610 | ||
d38ceaf9 AD |
611 | /** |
612 | * amdgpu_vram_location - try to find VRAM location | |
613 | * @adev: amdgpu device structure holding all necessary informations | |
614 | * @mc: memory controller structure holding memory informations | |
615 | * @base: base address at which to put VRAM | |
616 | * | |
617 | * Function will place try to place VRAM at base address provided | |
618 | * as parameter (which is so far either PCI aperture address or | |
619 | * for IGP TOM base address). | |
620 | * | |
621 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
622 | * address space then we limit the VRAM size to the aperture. | |
623 | * | |
624 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
625 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
626 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
627 | * not IGP. | |
628 | * | |
629 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
630 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
631 | * Novell bug 204882 + along with lots of ubuntu ones | |
632 | * | |
633 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
634 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
635 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
636 | * ones) | |
637 | * | |
638 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
639 | * explicitly check for that thought. | |
640 | * | |
641 | * FIXME: when reducing VRAM size align new size on power of 2. | |
642 | */ | |
643 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
644 | { | |
645 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
646 | ||
647 | mc->vram_start = base; | |
648 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
649 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
650 | mc->real_vram_size = mc->aper_size; | |
651 | mc->mc_vram_size = mc->aper_size; | |
652 | } | |
653 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
654 | if (limit && limit < mc->real_vram_size) | |
655 | mc->real_vram_size = limit; | |
656 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
657 | mc->mc_vram_size >> 20, mc->vram_start, | |
658 | mc->vram_end, mc->real_vram_size >> 20); | |
659 | } | |
660 | ||
661 | /** | |
662 | * amdgpu_gtt_location - try to find GTT location | |
663 | * @adev: amdgpu device structure holding all necessary informations | |
664 | * @mc: memory controller structure holding memory informations | |
665 | * | |
666 | * Function will place try to place GTT before or after VRAM. | |
667 | * | |
668 | * If GTT size is bigger than space left then we ajust GTT size. | |
669 | * Thus function will never fails. | |
670 | * | |
671 | * FIXME: when reducing GTT size align new size on power of 2. | |
672 | */ | |
673 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
674 | { | |
675 | u64 size_af, size_bf; | |
676 | ||
677 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
678 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
679 | if (size_bf > size_af) { | |
680 | if (mc->gtt_size > size_bf) { | |
681 | dev_warn(adev->dev, "limiting GTT\n"); | |
682 | mc->gtt_size = size_bf; | |
683 | } | |
9dc5a91e | 684 | mc->gtt_start = 0; |
d38ceaf9 AD |
685 | } else { |
686 | if (mc->gtt_size > size_af) { | |
687 | dev_warn(adev->dev, "limiting GTT\n"); | |
688 | mc->gtt_size = size_af; | |
689 | } | |
690 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
691 | } | |
692 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
693 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
694 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
695 | } | |
696 | ||
697 | /* | |
698 | * GPU helpers function. | |
699 | */ | |
700 | /** | |
c836fec5 | 701 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
702 | * |
703 | * @adev: amdgpu_device pointer | |
704 | * | |
c836fec5 JQ |
705 | * Check if the asic has been initialized (all asics) at driver startup |
706 | * or post is needed if hw reset is performed. | |
707 | * Returns true if need or false if not. | |
d38ceaf9 | 708 | */ |
c836fec5 | 709 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
710 | { |
711 | uint32_t reg; | |
712 | ||
c836fec5 JQ |
713 | if (adev->has_hw_reset) { |
714 | adev->has_hw_reset = false; | |
715 | return true; | |
716 | } | |
d38ceaf9 | 717 | /* then check MEM_SIZE, in case the crtcs are off */ |
bbf282d8 | 718 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 AD |
719 | |
720 | if (reg) | |
c836fec5 | 721 | return false; |
d38ceaf9 | 722 | |
c836fec5 | 723 | return true; |
d38ceaf9 AD |
724 | |
725 | } | |
726 | ||
bec86378 ML |
727 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
728 | { | |
729 | if (amdgpu_sriov_vf(adev)) | |
730 | return false; | |
731 | ||
732 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
733 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
734 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
735 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
736 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
737 | */ |
738 | if (adev->asic_type == CHIP_FIJI) { | |
739 | int err; | |
740 | uint32_t fw_ver; | |
741 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
742 | /* force vPost if error occured */ | |
743 | if (err) | |
744 | return true; | |
745 | ||
746 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
747 | if (fw_ver < 0x00160e00) |
748 | return true; | |
bec86378 | 749 | } |
bec86378 | 750 | } |
c836fec5 | 751 | return amdgpu_need_post(adev); |
bec86378 ML |
752 | } |
753 | ||
d38ceaf9 AD |
754 | /** |
755 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
756 | * | |
757 | * @adev: amdgpu_device pointer | |
758 | * | |
759 | * Allocate the dummy page used by the driver (all asics). | |
760 | * This dummy page is used by the driver as a filler for gart entries | |
761 | * when pages are taken out of the GART | |
762 | * Returns 0 on sucess, -ENOMEM on failure. | |
763 | */ | |
764 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
765 | { | |
766 | if (adev->dummy_page.page) | |
767 | return 0; | |
768 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
769 | if (adev->dummy_page.page == NULL) | |
770 | return -ENOMEM; | |
771 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
772 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
773 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
774 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
775 | __free_page(adev->dummy_page.page); | |
776 | adev->dummy_page.page = NULL; | |
777 | return -ENOMEM; | |
778 | } | |
779 | return 0; | |
780 | } | |
781 | ||
782 | /** | |
783 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
784 | * | |
785 | * @adev: amdgpu_device pointer | |
786 | * | |
787 | * Frees the dummy page used by the driver (all asics). | |
788 | */ | |
789 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
790 | { | |
791 | if (adev->dummy_page.page == NULL) | |
792 | return; | |
793 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
794 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
795 | __free_page(adev->dummy_page.page); | |
796 | adev->dummy_page.page = NULL; | |
797 | } | |
798 | ||
799 | ||
800 | /* ATOM accessor methods */ | |
801 | /* | |
802 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
803 | * driver registers callbacks to access registers and the interpreter | |
804 | * in the driver parses the tables and executes then to program specific | |
805 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
806 | * atombios.h, and atom.c | |
807 | */ | |
808 | ||
809 | /** | |
810 | * cail_pll_read - read PLL register | |
811 | * | |
812 | * @info: atom card_info pointer | |
813 | * @reg: PLL register offset | |
814 | * | |
815 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
816 | * Returns the value of the PLL register. | |
817 | */ | |
818 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
819 | { | |
820 | return 0; | |
821 | } | |
822 | ||
823 | /** | |
824 | * cail_pll_write - write PLL register | |
825 | * | |
826 | * @info: atom card_info pointer | |
827 | * @reg: PLL register offset | |
828 | * @val: value to write to the pll register | |
829 | * | |
830 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
831 | */ | |
832 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
833 | { | |
834 | ||
835 | } | |
836 | ||
837 | /** | |
838 | * cail_mc_read - read MC (Memory Controller) register | |
839 | * | |
840 | * @info: atom card_info pointer | |
841 | * @reg: MC register offset | |
842 | * | |
843 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
844 | * Returns the value of the MC register. | |
845 | */ | |
846 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
847 | { | |
848 | return 0; | |
849 | } | |
850 | ||
851 | /** | |
852 | * cail_mc_write - write MC (Memory Controller) register | |
853 | * | |
854 | * @info: atom card_info pointer | |
855 | * @reg: MC register offset | |
856 | * @val: value to write to the pll register | |
857 | * | |
858 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
859 | */ | |
860 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
861 | { | |
862 | ||
863 | } | |
864 | ||
865 | /** | |
866 | * cail_reg_write - write MMIO register | |
867 | * | |
868 | * @info: atom card_info pointer | |
869 | * @reg: MMIO register offset | |
870 | * @val: value to write to the pll register | |
871 | * | |
872 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
873 | */ | |
874 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
875 | { | |
876 | struct amdgpu_device *adev = info->dev->dev_private; | |
877 | ||
878 | WREG32(reg, val); | |
879 | } | |
880 | ||
881 | /** | |
882 | * cail_reg_read - read MMIO register | |
883 | * | |
884 | * @info: atom card_info pointer | |
885 | * @reg: MMIO register offset | |
886 | * | |
887 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
888 | * Returns the value of the MMIO register. | |
889 | */ | |
890 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
891 | { | |
892 | struct amdgpu_device *adev = info->dev->dev_private; | |
893 | uint32_t r; | |
894 | ||
895 | r = RREG32(reg); | |
896 | return r; | |
897 | } | |
898 | ||
899 | /** | |
900 | * cail_ioreg_write - write IO register | |
901 | * | |
902 | * @info: atom card_info pointer | |
903 | * @reg: IO register offset | |
904 | * @val: value to write to the pll register | |
905 | * | |
906 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
907 | */ | |
908 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
909 | { | |
910 | struct amdgpu_device *adev = info->dev->dev_private; | |
911 | ||
912 | WREG32_IO(reg, val); | |
913 | } | |
914 | ||
915 | /** | |
916 | * cail_ioreg_read - read IO register | |
917 | * | |
918 | * @info: atom card_info pointer | |
919 | * @reg: IO register offset | |
920 | * | |
921 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
922 | * Returns the value of the IO register. | |
923 | */ | |
924 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
925 | { | |
926 | struct amdgpu_device *adev = info->dev->dev_private; | |
927 | uint32_t r; | |
928 | ||
929 | r = RREG32_IO(reg); | |
930 | return r; | |
931 | } | |
932 | ||
933 | /** | |
934 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
935 | * | |
936 | * @adev: amdgpu_device pointer | |
937 | * | |
938 | * Frees the driver info and register access callbacks for the ATOM | |
939 | * interpreter (r4xx+). | |
940 | * Called at driver shutdown. | |
941 | */ | |
942 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
943 | { | |
89e0ec9f | 944 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 945 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
946 | kfree(adev->mode_info.atom_context->iio); |
947 | } | |
d38ceaf9 AD |
948 | kfree(adev->mode_info.atom_context); |
949 | adev->mode_info.atom_context = NULL; | |
950 | kfree(adev->mode_info.atom_card_info); | |
951 | adev->mode_info.atom_card_info = NULL; | |
952 | } | |
953 | ||
954 | /** | |
955 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
956 | * | |
957 | * @adev: amdgpu_device pointer | |
958 | * | |
959 | * Initializes the driver info and register access callbacks for the | |
960 | * ATOM interpreter (r4xx+). | |
961 | * Returns 0 on sucess, -ENOMEM on failure. | |
962 | * Called at driver startup. | |
963 | */ | |
964 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
965 | { | |
966 | struct card_info *atom_card_info = | |
967 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
968 | ||
969 | if (!atom_card_info) | |
970 | return -ENOMEM; | |
971 | ||
972 | adev->mode_info.atom_card_info = atom_card_info; | |
973 | atom_card_info->dev = adev->ddev; | |
974 | atom_card_info->reg_read = cail_reg_read; | |
975 | atom_card_info->reg_write = cail_reg_write; | |
976 | /* needed for iio ops */ | |
977 | if (adev->rio_mem) { | |
978 | atom_card_info->ioreg_read = cail_ioreg_read; | |
979 | atom_card_info->ioreg_write = cail_ioreg_write; | |
980 | } else { | |
b64a18c5 | 981 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
982 | atom_card_info->ioreg_read = cail_reg_read; |
983 | atom_card_info->ioreg_write = cail_reg_write; | |
984 | } | |
985 | atom_card_info->mc_read = cail_mc_read; | |
986 | atom_card_info->mc_write = cail_mc_write; | |
987 | atom_card_info->pll_read = cail_pll_read; | |
988 | atom_card_info->pll_write = cail_pll_write; | |
989 | ||
990 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
991 | if (!adev->mode_info.atom_context) { | |
992 | amdgpu_atombios_fini(adev); | |
993 | return -ENOMEM; | |
994 | } | |
995 | ||
996 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
997 | if (adev->is_atom_fw) { |
998 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
999 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1000 | } else { | |
1001 | amdgpu_atombios_scratch_regs_init(adev); | |
1002 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1003 | } | |
d38ceaf9 AD |
1004 | return 0; |
1005 | } | |
1006 | ||
1007 | /* if we get transitioned to only one device, take VGA back */ | |
1008 | /** | |
1009 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1010 | * | |
1011 | * @cookie: amdgpu_device pointer | |
1012 | * @state: enable/disable vga decode | |
1013 | * | |
1014 | * Enable/disable vga decode (all asics). | |
1015 | * Returns VGA resource flags. | |
1016 | */ | |
1017 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1018 | { | |
1019 | struct amdgpu_device *adev = cookie; | |
1020 | amdgpu_asic_set_vga_state(adev, state); | |
1021 | if (state) | |
1022 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1023 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1024 | else | |
1025 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1026 | } | |
1027 | ||
1028 | /** | |
1029 | * amdgpu_check_pot_argument - check that argument is a power of two | |
1030 | * | |
1031 | * @arg: value to check | |
1032 | * | |
1033 | * Validates that a certain argument is a power of two (all asics). | |
1034 | * Returns true if argument is valid. | |
1035 | */ | |
1036 | static bool amdgpu_check_pot_argument(int arg) | |
1037 | { | |
1038 | return (arg & (arg - 1)) == 0; | |
1039 | } | |
1040 | ||
1041 | /** | |
1042 | * amdgpu_check_arguments - validate module params | |
1043 | * | |
1044 | * @adev: amdgpu_device pointer | |
1045 | * | |
1046 | * Validates certain module parameters and updates | |
1047 | * the associated values used by the driver (all asics). | |
1048 | */ | |
1049 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1050 | { | |
5b011235 CZ |
1051 | if (amdgpu_sched_jobs < 4) { |
1052 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1053 | amdgpu_sched_jobs); | |
1054 | amdgpu_sched_jobs = 4; | |
1055 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
1056 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
1057 | amdgpu_sched_jobs); | |
1058 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1059 | } | |
d38ceaf9 AD |
1060 | |
1061 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 1062 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
1063 | if (amdgpu_gart_size < 32) { |
1064 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1065 | amdgpu_gart_size); | |
1066 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
1067 | } |
1068 | } | |
1069 | ||
1070 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
1071 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
1072 | amdgpu_vm_size); | |
8dacc127 | 1073 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1074 | } |
1075 | ||
1076 | if (amdgpu_vm_size < 1) { | |
1077 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1078 | amdgpu_vm_size); | |
8dacc127 | 1079 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1080 | } |
1081 | ||
1082 | /* | |
1083 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
1084 | */ | |
1085 | if (amdgpu_vm_size > 1024) { | |
1086 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1087 | amdgpu_vm_size); | |
8dacc127 | 1088 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1089 | } |
1090 | ||
1091 | /* defines number of bits in page table versus page directory, | |
1092 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1093 | * page table and the remaining bits are in the page directory */ | |
1094 | if (amdgpu_vm_block_size == -1) { | |
1095 | ||
1096 | /* Total bits covered by PD + PTs */ | |
1097 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
1098 | ||
1099 | /* Make sure the PD is 4K in size up to 8GB address space. | |
1100 | Above that split equal between PD and PTs */ | |
1101 | if (amdgpu_vm_size <= 8) | |
1102 | amdgpu_vm_block_size = bits - 9; | |
1103 | else | |
1104 | amdgpu_vm_block_size = (bits + 3) / 2; | |
1105 | ||
1106 | } else if (amdgpu_vm_block_size < 9) { | |
1107 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
1108 | amdgpu_vm_block_size); | |
1109 | amdgpu_vm_block_size = 9; | |
1110 | } | |
1111 | ||
1112 | if (amdgpu_vm_block_size > 24 || | |
1113 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1114 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1115 | amdgpu_vm_block_size); | |
1116 | amdgpu_vm_block_size = 9; | |
1117 | } | |
6a7f76e7 | 1118 | |
526bae37 | 1119 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
1120 | !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { | |
6a7f76e7 CK |
1121 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1122 | amdgpu_vram_page_split); | |
1123 | amdgpu_vram_page_split = 1024; | |
1124 | } | |
d38ceaf9 AD |
1125 | } |
1126 | ||
1127 | /** | |
1128 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1129 | * | |
1130 | * @pdev: pci dev pointer | |
1694467b | 1131 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1132 | * |
1133 | * Callback for the switcheroo driver. Suspends or resumes the | |
1134 | * the asics before or after it is powered up using ACPI methods. | |
1135 | */ | |
1136 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1137 | { | |
1138 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1139 | ||
1140 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1141 | return; | |
1142 | ||
1143 | if (state == VGA_SWITCHEROO_ON) { | |
1144 | unsigned d3_delay = dev->pdev->d3_delay; | |
1145 | ||
7ca85295 | 1146 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1147 | /* don't suspend or resume card normally */ |
1148 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1149 | ||
810ddc3a | 1150 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1151 | |
1152 | dev->pdev->d3_delay = d3_delay; | |
1153 | ||
1154 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1155 | drm_kms_helper_poll_enable(dev); | |
1156 | } else { | |
7ca85295 | 1157 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1158 | drm_kms_helper_poll_disable(dev); |
1159 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1160 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1161 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1162 | } | |
1163 | } | |
1164 | ||
1165 | /** | |
1166 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1167 | * | |
1168 | * @pdev: pci dev pointer | |
1169 | * | |
1170 | * Callback for the switcheroo driver. Check of the switcheroo | |
1171 | * state can be changed. | |
1172 | * Returns true if the state can be changed, false if not. | |
1173 | */ | |
1174 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1175 | { | |
1176 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1177 | ||
1178 | /* | |
1179 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1180 | * locking inversion with the driver load path. And the access here is | |
1181 | * completely racy anyway. So don't bother with locking for now. | |
1182 | */ | |
1183 | return dev->open_count == 0; | |
1184 | } | |
1185 | ||
1186 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1187 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1188 | .reprobe = NULL, | |
1189 | .can_switch = amdgpu_switcheroo_can_switch, | |
1190 | }; | |
1191 | ||
1192 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1193 | enum amd_ip_block_type block_type, |
1194 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1195 | { |
1196 | int i, r = 0; | |
1197 | ||
1198 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1199 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1200 | continue; |
c722865a RZ |
1201 | if (adev->ip_blocks[i].version->type != block_type) |
1202 | continue; | |
1203 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1204 | continue; | |
1205 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1206 | (void *)adev, state); | |
1207 | if (r) | |
1208 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1209 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1210 | } |
1211 | return r; | |
1212 | } | |
1213 | ||
1214 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1215 | enum amd_ip_block_type block_type, |
1216 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1217 | { |
1218 | int i, r = 0; | |
1219 | ||
1220 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1221 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1222 | continue; |
c722865a RZ |
1223 | if (adev->ip_blocks[i].version->type != block_type) |
1224 | continue; | |
1225 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1226 | continue; | |
1227 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1228 | (void *)adev, state); | |
1229 | if (r) | |
1230 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1231 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1232 | } |
1233 | return r; | |
1234 | } | |
1235 | ||
6cb2d4e4 HR |
1236 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1237 | { | |
1238 | int i; | |
1239 | ||
1240 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1241 | if (!adev->ip_blocks[i].status.valid) | |
1242 | continue; | |
1243 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1244 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1245 | } | |
1246 | } | |
1247 | ||
5dbbb60b AD |
1248 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1249 | enum amd_ip_block_type block_type) | |
1250 | { | |
1251 | int i, r; | |
1252 | ||
1253 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1254 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1255 | continue; |
a1255107 AD |
1256 | if (adev->ip_blocks[i].version->type == block_type) { |
1257 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1258 | if (r) |
1259 | return r; | |
1260 | break; | |
1261 | } | |
1262 | } | |
1263 | return 0; | |
1264 | ||
1265 | } | |
1266 | ||
1267 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1268 | enum amd_ip_block_type block_type) | |
1269 | { | |
1270 | int i; | |
1271 | ||
1272 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1273 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1274 | continue; |
a1255107 AD |
1275 | if (adev->ip_blocks[i].version->type == block_type) |
1276 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1277 | } |
1278 | return true; | |
1279 | ||
1280 | } | |
1281 | ||
a1255107 AD |
1282 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1283 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1284 | { |
1285 | int i; | |
1286 | ||
1287 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1288 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1289 | return &adev->ip_blocks[i]; |
1290 | ||
1291 | return NULL; | |
1292 | } | |
1293 | ||
1294 | /** | |
1295 | * amdgpu_ip_block_version_cmp | |
1296 | * | |
1297 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1298 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1299 | * @major: major version |
1300 | * @minor: minor version | |
1301 | * | |
1302 | * return 0 if equal or greater | |
1303 | * return 1 if smaller or the ip_block doesn't exist | |
1304 | */ | |
1305 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1306 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1307 | u32 major, u32 minor) |
1308 | { | |
a1255107 | 1309 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1310 | |
a1255107 AD |
1311 | if (ip_block && ((ip_block->version->major > major) || |
1312 | ((ip_block->version->major == major) && | |
1313 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1314 | return 0; |
1315 | ||
1316 | return 1; | |
1317 | } | |
1318 | ||
a1255107 AD |
1319 | /** |
1320 | * amdgpu_ip_block_add | |
1321 | * | |
1322 | * @adev: amdgpu_device pointer | |
1323 | * @ip_block_version: pointer to the IP to add | |
1324 | * | |
1325 | * Adds the IP block driver information to the collection of IPs | |
1326 | * on the asic. | |
1327 | */ | |
1328 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1329 | const struct amdgpu_ip_block_version *ip_block_version) | |
1330 | { | |
1331 | if (!ip_block_version) | |
1332 | return -EINVAL; | |
1333 | ||
1334 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; | |
1335 | ||
1336 | return 0; | |
1337 | } | |
1338 | ||
483ef985 | 1339 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1340 | { |
1341 | adev->enable_virtual_display = false; | |
1342 | ||
1343 | if (amdgpu_virtual_display) { | |
1344 | struct drm_device *ddev = adev->ddev; | |
1345 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1346 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1347 | |
1348 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1349 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1350 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1351 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1352 | if (!strcmp("all", pciaddname) |
1353 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1354 | long num_crtc; |
1355 | int res = -1; | |
1356 | ||
9accf2fd | 1357 | adev->enable_virtual_display = true; |
0f66356d ED |
1358 | |
1359 | if (pciaddname_tmp) | |
1360 | res = kstrtol(pciaddname_tmp, 10, | |
1361 | &num_crtc); | |
1362 | ||
1363 | if (!res) { | |
1364 | if (num_crtc < 1) | |
1365 | num_crtc = 1; | |
1366 | if (num_crtc > 6) | |
1367 | num_crtc = 6; | |
1368 | adev->mode_info.num_crtc = num_crtc; | |
1369 | } else { | |
1370 | adev->mode_info.num_crtc = 1; | |
1371 | } | |
9accf2fd ED |
1372 | break; |
1373 | } | |
1374 | } | |
1375 | ||
0f66356d ED |
1376 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1377 | amdgpu_virtual_display, pci_address_name, | |
1378 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1379 | |
1380 | kfree(pciaddstr); | |
1381 | } | |
1382 | } | |
1383 | ||
d38ceaf9 AD |
1384 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1385 | { | |
aaa36a97 | 1386 | int i, r; |
d38ceaf9 | 1387 | |
483ef985 | 1388 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1389 | |
d38ceaf9 | 1390 | switch (adev->asic_type) { |
aaa36a97 AD |
1391 | case CHIP_TOPAZ: |
1392 | case CHIP_TONGA: | |
48299f95 | 1393 | case CHIP_FIJI: |
2cc0c0b5 FC |
1394 | case CHIP_POLARIS11: |
1395 | case CHIP_POLARIS10: | |
c4642a47 | 1396 | case CHIP_POLARIS12: |
aaa36a97 | 1397 | case CHIP_CARRIZO: |
39bb0c92 SL |
1398 | case CHIP_STONEY: |
1399 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1400 | adev->family = AMDGPU_FAMILY_CZ; |
1401 | else | |
1402 | adev->family = AMDGPU_FAMILY_VI; | |
1403 | ||
1404 | r = vi_set_ip_blocks(adev); | |
1405 | if (r) | |
1406 | return r; | |
1407 | break; | |
33f34802 KW |
1408 | #ifdef CONFIG_DRM_AMDGPU_SI |
1409 | case CHIP_VERDE: | |
1410 | case CHIP_TAHITI: | |
1411 | case CHIP_PITCAIRN: | |
1412 | case CHIP_OLAND: | |
1413 | case CHIP_HAINAN: | |
295d0daf | 1414 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1415 | r = si_set_ip_blocks(adev); |
1416 | if (r) | |
1417 | return r; | |
1418 | break; | |
1419 | #endif | |
a2e73f56 AD |
1420 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1421 | case CHIP_BONAIRE: | |
1422 | case CHIP_HAWAII: | |
1423 | case CHIP_KAVERI: | |
1424 | case CHIP_KABINI: | |
1425 | case CHIP_MULLINS: | |
1426 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1427 | adev->family = AMDGPU_FAMILY_CI; | |
1428 | else | |
1429 | adev->family = AMDGPU_FAMILY_KV; | |
1430 | ||
1431 | r = cik_set_ip_blocks(adev); | |
1432 | if (r) | |
1433 | return r; | |
1434 | break; | |
1435 | #endif | |
d38ceaf9 AD |
1436 | default: |
1437 | /* FIXME: not supported yet */ | |
1438 | return -EINVAL; | |
1439 | } | |
1440 | ||
3149d9da XY |
1441 | if (amdgpu_sriov_vf(adev)) { |
1442 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1443 | if (r) | |
1444 | return r; | |
1445 | } | |
1446 | ||
d38ceaf9 AD |
1447 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1448 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1449 | DRM_ERROR("disabled ip block: %d\n", i); | |
a1255107 | 1450 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1451 | } else { |
a1255107 AD |
1452 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1453 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1454 | if (r == -ENOENT) { |
a1255107 | 1455 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1456 | } else if (r) { |
a1255107 AD |
1457 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1458 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1459 | return r; |
2c1a2784 | 1460 | } else { |
a1255107 | 1461 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1462 | } |
974e6b64 | 1463 | } else { |
a1255107 | 1464 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1465 | } |
d38ceaf9 AD |
1466 | } |
1467 | } | |
1468 | ||
395d1fb9 NH |
1469 | adev->cg_flags &= amdgpu_cg_mask; |
1470 | adev->pg_flags &= amdgpu_pg_mask; | |
1471 | ||
d38ceaf9 AD |
1472 | return 0; |
1473 | } | |
1474 | ||
1475 | static int amdgpu_init(struct amdgpu_device *adev) | |
1476 | { | |
1477 | int i, r; | |
1478 | ||
1479 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1480 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1481 | continue; |
a1255107 | 1482 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1483 | if (r) { |
a1255107 AD |
1484 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1485 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1486 | return r; |
2c1a2784 | 1487 | } |
a1255107 | 1488 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1489 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1490 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1491 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1492 | if (r) { |
1493 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1494 | return r; |
2c1a2784 | 1495 | } |
a1255107 | 1496 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1497 | if (r) { |
1498 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1499 | return r; |
2c1a2784 | 1500 | } |
d38ceaf9 | 1501 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1502 | if (r) { |
1503 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1504 | return r; |
2c1a2784 | 1505 | } |
a1255107 | 1506 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1507 | |
1508 | /* right after GMC hw init, we create CSA */ | |
1509 | if (amdgpu_sriov_vf(adev)) { | |
1510 | r = amdgpu_allocate_static_csa(adev); | |
1511 | if (r) { | |
1512 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1513 | return r; | |
1514 | } | |
1515 | } | |
d38ceaf9 AD |
1516 | } |
1517 | } | |
1518 | ||
1519 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1520 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1521 | continue; |
1522 | /* gmc hw init is done early */ | |
a1255107 | 1523 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1524 | continue; |
a1255107 | 1525 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1526 | if (r) { |
a1255107 AD |
1527 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1528 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1529 | return r; |
2c1a2784 | 1530 | } |
a1255107 | 1531 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1532 | } |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1538 | { | |
1539 | int i = 0, r; | |
1540 | ||
1541 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1542 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1543 | continue; |
a1255107 AD |
1544 | if (adev->ip_blocks[i].version->funcs->late_init) { |
1545 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2c1a2784 | 1546 | if (r) { |
a1255107 AD |
1547 | DRM_ERROR("late_init of IP block <%s> failed %d\n", |
1548 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1549 | return r; |
2c1a2784 | 1550 | } |
a1255107 | 1551 | adev->ip_blocks[i].status.late_initialized = true; |
d38ceaf9 | 1552 | } |
4a446d55 | 1553 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1554 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1555 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1556 | /* enable clockgating to save power */ |
a1255107 AD |
1557 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1558 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1559 | if (r) { |
1560 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1561 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1562 | return r; |
1563 | } | |
b0b00ff1 | 1564 | } |
d38ceaf9 AD |
1565 | } |
1566 | ||
d1aff8ec TSD |
1567 | amdgpu_dpm_enable_uvd(adev, false); |
1568 | amdgpu_dpm_enable_vce(adev, false); | |
1569 | ||
d38ceaf9 AD |
1570 | return 0; |
1571 | } | |
1572 | ||
1573 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1574 | { | |
1575 | int i, r; | |
1576 | ||
3e96dbfd AD |
1577 | /* need to disable SMC first */ |
1578 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1579 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1580 | continue; |
a1255107 | 1581 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1582 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1583 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1584 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1585 | if (r) { |
1586 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1587 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1588 | return r; |
1589 | } | |
a1255107 | 1590 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1591 | /* XXX handle errors */ |
1592 | if (r) { | |
1593 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1594 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1595 | } |
a1255107 | 1596 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1597 | break; |
1598 | } | |
1599 | } | |
1600 | ||
d38ceaf9 | 1601 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1602 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1603 | continue; |
a1255107 | 1604 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1605 | amdgpu_wb_fini(adev); |
1606 | amdgpu_vram_scratch_fini(adev); | |
1607 | } | |
8201a67a RZ |
1608 | |
1609 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1610 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1611 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1612 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1613 | AMD_CG_STATE_UNGATE); | |
1614 | if (r) { | |
1615 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1616 | adev->ip_blocks[i].version->funcs->name, r); | |
1617 | return r; | |
1618 | } | |
2c1a2784 | 1619 | } |
8201a67a | 1620 | |
a1255107 | 1621 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1622 | /* XXX handle errors */ |
2c1a2784 | 1623 | if (r) { |
a1255107 AD |
1624 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1625 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1626 | } |
8201a67a | 1627 | |
a1255107 | 1628 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1629 | } |
1630 | ||
1631 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1632 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1633 | continue; |
a1255107 | 1634 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1635 | /* XXX handle errors */ |
2c1a2784 | 1636 | if (r) { |
a1255107 AD |
1637 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1638 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1639 | } |
a1255107 AD |
1640 | adev->ip_blocks[i].status.sw = false; |
1641 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1642 | } |
1643 | ||
a6dcfd9c | 1644 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1645 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1646 | continue; |
a1255107 AD |
1647 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1648 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1649 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1650 | } |
1651 | ||
3149d9da | 1652 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1653 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1654 | amdgpu_virt_release_full_gpu(adev, false); |
1655 | } | |
2493664f | 1656 | |
d38ceaf9 AD |
1657 | return 0; |
1658 | } | |
1659 | ||
faefba95 | 1660 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1661 | { |
1662 | int i, r; | |
1663 | ||
e941ea99 XY |
1664 | if (amdgpu_sriov_vf(adev)) |
1665 | amdgpu_virt_request_full_gpu(adev, false); | |
1666 | ||
c5a93a28 FC |
1667 | /* ungate SMC block first */ |
1668 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1669 | AMD_CG_STATE_UNGATE); | |
1670 | if (r) { | |
1671 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1672 | } | |
1673 | ||
d38ceaf9 | 1674 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1675 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1676 | continue; |
1677 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1678 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1679 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1680 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1681 | if (r) { |
a1255107 AD |
1682 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1683 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1684 | } |
2c1a2784 | 1685 | } |
d38ceaf9 | 1686 | /* XXX handle errors */ |
a1255107 | 1687 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1688 | /* XXX handle errors */ |
2c1a2784 | 1689 | if (r) { |
a1255107 AD |
1690 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1691 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1692 | } |
d38ceaf9 AD |
1693 | } |
1694 | ||
e941ea99 XY |
1695 | if (amdgpu_sriov_vf(adev)) |
1696 | amdgpu_virt_release_full_gpu(adev, false); | |
1697 | ||
d38ceaf9 AD |
1698 | return 0; |
1699 | } | |
1700 | ||
e4f0fdcc | 1701 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1702 | { |
1703 | int i, r; | |
1704 | ||
1705 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1706 | if (!adev->ip_blocks[i].status.valid) | |
1707 | continue; | |
1708 | ||
1709 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1710 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1711 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) | |
e4f0fdcc | 1712 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); |
a90ad3c2 ML |
1713 | |
1714 | if (r) { | |
1715 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1716 | adev->ip_blocks[i].version->funcs->name, r); | |
1717 | return r; | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | return 0; | |
1722 | } | |
1723 | ||
e4f0fdcc | 1724 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1725 | { |
1726 | int i, r; | |
1727 | ||
1728 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1729 | if (!adev->ip_blocks[i].status.valid) | |
1730 | continue; | |
1731 | ||
1732 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1733 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1734 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1735 | continue; | |
1736 | ||
e4f0fdcc | 1737 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); |
a90ad3c2 ML |
1738 | if (r) { |
1739 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1740 | adev->ip_blocks[i].version->funcs->name, r); | |
1741 | return r; | |
1742 | } | |
1743 | } | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
d38ceaf9 AD |
1748 | static int amdgpu_resume(struct amdgpu_device *adev) |
1749 | { | |
1750 | int i, r; | |
1751 | ||
1752 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1753 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1754 | continue; |
a1255107 | 1755 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1756 | if (r) { |
a1255107 AD |
1757 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1758 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1759 | return r; |
2c1a2784 | 1760 | } |
d38ceaf9 AD |
1761 | } |
1762 | ||
1763 | return 0; | |
1764 | } | |
1765 | ||
4e99a44e | 1766 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1767 | { |
a5bde2f9 AD |
1768 | if (adev->is_atom_fw) { |
1769 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
1770 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1771 | } else { | |
1772 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
1773 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1774 | } | |
048765ad AR |
1775 | } |
1776 | ||
d38ceaf9 AD |
1777 | /** |
1778 | * amdgpu_device_init - initialize the driver | |
1779 | * | |
1780 | * @adev: amdgpu_device pointer | |
1781 | * @pdev: drm dev pointer | |
1782 | * @pdev: pci dev pointer | |
1783 | * @flags: driver flags | |
1784 | * | |
1785 | * Initializes the driver info and hw (all asics). | |
1786 | * Returns 0 for success or an error on failure. | |
1787 | * Called at driver startup. | |
1788 | */ | |
1789 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1790 | struct drm_device *ddev, | |
1791 | struct pci_dev *pdev, | |
1792 | uint32_t flags) | |
1793 | { | |
1794 | int r, i; | |
1795 | bool runtime = false; | |
95844d20 | 1796 | u32 max_MBps; |
d38ceaf9 AD |
1797 | |
1798 | adev->shutdown = false; | |
1799 | adev->dev = &pdev->dev; | |
1800 | adev->ddev = ddev; | |
1801 | adev->pdev = pdev; | |
1802 | adev->flags = flags; | |
2f7d10b3 | 1803 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1804 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
1805 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1806 | adev->accel_working = false; | |
1807 | adev->num_rings = 0; | |
1808 | adev->mman.buffer_funcs = NULL; | |
1809 | adev->mman.buffer_funcs_ring = NULL; | |
1810 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1811 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 1812 | adev->gart.gart_funcs = NULL; |
f54d1867 | 1813 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
1814 | |
1815 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1816 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1817 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1818 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
1819 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
1820 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1821 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
1822 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1823 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1824 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
1825 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
1826 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1827 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
1828 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1829 | ||
ccdbb20a | 1830 | |
3e39ab90 AD |
1831 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1832 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1833 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1834 | |
1835 | /* mutex initialization are all done here so we | |
1836 | * can recall function without having locking issues */ | |
8d0a7cea | 1837 | mutex_init(&adev->vm_manager.lock); |
d38ceaf9 | 1838 | atomic_set(&adev->irq.ih.lock, 0); |
d38ceaf9 AD |
1839 | mutex_init(&adev->pm.mutex); |
1840 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1841 | mutex_init(&adev->srbm_mutex); | |
1842 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
1843 | mutex_init(&adev->mn_lock); |
1844 | hash_init(adev->mn_hash); | |
1845 | ||
1846 | amdgpu_check_arguments(adev); | |
1847 | ||
1848 | /* Registers mapping */ | |
1849 | /* TODO: block userspace mapping of io register */ | |
1850 | spin_lock_init(&adev->mmio_idx_lock); | |
1851 | spin_lock_init(&adev->smc_idx_lock); | |
1852 | spin_lock_init(&adev->pcie_idx_lock); | |
1853 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1854 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 1855 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 1856 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 1857 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 1858 | |
0c4e7fa5 CZ |
1859 | INIT_LIST_HEAD(&adev->shadow_list); |
1860 | mutex_init(&adev->shadow_list_lock); | |
1861 | ||
5c1354bd CZ |
1862 | INIT_LIST_HEAD(&adev->gtt_list); |
1863 | spin_lock_init(&adev->gtt_list_lock); | |
1864 | ||
da69c161 KW |
1865 | if (adev->asic_type >= CHIP_BONAIRE) { |
1866 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1867 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1868 | } else { | |
1869 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
1870 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
1871 | } | |
d38ceaf9 | 1872 | |
d38ceaf9 AD |
1873 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
1874 | if (adev->rmmio == NULL) { | |
1875 | return -ENOMEM; | |
1876 | } | |
1877 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1878 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1879 | ||
da69c161 KW |
1880 | if (adev->asic_type >= CHIP_BONAIRE) |
1881 | /* doorbell bar mapping */ | |
1882 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
1883 | |
1884 | /* io port mapping */ | |
1885 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1886 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1887 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1888 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1889 | break; | |
1890 | } | |
1891 | } | |
1892 | if (adev->rio_mem == NULL) | |
b64a18c5 | 1893 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
1894 | |
1895 | /* early init functions */ | |
1896 | r = amdgpu_early_init(adev); | |
1897 | if (r) | |
1898 | return r; | |
1899 | ||
1900 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1901 | /* this will fail for cards that aren't VGA class devices, just | |
1902 | * ignore it */ | |
1903 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1904 | ||
1905 | if (amdgpu_runtime_pm == 1) | |
1906 | runtime = true; | |
e9bef455 | 1907 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 AD |
1908 | runtime = true; |
1909 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1910 | if (runtime) | |
1911 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1912 | ||
1913 | /* Read BIOS */ | |
83ba126a AD |
1914 | if (!amdgpu_get_bios(adev)) { |
1915 | r = -EINVAL; | |
1916 | goto failed; | |
1917 | } | |
f7e9e9fe | 1918 | |
d38ceaf9 | 1919 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
1920 | if (r) { |
1921 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 1922 | goto failed; |
2c1a2784 | 1923 | } |
d38ceaf9 | 1924 | |
4e99a44e ML |
1925 | /* detect if we are with an SRIOV vbios */ |
1926 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 1927 | |
d38ceaf9 | 1928 | /* Post card if necessary */ |
bec86378 | 1929 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 1930 | if (!adev->bios) { |
bec86378 | 1931 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
1932 | r = -EINVAL; |
1933 | goto failed; | |
d38ceaf9 | 1934 | } |
bec86378 | 1935 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
1936 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
1937 | if (r) { | |
1938 | dev_err(adev->dev, "gpu post error!\n"); | |
1939 | goto failed; | |
1940 | } | |
1941 | } else { | |
1942 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
1943 | } |
1944 | ||
a5bde2f9 AD |
1945 | if (!adev->is_atom_fw) { |
1946 | /* Initialize clocks */ | |
1947 | r = amdgpu_atombios_get_clock_info(adev); | |
1948 | if (r) { | |
1949 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
1950 | return r; | |
1951 | } | |
1952 | /* init i2c buses */ | |
1953 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 1954 | } |
d38ceaf9 AD |
1955 | |
1956 | /* Fence driver */ | |
1957 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1958 | if (r) { |
1959 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 1960 | goto failed; |
2c1a2784 | 1961 | } |
d38ceaf9 AD |
1962 | |
1963 | /* init the mode config */ | |
1964 | drm_mode_config_init(adev->ddev); | |
1965 | ||
1966 | r = amdgpu_init(adev); | |
1967 | if (r) { | |
2c1a2784 | 1968 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 1969 | amdgpu_fini(adev); |
83ba126a | 1970 | goto failed; |
d38ceaf9 AD |
1971 | } |
1972 | ||
1973 | adev->accel_working = true; | |
1974 | ||
95844d20 MO |
1975 | /* Initialize the buffer migration limit. */ |
1976 | if (amdgpu_moverate >= 0) | |
1977 | max_MBps = amdgpu_moverate; | |
1978 | else | |
1979 | max_MBps = 8; /* Allow 8 MB/s. */ | |
1980 | /* Get a log2 for easy divisions. */ | |
1981 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
1982 | ||
d38ceaf9 AD |
1983 | r = amdgpu_ib_pool_init(adev); |
1984 | if (r) { | |
1985 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 1986 | goto failed; |
d38ceaf9 AD |
1987 | } |
1988 | ||
1989 | r = amdgpu_ib_ring_tests(adev); | |
1990 | if (r) | |
1991 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1992 | ||
9bc92b9c ML |
1993 | amdgpu_fbdev_init(adev); |
1994 | ||
d38ceaf9 | 1995 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 1996 | if (r) |
d38ceaf9 | 1997 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
1998 | |
1999 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2000 | if (r) |
d38ceaf9 | 2001 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2002 | |
50ab2533 | 2003 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2004 | if (r) |
50ab2533 | 2005 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2006 | |
d38ceaf9 AD |
2007 | if ((amdgpu_testing & 1)) { |
2008 | if (adev->accel_working) | |
2009 | amdgpu_test_moves(adev); | |
2010 | else | |
2011 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2012 | } | |
d38ceaf9 AD |
2013 | if (amdgpu_benchmarking) { |
2014 | if (adev->accel_working) | |
2015 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2016 | else | |
2017 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2018 | } | |
2019 | ||
2020 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2021 | * explicit gating rather than handling it automatically. | |
2022 | */ | |
2023 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2024 | if (r) { |
2025 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 2026 | goto failed; |
2c1a2784 | 2027 | } |
d38ceaf9 AD |
2028 | |
2029 | return 0; | |
83ba126a AD |
2030 | |
2031 | failed: | |
2032 | if (runtime) | |
2033 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2034 | return r; | |
d38ceaf9 AD |
2035 | } |
2036 | ||
d38ceaf9 AD |
2037 | /** |
2038 | * amdgpu_device_fini - tear down the driver | |
2039 | * | |
2040 | * @adev: amdgpu_device pointer | |
2041 | * | |
2042 | * Tear down the driver info (all asics). | |
2043 | * Called at driver shutdown. | |
2044 | */ | |
2045 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2046 | { | |
2047 | int r; | |
2048 | ||
2049 | DRM_INFO("amdgpu: finishing device.\n"); | |
2050 | adev->shutdown = true; | |
a951ed85 | 2051 | drm_crtc_force_disable_all(adev->ddev); |
d38ceaf9 AD |
2052 | /* evict vram memory */ |
2053 | amdgpu_bo_evict_vram(adev); | |
2054 | amdgpu_ib_pool_fini(adev); | |
2055 | amdgpu_fence_driver_fini(adev); | |
2056 | amdgpu_fbdev_fini(adev); | |
2057 | r = amdgpu_fini(adev); | |
d38ceaf9 AD |
2058 | adev->accel_working = false; |
2059 | /* free i2c buses */ | |
2060 | amdgpu_i2c_fini(adev); | |
2061 | amdgpu_atombios_fini(adev); | |
2062 | kfree(adev->bios); | |
2063 | adev->bios = NULL; | |
2064 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2065 | if (adev->flags & AMD_IS_PX) |
2066 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2067 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2068 | if (adev->rio_mem) | |
2069 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2070 | adev->rio_mem = NULL; | |
2071 | iounmap(adev->rmmio); | |
2072 | adev->rmmio = NULL; | |
da69c161 KW |
2073 | if (adev->asic_type >= CHIP_BONAIRE) |
2074 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2075 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2076 | } |
2077 | ||
2078 | ||
2079 | /* | |
2080 | * Suspend & resume. | |
2081 | */ | |
2082 | /** | |
810ddc3a | 2083 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2084 | * |
2085 | * @pdev: drm dev pointer | |
2086 | * @state: suspend state | |
2087 | * | |
2088 | * Puts the hw in the suspend state (all asics). | |
2089 | * Returns 0 for success or an error on failure. | |
2090 | * Called at driver suspend. | |
2091 | */ | |
810ddc3a | 2092 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2093 | { |
2094 | struct amdgpu_device *adev; | |
2095 | struct drm_crtc *crtc; | |
2096 | struct drm_connector *connector; | |
5ceb54c6 | 2097 | int r; |
d38ceaf9 AD |
2098 | |
2099 | if (dev == NULL || dev->dev_private == NULL) { | |
2100 | return -ENODEV; | |
2101 | } | |
2102 | ||
2103 | adev = dev->dev_private; | |
2104 | ||
2105 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2106 | return 0; | |
2107 | ||
2108 | drm_kms_helper_poll_disable(dev); | |
2109 | ||
2110 | /* turn off display hw */ | |
4c7fbc39 | 2111 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2112 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2113 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2114 | } | |
4c7fbc39 | 2115 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2116 | |
756e6880 | 2117 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2118 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2119 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2120 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2121 | struct amdgpu_bo *robj; | |
2122 | ||
756e6880 AD |
2123 | if (amdgpu_crtc->cursor_bo) { |
2124 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2125 | r = amdgpu_bo_reserve(aobj, false); | |
2126 | if (r == 0) { | |
2127 | amdgpu_bo_unpin(aobj); | |
2128 | amdgpu_bo_unreserve(aobj); | |
2129 | } | |
2130 | } | |
2131 | ||
d38ceaf9 AD |
2132 | if (rfb == NULL || rfb->obj == NULL) { |
2133 | continue; | |
2134 | } | |
2135 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2136 | /* don't unpin kernel fb objects */ | |
2137 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
2138 | r = amdgpu_bo_reserve(robj, false); | |
2139 | if (r == 0) { | |
2140 | amdgpu_bo_unpin(robj); | |
2141 | amdgpu_bo_unreserve(robj); | |
2142 | } | |
2143 | } | |
2144 | } | |
2145 | /* evict vram memory */ | |
2146 | amdgpu_bo_evict_vram(adev); | |
2147 | ||
5ceb54c6 | 2148 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2149 | |
2150 | r = amdgpu_suspend(adev); | |
2151 | ||
a0a71e49 AD |
2152 | /* evict remaining vram memory |
2153 | * This second call to evict vram is to evict the gart page table | |
2154 | * using the CPU. | |
2155 | */ | |
d38ceaf9 AD |
2156 | amdgpu_bo_evict_vram(adev); |
2157 | ||
e695e77c | 2158 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
2159 | pci_save_state(dev->pdev); |
2160 | if (suspend) { | |
2161 | /* Shut down the device */ | |
2162 | pci_disable_device(dev->pdev); | |
2163 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2164 | } else { |
2165 | r = amdgpu_asic_reset(adev); | |
2166 | if (r) | |
2167 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2168 | } |
2169 | ||
2170 | if (fbcon) { | |
2171 | console_lock(); | |
2172 | amdgpu_fbdev_set_suspend(adev, 1); | |
2173 | console_unlock(); | |
2174 | } | |
2175 | return 0; | |
2176 | } | |
2177 | ||
2178 | /** | |
810ddc3a | 2179 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2180 | * |
2181 | * @pdev: drm dev pointer | |
2182 | * | |
2183 | * Bring the hw back to operating state (all asics). | |
2184 | * Returns 0 for success or an error on failure. | |
2185 | * Called at driver resume. | |
2186 | */ | |
810ddc3a | 2187 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2188 | { |
2189 | struct drm_connector *connector; | |
2190 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2191 | struct drm_crtc *crtc; |
d38ceaf9 AD |
2192 | int r; |
2193 | ||
2194 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2195 | return 0; | |
2196 | ||
74b0b157 | 2197 | if (fbcon) |
d38ceaf9 | 2198 | console_lock(); |
74b0b157 | 2199 | |
d38ceaf9 AD |
2200 | if (resume) { |
2201 | pci_set_power_state(dev->pdev, PCI_D0); | |
2202 | pci_restore_state(dev->pdev); | |
74b0b157 | 2203 | r = pci_enable_device(dev->pdev); |
2204 | if (r) { | |
d38ceaf9 AD |
2205 | if (fbcon) |
2206 | console_unlock(); | |
74b0b157 | 2207 | return r; |
d38ceaf9 AD |
2208 | } |
2209 | } | |
e695e77c | 2210 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2211 | |
2212 | /* post card */ | |
c836fec5 | 2213 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2214 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2215 | if (r) | |
2216 | DRM_ERROR("amdgpu asic init failed\n"); | |
2217 | } | |
d38ceaf9 AD |
2218 | |
2219 | r = amdgpu_resume(adev); | |
ca198528 FC |
2220 | if (r) |
2221 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); | |
d38ceaf9 | 2222 | |
5ceb54c6 AD |
2223 | amdgpu_fence_driver_resume(adev); |
2224 | ||
ca198528 FC |
2225 | if (resume) { |
2226 | r = amdgpu_ib_ring_tests(adev); | |
2227 | if (r) | |
2228 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2229 | } | |
d38ceaf9 AD |
2230 | |
2231 | r = amdgpu_late_init(adev); | |
c085bd51 JQ |
2232 | if (r) { |
2233 | if (fbcon) | |
2234 | console_unlock(); | |
d38ceaf9 | 2235 | return r; |
c085bd51 | 2236 | } |
d38ceaf9 | 2237 | |
756e6880 AD |
2238 | /* pin cursors */ |
2239 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2240 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2241 | ||
2242 | if (amdgpu_crtc->cursor_bo) { | |
2243 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2244 | r = amdgpu_bo_reserve(aobj, false); | |
2245 | if (r == 0) { | |
2246 | r = amdgpu_bo_pin(aobj, | |
2247 | AMDGPU_GEM_DOMAIN_VRAM, | |
2248 | &amdgpu_crtc->cursor_addr); | |
2249 | if (r != 0) | |
2250 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2251 | amdgpu_bo_unreserve(aobj); | |
2252 | } | |
2253 | } | |
2254 | } | |
2255 | ||
d38ceaf9 AD |
2256 | /* blat the mode back in */ |
2257 | if (fbcon) { | |
2258 | drm_helper_resume_force_mode(dev); | |
2259 | /* turn on display hw */ | |
4c7fbc39 | 2260 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2261 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2262 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2263 | } | |
4c7fbc39 | 2264 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2265 | } |
2266 | ||
2267 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2268 | |
2269 | /* | |
2270 | * Most of the connector probing functions try to acquire runtime pm | |
2271 | * refs to ensure that the GPU is powered on when connector polling is | |
2272 | * performed. Since we're calling this from a runtime PM callback, | |
2273 | * trying to acquire rpm refs will cause us to deadlock. | |
2274 | * | |
2275 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2276 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2277 | */ | |
2278 | #ifdef CONFIG_PM | |
2279 | dev->dev->power.disable_depth++; | |
2280 | #endif | |
54fb2a5c | 2281 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2282 | #ifdef CONFIG_PM |
2283 | dev->dev->power.disable_depth--; | |
2284 | #endif | |
d38ceaf9 AD |
2285 | |
2286 | if (fbcon) { | |
2287 | amdgpu_fbdev_set_suspend(adev, 0); | |
2288 | console_unlock(); | |
2289 | } | |
2290 | ||
2291 | return 0; | |
2292 | } | |
2293 | ||
63fbf42f CZ |
2294 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2295 | { | |
2296 | int i; | |
2297 | bool asic_hang = false; | |
2298 | ||
2299 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2300 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2301 | continue; |
a1255107 AD |
2302 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2303 | adev->ip_blocks[i].status.hang = | |
2304 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2305 | if (adev->ip_blocks[i].status.hang) { | |
2306 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2307 | asic_hang = true; |
2308 | } | |
2309 | } | |
2310 | return asic_hang; | |
2311 | } | |
2312 | ||
4d446656 | 2313 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2314 | { |
2315 | int i, r = 0; | |
2316 | ||
2317 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2318 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2319 | continue; |
a1255107 AD |
2320 | if (adev->ip_blocks[i].status.hang && |
2321 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2322 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2323 | if (r) |
2324 | return r; | |
2325 | } | |
2326 | } | |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | ||
35d782fe CZ |
2331 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2332 | { | |
da146d3b AD |
2333 | int i; |
2334 | ||
2335 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2336 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2337 | continue; |
a1255107 AD |
2338 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2339 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2340 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2341 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2342 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2343 | DRM_INFO("Some block need full reset!\n"); |
2344 | return true; | |
2345 | } | |
2346 | } | |
35d782fe CZ |
2347 | } |
2348 | return false; | |
2349 | } | |
2350 | ||
2351 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2352 | { | |
2353 | int i, r = 0; | |
2354 | ||
2355 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2356 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2357 | continue; |
a1255107 AD |
2358 | if (adev->ip_blocks[i].status.hang && |
2359 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2360 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2361 | if (r) |
2362 | return r; | |
2363 | } | |
2364 | } | |
2365 | ||
2366 | return 0; | |
2367 | } | |
2368 | ||
2369 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2370 | { | |
2371 | int i, r = 0; | |
2372 | ||
2373 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2374 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2375 | continue; |
a1255107 AD |
2376 | if (adev->ip_blocks[i].status.hang && |
2377 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2378 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2379 | if (r) |
2380 | return r; | |
2381 | } | |
2382 | ||
2383 | return 0; | |
2384 | } | |
2385 | ||
3ad81f16 CZ |
2386 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2387 | { | |
2388 | if (adev->flags & AMD_IS_APU) | |
2389 | return false; | |
2390 | ||
2391 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2392 | } | |
2393 | ||
53cdccd5 CZ |
2394 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2395 | struct amdgpu_ring *ring, | |
2396 | struct amdgpu_bo *bo, | |
f54d1867 | 2397 | struct dma_fence **fence) |
53cdccd5 CZ |
2398 | { |
2399 | uint32_t domain; | |
2400 | int r; | |
2401 | ||
2402 | if (!bo->shadow) | |
2403 | return 0; | |
2404 | ||
2405 | r = amdgpu_bo_reserve(bo, false); | |
2406 | if (r) | |
2407 | return r; | |
2408 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2409 | /* if bo has been evicted, then no need to recover */ | |
2410 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
2411 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, | |
2412 | NULL, fence, true); | |
2413 | if (r) { | |
2414 | DRM_ERROR("recover page table failed!\n"); | |
2415 | goto err; | |
2416 | } | |
2417 | } | |
2418 | err: | |
2419 | amdgpu_bo_unreserve(bo); | |
2420 | return r; | |
2421 | } | |
2422 | ||
a90ad3c2 ML |
2423 | /** |
2424 | * amdgpu_sriov_gpu_reset - reset the asic | |
2425 | * | |
2426 | * @adev: amdgpu device pointer | |
2427 | * @voluntary: if this reset is requested by guest. | |
2428 | * (true means by guest and false means by HYPERVISOR ) | |
2429 | * | |
2430 | * Attempt the reset the GPU if it has hung (all asics). | |
2431 | * for SRIOV case. | |
2432 | * Returns 0 for success or an error on failure. | |
2433 | */ | |
2434 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary) | |
2435 | { | |
2436 | int i, r = 0; | |
2437 | int resched; | |
2438 | struct amdgpu_bo *bo, *tmp; | |
2439 | struct amdgpu_ring *ring; | |
2440 | struct dma_fence *fence = NULL, *next = NULL; | |
2441 | ||
147b5983 | 2442 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2443 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2444 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2445 | |
2446 | /* block TTM */ | |
2447 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2448 | ||
2449 | /* block scheduler */ | |
2450 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2451 | ring = adev->rings[i]; | |
2452 | ||
2453 | if (!ring || !ring->sched.thread) | |
2454 | continue; | |
2455 | ||
2456 | kthread_park(ring->sched.thread); | |
2457 | amd_sched_hw_job_reset(&ring->sched); | |
2458 | } | |
2459 | ||
2460 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ | |
2461 | amdgpu_fence_driver_force_completion(adev); | |
2462 | ||
2463 | /* request to take full control of GPU before re-initialization */ | |
2464 | if (voluntary) | |
2465 | amdgpu_virt_reset_gpu(adev); | |
2466 | else | |
2467 | amdgpu_virt_request_full_gpu(adev, true); | |
2468 | ||
2469 | ||
2470 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2471 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2472 | |
2473 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2474 | amdgpu_ttm_recover_gart(adev); | |
2475 | ||
2476 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2477 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2478 | |
2479 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2480 | ||
2481 | if (amdgpu_ib_ring_tests(adev)) | |
2482 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2483 | ||
2484 | /* release full control of GPU after ib test */ | |
2485 | amdgpu_virt_release_full_gpu(adev, true); | |
2486 | ||
2487 | DRM_INFO("recover vram bo from shadow\n"); | |
2488 | ||
2489 | ring = adev->mman.buffer_funcs_ring; | |
2490 | mutex_lock(&adev->shadow_list_lock); | |
2491 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2492 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); | |
2493 | if (fence) { | |
2494 | r = dma_fence_wait(fence, false); | |
2495 | if (r) { | |
2496 | WARN(r, "recovery from shadow isn't completed\n"); | |
2497 | break; | |
2498 | } | |
2499 | } | |
2500 | ||
2501 | dma_fence_put(fence); | |
2502 | fence = next; | |
2503 | } | |
2504 | mutex_unlock(&adev->shadow_list_lock); | |
2505 | ||
2506 | if (fence) { | |
2507 | r = dma_fence_wait(fence, false); | |
2508 | if (r) | |
2509 | WARN(r, "recovery from shadow isn't completed\n"); | |
2510 | } | |
2511 | dma_fence_put(fence); | |
2512 | ||
2513 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2514 | struct amdgpu_ring *ring = adev->rings[i]; | |
2515 | if (!ring || !ring->sched.thread) | |
2516 | continue; | |
2517 | ||
2518 | amd_sched_job_recovery(&ring->sched); | |
2519 | kthread_unpark(ring->sched.thread); | |
2520 | } | |
2521 | ||
2522 | drm_helper_resume_force_mode(adev->ddev); | |
2523 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2524 | if (r) { | |
2525 | /* bad news, how to tell it to userspace ? */ | |
2526 | dev_info(adev->dev, "GPU reset failed\n"); | |
2527 | } | |
2528 | ||
1fb37a3d | 2529 | adev->gfx.in_reset = false; |
147b5983 | 2530 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2531 | return r; |
2532 | } | |
2533 | ||
d38ceaf9 AD |
2534 | /** |
2535 | * amdgpu_gpu_reset - reset the asic | |
2536 | * | |
2537 | * @adev: amdgpu device pointer | |
2538 | * | |
2539 | * Attempt the reset the GPU if it has hung (all asics). | |
2540 | * Returns 0 for success or an error on failure. | |
2541 | */ | |
2542 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2543 | { | |
d38ceaf9 AD |
2544 | int i, r; |
2545 | int resched; | |
35d782fe | 2546 | bool need_full_reset; |
d38ceaf9 | 2547 | |
fb140b29 | 2548 | if (amdgpu_sriov_vf(adev)) |
a90ad3c2 | 2549 | return amdgpu_sriov_gpu_reset(adev, true); |
fb140b29 | 2550 | |
63fbf42f CZ |
2551 | if (!amdgpu_check_soft_reset(adev)) { |
2552 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2553 | return 0; | |
2554 | } | |
d38ceaf9 | 2555 | |
d94aed5a | 2556 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2557 | |
a3c47d6b CZ |
2558 | /* block TTM */ |
2559 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2560 | ||
0875dc9e CZ |
2561 | /* block scheduler */ |
2562 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2563 | struct amdgpu_ring *ring = adev->rings[i]; | |
2564 | ||
2565 | if (!ring) | |
2566 | continue; | |
2567 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2568 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2569 | } |
2200edac CZ |
2570 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2571 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2572 | |
35d782fe | 2573 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2574 | |
35d782fe CZ |
2575 | if (!need_full_reset) { |
2576 | amdgpu_pre_soft_reset(adev); | |
2577 | r = amdgpu_soft_reset(adev); | |
2578 | amdgpu_post_soft_reset(adev); | |
2579 | if (r || amdgpu_check_soft_reset(adev)) { | |
2580 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2581 | need_full_reset = true; | |
2582 | } | |
f1aa7e08 CZ |
2583 | } |
2584 | ||
35d782fe | 2585 | if (need_full_reset) { |
35d782fe | 2586 | r = amdgpu_suspend(adev); |
bfa99269 | 2587 | |
35d782fe CZ |
2588 | retry: |
2589 | /* Disable fb access */ | |
2590 | if (adev->mode_info.num_crtc) { | |
2591 | struct amdgpu_mode_mc_save save; | |
2592 | amdgpu_display_stop_mc_access(adev, &save); | |
2593 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
2594 | } | |
e695e77c | 2595 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2596 | r = amdgpu_asic_reset(adev); |
e695e77c | 2597 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2598 | /* post card */ |
2599 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2600 | ||
2601 | if (!r) { | |
2602 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
2603 | r = amdgpu_resume(adev); | |
2604 | } | |
d38ceaf9 | 2605 | } |
d38ceaf9 | 2606 | if (!r) { |
e72cfd58 | 2607 | amdgpu_irq_gpu_reset_resume_helper(adev); |
2c0d7318 CZ |
2608 | if (need_full_reset && amdgpu_need_backup(adev)) { |
2609 | r = amdgpu_ttm_recover_gart(adev); | |
2610 | if (r) | |
2611 | DRM_ERROR("gart recovery failed!!!\n"); | |
2612 | } | |
1f465087 CZ |
2613 | r = amdgpu_ib_ring_tests(adev); |
2614 | if (r) { | |
2615 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2616 | r = amdgpu_suspend(adev); |
53cdccd5 | 2617 | need_full_reset = true; |
40019dc4 | 2618 | goto retry; |
1f465087 | 2619 | } |
53cdccd5 CZ |
2620 | /** |
2621 | * recovery vm page tables, since we cannot depend on VRAM is | |
2622 | * consistent after gpu full reset. | |
2623 | */ | |
2624 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2625 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2626 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2627 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2628 | |
2629 | DRM_INFO("recover vram bo from shadow\n"); | |
2630 | mutex_lock(&adev->shadow_list_lock); | |
2631 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2632 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); | |
2633 | if (fence) { | |
f54d1867 | 2634 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2635 | if (r) { |
1d7b17b0 | 2636 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2637 | break; |
2638 | } | |
2639 | } | |
1f465087 | 2640 | |
f54d1867 | 2641 | dma_fence_put(fence); |
53cdccd5 CZ |
2642 | fence = next; |
2643 | } | |
2644 | mutex_unlock(&adev->shadow_list_lock); | |
2645 | if (fence) { | |
f54d1867 | 2646 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2647 | if (r) |
1d7b17b0 | 2648 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2649 | } |
f54d1867 | 2650 | dma_fence_put(fence); |
53cdccd5 | 2651 | } |
d38ceaf9 AD |
2652 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2653 | struct amdgpu_ring *ring = adev->rings[i]; | |
2654 | if (!ring) | |
2655 | continue; | |
53cdccd5 | 2656 | |
aa1c8900 | 2657 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2658 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2659 | } |
d38ceaf9 | 2660 | } else { |
2200edac | 2661 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2662 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
0875dc9e CZ |
2663 | if (adev->rings[i]) { |
2664 | kthread_unpark(adev->rings[i]->sched.thread); | |
0875dc9e | 2665 | } |
d38ceaf9 AD |
2666 | } |
2667 | } | |
2668 | ||
2669 | drm_helper_resume_force_mode(adev->ddev); | |
2670 | ||
2671 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2672 | if (r) { | |
2673 | /* bad news, how to tell it to userspace ? */ | |
2674 | dev_info(adev->dev, "GPU reset failed\n"); | |
2675 | } | |
2676 | ||
d38ceaf9 AD |
2677 | return r; |
2678 | } | |
2679 | ||
d0dd7f0c AD |
2680 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2681 | { | |
2682 | u32 mask; | |
2683 | int ret; | |
2684 | ||
cd474ba0 AD |
2685 | if (amdgpu_pcie_gen_cap) |
2686 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2687 | |
cd474ba0 AD |
2688 | if (amdgpu_pcie_lane_cap) |
2689 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2690 | |
cd474ba0 AD |
2691 | /* covers APUs as well */ |
2692 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2693 | if (adev->pm.pcie_gen_mask == 0) | |
2694 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2695 | if (adev->pm.pcie_mlw_mask == 0) | |
2696 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2697 | return; |
cd474ba0 | 2698 | } |
d0dd7f0c | 2699 | |
cd474ba0 AD |
2700 | if (adev->pm.pcie_gen_mask == 0) { |
2701 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2702 | if (!ret) { | |
2703 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2704 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2705 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2706 | ||
2707 | if (mask & DRM_PCIE_SPEED_25) | |
2708 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2709 | if (mask & DRM_PCIE_SPEED_50) | |
2710 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2711 | if (mask & DRM_PCIE_SPEED_80) | |
2712 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2713 | } else { | |
2714 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2715 | } | |
2716 | } | |
2717 | if (adev->pm.pcie_mlw_mask == 0) { | |
2718 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2719 | if (!ret) { | |
2720 | switch (mask) { | |
2721 | case 32: | |
2722 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2723 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2724 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2725 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2726 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2727 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2728 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2729 | break; | |
2730 | case 16: | |
2731 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2732 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2733 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2734 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2735 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2736 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2737 | break; | |
2738 | case 12: | |
2739 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2740 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2741 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2742 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2743 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2744 | break; | |
2745 | case 8: | |
2746 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2747 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2748 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2749 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2750 | break; | |
2751 | case 4: | |
2752 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2753 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2754 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2755 | break; | |
2756 | case 2: | |
2757 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2758 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2759 | break; | |
2760 | case 1: | |
2761 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2762 | break; | |
2763 | default: | |
2764 | break; | |
2765 | } | |
2766 | } else { | |
2767 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2768 | } |
2769 | } | |
2770 | } | |
d38ceaf9 AD |
2771 | |
2772 | /* | |
2773 | * Debugfs | |
2774 | */ | |
2775 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 2776 | const struct drm_info_list *files, |
d38ceaf9 AD |
2777 | unsigned nfiles) |
2778 | { | |
2779 | unsigned i; | |
2780 | ||
2781 | for (i = 0; i < adev->debugfs_count; i++) { | |
2782 | if (adev->debugfs[i].files == files) { | |
2783 | /* Already registered */ | |
2784 | return 0; | |
2785 | } | |
2786 | } | |
2787 | ||
2788 | i = adev->debugfs_count + 1; | |
2789 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
2790 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
2791 | DRM_ERROR("Report so we increase " | |
2792 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
2793 | return -EINVAL; | |
2794 | } | |
2795 | adev->debugfs[adev->debugfs_count].files = files; | |
2796 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
2797 | adev->debugfs_count = i; | |
2798 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
2799 | drm_debugfs_create_files(files, nfiles, |
2800 | adev->ddev->primary->debugfs_root, | |
2801 | adev->ddev->primary); | |
2802 | #endif | |
2803 | return 0; | |
2804 | } | |
2805 | ||
d38ceaf9 AD |
2806 | #if defined(CONFIG_DEBUG_FS) |
2807 | ||
2808 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
2809 | size_t size, loff_t *pos) | |
2810 | { | |
45063097 | 2811 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
2812 | ssize_t result = 0; |
2813 | int r; | |
bd12267d | 2814 | bool pm_pg_lock, use_bank; |
56628159 | 2815 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
2816 | |
2817 | if (size & 0x3 || *pos & 0x3) | |
2818 | return -EINVAL; | |
2819 | ||
bd12267d TSD |
2820 | /* are we reading registers for which a PG lock is necessary? */ |
2821 | pm_pg_lock = (*pos >> 23) & 1; | |
2822 | ||
56628159 TSD |
2823 | if (*pos & (1ULL << 62)) { |
2824 | se_bank = (*pos >> 24) & 0x3FF; | |
2825 | sh_bank = (*pos >> 34) & 0x3FF; | |
2826 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
2827 | |
2828 | if (se_bank == 0x3FF) | |
2829 | se_bank = 0xFFFFFFFF; | |
2830 | if (sh_bank == 0x3FF) | |
2831 | sh_bank = 0xFFFFFFFF; | |
2832 | if (instance_bank == 0x3FF) | |
2833 | instance_bank = 0xFFFFFFFF; | |
56628159 | 2834 | use_bank = 1; |
56628159 TSD |
2835 | } else { |
2836 | use_bank = 0; | |
2837 | } | |
2838 | ||
801a6aa9 | 2839 | *pos &= (1UL << 22) - 1; |
bd12267d | 2840 | |
56628159 | 2841 | if (use_bank) { |
32977f93 TSD |
2842 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
2843 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
2844 | return -EINVAL; |
2845 | mutex_lock(&adev->grbm_idx_mutex); | |
2846 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2847 | sh_bank, instance_bank); | |
2848 | } | |
2849 | ||
bd12267d TSD |
2850 | if (pm_pg_lock) |
2851 | mutex_lock(&adev->pm.mutex); | |
2852 | ||
d38ceaf9 AD |
2853 | while (size) { |
2854 | uint32_t value; | |
2855 | ||
2856 | if (*pos > adev->rmmio_size) | |
56628159 | 2857 | goto end; |
d38ceaf9 AD |
2858 | |
2859 | value = RREG32(*pos >> 2); | |
2860 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
2861 | if (r) { |
2862 | result = r; | |
2863 | goto end; | |
2864 | } | |
d38ceaf9 AD |
2865 | |
2866 | result += 4; | |
2867 | buf += 4; | |
2868 | *pos += 4; | |
2869 | size -= 4; | |
2870 | } | |
2871 | ||
56628159 TSD |
2872 | end: |
2873 | if (use_bank) { | |
2874 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2875 | mutex_unlock(&adev->grbm_idx_mutex); | |
2876 | } | |
2877 | ||
bd12267d TSD |
2878 | if (pm_pg_lock) |
2879 | mutex_unlock(&adev->pm.mutex); | |
2880 | ||
d38ceaf9 AD |
2881 | return result; |
2882 | } | |
2883 | ||
2884 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
2885 | size_t size, loff_t *pos) | |
2886 | { | |
45063097 | 2887 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
2888 | ssize_t result = 0; |
2889 | int r; | |
394fdde2 TSD |
2890 | bool pm_pg_lock, use_bank; |
2891 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
2892 | |
2893 | if (size & 0x3 || *pos & 0x3) | |
2894 | return -EINVAL; | |
2895 | ||
394fdde2 TSD |
2896 | /* are we reading registers for which a PG lock is necessary? */ |
2897 | pm_pg_lock = (*pos >> 23) & 1; | |
2898 | ||
2899 | if (*pos & (1ULL << 62)) { | |
2900 | se_bank = (*pos >> 24) & 0x3FF; | |
2901 | sh_bank = (*pos >> 34) & 0x3FF; | |
2902 | instance_bank = (*pos >> 44) & 0x3FF; | |
2903 | ||
2904 | if (se_bank == 0x3FF) | |
2905 | se_bank = 0xFFFFFFFF; | |
2906 | if (sh_bank == 0x3FF) | |
2907 | sh_bank = 0xFFFFFFFF; | |
2908 | if (instance_bank == 0x3FF) | |
2909 | instance_bank = 0xFFFFFFFF; | |
2910 | use_bank = 1; | |
2911 | } else { | |
2912 | use_bank = 0; | |
2913 | } | |
2914 | ||
801a6aa9 | 2915 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
2916 | |
2917 | if (use_bank) { | |
2918 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
2919 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
2920 | return -EINVAL; | |
2921 | mutex_lock(&adev->grbm_idx_mutex); | |
2922 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2923 | sh_bank, instance_bank); | |
2924 | } | |
2925 | ||
2926 | if (pm_pg_lock) | |
2927 | mutex_lock(&adev->pm.mutex); | |
2928 | ||
d38ceaf9 AD |
2929 | while (size) { |
2930 | uint32_t value; | |
2931 | ||
2932 | if (*pos > adev->rmmio_size) | |
2933 | return result; | |
2934 | ||
2935 | r = get_user(value, (uint32_t *)buf); | |
2936 | if (r) | |
2937 | return r; | |
2938 | ||
2939 | WREG32(*pos >> 2, value); | |
2940 | ||
2941 | result += 4; | |
2942 | buf += 4; | |
2943 | *pos += 4; | |
2944 | size -= 4; | |
2945 | } | |
2946 | ||
394fdde2 TSD |
2947 | if (use_bank) { |
2948 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2949 | mutex_unlock(&adev->grbm_idx_mutex); | |
2950 | } | |
2951 | ||
2952 | if (pm_pg_lock) | |
2953 | mutex_unlock(&adev->pm.mutex); | |
2954 | ||
d38ceaf9 AD |
2955 | return result; |
2956 | } | |
2957 | ||
adcec288 TSD |
2958 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
2959 | size_t size, loff_t *pos) | |
2960 | { | |
45063097 | 2961 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
2962 | ssize_t result = 0; |
2963 | int r; | |
2964 | ||
2965 | if (size & 0x3 || *pos & 0x3) | |
2966 | return -EINVAL; | |
2967 | ||
2968 | while (size) { | |
2969 | uint32_t value; | |
2970 | ||
2971 | value = RREG32_PCIE(*pos >> 2); | |
2972 | r = put_user(value, (uint32_t *)buf); | |
2973 | if (r) | |
2974 | return r; | |
2975 | ||
2976 | result += 4; | |
2977 | buf += 4; | |
2978 | *pos += 4; | |
2979 | size -= 4; | |
2980 | } | |
2981 | ||
2982 | return result; | |
2983 | } | |
2984 | ||
2985 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
2986 | size_t size, loff_t *pos) | |
2987 | { | |
45063097 | 2988 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
2989 | ssize_t result = 0; |
2990 | int r; | |
2991 | ||
2992 | if (size & 0x3 || *pos & 0x3) | |
2993 | return -EINVAL; | |
2994 | ||
2995 | while (size) { | |
2996 | uint32_t value; | |
2997 | ||
2998 | r = get_user(value, (uint32_t *)buf); | |
2999 | if (r) | |
3000 | return r; | |
3001 | ||
3002 | WREG32_PCIE(*pos >> 2, value); | |
3003 | ||
3004 | result += 4; | |
3005 | buf += 4; | |
3006 | *pos += 4; | |
3007 | size -= 4; | |
3008 | } | |
3009 | ||
3010 | return result; | |
3011 | } | |
3012 | ||
3013 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3014 | size_t size, loff_t *pos) | |
3015 | { | |
45063097 | 3016 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3017 | ssize_t result = 0; |
3018 | int r; | |
3019 | ||
3020 | if (size & 0x3 || *pos & 0x3) | |
3021 | return -EINVAL; | |
3022 | ||
3023 | while (size) { | |
3024 | uint32_t value; | |
3025 | ||
3026 | value = RREG32_DIDT(*pos >> 2); | |
3027 | r = put_user(value, (uint32_t *)buf); | |
3028 | if (r) | |
3029 | return r; | |
3030 | ||
3031 | result += 4; | |
3032 | buf += 4; | |
3033 | *pos += 4; | |
3034 | size -= 4; | |
3035 | } | |
3036 | ||
3037 | return result; | |
3038 | } | |
3039 | ||
3040 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3041 | size_t size, loff_t *pos) | |
3042 | { | |
45063097 | 3043 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3044 | ssize_t result = 0; |
3045 | int r; | |
3046 | ||
3047 | if (size & 0x3 || *pos & 0x3) | |
3048 | return -EINVAL; | |
3049 | ||
3050 | while (size) { | |
3051 | uint32_t value; | |
3052 | ||
3053 | r = get_user(value, (uint32_t *)buf); | |
3054 | if (r) | |
3055 | return r; | |
3056 | ||
3057 | WREG32_DIDT(*pos >> 2, value); | |
3058 | ||
3059 | result += 4; | |
3060 | buf += 4; | |
3061 | *pos += 4; | |
3062 | size -= 4; | |
3063 | } | |
3064 | ||
3065 | return result; | |
3066 | } | |
3067 | ||
3068 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3069 | size_t size, loff_t *pos) | |
3070 | { | |
45063097 | 3071 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3072 | ssize_t result = 0; |
3073 | int r; | |
3074 | ||
3075 | if (size & 0x3 || *pos & 0x3) | |
3076 | return -EINVAL; | |
3077 | ||
3078 | while (size) { | |
3079 | uint32_t value; | |
3080 | ||
6fc0deaf | 3081 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3082 | r = put_user(value, (uint32_t *)buf); |
3083 | if (r) | |
3084 | return r; | |
3085 | ||
3086 | result += 4; | |
3087 | buf += 4; | |
3088 | *pos += 4; | |
3089 | size -= 4; | |
3090 | } | |
3091 | ||
3092 | return result; | |
3093 | } | |
3094 | ||
3095 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3096 | size_t size, loff_t *pos) | |
3097 | { | |
45063097 | 3098 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3099 | ssize_t result = 0; |
3100 | int r; | |
3101 | ||
3102 | if (size & 0x3 || *pos & 0x3) | |
3103 | return -EINVAL; | |
3104 | ||
3105 | while (size) { | |
3106 | uint32_t value; | |
3107 | ||
3108 | r = get_user(value, (uint32_t *)buf); | |
3109 | if (r) | |
3110 | return r; | |
3111 | ||
6fc0deaf | 3112 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3113 | |
3114 | result += 4; | |
3115 | buf += 4; | |
3116 | *pos += 4; | |
3117 | size -= 4; | |
3118 | } | |
3119 | ||
3120 | return result; | |
3121 | } | |
3122 | ||
1e051413 TSD |
3123 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3124 | size_t size, loff_t *pos) | |
3125 | { | |
45063097 | 3126 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3127 | ssize_t result = 0; |
3128 | int r; | |
3129 | uint32_t *config, no_regs = 0; | |
3130 | ||
3131 | if (size & 0x3 || *pos & 0x3) | |
3132 | return -EINVAL; | |
3133 | ||
ecab7668 | 3134 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3135 | if (!config) |
3136 | return -ENOMEM; | |
3137 | ||
3138 | /* version, increment each time something is added */ | |
9a999359 | 3139 | config[no_regs++] = 3; |
1e051413 TSD |
3140 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3141 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3142 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3143 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3144 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3145 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3146 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3147 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3148 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3149 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3150 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3151 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3152 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3153 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3154 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3155 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3156 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3157 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3158 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3159 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3160 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3161 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3162 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3163 | ||
89a8f309 TSD |
3164 | /* rev==1 */ |
3165 | config[no_regs++] = adev->rev_id; | |
3166 | config[no_regs++] = adev->pg_flags; | |
3167 | config[no_regs++] = adev->cg_flags; | |
3168 | ||
e9f11dc8 TSD |
3169 | /* rev==2 */ |
3170 | config[no_regs++] = adev->family; | |
3171 | config[no_regs++] = adev->external_rev_id; | |
3172 | ||
9a999359 TSD |
3173 | /* rev==3 */ |
3174 | config[no_regs++] = adev->pdev->device; | |
3175 | config[no_regs++] = adev->pdev->revision; | |
3176 | config[no_regs++] = adev->pdev->subsystem_device; | |
3177 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3178 | ||
1e051413 TSD |
3179 | while (size && (*pos < no_regs * 4)) { |
3180 | uint32_t value; | |
3181 | ||
3182 | value = config[*pos >> 2]; | |
3183 | r = put_user(value, (uint32_t *)buf); | |
3184 | if (r) { | |
3185 | kfree(config); | |
3186 | return r; | |
3187 | } | |
3188 | ||
3189 | result += 4; | |
3190 | buf += 4; | |
3191 | *pos += 4; | |
3192 | size -= 4; | |
3193 | } | |
3194 | ||
3195 | kfree(config); | |
3196 | return result; | |
3197 | } | |
3198 | ||
f2cdaf20 TSD |
3199 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3200 | size_t size, loff_t *pos) | |
3201 | { | |
45063097 | 3202 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3203 | int idx, x, outsize, r, valuesize; |
3204 | uint32_t values[16]; | |
f2cdaf20 | 3205 | |
9f8df7d7 | 3206 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3207 | return -EINVAL; |
3208 | ||
3cbc614f SP |
3209 | if (amdgpu_dpm == 0) |
3210 | return -EINVAL; | |
3211 | ||
f2cdaf20 TSD |
3212 | /* convert offset to sensor number */ |
3213 | idx = *pos >> 2; | |
3214 | ||
9f8df7d7 | 3215 | valuesize = sizeof(values); |
f2cdaf20 | 3216 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3217 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3218 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3219 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3220 | &valuesize); | |
f2cdaf20 TSD |
3221 | else |
3222 | return -EINVAL; | |
3223 | ||
9f8df7d7 TSD |
3224 | if (size > valuesize) |
3225 | return -EINVAL; | |
3226 | ||
3227 | outsize = 0; | |
3228 | x = 0; | |
3229 | if (!r) { | |
3230 | while (size) { | |
3231 | r = put_user(values[x++], (int32_t *)buf); | |
3232 | buf += 4; | |
3233 | size -= 4; | |
3234 | outsize += 4; | |
3235 | } | |
3236 | } | |
f2cdaf20 | 3237 | |
9f8df7d7 | 3238 | return !r ? outsize : r; |
f2cdaf20 | 3239 | } |
1e051413 | 3240 | |
273d7aa1 TSD |
3241 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3242 | size_t size, loff_t *pos) | |
3243 | { | |
3244 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3245 | int r, x; | |
3246 | ssize_t result=0; | |
472259f0 | 3247 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3248 | |
3249 | if (size & 3 || *pos & 3) | |
3250 | return -EINVAL; | |
3251 | ||
3252 | /* decode offset */ | |
3253 | offset = (*pos & 0x7F); | |
3254 | se = ((*pos >> 7) & 0xFF); | |
3255 | sh = ((*pos >> 15) & 0xFF); | |
3256 | cu = ((*pos >> 23) & 0xFF); | |
3257 | wave = ((*pos >> 31) & 0xFF); | |
3258 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3259 | |
3260 | /* switch to the specific se/sh/cu */ | |
3261 | mutex_lock(&adev->grbm_idx_mutex); | |
3262 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3263 | ||
3264 | x = 0; | |
472259f0 TSD |
3265 | if (adev->gfx.funcs->read_wave_data) |
3266 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3267 | |
3268 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3269 | mutex_unlock(&adev->grbm_idx_mutex); | |
3270 | ||
5ecfb3b8 TSD |
3271 | if (!x) |
3272 | return -EINVAL; | |
3273 | ||
472259f0 | 3274 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3275 | uint32_t value; |
3276 | ||
472259f0 | 3277 | value = data[offset >> 2]; |
273d7aa1 TSD |
3278 | r = put_user(value, (uint32_t *)buf); |
3279 | if (r) | |
3280 | return r; | |
3281 | ||
3282 | result += 4; | |
3283 | buf += 4; | |
472259f0 | 3284 | offset += 4; |
273d7aa1 TSD |
3285 | size -= 4; |
3286 | } | |
3287 | ||
3288 | return result; | |
3289 | } | |
3290 | ||
c5a60ce8 TSD |
3291 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3292 | size_t size, loff_t *pos) | |
3293 | { | |
3294 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3295 | int r; | |
3296 | ssize_t result = 0; | |
3297 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3298 | ||
3299 | if (size & 3 || *pos & 3) | |
3300 | return -EINVAL; | |
3301 | ||
3302 | /* decode offset */ | |
3303 | offset = (*pos & 0xFFF); /* in dwords */ | |
3304 | se = ((*pos >> 12) & 0xFF); | |
3305 | sh = ((*pos >> 20) & 0xFF); | |
3306 | cu = ((*pos >> 28) & 0xFF); | |
3307 | wave = ((*pos >> 36) & 0xFF); | |
3308 | simd = ((*pos >> 44) & 0xFF); | |
3309 | thread = ((*pos >> 52) & 0xFF); | |
3310 | bank = ((*pos >> 60) & 1); | |
3311 | ||
3312 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3313 | if (!data) | |
3314 | return -ENOMEM; | |
3315 | ||
3316 | /* switch to the specific se/sh/cu */ | |
3317 | mutex_lock(&adev->grbm_idx_mutex); | |
3318 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3319 | ||
3320 | if (bank == 0) { | |
3321 | if (adev->gfx.funcs->read_wave_vgprs) | |
3322 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3323 | } else { | |
3324 | if (adev->gfx.funcs->read_wave_sgprs) | |
3325 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3326 | } | |
3327 | ||
3328 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3329 | mutex_unlock(&adev->grbm_idx_mutex); | |
3330 | ||
3331 | while (size) { | |
3332 | uint32_t value; | |
3333 | ||
3334 | value = data[offset++]; | |
3335 | r = put_user(value, (uint32_t *)buf); | |
3336 | if (r) { | |
3337 | result = r; | |
3338 | goto err; | |
3339 | } | |
3340 | ||
3341 | result += 4; | |
3342 | buf += 4; | |
3343 | size -= 4; | |
3344 | } | |
3345 | ||
3346 | err: | |
3347 | kfree(data); | |
3348 | return result; | |
3349 | } | |
3350 | ||
d38ceaf9 AD |
3351 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3352 | .owner = THIS_MODULE, | |
3353 | .read = amdgpu_debugfs_regs_read, | |
3354 | .write = amdgpu_debugfs_regs_write, | |
3355 | .llseek = default_llseek | |
3356 | }; | |
adcec288 TSD |
3357 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3358 | .owner = THIS_MODULE, | |
3359 | .read = amdgpu_debugfs_regs_didt_read, | |
3360 | .write = amdgpu_debugfs_regs_didt_write, | |
3361 | .llseek = default_llseek | |
3362 | }; | |
3363 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3364 | .owner = THIS_MODULE, | |
3365 | .read = amdgpu_debugfs_regs_pcie_read, | |
3366 | .write = amdgpu_debugfs_regs_pcie_write, | |
3367 | .llseek = default_llseek | |
3368 | }; | |
3369 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3370 | .owner = THIS_MODULE, | |
3371 | .read = amdgpu_debugfs_regs_smc_read, | |
3372 | .write = amdgpu_debugfs_regs_smc_write, | |
3373 | .llseek = default_llseek | |
3374 | }; | |
3375 | ||
1e051413 TSD |
3376 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3377 | .owner = THIS_MODULE, | |
3378 | .read = amdgpu_debugfs_gca_config_read, | |
3379 | .llseek = default_llseek | |
3380 | }; | |
3381 | ||
f2cdaf20 TSD |
3382 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3383 | .owner = THIS_MODULE, | |
3384 | .read = amdgpu_debugfs_sensor_read, | |
3385 | .llseek = default_llseek | |
3386 | }; | |
3387 | ||
273d7aa1 TSD |
3388 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3389 | .owner = THIS_MODULE, | |
3390 | .read = amdgpu_debugfs_wave_read, | |
3391 | .llseek = default_llseek | |
3392 | }; | |
c5a60ce8 TSD |
3393 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3394 | .owner = THIS_MODULE, | |
3395 | .read = amdgpu_debugfs_gpr_read, | |
3396 | .llseek = default_llseek | |
3397 | }; | |
273d7aa1 | 3398 | |
adcec288 TSD |
3399 | static const struct file_operations *debugfs_regs[] = { |
3400 | &amdgpu_debugfs_regs_fops, | |
3401 | &amdgpu_debugfs_regs_didt_fops, | |
3402 | &amdgpu_debugfs_regs_pcie_fops, | |
3403 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3404 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3405 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3406 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3407 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3408 | }; |
3409 | ||
3410 | static const char *debugfs_regs_names[] = { | |
3411 | "amdgpu_regs", | |
3412 | "amdgpu_regs_didt", | |
3413 | "amdgpu_regs_pcie", | |
3414 | "amdgpu_regs_smc", | |
1e051413 | 3415 | "amdgpu_gca_config", |
f2cdaf20 | 3416 | "amdgpu_sensors", |
273d7aa1 | 3417 | "amdgpu_wave", |
c5a60ce8 | 3418 | "amdgpu_gpr", |
adcec288 | 3419 | }; |
d38ceaf9 AD |
3420 | |
3421 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3422 | { | |
3423 | struct drm_minor *minor = adev->ddev->primary; | |
3424 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3425 | unsigned i, j; |
3426 | ||
3427 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3428 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3429 | S_IFREG | S_IRUGO, root, | |
3430 | adev, debugfs_regs[i]); | |
3431 | if (IS_ERR(ent)) { | |
3432 | for (j = 0; j < i; j++) { | |
3433 | debugfs_remove(adev->debugfs_regs[i]); | |
3434 | adev->debugfs_regs[i] = NULL; | |
3435 | } | |
3436 | return PTR_ERR(ent); | |
3437 | } | |
d38ceaf9 | 3438 | |
adcec288 TSD |
3439 | if (!i) |
3440 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3441 | adev->debugfs_regs[i] = ent; | |
3442 | } | |
d38ceaf9 AD |
3443 | |
3444 | return 0; | |
3445 | } | |
3446 | ||
3447 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3448 | { | |
adcec288 TSD |
3449 | unsigned i; |
3450 | ||
3451 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3452 | if (adev->debugfs_regs[i]) { | |
3453 | debugfs_remove(adev->debugfs_regs[i]); | |
3454 | adev->debugfs_regs[i] = NULL; | |
3455 | } | |
3456 | } | |
d38ceaf9 AD |
3457 | } |
3458 | ||
3459 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
3460 | { | |
3461 | return 0; | |
3462 | } | |
7cebc728 AK |
3463 | #else |
3464 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3465 | { | |
3466 | return 0; | |
3467 | } | |
3468 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3469 | #endif |