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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
d38ceaf9 AD |
35 | #include <drm/amdgpu_drm.h> |
36 | #include <linux/vgaarb.h> | |
37 | #include <linux/vga_switcheroo.h> | |
38 | #include <linux/efi.h> | |
39 | #include "amdgpu.h" | |
f4b373f4 | 40 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
41 | #include "amdgpu_i2c.h" |
42 | #include "atom.h" | |
43 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 44 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 45 | #include "amd_pcie.h" |
33f34802 KW |
46 | #ifdef CONFIG_DRM_AMDGPU_SI |
47 | #include "si.h" | |
48 | #endif | |
a2e73f56 AD |
49 | #ifdef CONFIG_DRM_AMDGPU_CIK |
50 | #include "cik.h" | |
51 | #endif | |
aaa36a97 | 52 | #include "vi.h" |
460826e6 | 53 | #include "soc15.h" |
d38ceaf9 | 54 | #include "bif/bif_4_1_d.h" |
9accf2fd | 55 | #include <linux/pci.h> |
bec86378 | 56 | #include <linux/firmware.h> |
89041940 | 57 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 58 | |
ba997709 | 59 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 60 | #include "amdgpu_pm.h" |
d38ceaf9 | 61 | |
e2a75f88 | 62 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 63 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 64 | |
2dc80b00 S |
65 | #define AMDGPU_RESUME_MS 2000 |
66 | ||
d38ceaf9 AD |
67 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
68 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
4f0955fc | 69 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); |
db95e218 | 70 | static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev); |
d38ceaf9 AD |
71 | |
72 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
73 | "TAHITI", |
74 | "PITCAIRN", | |
75 | "VERDE", | |
76 | "OLAND", | |
77 | "HAINAN", | |
d38ceaf9 AD |
78 | "BONAIRE", |
79 | "KAVERI", | |
80 | "KABINI", | |
81 | "HAWAII", | |
82 | "MULLINS", | |
83 | "TOPAZ", | |
84 | "TONGA", | |
48299f95 | 85 | "FIJI", |
d38ceaf9 | 86 | "CARRIZO", |
139f4917 | 87 | "STONEY", |
2cc0c0b5 FC |
88 | "POLARIS10", |
89 | "POLARIS11", | |
c4642a47 | 90 | "POLARIS12", |
d4196f01 | 91 | "VEGA10", |
2ca8a5d2 | 92 | "RAVEN", |
d38ceaf9 AD |
93 | "LAST", |
94 | }; | |
95 | ||
96 | bool amdgpu_device_is_px(struct drm_device *dev) | |
97 | { | |
98 | struct amdgpu_device *adev = dev->dev_private; | |
99 | ||
2f7d10b3 | 100 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
101 | return true; |
102 | return false; | |
103 | } | |
104 | ||
105 | /* | |
106 | * MMIO register access helper functions. | |
107 | */ | |
108 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 109 | uint32_t acc_flags) |
d38ceaf9 | 110 | { |
f4b373f4 TSD |
111 | uint32_t ret; |
112 | ||
43ca8efa | 113 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 114 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 115 | |
15d72fd7 | 116 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 117 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
118 | else { |
119 | unsigned long flags; | |
d38ceaf9 AD |
120 | |
121 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
122 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
123 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
124 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 125 | } |
f4b373f4 TSD |
126 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
127 | return ret; | |
d38ceaf9 AD |
128 | } |
129 | ||
130 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 131 | uint32_t acc_flags) |
d38ceaf9 | 132 | { |
f4b373f4 | 133 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 134 | |
47ed4e1c KW |
135 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
136 | adev->last_mm_index = v; | |
137 | } | |
138 | ||
43ca8efa | 139 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 140 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 141 | |
15d72fd7 | 142 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
143 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
144 | else { | |
145 | unsigned long flags; | |
146 | ||
147 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
148 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
149 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
150 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
151 | } | |
47ed4e1c KW |
152 | |
153 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
154 | udelay(500); | |
155 | } | |
d38ceaf9 AD |
156 | } |
157 | ||
158 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
159 | { | |
160 | if ((reg * 4) < adev->rio_mem_size) | |
161 | return ioread32(adev->rio_mem + (reg * 4)); | |
162 | else { | |
163 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
164 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
165 | } | |
166 | } | |
167 | ||
168 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
169 | { | |
47ed4e1c KW |
170 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
171 | adev->last_mm_index = v; | |
172 | } | |
d38ceaf9 AD |
173 | |
174 | if ((reg * 4) < adev->rio_mem_size) | |
175 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
176 | else { | |
177 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
178 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
179 | } | |
47ed4e1c KW |
180 | |
181 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
182 | udelay(500); | |
183 | } | |
d38ceaf9 AD |
184 | } |
185 | ||
186 | /** | |
187 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
188 | * | |
189 | * @adev: amdgpu_device pointer | |
190 | * @index: doorbell index | |
191 | * | |
192 | * Returns the value in the doorbell aperture at the | |
193 | * requested doorbell index (CIK). | |
194 | */ | |
195 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
196 | { | |
197 | if (index < adev->doorbell.num_doorbells) { | |
198 | return readl(adev->doorbell.ptr + index); | |
199 | } else { | |
200 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
201 | return 0; | |
202 | } | |
203 | } | |
204 | ||
205 | /** | |
206 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
207 | * | |
208 | * @adev: amdgpu_device pointer | |
209 | * @index: doorbell index | |
210 | * @v: value to write | |
211 | * | |
212 | * Writes @v to the doorbell aperture at the | |
213 | * requested doorbell index (CIK). | |
214 | */ | |
215 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
216 | { | |
217 | if (index < adev->doorbell.num_doorbells) { | |
218 | writel(v, adev->doorbell.ptr + index); | |
219 | } else { | |
220 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
221 | } | |
222 | } | |
223 | ||
832be404 KW |
224 | /** |
225 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
226 | * | |
227 | * @adev: amdgpu_device pointer | |
228 | * @index: doorbell index | |
229 | * | |
230 | * Returns the value in the doorbell aperture at the | |
231 | * requested doorbell index (VEGA10+). | |
232 | */ | |
233 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
234 | { | |
235 | if (index < adev->doorbell.num_doorbells) { | |
236 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
237 | } else { | |
238 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
239 | return 0; | |
240 | } | |
241 | } | |
242 | ||
243 | /** | |
244 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
245 | * | |
246 | * @adev: amdgpu_device pointer | |
247 | * @index: doorbell index | |
248 | * @v: value to write | |
249 | * | |
250 | * Writes @v to the doorbell aperture at the | |
251 | * requested doorbell index (VEGA10+). | |
252 | */ | |
253 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
254 | { | |
255 | if (index < adev->doorbell.num_doorbells) { | |
256 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
257 | } else { | |
258 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
259 | } | |
260 | } | |
261 | ||
d38ceaf9 AD |
262 | /** |
263 | * amdgpu_invalid_rreg - dummy reg read function | |
264 | * | |
265 | * @adev: amdgpu device pointer | |
266 | * @reg: offset of register | |
267 | * | |
268 | * Dummy register read function. Used for register blocks | |
269 | * that certain asics don't have (all asics). | |
270 | * Returns the value in the register. | |
271 | */ | |
272 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
273 | { | |
274 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
275 | BUG(); | |
276 | return 0; | |
277 | } | |
278 | ||
279 | /** | |
280 | * amdgpu_invalid_wreg - dummy reg write function | |
281 | * | |
282 | * @adev: amdgpu device pointer | |
283 | * @reg: offset of register | |
284 | * @v: value to write to the register | |
285 | * | |
286 | * Dummy register read function. Used for register blocks | |
287 | * that certain asics don't have (all asics). | |
288 | */ | |
289 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
290 | { | |
291 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
292 | reg, v); | |
293 | BUG(); | |
294 | } | |
295 | ||
296 | /** | |
297 | * amdgpu_block_invalid_rreg - dummy reg read function | |
298 | * | |
299 | * @adev: amdgpu device pointer | |
300 | * @block: offset of instance | |
301 | * @reg: offset of register | |
302 | * | |
303 | * Dummy register read function. Used for register blocks | |
304 | * that certain asics don't have (all asics). | |
305 | * Returns the value in the register. | |
306 | */ | |
307 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
308 | uint32_t block, uint32_t reg) | |
309 | { | |
310 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
311 | reg, block); | |
312 | BUG(); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | /** | |
317 | * amdgpu_block_invalid_wreg - dummy reg write function | |
318 | * | |
319 | * @adev: amdgpu device pointer | |
320 | * @block: offset of instance | |
321 | * @reg: offset of register | |
322 | * @v: value to write to the register | |
323 | * | |
324 | * Dummy register read function. Used for register blocks | |
325 | * that certain asics don't have (all asics). | |
326 | */ | |
327 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
328 | uint32_t block, | |
329 | uint32_t reg, uint32_t v) | |
330 | { | |
331 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
332 | reg, block, v); | |
333 | BUG(); | |
334 | } | |
335 | ||
336 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
337 | { | |
a4a02777 CK |
338 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
339 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
340 | &adev->vram_scratch.robj, | |
341 | &adev->vram_scratch.gpu_addr, | |
342 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
343 | } |
344 | ||
345 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
346 | { | |
078af1a3 | 347 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
348 | } |
349 | ||
350 | /** | |
351 | * amdgpu_program_register_sequence - program an array of registers. | |
352 | * | |
353 | * @adev: amdgpu_device pointer | |
354 | * @registers: pointer to the register array | |
355 | * @array_size: size of the register array | |
356 | * | |
357 | * Programs an array or registers with and and or masks. | |
358 | * This is a helper for setting golden registers. | |
359 | */ | |
360 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
361 | const u32 *registers, | |
362 | const u32 array_size) | |
363 | { | |
364 | u32 tmp, reg, and_mask, or_mask; | |
365 | int i; | |
366 | ||
367 | if (array_size % 3) | |
368 | return; | |
369 | ||
370 | for (i = 0; i < array_size; i +=3) { | |
371 | reg = registers[i + 0]; | |
372 | and_mask = registers[i + 1]; | |
373 | or_mask = registers[i + 2]; | |
374 | ||
375 | if (and_mask == 0xffffffff) { | |
376 | tmp = or_mask; | |
377 | } else { | |
378 | tmp = RREG32(reg); | |
379 | tmp &= ~and_mask; | |
380 | tmp |= or_mask; | |
381 | } | |
382 | WREG32(reg, tmp); | |
383 | } | |
384 | } | |
385 | ||
386 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
387 | { | |
388 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
389 | } | |
390 | ||
391 | /* | |
392 | * GPU doorbell aperture helpers function. | |
393 | */ | |
394 | /** | |
395 | * amdgpu_doorbell_init - Init doorbell driver information. | |
396 | * | |
397 | * @adev: amdgpu_device pointer | |
398 | * | |
399 | * Init doorbell driver information (CIK) | |
400 | * Returns 0 on success, error on failure. | |
401 | */ | |
402 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
403 | { | |
705e519e CK |
404 | /* No doorbell on SI hardware generation */ |
405 | if (adev->asic_type < CHIP_BONAIRE) { | |
406 | adev->doorbell.base = 0; | |
407 | adev->doorbell.size = 0; | |
408 | adev->doorbell.num_doorbells = 0; | |
409 | adev->doorbell.ptr = NULL; | |
410 | return 0; | |
411 | } | |
412 | ||
d6895ad3 CK |
413 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
414 | return -EINVAL; | |
415 | ||
d38ceaf9 AD |
416 | /* doorbell bar mapping */ |
417 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
418 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
419 | ||
edf600da | 420 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
421 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
422 | if (adev->doorbell.num_doorbells == 0) | |
423 | return -EINVAL; | |
424 | ||
8972e5d2 CK |
425 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
426 | adev->doorbell.num_doorbells * | |
427 | sizeof(u32)); | |
428 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 429 | return -ENOMEM; |
d38ceaf9 AD |
430 | |
431 | return 0; | |
432 | } | |
433 | ||
434 | /** | |
435 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
436 | * | |
437 | * @adev: amdgpu_device pointer | |
438 | * | |
439 | * Tear down doorbell driver information (CIK) | |
440 | */ | |
441 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
442 | { | |
443 | iounmap(adev->doorbell.ptr); | |
444 | adev->doorbell.ptr = NULL; | |
445 | } | |
446 | ||
447 | /** | |
448 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
449 | * setup amdkfd | |
450 | * | |
451 | * @adev: amdgpu_device pointer | |
452 | * @aperture_base: output returning doorbell aperture base physical address | |
453 | * @aperture_size: output returning doorbell aperture size in bytes | |
454 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
455 | * | |
456 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
457 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
458 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
459 | */ | |
460 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
461 | phys_addr_t *aperture_base, | |
462 | size_t *aperture_size, | |
463 | size_t *start_offset) | |
464 | { | |
465 | /* | |
466 | * The first num_doorbells are used by amdgpu. | |
467 | * amdkfd takes whatever's left in the aperture. | |
468 | */ | |
469 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
470 | *aperture_base = adev->doorbell.base; | |
471 | *aperture_size = adev->doorbell.size; | |
472 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
473 | } else { | |
474 | *aperture_base = 0; | |
475 | *aperture_size = 0; | |
476 | *start_offset = 0; | |
477 | } | |
478 | } | |
479 | ||
480 | /* | |
481 | * amdgpu_wb_*() | |
455a7bc2 | 482 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 483 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
484 | */ |
485 | ||
486 | /** | |
487 | * amdgpu_wb_fini - Disable Writeback and free memory | |
488 | * | |
489 | * @adev: amdgpu_device pointer | |
490 | * | |
491 | * Disables Writeback and frees the Writeback memory (all asics). | |
492 | * Used at driver shutdown. | |
493 | */ | |
494 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
495 | { | |
496 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
497 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
498 | &adev->wb.gpu_addr, | |
499 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
500 | adev->wb.wb_obj = NULL; |
501 | } | |
502 | } | |
503 | ||
504 | /** | |
505 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
506 | * | |
507 | * @adev: amdgpu_device pointer | |
508 | * | |
455a7bc2 | 509 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
510 | * Used at driver startup. |
511 | * Returns 0 on success or an -error on failure. | |
512 | */ | |
513 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
514 | { | |
515 | int r; | |
516 | ||
517 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
518 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
519 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
520 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
521 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
522 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
523 | if (r) { |
524 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
525 | return r; | |
526 | } | |
d38ceaf9 AD |
527 | |
528 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
529 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
530 | ||
531 | /* clear wb memory */ | |
60a970a6 | 532 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
533 | } |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | /** | |
539 | * amdgpu_wb_get - Allocate a wb entry | |
540 | * | |
541 | * @adev: amdgpu_device pointer | |
542 | * @wb: wb index | |
543 | * | |
544 | * Allocate a wb slot for use by the driver (all asics). | |
545 | * Returns 0 on success or -EINVAL on failure. | |
546 | */ | |
547 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
548 | { | |
549 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 550 | |
97407b63 | 551 | if (offset < adev->wb.num_wb) { |
7014285a | 552 | __set_bit(offset, adev->wb.used); |
63ae07ca | 553 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
554 | return 0; |
555 | } else { | |
556 | return -EINVAL; | |
557 | } | |
558 | } | |
559 | ||
d38ceaf9 AD |
560 | /** |
561 | * amdgpu_wb_free - Free a wb entry | |
562 | * | |
563 | * @adev: amdgpu_device pointer | |
564 | * @wb: wb index | |
565 | * | |
566 | * Free a wb slot allocated for use by the driver (all asics) | |
567 | */ | |
568 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
569 | { | |
570 | if (wb < adev->wb.num_wb) | |
63ae07ca | 571 | __clear_bit(wb >> 3, adev->wb.used); |
d38ceaf9 AD |
572 | } |
573 | ||
574 | /** | |
575 | * amdgpu_vram_location - try to find VRAM location | |
576 | * @adev: amdgpu device structure holding all necessary informations | |
577 | * @mc: memory controller structure holding memory informations | |
578 | * @base: base address at which to put VRAM | |
579 | * | |
455a7bc2 | 580 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
581 | * as parameter (which is so far either PCI aperture address or |
582 | * for IGP TOM base address). | |
583 | * | |
584 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
585 | * address space then we limit the VRAM size to the aperture. | |
586 | * | |
587 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
588 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
589 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
590 | * not IGP. | |
591 | * | |
592 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
593 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
594 | * Novell bug 204882 + along with lots of ubuntu ones | |
595 | * | |
596 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
597 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
598 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
599 | * ones) | |
600 | * | |
601 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 602 | * explicitly check for that though. |
d38ceaf9 AD |
603 | * |
604 | * FIXME: when reducing VRAM size align new size on power of 2. | |
605 | */ | |
606 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
607 | { | |
608 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
609 | ||
610 | mc->vram_start = base; | |
611 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
612 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
613 | mc->real_vram_size = mc->aper_size; | |
614 | mc->mc_vram_size = mc->aper_size; | |
615 | } | |
616 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
617 | if (limit && limit < mc->real_vram_size) | |
618 | mc->real_vram_size = limit; | |
619 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
620 | mc->mc_vram_size >> 20, mc->vram_start, | |
621 | mc->vram_end, mc->real_vram_size >> 20); | |
622 | } | |
623 | ||
624 | /** | |
6f02a696 | 625 | * amdgpu_gart_location - try to find GTT location |
d38ceaf9 AD |
626 | * @adev: amdgpu device structure holding all necessary informations |
627 | * @mc: memory controller structure holding memory informations | |
628 | * | |
629 | * Function will place try to place GTT before or after VRAM. | |
630 | * | |
631 | * If GTT size is bigger than space left then we ajust GTT size. | |
632 | * Thus function will never fails. | |
633 | * | |
634 | * FIXME: when reducing GTT size align new size on power of 2. | |
635 | */ | |
6f02a696 | 636 | void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) |
d38ceaf9 AD |
637 | { |
638 | u64 size_af, size_bf; | |
639 | ||
ed21c047 CK |
640 | size_af = adev->mc.mc_mask - mc->vram_end; |
641 | size_bf = mc->vram_start; | |
d38ceaf9 | 642 | if (size_bf > size_af) { |
6f02a696 | 643 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 644 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 645 | mc->gart_size = size_bf; |
d38ceaf9 | 646 | } |
6f02a696 | 647 | mc->gart_start = 0; |
d38ceaf9 | 648 | } else { |
6f02a696 | 649 | if (mc->gart_size > size_af) { |
d38ceaf9 | 650 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 651 | mc->gart_size = size_af; |
d38ceaf9 | 652 | } |
6f02a696 | 653 | mc->gart_start = mc->vram_end + 1; |
d38ceaf9 | 654 | } |
6f02a696 | 655 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 656 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 657 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
658 | } |
659 | ||
a05502e5 HC |
660 | /* |
661 | * Firmware Reservation functions | |
662 | */ | |
663 | /** | |
664 | * amdgpu_fw_reserve_vram_fini - free fw reserved vram | |
665 | * | |
666 | * @adev: amdgpu_device pointer | |
667 | * | |
668 | * free fw reserved vram if it has been reserved. | |
669 | */ | |
670 | void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev) | |
671 | { | |
672 | amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, | |
673 | NULL, &adev->fw_vram_usage.va); | |
674 | } | |
675 | ||
676 | /** | |
677 | * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw | |
678 | * | |
679 | * @adev: amdgpu_device pointer | |
680 | * | |
681 | * create bo vram reservation from fw. | |
682 | */ | |
683 | int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) | |
684 | { | |
685 | int r = 0; | |
3c738893 | 686 | int i; |
a05502e5 HC |
687 | u64 gpu_addr; |
688 | u64 vram_size = adev->mc.visible_vram_size; | |
3c738893 HC |
689 | u64 offset = adev->fw_vram_usage.start_offset; |
690 | u64 size = adev->fw_vram_usage.size; | |
691 | struct amdgpu_bo *bo; | |
a05502e5 HC |
692 | |
693 | adev->fw_vram_usage.va = NULL; | |
694 | adev->fw_vram_usage.reserved_bo = NULL; | |
695 | ||
696 | if (adev->fw_vram_usage.size > 0 && | |
697 | adev->fw_vram_usage.size <= vram_size) { | |
698 | ||
699 | r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, | |
3c738893 | 700 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
a05502e5 HC |
701 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
702 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0, | |
703 | &adev->fw_vram_usage.reserved_bo); | |
704 | if (r) | |
705 | goto error_create; | |
706 | ||
707 | r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false); | |
708 | if (r) | |
709 | goto error_reserve; | |
3c738893 HC |
710 | |
711 | /* remove the original mem node and create a new one at the | |
712 | * request position | |
713 | */ | |
714 | bo = adev->fw_vram_usage.reserved_bo; | |
715 | offset = ALIGN(offset, PAGE_SIZE); | |
716 | for (i = 0; i < bo->placement.num_placement; ++i) { | |
717 | bo->placements[i].fpfn = offset >> PAGE_SHIFT; | |
718 | bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; | |
719 | } | |
720 | ||
721 | ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); | |
722 | r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, | |
723 | false, false); | |
724 | if (r) | |
725 | goto error_pin; | |
726 | ||
a05502e5 HC |
727 | r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo, |
728 | AMDGPU_GEM_DOMAIN_VRAM, | |
729 | adev->fw_vram_usage.start_offset, | |
730 | (adev->fw_vram_usage.start_offset + | |
731 | adev->fw_vram_usage.size), &gpu_addr); | |
732 | if (r) | |
733 | goto error_pin; | |
734 | r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, | |
735 | &adev->fw_vram_usage.va); | |
736 | if (r) | |
737 | goto error_kmap; | |
738 | ||
739 | amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); | |
740 | } | |
741 | return r; | |
742 | ||
743 | error_kmap: | |
744 | amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo); | |
745 | error_pin: | |
746 | amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); | |
747 | error_reserve: | |
748 | amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo); | |
749 | error_create: | |
750 | adev->fw_vram_usage.va = NULL; | |
751 | adev->fw_vram_usage.reserved_bo = NULL; | |
752 | return r; | |
753 | } | |
754 | ||
d6895ad3 CK |
755 | /** |
756 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
757 | * | |
758 | * @adev: amdgpu_device pointer | |
759 | * | |
760 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
761 | * to fail, but if any of the BARs is not accessible after the size we abort | |
762 | * driver loading by returning -ENODEV. | |
763 | */ | |
764 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
765 | { | |
766 | u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size); | |
767 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; | |
768 | u16 cmd; | |
769 | int r; | |
770 | ||
0c03b912 | 771 | /* Bypass for VF */ |
772 | if (amdgpu_sriov_vf(adev)) | |
773 | return 0; | |
774 | ||
d6895ad3 CK |
775 | /* Disable memory decoding while we change the BAR addresses and size */ |
776 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
777 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
778 | cmd & ~PCI_COMMAND_MEMORY); | |
779 | ||
780 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
781 | amdgpu_doorbell_fini(adev); | |
782 | if (adev->asic_type >= CHIP_BONAIRE) | |
783 | pci_release_resource(adev->pdev, 2); | |
784 | ||
785 | pci_release_resource(adev->pdev, 0); | |
786 | ||
787 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
788 | if (r == -ENOSPC) | |
789 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
790 | else if (r && r != -ENOTSUPP) | |
791 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
792 | ||
793 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
794 | ||
795 | /* When the doorbell or fb BAR isn't available we have no chance of | |
796 | * using the device. | |
797 | */ | |
798 | r = amdgpu_doorbell_init(adev); | |
799 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) | |
800 | return -ENODEV; | |
801 | ||
802 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
803 | ||
804 | return 0; | |
805 | } | |
a05502e5 | 806 | |
d38ceaf9 AD |
807 | /* |
808 | * GPU helpers function. | |
809 | */ | |
810 | /** | |
c836fec5 | 811 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
812 | * |
813 | * @adev: amdgpu_device pointer | |
814 | * | |
c836fec5 JQ |
815 | * Check if the asic has been initialized (all asics) at driver startup |
816 | * or post is needed if hw reset is performed. | |
817 | * Returns true if need or false if not. | |
d38ceaf9 | 818 | */ |
c836fec5 | 819 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
820 | { |
821 | uint32_t reg; | |
822 | ||
bec86378 ML |
823 | if (amdgpu_sriov_vf(adev)) |
824 | return false; | |
825 | ||
826 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
827 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
828 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
829 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
830 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
831 | */ |
832 | if (adev->asic_type == CHIP_FIJI) { | |
833 | int err; | |
834 | uint32_t fw_ver; | |
835 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
836 | /* force vPost if error occured */ | |
837 | if (err) | |
838 | return true; | |
839 | ||
840 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
841 | if (fw_ver < 0x00160e00) |
842 | return true; | |
bec86378 | 843 | } |
bec86378 | 844 | } |
91fe77eb | 845 | |
846 | if (adev->has_hw_reset) { | |
847 | adev->has_hw_reset = false; | |
848 | return true; | |
849 | } | |
850 | ||
851 | /* bios scratch used on CIK+ */ | |
852 | if (adev->asic_type >= CHIP_BONAIRE) | |
853 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
854 | ||
855 | /* check MEM_SIZE for older asics */ | |
856 | reg = amdgpu_asic_get_config_memsize(adev); | |
857 | ||
858 | if ((reg != 0) && (reg != 0xffffffff)) | |
859 | return false; | |
860 | ||
861 | return true; | |
bec86378 ML |
862 | } |
863 | ||
d38ceaf9 AD |
864 | /** |
865 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
866 | * | |
867 | * @adev: amdgpu_device pointer | |
868 | * | |
869 | * Allocate the dummy page used by the driver (all asics). | |
870 | * This dummy page is used by the driver as a filler for gart entries | |
871 | * when pages are taken out of the GART | |
872 | * Returns 0 on sucess, -ENOMEM on failure. | |
873 | */ | |
874 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
875 | { | |
876 | if (adev->dummy_page.page) | |
877 | return 0; | |
878 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
879 | if (adev->dummy_page.page == NULL) | |
880 | return -ENOMEM; | |
881 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
882 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
883 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
884 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
885 | __free_page(adev->dummy_page.page); | |
886 | adev->dummy_page.page = NULL; | |
887 | return -ENOMEM; | |
888 | } | |
889 | return 0; | |
890 | } | |
891 | ||
892 | /** | |
893 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
894 | * | |
895 | * @adev: amdgpu_device pointer | |
896 | * | |
897 | * Frees the dummy page used by the driver (all asics). | |
898 | */ | |
899 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
900 | { | |
901 | if (adev->dummy_page.page == NULL) | |
902 | return; | |
903 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
904 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
905 | __free_page(adev->dummy_page.page); | |
906 | adev->dummy_page.page = NULL; | |
907 | } | |
908 | ||
909 | ||
910 | /* ATOM accessor methods */ | |
911 | /* | |
912 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
913 | * driver registers callbacks to access registers and the interpreter | |
914 | * in the driver parses the tables and executes then to program specific | |
915 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
916 | * atombios.h, and atom.c | |
917 | */ | |
918 | ||
919 | /** | |
920 | * cail_pll_read - read PLL register | |
921 | * | |
922 | * @info: atom card_info pointer | |
923 | * @reg: PLL register offset | |
924 | * | |
925 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
926 | * Returns the value of the PLL register. | |
927 | */ | |
928 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
929 | { | |
930 | return 0; | |
931 | } | |
932 | ||
933 | /** | |
934 | * cail_pll_write - write PLL register | |
935 | * | |
936 | * @info: atom card_info pointer | |
937 | * @reg: PLL register offset | |
938 | * @val: value to write to the pll register | |
939 | * | |
940 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
941 | */ | |
942 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
943 | { | |
944 | ||
945 | } | |
946 | ||
947 | /** | |
948 | * cail_mc_read - read MC (Memory Controller) register | |
949 | * | |
950 | * @info: atom card_info pointer | |
951 | * @reg: MC register offset | |
952 | * | |
953 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
954 | * Returns the value of the MC register. | |
955 | */ | |
956 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
957 | { | |
958 | return 0; | |
959 | } | |
960 | ||
961 | /** | |
962 | * cail_mc_write - write MC (Memory Controller) register | |
963 | * | |
964 | * @info: atom card_info pointer | |
965 | * @reg: MC register offset | |
966 | * @val: value to write to the pll register | |
967 | * | |
968 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
969 | */ | |
970 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
971 | { | |
972 | ||
973 | } | |
974 | ||
975 | /** | |
976 | * cail_reg_write - write MMIO register | |
977 | * | |
978 | * @info: atom card_info pointer | |
979 | * @reg: MMIO register offset | |
980 | * @val: value to write to the pll register | |
981 | * | |
982 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
983 | */ | |
984 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
985 | { | |
986 | struct amdgpu_device *adev = info->dev->dev_private; | |
987 | ||
988 | WREG32(reg, val); | |
989 | } | |
990 | ||
991 | /** | |
992 | * cail_reg_read - read MMIO register | |
993 | * | |
994 | * @info: atom card_info pointer | |
995 | * @reg: MMIO register offset | |
996 | * | |
997 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
998 | * Returns the value of the MMIO register. | |
999 | */ | |
1000 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
1001 | { | |
1002 | struct amdgpu_device *adev = info->dev->dev_private; | |
1003 | uint32_t r; | |
1004 | ||
1005 | r = RREG32(reg); | |
1006 | return r; | |
1007 | } | |
1008 | ||
1009 | /** | |
1010 | * cail_ioreg_write - write IO register | |
1011 | * | |
1012 | * @info: atom card_info pointer | |
1013 | * @reg: IO register offset | |
1014 | * @val: value to write to the pll register | |
1015 | * | |
1016 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
1017 | */ | |
1018 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
1019 | { | |
1020 | struct amdgpu_device *adev = info->dev->dev_private; | |
1021 | ||
1022 | WREG32_IO(reg, val); | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * cail_ioreg_read - read IO register | |
1027 | * | |
1028 | * @info: atom card_info pointer | |
1029 | * @reg: IO register offset | |
1030 | * | |
1031 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
1032 | * Returns the value of the IO register. | |
1033 | */ | |
1034 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
1035 | { | |
1036 | struct amdgpu_device *adev = info->dev->dev_private; | |
1037 | uint32_t r; | |
1038 | ||
1039 | r = RREG32_IO(reg); | |
1040 | return r; | |
1041 | } | |
1042 | ||
5b41d94c KR |
1043 | static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, |
1044 | struct device_attribute *attr, | |
1045 | char *buf) | |
1046 | { | |
1047 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1048 | struct amdgpu_device *adev = ddev->dev_private; | |
1049 | struct atom_context *ctx = adev->mode_info.atom_context; | |
1050 | ||
1051 | return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version); | |
1052 | } | |
1053 | ||
1054 | static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, | |
1055 | NULL); | |
1056 | ||
d38ceaf9 AD |
1057 | /** |
1058 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
1059 | * | |
1060 | * @adev: amdgpu_device pointer | |
1061 | * | |
1062 | * Frees the driver info and register access callbacks for the ATOM | |
1063 | * interpreter (r4xx+). | |
1064 | * Called at driver shutdown. | |
1065 | */ | |
1066 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
1067 | { | |
89e0ec9f | 1068 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 1069 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
1070 | kfree(adev->mode_info.atom_context->iio); |
1071 | } | |
d38ceaf9 AD |
1072 | kfree(adev->mode_info.atom_context); |
1073 | adev->mode_info.atom_context = NULL; | |
1074 | kfree(adev->mode_info.atom_card_info); | |
1075 | adev->mode_info.atom_card_info = NULL; | |
5b41d94c | 1076 | device_remove_file(adev->dev, &dev_attr_vbios_version); |
d38ceaf9 AD |
1077 | } |
1078 | ||
1079 | /** | |
1080 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
1081 | * | |
1082 | * @adev: amdgpu_device pointer | |
1083 | * | |
1084 | * Initializes the driver info and register access callbacks for the | |
1085 | * ATOM interpreter (r4xx+). | |
1086 | * Returns 0 on sucess, -ENOMEM on failure. | |
1087 | * Called at driver startup. | |
1088 | */ | |
1089 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
1090 | { | |
1091 | struct card_info *atom_card_info = | |
1092 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
5b41d94c | 1093 | int ret; |
d38ceaf9 AD |
1094 | |
1095 | if (!atom_card_info) | |
1096 | return -ENOMEM; | |
1097 | ||
1098 | adev->mode_info.atom_card_info = atom_card_info; | |
1099 | atom_card_info->dev = adev->ddev; | |
1100 | atom_card_info->reg_read = cail_reg_read; | |
1101 | atom_card_info->reg_write = cail_reg_write; | |
1102 | /* needed for iio ops */ | |
1103 | if (adev->rio_mem) { | |
1104 | atom_card_info->ioreg_read = cail_ioreg_read; | |
1105 | atom_card_info->ioreg_write = cail_ioreg_write; | |
1106 | } else { | |
9953b72f | 1107 | DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
1108 | atom_card_info->ioreg_read = cail_reg_read; |
1109 | atom_card_info->ioreg_write = cail_reg_write; | |
1110 | } | |
1111 | atom_card_info->mc_read = cail_mc_read; | |
1112 | atom_card_info->mc_write = cail_mc_write; | |
1113 | atom_card_info->pll_read = cail_pll_read; | |
1114 | atom_card_info->pll_write = cail_pll_write; | |
1115 | ||
1116 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
1117 | if (!adev->mode_info.atom_context) { | |
1118 | amdgpu_atombios_fini(adev); | |
1119 | return -ENOMEM; | |
1120 | } | |
1121 | ||
1122 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1123 | if (adev->is_atom_fw) { |
1124 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1125 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1126 | } else { | |
1127 | amdgpu_atombios_scratch_regs_init(adev); | |
1128 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1129 | } | |
5b41d94c KR |
1130 | |
1131 | ret = device_create_file(adev->dev, &dev_attr_vbios_version); | |
1132 | if (ret) { | |
1133 | DRM_ERROR("Failed to create device file for VBIOS version\n"); | |
1134 | return ret; | |
1135 | } | |
1136 | ||
d38ceaf9 AD |
1137 | return 0; |
1138 | } | |
1139 | ||
1140 | /* if we get transitioned to only one device, take VGA back */ | |
1141 | /** | |
1142 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1143 | * | |
1144 | * @cookie: amdgpu_device pointer | |
1145 | * @state: enable/disable vga decode | |
1146 | * | |
1147 | * Enable/disable vga decode (all asics). | |
1148 | * Returns VGA resource flags. | |
1149 | */ | |
1150 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1151 | { | |
1152 | struct amdgpu_device *adev = cookie; | |
1153 | amdgpu_asic_set_vga_state(adev, state); | |
1154 | if (state) | |
1155 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1156 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1157 | else | |
1158 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1159 | } | |
1160 | ||
bab4fee7 | 1161 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1162 | { |
1163 | /* defines number of bits in page table versus page directory, | |
1164 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1165 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1166 | if (amdgpu_vm_block_size == -1) |
1167 | return; | |
a1adf8be | 1168 | |
bab4fee7 | 1169 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1170 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1171 | amdgpu_vm_block_size); | |
bab4fee7 | 1172 | goto def_value; |
a1adf8be CZ |
1173 | } |
1174 | ||
1175 | if (amdgpu_vm_block_size > 24 || | |
1176 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1177 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1178 | amdgpu_vm_block_size); | |
bab4fee7 | 1179 | goto def_value; |
a1adf8be | 1180 | } |
bab4fee7 JZ |
1181 | |
1182 | return; | |
1183 | ||
1184 | def_value: | |
1185 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1186 | } |
1187 | ||
83ca145d ZJ |
1188 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1189 | { | |
64dab074 AD |
1190 | /* no need to check the default value */ |
1191 | if (amdgpu_vm_size == -1) | |
1192 | return; | |
1193 | ||
76117507 | 1194 | if (!is_power_of_2(amdgpu_vm_size)) { |
83ca145d ZJ |
1195 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", |
1196 | amdgpu_vm_size); | |
1197 | goto def_value; | |
1198 | } | |
1199 | ||
1200 | if (amdgpu_vm_size < 1) { | |
1201 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1202 | amdgpu_vm_size); | |
1203 | goto def_value; | |
1204 | } | |
1205 | ||
1206 | /* | |
1207 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1208 | */ | |
1209 | if (amdgpu_vm_size > 1024) { | |
1210 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1211 | amdgpu_vm_size); | |
1212 | goto def_value; | |
1213 | } | |
1214 | ||
1215 | return; | |
1216 | ||
1217 | def_value: | |
bab4fee7 | 1218 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1219 | } |
1220 | ||
d38ceaf9 AD |
1221 | /** |
1222 | * amdgpu_check_arguments - validate module params | |
1223 | * | |
1224 | * @adev: amdgpu_device pointer | |
1225 | * | |
1226 | * Validates certain module parameters and updates | |
1227 | * the associated values used by the driver (all asics). | |
1228 | */ | |
1229 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1230 | { | |
5b011235 CZ |
1231 | if (amdgpu_sched_jobs < 4) { |
1232 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1233 | amdgpu_sched_jobs); | |
1234 | amdgpu_sched_jobs = 4; | |
76117507 | 1235 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1236 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1237 | amdgpu_sched_jobs); | |
1238 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1239 | } | |
d38ceaf9 | 1240 | |
83e74db6 | 1241 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1242 | /* gart size must be greater or equal to 32M */ |
1243 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1244 | amdgpu_gart_size); | |
83e74db6 | 1245 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1246 | } |
1247 | ||
36d38372 | 1248 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1249 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1250 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1251 | amdgpu_gtt_size); | |
1252 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1253 | } |
1254 | ||
d07f14be RH |
1255 | /* valid range is between 4 and 9 inclusive */ |
1256 | if (amdgpu_vm_fragment_size != -1 && | |
1257 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1258 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1259 | amdgpu_vm_fragment_size = -1; | |
1260 | } | |
1261 | ||
83ca145d | 1262 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1263 | |
bab4fee7 | 1264 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1265 | |
526bae37 | 1266 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1267 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1268 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1269 | amdgpu_vram_page_split); | |
1270 | amdgpu_vram_page_split = 1024; | |
1271 | } | |
d38ceaf9 AD |
1272 | } |
1273 | ||
1274 | /** | |
1275 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1276 | * | |
1277 | * @pdev: pci dev pointer | |
1694467b | 1278 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1279 | * |
1280 | * Callback for the switcheroo driver. Suspends or resumes the | |
1281 | * the asics before or after it is powered up using ACPI methods. | |
1282 | */ | |
1283 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1284 | { | |
1285 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1286 | ||
1287 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1288 | return; | |
1289 | ||
1290 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1291 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1292 | /* don't suspend or resume card normally */ |
1293 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1294 | ||
810ddc3a | 1295 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1296 | |
d38ceaf9 AD |
1297 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1298 | drm_kms_helper_poll_enable(dev); | |
1299 | } else { | |
7ca85295 | 1300 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1301 | drm_kms_helper_poll_disable(dev); |
1302 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1303 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1304 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1305 | } | |
1306 | } | |
1307 | ||
1308 | /** | |
1309 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1310 | * | |
1311 | * @pdev: pci dev pointer | |
1312 | * | |
1313 | * Callback for the switcheroo driver. Check of the switcheroo | |
1314 | * state can be changed. | |
1315 | * Returns true if the state can be changed, false if not. | |
1316 | */ | |
1317 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1318 | { | |
1319 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1320 | ||
1321 | /* | |
1322 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1323 | * locking inversion with the driver load path. And the access here is | |
1324 | * completely racy anyway. So don't bother with locking for now. | |
1325 | */ | |
1326 | return dev->open_count == 0; | |
1327 | } | |
1328 | ||
1329 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1330 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1331 | .reprobe = NULL, | |
1332 | .can_switch = amdgpu_switcheroo_can_switch, | |
1333 | }; | |
1334 | ||
1335 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1336 | enum amd_ip_block_type block_type, |
1337 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1338 | { |
1339 | int i, r = 0; | |
1340 | ||
1341 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1342 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1343 | continue; |
c722865a RZ |
1344 | if (adev->ip_blocks[i].version->type != block_type) |
1345 | continue; | |
1346 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1347 | continue; | |
1348 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1349 | (void *)adev, state); | |
1350 | if (r) | |
1351 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1352 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1353 | } |
1354 | return r; | |
1355 | } | |
1356 | ||
1357 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1358 | enum amd_ip_block_type block_type, |
1359 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1360 | { |
1361 | int i, r = 0; | |
1362 | ||
1363 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1364 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1365 | continue; |
c722865a RZ |
1366 | if (adev->ip_blocks[i].version->type != block_type) |
1367 | continue; | |
1368 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1369 | continue; | |
1370 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1371 | (void *)adev, state); | |
1372 | if (r) | |
1373 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1374 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1375 | } |
1376 | return r; | |
1377 | } | |
1378 | ||
6cb2d4e4 HR |
1379 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1380 | { | |
1381 | int i; | |
1382 | ||
1383 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1384 | if (!adev->ip_blocks[i].status.valid) | |
1385 | continue; | |
1386 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1387 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1388 | } | |
1389 | } | |
1390 | ||
5dbbb60b AD |
1391 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1392 | enum amd_ip_block_type block_type) | |
1393 | { | |
1394 | int i, r; | |
1395 | ||
1396 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1397 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1398 | continue; |
a1255107 AD |
1399 | if (adev->ip_blocks[i].version->type == block_type) { |
1400 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1401 | if (r) |
1402 | return r; | |
1403 | break; | |
1404 | } | |
1405 | } | |
1406 | return 0; | |
1407 | ||
1408 | } | |
1409 | ||
1410 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1411 | enum amd_ip_block_type block_type) | |
1412 | { | |
1413 | int i; | |
1414 | ||
1415 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1416 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1417 | continue; |
a1255107 AD |
1418 | if (adev->ip_blocks[i].version->type == block_type) |
1419 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1420 | } |
1421 | return true; | |
1422 | ||
1423 | } | |
1424 | ||
a1255107 AD |
1425 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1426 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1427 | { |
1428 | int i; | |
1429 | ||
1430 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1431 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1432 | return &adev->ip_blocks[i]; |
1433 | ||
1434 | return NULL; | |
1435 | } | |
1436 | ||
1437 | /** | |
1438 | * amdgpu_ip_block_version_cmp | |
1439 | * | |
1440 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1441 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1442 | * @major: major version |
1443 | * @minor: minor version | |
1444 | * | |
1445 | * return 0 if equal or greater | |
1446 | * return 1 if smaller or the ip_block doesn't exist | |
1447 | */ | |
1448 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1449 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1450 | u32 major, u32 minor) |
1451 | { | |
a1255107 | 1452 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1453 | |
a1255107 AD |
1454 | if (ip_block && ((ip_block->version->major > major) || |
1455 | ((ip_block->version->major == major) && | |
1456 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1457 | return 0; |
1458 | ||
1459 | return 1; | |
1460 | } | |
1461 | ||
a1255107 AD |
1462 | /** |
1463 | * amdgpu_ip_block_add | |
1464 | * | |
1465 | * @adev: amdgpu_device pointer | |
1466 | * @ip_block_version: pointer to the IP to add | |
1467 | * | |
1468 | * Adds the IP block driver information to the collection of IPs | |
1469 | * on the asic. | |
1470 | */ | |
1471 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1472 | const struct amdgpu_ip_block_version *ip_block_version) | |
1473 | { | |
1474 | if (!ip_block_version) | |
1475 | return -EINVAL; | |
1476 | ||
a0bae357 HR |
1477 | DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, |
1478 | ip_block_version->funcs->name); | |
1479 | ||
a1255107 AD |
1480 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
483ef985 | 1485 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1486 | { |
1487 | adev->enable_virtual_display = false; | |
1488 | ||
1489 | if (amdgpu_virtual_display) { | |
1490 | struct drm_device *ddev = adev->ddev; | |
1491 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1492 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1493 | |
1494 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1495 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1496 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1497 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1498 | if (!strcmp("all", pciaddname) |
1499 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1500 | long num_crtc; |
1501 | int res = -1; | |
1502 | ||
9accf2fd | 1503 | adev->enable_virtual_display = true; |
0f66356d ED |
1504 | |
1505 | if (pciaddname_tmp) | |
1506 | res = kstrtol(pciaddname_tmp, 10, | |
1507 | &num_crtc); | |
1508 | ||
1509 | if (!res) { | |
1510 | if (num_crtc < 1) | |
1511 | num_crtc = 1; | |
1512 | if (num_crtc > 6) | |
1513 | num_crtc = 6; | |
1514 | adev->mode_info.num_crtc = num_crtc; | |
1515 | } else { | |
1516 | adev->mode_info.num_crtc = 1; | |
1517 | } | |
9accf2fd ED |
1518 | break; |
1519 | } | |
1520 | } | |
1521 | ||
0f66356d ED |
1522 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1523 | amdgpu_virtual_display, pci_address_name, | |
1524 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1525 | |
1526 | kfree(pciaddstr); | |
1527 | } | |
1528 | } | |
1529 | ||
e2a75f88 AD |
1530 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1531 | { | |
e2a75f88 AD |
1532 | const char *chip_name; |
1533 | char fw_name[30]; | |
1534 | int err; | |
1535 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1536 | ||
ab4fe3e1 HR |
1537 | adev->firmware.gpu_info_fw = NULL; |
1538 | ||
e2a75f88 AD |
1539 | switch (adev->asic_type) { |
1540 | case CHIP_TOPAZ: | |
1541 | case CHIP_TONGA: | |
1542 | case CHIP_FIJI: | |
1543 | case CHIP_POLARIS11: | |
1544 | case CHIP_POLARIS10: | |
1545 | case CHIP_POLARIS12: | |
1546 | case CHIP_CARRIZO: | |
1547 | case CHIP_STONEY: | |
1548 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1549 | case CHIP_VERDE: | |
1550 | case CHIP_TAHITI: | |
1551 | case CHIP_PITCAIRN: | |
1552 | case CHIP_OLAND: | |
1553 | case CHIP_HAINAN: | |
1554 | #endif | |
1555 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1556 | case CHIP_BONAIRE: | |
1557 | case CHIP_HAWAII: | |
1558 | case CHIP_KAVERI: | |
1559 | case CHIP_KABINI: | |
1560 | case CHIP_MULLINS: | |
1561 | #endif | |
1562 | default: | |
1563 | return 0; | |
1564 | case CHIP_VEGA10: | |
1565 | chip_name = "vega10"; | |
1566 | break; | |
2d2e5e7e AD |
1567 | case CHIP_RAVEN: |
1568 | chip_name = "raven"; | |
1569 | break; | |
e2a75f88 AD |
1570 | } |
1571 | ||
1572 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1573 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1574 | if (err) { |
1575 | dev_err(adev->dev, | |
1576 | "Failed to load gpu_info firmware \"%s\"\n", | |
1577 | fw_name); | |
1578 | goto out; | |
1579 | } | |
ab4fe3e1 | 1580 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1581 | if (err) { |
1582 | dev_err(adev->dev, | |
1583 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1584 | fw_name); | |
1585 | goto out; | |
1586 | } | |
1587 | ||
ab4fe3e1 | 1588 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1589 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1590 | ||
1591 | switch (hdr->version_major) { | |
1592 | case 1: | |
1593 | { | |
1594 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1595 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1596 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1597 | ||
b5ab16bf AD |
1598 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1599 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1600 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1601 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1602 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1603 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1604 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1605 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1606 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1607 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1608 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1609 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1610 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1611 | adev->gfx.cu_info.max_waves_per_simd = |
1612 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1613 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1614 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1615 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1616 | break; |
1617 | } | |
1618 | default: | |
1619 | dev_err(adev->dev, | |
1620 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1621 | err = -EINVAL; | |
1622 | goto out; | |
1623 | } | |
1624 | out: | |
e2a75f88 AD |
1625 | return err; |
1626 | } | |
1627 | ||
d38ceaf9 AD |
1628 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1629 | { | |
aaa36a97 | 1630 | int i, r; |
d38ceaf9 | 1631 | |
483ef985 | 1632 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1633 | |
d38ceaf9 | 1634 | switch (adev->asic_type) { |
aaa36a97 AD |
1635 | case CHIP_TOPAZ: |
1636 | case CHIP_TONGA: | |
48299f95 | 1637 | case CHIP_FIJI: |
2cc0c0b5 FC |
1638 | case CHIP_POLARIS11: |
1639 | case CHIP_POLARIS10: | |
c4642a47 | 1640 | case CHIP_POLARIS12: |
aaa36a97 | 1641 | case CHIP_CARRIZO: |
39bb0c92 SL |
1642 | case CHIP_STONEY: |
1643 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1644 | adev->family = AMDGPU_FAMILY_CZ; |
1645 | else | |
1646 | adev->family = AMDGPU_FAMILY_VI; | |
1647 | ||
1648 | r = vi_set_ip_blocks(adev); | |
1649 | if (r) | |
1650 | return r; | |
1651 | break; | |
33f34802 KW |
1652 | #ifdef CONFIG_DRM_AMDGPU_SI |
1653 | case CHIP_VERDE: | |
1654 | case CHIP_TAHITI: | |
1655 | case CHIP_PITCAIRN: | |
1656 | case CHIP_OLAND: | |
1657 | case CHIP_HAINAN: | |
295d0daf | 1658 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1659 | r = si_set_ip_blocks(adev); |
1660 | if (r) | |
1661 | return r; | |
1662 | break; | |
1663 | #endif | |
a2e73f56 AD |
1664 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1665 | case CHIP_BONAIRE: | |
1666 | case CHIP_HAWAII: | |
1667 | case CHIP_KAVERI: | |
1668 | case CHIP_KABINI: | |
1669 | case CHIP_MULLINS: | |
1670 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1671 | adev->family = AMDGPU_FAMILY_CI; | |
1672 | else | |
1673 | adev->family = AMDGPU_FAMILY_KV; | |
1674 | ||
1675 | r = cik_set_ip_blocks(adev); | |
1676 | if (r) | |
1677 | return r; | |
1678 | break; | |
1679 | #endif | |
2ca8a5d2 CZ |
1680 | case CHIP_VEGA10: |
1681 | case CHIP_RAVEN: | |
1682 | if (adev->asic_type == CHIP_RAVEN) | |
1683 | adev->family = AMDGPU_FAMILY_RV; | |
1684 | else | |
1685 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1686 | |
1687 | r = soc15_set_ip_blocks(adev); | |
1688 | if (r) | |
1689 | return r; | |
1690 | break; | |
d38ceaf9 AD |
1691 | default: |
1692 | /* FIXME: not supported yet */ | |
1693 | return -EINVAL; | |
1694 | } | |
1695 | ||
e2a75f88 AD |
1696 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1697 | if (r) | |
1698 | return r; | |
1699 | ||
1884734a | 1700 | amdgpu_amdkfd_device_probe(adev); |
1701 | ||
3149d9da XY |
1702 | if (amdgpu_sriov_vf(adev)) { |
1703 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1704 | if (r) | |
5ffa61c1 | 1705 | return -EAGAIN; |
3149d9da XY |
1706 | } |
1707 | ||
d38ceaf9 AD |
1708 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1709 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1710 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1711 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1712 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1713 | } else { |
a1255107 AD |
1714 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1715 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1716 | if (r == -ENOENT) { |
a1255107 | 1717 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1718 | } else if (r) { |
a1255107 AD |
1719 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1720 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1721 | return r; |
2c1a2784 | 1722 | } else { |
a1255107 | 1723 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1724 | } |
974e6b64 | 1725 | } else { |
a1255107 | 1726 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1727 | } |
d38ceaf9 AD |
1728 | } |
1729 | } | |
1730 | ||
395d1fb9 NH |
1731 | adev->cg_flags &= amdgpu_cg_mask; |
1732 | adev->pg_flags &= amdgpu_pg_mask; | |
1733 | ||
d38ceaf9 AD |
1734 | return 0; |
1735 | } | |
1736 | ||
1737 | static int amdgpu_init(struct amdgpu_device *adev) | |
1738 | { | |
1739 | int i, r; | |
1740 | ||
1741 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1742 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1743 | continue; |
a1255107 | 1744 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1745 | if (r) { |
a1255107 AD |
1746 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1747 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1748 | return r; |
2c1a2784 | 1749 | } |
a1255107 | 1750 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1751 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1752 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1753 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1754 | if (r) { |
1755 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1756 | return r; |
2c1a2784 | 1757 | } |
a1255107 | 1758 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1759 | if (r) { |
1760 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1761 | return r; |
2c1a2784 | 1762 | } |
d38ceaf9 | 1763 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1764 | if (r) { |
1765 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1766 | return r; |
2c1a2784 | 1767 | } |
a1255107 | 1768 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1769 | |
1770 | /* right after GMC hw init, we create CSA */ | |
1771 | if (amdgpu_sriov_vf(adev)) { | |
1772 | r = amdgpu_allocate_static_csa(adev); | |
1773 | if (r) { | |
1774 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1775 | return r; | |
1776 | } | |
1777 | } | |
d38ceaf9 AD |
1778 | } |
1779 | } | |
1780 | ||
1781 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1782 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1783 | continue; |
1784 | /* gmc hw init is done early */ | |
a1255107 | 1785 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1786 | continue; |
a1255107 | 1787 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1788 | if (r) { |
a1255107 AD |
1789 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1790 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1791 | return r; |
2c1a2784 | 1792 | } |
a1255107 | 1793 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1794 | } |
1795 | ||
1884734a | 1796 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1797 | |
1798 | if (amdgpu_sriov_vf(adev)) | |
1799 | amdgpu_virt_release_full_gpu(adev, true); | |
1800 | ||
d38ceaf9 AD |
1801 | return 0; |
1802 | } | |
1803 | ||
0c49e0b8 CZ |
1804 | static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) |
1805 | { | |
1806 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1807 | } | |
1808 | ||
1809 | static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) | |
1810 | { | |
1811 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1812 | AMDGPU_RESET_MAGIC_NUM); | |
1813 | } | |
1814 | ||
2dc80b00 | 1815 | static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1816 | { |
1817 | int i = 0, r; | |
1818 | ||
1819 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1820 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1821 | continue; |
4a446d55 | 1822 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1823 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1824 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1825 | /* enable clockgating to save power */ |
a1255107 AD |
1826 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1827 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1828 | if (r) { |
1829 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1830 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1831 | return r; |
1832 | } | |
b0b00ff1 | 1833 | } |
d38ceaf9 | 1834 | } |
2dc80b00 S |
1835 | return 0; |
1836 | } | |
1837 | ||
1838 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1839 | { | |
1840 | int i = 0, r; | |
1841 | ||
1842 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1843 | if (!adev->ip_blocks[i].status.valid) | |
1844 | continue; | |
1845 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1846 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1847 | if (r) { | |
1848 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1849 | adev->ip_blocks[i].version->funcs->name, r); | |
1850 | return r; | |
1851 | } | |
1852 | adev->ip_blocks[i].status.late_initialized = true; | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1857 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1858 | |
0c49e0b8 | 1859 | amdgpu_fill_reset_magic(adev); |
d38ceaf9 AD |
1860 | |
1861 | return 0; | |
1862 | } | |
1863 | ||
1864 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1865 | { | |
1866 | int i, r; | |
1867 | ||
1884734a | 1868 | amdgpu_amdkfd_device_fini(adev); |
3e96dbfd AD |
1869 | /* need to disable SMC first */ |
1870 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1871 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1872 | continue; |
a1255107 | 1873 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1874 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1875 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1876 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1877 | if (r) { |
1878 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1879 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1880 | return r; |
1881 | } | |
a1255107 | 1882 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1883 | /* XXX handle errors */ |
1884 | if (r) { | |
1885 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1886 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1887 | } |
a1255107 | 1888 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1889 | break; |
1890 | } | |
1891 | } | |
1892 | ||
d38ceaf9 | 1893 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1894 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1895 | continue; |
a1255107 | 1896 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1897 | amdgpu_wb_fini(adev); |
1898 | amdgpu_vram_scratch_fini(adev); | |
1899 | } | |
8201a67a RZ |
1900 | |
1901 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1902 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1903 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1904 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1905 | AMD_CG_STATE_UNGATE); | |
1906 | if (r) { | |
1907 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1908 | adev->ip_blocks[i].version->funcs->name, r); | |
1909 | return r; | |
1910 | } | |
2c1a2784 | 1911 | } |
8201a67a | 1912 | |
a1255107 | 1913 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1914 | /* XXX handle errors */ |
2c1a2784 | 1915 | if (r) { |
a1255107 AD |
1916 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1917 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1918 | } |
8201a67a | 1919 | |
a1255107 | 1920 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1921 | } |
1922 | ||
1923 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1924 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1925 | continue; |
a1255107 | 1926 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1927 | /* XXX handle errors */ |
2c1a2784 | 1928 | if (r) { |
a1255107 AD |
1929 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1930 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1931 | } |
a1255107 AD |
1932 | adev->ip_blocks[i].status.sw = false; |
1933 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1934 | } |
1935 | ||
a6dcfd9c | 1936 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1937 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1938 | continue; |
a1255107 AD |
1939 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1940 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1941 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1942 | } |
1943 | ||
030308fc | 1944 | if (amdgpu_sriov_vf(adev)) |
3149d9da | 1945 | amdgpu_virt_release_full_gpu(adev, false); |
2493664f | 1946 | |
d38ceaf9 AD |
1947 | return 0; |
1948 | } | |
1949 | ||
2dc80b00 S |
1950 | static void amdgpu_late_init_func_handler(struct work_struct *work) |
1951 | { | |
1952 | struct amdgpu_device *adev = | |
1953 | container_of(work, struct amdgpu_device, late_init_work.work); | |
1954 | amdgpu_late_set_cg_state(adev); | |
1955 | } | |
1956 | ||
faefba95 | 1957 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1958 | { |
1959 | int i, r; | |
1960 | ||
e941ea99 XY |
1961 | if (amdgpu_sriov_vf(adev)) |
1962 | amdgpu_virt_request_full_gpu(adev, false); | |
1963 | ||
c5a93a28 FC |
1964 | /* ungate SMC block first */ |
1965 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1966 | AMD_CG_STATE_UNGATE); | |
1967 | if (r) { | |
1968 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1969 | } | |
1970 | ||
d38ceaf9 | 1971 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1972 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1973 | continue; |
1974 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1975 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1976 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1977 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1978 | if (r) { |
a1255107 AD |
1979 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1980 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1981 | } |
2c1a2784 | 1982 | } |
d38ceaf9 | 1983 | /* XXX handle errors */ |
a1255107 | 1984 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1985 | /* XXX handle errors */ |
2c1a2784 | 1986 | if (r) { |
a1255107 AD |
1987 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1988 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1989 | } |
d38ceaf9 AD |
1990 | } |
1991 | ||
e941ea99 XY |
1992 | if (amdgpu_sriov_vf(adev)) |
1993 | amdgpu_virt_release_full_gpu(adev, false); | |
1994 | ||
d38ceaf9 AD |
1995 | return 0; |
1996 | } | |
1997 | ||
e4f0fdcc | 1998 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1999 | { |
2000 | int i, r; | |
2001 | ||
2cb681b6 ML |
2002 | static enum amd_ip_block_type ip_order[] = { |
2003 | AMD_IP_BLOCK_TYPE_GMC, | |
2004 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
2005 | AMD_IP_BLOCK_TYPE_IH, |
2006 | }; | |
a90ad3c2 | 2007 | |
2cb681b6 ML |
2008 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2009 | int j; | |
2010 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2011 | |
2cb681b6 ML |
2012 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2013 | block = &adev->ip_blocks[j]; | |
2014 | ||
2015 | if (block->version->type != ip_order[i] || | |
2016 | !block->status.valid) | |
2017 | continue; | |
2018 | ||
2019 | r = block->version->funcs->hw_init(adev); | |
2020 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
2021 | } |
2022 | } | |
2023 | ||
2024 | return 0; | |
2025 | } | |
2026 | ||
e4f0fdcc | 2027 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
2028 | { |
2029 | int i, r; | |
2030 | ||
2cb681b6 ML |
2031 | static enum amd_ip_block_type ip_order[] = { |
2032 | AMD_IP_BLOCK_TYPE_SMC, | |
ef4c166d | 2033 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2034 | AMD_IP_BLOCK_TYPE_DCE, |
2035 | AMD_IP_BLOCK_TYPE_GFX, | |
2036 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
2037 | AMD_IP_BLOCK_TYPE_UVD, |
2038 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 2039 | }; |
a90ad3c2 | 2040 | |
2cb681b6 ML |
2041 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2042 | int j; | |
2043 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2044 | |
2cb681b6 ML |
2045 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2046 | block = &adev->ip_blocks[j]; | |
2047 | ||
2048 | if (block->version->type != ip_order[i] || | |
2049 | !block->status.valid) | |
2050 | continue; | |
2051 | ||
2052 | r = block->version->funcs->hw_init(adev); | |
2053 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
2054 | } |
2055 | } | |
2056 | ||
2057 | return 0; | |
2058 | } | |
2059 | ||
fcf0649f | 2060 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2061 | { |
2062 | int i, r; | |
2063 | ||
a90ad3c2 ML |
2064 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2065 | if (!adev->ip_blocks[i].status.valid) | |
2066 | continue; | |
a90ad3c2 ML |
2067 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
2068 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
fcf0649f CZ |
2069 | adev->ip_blocks[i].version->type == |
2070 | AMD_IP_BLOCK_TYPE_IH) { | |
2071 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
2072 | if (r) { | |
2073 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2074 | adev->ip_blocks[i].version->funcs->name, r); | |
2075 | return r; | |
2076 | } | |
a90ad3c2 ML |
2077 | } |
2078 | } | |
2079 | ||
2080 | return 0; | |
2081 | } | |
2082 | ||
fcf0649f | 2083 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2084 | { |
2085 | int i, r; | |
2086 | ||
2087 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2088 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2089 | continue; |
fcf0649f CZ |
2090 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
2091 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2092 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
2093 | continue; | |
a1255107 | 2094 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2095 | if (r) { |
a1255107 AD |
2096 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2097 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2098 | return r; |
2c1a2784 | 2099 | } |
d38ceaf9 AD |
2100 | } |
2101 | ||
2102 | return 0; | |
2103 | } | |
2104 | ||
fcf0649f CZ |
2105 | static int amdgpu_resume(struct amdgpu_device *adev) |
2106 | { | |
2107 | int r; | |
2108 | ||
2109 | r = amdgpu_resume_phase1(adev); | |
2110 | if (r) | |
2111 | return r; | |
2112 | r = amdgpu_resume_phase2(adev); | |
2113 | ||
2114 | return r; | |
2115 | } | |
2116 | ||
4e99a44e | 2117 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2118 | { |
6867e1b5 ML |
2119 | if (amdgpu_sriov_vf(adev)) { |
2120 | if (adev->is_atom_fw) { | |
2121 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2122 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2123 | } else { | |
2124 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2125 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2126 | } | |
2127 | ||
2128 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2129 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2130 | } |
048765ad AR |
2131 | } |
2132 | ||
4562236b HW |
2133 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2134 | { | |
2135 | switch (asic_type) { | |
2136 | #if defined(CONFIG_DRM_AMD_DC) | |
2137 | case CHIP_BONAIRE: | |
2138 | case CHIP_HAWAII: | |
0d6fbccb | 2139 | case CHIP_KAVERI: |
4562236b HW |
2140 | case CHIP_CARRIZO: |
2141 | case CHIP_STONEY: | |
2142 | case CHIP_POLARIS11: | |
2143 | case CHIP_POLARIS10: | |
2c8ad2d5 | 2144 | case CHIP_POLARIS12: |
4562236b HW |
2145 | case CHIP_TONGA: |
2146 | case CHIP_FIJI: | |
2147 | #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) | |
2148 | return amdgpu_dc != 0; | |
4562236b | 2149 | #endif |
17b7cf8c AD |
2150 | case CHIP_KABINI: |
2151 | case CHIP_MULLINS: | |
2152 | return amdgpu_dc > 0; | |
42f8ffa1 HW |
2153 | case CHIP_VEGA10: |
2154 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | |
fd187853 | 2155 | case CHIP_RAVEN: |
42f8ffa1 | 2156 | #endif |
fd187853 | 2157 | return amdgpu_dc != 0; |
4562236b HW |
2158 | #endif |
2159 | default: | |
2160 | return false; | |
2161 | } | |
2162 | } | |
2163 | ||
2164 | /** | |
2165 | * amdgpu_device_has_dc_support - check if dc is supported | |
2166 | * | |
2167 | * @adev: amdgpu_device_pointer | |
2168 | * | |
2169 | * Returns true for supported, false for not supported | |
2170 | */ | |
2171 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2172 | { | |
2555039d XY |
2173 | if (amdgpu_sriov_vf(adev)) |
2174 | return false; | |
2175 | ||
4562236b HW |
2176 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2177 | } | |
2178 | ||
d38ceaf9 AD |
2179 | /** |
2180 | * amdgpu_device_init - initialize the driver | |
2181 | * | |
2182 | * @adev: amdgpu_device pointer | |
2183 | * @pdev: drm dev pointer | |
2184 | * @pdev: pci dev pointer | |
2185 | * @flags: driver flags | |
2186 | * | |
2187 | * Initializes the driver info and hw (all asics). | |
2188 | * Returns 0 for success or an error on failure. | |
2189 | * Called at driver startup. | |
2190 | */ | |
2191 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2192 | struct drm_device *ddev, | |
2193 | struct pci_dev *pdev, | |
2194 | uint32_t flags) | |
2195 | { | |
2196 | int r, i; | |
2197 | bool runtime = false; | |
95844d20 | 2198 | u32 max_MBps; |
d38ceaf9 AD |
2199 | |
2200 | adev->shutdown = false; | |
2201 | adev->dev = &pdev->dev; | |
2202 | adev->ddev = ddev; | |
2203 | adev->pdev = pdev; | |
2204 | adev->flags = flags; | |
2f7d10b3 | 2205 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2206 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
6f02a696 | 2207 | adev->mc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2208 | adev->accel_working = false; |
2209 | adev->num_rings = 0; | |
2210 | adev->mman.buffer_funcs = NULL; | |
2211 | adev->mman.buffer_funcs_ring = NULL; | |
2212 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2213 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 2214 | adev->gart.gart_funcs = NULL; |
f54d1867 | 2215 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2216 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2217 | |
2218 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2219 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2220 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2221 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2222 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2223 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2224 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2225 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2226 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2227 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2228 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2229 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2230 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2231 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2232 | ||
3e39ab90 AD |
2233 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2234 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2235 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2236 | |
2237 | /* mutex initialization are all done here so we | |
2238 | * can recall function without having locking issues */ | |
d38ceaf9 | 2239 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2240 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2241 | mutex_init(&adev->pm.mutex); |
2242 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2243 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2244 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d38ceaf9 | 2245 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2246 | mutex_init(&adev->mn_lock); |
e23b74aa | 2247 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 2248 | hash_init(adev->mn_hash); |
13a752e3 | 2249 | mutex_init(&adev->lock_reset); |
d38ceaf9 AD |
2250 | |
2251 | amdgpu_check_arguments(adev); | |
2252 | ||
d38ceaf9 AD |
2253 | spin_lock_init(&adev->mmio_idx_lock); |
2254 | spin_lock_init(&adev->smc_idx_lock); | |
2255 | spin_lock_init(&adev->pcie_idx_lock); | |
2256 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2257 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2258 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2259 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2260 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2261 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2262 | |
0c4e7fa5 CZ |
2263 | INIT_LIST_HEAD(&adev->shadow_list); |
2264 | mutex_init(&adev->shadow_list_lock); | |
2265 | ||
795f2813 AR |
2266 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2267 | spin_lock_init(&adev->ring_lru_list_lock); | |
2268 | ||
2dc80b00 S |
2269 | INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); |
2270 | ||
0fa49558 AX |
2271 | /* Registers mapping */ |
2272 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2273 | if (adev->asic_type >= CHIP_BONAIRE) { |
2274 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2275 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2276 | } else { | |
2277 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2278 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2279 | } | |
d38ceaf9 | 2280 | |
d38ceaf9 AD |
2281 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2282 | if (adev->rmmio == NULL) { | |
2283 | return -ENOMEM; | |
2284 | } | |
2285 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2286 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2287 | ||
705e519e CK |
2288 | /* doorbell bar mapping */ |
2289 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2290 | |
2291 | /* io port mapping */ | |
2292 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2293 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2294 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2295 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2296 | break; | |
2297 | } | |
2298 | } | |
2299 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2300 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2301 | |
2302 | /* early init functions */ | |
2303 | r = amdgpu_early_init(adev); | |
2304 | if (r) | |
2305 | return r; | |
2306 | ||
2307 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2308 | /* this will fail for cards that aren't VGA class devices, just | |
2309 | * ignore it */ | |
2310 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2311 | ||
2312 | if (amdgpu_runtime_pm == 1) | |
2313 | runtime = true; | |
e9bef455 | 2314 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2315 | runtime = true; |
84c8b22e LW |
2316 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2317 | vga_switcheroo_register_client(adev->pdev, | |
2318 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2319 | if (runtime) |
2320 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2321 | ||
2322 | /* Read BIOS */ | |
83ba126a AD |
2323 | if (!amdgpu_get_bios(adev)) { |
2324 | r = -EINVAL; | |
2325 | goto failed; | |
2326 | } | |
f7e9e9fe | 2327 | |
d38ceaf9 | 2328 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2329 | if (r) { |
2330 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
e23b74aa | 2331 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2332 | goto failed; |
2c1a2784 | 2333 | } |
d38ceaf9 | 2334 | |
4e99a44e ML |
2335 | /* detect if we are with an SRIOV vbios */ |
2336 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2337 | |
d38ceaf9 | 2338 | /* Post card if necessary */ |
91fe77eb | 2339 | if (amdgpu_need_post(adev)) { |
d38ceaf9 | 2340 | if (!adev->bios) { |
bec86378 | 2341 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2342 | r = -EINVAL; |
2343 | goto failed; | |
d38ceaf9 | 2344 | } |
bec86378 | 2345 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2346 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2347 | if (r) { | |
2348 | dev_err(adev->dev, "gpu post error!\n"); | |
2349 | goto failed; | |
2350 | } | |
d38ceaf9 AD |
2351 | } |
2352 | ||
88b64e95 AD |
2353 | if (adev->is_atom_fw) { |
2354 | /* Initialize clocks */ | |
2355 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2356 | if (r) { | |
2357 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2358 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2359 | goto failed; |
2360 | } | |
2361 | } else { | |
a5bde2f9 AD |
2362 | /* Initialize clocks */ |
2363 | r = amdgpu_atombios_get_clock_info(adev); | |
2364 | if (r) { | |
2365 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2366 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2367 | goto failed; |
a5bde2f9 AD |
2368 | } |
2369 | /* init i2c buses */ | |
4562236b HW |
2370 | if (!amdgpu_device_has_dc_support(adev)) |
2371 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2372 | } |
d38ceaf9 AD |
2373 | |
2374 | /* Fence driver */ | |
2375 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2376 | if (r) { |
2377 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2378 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2379 | goto failed; |
2c1a2784 | 2380 | } |
d38ceaf9 AD |
2381 | |
2382 | /* init the mode config */ | |
2383 | drm_mode_config_init(adev->ddev); | |
2384 | ||
2385 | r = amdgpu_init(adev); | |
2386 | if (r) { | |
8840a387 | 2387 | /* failed in exclusive mode due to timeout */ |
2388 | if (amdgpu_sriov_vf(adev) && | |
2389 | !amdgpu_sriov_runtime(adev) && | |
2390 | amdgpu_virt_mmio_blocked(adev) && | |
2391 | !amdgpu_virt_wait_reset(adev)) { | |
2392 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
2393 | r = -EAGAIN; | |
2394 | goto failed; | |
2395 | } | |
2c1a2784 | 2396 | dev_err(adev->dev, "amdgpu_init failed\n"); |
e23b74aa | 2397 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
d38ceaf9 | 2398 | amdgpu_fini(adev); |
83ba126a | 2399 | goto failed; |
d38ceaf9 AD |
2400 | } |
2401 | ||
2402 | adev->accel_working = true; | |
2403 | ||
e59c0205 AX |
2404 | amdgpu_vm_check_compute_bug(adev); |
2405 | ||
95844d20 MO |
2406 | /* Initialize the buffer migration limit. */ |
2407 | if (amdgpu_moverate >= 0) | |
2408 | max_MBps = amdgpu_moverate; | |
2409 | else | |
2410 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2411 | /* Get a log2 for easy divisions. */ | |
2412 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2413 | ||
d38ceaf9 AD |
2414 | r = amdgpu_ib_pool_init(adev); |
2415 | if (r) { | |
2416 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
e23b74aa | 2417 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2418 | goto failed; |
d38ceaf9 AD |
2419 | } |
2420 | ||
2421 | r = amdgpu_ib_ring_tests(adev); | |
2422 | if (r) | |
2423 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2424 | ||
2dc8f81e HC |
2425 | if (amdgpu_sriov_vf(adev)) |
2426 | amdgpu_virt_init_data_exchange(adev); | |
2427 | ||
9bc92b9c ML |
2428 | amdgpu_fbdev_init(adev); |
2429 | ||
d2f52ac8 RZ |
2430 | r = amdgpu_pm_sysfs_init(adev); |
2431 | if (r) | |
2432 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2433 | ||
d38ceaf9 | 2434 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2435 | if (r) |
d38ceaf9 | 2436 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2437 | |
2438 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2439 | if (r) |
d38ceaf9 | 2440 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2441 | |
4f0955fc HR |
2442 | r = amdgpu_debugfs_test_ib_ring_init(adev); |
2443 | if (r) | |
2444 | DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); | |
2445 | ||
50ab2533 | 2446 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2447 | if (r) |
50ab2533 | 2448 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2449 | |
db95e218 KR |
2450 | r = amdgpu_debugfs_vbios_dump_init(adev); |
2451 | if (r) | |
2452 | DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r); | |
2453 | ||
d38ceaf9 AD |
2454 | if ((amdgpu_testing & 1)) { |
2455 | if (adev->accel_working) | |
2456 | amdgpu_test_moves(adev); | |
2457 | else | |
2458 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2459 | } | |
d38ceaf9 AD |
2460 | if (amdgpu_benchmarking) { |
2461 | if (adev->accel_working) | |
2462 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2463 | else | |
2464 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2465 | } | |
2466 | ||
2467 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2468 | * explicit gating rather than handling it automatically. | |
2469 | */ | |
2470 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2471 | if (r) { |
2472 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
e23b74aa | 2473 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2474 | goto failed; |
2c1a2784 | 2475 | } |
d38ceaf9 AD |
2476 | |
2477 | return 0; | |
83ba126a AD |
2478 | |
2479 | failed: | |
89041940 | 2480 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2481 | if (runtime) |
2482 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 2483 | |
83ba126a | 2484 | return r; |
d38ceaf9 AD |
2485 | } |
2486 | ||
d38ceaf9 AD |
2487 | /** |
2488 | * amdgpu_device_fini - tear down the driver | |
2489 | * | |
2490 | * @adev: amdgpu_device pointer | |
2491 | * | |
2492 | * Tear down the driver info (all asics). | |
2493 | * Called at driver shutdown. | |
2494 | */ | |
2495 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2496 | { | |
2497 | int r; | |
2498 | ||
2499 | DRM_INFO("amdgpu: finishing device.\n"); | |
2500 | adev->shutdown = true; | |
db2c2a97 PD |
2501 | if (adev->mode_info.mode_config_initialized) |
2502 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2503 | /* evict vram memory */ |
2504 | amdgpu_bo_evict_vram(adev); | |
2505 | amdgpu_ib_pool_fini(adev); | |
a05502e5 | 2506 | amdgpu_fw_reserve_vram_fini(adev); |
d38ceaf9 AD |
2507 | amdgpu_fence_driver_fini(adev); |
2508 | amdgpu_fbdev_fini(adev); | |
2509 | r = amdgpu_fini(adev); | |
ab4fe3e1 HR |
2510 | if (adev->firmware.gpu_info_fw) { |
2511 | release_firmware(adev->firmware.gpu_info_fw); | |
2512 | adev->firmware.gpu_info_fw = NULL; | |
2513 | } | |
d38ceaf9 | 2514 | adev->accel_working = false; |
2dc80b00 | 2515 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 | 2516 | /* free i2c buses */ |
4562236b HW |
2517 | if (!amdgpu_device_has_dc_support(adev)) |
2518 | amdgpu_i2c_fini(adev); | |
d38ceaf9 AD |
2519 | amdgpu_atombios_fini(adev); |
2520 | kfree(adev->bios); | |
2521 | adev->bios = NULL; | |
84c8b22e LW |
2522 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2523 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2524 | if (adev->flags & AMD_IS_PX) |
2525 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2526 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2527 | if (adev->rio_mem) | |
2528 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2529 | adev->rio_mem = NULL; | |
2530 | iounmap(adev->rmmio); | |
2531 | adev->rmmio = NULL; | |
705e519e | 2532 | amdgpu_doorbell_fini(adev); |
d2f52ac8 | 2533 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2534 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2535 | } |
2536 | ||
2537 | ||
2538 | /* | |
2539 | * Suspend & resume. | |
2540 | */ | |
2541 | /** | |
810ddc3a | 2542 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2543 | * |
2544 | * @pdev: drm dev pointer | |
2545 | * @state: suspend state | |
2546 | * | |
2547 | * Puts the hw in the suspend state (all asics). | |
2548 | * Returns 0 for success or an error on failure. | |
2549 | * Called at driver suspend. | |
2550 | */ | |
810ddc3a | 2551 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2552 | { |
2553 | struct amdgpu_device *adev; | |
2554 | struct drm_crtc *crtc; | |
2555 | struct drm_connector *connector; | |
5ceb54c6 | 2556 | int r; |
d38ceaf9 AD |
2557 | |
2558 | if (dev == NULL || dev->dev_private == NULL) { | |
2559 | return -ENODEV; | |
2560 | } | |
2561 | ||
2562 | adev = dev->dev_private; | |
2563 | ||
2564 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2565 | return 0; | |
2566 | ||
2567 | drm_kms_helper_poll_disable(dev); | |
2568 | ||
4562236b HW |
2569 | if (!amdgpu_device_has_dc_support(adev)) { |
2570 | /* turn off display hw */ | |
2571 | drm_modeset_lock_all(dev); | |
2572 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2573 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2574 | } | |
2575 | drm_modeset_unlock_all(dev); | |
d38ceaf9 AD |
2576 | } |
2577 | ||
ba997709 YZ |
2578 | amdgpu_amdkfd_suspend(adev); |
2579 | ||
756e6880 | 2580 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2581 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2582 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2583 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2584 | struct amdgpu_bo *robj; | |
2585 | ||
756e6880 AD |
2586 | if (amdgpu_crtc->cursor_bo) { |
2587 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2588 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2589 | if (r == 0) { |
2590 | amdgpu_bo_unpin(aobj); | |
2591 | amdgpu_bo_unreserve(aobj); | |
2592 | } | |
2593 | } | |
2594 | ||
d38ceaf9 AD |
2595 | if (rfb == NULL || rfb->obj == NULL) { |
2596 | continue; | |
2597 | } | |
2598 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2599 | /* don't unpin kernel fb objects */ | |
2600 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2601 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2602 | if (r == 0) { |
2603 | amdgpu_bo_unpin(robj); | |
2604 | amdgpu_bo_unreserve(robj); | |
2605 | } | |
2606 | } | |
2607 | } | |
2608 | /* evict vram memory */ | |
2609 | amdgpu_bo_evict_vram(adev); | |
2610 | ||
5ceb54c6 | 2611 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2612 | |
2613 | r = amdgpu_suspend(adev); | |
2614 | ||
a0a71e49 AD |
2615 | /* evict remaining vram memory |
2616 | * This second call to evict vram is to evict the gart page table | |
2617 | * using the CPU. | |
2618 | */ | |
d38ceaf9 AD |
2619 | amdgpu_bo_evict_vram(adev); |
2620 | ||
d05da0e2 | 2621 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
2622 | pci_save_state(dev->pdev); |
2623 | if (suspend) { | |
2624 | /* Shut down the device */ | |
2625 | pci_disable_device(dev->pdev); | |
2626 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2627 | } else { |
2628 | r = amdgpu_asic_reset(adev); | |
2629 | if (r) | |
2630 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2631 | } |
2632 | ||
2633 | if (fbcon) { | |
2634 | console_lock(); | |
2635 | amdgpu_fbdev_set_suspend(adev, 1); | |
2636 | console_unlock(); | |
2637 | } | |
2638 | return 0; | |
2639 | } | |
2640 | ||
2641 | /** | |
810ddc3a | 2642 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2643 | * |
2644 | * @pdev: drm dev pointer | |
2645 | * | |
2646 | * Bring the hw back to operating state (all asics). | |
2647 | * Returns 0 for success or an error on failure. | |
2648 | * Called at driver resume. | |
2649 | */ | |
810ddc3a | 2650 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2651 | { |
2652 | struct drm_connector *connector; | |
2653 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2654 | struct drm_crtc *crtc; |
03161a6e | 2655 | int r = 0; |
d38ceaf9 AD |
2656 | |
2657 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2658 | return 0; | |
2659 | ||
74b0b157 | 2660 | if (fbcon) |
d38ceaf9 | 2661 | console_lock(); |
74b0b157 | 2662 | |
d38ceaf9 AD |
2663 | if (resume) { |
2664 | pci_set_power_state(dev->pdev, PCI_D0); | |
2665 | pci_restore_state(dev->pdev); | |
74b0b157 | 2666 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2667 | if (r) |
2668 | goto unlock; | |
d38ceaf9 | 2669 | } |
d05da0e2 | 2670 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2671 | |
2672 | /* post card */ | |
c836fec5 | 2673 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2674 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2675 | if (r) | |
2676 | DRM_ERROR("amdgpu asic init failed\n"); | |
2677 | } | |
d38ceaf9 AD |
2678 | |
2679 | r = amdgpu_resume(adev); | |
e6707218 | 2680 | if (r) { |
ca198528 | 2681 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2682 | goto unlock; |
e6707218 | 2683 | } |
5ceb54c6 AD |
2684 | amdgpu_fence_driver_resume(adev); |
2685 | ||
ca198528 FC |
2686 | if (resume) { |
2687 | r = amdgpu_ib_ring_tests(adev); | |
2688 | if (r) | |
2689 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2690 | } | |
d38ceaf9 AD |
2691 | |
2692 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2693 | if (r) |
2694 | goto unlock; | |
d38ceaf9 | 2695 | |
756e6880 AD |
2696 | /* pin cursors */ |
2697 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2698 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2699 | ||
2700 | if (amdgpu_crtc->cursor_bo) { | |
2701 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2702 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2703 | if (r == 0) { |
2704 | r = amdgpu_bo_pin(aobj, | |
2705 | AMDGPU_GEM_DOMAIN_VRAM, | |
2706 | &amdgpu_crtc->cursor_addr); | |
2707 | if (r != 0) | |
2708 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2709 | amdgpu_bo_unreserve(aobj); | |
2710 | } | |
2711 | } | |
2712 | } | |
ba997709 YZ |
2713 | r = amdgpu_amdkfd_resume(adev); |
2714 | if (r) | |
2715 | return r; | |
756e6880 | 2716 | |
d38ceaf9 AD |
2717 | /* blat the mode back in */ |
2718 | if (fbcon) { | |
4562236b HW |
2719 | if (!amdgpu_device_has_dc_support(adev)) { |
2720 | /* pre DCE11 */ | |
2721 | drm_helper_resume_force_mode(dev); | |
2722 | ||
2723 | /* turn on display hw */ | |
2724 | drm_modeset_lock_all(dev); | |
2725 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2726 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2727 | } | |
2728 | drm_modeset_unlock_all(dev); | |
2729 | } else { | |
2730 | /* | |
2731 | * There is no equivalent atomic helper to turn on | |
2732 | * display, so we defined our own function for this, | |
2733 | * once suspend resume is supported by the atomic | |
2734 | * framework this will be reworked | |
2735 | */ | |
2736 | amdgpu_dm_display_resume(adev); | |
d38ceaf9 AD |
2737 | } |
2738 | } | |
2739 | ||
2740 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2741 | |
2742 | /* | |
2743 | * Most of the connector probing functions try to acquire runtime pm | |
2744 | * refs to ensure that the GPU is powered on when connector polling is | |
2745 | * performed. Since we're calling this from a runtime PM callback, | |
2746 | * trying to acquire rpm refs will cause us to deadlock. | |
2747 | * | |
2748 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2749 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2750 | */ | |
2751 | #ifdef CONFIG_PM | |
2752 | dev->dev->power.disable_depth++; | |
2753 | #endif | |
4562236b HW |
2754 | if (!amdgpu_device_has_dc_support(adev)) |
2755 | drm_helper_hpd_irq_event(dev); | |
2756 | else | |
2757 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
2758 | #ifdef CONFIG_PM |
2759 | dev->dev->power.disable_depth--; | |
2760 | #endif | |
d38ceaf9 | 2761 | |
03161a6e | 2762 | if (fbcon) |
d38ceaf9 | 2763 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2764 | |
2765 | unlock: | |
2766 | if (fbcon) | |
d38ceaf9 | 2767 | console_unlock(); |
d38ceaf9 | 2768 | |
03161a6e | 2769 | return r; |
d38ceaf9 AD |
2770 | } |
2771 | ||
63fbf42f CZ |
2772 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2773 | { | |
2774 | int i; | |
2775 | bool asic_hang = false; | |
2776 | ||
f993d628 ML |
2777 | if (amdgpu_sriov_vf(adev)) |
2778 | return true; | |
2779 | ||
63fbf42f | 2780 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2781 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2782 | continue; |
a1255107 AD |
2783 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2784 | adev->ip_blocks[i].status.hang = | |
2785 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2786 | if (adev->ip_blocks[i].status.hang) { | |
2787 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2788 | asic_hang = true; |
2789 | } | |
2790 | } | |
2791 | return asic_hang; | |
2792 | } | |
2793 | ||
4d446656 | 2794 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2795 | { |
2796 | int i, r = 0; | |
2797 | ||
2798 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2799 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2800 | continue; |
a1255107 AD |
2801 | if (adev->ip_blocks[i].status.hang && |
2802 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2803 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2804 | if (r) |
2805 | return r; | |
2806 | } | |
2807 | } | |
2808 | ||
2809 | return 0; | |
2810 | } | |
2811 | ||
35d782fe CZ |
2812 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2813 | { | |
da146d3b AD |
2814 | int i; |
2815 | ||
2816 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2817 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2818 | continue; |
a1255107 AD |
2819 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2820 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2821 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
2822 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
2823 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 2824 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
2825 | DRM_INFO("Some block need full reset!\n"); |
2826 | return true; | |
2827 | } | |
2828 | } | |
35d782fe CZ |
2829 | } |
2830 | return false; | |
2831 | } | |
2832 | ||
2833 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2834 | { | |
2835 | int i, r = 0; | |
2836 | ||
2837 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2838 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2839 | continue; |
a1255107 AD |
2840 | if (adev->ip_blocks[i].status.hang && |
2841 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2842 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2843 | if (r) |
2844 | return r; | |
2845 | } | |
2846 | } | |
2847 | ||
2848 | return 0; | |
2849 | } | |
2850 | ||
2851 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2852 | { | |
2853 | int i, r = 0; | |
2854 | ||
2855 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2856 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2857 | continue; |
a1255107 AD |
2858 | if (adev->ip_blocks[i].status.hang && |
2859 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2860 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2861 | if (r) |
2862 | return r; | |
2863 | } | |
2864 | ||
2865 | return 0; | |
2866 | } | |
2867 | ||
3ad81f16 CZ |
2868 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2869 | { | |
2870 | if (adev->flags & AMD_IS_APU) | |
2871 | return false; | |
2872 | ||
2873 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2874 | } | |
2875 | ||
53cdccd5 CZ |
2876 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2877 | struct amdgpu_ring *ring, | |
2878 | struct amdgpu_bo *bo, | |
f54d1867 | 2879 | struct dma_fence **fence) |
53cdccd5 CZ |
2880 | { |
2881 | uint32_t domain; | |
2882 | int r; | |
2883 | ||
23d2e504 RH |
2884 | if (!bo->shadow) |
2885 | return 0; | |
2886 | ||
1d284797 | 2887 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2888 | if (r) |
2889 | return r; | |
2890 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2891 | /* if bo has been evicted, then no need to recover */ | |
2892 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2893 | r = amdgpu_bo_validate(bo->shadow); |
2894 | if (r) { | |
2895 | DRM_ERROR("bo validate failed!\n"); | |
2896 | goto err; | |
2897 | } | |
2898 | ||
23d2e504 | 2899 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2900 | NULL, fence, true); |
23d2e504 RH |
2901 | if (r) { |
2902 | DRM_ERROR("recover page table failed!\n"); | |
2903 | goto err; | |
2904 | } | |
2905 | } | |
53cdccd5 | 2906 | err: |
23d2e504 RH |
2907 | amdgpu_bo_unreserve(bo); |
2908 | return r; | |
53cdccd5 CZ |
2909 | } |
2910 | ||
5740682e ML |
2911 | /* |
2912 | * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough | |
a90ad3c2 ML |
2913 | * |
2914 | * @adev: amdgpu device pointer | |
5740682e | 2915 | * @reset_flags: output param tells caller the reset result |
a90ad3c2 | 2916 | * |
5740682e ML |
2917 | * attempt to do soft-reset or full-reset and reinitialize Asic |
2918 | * return 0 means successed otherwise failed | |
2919 | */ | |
2920 | static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) | |
a90ad3c2 | 2921 | { |
5740682e ML |
2922 | bool need_full_reset, vram_lost = 0; |
2923 | int r; | |
a90ad3c2 | 2924 | |
5740682e | 2925 | need_full_reset = amdgpu_need_full_reset(adev); |
a90ad3c2 | 2926 | |
5740682e ML |
2927 | if (!need_full_reset) { |
2928 | amdgpu_pre_soft_reset(adev); | |
2929 | r = amdgpu_soft_reset(adev); | |
2930 | amdgpu_post_soft_reset(adev); | |
2931 | if (r || amdgpu_check_soft_reset(adev)) { | |
2932 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2933 | need_full_reset = true; | |
2934 | } | |
a90ad3c2 | 2935 | |
5740682e | 2936 | } |
a90ad3c2 | 2937 | |
5740682e ML |
2938 | if (need_full_reset) { |
2939 | r = amdgpu_suspend(adev); | |
a90ad3c2 | 2940 | |
5740682e ML |
2941 | retry: |
2942 | amdgpu_atombios_scratch_regs_save(adev); | |
2943 | r = amdgpu_asic_reset(adev); | |
2944 | amdgpu_atombios_scratch_regs_restore(adev); | |
2945 | /* post card */ | |
2946 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
65781c78 | 2947 | |
5740682e ML |
2948 | if (!r) { |
2949 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
2950 | r = amdgpu_resume_phase1(adev); | |
2951 | if (r) | |
2952 | goto out; | |
65781c78 | 2953 | |
5740682e ML |
2954 | vram_lost = amdgpu_check_vram_lost(adev); |
2955 | if (vram_lost) { | |
2956 | DRM_ERROR("VRAM is lost!\n"); | |
2957 | atomic_inc(&adev->vram_lost_counter); | |
2958 | } | |
2959 | ||
c1c7ce8f CK |
2960 | r = amdgpu_gtt_mgr_recover( |
2961 | &adev->mman.bdev.man[TTM_PL_TT]); | |
5740682e ML |
2962 | if (r) |
2963 | goto out; | |
2964 | ||
2965 | r = amdgpu_resume_phase2(adev); | |
2966 | if (r) | |
2967 | goto out; | |
2968 | ||
2969 | if (vram_lost) | |
2970 | amdgpu_fill_reset_magic(adev); | |
65781c78 | 2971 | } |
5740682e | 2972 | } |
65781c78 | 2973 | |
5740682e ML |
2974 | out: |
2975 | if (!r) { | |
2976 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2977 | r = amdgpu_ib_ring_tests(adev); | |
2978 | if (r) { | |
2979 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
2980 | r = amdgpu_suspend(adev); | |
2981 | need_full_reset = true; | |
2982 | goto retry; | |
2983 | } | |
2984 | } | |
65781c78 | 2985 | |
5740682e ML |
2986 | if (reset_flags) { |
2987 | if (vram_lost) | |
2988 | (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST; | |
a90ad3c2 | 2989 | |
5740682e ML |
2990 | if (need_full_reset) |
2991 | (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET; | |
65781c78 | 2992 | } |
a90ad3c2 | 2993 | |
5740682e ML |
2994 | return r; |
2995 | } | |
a90ad3c2 | 2996 | |
5740682e ML |
2997 | /* |
2998 | * amdgpu_reset_sriov - reset ASIC for SR-IOV vf | |
2999 | * | |
3000 | * @adev: amdgpu device pointer | |
3001 | * @reset_flags: output param tells caller the reset result | |
3002 | * | |
3003 | * do VF FLR and reinitialize Asic | |
3004 | * return 0 means successed otherwise failed | |
3005 | */ | |
3006 | static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor) | |
3007 | { | |
3008 | int r; | |
3009 | ||
3010 | if (from_hypervisor) | |
3011 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3012 | else | |
3013 | r = amdgpu_virt_reset_gpu(adev); | |
3014 | if (r) | |
3015 | return r; | |
a90ad3c2 ML |
3016 | |
3017 | /* Resume IP prior to SMC */ | |
5740682e ML |
3018 | r = amdgpu_sriov_reinit_early(adev); |
3019 | if (r) | |
3020 | goto error; | |
a90ad3c2 ML |
3021 | |
3022 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 3023 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 ML |
3024 | |
3025 | /* now we are okay to resume SMC/CP/SDMA */ | |
5740682e ML |
3026 | r = amdgpu_sriov_reinit_late(adev); |
3027 | if (r) | |
3028 | goto error; | |
a90ad3c2 ML |
3029 | |
3030 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e ML |
3031 | r = amdgpu_ib_ring_tests(adev); |
3032 | if (r) | |
a90ad3c2 ML |
3033 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); |
3034 | ||
5740682e | 3035 | error: |
a90ad3c2 ML |
3036 | /* release full control of GPU after ib test */ |
3037 | amdgpu_virt_release_full_gpu(adev, true); | |
3038 | ||
5740682e | 3039 | if (reset_flags) { |
75bc6099 ML |
3040 | if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
3041 | (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST; | |
3042 | atomic_inc(&adev->vram_lost_counter); | |
3043 | } | |
a90ad3c2 | 3044 | |
5740682e ML |
3045 | /* VF FLR or hotlink reset is always full-reset */ |
3046 | (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET; | |
a90ad3c2 ML |
3047 | } |
3048 | ||
3049 | return r; | |
3050 | } | |
3051 | ||
d38ceaf9 | 3052 | /** |
5740682e | 3053 | * amdgpu_gpu_recover - reset the asic and recover scheduler |
d38ceaf9 AD |
3054 | * |
3055 | * @adev: amdgpu device pointer | |
5740682e | 3056 | * @job: which job trigger hang |
d38ceaf9 | 3057 | * |
5740682e | 3058 | * Attempt to reset the GPU if it has hung (all asics). |
d38ceaf9 AD |
3059 | * Returns 0 for success or an error on failure. |
3060 | */ | |
5740682e | 3061 | int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) |
d38ceaf9 | 3062 | { |
4562236b | 3063 | struct drm_atomic_state *state = NULL; |
5740682e ML |
3064 | uint64_t reset_flags = 0; |
3065 | int i, r, resched; | |
fb140b29 | 3066 | |
63fbf42f CZ |
3067 | if (!amdgpu_check_soft_reset(adev)) { |
3068 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
3069 | return 0; | |
3070 | } | |
d38ceaf9 | 3071 | |
5740682e ML |
3072 | dev_info(adev->dev, "GPU reset begin!\n"); |
3073 | ||
13a752e3 | 3074 | mutex_lock(&adev->lock_reset); |
d94aed5a | 3075 | atomic_inc(&adev->gpu_reset_counter); |
13a752e3 | 3076 | adev->in_gpu_reset = 1; |
d38ceaf9 | 3077 | |
a3c47d6b CZ |
3078 | /* block TTM */ |
3079 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
4562236b HW |
3080 | /* store modesetting */ |
3081 | if (amdgpu_device_has_dc_support(adev)) | |
3082 | state = drm_atomic_helper_suspend(adev->ddev); | |
a3c47d6b | 3083 | |
0875dc9e CZ |
3084 | /* block scheduler */ |
3085 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
3086 | struct amdgpu_ring *ring = adev->rings[i]; | |
3087 | ||
51687759 | 3088 | if (!ring || !ring->sched.thread) |
0875dc9e | 3089 | continue; |
5740682e ML |
3090 | |
3091 | /* only focus on the ring hit timeout if &job not NULL */ | |
3092 | if (job && job->ring->idx != i) | |
3093 | continue; | |
3094 | ||
0875dc9e | 3095 | kthread_park(ring->sched.thread); |
5740682e ML |
3096 | amd_sched_hw_job_reset(&ring->sched, &job->base); |
3097 | ||
2f9d4084 ML |
3098 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
3099 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 3100 | } |
d38ceaf9 | 3101 | |
5740682e ML |
3102 | if (amdgpu_sriov_vf(adev)) |
3103 | r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true); | |
3104 | else | |
3105 | r = amdgpu_reset(adev, &reset_flags); | |
35d782fe | 3106 | |
d38ceaf9 | 3107 | if (!r) { |
5740682e ML |
3108 | if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) || |
3109 | (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) { | |
53cdccd5 CZ |
3110 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; |
3111 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 3112 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
3113 | |
3114 | DRM_INFO("recover vram bo from shadow\n"); | |
3115 | mutex_lock(&adev->shadow_list_lock); | |
3116 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 3117 | next = NULL; |
53cdccd5 CZ |
3118 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
3119 | if (fence) { | |
f54d1867 | 3120 | r = dma_fence_wait(fence, false); |
53cdccd5 | 3121 | if (r) { |
1d7b17b0 | 3122 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
3123 | break; |
3124 | } | |
3125 | } | |
1f465087 | 3126 | |
f54d1867 | 3127 | dma_fence_put(fence); |
53cdccd5 CZ |
3128 | fence = next; |
3129 | } | |
3130 | mutex_unlock(&adev->shadow_list_lock); | |
3131 | if (fence) { | |
f54d1867 | 3132 | r = dma_fence_wait(fence, false); |
53cdccd5 | 3133 | if (r) |
1d7b17b0 | 3134 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 3135 | } |
f54d1867 | 3136 | dma_fence_put(fence); |
53cdccd5 | 3137 | } |
5740682e | 3138 | |
d38ceaf9 AD |
3139 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3140 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
3141 | |
3142 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 3143 | continue; |
53cdccd5 | 3144 | |
5740682e ML |
3145 | /* only focus on the ring hit timeout if &job not NULL */ |
3146 | if (job && job->ring->idx != i) | |
3147 | continue; | |
3148 | ||
aa1c8900 | 3149 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 3150 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 3151 | } |
d38ceaf9 | 3152 | } else { |
d38ceaf9 | 3153 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5740682e ML |
3154 | struct amdgpu_ring *ring = adev->rings[i]; |
3155 | ||
3156 | if (!ring || !ring->sched.thread) | |
3157 | continue; | |
3158 | ||
3159 | /* only focus on the ring hit timeout if &job not NULL */ | |
3160 | if (job && job->ring->idx != i) | |
3161 | continue; | |
3162 | ||
3163 | kthread_unpark(adev->rings[i]->sched.thread); | |
d38ceaf9 AD |
3164 | } |
3165 | } | |
3166 | ||
4562236b | 3167 | if (amdgpu_device_has_dc_support(adev)) { |
5740682e ML |
3168 | if (drm_atomic_helper_resume(adev->ddev, state)) |
3169 | dev_info(adev->dev, "drm resume failed:%d\n", r); | |
4562236b | 3170 | amdgpu_dm_display_resume(adev); |
5740682e | 3171 | } else { |
4562236b | 3172 | drm_helper_resume_force_mode(adev->ddev); |
5740682e | 3173 | } |
d38ceaf9 AD |
3174 | |
3175 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
5740682e | 3176 | |
89041940 | 3177 | if (r) { |
d38ceaf9 | 3178 | /* bad news, how to tell it to userspace ? */ |
5740682e ML |
3179 | dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); |
3180 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); | |
3181 | } else { | |
3182 | dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter)); | |
89041940 | 3183 | } |
d38ceaf9 | 3184 | |
89041940 | 3185 | amdgpu_vf_error_trans_all(adev); |
13a752e3 ML |
3186 | adev->in_gpu_reset = 0; |
3187 | mutex_unlock(&adev->lock_reset); | |
d38ceaf9 AD |
3188 | return r; |
3189 | } | |
3190 | ||
d0dd7f0c AD |
3191 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
3192 | { | |
3193 | u32 mask; | |
3194 | int ret; | |
3195 | ||
cd474ba0 AD |
3196 | if (amdgpu_pcie_gen_cap) |
3197 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3198 | |
cd474ba0 AD |
3199 | if (amdgpu_pcie_lane_cap) |
3200 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3201 | |
cd474ba0 AD |
3202 | /* covers APUs as well */ |
3203 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3204 | if (adev->pm.pcie_gen_mask == 0) | |
3205 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3206 | if (adev->pm.pcie_mlw_mask == 0) | |
3207 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3208 | return; |
cd474ba0 | 3209 | } |
d0dd7f0c | 3210 | |
cd474ba0 AD |
3211 | if (adev->pm.pcie_gen_mask == 0) { |
3212 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
3213 | if (!ret) { | |
3214 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3215 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3216 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3217 | ||
3218 | if (mask & DRM_PCIE_SPEED_25) | |
3219 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3220 | if (mask & DRM_PCIE_SPEED_50) | |
3221 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3222 | if (mask & DRM_PCIE_SPEED_80) | |
3223 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3224 | } else { | |
3225 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3226 | } | |
3227 | } | |
3228 | if (adev->pm.pcie_mlw_mask == 0) { | |
3229 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3230 | if (!ret) { | |
3231 | switch (mask) { | |
3232 | case 32: | |
3233 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3234 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3235 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3236 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3237 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3238 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3239 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3240 | break; | |
3241 | case 16: | |
3242 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3243 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3244 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3245 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3246 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3247 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3248 | break; | |
3249 | case 12: | |
3250 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3251 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3252 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3253 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3254 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3255 | break; | |
3256 | case 8: | |
3257 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3258 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3259 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3260 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3261 | break; | |
3262 | case 4: | |
3263 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3264 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3265 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3266 | break; | |
3267 | case 2: | |
3268 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3269 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3270 | break; | |
3271 | case 1: | |
3272 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3273 | break; | |
3274 | default: | |
3275 | break; | |
3276 | } | |
3277 | } else { | |
3278 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3279 | } |
3280 | } | |
3281 | } | |
d38ceaf9 AD |
3282 | |
3283 | /* | |
3284 | * Debugfs | |
3285 | */ | |
3286 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3287 | const struct drm_info_list *files, |
d38ceaf9 AD |
3288 | unsigned nfiles) |
3289 | { | |
3290 | unsigned i; | |
3291 | ||
3292 | for (i = 0; i < adev->debugfs_count; i++) { | |
3293 | if (adev->debugfs[i].files == files) { | |
3294 | /* Already registered */ | |
3295 | return 0; | |
3296 | } | |
3297 | } | |
3298 | ||
3299 | i = adev->debugfs_count + 1; | |
3300 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3301 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3302 | DRM_ERROR("Report so we increase " | |
3303 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3304 | return -EINVAL; | |
3305 | } | |
3306 | adev->debugfs[adev->debugfs_count].files = files; | |
3307 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3308 | adev->debugfs_count = i; | |
3309 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3310 | drm_debugfs_create_files(files, nfiles, |
3311 | adev->ddev->primary->debugfs_root, | |
3312 | adev->ddev->primary); | |
3313 | #endif | |
3314 | return 0; | |
3315 | } | |
3316 | ||
d38ceaf9 AD |
3317 | #if defined(CONFIG_DEBUG_FS) |
3318 | ||
3319 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3320 | size_t size, loff_t *pos) | |
3321 | { | |
45063097 | 3322 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3323 | ssize_t result = 0; |
3324 | int r; | |
bd12267d | 3325 | bool pm_pg_lock, use_bank; |
56628159 | 3326 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3327 | |
3328 | if (size & 0x3 || *pos & 0x3) | |
3329 | return -EINVAL; | |
3330 | ||
bd12267d TSD |
3331 | /* are we reading registers for which a PG lock is necessary? */ |
3332 | pm_pg_lock = (*pos >> 23) & 1; | |
3333 | ||
56628159 | 3334 | if (*pos & (1ULL << 62)) { |
0b968650 TSD |
3335 | se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; |
3336 | sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; | |
3337 | instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; | |
32977f93 TSD |
3338 | |
3339 | if (se_bank == 0x3FF) | |
3340 | se_bank = 0xFFFFFFFF; | |
3341 | if (sh_bank == 0x3FF) | |
3342 | sh_bank = 0xFFFFFFFF; | |
3343 | if (instance_bank == 0x3FF) | |
3344 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3345 | use_bank = 1; |
56628159 TSD |
3346 | } else { |
3347 | use_bank = 0; | |
3348 | } | |
3349 | ||
801a6aa9 | 3350 | *pos &= (1UL << 22) - 1; |
bd12267d | 3351 | |
56628159 | 3352 | if (use_bank) { |
32977f93 TSD |
3353 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3354 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3355 | return -EINVAL; |
3356 | mutex_lock(&adev->grbm_idx_mutex); | |
3357 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3358 | sh_bank, instance_bank); | |
3359 | } | |
3360 | ||
bd12267d TSD |
3361 | if (pm_pg_lock) |
3362 | mutex_lock(&adev->pm.mutex); | |
3363 | ||
d38ceaf9 AD |
3364 | while (size) { |
3365 | uint32_t value; | |
3366 | ||
3367 | if (*pos > adev->rmmio_size) | |
56628159 | 3368 | goto end; |
d38ceaf9 AD |
3369 | |
3370 | value = RREG32(*pos >> 2); | |
3371 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3372 | if (r) { |
3373 | result = r; | |
3374 | goto end; | |
3375 | } | |
d38ceaf9 AD |
3376 | |
3377 | result += 4; | |
3378 | buf += 4; | |
3379 | *pos += 4; | |
3380 | size -= 4; | |
3381 | } | |
3382 | ||
56628159 TSD |
3383 | end: |
3384 | if (use_bank) { | |
3385 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3386 | mutex_unlock(&adev->grbm_idx_mutex); | |
3387 | } | |
3388 | ||
bd12267d TSD |
3389 | if (pm_pg_lock) |
3390 | mutex_unlock(&adev->pm.mutex); | |
3391 | ||
d38ceaf9 AD |
3392 | return result; |
3393 | } | |
3394 | ||
3395 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3396 | size_t size, loff_t *pos) | |
3397 | { | |
45063097 | 3398 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3399 | ssize_t result = 0; |
3400 | int r; | |
394fdde2 TSD |
3401 | bool pm_pg_lock, use_bank; |
3402 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3403 | |
3404 | if (size & 0x3 || *pos & 0x3) | |
3405 | return -EINVAL; | |
3406 | ||
394fdde2 TSD |
3407 | /* are we reading registers for which a PG lock is necessary? */ |
3408 | pm_pg_lock = (*pos >> 23) & 1; | |
3409 | ||
3410 | if (*pos & (1ULL << 62)) { | |
0b968650 TSD |
3411 | se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; |
3412 | sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; | |
3413 | instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; | |
394fdde2 TSD |
3414 | |
3415 | if (se_bank == 0x3FF) | |
3416 | se_bank = 0xFFFFFFFF; | |
3417 | if (sh_bank == 0x3FF) | |
3418 | sh_bank = 0xFFFFFFFF; | |
3419 | if (instance_bank == 0x3FF) | |
3420 | instance_bank = 0xFFFFFFFF; | |
3421 | use_bank = 1; | |
3422 | } else { | |
3423 | use_bank = 0; | |
3424 | } | |
3425 | ||
801a6aa9 | 3426 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3427 | |
3428 | if (use_bank) { | |
3429 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3430 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3431 | return -EINVAL; | |
3432 | mutex_lock(&adev->grbm_idx_mutex); | |
3433 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3434 | sh_bank, instance_bank); | |
3435 | } | |
3436 | ||
3437 | if (pm_pg_lock) | |
3438 | mutex_lock(&adev->pm.mutex); | |
3439 | ||
d38ceaf9 AD |
3440 | while (size) { |
3441 | uint32_t value; | |
3442 | ||
3443 | if (*pos > adev->rmmio_size) | |
3444 | return result; | |
3445 | ||
3446 | r = get_user(value, (uint32_t *)buf); | |
3447 | if (r) | |
3448 | return r; | |
3449 | ||
3450 | WREG32(*pos >> 2, value); | |
3451 | ||
3452 | result += 4; | |
3453 | buf += 4; | |
3454 | *pos += 4; | |
3455 | size -= 4; | |
3456 | } | |
3457 | ||
394fdde2 TSD |
3458 | if (use_bank) { |
3459 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3460 | mutex_unlock(&adev->grbm_idx_mutex); | |
3461 | } | |
3462 | ||
3463 | if (pm_pg_lock) | |
3464 | mutex_unlock(&adev->pm.mutex); | |
3465 | ||
d38ceaf9 AD |
3466 | return result; |
3467 | } | |
3468 | ||
adcec288 TSD |
3469 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3470 | size_t size, loff_t *pos) | |
3471 | { | |
45063097 | 3472 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3473 | ssize_t result = 0; |
3474 | int r; | |
3475 | ||
3476 | if (size & 0x3 || *pos & 0x3) | |
3477 | return -EINVAL; | |
3478 | ||
3479 | while (size) { | |
3480 | uint32_t value; | |
3481 | ||
3482 | value = RREG32_PCIE(*pos >> 2); | |
3483 | r = put_user(value, (uint32_t *)buf); | |
3484 | if (r) | |
3485 | return r; | |
3486 | ||
3487 | result += 4; | |
3488 | buf += 4; | |
3489 | *pos += 4; | |
3490 | size -= 4; | |
3491 | } | |
3492 | ||
3493 | return result; | |
3494 | } | |
3495 | ||
3496 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3497 | size_t size, loff_t *pos) | |
3498 | { | |
45063097 | 3499 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3500 | ssize_t result = 0; |
3501 | int r; | |
3502 | ||
3503 | if (size & 0x3 || *pos & 0x3) | |
3504 | return -EINVAL; | |
3505 | ||
3506 | while (size) { | |
3507 | uint32_t value; | |
3508 | ||
3509 | r = get_user(value, (uint32_t *)buf); | |
3510 | if (r) | |
3511 | return r; | |
3512 | ||
3513 | WREG32_PCIE(*pos >> 2, value); | |
3514 | ||
3515 | result += 4; | |
3516 | buf += 4; | |
3517 | *pos += 4; | |
3518 | size -= 4; | |
3519 | } | |
3520 | ||
3521 | return result; | |
3522 | } | |
3523 | ||
3524 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3525 | size_t size, loff_t *pos) | |
3526 | { | |
45063097 | 3527 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3528 | ssize_t result = 0; |
3529 | int r; | |
3530 | ||
3531 | if (size & 0x3 || *pos & 0x3) | |
3532 | return -EINVAL; | |
3533 | ||
3534 | while (size) { | |
3535 | uint32_t value; | |
3536 | ||
3537 | value = RREG32_DIDT(*pos >> 2); | |
3538 | r = put_user(value, (uint32_t *)buf); | |
3539 | if (r) | |
3540 | return r; | |
3541 | ||
3542 | result += 4; | |
3543 | buf += 4; | |
3544 | *pos += 4; | |
3545 | size -= 4; | |
3546 | } | |
3547 | ||
3548 | return result; | |
3549 | } | |
3550 | ||
3551 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3552 | size_t size, loff_t *pos) | |
3553 | { | |
45063097 | 3554 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3555 | ssize_t result = 0; |
3556 | int r; | |
3557 | ||
3558 | if (size & 0x3 || *pos & 0x3) | |
3559 | return -EINVAL; | |
3560 | ||
3561 | while (size) { | |
3562 | uint32_t value; | |
3563 | ||
3564 | r = get_user(value, (uint32_t *)buf); | |
3565 | if (r) | |
3566 | return r; | |
3567 | ||
3568 | WREG32_DIDT(*pos >> 2, value); | |
3569 | ||
3570 | result += 4; | |
3571 | buf += 4; | |
3572 | *pos += 4; | |
3573 | size -= 4; | |
3574 | } | |
3575 | ||
3576 | return result; | |
3577 | } | |
3578 | ||
3579 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3580 | size_t size, loff_t *pos) | |
3581 | { | |
45063097 | 3582 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3583 | ssize_t result = 0; |
3584 | int r; | |
3585 | ||
3586 | if (size & 0x3 || *pos & 0x3) | |
3587 | return -EINVAL; | |
3588 | ||
3589 | while (size) { | |
3590 | uint32_t value; | |
3591 | ||
6fc0deaf | 3592 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3593 | r = put_user(value, (uint32_t *)buf); |
3594 | if (r) | |
3595 | return r; | |
3596 | ||
3597 | result += 4; | |
3598 | buf += 4; | |
3599 | *pos += 4; | |
3600 | size -= 4; | |
3601 | } | |
3602 | ||
3603 | return result; | |
3604 | } | |
3605 | ||
3606 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3607 | size_t size, loff_t *pos) | |
3608 | { | |
45063097 | 3609 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3610 | ssize_t result = 0; |
3611 | int r; | |
3612 | ||
3613 | if (size & 0x3 || *pos & 0x3) | |
3614 | return -EINVAL; | |
3615 | ||
3616 | while (size) { | |
3617 | uint32_t value; | |
3618 | ||
3619 | r = get_user(value, (uint32_t *)buf); | |
3620 | if (r) | |
3621 | return r; | |
3622 | ||
6fc0deaf | 3623 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3624 | |
3625 | result += 4; | |
3626 | buf += 4; | |
3627 | *pos += 4; | |
3628 | size -= 4; | |
3629 | } | |
3630 | ||
3631 | return result; | |
3632 | } | |
3633 | ||
1e051413 TSD |
3634 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3635 | size_t size, loff_t *pos) | |
3636 | { | |
45063097 | 3637 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3638 | ssize_t result = 0; |
3639 | int r; | |
3640 | uint32_t *config, no_regs = 0; | |
3641 | ||
3642 | if (size & 0x3 || *pos & 0x3) | |
3643 | return -EINVAL; | |
3644 | ||
ecab7668 | 3645 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3646 | if (!config) |
3647 | return -ENOMEM; | |
3648 | ||
3649 | /* version, increment each time something is added */ | |
9a999359 | 3650 | config[no_regs++] = 3; |
1e051413 TSD |
3651 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3652 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3653 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3654 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3655 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3656 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3657 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3658 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3659 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3660 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3661 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3662 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3663 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3664 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3665 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3666 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3667 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3668 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3669 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3670 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3671 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3672 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3673 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3674 | ||
89a8f309 TSD |
3675 | /* rev==1 */ |
3676 | config[no_regs++] = adev->rev_id; | |
3677 | config[no_regs++] = adev->pg_flags; | |
3678 | config[no_regs++] = adev->cg_flags; | |
3679 | ||
e9f11dc8 TSD |
3680 | /* rev==2 */ |
3681 | config[no_regs++] = adev->family; | |
3682 | config[no_regs++] = adev->external_rev_id; | |
3683 | ||
9a999359 TSD |
3684 | /* rev==3 */ |
3685 | config[no_regs++] = adev->pdev->device; | |
3686 | config[no_regs++] = adev->pdev->revision; | |
3687 | config[no_regs++] = adev->pdev->subsystem_device; | |
3688 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3689 | ||
1e051413 TSD |
3690 | while (size && (*pos < no_regs * 4)) { |
3691 | uint32_t value; | |
3692 | ||
3693 | value = config[*pos >> 2]; | |
3694 | r = put_user(value, (uint32_t *)buf); | |
3695 | if (r) { | |
3696 | kfree(config); | |
3697 | return r; | |
3698 | } | |
3699 | ||
3700 | result += 4; | |
3701 | buf += 4; | |
3702 | *pos += 4; | |
3703 | size -= 4; | |
3704 | } | |
3705 | ||
3706 | kfree(config); | |
3707 | return result; | |
3708 | } | |
3709 | ||
f2cdaf20 TSD |
3710 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3711 | size_t size, loff_t *pos) | |
3712 | { | |
45063097 | 3713 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3714 | int idx, x, outsize, r, valuesize; |
3715 | uint32_t values[16]; | |
f2cdaf20 | 3716 | |
9f8df7d7 | 3717 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3718 | return -EINVAL; |
3719 | ||
3cbc614f SP |
3720 | if (amdgpu_dpm == 0) |
3721 | return -EINVAL; | |
3722 | ||
f2cdaf20 TSD |
3723 | /* convert offset to sensor number */ |
3724 | idx = *pos >> 2; | |
3725 | ||
9f8df7d7 | 3726 | valuesize = sizeof(values); |
f2cdaf20 | 3727 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
cd4d7464 | 3728 | r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); |
f2cdaf20 TSD |
3729 | else |
3730 | return -EINVAL; | |
3731 | ||
9f8df7d7 TSD |
3732 | if (size > valuesize) |
3733 | return -EINVAL; | |
3734 | ||
3735 | outsize = 0; | |
3736 | x = 0; | |
3737 | if (!r) { | |
3738 | while (size) { | |
3739 | r = put_user(values[x++], (int32_t *)buf); | |
3740 | buf += 4; | |
3741 | size -= 4; | |
3742 | outsize += 4; | |
3743 | } | |
3744 | } | |
f2cdaf20 | 3745 | |
9f8df7d7 | 3746 | return !r ? outsize : r; |
f2cdaf20 | 3747 | } |
1e051413 | 3748 | |
273d7aa1 TSD |
3749 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3750 | size_t size, loff_t *pos) | |
3751 | { | |
3752 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3753 | int r, x; | |
3754 | ssize_t result=0; | |
472259f0 | 3755 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3756 | |
3757 | if (size & 3 || *pos & 3) | |
3758 | return -EINVAL; | |
3759 | ||
3760 | /* decode offset */ | |
0b968650 TSD |
3761 | offset = (*pos & GENMASK_ULL(6, 0)); |
3762 | se = (*pos & GENMASK_ULL(14, 7)) >> 7; | |
3763 | sh = (*pos & GENMASK_ULL(22, 15)) >> 15; | |
3764 | cu = (*pos & GENMASK_ULL(30, 23)) >> 23; | |
3765 | wave = (*pos & GENMASK_ULL(36, 31)) >> 31; | |
3766 | simd = (*pos & GENMASK_ULL(44, 37)) >> 37; | |
273d7aa1 TSD |
3767 | |
3768 | /* switch to the specific se/sh/cu */ | |
3769 | mutex_lock(&adev->grbm_idx_mutex); | |
3770 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3771 | ||
3772 | x = 0; | |
472259f0 TSD |
3773 | if (adev->gfx.funcs->read_wave_data) |
3774 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3775 | |
3776 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3777 | mutex_unlock(&adev->grbm_idx_mutex); | |
3778 | ||
5ecfb3b8 TSD |
3779 | if (!x) |
3780 | return -EINVAL; | |
3781 | ||
472259f0 | 3782 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3783 | uint32_t value; |
3784 | ||
472259f0 | 3785 | value = data[offset >> 2]; |
273d7aa1 TSD |
3786 | r = put_user(value, (uint32_t *)buf); |
3787 | if (r) | |
3788 | return r; | |
3789 | ||
3790 | result += 4; | |
3791 | buf += 4; | |
472259f0 | 3792 | offset += 4; |
273d7aa1 TSD |
3793 | size -= 4; |
3794 | } | |
3795 | ||
3796 | return result; | |
3797 | } | |
3798 | ||
c5a60ce8 TSD |
3799 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3800 | size_t size, loff_t *pos) | |
3801 | { | |
3802 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3803 | int r; | |
3804 | ssize_t result = 0; | |
3805 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3806 | ||
3807 | if (size & 3 || *pos & 3) | |
3808 | return -EINVAL; | |
3809 | ||
3810 | /* decode offset */ | |
0b968650 TSD |
3811 | offset = *pos & GENMASK_ULL(11, 0); |
3812 | se = (*pos & GENMASK_ULL(19, 12)) >> 12; | |
3813 | sh = (*pos & GENMASK_ULL(27, 20)) >> 20; | |
3814 | cu = (*pos & GENMASK_ULL(35, 28)) >> 28; | |
3815 | wave = (*pos & GENMASK_ULL(43, 36)) >> 36; | |
3816 | simd = (*pos & GENMASK_ULL(51, 44)) >> 44; | |
3817 | thread = (*pos & GENMASK_ULL(59, 52)) >> 52; | |
3818 | bank = (*pos & GENMASK_ULL(61, 60)) >> 60; | |
c5a60ce8 TSD |
3819 | |
3820 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3821 | if (!data) | |
3822 | return -ENOMEM; | |
3823 | ||
3824 | /* switch to the specific se/sh/cu */ | |
3825 | mutex_lock(&adev->grbm_idx_mutex); | |
3826 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3827 | ||
3828 | if (bank == 0) { | |
3829 | if (adev->gfx.funcs->read_wave_vgprs) | |
3830 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3831 | } else { | |
3832 | if (adev->gfx.funcs->read_wave_sgprs) | |
3833 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3834 | } | |
3835 | ||
3836 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3837 | mutex_unlock(&adev->grbm_idx_mutex); | |
3838 | ||
3839 | while (size) { | |
3840 | uint32_t value; | |
3841 | ||
3842 | value = data[offset++]; | |
3843 | r = put_user(value, (uint32_t *)buf); | |
3844 | if (r) { | |
3845 | result = r; | |
3846 | goto err; | |
3847 | } | |
3848 | ||
3849 | result += 4; | |
3850 | buf += 4; | |
3851 | size -= 4; | |
3852 | } | |
3853 | ||
3854 | err: | |
3855 | kfree(data); | |
3856 | return result; | |
3857 | } | |
3858 | ||
d38ceaf9 AD |
3859 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3860 | .owner = THIS_MODULE, | |
3861 | .read = amdgpu_debugfs_regs_read, | |
3862 | .write = amdgpu_debugfs_regs_write, | |
3863 | .llseek = default_llseek | |
3864 | }; | |
adcec288 TSD |
3865 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3866 | .owner = THIS_MODULE, | |
3867 | .read = amdgpu_debugfs_regs_didt_read, | |
3868 | .write = amdgpu_debugfs_regs_didt_write, | |
3869 | .llseek = default_llseek | |
3870 | }; | |
3871 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3872 | .owner = THIS_MODULE, | |
3873 | .read = amdgpu_debugfs_regs_pcie_read, | |
3874 | .write = amdgpu_debugfs_regs_pcie_write, | |
3875 | .llseek = default_llseek | |
3876 | }; | |
3877 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3878 | .owner = THIS_MODULE, | |
3879 | .read = amdgpu_debugfs_regs_smc_read, | |
3880 | .write = amdgpu_debugfs_regs_smc_write, | |
3881 | .llseek = default_llseek | |
3882 | }; | |
3883 | ||
1e051413 TSD |
3884 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3885 | .owner = THIS_MODULE, | |
3886 | .read = amdgpu_debugfs_gca_config_read, | |
3887 | .llseek = default_llseek | |
3888 | }; | |
3889 | ||
f2cdaf20 TSD |
3890 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3891 | .owner = THIS_MODULE, | |
3892 | .read = amdgpu_debugfs_sensor_read, | |
3893 | .llseek = default_llseek | |
3894 | }; | |
3895 | ||
273d7aa1 TSD |
3896 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3897 | .owner = THIS_MODULE, | |
3898 | .read = amdgpu_debugfs_wave_read, | |
3899 | .llseek = default_llseek | |
3900 | }; | |
c5a60ce8 TSD |
3901 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3902 | .owner = THIS_MODULE, | |
3903 | .read = amdgpu_debugfs_gpr_read, | |
3904 | .llseek = default_llseek | |
3905 | }; | |
273d7aa1 | 3906 | |
adcec288 TSD |
3907 | static const struct file_operations *debugfs_regs[] = { |
3908 | &amdgpu_debugfs_regs_fops, | |
3909 | &amdgpu_debugfs_regs_didt_fops, | |
3910 | &amdgpu_debugfs_regs_pcie_fops, | |
3911 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3912 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3913 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3914 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3915 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3916 | }; |
3917 | ||
3918 | static const char *debugfs_regs_names[] = { | |
3919 | "amdgpu_regs", | |
3920 | "amdgpu_regs_didt", | |
3921 | "amdgpu_regs_pcie", | |
3922 | "amdgpu_regs_smc", | |
1e051413 | 3923 | "amdgpu_gca_config", |
f2cdaf20 | 3924 | "amdgpu_sensors", |
273d7aa1 | 3925 | "amdgpu_wave", |
c5a60ce8 | 3926 | "amdgpu_gpr", |
adcec288 | 3927 | }; |
d38ceaf9 AD |
3928 | |
3929 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3930 | { | |
3931 | struct drm_minor *minor = adev->ddev->primary; | |
3932 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3933 | unsigned i, j; |
3934 | ||
3935 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3936 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3937 | S_IFREG | S_IRUGO, root, | |
3938 | adev, debugfs_regs[i]); | |
3939 | if (IS_ERR(ent)) { | |
3940 | for (j = 0; j < i; j++) { | |
3941 | debugfs_remove(adev->debugfs_regs[i]); | |
3942 | adev->debugfs_regs[i] = NULL; | |
3943 | } | |
3944 | return PTR_ERR(ent); | |
3945 | } | |
d38ceaf9 | 3946 | |
adcec288 TSD |
3947 | if (!i) |
3948 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3949 | adev->debugfs_regs[i] = ent; | |
3950 | } | |
d38ceaf9 AD |
3951 | |
3952 | return 0; | |
3953 | } | |
3954 | ||
3955 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3956 | { | |
adcec288 TSD |
3957 | unsigned i; |
3958 | ||
3959 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3960 | if (adev->debugfs_regs[i]) { | |
3961 | debugfs_remove(adev->debugfs_regs[i]); | |
3962 | adev->debugfs_regs[i] = NULL; | |
3963 | } | |
3964 | } | |
d38ceaf9 AD |
3965 | } |
3966 | ||
4f0955fc HR |
3967 | static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) |
3968 | { | |
3969 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3970 | struct drm_device *dev = node->minor->dev; | |
3971 | struct amdgpu_device *adev = dev->dev_private; | |
3972 | int r = 0, i; | |
3973 | ||
3974 | /* hold on the scheduler */ | |
3975 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3976 | struct amdgpu_ring *ring = adev->rings[i]; | |
3977 | ||
3978 | if (!ring || !ring->sched.thread) | |
3979 | continue; | |
3980 | kthread_park(ring->sched.thread); | |
3981 | } | |
3982 | ||
3983 | seq_printf(m, "run ib test:\n"); | |
3984 | r = amdgpu_ib_ring_tests(adev); | |
3985 | if (r) | |
3986 | seq_printf(m, "ib ring tests failed (%d).\n", r); | |
3987 | else | |
3988 | seq_printf(m, "ib ring tests passed.\n"); | |
3989 | ||
3990 | /* go on the scheduler */ | |
3991 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3992 | struct amdgpu_ring *ring = adev->rings[i]; | |
3993 | ||
3994 | if (!ring || !ring->sched.thread) | |
3995 | continue; | |
3996 | kthread_unpark(ring->sched.thread); | |
3997 | } | |
3998 | ||
3999 | return 0; | |
4000 | } | |
4001 | ||
4002 | static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { | |
4003 | {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} | |
4004 | }; | |
4005 | ||
4006 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) | |
4007 | { | |
4008 | return amdgpu_debugfs_add_files(adev, | |
4009 | amdgpu_debugfs_test_ib_ring_list, 1); | |
4010 | } | |
4011 | ||
d38ceaf9 AD |
4012 | int amdgpu_debugfs_init(struct drm_minor *minor) |
4013 | { | |
4014 | return 0; | |
4015 | } | |
db95e218 KR |
4016 | |
4017 | static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) | |
4018 | { | |
4019 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
4020 | struct drm_device *dev = node->minor->dev; | |
4021 | struct amdgpu_device *adev = dev->dev_private; | |
4022 | ||
4023 | seq_write(m, adev->bios, adev->bios_size); | |
4024 | return 0; | |
4025 | } | |
4026 | ||
db95e218 KR |
4027 | static const struct drm_info_list amdgpu_vbios_dump_list[] = { |
4028 | {"amdgpu_vbios", | |
4029 | amdgpu_debugfs_get_vbios_dump, | |
4030 | 0, NULL}, | |
4031 | }; | |
4032 | ||
db95e218 KR |
4033 | static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) |
4034 | { | |
4035 | return amdgpu_debugfs_add_files(adev, | |
4036 | amdgpu_vbios_dump_list, 1); | |
4037 | } | |
7cebc728 | 4038 | #else |
27bad5b9 | 4039 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) |
4f0955fc HR |
4040 | { |
4041 | return 0; | |
4042 | } | |
7cebc728 AK |
4043 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) |
4044 | { | |
4045 | return 0; | |
4046 | } | |
db95e218 KR |
4047 | static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) |
4048 | { | |
4049 | return 0; | |
4050 | } | |
7cebc728 | 4051 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } |
d38ceaf9 | 4052 | #endif |