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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
e2a75f88 | 58 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 59 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 60 | |
2dc80b00 S |
61 | #define AMDGPU_RESUME_MS 2000 |
62 | ||
d38ceaf9 AD |
63 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
64 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
4f0955fc | 65 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); |
d38ceaf9 AD |
66 | |
67 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
68 | "TAHITI", |
69 | "PITCAIRN", | |
70 | "VERDE", | |
71 | "OLAND", | |
72 | "HAINAN", | |
d38ceaf9 AD |
73 | "BONAIRE", |
74 | "KAVERI", | |
75 | "KABINI", | |
76 | "HAWAII", | |
77 | "MULLINS", | |
78 | "TOPAZ", | |
79 | "TONGA", | |
48299f95 | 80 | "FIJI", |
d38ceaf9 | 81 | "CARRIZO", |
139f4917 | 82 | "STONEY", |
2cc0c0b5 FC |
83 | "POLARIS10", |
84 | "POLARIS11", | |
c4642a47 | 85 | "POLARIS12", |
d4196f01 | 86 | "VEGA10", |
2ca8a5d2 | 87 | "RAVEN", |
d38ceaf9 AD |
88 | "LAST", |
89 | }; | |
90 | ||
91 | bool amdgpu_device_is_px(struct drm_device *dev) | |
92 | { | |
93 | struct amdgpu_device *adev = dev->dev_private; | |
94 | ||
2f7d10b3 | 95 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
96 | return true; |
97 | return false; | |
98 | } | |
99 | ||
100 | /* | |
101 | * MMIO register access helper functions. | |
102 | */ | |
103 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 104 | uint32_t acc_flags) |
d38ceaf9 | 105 | { |
f4b373f4 TSD |
106 | uint32_t ret; |
107 | ||
15d72fd7 | 108 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
109 | BUG_ON(in_interrupt()); |
110 | return amdgpu_virt_kiq_rreg(adev, reg); | |
111 | } | |
112 | ||
15d72fd7 | 113 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 114 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
115 | else { |
116 | unsigned long flags; | |
d38ceaf9 AD |
117 | |
118 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
119 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
120 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
121 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 122 | } |
f4b373f4 TSD |
123 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
124 | return ret; | |
d38ceaf9 AD |
125 | } |
126 | ||
127 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 128 | uint32_t acc_flags) |
d38ceaf9 | 129 | { |
f4b373f4 | 130 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 131 | |
47ed4e1c KW |
132 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
133 | adev->last_mm_index = v; | |
134 | } | |
135 | ||
15d72fd7 | 136 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { |
bc992ba5 XY |
137 | BUG_ON(in_interrupt()); |
138 | return amdgpu_virt_kiq_wreg(adev, reg, v); | |
139 | } | |
140 | ||
15d72fd7 | 141 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
142 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
143 | else { | |
144 | unsigned long flags; | |
145 | ||
146 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
147 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
148 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
149 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
150 | } | |
47ed4e1c KW |
151 | |
152 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
153 | udelay(500); | |
154 | } | |
d38ceaf9 AD |
155 | } |
156 | ||
157 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
158 | { | |
159 | if ((reg * 4) < adev->rio_mem_size) | |
160 | return ioread32(adev->rio_mem + (reg * 4)); | |
161 | else { | |
162 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
163 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
164 | } | |
165 | } | |
166 | ||
167 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
168 | { | |
47ed4e1c KW |
169 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
170 | adev->last_mm_index = v; | |
171 | } | |
d38ceaf9 AD |
172 | |
173 | if ((reg * 4) < adev->rio_mem_size) | |
174 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
175 | else { | |
176 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
177 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
178 | } | |
47ed4e1c KW |
179 | |
180 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
181 | udelay(500); | |
182 | } | |
d38ceaf9 AD |
183 | } |
184 | ||
185 | /** | |
186 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
187 | * | |
188 | * @adev: amdgpu_device pointer | |
189 | * @index: doorbell index | |
190 | * | |
191 | * Returns the value in the doorbell aperture at the | |
192 | * requested doorbell index (CIK). | |
193 | */ | |
194 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
195 | { | |
196 | if (index < adev->doorbell.num_doorbells) { | |
197 | return readl(adev->doorbell.ptr + index); | |
198 | } else { | |
199 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
200 | return 0; | |
201 | } | |
202 | } | |
203 | ||
204 | /** | |
205 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
206 | * | |
207 | * @adev: amdgpu_device pointer | |
208 | * @index: doorbell index | |
209 | * @v: value to write | |
210 | * | |
211 | * Writes @v to the doorbell aperture at the | |
212 | * requested doorbell index (CIK). | |
213 | */ | |
214 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
215 | { | |
216 | if (index < adev->doorbell.num_doorbells) { | |
217 | writel(v, adev->doorbell.ptr + index); | |
218 | } else { | |
219 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
220 | } | |
221 | } | |
222 | ||
832be404 KW |
223 | /** |
224 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
225 | * | |
226 | * @adev: amdgpu_device pointer | |
227 | * @index: doorbell index | |
228 | * | |
229 | * Returns the value in the doorbell aperture at the | |
230 | * requested doorbell index (VEGA10+). | |
231 | */ | |
232 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
233 | { | |
234 | if (index < adev->doorbell.num_doorbells) { | |
235 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
236 | } else { | |
237 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
238 | return 0; | |
239 | } | |
240 | } | |
241 | ||
242 | /** | |
243 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
244 | * | |
245 | * @adev: amdgpu_device pointer | |
246 | * @index: doorbell index | |
247 | * @v: value to write | |
248 | * | |
249 | * Writes @v to the doorbell aperture at the | |
250 | * requested doorbell index (VEGA10+). | |
251 | */ | |
252 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
253 | { | |
254 | if (index < adev->doorbell.num_doorbells) { | |
255 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
256 | } else { | |
257 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
258 | } | |
259 | } | |
260 | ||
d38ceaf9 AD |
261 | /** |
262 | * amdgpu_invalid_rreg - dummy reg read function | |
263 | * | |
264 | * @adev: amdgpu device pointer | |
265 | * @reg: offset of register | |
266 | * | |
267 | * Dummy register read function. Used for register blocks | |
268 | * that certain asics don't have (all asics). | |
269 | * Returns the value in the register. | |
270 | */ | |
271 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
272 | { | |
273 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
274 | BUG(); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /** | |
279 | * amdgpu_invalid_wreg - dummy reg write function | |
280 | * | |
281 | * @adev: amdgpu device pointer | |
282 | * @reg: offset of register | |
283 | * @v: value to write to the register | |
284 | * | |
285 | * Dummy register read function. Used for register blocks | |
286 | * that certain asics don't have (all asics). | |
287 | */ | |
288 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
289 | { | |
290 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
291 | reg, v); | |
292 | BUG(); | |
293 | } | |
294 | ||
295 | /** | |
296 | * amdgpu_block_invalid_rreg - dummy reg read function | |
297 | * | |
298 | * @adev: amdgpu device pointer | |
299 | * @block: offset of instance | |
300 | * @reg: offset of register | |
301 | * | |
302 | * Dummy register read function. Used for register blocks | |
303 | * that certain asics don't have (all asics). | |
304 | * Returns the value in the register. | |
305 | */ | |
306 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
307 | uint32_t block, uint32_t reg) | |
308 | { | |
309 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
310 | reg, block); | |
311 | BUG(); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | /** | |
316 | * amdgpu_block_invalid_wreg - dummy reg write function | |
317 | * | |
318 | * @adev: amdgpu device pointer | |
319 | * @block: offset of instance | |
320 | * @reg: offset of register | |
321 | * @v: value to write to the register | |
322 | * | |
323 | * Dummy register read function. Used for register blocks | |
324 | * that certain asics don't have (all asics). | |
325 | */ | |
326 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
327 | uint32_t block, | |
328 | uint32_t reg, uint32_t v) | |
329 | { | |
330 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
331 | reg, block, v); | |
332 | BUG(); | |
333 | } | |
334 | ||
335 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
336 | { | |
337 | int r; | |
338 | ||
339 | if (adev->vram_scratch.robj == NULL) { | |
340 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 341 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
342 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
343 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 344 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
345 | if (r) { |
346 | return r; | |
347 | } | |
348 | } | |
349 | ||
350 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
351 | if (unlikely(r != 0)) | |
352 | return r; | |
353 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
354 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
355 | if (r) { | |
356 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
357 | return r; | |
358 | } | |
359 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
360 | (void **)&adev->vram_scratch.ptr); | |
361 | if (r) | |
362 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
363 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
364 | ||
365 | return r; | |
366 | } | |
367 | ||
368 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
369 | { | |
370 | int r; | |
371 | ||
372 | if (adev->vram_scratch.robj == NULL) { | |
373 | return; | |
374 | } | |
8ab25b4f | 375 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, true); |
d38ceaf9 AD |
376 | if (likely(r == 0)) { |
377 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
378 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
379 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
380 | } | |
381 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
382 | } | |
383 | ||
384 | /** | |
385 | * amdgpu_program_register_sequence - program an array of registers. | |
386 | * | |
387 | * @adev: amdgpu_device pointer | |
388 | * @registers: pointer to the register array | |
389 | * @array_size: size of the register array | |
390 | * | |
391 | * Programs an array or registers with and and or masks. | |
392 | * This is a helper for setting golden registers. | |
393 | */ | |
394 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
395 | const u32 *registers, | |
396 | const u32 array_size) | |
397 | { | |
398 | u32 tmp, reg, and_mask, or_mask; | |
399 | int i; | |
400 | ||
401 | if (array_size % 3) | |
402 | return; | |
403 | ||
404 | for (i = 0; i < array_size; i +=3) { | |
405 | reg = registers[i + 0]; | |
406 | and_mask = registers[i + 1]; | |
407 | or_mask = registers[i + 2]; | |
408 | ||
409 | if (and_mask == 0xffffffff) { | |
410 | tmp = or_mask; | |
411 | } else { | |
412 | tmp = RREG32(reg); | |
413 | tmp &= ~and_mask; | |
414 | tmp |= or_mask; | |
415 | } | |
416 | WREG32(reg, tmp); | |
417 | } | |
418 | } | |
419 | ||
420 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
421 | { | |
422 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
423 | } | |
424 | ||
425 | /* | |
426 | * GPU doorbell aperture helpers function. | |
427 | */ | |
428 | /** | |
429 | * amdgpu_doorbell_init - Init doorbell driver information. | |
430 | * | |
431 | * @adev: amdgpu_device pointer | |
432 | * | |
433 | * Init doorbell driver information (CIK) | |
434 | * Returns 0 on success, error on failure. | |
435 | */ | |
436 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
437 | { | |
438 | /* doorbell bar mapping */ | |
439 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
440 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
441 | ||
edf600da | 442 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
443 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
444 | if (adev->doorbell.num_doorbells == 0) | |
445 | return -EINVAL; | |
446 | ||
8972e5d2 CK |
447 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
448 | adev->doorbell.num_doorbells * | |
449 | sizeof(u32)); | |
450 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 451 | return -ENOMEM; |
d38ceaf9 AD |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
456 | /** | |
457 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
458 | * | |
459 | * @adev: amdgpu_device pointer | |
460 | * | |
461 | * Tear down doorbell driver information (CIK) | |
462 | */ | |
463 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
464 | { | |
465 | iounmap(adev->doorbell.ptr); | |
466 | adev->doorbell.ptr = NULL; | |
467 | } | |
468 | ||
469 | /** | |
470 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
471 | * setup amdkfd | |
472 | * | |
473 | * @adev: amdgpu_device pointer | |
474 | * @aperture_base: output returning doorbell aperture base physical address | |
475 | * @aperture_size: output returning doorbell aperture size in bytes | |
476 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
477 | * | |
478 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
479 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
480 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
481 | */ | |
482 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
483 | phys_addr_t *aperture_base, | |
484 | size_t *aperture_size, | |
485 | size_t *start_offset) | |
486 | { | |
487 | /* | |
488 | * The first num_doorbells are used by amdgpu. | |
489 | * amdkfd takes whatever's left in the aperture. | |
490 | */ | |
491 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
492 | *aperture_base = adev->doorbell.base; | |
493 | *aperture_size = adev->doorbell.size; | |
494 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
495 | } else { | |
496 | *aperture_base = 0; | |
497 | *aperture_size = 0; | |
498 | *start_offset = 0; | |
499 | } | |
500 | } | |
501 | ||
502 | /* | |
503 | * amdgpu_wb_*() | |
455a7bc2 | 504 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 505 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
506 | */ |
507 | ||
508 | /** | |
509 | * amdgpu_wb_fini - Disable Writeback and free memory | |
510 | * | |
511 | * @adev: amdgpu_device pointer | |
512 | * | |
513 | * Disables Writeback and frees the Writeback memory (all asics). | |
514 | * Used at driver shutdown. | |
515 | */ | |
516 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
517 | { | |
518 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
519 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
520 | &adev->wb.gpu_addr, | |
521 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
522 | adev->wb.wb_obj = NULL; |
523 | } | |
524 | } | |
525 | ||
526 | /** | |
527 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
528 | * | |
529 | * @adev: amdgpu_device pointer | |
530 | * | |
455a7bc2 | 531 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
532 | * Used at driver startup. |
533 | * Returns 0 on success or an -error on failure. | |
534 | */ | |
535 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
536 | { | |
537 | int r; | |
538 | ||
539 | if (adev->wb.wb_obj == NULL) { | |
60a970a6 | 540 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), |
a76ed485 AD |
541 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
542 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
543 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
544 | if (r) { |
545 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
546 | return r; | |
547 | } | |
d38ceaf9 AD |
548 | |
549 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
550 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
551 | ||
552 | /* clear wb memory */ | |
60a970a6 | 553 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
554 | } |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
559 | /** | |
560 | * amdgpu_wb_get - Allocate a wb entry | |
561 | * | |
562 | * @adev: amdgpu_device pointer | |
563 | * @wb: wb index | |
564 | * | |
565 | * Allocate a wb slot for use by the driver (all asics). | |
566 | * Returns 0 on success or -EINVAL on failure. | |
567 | */ | |
568 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
569 | { | |
570 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
571 | if (offset < adev->wb.num_wb) { | |
572 | __set_bit(offset, adev->wb.used); | |
573 | *wb = offset; | |
574 | return 0; | |
575 | } else { | |
576 | return -EINVAL; | |
577 | } | |
578 | } | |
579 | ||
7014285a KW |
580 | /** |
581 | * amdgpu_wb_get_64bit - Allocate a wb entry | |
582 | * | |
583 | * @adev: amdgpu_device pointer | |
584 | * @wb: wb index | |
585 | * | |
586 | * Allocate a wb slot for use by the driver (all asics). | |
587 | * Returns 0 on success or -EINVAL on failure. | |
588 | */ | |
589 | int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) | |
590 | { | |
591 | unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, | |
592 | adev->wb.num_wb, 0, 2, 7, 0); | |
593 | if ((offset + 1) < adev->wb.num_wb) { | |
594 | __set_bit(offset, adev->wb.used); | |
595 | __set_bit(offset + 1, adev->wb.used); | |
596 | *wb = offset; | |
597 | return 0; | |
598 | } else { | |
599 | return -EINVAL; | |
600 | } | |
601 | } | |
602 | ||
d38ceaf9 AD |
603 | /** |
604 | * amdgpu_wb_free - Free a wb entry | |
605 | * | |
606 | * @adev: amdgpu_device pointer | |
607 | * @wb: wb index | |
608 | * | |
609 | * Free a wb slot allocated for use by the driver (all asics) | |
610 | */ | |
611 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
612 | { | |
613 | if (wb < adev->wb.num_wb) | |
614 | __clear_bit(wb, adev->wb.used); | |
615 | } | |
616 | ||
7014285a KW |
617 | /** |
618 | * amdgpu_wb_free_64bit - Free a wb entry | |
619 | * | |
620 | * @adev: amdgpu_device pointer | |
621 | * @wb: wb index | |
622 | * | |
623 | * Free a wb slot allocated for use by the driver (all asics) | |
624 | */ | |
625 | void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) | |
626 | { | |
627 | if ((wb + 1) < adev->wb.num_wb) { | |
628 | __clear_bit(wb, adev->wb.used); | |
629 | __clear_bit(wb + 1, adev->wb.used); | |
630 | } | |
631 | } | |
632 | ||
d38ceaf9 AD |
633 | /** |
634 | * amdgpu_vram_location - try to find VRAM location | |
635 | * @adev: amdgpu device structure holding all necessary informations | |
636 | * @mc: memory controller structure holding memory informations | |
637 | * @base: base address at which to put VRAM | |
638 | * | |
455a7bc2 | 639 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
640 | * as parameter (which is so far either PCI aperture address or |
641 | * for IGP TOM base address). | |
642 | * | |
643 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
644 | * address space then we limit the VRAM size to the aperture. | |
645 | * | |
646 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
647 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
648 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
649 | * not IGP. | |
650 | * | |
651 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
652 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
653 | * Novell bug 204882 + along with lots of ubuntu ones | |
654 | * | |
655 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
656 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
657 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
658 | * ones) | |
659 | * | |
660 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 661 | * explicitly check for that though. |
d38ceaf9 AD |
662 | * |
663 | * FIXME: when reducing VRAM size align new size on power of 2. | |
664 | */ | |
665 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
666 | { | |
667 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
668 | ||
669 | mc->vram_start = base; | |
670 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
671 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
672 | mc->real_vram_size = mc->aper_size; | |
673 | mc->mc_vram_size = mc->aper_size; | |
674 | } | |
675 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
676 | if (limit && limit < mc->real_vram_size) | |
677 | mc->real_vram_size = limit; | |
678 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
679 | mc->mc_vram_size >> 20, mc->vram_start, | |
680 | mc->vram_end, mc->real_vram_size >> 20); | |
681 | } | |
682 | ||
683 | /** | |
684 | * amdgpu_gtt_location - try to find GTT location | |
685 | * @adev: amdgpu device structure holding all necessary informations | |
686 | * @mc: memory controller structure holding memory informations | |
687 | * | |
688 | * Function will place try to place GTT before or after VRAM. | |
689 | * | |
690 | * If GTT size is bigger than space left then we ajust GTT size. | |
691 | * Thus function will never fails. | |
692 | * | |
693 | * FIXME: when reducing GTT size align new size on power of 2. | |
694 | */ | |
695 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
696 | { | |
697 | u64 size_af, size_bf; | |
698 | ||
699 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
700 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
701 | if (size_bf > size_af) { | |
702 | if (mc->gtt_size > size_bf) { | |
703 | dev_warn(adev->dev, "limiting GTT\n"); | |
704 | mc->gtt_size = size_bf; | |
705 | } | |
9dc5a91e | 706 | mc->gtt_start = 0; |
d38ceaf9 AD |
707 | } else { |
708 | if (mc->gtt_size > size_af) { | |
709 | dev_warn(adev->dev, "limiting GTT\n"); | |
710 | mc->gtt_size = size_af; | |
711 | } | |
712 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
713 | } | |
714 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
715 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
716 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
717 | } | |
718 | ||
719 | /* | |
720 | * GPU helpers function. | |
721 | */ | |
722 | /** | |
c836fec5 | 723 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
724 | * |
725 | * @adev: amdgpu_device pointer | |
726 | * | |
c836fec5 JQ |
727 | * Check if the asic has been initialized (all asics) at driver startup |
728 | * or post is needed if hw reset is performed. | |
729 | * Returns true if need or false if not. | |
d38ceaf9 | 730 | */ |
c836fec5 | 731 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
732 | { |
733 | uint32_t reg; | |
734 | ||
c836fec5 JQ |
735 | if (adev->has_hw_reset) { |
736 | adev->has_hw_reset = false; | |
737 | return true; | |
738 | } | |
d38ceaf9 | 739 | /* then check MEM_SIZE, in case the crtcs are off */ |
bbf282d8 | 740 | reg = amdgpu_asic_get_config_memsize(adev); |
d38ceaf9 | 741 | |
f2713e8c | 742 | if ((reg != 0) && (reg != 0xffffffff)) |
c836fec5 | 743 | return false; |
d38ceaf9 | 744 | |
c836fec5 | 745 | return true; |
d38ceaf9 AD |
746 | |
747 | } | |
748 | ||
bec86378 ML |
749 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
750 | { | |
751 | if (amdgpu_sriov_vf(adev)) | |
752 | return false; | |
753 | ||
754 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
755 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
756 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
757 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
758 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
759 | */ |
760 | if (adev->asic_type == CHIP_FIJI) { | |
761 | int err; | |
762 | uint32_t fw_ver; | |
763 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
764 | /* force vPost if error occured */ | |
765 | if (err) | |
766 | return true; | |
767 | ||
768 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
769 | if (fw_ver < 0x00160e00) |
770 | return true; | |
bec86378 | 771 | } |
bec86378 | 772 | } |
c836fec5 | 773 | return amdgpu_need_post(adev); |
bec86378 ML |
774 | } |
775 | ||
d38ceaf9 AD |
776 | /** |
777 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
778 | * | |
779 | * @adev: amdgpu_device pointer | |
780 | * | |
781 | * Allocate the dummy page used by the driver (all asics). | |
782 | * This dummy page is used by the driver as a filler for gart entries | |
783 | * when pages are taken out of the GART | |
784 | * Returns 0 on sucess, -ENOMEM on failure. | |
785 | */ | |
786 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
787 | { | |
788 | if (adev->dummy_page.page) | |
789 | return 0; | |
790 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
791 | if (adev->dummy_page.page == NULL) | |
792 | return -ENOMEM; | |
793 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
794 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
795 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
796 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
797 | __free_page(adev->dummy_page.page); | |
798 | adev->dummy_page.page = NULL; | |
799 | return -ENOMEM; | |
800 | } | |
801 | return 0; | |
802 | } | |
803 | ||
804 | /** | |
805 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
806 | * | |
807 | * @adev: amdgpu_device pointer | |
808 | * | |
809 | * Frees the dummy page used by the driver (all asics). | |
810 | */ | |
811 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
812 | { | |
813 | if (adev->dummy_page.page == NULL) | |
814 | return; | |
815 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
816 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
817 | __free_page(adev->dummy_page.page); | |
818 | adev->dummy_page.page = NULL; | |
819 | } | |
820 | ||
821 | ||
822 | /* ATOM accessor methods */ | |
823 | /* | |
824 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
825 | * driver registers callbacks to access registers and the interpreter | |
826 | * in the driver parses the tables and executes then to program specific | |
827 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
828 | * atombios.h, and atom.c | |
829 | */ | |
830 | ||
831 | /** | |
832 | * cail_pll_read - read PLL register | |
833 | * | |
834 | * @info: atom card_info pointer | |
835 | * @reg: PLL register offset | |
836 | * | |
837 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
838 | * Returns the value of the PLL register. | |
839 | */ | |
840 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
841 | { | |
842 | return 0; | |
843 | } | |
844 | ||
845 | /** | |
846 | * cail_pll_write - write PLL register | |
847 | * | |
848 | * @info: atom card_info pointer | |
849 | * @reg: PLL register offset | |
850 | * @val: value to write to the pll register | |
851 | * | |
852 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
853 | */ | |
854 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
855 | { | |
856 | ||
857 | } | |
858 | ||
859 | /** | |
860 | * cail_mc_read - read MC (Memory Controller) register | |
861 | * | |
862 | * @info: atom card_info pointer | |
863 | * @reg: MC register offset | |
864 | * | |
865 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
866 | * Returns the value of the MC register. | |
867 | */ | |
868 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
869 | { | |
870 | return 0; | |
871 | } | |
872 | ||
873 | /** | |
874 | * cail_mc_write - write MC (Memory Controller) register | |
875 | * | |
876 | * @info: atom card_info pointer | |
877 | * @reg: MC register offset | |
878 | * @val: value to write to the pll register | |
879 | * | |
880 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
881 | */ | |
882 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
883 | { | |
884 | ||
885 | } | |
886 | ||
887 | /** | |
888 | * cail_reg_write - write MMIO register | |
889 | * | |
890 | * @info: atom card_info pointer | |
891 | * @reg: MMIO register offset | |
892 | * @val: value to write to the pll register | |
893 | * | |
894 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
895 | */ | |
896 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
897 | { | |
898 | struct amdgpu_device *adev = info->dev->dev_private; | |
899 | ||
900 | WREG32(reg, val); | |
901 | } | |
902 | ||
903 | /** | |
904 | * cail_reg_read - read MMIO register | |
905 | * | |
906 | * @info: atom card_info pointer | |
907 | * @reg: MMIO register offset | |
908 | * | |
909 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
910 | * Returns the value of the MMIO register. | |
911 | */ | |
912 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
913 | { | |
914 | struct amdgpu_device *adev = info->dev->dev_private; | |
915 | uint32_t r; | |
916 | ||
917 | r = RREG32(reg); | |
918 | return r; | |
919 | } | |
920 | ||
921 | /** | |
922 | * cail_ioreg_write - write IO register | |
923 | * | |
924 | * @info: atom card_info pointer | |
925 | * @reg: IO register offset | |
926 | * @val: value to write to the pll register | |
927 | * | |
928 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
929 | */ | |
930 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
931 | { | |
932 | struct amdgpu_device *adev = info->dev->dev_private; | |
933 | ||
934 | WREG32_IO(reg, val); | |
935 | } | |
936 | ||
937 | /** | |
938 | * cail_ioreg_read - read IO register | |
939 | * | |
940 | * @info: atom card_info pointer | |
941 | * @reg: IO register offset | |
942 | * | |
943 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
944 | * Returns the value of the IO register. | |
945 | */ | |
946 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
947 | { | |
948 | struct amdgpu_device *adev = info->dev->dev_private; | |
949 | uint32_t r; | |
950 | ||
951 | r = RREG32_IO(reg); | |
952 | return r; | |
953 | } | |
954 | ||
955 | /** | |
956 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
957 | * | |
958 | * @adev: amdgpu_device pointer | |
959 | * | |
960 | * Frees the driver info and register access callbacks for the ATOM | |
961 | * interpreter (r4xx+). | |
962 | * Called at driver shutdown. | |
963 | */ | |
964 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
965 | { | |
89e0ec9f | 966 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 967 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
968 | kfree(adev->mode_info.atom_context->iio); |
969 | } | |
d38ceaf9 AD |
970 | kfree(adev->mode_info.atom_context); |
971 | adev->mode_info.atom_context = NULL; | |
972 | kfree(adev->mode_info.atom_card_info); | |
973 | adev->mode_info.atom_card_info = NULL; | |
974 | } | |
975 | ||
976 | /** | |
977 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
978 | * | |
979 | * @adev: amdgpu_device pointer | |
980 | * | |
981 | * Initializes the driver info and register access callbacks for the | |
982 | * ATOM interpreter (r4xx+). | |
983 | * Returns 0 on sucess, -ENOMEM on failure. | |
984 | * Called at driver startup. | |
985 | */ | |
986 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
987 | { | |
988 | struct card_info *atom_card_info = | |
989 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
990 | ||
991 | if (!atom_card_info) | |
992 | return -ENOMEM; | |
993 | ||
994 | adev->mode_info.atom_card_info = atom_card_info; | |
995 | atom_card_info->dev = adev->ddev; | |
996 | atom_card_info->reg_read = cail_reg_read; | |
997 | atom_card_info->reg_write = cail_reg_write; | |
998 | /* needed for iio ops */ | |
999 | if (adev->rio_mem) { | |
1000 | atom_card_info->ioreg_read = cail_ioreg_read; | |
1001 | atom_card_info->ioreg_write = cail_ioreg_write; | |
1002 | } else { | |
b64a18c5 | 1003 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
1004 | atom_card_info->ioreg_read = cail_reg_read; |
1005 | atom_card_info->ioreg_write = cail_reg_write; | |
1006 | } | |
1007 | atom_card_info->mc_read = cail_mc_read; | |
1008 | atom_card_info->mc_write = cail_mc_write; | |
1009 | atom_card_info->pll_read = cail_pll_read; | |
1010 | atom_card_info->pll_write = cail_pll_write; | |
1011 | ||
1012 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
1013 | if (!adev->mode_info.atom_context) { | |
1014 | amdgpu_atombios_fini(adev); | |
1015 | return -ENOMEM; | |
1016 | } | |
1017 | ||
1018 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1019 | if (adev->is_atom_fw) { |
1020 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1021 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1022 | } else { | |
1023 | amdgpu_atombios_scratch_regs_init(adev); | |
1024 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1025 | } | |
d38ceaf9 AD |
1026 | return 0; |
1027 | } | |
1028 | ||
1029 | /* if we get transitioned to only one device, take VGA back */ | |
1030 | /** | |
1031 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1032 | * | |
1033 | * @cookie: amdgpu_device pointer | |
1034 | * @state: enable/disable vga decode | |
1035 | * | |
1036 | * Enable/disable vga decode (all asics). | |
1037 | * Returns VGA resource flags. | |
1038 | */ | |
1039 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1040 | { | |
1041 | struct amdgpu_device *adev = cookie; | |
1042 | amdgpu_asic_set_vga_state(adev, state); | |
1043 | if (state) | |
1044 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1045 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1046 | else | |
1047 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1048 | } | |
1049 | ||
bab4fee7 | 1050 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1051 | { |
1052 | /* defines number of bits in page table versus page directory, | |
1053 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1054 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1055 | if (amdgpu_vm_block_size == -1) |
1056 | return; | |
a1adf8be | 1057 | |
bab4fee7 | 1058 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1059 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1060 | amdgpu_vm_block_size); | |
bab4fee7 | 1061 | goto def_value; |
a1adf8be CZ |
1062 | } |
1063 | ||
1064 | if (amdgpu_vm_block_size > 24 || | |
1065 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1066 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1067 | amdgpu_vm_block_size); | |
bab4fee7 | 1068 | goto def_value; |
a1adf8be | 1069 | } |
bab4fee7 JZ |
1070 | |
1071 | return; | |
1072 | ||
1073 | def_value: | |
1074 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1075 | } |
1076 | ||
83ca145d ZJ |
1077 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1078 | { | |
64dab074 AD |
1079 | /* no need to check the default value */ |
1080 | if (amdgpu_vm_size == -1) | |
1081 | return; | |
1082 | ||
76117507 | 1083 | if (!is_power_of_2(amdgpu_vm_size)) { |
83ca145d ZJ |
1084 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", |
1085 | amdgpu_vm_size); | |
1086 | goto def_value; | |
1087 | } | |
1088 | ||
1089 | if (amdgpu_vm_size < 1) { | |
1090 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1091 | amdgpu_vm_size); | |
1092 | goto def_value; | |
1093 | } | |
1094 | ||
1095 | /* | |
1096 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1097 | */ | |
1098 | if (amdgpu_vm_size > 1024) { | |
1099 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1100 | amdgpu_vm_size); | |
1101 | goto def_value; | |
1102 | } | |
1103 | ||
1104 | return; | |
1105 | ||
1106 | def_value: | |
bab4fee7 | 1107 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1108 | } |
1109 | ||
d38ceaf9 AD |
1110 | /** |
1111 | * amdgpu_check_arguments - validate module params | |
1112 | * | |
1113 | * @adev: amdgpu_device pointer | |
1114 | * | |
1115 | * Validates certain module parameters and updates | |
1116 | * the associated values used by the driver (all asics). | |
1117 | */ | |
1118 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1119 | { | |
5b011235 CZ |
1120 | if (amdgpu_sched_jobs < 4) { |
1121 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1122 | amdgpu_sched_jobs); | |
1123 | amdgpu_sched_jobs = 4; | |
76117507 | 1124 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1125 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1126 | amdgpu_sched_jobs); | |
1127 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1128 | } | |
d38ceaf9 AD |
1129 | |
1130 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 1131 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
1132 | if (amdgpu_gart_size < 32) { |
1133 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1134 | amdgpu_gart_size); | |
1135 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
1136 | } |
1137 | } | |
1138 | ||
83ca145d | 1139 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1140 | |
bab4fee7 | 1141 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1142 | |
526bae37 | 1143 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1144 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1145 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1146 | amdgpu_vram_page_split); | |
1147 | amdgpu_vram_page_split = 1024; | |
1148 | } | |
d38ceaf9 AD |
1149 | } |
1150 | ||
1151 | /** | |
1152 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1153 | * | |
1154 | * @pdev: pci dev pointer | |
1694467b | 1155 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1156 | * |
1157 | * Callback for the switcheroo driver. Suspends or resumes the | |
1158 | * the asics before or after it is powered up using ACPI methods. | |
1159 | */ | |
1160 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1161 | { | |
1162 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1163 | ||
1164 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1165 | return; | |
1166 | ||
1167 | if (state == VGA_SWITCHEROO_ON) { | |
1168 | unsigned d3_delay = dev->pdev->d3_delay; | |
1169 | ||
7ca85295 | 1170 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1171 | /* don't suspend or resume card normally */ |
1172 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1173 | ||
810ddc3a | 1174 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1175 | |
1176 | dev->pdev->d3_delay = d3_delay; | |
1177 | ||
1178 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1179 | drm_kms_helper_poll_enable(dev); | |
1180 | } else { | |
7ca85295 | 1181 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1182 | drm_kms_helper_poll_disable(dev); |
1183 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1184 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1185 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1186 | } | |
1187 | } | |
1188 | ||
1189 | /** | |
1190 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1191 | * | |
1192 | * @pdev: pci dev pointer | |
1193 | * | |
1194 | * Callback for the switcheroo driver. Check of the switcheroo | |
1195 | * state can be changed. | |
1196 | * Returns true if the state can be changed, false if not. | |
1197 | */ | |
1198 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1199 | { | |
1200 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1201 | ||
1202 | /* | |
1203 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1204 | * locking inversion with the driver load path. And the access here is | |
1205 | * completely racy anyway. So don't bother with locking for now. | |
1206 | */ | |
1207 | return dev->open_count == 0; | |
1208 | } | |
1209 | ||
1210 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1211 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1212 | .reprobe = NULL, | |
1213 | .can_switch = amdgpu_switcheroo_can_switch, | |
1214 | }; | |
1215 | ||
1216 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1217 | enum amd_ip_block_type block_type, |
1218 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1219 | { |
1220 | int i, r = 0; | |
1221 | ||
1222 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1223 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1224 | continue; |
c722865a RZ |
1225 | if (adev->ip_blocks[i].version->type != block_type) |
1226 | continue; | |
1227 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1228 | continue; | |
1229 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1230 | (void *)adev, state); | |
1231 | if (r) | |
1232 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1233 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1234 | } |
1235 | return r; | |
1236 | } | |
1237 | ||
1238 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1239 | enum amd_ip_block_type block_type, |
1240 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1241 | { |
1242 | int i, r = 0; | |
1243 | ||
1244 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1245 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1246 | continue; |
c722865a RZ |
1247 | if (adev->ip_blocks[i].version->type != block_type) |
1248 | continue; | |
1249 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1250 | continue; | |
1251 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1252 | (void *)adev, state); | |
1253 | if (r) | |
1254 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1255 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1256 | } |
1257 | return r; | |
1258 | } | |
1259 | ||
6cb2d4e4 HR |
1260 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1261 | { | |
1262 | int i; | |
1263 | ||
1264 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1265 | if (!adev->ip_blocks[i].status.valid) | |
1266 | continue; | |
1267 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1268 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1269 | } | |
1270 | } | |
1271 | ||
5dbbb60b AD |
1272 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1273 | enum amd_ip_block_type block_type) | |
1274 | { | |
1275 | int i, r; | |
1276 | ||
1277 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1278 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1279 | continue; |
a1255107 AD |
1280 | if (adev->ip_blocks[i].version->type == block_type) { |
1281 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1282 | if (r) |
1283 | return r; | |
1284 | break; | |
1285 | } | |
1286 | } | |
1287 | return 0; | |
1288 | ||
1289 | } | |
1290 | ||
1291 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1292 | enum amd_ip_block_type block_type) | |
1293 | { | |
1294 | int i; | |
1295 | ||
1296 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1297 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1298 | continue; |
a1255107 AD |
1299 | if (adev->ip_blocks[i].version->type == block_type) |
1300 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1301 | } |
1302 | return true; | |
1303 | ||
1304 | } | |
1305 | ||
a1255107 AD |
1306 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1307 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1308 | { |
1309 | int i; | |
1310 | ||
1311 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1312 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1313 | return &adev->ip_blocks[i]; |
1314 | ||
1315 | return NULL; | |
1316 | } | |
1317 | ||
1318 | /** | |
1319 | * amdgpu_ip_block_version_cmp | |
1320 | * | |
1321 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1322 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1323 | * @major: major version |
1324 | * @minor: minor version | |
1325 | * | |
1326 | * return 0 if equal or greater | |
1327 | * return 1 if smaller or the ip_block doesn't exist | |
1328 | */ | |
1329 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1330 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1331 | u32 major, u32 minor) |
1332 | { | |
a1255107 | 1333 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1334 | |
a1255107 AD |
1335 | if (ip_block && ((ip_block->version->major > major) || |
1336 | ((ip_block->version->major == major) && | |
1337 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1338 | return 0; |
1339 | ||
1340 | return 1; | |
1341 | } | |
1342 | ||
a1255107 AD |
1343 | /** |
1344 | * amdgpu_ip_block_add | |
1345 | * | |
1346 | * @adev: amdgpu_device pointer | |
1347 | * @ip_block_version: pointer to the IP to add | |
1348 | * | |
1349 | * Adds the IP block driver information to the collection of IPs | |
1350 | * on the asic. | |
1351 | */ | |
1352 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1353 | const struct amdgpu_ip_block_version *ip_block_version) | |
1354 | { | |
1355 | if (!ip_block_version) | |
1356 | return -EINVAL; | |
1357 | ||
a0bae357 HR |
1358 | DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, |
1359 | ip_block_version->funcs->name); | |
1360 | ||
a1255107 AD |
1361 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
483ef985 | 1366 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1367 | { |
1368 | adev->enable_virtual_display = false; | |
1369 | ||
1370 | if (amdgpu_virtual_display) { | |
1371 | struct drm_device *ddev = adev->ddev; | |
1372 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1373 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1374 | |
1375 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1376 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1377 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1378 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1379 | if (!strcmp("all", pciaddname) |
1380 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1381 | long num_crtc; |
1382 | int res = -1; | |
1383 | ||
9accf2fd | 1384 | adev->enable_virtual_display = true; |
0f66356d ED |
1385 | |
1386 | if (pciaddname_tmp) | |
1387 | res = kstrtol(pciaddname_tmp, 10, | |
1388 | &num_crtc); | |
1389 | ||
1390 | if (!res) { | |
1391 | if (num_crtc < 1) | |
1392 | num_crtc = 1; | |
1393 | if (num_crtc > 6) | |
1394 | num_crtc = 6; | |
1395 | adev->mode_info.num_crtc = num_crtc; | |
1396 | } else { | |
1397 | adev->mode_info.num_crtc = 1; | |
1398 | } | |
9accf2fd ED |
1399 | break; |
1400 | } | |
1401 | } | |
1402 | ||
0f66356d ED |
1403 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1404 | amdgpu_virtual_display, pci_address_name, | |
1405 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1406 | |
1407 | kfree(pciaddstr); | |
1408 | } | |
1409 | } | |
1410 | ||
e2a75f88 AD |
1411 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1412 | { | |
e2a75f88 AD |
1413 | const char *chip_name; |
1414 | char fw_name[30]; | |
1415 | int err; | |
1416 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1417 | ||
ab4fe3e1 HR |
1418 | adev->firmware.gpu_info_fw = NULL; |
1419 | ||
e2a75f88 AD |
1420 | switch (adev->asic_type) { |
1421 | case CHIP_TOPAZ: | |
1422 | case CHIP_TONGA: | |
1423 | case CHIP_FIJI: | |
1424 | case CHIP_POLARIS11: | |
1425 | case CHIP_POLARIS10: | |
1426 | case CHIP_POLARIS12: | |
1427 | case CHIP_CARRIZO: | |
1428 | case CHIP_STONEY: | |
1429 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1430 | case CHIP_VERDE: | |
1431 | case CHIP_TAHITI: | |
1432 | case CHIP_PITCAIRN: | |
1433 | case CHIP_OLAND: | |
1434 | case CHIP_HAINAN: | |
1435 | #endif | |
1436 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1437 | case CHIP_BONAIRE: | |
1438 | case CHIP_HAWAII: | |
1439 | case CHIP_KAVERI: | |
1440 | case CHIP_KABINI: | |
1441 | case CHIP_MULLINS: | |
1442 | #endif | |
1443 | default: | |
1444 | return 0; | |
1445 | case CHIP_VEGA10: | |
1446 | chip_name = "vega10"; | |
1447 | break; | |
2d2e5e7e AD |
1448 | case CHIP_RAVEN: |
1449 | chip_name = "raven"; | |
1450 | break; | |
e2a75f88 AD |
1451 | } |
1452 | ||
1453 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1454 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1455 | if (err) { |
1456 | dev_err(adev->dev, | |
1457 | "Failed to load gpu_info firmware \"%s\"\n", | |
1458 | fw_name); | |
1459 | goto out; | |
1460 | } | |
ab4fe3e1 | 1461 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1462 | if (err) { |
1463 | dev_err(adev->dev, | |
1464 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1465 | fw_name); | |
1466 | goto out; | |
1467 | } | |
1468 | ||
ab4fe3e1 | 1469 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1470 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1471 | ||
1472 | switch (hdr->version_major) { | |
1473 | case 1: | |
1474 | { | |
1475 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1476 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1477 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1478 | ||
b5ab16bf AD |
1479 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1480 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1481 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1482 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1483 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1484 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1485 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1486 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1487 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1488 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1489 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1490 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1491 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1492 | adev->gfx.cu_info.max_waves_per_simd = |
1493 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1494 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1495 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1496 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1497 | break; |
1498 | } | |
1499 | default: | |
1500 | dev_err(adev->dev, | |
1501 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1502 | err = -EINVAL; | |
1503 | goto out; | |
1504 | } | |
1505 | out: | |
e2a75f88 AD |
1506 | return err; |
1507 | } | |
1508 | ||
d38ceaf9 AD |
1509 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1510 | { | |
aaa36a97 | 1511 | int i, r; |
d38ceaf9 | 1512 | |
483ef985 | 1513 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1514 | |
d38ceaf9 | 1515 | switch (adev->asic_type) { |
aaa36a97 AD |
1516 | case CHIP_TOPAZ: |
1517 | case CHIP_TONGA: | |
48299f95 | 1518 | case CHIP_FIJI: |
2cc0c0b5 FC |
1519 | case CHIP_POLARIS11: |
1520 | case CHIP_POLARIS10: | |
c4642a47 | 1521 | case CHIP_POLARIS12: |
aaa36a97 | 1522 | case CHIP_CARRIZO: |
39bb0c92 SL |
1523 | case CHIP_STONEY: |
1524 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1525 | adev->family = AMDGPU_FAMILY_CZ; |
1526 | else | |
1527 | adev->family = AMDGPU_FAMILY_VI; | |
1528 | ||
1529 | r = vi_set_ip_blocks(adev); | |
1530 | if (r) | |
1531 | return r; | |
1532 | break; | |
33f34802 KW |
1533 | #ifdef CONFIG_DRM_AMDGPU_SI |
1534 | case CHIP_VERDE: | |
1535 | case CHIP_TAHITI: | |
1536 | case CHIP_PITCAIRN: | |
1537 | case CHIP_OLAND: | |
1538 | case CHIP_HAINAN: | |
295d0daf | 1539 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1540 | r = si_set_ip_blocks(adev); |
1541 | if (r) | |
1542 | return r; | |
1543 | break; | |
1544 | #endif | |
a2e73f56 AD |
1545 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1546 | case CHIP_BONAIRE: | |
1547 | case CHIP_HAWAII: | |
1548 | case CHIP_KAVERI: | |
1549 | case CHIP_KABINI: | |
1550 | case CHIP_MULLINS: | |
1551 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1552 | adev->family = AMDGPU_FAMILY_CI; | |
1553 | else | |
1554 | adev->family = AMDGPU_FAMILY_KV; | |
1555 | ||
1556 | r = cik_set_ip_blocks(adev); | |
1557 | if (r) | |
1558 | return r; | |
1559 | break; | |
1560 | #endif | |
2ca8a5d2 CZ |
1561 | case CHIP_VEGA10: |
1562 | case CHIP_RAVEN: | |
1563 | if (adev->asic_type == CHIP_RAVEN) | |
1564 | adev->family = AMDGPU_FAMILY_RV; | |
1565 | else | |
1566 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1567 | |
1568 | r = soc15_set_ip_blocks(adev); | |
1569 | if (r) | |
1570 | return r; | |
1571 | break; | |
d38ceaf9 AD |
1572 | default: |
1573 | /* FIXME: not supported yet */ | |
1574 | return -EINVAL; | |
1575 | } | |
1576 | ||
e2a75f88 AD |
1577 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1578 | if (r) | |
1579 | return r; | |
1580 | ||
3149d9da XY |
1581 | if (amdgpu_sriov_vf(adev)) { |
1582 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1583 | if (r) | |
1584 | return r; | |
1585 | } | |
1586 | ||
d38ceaf9 AD |
1587 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1588 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1589 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1590 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1591 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1592 | } else { |
a1255107 AD |
1593 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1594 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1595 | if (r == -ENOENT) { |
a1255107 | 1596 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1597 | } else if (r) { |
a1255107 AD |
1598 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1599 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1600 | return r; |
2c1a2784 | 1601 | } else { |
a1255107 | 1602 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1603 | } |
974e6b64 | 1604 | } else { |
a1255107 | 1605 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1606 | } |
d38ceaf9 AD |
1607 | } |
1608 | } | |
1609 | ||
395d1fb9 NH |
1610 | adev->cg_flags &= amdgpu_cg_mask; |
1611 | adev->pg_flags &= amdgpu_pg_mask; | |
1612 | ||
d38ceaf9 AD |
1613 | return 0; |
1614 | } | |
1615 | ||
1616 | static int amdgpu_init(struct amdgpu_device *adev) | |
1617 | { | |
1618 | int i, r; | |
1619 | ||
1620 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1621 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1622 | continue; |
a1255107 | 1623 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1624 | if (r) { |
a1255107 AD |
1625 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1626 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1627 | return r; |
2c1a2784 | 1628 | } |
a1255107 | 1629 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1630 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1631 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1632 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1633 | if (r) { |
1634 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1635 | return r; |
2c1a2784 | 1636 | } |
a1255107 | 1637 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1638 | if (r) { |
1639 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1640 | return r; |
2c1a2784 | 1641 | } |
d38ceaf9 | 1642 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1643 | if (r) { |
1644 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1645 | return r; |
2c1a2784 | 1646 | } |
a1255107 | 1647 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1648 | |
1649 | /* right after GMC hw init, we create CSA */ | |
1650 | if (amdgpu_sriov_vf(adev)) { | |
1651 | r = amdgpu_allocate_static_csa(adev); | |
1652 | if (r) { | |
1653 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1654 | return r; | |
1655 | } | |
1656 | } | |
d38ceaf9 AD |
1657 | } |
1658 | } | |
1659 | ||
1660 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1661 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1662 | continue; |
1663 | /* gmc hw init is done early */ | |
a1255107 | 1664 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1665 | continue; |
a1255107 | 1666 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1667 | if (r) { |
a1255107 AD |
1668 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1669 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1670 | return r; |
2c1a2784 | 1671 | } |
a1255107 | 1672 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1673 | } |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
0c49e0b8 CZ |
1678 | static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) |
1679 | { | |
1680 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1681 | } | |
1682 | ||
1683 | static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) | |
1684 | { | |
1685 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1686 | AMDGPU_RESET_MAGIC_NUM); | |
1687 | } | |
1688 | ||
2dc80b00 | 1689 | static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1690 | { |
1691 | int i = 0, r; | |
1692 | ||
1693 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1694 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1695 | continue; |
4a446d55 | 1696 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1697 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1698 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1699 | /* enable clockgating to save power */ |
a1255107 AD |
1700 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1701 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1702 | if (r) { |
1703 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1704 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1705 | return r; |
1706 | } | |
b0b00ff1 | 1707 | } |
d38ceaf9 | 1708 | } |
2dc80b00 S |
1709 | return 0; |
1710 | } | |
1711 | ||
1712 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1713 | { | |
1714 | int i = 0, r; | |
1715 | ||
1716 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1717 | if (!adev->ip_blocks[i].status.valid) | |
1718 | continue; | |
1719 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1720 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1721 | if (r) { | |
1722 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1723 | adev->ip_blocks[i].version->funcs->name, r); | |
1724 | return r; | |
1725 | } | |
1726 | adev->ip_blocks[i].status.late_initialized = true; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1731 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1732 | |
0c49e0b8 CZ |
1733 | amdgpu_fill_reset_magic(adev); |
1734 | ||
d38ceaf9 AD |
1735 | return 0; |
1736 | } | |
1737 | ||
1738 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1739 | { | |
1740 | int i, r; | |
1741 | ||
3e96dbfd AD |
1742 | /* need to disable SMC first */ |
1743 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1744 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1745 | continue; |
a1255107 | 1746 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1747 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1748 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1749 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1750 | if (r) { |
1751 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1752 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1753 | return r; |
1754 | } | |
a1255107 | 1755 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1756 | /* XXX handle errors */ |
1757 | if (r) { | |
1758 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1759 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1760 | } |
a1255107 | 1761 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1762 | break; |
1763 | } | |
1764 | } | |
1765 | ||
d38ceaf9 | 1766 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1767 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1768 | continue; |
a1255107 | 1769 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1770 | amdgpu_wb_fini(adev); |
1771 | amdgpu_vram_scratch_fini(adev); | |
1772 | } | |
8201a67a RZ |
1773 | |
1774 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1775 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1776 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1777 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1778 | AMD_CG_STATE_UNGATE); | |
1779 | if (r) { | |
1780 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1781 | adev->ip_blocks[i].version->funcs->name, r); | |
1782 | return r; | |
1783 | } | |
2c1a2784 | 1784 | } |
8201a67a | 1785 | |
a1255107 | 1786 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1787 | /* XXX handle errors */ |
2c1a2784 | 1788 | if (r) { |
a1255107 AD |
1789 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1790 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1791 | } |
8201a67a | 1792 | |
a1255107 | 1793 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1794 | } |
1795 | ||
1796 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1797 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1798 | continue; |
a1255107 | 1799 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1800 | /* XXX handle errors */ |
2c1a2784 | 1801 | if (r) { |
a1255107 AD |
1802 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1803 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1804 | } |
a1255107 AD |
1805 | adev->ip_blocks[i].status.sw = false; |
1806 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1807 | } |
1808 | ||
a6dcfd9c | 1809 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1810 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1811 | continue; |
a1255107 AD |
1812 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1813 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1814 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1815 | } |
1816 | ||
3149d9da | 1817 | if (amdgpu_sriov_vf(adev)) { |
2493664f | 1818 | amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); |
3149d9da XY |
1819 | amdgpu_virt_release_full_gpu(adev, false); |
1820 | } | |
2493664f | 1821 | |
d38ceaf9 AD |
1822 | return 0; |
1823 | } | |
1824 | ||
2dc80b00 S |
1825 | static void amdgpu_late_init_func_handler(struct work_struct *work) |
1826 | { | |
1827 | struct amdgpu_device *adev = | |
1828 | container_of(work, struct amdgpu_device, late_init_work.work); | |
1829 | amdgpu_late_set_cg_state(adev); | |
1830 | } | |
1831 | ||
faefba95 | 1832 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1833 | { |
1834 | int i, r; | |
1835 | ||
e941ea99 XY |
1836 | if (amdgpu_sriov_vf(adev)) |
1837 | amdgpu_virt_request_full_gpu(adev, false); | |
1838 | ||
c5a93a28 FC |
1839 | /* ungate SMC block first */ |
1840 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1841 | AMD_CG_STATE_UNGATE); | |
1842 | if (r) { | |
1843 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1844 | } | |
1845 | ||
d38ceaf9 | 1846 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1847 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1848 | continue; |
1849 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1850 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1851 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1852 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1853 | if (r) { |
a1255107 AD |
1854 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1855 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1856 | } |
2c1a2784 | 1857 | } |
d38ceaf9 | 1858 | /* XXX handle errors */ |
a1255107 | 1859 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1860 | /* XXX handle errors */ |
2c1a2784 | 1861 | if (r) { |
a1255107 AD |
1862 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1863 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1864 | } |
d38ceaf9 AD |
1865 | } |
1866 | ||
e941ea99 XY |
1867 | if (amdgpu_sriov_vf(adev)) |
1868 | amdgpu_virt_release_full_gpu(adev, false); | |
1869 | ||
d38ceaf9 AD |
1870 | return 0; |
1871 | } | |
1872 | ||
e4f0fdcc | 1873 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1874 | { |
1875 | int i, r; | |
1876 | ||
2cb681b6 ML |
1877 | static enum amd_ip_block_type ip_order[] = { |
1878 | AMD_IP_BLOCK_TYPE_GMC, | |
1879 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1880 | AMD_IP_BLOCK_TYPE_IH, |
1881 | }; | |
1882 | ||
1883 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { | |
1884 | int j; | |
1885 | struct amdgpu_ip_block *block; | |
1886 | ||
1887 | for (j = 0; j < adev->num_ip_blocks; j++) { | |
1888 | block = &adev->ip_blocks[j]; | |
1889 | ||
1890 | if (block->version->type != ip_order[i] || | |
1891 | !block->status.valid) | |
1892 | continue; | |
1893 | ||
1894 | r = block->version->funcs->hw_init(adev); | |
1895 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1896 | } |
1897 | } | |
1898 | ||
1899 | return 0; | |
1900 | } | |
1901 | ||
e4f0fdcc | 1902 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1903 | { |
1904 | int i, r; | |
1905 | ||
2cb681b6 ML |
1906 | static enum amd_ip_block_type ip_order[] = { |
1907 | AMD_IP_BLOCK_TYPE_SMC, | |
1908 | AMD_IP_BLOCK_TYPE_DCE, | |
1909 | AMD_IP_BLOCK_TYPE_GFX, | |
1910 | AMD_IP_BLOCK_TYPE_SDMA, | |
1911 | AMD_IP_BLOCK_TYPE_VCE, | |
1912 | }; | |
a90ad3c2 | 1913 | |
2cb681b6 ML |
1914 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1915 | int j; | |
1916 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1917 | |
2cb681b6 ML |
1918 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1919 | block = &adev->ip_blocks[j]; | |
1920 | ||
1921 | if (block->version->type != ip_order[i] || | |
1922 | !block->status.valid) | |
1923 | continue; | |
1924 | ||
1925 | r = block->version->funcs->hw_init(adev); | |
1926 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1927 | } |
1928 | } | |
1929 | ||
1930 | return 0; | |
1931 | } | |
1932 | ||
fcf0649f | 1933 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1934 | { |
1935 | int i, r; | |
1936 | ||
1937 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1938 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1939 | continue; |
fcf0649f CZ |
1940 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1941 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1942 | adev->ip_blocks[i].version->type == | |
1943 | AMD_IP_BLOCK_TYPE_IH) { | |
1944 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1945 | if (r) { | |
1946 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1947 | adev->ip_blocks[i].version->funcs->name, r); | |
1948 | return r; | |
1949 | } | |
1950 | } | |
1951 | } | |
1952 | ||
1953 | return 0; | |
1954 | } | |
1955 | ||
1956 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) | |
1957 | { | |
1958 | int i, r; | |
1959 | ||
1960 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1961 | if (!adev->ip_blocks[i].status.valid) | |
1962 | continue; | |
1963 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
1964 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
1965 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
1966 | continue; | |
a1255107 | 1967 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1968 | if (r) { |
a1255107 AD |
1969 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1970 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1971 | return r; |
2c1a2784 | 1972 | } |
d38ceaf9 AD |
1973 | } |
1974 | ||
1975 | return 0; | |
1976 | } | |
1977 | ||
fcf0649f CZ |
1978 | static int amdgpu_resume(struct amdgpu_device *adev) |
1979 | { | |
1980 | int r; | |
1981 | ||
1982 | r = amdgpu_resume_phase1(adev); | |
1983 | if (r) | |
1984 | return r; | |
1985 | r = amdgpu_resume_phase2(adev); | |
1986 | ||
1987 | return r; | |
1988 | } | |
1989 | ||
4e99a44e | 1990 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1991 | { |
a5bde2f9 AD |
1992 | if (adev->is_atom_fw) { |
1993 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
1994 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1995 | } else { | |
1996 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
1997 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
1998 | } | |
048765ad AR |
1999 | } |
2000 | ||
d38ceaf9 AD |
2001 | /** |
2002 | * amdgpu_device_init - initialize the driver | |
2003 | * | |
2004 | * @adev: amdgpu_device pointer | |
2005 | * @pdev: drm dev pointer | |
2006 | * @pdev: pci dev pointer | |
2007 | * @flags: driver flags | |
2008 | * | |
2009 | * Initializes the driver info and hw (all asics). | |
2010 | * Returns 0 for success or an error on failure. | |
2011 | * Called at driver startup. | |
2012 | */ | |
2013 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2014 | struct drm_device *ddev, | |
2015 | struct pci_dev *pdev, | |
2016 | uint32_t flags) | |
2017 | { | |
2018 | int r, i; | |
2019 | bool runtime = false; | |
95844d20 | 2020 | u32 max_MBps; |
d38ceaf9 AD |
2021 | |
2022 | adev->shutdown = false; | |
2023 | adev->dev = &pdev->dev; | |
2024 | adev->ddev = ddev; | |
2025 | adev->pdev = pdev; | |
2026 | adev->flags = flags; | |
2f7d10b3 | 2027 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
2028 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
2029 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
2030 | adev->accel_working = false; | |
2031 | adev->num_rings = 0; | |
2032 | adev->mman.buffer_funcs = NULL; | |
2033 | adev->mman.buffer_funcs_ring = NULL; | |
2034 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2035 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 2036 | adev->gart.gart_funcs = NULL; |
f54d1867 | 2037 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
2038 | |
2039 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2040 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2041 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2042 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2043 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2044 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2045 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2046 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2047 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2048 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2049 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2050 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2051 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2052 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2053 | ||
ccdbb20a | 2054 | |
3e39ab90 AD |
2055 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2056 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2057 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2058 | |
2059 | /* mutex initialization are all done here so we | |
2060 | * can recall function without having locking issues */ | |
d38ceaf9 | 2061 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2062 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2063 | mutex_init(&adev->pm.mutex); |
2064 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2065 | mutex_init(&adev->srbm_mutex); | |
2066 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
2067 | mutex_init(&adev->mn_lock); |
2068 | hash_init(adev->mn_hash); | |
2069 | ||
2070 | amdgpu_check_arguments(adev); | |
2071 | ||
d38ceaf9 AD |
2072 | spin_lock_init(&adev->mmio_idx_lock); |
2073 | spin_lock_init(&adev->smc_idx_lock); | |
2074 | spin_lock_init(&adev->pcie_idx_lock); | |
2075 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2076 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2077 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 2078 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2079 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2080 | |
0c4e7fa5 CZ |
2081 | INIT_LIST_HEAD(&adev->shadow_list); |
2082 | mutex_init(&adev->shadow_list_lock); | |
2083 | ||
5c1354bd CZ |
2084 | INIT_LIST_HEAD(&adev->gtt_list); |
2085 | spin_lock_init(&adev->gtt_list_lock); | |
2086 | ||
795f2813 AR |
2087 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2088 | spin_lock_init(&adev->ring_lru_list_lock); | |
2089 | ||
2dc80b00 S |
2090 | INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); |
2091 | ||
0fa49558 AX |
2092 | /* Registers mapping */ |
2093 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2094 | if (adev->asic_type >= CHIP_BONAIRE) { |
2095 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2096 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2097 | } else { | |
2098 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2099 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2100 | } | |
d38ceaf9 | 2101 | |
d38ceaf9 AD |
2102 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2103 | if (adev->rmmio == NULL) { | |
2104 | return -ENOMEM; | |
2105 | } | |
2106 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2107 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2108 | ||
da69c161 KW |
2109 | if (adev->asic_type >= CHIP_BONAIRE) |
2110 | /* doorbell bar mapping */ | |
2111 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2112 | |
2113 | /* io port mapping */ | |
2114 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2115 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2116 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2117 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2118 | break; | |
2119 | } | |
2120 | } | |
2121 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2122 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2123 | |
2124 | /* early init functions */ | |
2125 | r = amdgpu_early_init(adev); | |
2126 | if (r) | |
2127 | return r; | |
2128 | ||
2129 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2130 | /* this will fail for cards that aren't VGA class devices, just | |
2131 | * ignore it */ | |
2132 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2133 | ||
2134 | if (amdgpu_runtime_pm == 1) | |
2135 | runtime = true; | |
e9bef455 | 2136 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2137 | runtime = true; |
84c8b22e LW |
2138 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2139 | vga_switcheroo_register_client(adev->pdev, | |
2140 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2141 | if (runtime) |
2142 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2143 | ||
2144 | /* Read BIOS */ | |
83ba126a AD |
2145 | if (!amdgpu_get_bios(adev)) { |
2146 | r = -EINVAL; | |
2147 | goto failed; | |
2148 | } | |
f7e9e9fe | 2149 | |
d38ceaf9 | 2150 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2151 | if (r) { |
2152 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
89041940 | 2153 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2154 | goto failed; |
2c1a2784 | 2155 | } |
d38ceaf9 | 2156 | |
4e99a44e ML |
2157 | /* detect if we are with an SRIOV vbios */ |
2158 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2159 | |
d38ceaf9 | 2160 | /* Post card if necessary */ |
bec86378 | 2161 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 2162 | if (!adev->bios) { |
bec86378 | 2163 | dev_err(adev->dev, "no vBIOS found\n"); |
89041940 | 2164 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); |
83ba126a AD |
2165 | r = -EINVAL; |
2166 | goto failed; | |
d38ceaf9 | 2167 | } |
bec86378 | 2168 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2169 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2170 | if (r) { | |
2171 | dev_err(adev->dev, "gpu post error!\n"); | |
89041940 | 2172 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0); |
4e99a44e ML |
2173 | goto failed; |
2174 | } | |
2175 | } else { | |
2176 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
2177 | } |
2178 | ||
a5bde2f9 AD |
2179 | if (!adev->is_atom_fw) { |
2180 | /* Initialize clocks */ | |
2181 | r = amdgpu_atombios_get_clock_info(adev); | |
2182 | if (r) { | |
2183 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
89041940 GW |
2184 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
2185 | goto failed; | |
a5bde2f9 AD |
2186 | } |
2187 | /* init i2c buses */ | |
2188 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2189 | } |
d38ceaf9 AD |
2190 | |
2191 | /* Fence driver */ | |
2192 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2193 | if (r) { |
2194 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
89041940 | 2195 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2196 | goto failed; |
2c1a2784 | 2197 | } |
d38ceaf9 AD |
2198 | |
2199 | /* init the mode config */ | |
2200 | drm_mode_config_init(adev->ddev); | |
2201 | ||
2202 | r = amdgpu_init(adev); | |
2203 | if (r) { | |
2c1a2784 | 2204 | dev_err(adev->dev, "amdgpu_init failed\n"); |
89041940 | 2205 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
d38ceaf9 | 2206 | amdgpu_fini(adev); |
83ba126a | 2207 | goto failed; |
d38ceaf9 AD |
2208 | } |
2209 | ||
2210 | adev->accel_working = true; | |
2211 | ||
e59c0205 AX |
2212 | amdgpu_vm_check_compute_bug(adev); |
2213 | ||
95844d20 MO |
2214 | /* Initialize the buffer migration limit. */ |
2215 | if (amdgpu_moverate >= 0) | |
2216 | max_MBps = amdgpu_moverate; | |
2217 | else | |
2218 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2219 | /* Get a log2 for easy divisions. */ | |
2220 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2221 | ||
d38ceaf9 AD |
2222 | r = amdgpu_ib_pool_init(adev); |
2223 | if (r) { | |
2224 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
89041940 | 2225 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2226 | goto failed; |
d38ceaf9 AD |
2227 | } |
2228 | ||
2229 | r = amdgpu_ib_ring_tests(adev); | |
2230 | if (r) | |
2231 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2232 | ||
9bc92b9c ML |
2233 | amdgpu_fbdev_init(adev); |
2234 | ||
d38ceaf9 | 2235 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2236 | if (r) |
d38ceaf9 | 2237 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2238 | |
2239 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2240 | if (r) |
d38ceaf9 | 2241 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2242 | |
4f0955fc HR |
2243 | r = amdgpu_debugfs_test_ib_ring_init(adev); |
2244 | if (r) | |
2245 | DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); | |
2246 | ||
50ab2533 | 2247 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2248 | if (r) |
50ab2533 | 2249 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2250 | |
d38ceaf9 AD |
2251 | if ((amdgpu_testing & 1)) { |
2252 | if (adev->accel_working) | |
2253 | amdgpu_test_moves(adev); | |
2254 | else | |
2255 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2256 | } | |
d38ceaf9 AD |
2257 | if (amdgpu_benchmarking) { |
2258 | if (adev->accel_working) | |
2259 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2260 | else | |
2261 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2262 | } | |
2263 | ||
2264 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2265 | * explicit gating rather than handling it automatically. | |
2266 | */ | |
2267 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2268 | if (r) { |
2269 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
89041940 | 2270 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2271 | goto failed; |
2c1a2784 | 2272 | } |
d38ceaf9 AD |
2273 | |
2274 | return 0; | |
83ba126a AD |
2275 | |
2276 | failed: | |
89041940 | 2277 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2278 | if (runtime) |
2279 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2280 | return r; | |
d38ceaf9 AD |
2281 | } |
2282 | ||
d38ceaf9 AD |
2283 | /** |
2284 | * amdgpu_device_fini - tear down the driver | |
2285 | * | |
2286 | * @adev: amdgpu_device pointer | |
2287 | * | |
2288 | * Tear down the driver info (all asics). | |
2289 | * Called at driver shutdown. | |
2290 | */ | |
2291 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2292 | { | |
2293 | int r; | |
2294 | ||
2295 | DRM_INFO("amdgpu: finishing device.\n"); | |
2296 | adev->shutdown = true; | |
db2c2a97 PD |
2297 | if (adev->mode_info.mode_config_initialized) |
2298 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2299 | /* evict vram memory */ |
2300 | amdgpu_bo_evict_vram(adev); | |
2301 | amdgpu_ib_pool_fini(adev); | |
2302 | amdgpu_fence_driver_fini(adev); | |
2303 | amdgpu_fbdev_fini(adev); | |
2304 | r = amdgpu_fini(adev); | |
ab4fe3e1 HR |
2305 | if (adev->firmware.gpu_info_fw) { |
2306 | release_firmware(adev->firmware.gpu_info_fw); | |
2307 | adev->firmware.gpu_info_fw = NULL; | |
2308 | } | |
d38ceaf9 | 2309 | adev->accel_working = false; |
2dc80b00 | 2310 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 AD |
2311 | /* free i2c buses */ |
2312 | amdgpu_i2c_fini(adev); | |
2313 | amdgpu_atombios_fini(adev); | |
2314 | kfree(adev->bios); | |
2315 | adev->bios = NULL; | |
84c8b22e LW |
2316 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2317 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2318 | if (adev->flags & AMD_IS_PX) |
2319 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2320 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2321 | if (adev->rio_mem) | |
2322 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2323 | adev->rio_mem = NULL; | |
2324 | iounmap(adev->rmmio); | |
2325 | adev->rmmio = NULL; | |
da69c161 KW |
2326 | if (adev->asic_type >= CHIP_BONAIRE) |
2327 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 | 2328 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2329 | } |
2330 | ||
2331 | ||
2332 | /* | |
2333 | * Suspend & resume. | |
2334 | */ | |
2335 | /** | |
810ddc3a | 2336 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2337 | * |
2338 | * @pdev: drm dev pointer | |
2339 | * @state: suspend state | |
2340 | * | |
2341 | * Puts the hw in the suspend state (all asics). | |
2342 | * Returns 0 for success or an error on failure. | |
2343 | * Called at driver suspend. | |
2344 | */ | |
810ddc3a | 2345 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2346 | { |
2347 | struct amdgpu_device *adev; | |
2348 | struct drm_crtc *crtc; | |
2349 | struct drm_connector *connector; | |
5ceb54c6 | 2350 | int r; |
d38ceaf9 AD |
2351 | |
2352 | if (dev == NULL || dev->dev_private == NULL) { | |
2353 | return -ENODEV; | |
2354 | } | |
2355 | ||
2356 | adev = dev->dev_private; | |
2357 | ||
2358 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2359 | return 0; | |
2360 | ||
2361 | drm_kms_helper_poll_disable(dev); | |
2362 | ||
2363 | /* turn off display hw */ | |
4c7fbc39 | 2364 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2365 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2366 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2367 | } | |
4c7fbc39 | 2368 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2369 | |
756e6880 | 2370 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2371 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2372 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2373 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2374 | struct amdgpu_bo *robj; | |
2375 | ||
756e6880 AD |
2376 | if (amdgpu_crtc->cursor_bo) { |
2377 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2378 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2379 | if (r == 0) { |
2380 | amdgpu_bo_unpin(aobj); | |
2381 | amdgpu_bo_unreserve(aobj); | |
2382 | } | |
2383 | } | |
2384 | ||
d38ceaf9 AD |
2385 | if (rfb == NULL || rfb->obj == NULL) { |
2386 | continue; | |
2387 | } | |
2388 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2389 | /* don't unpin kernel fb objects */ | |
2390 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2391 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2392 | if (r == 0) { |
2393 | amdgpu_bo_unpin(robj); | |
2394 | amdgpu_bo_unreserve(robj); | |
2395 | } | |
2396 | } | |
2397 | } | |
2398 | /* evict vram memory */ | |
2399 | amdgpu_bo_evict_vram(adev); | |
2400 | ||
5ceb54c6 | 2401 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2402 | |
2403 | r = amdgpu_suspend(adev); | |
2404 | ||
a0a71e49 AD |
2405 | /* evict remaining vram memory |
2406 | * This second call to evict vram is to evict the gart page table | |
2407 | * using the CPU. | |
2408 | */ | |
d38ceaf9 AD |
2409 | amdgpu_bo_evict_vram(adev); |
2410 | ||
d05da0e2 | 2411 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
2412 | pci_save_state(dev->pdev); |
2413 | if (suspend) { | |
2414 | /* Shut down the device */ | |
2415 | pci_disable_device(dev->pdev); | |
2416 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2417 | } else { |
2418 | r = amdgpu_asic_reset(adev); | |
2419 | if (r) | |
2420 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2421 | } |
2422 | ||
2423 | if (fbcon) { | |
2424 | console_lock(); | |
2425 | amdgpu_fbdev_set_suspend(adev, 1); | |
2426 | console_unlock(); | |
2427 | } | |
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | /** | |
810ddc3a | 2432 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2433 | * |
2434 | * @pdev: drm dev pointer | |
2435 | * | |
2436 | * Bring the hw back to operating state (all asics). | |
2437 | * Returns 0 for success or an error on failure. | |
2438 | * Called at driver resume. | |
2439 | */ | |
810ddc3a | 2440 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2441 | { |
2442 | struct drm_connector *connector; | |
2443 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2444 | struct drm_crtc *crtc; |
03161a6e | 2445 | int r = 0; |
d38ceaf9 AD |
2446 | |
2447 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2448 | return 0; | |
2449 | ||
74b0b157 | 2450 | if (fbcon) |
d38ceaf9 | 2451 | console_lock(); |
74b0b157 | 2452 | |
d38ceaf9 AD |
2453 | if (resume) { |
2454 | pci_set_power_state(dev->pdev, PCI_D0); | |
2455 | pci_restore_state(dev->pdev); | |
74b0b157 | 2456 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2457 | if (r) |
2458 | goto unlock; | |
d38ceaf9 | 2459 | } |
d05da0e2 | 2460 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2461 | |
2462 | /* post card */ | |
c836fec5 | 2463 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2464 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2465 | if (r) | |
2466 | DRM_ERROR("amdgpu asic init failed\n"); | |
2467 | } | |
d38ceaf9 AD |
2468 | |
2469 | r = amdgpu_resume(adev); | |
e6707218 | 2470 | if (r) { |
ca198528 | 2471 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2472 | goto unlock; |
e6707218 | 2473 | } |
5ceb54c6 AD |
2474 | amdgpu_fence_driver_resume(adev); |
2475 | ||
ca198528 FC |
2476 | if (resume) { |
2477 | r = amdgpu_ib_ring_tests(adev); | |
2478 | if (r) | |
2479 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2480 | } | |
d38ceaf9 AD |
2481 | |
2482 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2483 | if (r) |
2484 | goto unlock; | |
d38ceaf9 | 2485 | |
756e6880 AD |
2486 | /* pin cursors */ |
2487 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2488 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2489 | ||
2490 | if (amdgpu_crtc->cursor_bo) { | |
2491 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2492 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2493 | if (r == 0) { |
2494 | r = amdgpu_bo_pin(aobj, | |
2495 | AMDGPU_GEM_DOMAIN_VRAM, | |
2496 | &amdgpu_crtc->cursor_addr); | |
2497 | if (r != 0) | |
2498 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2499 | amdgpu_bo_unreserve(aobj); | |
2500 | } | |
2501 | } | |
2502 | } | |
2503 | ||
d38ceaf9 AD |
2504 | /* blat the mode back in */ |
2505 | if (fbcon) { | |
2506 | drm_helper_resume_force_mode(dev); | |
2507 | /* turn on display hw */ | |
4c7fbc39 | 2508 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2509 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2510 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2511 | } | |
4c7fbc39 | 2512 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2513 | } |
2514 | ||
2515 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2516 | |
2517 | /* | |
2518 | * Most of the connector probing functions try to acquire runtime pm | |
2519 | * refs to ensure that the GPU is powered on when connector polling is | |
2520 | * performed. Since we're calling this from a runtime PM callback, | |
2521 | * trying to acquire rpm refs will cause us to deadlock. | |
2522 | * | |
2523 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2524 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2525 | */ | |
2526 | #ifdef CONFIG_PM | |
2527 | dev->dev->power.disable_depth++; | |
2528 | #endif | |
54fb2a5c | 2529 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2530 | #ifdef CONFIG_PM |
2531 | dev->dev->power.disable_depth--; | |
2532 | #endif | |
d38ceaf9 | 2533 | |
03161a6e | 2534 | if (fbcon) |
d38ceaf9 | 2535 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2536 | |
2537 | unlock: | |
2538 | if (fbcon) | |
d38ceaf9 | 2539 | console_unlock(); |
d38ceaf9 | 2540 | |
03161a6e | 2541 | return r; |
d38ceaf9 AD |
2542 | } |
2543 | ||
63fbf42f CZ |
2544 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2545 | { | |
2546 | int i; | |
2547 | bool asic_hang = false; | |
2548 | ||
2549 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2550 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2551 | continue; |
a1255107 AD |
2552 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2553 | adev->ip_blocks[i].status.hang = | |
2554 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2555 | if (adev->ip_blocks[i].status.hang) { | |
2556 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2557 | asic_hang = true; |
2558 | } | |
2559 | } | |
2560 | return asic_hang; | |
2561 | } | |
2562 | ||
4d446656 | 2563 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2564 | { |
2565 | int i, r = 0; | |
2566 | ||
2567 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2568 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2569 | continue; |
a1255107 AD |
2570 | if (adev->ip_blocks[i].status.hang && |
2571 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2572 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2573 | if (r) |
2574 | return r; | |
2575 | } | |
2576 | } | |
2577 | ||
2578 | return 0; | |
2579 | } | |
2580 | ||
35d782fe CZ |
2581 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2582 | { | |
da146d3b AD |
2583 | int i; |
2584 | ||
2585 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2586 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2587 | continue; |
a1255107 AD |
2588 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2589 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2590 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2591 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2592 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2593 | DRM_INFO("Some block need full reset!\n"); |
2594 | return true; | |
2595 | } | |
2596 | } | |
35d782fe CZ |
2597 | } |
2598 | return false; | |
2599 | } | |
2600 | ||
2601 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2602 | { | |
2603 | int i, r = 0; | |
2604 | ||
2605 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2606 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2607 | continue; |
a1255107 AD |
2608 | if (adev->ip_blocks[i].status.hang && |
2609 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2610 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2611 | if (r) |
2612 | return r; | |
2613 | } | |
2614 | } | |
2615 | ||
2616 | return 0; | |
2617 | } | |
2618 | ||
2619 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2620 | { | |
2621 | int i, r = 0; | |
2622 | ||
2623 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2624 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2625 | continue; |
a1255107 AD |
2626 | if (adev->ip_blocks[i].status.hang && |
2627 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2628 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2629 | if (r) |
2630 | return r; | |
2631 | } | |
2632 | ||
2633 | return 0; | |
2634 | } | |
2635 | ||
3ad81f16 CZ |
2636 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2637 | { | |
2638 | if (adev->flags & AMD_IS_APU) | |
2639 | return false; | |
2640 | ||
2641 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2642 | } | |
2643 | ||
53cdccd5 CZ |
2644 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2645 | struct amdgpu_ring *ring, | |
2646 | struct amdgpu_bo *bo, | |
f54d1867 | 2647 | struct dma_fence **fence) |
53cdccd5 CZ |
2648 | { |
2649 | uint32_t domain; | |
2650 | int r; | |
2651 | ||
23d2e504 RH |
2652 | if (!bo->shadow) |
2653 | return 0; | |
2654 | ||
1d284797 | 2655 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2656 | if (r) |
2657 | return r; | |
2658 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2659 | /* if bo has been evicted, then no need to recover */ | |
2660 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2661 | r = amdgpu_bo_validate(bo->shadow); |
2662 | if (r) { | |
2663 | DRM_ERROR("bo validate failed!\n"); | |
2664 | goto err; | |
2665 | } | |
2666 | ||
2667 | r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem); | |
2668 | if (r) { | |
2669 | DRM_ERROR("%p bind failed\n", bo->shadow); | |
2670 | goto err; | |
2671 | } | |
2672 | ||
23d2e504 | 2673 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2674 | NULL, fence, true); |
23d2e504 RH |
2675 | if (r) { |
2676 | DRM_ERROR("recover page table failed!\n"); | |
2677 | goto err; | |
2678 | } | |
2679 | } | |
53cdccd5 | 2680 | err: |
23d2e504 RH |
2681 | amdgpu_bo_unreserve(bo); |
2682 | return r; | |
53cdccd5 CZ |
2683 | } |
2684 | ||
a90ad3c2 ML |
2685 | /** |
2686 | * amdgpu_sriov_gpu_reset - reset the asic | |
2687 | * | |
2688 | * @adev: amdgpu device pointer | |
7225f873 | 2689 | * @job: which job trigger hang |
a90ad3c2 ML |
2690 | * |
2691 | * Attempt the reset the GPU if it has hung (all asics). | |
2692 | * for SRIOV case. | |
2693 | * Returns 0 for success or an error on failure. | |
2694 | */ | |
7225f873 | 2695 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) |
a90ad3c2 | 2696 | { |
65781c78 | 2697 | int i, j, r = 0; |
a90ad3c2 ML |
2698 | int resched; |
2699 | struct amdgpu_bo *bo, *tmp; | |
2700 | struct amdgpu_ring *ring; | |
2701 | struct dma_fence *fence = NULL, *next = NULL; | |
2702 | ||
147b5983 | 2703 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2704 | atomic_inc(&adev->gpu_reset_counter); |
1fb37a3d | 2705 | adev->gfx.in_reset = true; |
a90ad3c2 ML |
2706 | |
2707 | /* block TTM */ | |
2708 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2709 | ||
65781c78 ML |
2710 | /* we start from the ring trigger GPU hang */ |
2711 | j = job ? job->ring->idx : 0; | |
a90ad3c2 | 2712 | |
65781c78 ML |
2713 | /* block scheduler */ |
2714 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { | |
2715 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2716 | if (!ring || !ring->sched.thread) |
2717 | continue; | |
2718 | ||
2719 | kthread_park(ring->sched.thread); | |
65781c78 ML |
2720 | |
2721 | if (job && j != i) | |
2722 | continue; | |
2723 | ||
4f059ecd | 2724 | /* here give the last chance to check if job removed from mirror-list |
65781c78 | 2725 | * since we already pay some time on kthread_park */ |
4f059ecd | 2726 | if (job && list_empty(&job->base.node)) { |
65781c78 ML |
2727 | kthread_unpark(ring->sched.thread); |
2728 | goto give_up_reset; | |
2729 | } | |
2730 | ||
2731 | if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) | |
2732 | amd_sched_job_kickout(&job->base); | |
2733 | ||
2734 | /* only do job_reset on the hang ring if @job not NULL */ | |
a90ad3c2 | 2735 | amd_sched_hw_job_reset(&ring->sched); |
a90ad3c2 | 2736 | |
65781c78 ML |
2737 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2738 | amdgpu_fence_driver_force_completion_ring(ring); | |
2739 | } | |
a90ad3c2 ML |
2740 | |
2741 | /* request to take full control of GPU before re-initialization */ | |
7225f873 | 2742 | if (job) |
a90ad3c2 ML |
2743 | amdgpu_virt_reset_gpu(adev); |
2744 | else | |
2745 | amdgpu_virt_request_full_gpu(adev, true); | |
2746 | ||
2747 | ||
2748 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2749 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2750 | |
2751 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2752 | amdgpu_ttm_recover_gart(adev); | |
2753 | ||
2754 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2755 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2756 | |
2757 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2758 | ||
2759 | if (amdgpu_ib_ring_tests(adev)) | |
2760 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2761 | ||
2762 | /* release full control of GPU after ib test */ | |
2763 | amdgpu_virt_release_full_gpu(adev, true); | |
2764 | ||
2765 | DRM_INFO("recover vram bo from shadow\n"); | |
2766 | ||
2767 | ring = adev->mman.buffer_funcs_ring; | |
2768 | mutex_lock(&adev->shadow_list_lock); | |
2769 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2770 | next = NULL; |
a90ad3c2 ML |
2771 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2772 | if (fence) { | |
2773 | r = dma_fence_wait(fence, false); | |
2774 | if (r) { | |
2775 | WARN(r, "recovery from shadow isn't completed\n"); | |
2776 | break; | |
2777 | } | |
2778 | } | |
2779 | ||
2780 | dma_fence_put(fence); | |
2781 | fence = next; | |
2782 | } | |
2783 | mutex_unlock(&adev->shadow_list_lock); | |
2784 | ||
2785 | if (fence) { | |
2786 | r = dma_fence_wait(fence, false); | |
2787 | if (r) | |
2788 | WARN(r, "recovery from shadow isn't completed\n"); | |
2789 | } | |
2790 | dma_fence_put(fence); | |
2791 | ||
65781c78 ML |
2792 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { |
2793 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2794 | if (!ring || !ring->sched.thread) |
2795 | continue; | |
2796 | ||
65781c78 ML |
2797 | if (job && j != i) { |
2798 | kthread_unpark(ring->sched.thread); | |
2799 | continue; | |
2800 | } | |
2801 | ||
a90ad3c2 ML |
2802 | amd_sched_job_recovery(&ring->sched); |
2803 | kthread_unpark(ring->sched.thread); | |
2804 | } | |
2805 | ||
2806 | drm_helper_resume_force_mode(adev->ddev); | |
65781c78 | 2807 | give_up_reset: |
a90ad3c2 ML |
2808 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); |
2809 | if (r) { | |
2810 | /* bad news, how to tell it to userspace ? */ | |
2811 | dev_info(adev->dev, "GPU reset failed\n"); | |
65781c78 ML |
2812 | } else { |
2813 | dev_info(adev->dev, "GPU reset successed!\n"); | |
a90ad3c2 ML |
2814 | } |
2815 | ||
1fb37a3d | 2816 | adev->gfx.in_reset = false; |
147b5983 | 2817 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2818 | return r; |
2819 | } | |
2820 | ||
d38ceaf9 AD |
2821 | /** |
2822 | * amdgpu_gpu_reset - reset the asic | |
2823 | * | |
2824 | * @adev: amdgpu device pointer | |
2825 | * | |
2826 | * Attempt the reset the GPU if it has hung (all asics). | |
2827 | * Returns 0 for success or an error on failure. | |
2828 | */ | |
2829 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2830 | { | |
d38ceaf9 AD |
2831 | int i, r; |
2832 | int resched; | |
0c49e0b8 | 2833 | bool need_full_reset, vram_lost = false; |
d38ceaf9 | 2834 | |
63fbf42f CZ |
2835 | if (!amdgpu_check_soft_reset(adev)) { |
2836 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2837 | return 0; | |
2838 | } | |
d38ceaf9 | 2839 | |
d94aed5a | 2840 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2841 | |
a3c47d6b CZ |
2842 | /* block TTM */ |
2843 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2844 | ||
0875dc9e CZ |
2845 | /* block scheduler */ |
2846 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2847 | struct amdgpu_ring *ring = adev->rings[i]; | |
2848 | ||
51687759 | 2849 | if (!ring || !ring->sched.thread) |
0875dc9e CZ |
2850 | continue; |
2851 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2852 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2853 | } |
2200edac CZ |
2854 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2855 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2856 | |
35d782fe | 2857 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2858 | |
35d782fe CZ |
2859 | if (!need_full_reset) { |
2860 | amdgpu_pre_soft_reset(adev); | |
2861 | r = amdgpu_soft_reset(adev); | |
2862 | amdgpu_post_soft_reset(adev); | |
2863 | if (r || amdgpu_check_soft_reset(adev)) { | |
2864 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2865 | need_full_reset = true; | |
2866 | } | |
f1aa7e08 CZ |
2867 | } |
2868 | ||
35d782fe | 2869 | if (need_full_reset) { |
35d782fe | 2870 | r = amdgpu_suspend(adev); |
bfa99269 | 2871 | |
35d782fe | 2872 | retry: |
d05da0e2 | 2873 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2874 | r = amdgpu_asic_reset(adev); |
d05da0e2 | 2875 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2876 | /* post card */ |
2877 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2878 | ||
2879 | if (!r) { | |
2880 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
fcf0649f CZ |
2881 | r = amdgpu_resume_phase1(adev); |
2882 | if (r) | |
2883 | goto out; | |
0c49e0b8 | 2884 | vram_lost = amdgpu_check_vram_lost(adev); |
f1892138 | 2885 | if (vram_lost) { |
0c49e0b8 | 2886 | DRM_ERROR("VRAM is lost!\n"); |
f1892138 CZ |
2887 | atomic_inc(&adev->vram_lost_counter); |
2888 | } | |
fcf0649f CZ |
2889 | r = amdgpu_ttm_recover_gart(adev); |
2890 | if (r) | |
2891 | goto out; | |
2892 | r = amdgpu_resume_phase2(adev); | |
2893 | if (r) | |
2894 | goto out; | |
0c49e0b8 CZ |
2895 | if (vram_lost) |
2896 | amdgpu_fill_reset_magic(adev); | |
35d782fe | 2897 | } |
d38ceaf9 | 2898 | } |
fcf0649f | 2899 | out: |
d38ceaf9 | 2900 | if (!r) { |
e72cfd58 | 2901 | amdgpu_irq_gpu_reset_resume_helper(adev); |
1f465087 CZ |
2902 | r = amdgpu_ib_ring_tests(adev); |
2903 | if (r) { | |
2904 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2905 | r = amdgpu_suspend(adev); |
53cdccd5 | 2906 | need_full_reset = true; |
40019dc4 | 2907 | goto retry; |
1f465087 | 2908 | } |
53cdccd5 CZ |
2909 | /** |
2910 | * recovery vm page tables, since we cannot depend on VRAM is | |
2911 | * consistent after gpu full reset. | |
2912 | */ | |
2913 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2914 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2915 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2916 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2917 | |
2918 | DRM_INFO("recover vram bo from shadow\n"); | |
2919 | mutex_lock(&adev->shadow_list_lock); | |
2920 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2921 | next = NULL; |
53cdccd5 CZ |
2922 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2923 | if (fence) { | |
f54d1867 | 2924 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2925 | if (r) { |
1d7b17b0 | 2926 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
2927 | break; |
2928 | } | |
2929 | } | |
1f465087 | 2930 | |
f54d1867 | 2931 | dma_fence_put(fence); |
53cdccd5 CZ |
2932 | fence = next; |
2933 | } | |
2934 | mutex_unlock(&adev->shadow_list_lock); | |
2935 | if (fence) { | |
f54d1867 | 2936 | r = dma_fence_wait(fence, false); |
53cdccd5 | 2937 | if (r) |
1d7b17b0 | 2938 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 2939 | } |
f54d1867 | 2940 | dma_fence_put(fence); |
53cdccd5 | 2941 | } |
d38ceaf9 AD |
2942 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2943 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
2944 | |
2945 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 2946 | continue; |
53cdccd5 | 2947 | |
aa1c8900 | 2948 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2949 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2950 | } |
d38ceaf9 | 2951 | } else { |
2200edac | 2952 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
89041940 | 2953 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r); |
d38ceaf9 | 2954 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
51687759 | 2955 | if (adev->rings[i] && adev->rings[i]->sched.thread) { |
0875dc9e | 2956 | kthread_unpark(adev->rings[i]->sched.thread); |
0875dc9e | 2957 | } |
d38ceaf9 AD |
2958 | } |
2959 | } | |
2960 | ||
2961 | drm_helper_resume_force_mode(adev->ddev); | |
2962 | ||
2963 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
89041940 | 2964 | if (r) { |
d38ceaf9 AD |
2965 | /* bad news, how to tell it to userspace ? */ |
2966 | dev_info(adev->dev, "GPU reset failed\n"); | |
89041940 GW |
2967 | amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
2968 | } | |
2969 | else { | |
6643be65 | 2970 | dev_info(adev->dev, "GPU reset successed!\n"); |
89041940 | 2971 | } |
d38ceaf9 | 2972 | |
89041940 | 2973 | amdgpu_vf_error_trans_all(adev); |
d38ceaf9 AD |
2974 | return r; |
2975 | } | |
2976 | ||
d0dd7f0c AD |
2977 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2978 | { | |
2979 | u32 mask; | |
2980 | int ret; | |
2981 | ||
cd474ba0 AD |
2982 | if (amdgpu_pcie_gen_cap) |
2983 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2984 | |
cd474ba0 AD |
2985 | if (amdgpu_pcie_lane_cap) |
2986 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2987 | |
cd474ba0 AD |
2988 | /* covers APUs as well */ |
2989 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2990 | if (adev->pm.pcie_gen_mask == 0) | |
2991 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2992 | if (adev->pm.pcie_mlw_mask == 0) | |
2993 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2994 | return; |
cd474ba0 | 2995 | } |
d0dd7f0c | 2996 | |
cd474ba0 AD |
2997 | if (adev->pm.pcie_gen_mask == 0) { |
2998 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2999 | if (!ret) { | |
3000 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3001 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3002 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3003 | ||
3004 | if (mask & DRM_PCIE_SPEED_25) | |
3005 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3006 | if (mask & DRM_PCIE_SPEED_50) | |
3007 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3008 | if (mask & DRM_PCIE_SPEED_80) | |
3009 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3010 | } else { | |
3011 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3012 | } | |
3013 | } | |
3014 | if (adev->pm.pcie_mlw_mask == 0) { | |
3015 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3016 | if (!ret) { | |
3017 | switch (mask) { | |
3018 | case 32: | |
3019 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3020 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3021 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3022 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3023 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3024 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3025 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3026 | break; | |
3027 | case 16: | |
3028 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3029 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3030 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3031 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3032 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3033 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3034 | break; | |
3035 | case 12: | |
3036 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3037 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3038 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3039 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3040 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3041 | break; | |
3042 | case 8: | |
3043 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3044 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3045 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3046 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3047 | break; | |
3048 | case 4: | |
3049 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3050 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3051 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3052 | break; | |
3053 | case 2: | |
3054 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3055 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3056 | break; | |
3057 | case 1: | |
3058 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3059 | break; | |
3060 | default: | |
3061 | break; | |
3062 | } | |
3063 | } else { | |
3064 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3065 | } |
3066 | } | |
3067 | } | |
d38ceaf9 AD |
3068 | |
3069 | /* | |
3070 | * Debugfs | |
3071 | */ | |
3072 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3073 | const struct drm_info_list *files, |
d38ceaf9 AD |
3074 | unsigned nfiles) |
3075 | { | |
3076 | unsigned i; | |
3077 | ||
3078 | for (i = 0; i < adev->debugfs_count; i++) { | |
3079 | if (adev->debugfs[i].files == files) { | |
3080 | /* Already registered */ | |
3081 | return 0; | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | i = adev->debugfs_count + 1; | |
3086 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3087 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3088 | DRM_ERROR("Report so we increase " | |
3089 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3090 | return -EINVAL; | |
3091 | } | |
3092 | adev->debugfs[adev->debugfs_count].files = files; | |
3093 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3094 | adev->debugfs_count = i; | |
3095 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3096 | drm_debugfs_create_files(files, nfiles, |
3097 | adev->ddev->primary->debugfs_root, | |
3098 | adev->ddev->primary); | |
3099 | #endif | |
3100 | return 0; | |
3101 | } | |
3102 | ||
d38ceaf9 AD |
3103 | #if defined(CONFIG_DEBUG_FS) |
3104 | ||
3105 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3106 | size_t size, loff_t *pos) | |
3107 | { | |
45063097 | 3108 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3109 | ssize_t result = 0; |
3110 | int r; | |
bd12267d | 3111 | bool pm_pg_lock, use_bank; |
56628159 | 3112 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3113 | |
3114 | if (size & 0x3 || *pos & 0x3) | |
3115 | return -EINVAL; | |
3116 | ||
bd12267d TSD |
3117 | /* are we reading registers for which a PG lock is necessary? */ |
3118 | pm_pg_lock = (*pos >> 23) & 1; | |
3119 | ||
56628159 TSD |
3120 | if (*pos & (1ULL << 62)) { |
3121 | se_bank = (*pos >> 24) & 0x3FF; | |
3122 | sh_bank = (*pos >> 34) & 0x3FF; | |
3123 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
3124 | |
3125 | if (se_bank == 0x3FF) | |
3126 | se_bank = 0xFFFFFFFF; | |
3127 | if (sh_bank == 0x3FF) | |
3128 | sh_bank = 0xFFFFFFFF; | |
3129 | if (instance_bank == 0x3FF) | |
3130 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3131 | use_bank = 1; |
56628159 TSD |
3132 | } else { |
3133 | use_bank = 0; | |
3134 | } | |
3135 | ||
801a6aa9 | 3136 | *pos &= (1UL << 22) - 1; |
bd12267d | 3137 | |
56628159 | 3138 | if (use_bank) { |
32977f93 TSD |
3139 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3140 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3141 | return -EINVAL; |
3142 | mutex_lock(&adev->grbm_idx_mutex); | |
3143 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3144 | sh_bank, instance_bank); | |
3145 | } | |
3146 | ||
bd12267d TSD |
3147 | if (pm_pg_lock) |
3148 | mutex_lock(&adev->pm.mutex); | |
3149 | ||
d38ceaf9 AD |
3150 | while (size) { |
3151 | uint32_t value; | |
3152 | ||
3153 | if (*pos > adev->rmmio_size) | |
56628159 | 3154 | goto end; |
d38ceaf9 AD |
3155 | |
3156 | value = RREG32(*pos >> 2); | |
3157 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3158 | if (r) { |
3159 | result = r; | |
3160 | goto end; | |
3161 | } | |
d38ceaf9 AD |
3162 | |
3163 | result += 4; | |
3164 | buf += 4; | |
3165 | *pos += 4; | |
3166 | size -= 4; | |
3167 | } | |
3168 | ||
56628159 TSD |
3169 | end: |
3170 | if (use_bank) { | |
3171 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3172 | mutex_unlock(&adev->grbm_idx_mutex); | |
3173 | } | |
3174 | ||
bd12267d TSD |
3175 | if (pm_pg_lock) |
3176 | mutex_unlock(&adev->pm.mutex); | |
3177 | ||
d38ceaf9 AD |
3178 | return result; |
3179 | } | |
3180 | ||
3181 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3182 | size_t size, loff_t *pos) | |
3183 | { | |
45063097 | 3184 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3185 | ssize_t result = 0; |
3186 | int r; | |
394fdde2 TSD |
3187 | bool pm_pg_lock, use_bank; |
3188 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3189 | |
3190 | if (size & 0x3 || *pos & 0x3) | |
3191 | return -EINVAL; | |
3192 | ||
394fdde2 TSD |
3193 | /* are we reading registers for which a PG lock is necessary? */ |
3194 | pm_pg_lock = (*pos >> 23) & 1; | |
3195 | ||
3196 | if (*pos & (1ULL << 62)) { | |
3197 | se_bank = (*pos >> 24) & 0x3FF; | |
3198 | sh_bank = (*pos >> 34) & 0x3FF; | |
3199 | instance_bank = (*pos >> 44) & 0x3FF; | |
3200 | ||
3201 | if (se_bank == 0x3FF) | |
3202 | se_bank = 0xFFFFFFFF; | |
3203 | if (sh_bank == 0x3FF) | |
3204 | sh_bank = 0xFFFFFFFF; | |
3205 | if (instance_bank == 0x3FF) | |
3206 | instance_bank = 0xFFFFFFFF; | |
3207 | use_bank = 1; | |
3208 | } else { | |
3209 | use_bank = 0; | |
3210 | } | |
3211 | ||
801a6aa9 | 3212 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3213 | |
3214 | if (use_bank) { | |
3215 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3216 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3217 | return -EINVAL; | |
3218 | mutex_lock(&adev->grbm_idx_mutex); | |
3219 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3220 | sh_bank, instance_bank); | |
3221 | } | |
3222 | ||
3223 | if (pm_pg_lock) | |
3224 | mutex_lock(&adev->pm.mutex); | |
3225 | ||
d38ceaf9 AD |
3226 | while (size) { |
3227 | uint32_t value; | |
3228 | ||
3229 | if (*pos > adev->rmmio_size) | |
3230 | return result; | |
3231 | ||
3232 | r = get_user(value, (uint32_t *)buf); | |
3233 | if (r) | |
3234 | return r; | |
3235 | ||
3236 | WREG32(*pos >> 2, value); | |
3237 | ||
3238 | result += 4; | |
3239 | buf += 4; | |
3240 | *pos += 4; | |
3241 | size -= 4; | |
3242 | } | |
3243 | ||
394fdde2 TSD |
3244 | if (use_bank) { |
3245 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3246 | mutex_unlock(&adev->grbm_idx_mutex); | |
3247 | } | |
3248 | ||
3249 | if (pm_pg_lock) | |
3250 | mutex_unlock(&adev->pm.mutex); | |
3251 | ||
d38ceaf9 AD |
3252 | return result; |
3253 | } | |
3254 | ||
adcec288 TSD |
3255 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3256 | size_t size, loff_t *pos) | |
3257 | { | |
45063097 | 3258 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3259 | ssize_t result = 0; |
3260 | int r; | |
3261 | ||
3262 | if (size & 0x3 || *pos & 0x3) | |
3263 | return -EINVAL; | |
3264 | ||
3265 | while (size) { | |
3266 | uint32_t value; | |
3267 | ||
3268 | value = RREG32_PCIE(*pos >> 2); | |
3269 | r = put_user(value, (uint32_t *)buf); | |
3270 | if (r) | |
3271 | return r; | |
3272 | ||
3273 | result += 4; | |
3274 | buf += 4; | |
3275 | *pos += 4; | |
3276 | size -= 4; | |
3277 | } | |
3278 | ||
3279 | return result; | |
3280 | } | |
3281 | ||
3282 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3283 | size_t size, loff_t *pos) | |
3284 | { | |
45063097 | 3285 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3286 | ssize_t result = 0; |
3287 | int r; | |
3288 | ||
3289 | if (size & 0x3 || *pos & 0x3) | |
3290 | return -EINVAL; | |
3291 | ||
3292 | while (size) { | |
3293 | uint32_t value; | |
3294 | ||
3295 | r = get_user(value, (uint32_t *)buf); | |
3296 | if (r) | |
3297 | return r; | |
3298 | ||
3299 | WREG32_PCIE(*pos >> 2, value); | |
3300 | ||
3301 | result += 4; | |
3302 | buf += 4; | |
3303 | *pos += 4; | |
3304 | size -= 4; | |
3305 | } | |
3306 | ||
3307 | return result; | |
3308 | } | |
3309 | ||
3310 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3311 | size_t size, loff_t *pos) | |
3312 | { | |
45063097 | 3313 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3314 | ssize_t result = 0; |
3315 | int r; | |
3316 | ||
3317 | if (size & 0x3 || *pos & 0x3) | |
3318 | return -EINVAL; | |
3319 | ||
3320 | while (size) { | |
3321 | uint32_t value; | |
3322 | ||
3323 | value = RREG32_DIDT(*pos >> 2); | |
3324 | r = put_user(value, (uint32_t *)buf); | |
3325 | if (r) | |
3326 | return r; | |
3327 | ||
3328 | result += 4; | |
3329 | buf += 4; | |
3330 | *pos += 4; | |
3331 | size -= 4; | |
3332 | } | |
3333 | ||
3334 | return result; | |
3335 | } | |
3336 | ||
3337 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3338 | size_t size, loff_t *pos) | |
3339 | { | |
45063097 | 3340 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3341 | ssize_t result = 0; |
3342 | int r; | |
3343 | ||
3344 | if (size & 0x3 || *pos & 0x3) | |
3345 | return -EINVAL; | |
3346 | ||
3347 | while (size) { | |
3348 | uint32_t value; | |
3349 | ||
3350 | r = get_user(value, (uint32_t *)buf); | |
3351 | if (r) | |
3352 | return r; | |
3353 | ||
3354 | WREG32_DIDT(*pos >> 2, value); | |
3355 | ||
3356 | result += 4; | |
3357 | buf += 4; | |
3358 | *pos += 4; | |
3359 | size -= 4; | |
3360 | } | |
3361 | ||
3362 | return result; | |
3363 | } | |
3364 | ||
3365 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3366 | size_t size, loff_t *pos) | |
3367 | { | |
45063097 | 3368 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3369 | ssize_t result = 0; |
3370 | int r; | |
3371 | ||
3372 | if (size & 0x3 || *pos & 0x3) | |
3373 | return -EINVAL; | |
3374 | ||
3375 | while (size) { | |
3376 | uint32_t value; | |
3377 | ||
6fc0deaf | 3378 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3379 | r = put_user(value, (uint32_t *)buf); |
3380 | if (r) | |
3381 | return r; | |
3382 | ||
3383 | result += 4; | |
3384 | buf += 4; | |
3385 | *pos += 4; | |
3386 | size -= 4; | |
3387 | } | |
3388 | ||
3389 | return result; | |
3390 | } | |
3391 | ||
3392 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3393 | size_t size, loff_t *pos) | |
3394 | { | |
45063097 | 3395 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3396 | ssize_t result = 0; |
3397 | int r; | |
3398 | ||
3399 | if (size & 0x3 || *pos & 0x3) | |
3400 | return -EINVAL; | |
3401 | ||
3402 | while (size) { | |
3403 | uint32_t value; | |
3404 | ||
3405 | r = get_user(value, (uint32_t *)buf); | |
3406 | if (r) | |
3407 | return r; | |
3408 | ||
6fc0deaf | 3409 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3410 | |
3411 | result += 4; | |
3412 | buf += 4; | |
3413 | *pos += 4; | |
3414 | size -= 4; | |
3415 | } | |
3416 | ||
3417 | return result; | |
3418 | } | |
3419 | ||
1e051413 TSD |
3420 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3421 | size_t size, loff_t *pos) | |
3422 | { | |
45063097 | 3423 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3424 | ssize_t result = 0; |
3425 | int r; | |
3426 | uint32_t *config, no_regs = 0; | |
3427 | ||
3428 | if (size & 0x3 || *pos & 0x3) | |
3429 | return -EINVAL; | |
3430 | ||
ecab7668 | 3431 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3432 | if (!config) |
3433 | return -ENOMEM; | |
3434 | ||
3435 | /* version, increment each time something is added */ | |
9a999359 | 3436 | config[no_regs++] = 3; |
1e051413 TSD |
3437 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3438 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3439 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3440 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3441 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3442 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3443 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3444 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3445 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3446 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3447 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3448 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3449 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3450 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3451 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3452 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3453 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3454 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3455 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3456 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3457 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3458 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3459 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3460 | ||
89a8f309 TSD |
3461 | /* rev==1 */ |
3462 | config[no_regs++] = adev->rev_id; | |
3463 | config[no_regs++] = adev->pg_flags; | |
3464 | config[no_regs++] = adev->cg_flags; | |
3465 | ||
e9f11dc8 TSD |
3466 | /* rev==2 */ |
3467 | config[no_regs++] = adev->family; | |
3468 | config[no_regs++] = adev->external_rev_id; | |
3469 | ||
9a999359 TSD |
3470 | /* rev==3 */ |
3471 | config[no_regs++] = adev->pdev->device; | |
3472 | config[no_regs++] = adev->pdev->revision; | |
3473 | config[no_regs++] = adev->pdev->subsystem_device; | |
3474 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3475 | ||
1e051413 TSD |
3476 | while (size && (*pos < no_regs * 4)) { |
3477 | uint32_t value; | |
3478 | ||
3479 | value = config[*pos >> 2]; | |
3480 | r = put_user(value, (uint32_t *)buf); | |
3481 | if (r) { | |
3482 | kfree(config); | |
3483 | return r; | |
3484 | } | |
3485 | ||
3486 | result += 4; | |
3487 | buf += 4; | |
3488 | *pos += 4; | |
3489 | size -= 4; | |
3490 | } | |
3491 | ||
3492 | kfree(config); | |
3493 | return result; | |
3494 | } | |
3495 | ||
f2cdaf20 TSD |
3496 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3497 | size_t size, loff_t *pos) | |
3498 | { | |
45063097 | 3499 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3500 | int idx, x, outsize, r, valuesize; |
3501 | uint32_t values[16]; | |
f2cdaf20 | 3502 | |
9f8df7d7 | 3503 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3504 | return -EINVAL; |
3505 | ||
3cbc614f SP |
3506 | if (amdgpu_dpm == 0) |
3507 | return -EINVAL; | |
3508 | ||
f2cdaf20 TSD |
3509 | /* convert offset to sensor number */ |
3510 | idx = *pos >> 2; | |
3511 | ||
9f8df7d7 | 3512 | valuesize = sizeof(values); |
f2cdaf20 | 3513 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
9f8df7d7 | 3514 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); |
3cbc614f SP |
3515 | else if (adev->pm.funcs && adev->pm.funcs->read_sensor) |
3516 | r = adev->pm.funcs->read_sensor(adev, idx, &values[0], | |
3517 | &valuesize); | |
f2cdaf20 TSD |
3518 | else |
3519 | return -EINVAL; | |
3520 | ||
9f8df7d7 TSD |
3521 | if (size > valuesize) |
3522 | return -EINVAL; | |
3523 | ||
3524 | outsize = 0; | |
3525 | x = 0; | |
3526 | if (!r) { | |
3527 | while (size) { | |
3528 | r = put_user(values[x++], (int32_t *)buf); | |
3529 | buf += 4; | |
3530 | size -= 4; | |
3531 | outsize += 4; | |
3532 | } | |
3533 | } | |
f2cdaf20 | 3534 | |
9f8df7d7 | 3535 | return !r ? outsize : r; |
f2cdaf20 | 3536 | } |
1e051413 | 3537 | |
273d7aa1 TSD |
3538 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3539 | size_t size, loff_t *pos) | |
3540 | { | |
3541 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3542 | int r, x; | |
3543 | ssize_t result=0; | |
472259f0 | 3544 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3545 | |
3546 | if (size & 3 || *pos & 3) | |
3547 | return -EINVAL; | |
3548 | ||
3549 | /* decode offset */ | |
3550 | offset = (*pos & 0x7F); | |
3551 | se = ((*pos >> 7) & 0xFF); | |
3552 | sh = ((*pos >> 15) & 0xFF); | |
3553 | cu = ((*pos >> 23) & 0xFF); | |
3554 | wave = ((*pos >> 31) & 0xFF); | |
3555 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
3556 | |
3557 | /* switch to the specific se/sh/cu */ | |
3558 | mutex_lock(&adev->grbm_idx_mutex); | |
3559 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3560 | ||
3561 | x = 0; | |
472259f0 TSD |
3562 | if (adev->gfx.funcs->read_wave_data) |
3563 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3564 | |
3565 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3566 | mutex_unlock(&adev->grbm_idx_mutex); | |
3567 | ||
5ecfb3b8 TSD |
3568 | if (!x) |
3569 | return -EINVAL; | |
3570 | ||
472259f0 | 3571 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3572 | uint32_t value; |
3573 | ||
472259f0 | 3574 | value = data[offset >> 2]; |
273d7aa1 TSD |
3575 | r = put_user(value, (uint32_t *)buf); |
3576 | if (r) | |
3577 | return r; | |
3578 | ||
3579 | result += 4; | |
3580 | buf += 4; | |
472259f0 | 3581 | offset += 4; |
273d7aa1 TSD |
3582 | size -= 4; |
3583 | } | |
3584 | ||
3585 | return result; | |
3586 | } | |
3587 | ||
c5a60ce8 TSD |
3588 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3589 | size_t size, loff_t *pos) | |
3590 | { | |
3591 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3592 | int r; | |
3593 | ssize_t result = 0; | |
3594 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3595 | ||
3596 | if (size & 3 || *pos & 3) | |
3597 | return -EINVAL; | |
3598 | ||
3599 | /* decode offset */ | |
3600 | offset = (*pos & 0xFFF); /* in dwords */ | |
3601 | se = ((*pos >> 12) & 0xFF); | |
3602 | sh = ((*pos >> 20) & 0xFF); | |
3603 | cu = ((*pos >> 28) & 0xFF); | |
3604 | wave = ((*pos >> 36) & 0xFF); | |
3605 | simd = ((*pos >> 44) & 0xFF); | |
3606 | thread = ((*pos >> 52) & 0xFF); | |
3607 | bank = ((*pos >> 60) & 1); | |
3608 | ||
3609 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3610 | if (!data) | |
3611 | return -ENOMEM; | |
3612 | ||
3613 | /* switch to the specific se/sh/cu */ | |
3614 | mutex_lock(&adev->grbm_idx_mutex); | |
3615 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3616 | ||
3617 | if (bank == 0) { | |
3618 | if (adev->gfx.funcs->read_wave_vgprs) | |
3619 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3620 | } else { | |
3621 | if (adev->gfx.funcs->read_wave_sgprs) | |
3622 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3623 | } | |
3624 | ||
3625 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3626 | mutex_unlock(&adev->grbm_idx_mutex); | |
3627 | ||
3628 | while (size) { | |
3629 | uint32_t value; | |
3630 | ||
3631 | value = data[offset++]; | |
3632 | r = put_user(value, (uint32_t *)buf); | |
3633 | if (r) { | |
3634 | result = r; | |
3635 | goto err; | |
3636 | } | |
3637 | ||
3638 | result += 4; | |
3639 | buf += 4; | |
3640 | size -= 4; | |
3641 | } | |
3642 | ||
3643 | err: | |
3644 | kfree(data); | |
3645 | return result; | |
3646 | } | |
3647 | ||
d38ceaf9 AD |
3648 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3649 | .owner = THIS_MODULE, | |
3650 | .read = amdgpu_debugfs_regs_read, | |
3651 | .write = amdgpu_debugfs_regs_write, | |
3652 | .llseek = default_llseek | |
3653 | }; | |
adcec288 TSD |
3654 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3655 | .owner = THIS_MODULE, | |
3656 | .read = amdgpu_debugfs_regs_didt_read, | |
3657 | .write = amdgpu_debugfs_regs_didt_write, | |
3658 | .llseek = default_llseek | |
3659 | }; | |
3660 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3661 | .owner = THIS_MODULE, | |
3662 | .read = amdgpu_debugfs_regs_pcie_read, | |
3663 | .write = amdgpu_debugfs_regs_pcie_write, | |
3664 | .llseek = default_llseek | |
3665 | }; | |
3666 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3667 | .owner = THIS_MODULE, | |
3668 | .read = amdgpu_debugfs_regs_smc_read, | |
3669 | .write = amdgpu_debugfs_regs_smc_write, | |
3670 | .llseek = default_llseek | |
3671 | }; | |
3672 | ||
1e051413 TSD |
3673 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3674 | .owner = THIS_MODULE, | |
3675 | .read = amdgpu_debugfs_gca_config_read, | |
3676 | .llseek = default_llseek | |
3677 | }; | |
3678 | ||
f2cdaf20 TSD |
3679 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3680 | .owner = THIS_MODULE, | |
3681 | .read = amdgpu_debugfs_sensor_read, | |
3682 | .llseek = default_llseek | |
3683 | }; | |
3684 | ||
273d7aa1 TSD |
3685 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3686 | .owner = THIS_MODULE, | |
3687 | .read = amdgpu_debugfs_wave_read, | |
3688 | .llseek = default_llseek | |
3689 | }; | |
c5a60ce8 TSD |
3690 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3691 | .owner = THIS_MODULE, | |
3692 | .read = amdgpu_debugfs_gpr_read, | |
3693 | .llseek = default_llseek | |
3694 | }; | |
273d7aa1 | 3695 | |
adcec288 TSD |
3696 | static const struct file_operations *debugfs_regs[] = { |
3697 | &amdgpu_debugfs_regs_fops, | |
3698 | &amdgpu_debugfs_regs_didt_fops, | |
3699 | &amdgpu_debugfs_regs_pcie_fops, | |
3700 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3701 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3702 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3703 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3704 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3705 | }; |
3706 | ||
3707 | static const char *debugfs_regs_names[] = { | |
3708 | "amdgpu_regs", | |
3709 | "amdgpu_regs_didt", | |
3710 | "amdgpu_regs_pcie", | |
3711 | "amdgpu_regs_smc", | |
1e051413 | 3712 | "amdgpu_gca_config", |
f2cdaf20 | 3713 | "amdgpu_sensors", |
273d7aa1 | 3714 | "amdgpu_wave", |
c5a60ce8 | 3715 | "amdgpu_gpr", |
adcec288 | 3716 | }; |
d38ceaf9 AD |
3717 | |
3718 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3719 | { | |
3720 | struct drm_minor *minor = adev->ddev->primary; | |
3721 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3722 | unsigned i, j; |
3723 | ||
3724 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3725 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3726 | S_IFREG | S_IRUGO, root, | |
3727 | adev, debugfs_regs[i]); | |
3728 | if (IS_ERR(ent)) { | |
3729 | for (j = 0; j < i; j++) { | |
3730 | debugfs_remove(adev->debugfs_regs[i]); | |
3731 | adev->debugfs_regs[i] = NULL; | |
3732 | } | |
3733 | return PTR_ERR(ent); | |
3734 | } | |
d38ceaf9 | 3735 | |
adcec288 TSD |
3736 | if (!i) |
3737 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3738 | adev->debugfs_regs[i] = ent; | |
3739 | } | |
d38ceaf9 AD |
3740 | |
3741 | return 0; | |
3742 | } | |
3743 | ||
3744 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3745 | { | |
adcec288 TSD |
3746 | unsigned i; |
3747 | ||
3748 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3749 | if (adev->debugfs_regs[i]) { | |
3750 | debugfs_remove(adev->debugfs_regs[i]); | |
3751 | adev->debugfs_regs[i] = NULL; | |
3752 | } | |
3753 | } | |
d38ceaf9 AD |
3754 | } |
3755 | ||
4f0955fc HR |
3756 | static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) |
3757 | { | |
3758 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3759 | struct drm_device *dev = node->minor->dev; | |
3760 | struct amdgpu_device *adev = dev->dev_private; | |
3761 | int r = 0, i; | |
3762 | ||
3763 | /* hold on the scheduler */ | |
3764 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3765 | struct amdgpu_ring *ring = adev->rings[i]; | |
3766 | ||
3767 | if (!ring || !ring->sched.thread) | |
3768 | continue; | |
3769 | kthread_park(ring->sched.thread); | |
3770 | } | |
3771 | ||
3772 | seq_printf(m, "run ib test:\n"); | |
3773 | r = amdgpu_ib_ring_tests(adev); | |
3774 | if (r) | |
3775 | seq_printf(m, "ib ring tests failed (%d).\n", r); | |
3776 | else | |
3777 | seq_printf(m, "ib ring tests passed.\n"); | |
3778 | ||
3779 | /* go on the scheduler */ | |
3780 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3781 | struct amdgpu_ring *ring = adev->rings[i]; | |
3782 | ||
3783 | if (!ring || !ring->sched.thread) | |
3784 | continue; | |
3785 | kthread_unpark(ring->sched.thread); | |
3786 | } | |
3787 | ||
3788 | return 0; | |
3789 | } | |
3790 | ||
3791 | static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { | |
3792 | {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} | |
3793 | }; | |
3794 | ||
3795 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) | |
3796 | { | |
3797 | return amdgpu_debugfs_add_files(adev, | |
3798 | amdgpu_debugfs_test_ib_ring_list, 1); | |
3799 | } | |
3800 | ||
d38ceaf9 AD |
3801 | int amdgpu_debugfs_init(struct drm_minor *minor) |
3802 | { | |
3803 | return 0; | |
3804 | } | |
7cebc728 | 3805 | #else |
27bad5b9 | 3806 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) |
4f0955fc HR |
3807 | { |
3808 | return 0; | |
3809 | } | |
7cebc728 AK |
3810 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) |
3811 | { | |
3812 | return 0; | |
3813 | } | |
3814 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3815 | #endif |