Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
4a74c38c | 33 | #include <linux/iommu.h> |
fdf2f6c5 | 34 | |
4562236b | 35 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 36 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
37 | #include <drm/amdgpu_drm.h> |
38 | #include <linux/vgaarb.h> | |
39 | #include <linux/vga_switcheroo.h> | |
40 | #include <linux/efi.h> | |
41 | #include "amdgpu.h" | |
f4b373f4 | 42 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
43 | #include "amdgpu_i2c.h" |
44 | #include "atom.h" | |
45 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 46 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 47 | #include "amd_pcie.h" |
33f34802 KW |
48 | #ifdef CONFIG_DRM_AMDGPU_SI |
49 | #include "si.h" | |
50 | #endif | |
a2e73f56 AD |
51 | #ifdef CONFIG_DRM_AMDGPU_CIK |
52 | #include "cik.h" | |
53 | #endif | |
aaa36a97 | 54 | #include "vi.h" |
460826e6 | 55 | #include "soc15.h" |
0a5b8c7b | 56 | #include "nv.h" |
d38ceaf9 | 57 | #include "bif/bif_4_1_d.h" |
9accf2fd | 58 | #include <linux/pci.h> |
bec86378 | 59 | #include <linux/firmware.h> |
89041940 | 60 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 61 | |
ba997709 | 62 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 63 | #include "amdgpu_pm.h" |
d38ceaf9 | 64 | |
5183411b | 65 | #include "amdgpu_xgmi.h" |
c030f2e4 | 66 | #include "amdgpu_ras.h" |
9c7c85f7 | 67 | #include "amdgpu_pmu.h" |
bd607166 | 68 | #include "amdgpu_fru_eeprom.h" |
04442bf7 | 69 | #include "amdgpu_reset.h" |
5183411b | 70 | |
d5ea093e | 71 | #include <linux/suspend.h> |
c6a6e2db | 72 | #include <drm/task_barrier.h> |
3f12acc8 | 73 | #include <linux/pm_runtime.h> |
d5ea093e | 74 | |
f89f8c6b AG |
75 | #include <drm/drm_drv.h> |
76 | ||
e2a75f88 | 77 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 78 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 79 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 80 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 81 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 82 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 83 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 84 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 85 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 86 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
4e52a9f8 | 87 | MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin"); |
8bf84f60 | 88 | MODULE_FIRMWARE("amdgpu/yellow_carp_gpu_info.bin"); |
e2a75f88 | 89 | |
2dc80b00 S |
90 | #define AMDGPU_RESUME_MS 2000 |
91 | ||
050091ab | 92 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
93 | "TAHITI", |
94 | "PITCAIRN", | |
95 | "VERDE", | |
96 | "OLAND", | |
97 | "HAINAN", | |
d38ceaf9 AD |
98 | "BONAIRE", |
99 | "KAVERI", | |
100 | "KABINI", | |
101 | "HAWAII", | |
102 | "MULLINS", | |
103 | "TOPAZ", | |
104 | "TONGA", | |
48299f95 | 105 | "FIJI", |
d38ceaf9 | 106 | "CARRIZO", |
139f4917 | 107 | "STONEY", |
2cc0c0b5 FC |
108 | "POLARIS10", |
109 | "POLARIS11", | |
c4642a47 | 110 | "POLARIS12", |
48ff108d | 111 | "VEGAM", |
d4196f01 | 112 | "VEGA10", |
8fab806a | 113 | "VEGA12", |
956fcddc | 114 | "VEGA20", |
2ca8a5d2 | 115 | "RAVEN", |
d6c3b24e | 116 | "ARCTURUS", |
1eee4228 | 117 | "RENOIR", |
d46b417a | 118 | "ALDEBARAN", |
852a6626 | 119 | "NAVI10", |
d0f56dc2 | 120 | "CYAN_SKILLFISH", |
87dbad02 | 121 | "NAVI14", |
9802f5d7 | 122 | "NAVI12", |
ccaf72d3 | 123 | "SIENNA_CICHLID", |
ddd8fbe7 | 124 | "NAVY_FLOUNDER", |
4f1e9a76 | 125 | "VANGOGH", |
a2468e04 | 126 | "DIMGREY_CAVEFISH", |
6f169591 | 127 | "BEIGE_GOBY", |
ee9236b7 | 128 | "YELLOW_CARP", |
3ae695d6 | 129 | "IP DISCOVERY", |
d38ceaf9 AD |
130 | "LAST", |
131 | }; | |
132 | ||
dcea6e65 KR |
133 | /** |
134 | * DOC: pcie_replay_count | |
135 | * | |
136 | * The amdgpu driver provides a sysfs API for reporting the total number | |
137 | * of PCIe replays (NAKs) | |
138 | * The file pcie_replay_count is used for this and returns the total | |
139 | * number of replays as a sum of the NAKs generated and NAKs received | |
140 | */ | |
141 | ||
142 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
143 | struct device_attribute *attr, char *buf) | |
144 | { | |
145 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 146 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
147 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
148 | ||
36000c7a | 149 | return sysfs_emit(buf, "%llu\n", cnt); |
dcea6e65 KR |
150 | } |
151 | ||
152 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
153 | amdgpu_device_get_pcie_replay_count, NULL); | |
154 | ||
5494d864 AD |
155 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
156 | ||
bd607166 KR |
157 | /** |
158 | * DOC: product_name | |
159 | * | |
160 | * The amdgpu driver provides a sysfs API for reporting the product name | |
161 | * for the device | |
162 | * The file serial_number is used for this and returns the product name | |
163 | * as returned from the FRU. | |
164 | * NOTE: This is only available for certain server cards | |
165 | */ | |
166 | ||
167 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
168 | struct device_attribute *attr, char *buf) | |
169 | { | |
170 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 171 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 172 | |
36000c7a | 173 | return sysfs_emit(buf, "%s\n", adev->product_name); |
bd607166 KR |
174 | } |
175 | ||
176 | static DEVICE_ATTR(product_name, S_IRUGO, | |
177 | amdgpu_device_get_product_name, NULL); | |
178 | ||
179 | /** | |
180 | * DOC: product_number | |
181 | * | |
182 | * The amdgpu driver provides a sysfs API for reporting the part number | |
183 | * for the device | |
184 | * The file serial_number is used for this and returns the part number | |
185 | * as returned from the FRU. | |
186 | * NOTE: This is only available for certain server cards | |
187 | */ | |
188 | ||
189 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
190 | struct device_attribute *attr, char *buf) | |
191 | { | |
192 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 193 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 194 | |
36000c7a | 195 | return sysfs_emit(buf, "%s\n", adev->product_number); |
bd607166 KR |
196 | } |
197 | ||
198 | static DEVICE_ATTR(product_number, S_IRUGO, | |
199 | amdgpu_device_get_product_number, NULL); | |
200 | ||
201 | /** | |
202 | * DOC: serial_number | |
203 | * | |
204 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
205 | * for the device | |
206 | * The file serial_number is used for this and returns the serial number | |
207 | * as returned from the FRU. | |
208 | * NOTE: This is only available for certain server cards | |
209 | */ | |
210 | ||
211 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
212 | struct device_attribute *attr, char *buf) | |
213 | { | |
214 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 215 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 216 | |
36000c7a | 217 | return sysfs_emit(buf, "%s\n", adev->serial); |
bd607166 KR |
218 | } |
219 | ||
220 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
221 | amdgpu_device_get_serial_number, NULL); | |
222 | ||
fd496ca8 | 223 | /** |
b98c6299 | 224 | * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control |
fd496ca8 AD |
225 | * |
226 | * @dev: drm_device pointer | |
227 | * | |
b98c6299 | 228 | * Returns true if the device is a dGPU with ATPX power control, |
fd496ca8 AD |
229 | * otherwise return false. |
230 | */ | |
b98c6299 | 231 | bool amdgpu_device_supports_px(struct drm_device *dev) |
fd496ca8 AD |
232 | { |
233 | struct amdgpu_device *adev = drm_to_adev(dev); | |
234 | ||
b98c6299 | 235 | if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid()) |
fd496ca8 AD |
236 | return true; |
237 | return false; | |
238 | } | |
239 | ||
e3ecdffa | 240 | /** |
0330b848 | 241 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
242 | * |
243 | * @dev: drm_device pointer | |
244 | * | |
b98c6299 | 245 | * Returns true if the device is a dGPU with ACPI power control, |
e3ecdffa AD |
246 | * otherwise return false. |
247 | */ | |
31af062a | 248 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 249 | { |
1348969a | 250 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 251 | |
b98c6299 AD |
252 | if (adev->has_pr3 || |
253 | ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid())) | |
d38ceaf9 AD |
254 | return true; |
255 | return false; | |
256 | } | |
257 | ||
a69cba42 AD |
258 | /** |
259 | * amdgpu_device_supports_baco - Does the device support BACO | |
260 | * | |
261 | * @dev: drm_device pointer | |
262 | * | |
263 | * Returns true if the device supporte BACO, | |
264 | * otherwise return false. | |
265 | */ | |
266 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
267 | { | |
1348969a | 268 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
269 | |
270 | return amdgpu_asic_supports_baco(adev); | |
271 | } | |
272 | ||
3fa8f89d S |
273 | /** |
274 | * amdgpu_device_supports_smart_shift - Is the device dGPU with | |
275 | * smart shift support | |
276 | * | |
277 | * @dev: drm_device pointer | |
278 | * | |
279 | * Returns true if the device is a dGPU with Smart Shift support, | |
280 | * otherwise returns false. | |
281 | */ | |
282 | bool amdgpu_device_supports_smart_shift(struct drm_device *dev) | |
283 | { | |
284 | return (amdgpu_device_supports_boco(dev) && | |
285 | amdgpu_acpi_is_power_shift_control_supported()); | |
286 | } | |
287 | ||
6e3cd2a9 MCC |
288 | /* |
289 | * VRAM access helper functions | |
290 | */ | |
291 | ||
e35e2b11 | 292 | /** |
048af66b | 293 | * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA |
e35e2b11 TY |
294 | * |
295 | * @adev: amdgpu_device pointer | |
296 | * @pos: offset of the buffer in vram | |
297 | * @buf: virtual address of the buffer in system memory | |
298 | * @size: read/write size, sizeof(@buf) must > @size | |
299 | * @write: true - write to vram, otherwise - read from vram | |
300 | */ | |
048af66b KW |
301 | void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, |
302 | void *buf, size_t size, bool write) | |
e35e2b11 | 303 | { |
e35e2b11 | 304 | unsigned long flags; |
048af66b KW |
305 | uint32_t hi = ~0, tmp = 0; |
306 | uint32_t *data = buf; | |
ce05ac56 | 307 | uint64_t last; |
f89f8c6b | 308 | int idx; |
ce05ac56 | 309 | |
c58a863b | 310 | if (!drm_dev_enter(adev_to_drm(adev), &idx)) |
f89f8c6b | 311 | return; |
9d11eb0d | 312 | |
048af66b KW |
313 | BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4)); |
314 | ||
315 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
316 | for (last = pos + size; pos < last; pos += 4) { | |
317 | tmp = pos >> 31; | |
318 | ||
319 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); | |
320 | if (tmp != hi) { | |
321 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
322 | hi = tmp; | |
323 | } | |
324 | if (write) | |
325 | WREG32_NO_KIQ(mmMM_DATA, *data++); | |
326 | else | |
327 | *data++ = RREG32_NO_KIQ(mmMM_DATA); | |
328 | } | |
329 | ||
330 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
331 | drm_dev_exit(idx); | |
332 | } | |
333 | ||
334 | /** | |
bbe04dec | 335 | * amdgpu_device_aper_access - access vram by vram aperature |
048af66b KW |
336 | * |
337 | * @adev: amdgpu_device pointer | |
338 | * @pos: offset of the buffer in vram | |
339 | * @buf: virtual address of the buffer in system memory | |
340 | * @size: read/write size, sizeof(@buf) must > @size | |
341 | * @write: true - write to vram, otherwise - read from vram | |
342 | * | |
343 | * The return value means how many bytes have been transferred. | |
344 | */ | |
345 | size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, | |
346 | void *buf, size_t size, bool write) | |
347 | { | |
9d11eb0d | 348 | #ifdef CONFIG_64BIT |
048af66b KW |
349 | void __iomem *addr; |
350 | size_t count = 0; | |
351 | uint64_t last; | |
352 | ||
353 | if (!adev->mman.aper_base_kaddr) | |
354 | return 0; | |
355 | ||
9d11eb0d CK |
356 | last = min(pos + size, adev->gmc.visible_vram_size); |
357 | if (last > pos) { | |
048af66b KW |
358 | addr = adev->mman.aper_base_kaddr + pos; |
359 | count = last - pos; | |
9d11eb0d CK |
360 | |
361 | if (write) { | |
362 | memcpy_toio(addr, buf, count); | |
363 | mb(); | |
810085dd | 364 | amdgpu_device_flush_hdp(adev, NULL); |
9d11eb0d | 365 | } else { |
810085dd | 366 | amdgpu_device_invalidate_hdp(adev, NULL); |
9d11eb0d CK |
367 | mb(); |
368 | memcpy_fromio(buf, addr, count); | |
369 | } | |
370 | ||
9d11eb0d | 371 | } |
048af66b KW |
372 | |
373 | return count; | |
374 | #else | |
375 | return 0; | |
9d11eb0d | 376 | #endif |
048af66b | 377 | } |
9d11eb0d | 378 | |
048af66b KW |
379 | /** |
380 | * amdgpu_device_vram_access - read/write a buffer in vram | |
381 | * | |
382 | * @adev: amdgpu_device pointer | |
383 | * @pos: offset of the buffer in vram | |
384 | * @buf: virtual address of the buffer in system memory | |
385 | * @size: read/write size, sizeof(@buf) must > @size | |
386 | * @write: true - write to vram, otherwise - read from vram | |
387 | */ | |
388 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
389 | void *buf, size_t size, bool write) | |
390 | { | |
391 | size_t count; | |
e35e2b11 | 392 | |
048af66b KW |
393 | /* try to using vram apreature to access vram first */ |
394 | count = amdgpu_device_aper_access(adev, pos, buf, size, write); | |
395 | size -= count; | |
396 | if (size) { | |
397 | /* using MM to access rest vram */ | |
398 | pos += count; | |
399 | buf += count; | |
400 | amdgpu_device_mm_access(adev, pos, buf, size, write); | |
e35e2b11 TY |
401 | } |
402 | } | |
403 | ||
d38ceaf9 | 404 | /* |
f7ee1874 | 405 | * register access helper functions. |
d38ceaf9 | 406 | */ |
56b53c0b DL |
407 | |
408 | /* Check if hw access should be skipped because of hotplug or device error */ | |
409 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
410 | { | |
7afefb81 | 411 | if (adev->no_hw_access) |
56b53c0b DL |
412 | return true; |
413 | ||
414 | #ifdef CONFIG_LOCKDEP | |
415 | /* | |
416 | * This is a bit complicated to understand, so worth a comment. What we assert | |
417 | * here is that the GPU reset is not running on another thread in parallel. | |
418 | * | |
419 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
420 | * we know that the reset is not running in paralell. | |
421 | * | |
422 | * If the trylock fails we assert that we are either already holding the read | |
423 | * side of the lock or are the reset thread itself and hold the write side of | |
424 | * the lock. | |
425 | */ | |
426 | if (in_task()) { | |
427 | if (down_read_trylock(&adev->reset_sem)) | |
428 | up_read(&adev->reset_sem); | |
429 | else | |
430 | lockdep_assert_held(&adev->reset_sem); | |
431 | } | |
432 | #endif | |
433 | return false; | |
434 | } | |
435 | ||
e3ecdffa | 436 | /** |
f7ee1874 | 437 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
438 | * |
439 | * @adev: amdgpu_device pointer | |
440 | * @reg: dword aligned register offset | |
441 | * @acc_flags: access flags which require special behavior | |
442 | * | |
443 | * Returns the 32 bit value from the offset specified. | |
444 | */ | |
f7ee1874 HZ |
445 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
446 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 447 | { |
f4b373f4 TSD |
448 | uint32_t ret; |
449 | ||
56b53c0b | 450 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
451 | return 0; |
452 | ||
f7ee1874 HZ |
453 | if ((reg * 4) < adev->rmmio_size) { |
454 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
455 | amdgpu_sriov_runtime(adev) && | |
456 | down_read_trylock(&adev->reset_sem)) { | |
457 | ret = amdgpu_kiq_rreg(adev, reg); | |
458 | up_read(&adev->reset_sem); | |
459 | } else { | |
460 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
461 | } | |
462 | } else { | |
463 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 464 | } |
bc992ba5 | 465 | |
f7ee1874 | 466 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 467 | |
f4b373f4 | 468 | return ret; |
d38ceaf9 AD |
469 | } |
470 | ||
421a2a30 ML |
471 | /* |
472 | * MMIO register read with bytes helper functions | |
473 | * @offset:bytes offset from MMIO start | |
474 | * | |
475 | */ | |
476 | ||
e3ecdffa AD |
477 | /** |
478 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
479 | * | |
480 | * @adev: amdgpu_device pointer | |
481 | * @offset: byte aligned register offset | |
482 | * | |
483 | * Returns the 8 bit value from the offset specified. | |
484 | */ | |
7cbbc745 AG |
485 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
486 | { | |
56b53c0b | 487 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
488 | return 0; |
489 | ||
421a2a30 ML |
490 | if (offset < adev->rmmio_size) |
491 | return (readb(adev->rmmio + offset)); | |
492 | BUG(); | |
493 | } | |
494 | ||
495 | /* | |
496 | * MMIO register write with bytes helper functions | |
497 | * @offset:bytes offset from MMIO start | |
498 | * @value: the value want to be written to the register | |
499 | * | |
500 | */ | |
e3ecdffa AD |
501 | /** |
502 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
503 | * | |
504 | * @adev: amdgpu_device pointer | |
505 | * @offset: byte aligned register offset | |
506 | * @value: 8 bit value to write | |
507 | * | |
508 | * Writes the value specified to the offset specified. | |
509 | */ | |
7cbbc745 AG |
510 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
511 | { | |
56b53c0b | 512 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
513 | return; |
514 | ||
421a2a30 ML |
515 | if (offset < adev->rmmio_size) |
516 | writeb(value, adev->rmmio + offset); | |
517 | else | |
518 | BUG(); | |
519 | } | |
520 | ||
e3ecdffa | 521 | /** |
f7ee1874 | 522 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
523 | * |
524 | * @adev: amdgpu_device pointer | |
525 | * @reg: dword aligned register offset | |
526 | * @v: 32 bit value to write to the register | |
527 | * @acc_flags: access flags which require special behavior | |
528 | * | |
529 | * Writes the value specified to the offset specified. | |
530 | */ | |
f7ee1874 HZ |
531 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
532 | uint32_t reg, uint32_t v, | |
533 | uint32_t acc_flags) | |
d38ceaf9 | 534 | { |
56b53c0b | 535 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
536 | return; |
537 | ||
f7ee1874 HZ |
538 | if ((reg * 4) < adev->rmmio_size) { |
539 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
540 | amdgpu_sriov_runtime(adev) && | |
541 | down_read_trylock(&adev->reset_sem)) { | |
542 | amdgpu_kiq_wreg(adev, reg, v); | |
543 | up_read(&adev->reset_sem); | |
544 | } else { | |
545 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
546 | } | |
547 | } else { | |
548 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 549 | } |
bc992ba5 | 550 | |
f7ee1874 | 551 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 552 | } |
d38ceaf9 | 553 | |
03f2abb0 | 554 | /** |
2e0cc4d4 ML |
555 | * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range |
556 | * | |
557 | * this function is invoked only the debugfs register access | |
03f2abb0 | 558 | */ |
f7ee1874 HZ |
559 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
560 | uint32_t reg, uint32_t v) | |
2e0cc4d4 | 561 | { |
56b53c0b | 562 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
563 | return; |
564 | ||
2e0cc4d4 | 565 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
566 | adev->gfx.rlc.funcs && |
567 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 | 568 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
1a4772d9 | 569 | return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 0); |
f7ee1874 HZ |
570 | } else { |
571 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 572 | } |
d38ceaf9 AD |
573 | } |
574 | ||
d38ceaf9 AD |
575 | /** |
576 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
577 | * | |
578 | * @adev: amdgpu_device pointer | |
579 | * @index: doorbell index | |
580 | * | |
581 | * Returns the value in the doorbell aperture at the | |
582 | * requested doorbell index (CIK). | |
583 | */ | |
584 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
585 | { | |
56b53c0b | 586 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
587 | return 0; |
588 | ||
d38ceaf9 AD |
589 | if (index < adev->doorbell.num_doorbells) { |
590 | return readl(adev->doorbell.ptr + index); | |
591 | } else { | |
592 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
593 | return 0; | |
594 | } | |
595 | } | |
596 | ||
597 | /** | |
598 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
599 | * | |
600 | * @adev: amdgpu_device pointer | |
601 | * @index: doorbell index | |
602 | * @v: value to write | |
603 | * | |
604 | * Writes @v to the doorbell aperture at the | |
605 | * requested doorbell index (CIK). | |
606 | */ | |
607 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
608 | { | |
56b53c0b | 609 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
610 | return; |
611 | ||
d38ceaf9 AD |
612 | if (index < adev->doorbell.num_doorbells) { |
613 | writel(v, adev->doorbell.ptr + index); | |
614 | } else { | |
615 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
616 | } | |
617 | } | |
618 | ||
832be404 KW |
619 | /** |
620 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
621 | * | |
622 | * @adev: amdgpu_device pointer | |
623 | * @index: doorbell index | |
624 | * | |
625 | * Returns the value in the doorbell aperture at the | |
626 | * requested doorbell index (VEGA10+). | |
627 | */ | |
628 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
629 | { | |
56b53c0b | 630 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
631 | return 0; |
632 | ||
832be404 KW |
633 | if (index < adev->doorbell.num_doorbells) { |
634 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
635 | } else { | |
636 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
637 | return 0; | |
638 | } | |
639 | } | |
640 | ||
641 | /** | |
642 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
643 | * | |
644 | * @adev: amdgpu_device pointer | |
645 | * @index: doorbell index | |
646 | * @v: value to write | |
647 | * | |
648 | * Writes @v to the doorbell aperture at the | |
649 | * requested doorbell index (VEGA10+). | |
650 | */ | |
651 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
652 | { | |
56b53c0b | 653 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
654 | return; |
655 | ||
832be404 KW |
656 | if (index < adev->doorbell.num_doorbells) { |
657 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
658 | } else { | |
659 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
660 | } | |
661 | } | |
662 | ||
1bba3683 HZ |
663 | /** |
664 | * amdgpu_device_indirect_rreg - read an indirect register | |
665 | * | |
666 | * @adev: amdgpu_device pointer | |
667 | * @pcie_index: mmio register offset | |
668 | * @pcie_data: mmio register offset | |
22f453fb | 669 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
670 | * |
671 | * Returns the value of indirect register @reg_addr | |
672 | */ | |
673 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
674 | u32 pcie_index, u32 pcie_data, | |
675 | u32 reg_addr) | |
676 | { | |
677 | unsigned long flags; | |
678 | u32 r; | |
679 | void __iomem *pcie_index_offset; | |
680 | void __iomem *pcie_data_offset; | |
681 | ||
682 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
683 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
684 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
685 | ||
686 | writel(reg_addr, pcie_index_offset); | |
687 | readl(pcie_index_offset); | |
688 | r = readl(pcie_data_offset); | |
689 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
690 | ||
691 | return r; | |
692 | } | |
693 | ||
694 | /** | |
695 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
696 | * | |
697 | * @adev: amdgpu_device pointer | |
698 | * @pcie_index: mmio register offset | |
699 | * @pcie_data: mmio register offset | |
22f453fb | 700 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
701 | * |
702 | * Returns the value of indirect register @reg_addr | |
703 | */ | |
704 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
705 | u32 pcie_index, u32 pcie_data, | |
706 | u32 reg_addr) | |
707 | { | |
708 | unsigned long flags; | |
709 | u64 r; | |
710 | void __iomem *pcie_index_offset; | |
711 | void __iomem *pcie_data_offset; | |
712 | ||
713 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
714 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
715 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
716 | ||
717 | /* read low 32 bits */ | |
718 | writel(reg_addr, pcie_index_offset); | |
719 | readl(pcie_index_offset); | |
720 | r = readl(pcie_data_offset); | |
721 | /* read high 32 bits */ | |
722 | writel(reg_addr + 4, pcie_index_offset); | |
723 | readl(pcie_index_offset); | |
724 | r |= ((u64)readl(pcie_data_offset) << 32); | |
725 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
726 | ||
727 | return r; | |
728 | } | |
729 | ||
730 | /** | |
731 | * amdgpu_device_indirect_wreg - write an indirect register address | |
732 | * | |
733 | * @adev: amdgpu_device pointer | |
734 | * @pcie_index: mmio register offset | |
735 | * @pcie_data: mmio register offset | |
736 | * @reg_addr: indirect register offset | |
737 | * @reg_data: indirect register data | |
738 | * | |
739 | */ | |
740 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
741 | u32 pcie_index, u32 pcie_data, | |
742 | u32 reg_addr, u32 reg_data) | |
743 | { | |
744 | unsigned long flags; | |
745 | void __iomem *pcie_index_offset; | |
746 | void __iomem *pcie_data_offset; | |
747 | ||
748 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
749 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
750 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
751 | ||
752 | writel(reg_addr, pcie_index_offset); | |
753 | readl(pcie_index_offset); | |
754 | writel(reg_data, pcie_data_offset); | |
755 | readl(pcie_data_offset); | |
756 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
757 | } | |
758 | ||
759 | /** | |
760 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
761 | * | |
762 | * @adev: amdgpu_device pointer | |
763 | * @pcie_index: mmio register offset | |
764 | * @pcie_data: mmio register offset | |
765 | * @reg_addr: indirect register offset | |
766 | * @reg_data: indirect register data | |
767 | * | |
768 | */ | |
769 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
770 | u32 pcie_index, u32 pcie_data, | |
771 | u32 reg_addr, u64 reg_data) | |
772 | { | |
773 | unsigned long flags; | |
774 | void __iomem *pcie_index_offset; | |
775 | void __iomem *pcie_data_offset; | |
776 | ||
777 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
778 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
779 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
780 | ||
781 | /* write low 32 bits */ | |
782 | writel(reg_addr, pcie_index_offset); | |
783 | readl(pcie_index_offset); | |
784 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
785 | readl(pcie_data_offset); | |
786 | /* write high 32 bits */ | |
787 | writel(reg_addr + 4, pcie_index_offset); | |
788 | readl(pcie_index_offset); | |
789 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
790 | readl(pcie_data_offset); | |
791 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
792 | } | |
793 | ||
d38ceaf9 AD |
794 | /** |
795 | * amdgpu_invalid_rreg - dummy reg read function | |
796 | * | |
982a820b | 797 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
798 | * @reg: offset of register |
799 | * | |
800 | * Dummy register read function. Used for register blocks | |
801 | * that certain asics don't have (all asics). | |
802 | * Returns the value in the register. | |
803 | */ | |
804 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
805 | { | |
806 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
807 | BUG(); | |
808 | return 0; | |
809 | } | |
810 | ||
811 | /** | |
812 | * amdgpu_invalid_wreg - dummy reg write function | |
813 | * | |
982a820b | 814 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
815 | * @reg: offset of register |
816 | * @v: value to write to the register | |
817 | * | |
818 | * Dummy register read function. Used for register blocks | |
819 | * that certain asics don't have (all asics). | |
820 | */ | |
821 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
822 | { | |
823 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
824 | reg, v); | |
825 | BUG(); | |
826 | } | |
827 | ||
4fa1c6a6 TZ |
828 | /** |
829 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
830 | * | |
982a820b | 831 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
832 | * @reg: offset of register |
833 | * | |
834 | * Dummy register read function. Used for register blocks | |
835 | * that certain asics don't have (all asics). | |
836 | * Returns the value in the register. | |
837 | */ | |
838 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
839 | { | |
840 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
841 | BUG(); | |
842 | return 0; | |
843 | } | |
844 | ||
845 | /** | |
846 | * amdgpu_invalid_wreg64 - dummy reg write function | |
847 | * | |
982a820b | 848 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
849 | * @reg: offset of register |
850 | * @v: value to write to the register | |
851 | * | |
852 | * Dummy register read function. Used for register blocks | |
853 | * that certain asics don't have (all asics). | |
854 | */ | |
855 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
856 | { | |
857 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
858 | reg, v); | |
859 | BUG(); | |
860 | } | |
861 | ||
d38ceaf9 AD |
862 | /** |
863 | * amdgpu_block_invalid_rreg - dummy reg read function | |
864 | * | |
982a820b | 865 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
866 | * @block: offset of instance |
867 | * @reg: offset of register | |
868 | * | |
869 | * Dummy register read function. Used for register blocks | |
870 | * that certain asics don't have (all asics). | |
871 | * Returns the value in the register. | |
872 | */ | |
873 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
874 | uint32_t block, uint32_t reg) | |
875 | { | |
876 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
877 | reg, block); | |
878 | BUG(); | |
879 | return 0; | |
880 | } | |
881 | ||
882 | /** | |
883 | * amdgpu_block_invalid_wreg - dummy reg write function | |
884 | * | |
982a820b | 885 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
886 | * @block: offset of instance |
887 | * @reg: offset of register | |
888 | * @v: value to write to the register | |
889 | * | |
890 | * Dummy register read function. Used for register blocks | |
891 | * that certain asics don't have (all asics). | |
892 | */ | |
893 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
894 | uint32_t block, | |
895 | uint32_t reg, uint32_t v) | |
896 | { | |
897 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
898 | reg, block, v); | |
899 | BUG(); | |
900 | } | |
901 | ||
4d2997ab AD |
902 | /** |
903 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
904 | * | |
982a820b | 905 | * @adev: amdgpu_device pointer |
4d2997ab AD |
906 | * |
907 | * Does any asic specific work and then calls atom asic init. | |
908 | */ | |
909 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
910 | { | |
911 | amdgpu_asic_pre_asic_init(adev); | |
912 | ||
913 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
914 | } | |
915 | ||
e3ecdffa AD |
916 | /** |
917 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
918 | * | |
982a820b | 919 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
920 | * |
921 | * Allocates a scratch page of VRAM for use by various things in the | |
922 | * driver. | |
923 | */ | |
06ec9070 | 924 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 925 | { |
a4a02777 CK |
926 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
927 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
928 | &adev->vram_scratch.robj, | |
929 | &adev->vram_scratch.gpu_addr, | |
930 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
931 | } |
932 | ||
e3ecdffa AD |
933 | /** |
934 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
935 | * | |
982a820b | 936 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
937 | * |
938 | * Frees the VRAM scratch page. | |
939 | */ | |
06ec9070 | 940 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 941 | { |
078af1a3 | 942 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
943 | } |
944 | ||
945 | /** | |
9c3f2b54 | 946 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
947 | * |
948 | * @adev: amdgpu_device pointer | |
949 | * @registers: pointer to the register array | |
950 | * @array_size: size of the register array | |
951 | * | |
952 | * Programs an array or registers with and and or masks. | |
953 | * This is a helper for setting golden registers. | |
954 | */ | |
9c3f2b54 AD |
955 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
956 | const u32 *registers, | |
957 | const u32 array_size) | |
d38ceaf9 AD |
958 | { |
959 | u32 tmp, reg, and_mask, or_mask; | |
960 | int i; | |
961 | ||
962 | if (array_size % 3) | |
963 | return; | |
964 | ||
965 | for (i = 0; i < array_size; i +=3) { | |
966 | reg = registers[i + 0]; | |
967 | and_mask = registers[i + 1]; | |
968 | or_mask = registers[i + 2]; | |
969 | ||
970 | if (and_mask == 0xffffffff) { | |
971 | tmp = or_mask; | |
972 | } else { | |
973 | tmp = RREG32(reg); | |
974 | tmp &= ~and_mask; | |
e0d07657 HZ |
975 | if (adev->family >= AMDGPU_FAMILY_AI) |
976 | tmp |= (or_mask & and_mask); | |
977 | else | |
978 | tmp |= or_mask; | |
d38ceaf9 AD |
979 | } |
980 | WREG32(reg, tmp); | |
981 | } | |
982 | } | |
983 | ||
e3ecdffa AD |
984 | /** |
985 | * amdgpu_device_pci_config_reset - reset the GPU | |
986 | * | |
987 | * @adev: amdgpu_device pointer | |
988 | * | |
989 | * Resets the GPU using the pci config reset sequence. | |
990 | * Only applicable to asics prior to vega10. | |
991 | */ | |
8111c387 | 992 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
993 | { |
994 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
995 | } | |
996 | ||
af484df8 AD |
997 | /** |
998 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
999 | * | |
1000 | * @adev: amdgpu_device pointer | |
1001 | * | |
1002 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
1003 | */ | |
1004 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
1005 | { | |
1006 | return pci_reset_function(adev->pdev); | |
1007 | } | |
1008 | ||
d38ceaf9 AD |
1009 | /* |
1010 | * GPU doorbell aperture helpers function. | |
1011 | */ | |
1012 | /** | |
06ec9070 | 1013 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
1014 | * |
1015 | * @adev: amdgpu_device pointer | |
1016 | * | |
1017 | * Init doorbell driver information (CIK) | |
1018 | * Returns 0 on success, error on failure. | |
1019 | */ | |
06ec9070 | 1020 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 1021 | { |
6585661d | 1022 | |
705e519e CK |
1023 | /* No doorbell on SI hardware generation */ |
1024 | if (adev->asic_type < CHIP_BONAIRE) { | |
1025 | adev->doorbell.base = 0; | |
1026 | adev->doorbell.size = 0; | |
1027 | adev->doorbell.num_doorbells = 0; | |
1028 | adev->doorbell.ptr = NULL; | |
1029 | return 0; | |
1030 | } | |
1031 | ||
d6895ad3 CK |
1032 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
1033 | return -EINVAL; | |
1034 | ||
22357775 AD |
1035 | amdgpu_asic_init_doorbell_index(adev); |
1036 | ||
d38ceaf9 AD |
1037 | /* doorbell bar mapping */ |
1038 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
1039 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
1040 | ||
edf600da | 1041 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 1042 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
1043 | if (adev->doorbell.num_doorbells == 0) |
1044 | return -EINVAL; | |
1045 | ||
ec3db8a6 | 1046 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
1047 | * paging queue doorbell use the second page. The |
1048 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
1049 | * doorbells are in the first page. So with paging queue enabled, | |
1050 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
1051 | */ |
1052 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 1053 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 1054 | |
8972e5d2 CK |
1055 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
1056 | adev->doorbell.num_doorbells * | |
1057 | sizeof(u32)); | |
1058 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 1059 | return -ENOMEM; |
d38ceaf9 AD |
1060 | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | /** | |
06ec9070 | 1065 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
1066 | * |
1067 | * @adev: amdgpu_device pointer | |
1068 | * | |
1069 | * Tear down doorbell driver information (CIK) | |
1070 | */ | |
06ec9070 | 1071 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1072 | { |
1073 | iounmap(adev->doorbell.ptr); | |
1074 | adev->doorbell.ptr = NULL; | |
1075 | } | |
1076 | ||
22cb0164 | 1077 | |
d38ceaf9 AD |
1078 | |
1079 | /* | |
06ec9070 | 1080 | * amdgpu_device_wb_*() |
455a7bc2 | 1081 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1082 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1083 | */ |
1084 | ||
1085 | /** | |
06ec9070 | 1086 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1087 | * |
1088 | * @adev: amdgpu_device pointer | |
1089 | * | |
1090 | * Disables Writeback and frees the Writeback memory (all asics). | |
1091 | * Used at driver shutdown. | |
1092 | */ | |
06ec9070 | 1093 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1094 | { |
1095 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1096 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1097 | &adev->wb.gpu_addr, | |
1098 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1099 | adev->wb.wb_obj = NULL; |
1100 | } | |
1101 | } | |
1102 | ||
1103 | /** | |
03f2abb0 | 1104 | * amdgpu_device_wb_init - Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1105 | * |
1106 | * @adev: amdgpu_device pointer | |
1107 | * | |
455a7bc2 | 1108 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1109 | * Used at driver startup. |
1110 | * Returns 0 on success or an -error on failure. | |
1111 | */ | |
06ec9070 | 1112 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1113 | { |
1114 | int r; | |
1115 | ||
1116 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1117 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1118 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1119 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1120 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1121 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1122 | if (r) { |
1123 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1124 | return r; | |
1125 | } | |
d38ceaf9 AD |
1126 | |
1127 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1128 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1129 | ||
1130 | /* clear wb memory */ | |
73469585 | 1131 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1132 | } |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | /** | |
131b4b36 | 1138 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1139 | * |
1140 | * @adev: amdgpu_device pointer | |
1141 | * @wb: wb index | |
1142 | * | |
1143 | * Allocate a wb slot for use by the driver (all asics). | |
1144 | * Returns 0 on success or -EINVAL on failure. | |
1145 | */ | |
131b4b36 | 1146 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1147 | { |
1148 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1149 | |
97407b63 | 1150 | if (offset < adev->wb.num_wb) { |
7014285a | 1151 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1152 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1153 | return 0; |
1154 | } else { | |
1155 | return -EINVAL; | |
1156 | } | |
1157 | } | |
1158 | ||
d38ceaf9 | 1159 | /** |
131b4b36 | 1160 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1161 | * |
1162 | * @adev: amdgpu_device pointer | |
1163 | * @wb: wb index | |
1164 | * | |
1165 | * Free a wb slot allocated for use by the driver (all asics) | |
1166 | */ | |
131b4b36 | 1167 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1168 | { |
73469585 | 1169 | wb >>= 3; |
d38ceaf9 | 1170 | if (wb < adev->wb.num_wb) |
73469585 | 1171 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1172 | } |
1173 | ||
d6895ad3 CK |
1174 | /** |
1175 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1176 | * | |
1177 | * @adev: amdgpu_device pointer | |
1178 | * | |
1179 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1180 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1181 | * driver loading by returning -ENODEV. | |
1182 | */ | |
1183 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1184 | { | |
453f617a | 1185 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1186 | struct pci_bus *root; |
1187 | struct resource *res; | |
1188 | unsigned i; | |
d6895ad3 CK |
1189 | u16 cmd; |
1190 | int r; | |
1191 | ||
0c03b912 | 1192 | /* Bypass for VF */ |
1193 | if (amdgpu_sriov_vf(adev)) | |
1194 | return 0; | |
1195 | ||
b7221f2b AD |
1196 | /* skip if the bios has already enabled large BAR */ |
1197 | if (adev->gmc.real_vram_size && | |
1198 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1199 | return 0; | |
1200 | ||
31b8adab CK |
1201 | /* Check if the root BUS has 64bit memory resources */ |
1202 | root = adev->pdev->bus; | |
1203 | while (root->parent) | |
1204 | root = root->parent; | |
1205 | ||
1206 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1207 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1208 | res->start > 0x100000000ull) |
1209 | break; | |
1210 | } | |
1211 | ||
1212 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1213 | if (!res) | |
1214 | return 0; | |
1215 | ||
453f617a ND |
1216 | /* Limit the BAR size to what is available */ |
1217 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1218 | rbar_size); | |
1219 | ||
d6895ad3 CK |
1220 | /* Disable memory decoding while we change the BAR addresses and size */ |
1221 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1222 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1223 | cmd & ~PCI_COMMAND_MEMORY); | |
1224 | ||
1225 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 1226 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
1227 | if (adev->asic_type >= CHIP_BONAIRE) |
1228 | pci_release_resource(adev->pdev, 2); | |
1229 | ||
1230 | pci_release_resource(adev->pdev, 0); | |
1231 | ||
1232 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1233 | if (r == -ENOSPC) | |
1234 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1235 | else if (r && r != -ENOTSUPP) | |
1236 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1237 | ||
1238 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1239 | ||
1240 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1241 | * using the device. | |
1242 | */ | |
06ec9070 | 1243 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
1244 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1245 | return -ENODEV; | |
1246 | ||
1247 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1248 | ||
1249 | return 0; | |
1250 | } | |
a05502e5 | 1251 | |
d38ceaf9 AD |
1252 | /* |
1253 | * GPU helpers function. | |
1254 | */ | |
1255 | /** | |
39c640c0 | 1256 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1257 | * |
1258 | * @adev: amdgpu_device pointer | |
1259 | * | |
c836fec5 JQ |
1260 | * Check if the asic has been initialized (all asics) at driver startup |
1261 | * or post is needed if hw reset is performed. | |
1262 | * Returns true if need or false if not. | |
d38ceaf9 | 1263 | */ |
39c640c0 | 1264 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1265 | { |
1266 | uint32_t reg; | |
1267 | ||
bec86378 ML |
1268 | if (amdgpu_sriov_vf(adev)) |
1269 | return false; | |
1270 | ||
1271 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1272 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1273 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1274 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1275 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1276 | */ |
1277 | if (adev->asic_type == CHIP_FIJI) { | |
1278 | int err; | |
1279 | uint32_t fw_ver; | |
1280 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1281 | /* force vPost if error occured */ | |
1282 | if (err) | |
1283 | return true; | |
1284 | ||
1285 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1286 | if (fw_ver < 0x00160e00) |
1287 | return true; | |
bec86378 | 1288 | } |
bec86378 | 1289 | } |
91fe77eb | 1290 | |
e3c1b071 | 1291 | /* Don't post if we need to reset whole hive on init */ |
1292 | if (adev->gmc.xgmi.pending_reset) | |
1293 | return false; | |
1294 | ||
91fe77eb | 1295 | if (adev->has_hw_reset) { |
1296 | adev->has_hw_reset = false; | |
1297 | return true; | |
1298 | } | |
1299 | ||
1300 | /* bios scratch used on CIK+ */ | |
1301 | if (adev->asic_type >= CHIP_BONAIRE) | |
1302 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1303 | ||
1304 | /* check MEM_SIZE for older asics */ | |
1305 | reg = amdgpu_asic_get_config_memsize(adev); | |
1306 | ||
1307 | if ((reg != 0) && (reg != 0xffffffff)) | |
1308 | return false; | |
1309 | ||
1310 | return true; | |
bec86378 ML |
1311 | } |
1312 | ||
d38ceaf9 AD |
1313 | /* if we get transitioned to only one device, take VGA back */ |
1314 | /** | |
06ec9070 | 1315 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 | 1316 | * |
bf44e8ce | 1317 | * @pdev: PCI device pointer |
d38ceaf9 AD |
1318 | * @state: enable/disable vga decode |
1319 | * | |
1320 | * Enable/disable vga decode (all asics). | |
1321 | * Returns VGA resource flags. | |
1322 | */ | |
bf44e8ce CH |
1323 | static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, |
1324 | bool state) | |
d38ceaf9 | 1325 | { |
bf44e8ce | 1326 | struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); |
d38ceaf9 AD |
1327 | amdgpu_asic_set_vga_state(adev, state); |
1328 | if (state) | |
1329 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1330 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1331 | else | |
1332 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1333 | } | |
1334 | ||
e3ecdffa AD |
1335 | /** |
1336 | * amdgpu_device_check_block_size - validate the vm block size | |
1337 | * | |
1338 | * @adev: amdgpu_device pointer | |
1339 | * | |
1340 | * Validates the vm block size specified via module parameter. | |
1341 | * The vm block size defines number of bits in page table versus page directory, | |
1342 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1343 | * page table and the remaining bits are in the page directory. | |
1344 | */ | |
06ec9070 | 1345 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1346 | { |
1347 | /* defines number of bits in page table versus page directory, | |
1348 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1349 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1350 | if (amdgpu_vm_block_size == -1) |
1351 | return; | |
a1adf8be | 1352 | |
bab4fee7 | 1353 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1354 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1355 | amdgpu_vm_block_size); | |
97489129 | 1356 | amdgpu_vm_block_size = -1; |
a1adf8be | 1357 | } |
a1adf8be CZ |
1358 | } |
1359 | ||
e3ecdffa AD |
1360 | /** |
1361 | * amdgpu_device_check_vm_size - validate the vm size | |
1362 | * | |
1363 | * @adev: amdgpu_device pointer | |
1364 | * | |
1365 | * Validates the vm size in GB specified via module parameter. | |
1366 | * The VM size is the size of the GPU virtual memory space in GB. | |
1367 | */ | |
06ec9070 | 1368 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1369 | { |
64dab074 AD |
1370 | /* no need to check the default value */ |
1371 | if (amdgpu_vm_size == -1) | |
1372 | return; | |
1373 | ||
83ca145d ZJ |
1374 | if (amdgpu_vm_size < 1) { |
1375 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1376 | amdgpu_vm_size); | |
f3368128 | 1377 | amdgpu_vm_size = -1; |
83ca145d | 1378 | } |
83ca145d ZJ |
1379 | } |
1380 | ||
7951e376 RZ |
1381 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1382 | { | |
1383 | struct sysinfo si; | |
a9d4fe2f | 1384 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1385 | uint64_t total_memory; |
1386 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1387 | uint64_t dram_size_three_GB = 0xB8000000; | |
1388 | ||
1389 | if (amdgpu_smu_memory_pool_size == 0) | |
1390 | return; | |
1391 | ||
1392 | if (!is_os_64) { | |
1393 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1394 | goto def_value; | |
1395 | } | |
1396 | si_meminfo(&si); | |
1397 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1398 | ||
1399 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1400 | (amdgpu_smu_memory_pool_size == 2)) { | |
1401 | if (total_memory < dram_size_three_GB) | |
1402 | goto def_value1; | |
1403 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1404 | (amdgpu_smu_memory_pool_size == 8)) { | |
1405 | if (total_memory < dram_size_seven_GB) | |
1406 | goto def_value1; | |
1407 | } else { | |
1408 | DRM_WARN("Smu memory pool size not supported\n"); | |
1409 | goto def_value; | |
1410 | } | |
1411 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1412 | ||
1413 | return; | |
1414 | ||
1415 | def_value1: | |
1416 | DRM_WARN("No enough system memory\n"); | |
1417 | def_value: | |
1418 | adev->pm.smu_prv_buffer_size = 0; | |
1419 | } | |
1420 | ||
9f6a7857 HR |
1421 | static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) |
1422 | { | |
1423 | if (!(adev->flags & AMD_IS_APU) || | |
1424 | adev->asic_type < CHIP_RAVEN) | |
1425 | return 0; | |
1426 | ||
1427 | switch (adev->asic_type) { | |
1428 | case CHIP_RAVEN: | |
1429 | if (adev->pdev->device == 0x15dd) | |
1430 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1431 | if (adev->pdev->device == 0x15d8) | |
1432 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
1433 | break; | |
1434 | case CHIP_RENOIR: | |
1435 | if ((adev->pdev->device == 0x1636) || | |
1436 | (adev->pdev->device == 0x164c)) | |
1437 | adev->apu_flags |= AMD_APU_IS_RENOIR; | |
1438 | else | |
1439 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1440 | break; | |
1441 | case CHIP_VANGOGH: | |
1442 | adev->apu_flags |= AMD_APU_IS_VANGOGH; | |
1443 | break; | |
1444 | case CHIP_YELLOW_CARP: | |
1445 | break; | |
d0f56dc2 TZ |
1446 | case CHIP_CYAN_SKILLFISH: |
1447 | if (adev->pdev->device == 0x13FE) | |
1448 | adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2; | |
1449 | break; | |
9f6a7857 HR |
1450 | default: |
1451 | return -EINVAL; | |
1452 | } | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | ||
d38ceaf9 | 1457 | /** |
06ec9070 | 1458 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1459 | * |
1460 | * @adev: amdgpu_device pointer | |
1461 | * | |
1462 | * Validates certain module parameters and updates | |
1463 | * the associated values used by the driver (all asics). | |
1464 | */ | |
912dfc84 | 1465 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1466 | { |
5b011235 CZ |
1467 | if (amdgpu_sched_jobs < 4) { |
1468 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1469 | amdgpu_sched_jobs); | |
1470 | amdgpu_sched_jobs = 4; | |
76117507 | 1471 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1472 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1473 | amdgpu_sched_jobs); | |
1474 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1475 | } | |
d38ceaf9 | 1476 | |
83e74db6 | 1477 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1478 | /* gart size must be greater or equal to 32M */ |
1479 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1480 | amdgpu_gart_size); | |
83e74db6 | 1481 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1482 | } |
1483 | ||
36d38372 | 1484 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1485 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1486 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1487 | amdgpu_gtt_size); | |
1488 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1489 | } |
1490 | ||
d07f14be RH |
1491 | /* valid range is between 4 and 9 inclusive */ |
1492 | if (amdgpu_vm_fragment_size != -1 && | |
1493 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1494 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1495 | amdgpu_vm_fragment_size = -1; | |
1496 | } | |
1497 | ||
5d5bd5e3 KW |
1498 | if (amdgpu_sched_hw_submission < 2) { |
1499 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1500 | amdgpu_sched_hw_submission); | |
1501 | amdgpu_sched_hw_submission = 2; | |
1502 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1503 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1504 | amdgpu_sched_hw_submission); | |
1505 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1506 | } | |
1507 | ||
7951e376 RZ |
1508 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1509 | ||
06ec9070 | 1510 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1511 | |
06ec9070 | 1512 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1513 | |
19aede77 | 1514 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1515 | |
c6252390 | 1516 | amdgpu_gmc_tmz_set(adev); |
01a8dcec | 1517 | |
9b498efa AD |
1518 | amdgpu_gmc_noretry_set(adev); |
1519 | ||
e3c00faa | 1520 | return 0; |
d38ceaf9 AD |
1521 | } |
1522 | ||
1523 | /** | |
1524 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1525 | * | |
1526 | * @pdev: pci dev pointer | |
1694467b | 1527 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1528 | * |
1529 | * Callback for the switcheroo driver. Suspends or resumes the | |
1530 | * the asics before or after it is powered up using ACPI methods. | |
1531 | */ | |
8aba21b7 LT |
1532 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1533 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1534 | { |
1535 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1536 | int r; |
d38ceaf9 | 1537 | |
b98c6299 | 1538 | if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1539 | return; |
1540 | ||
1541 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1542 | pr_info("switched on\n"); |
d38ceaf9 AD |
1543 | /* don't suspend or resume card normally */ |
1544 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1545 | ||
8f66090b TZ |
1546 | pci_set_power_state(pdev, PCI_D0); |
1547 | amdgpu_device_load_pci_state(pdev); | |
1548 | r = pci_enable_device(pdev); | |
de185019 AD |
1549 | if (r) |
1550 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1551 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1552 | |
d38ceaf9 | 1553 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1554 | } else { |
dd4fa6c1 | 1555 | pr_info("switched off\n"); |
d38ceaf9 | 1556 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
de185019 | 1557 | amdgpu_device_suspend(dev, true); |
8f66090b | 1558 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1559 | /* Shut down the device */ |
8f66090b TZ |
1560 | pci_disable_device(pdev); |
1561 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1562 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1563 | } | |
1564 | } | |
1565 | ||
1566 | /** | |
1567 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1568 | * | |
1569 | * @pdev: pci dev pointer | |
1570 | * | |
1571 | * Callback for the switcheroo driver. Check of the switcheroo | |
1572 | * state can be changed. | |
1573 | * Returns true if the state can be changed, false if not. | |
1574 | */ | |
1575 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1576 | { | |
1577 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1578 | ||
1579 | /* | |
1580 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1581 | * locking inversion with the driver load path. And the access here is | |
1582 | * completely racy anyway. So don't bother with locking for now. | |
1583 | */ | |
7e13ad89 | 1584 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1585 | } |
1586 | ||
1587 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1588 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1589 | .reprobe = NULL, | |
1590 | .can_switch = amdgpu_switcheroo_can_switch, | |
1591 | }; | |
1592 | ||
e3ecdffa AD |
1593 | /** |
1594 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1595 | * | |
87e3f136 | 1596 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1597 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1598 | * @state: clockgating state (gate or ungate) | |
1599 | * | |
1600 | * Sets the requested clockgating state for all instances of | |
1601 | * the hardware IP specified. | |
1602 | * Returns the error code from the last instance. | |
1603 | */ | |
43fa561f | 1604 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1605 | enum amd_ip_block_type block_type, |
1606 | enum amd_clockgating_state state) | |
d38ceaf9 | 1607 | { |
43fa561f | 1608 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1609 | int i, r = 0; |
1610 | ||
1611 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1612 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1613 | continue; |
c722865a RZ |
1614 | if (adev->ip_blocks[i].version->type != block_type) |
1615 | continue; | |
1616 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1617 | continue; | |
1618 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1619 | (void *)adev, state); | |
1620 | if (r) | |
1621 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1622 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1623 | } |
1624 | return r; | |
1625 | } | |
1626 | ||
e3ecdffa AD |
1627 | /** |
1628 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1629 | * | |
87e3f136 | 1630 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1631 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1632 | * @state: powergating state (gate or ungate) | |
1633 | * | |
1634 | * Sets the requested powergating state for all instances of | |
1635 | * the hardware IP specified. | |
1636 | * Returns the error code from the last instance. | |
1637 | */ | |
43fa561f | 1638 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1639 | enum amd_ip_block_type block_type, |
1640 | enum amd_powergating_state state) | |
d38ceaf9 | 1641 | { |
43fa561f | 1642 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1643 | int i, r = 0; |
1644 | ||
1645 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1646 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1647 | continue; |
c722865a RZ |
1648 | if (adev->ip_blocks[i].version->type != block_type) |
1649 | continue; | |
1650 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1651 | continue; | |
1652 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1653 | (void *)adev, state); | |
1654 | if (r) | |
1655 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1656 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1657 | } |
1658 | return r; | |
1659 | } | |
1660 | ||
e3ecdffa AD |
1661 | /** |
1662 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1663 | * | |
1664 | * @adev: amdgpu_device pointer | |
1665 | * @flags: clockgating feature flags | |
1666 | * | |
1667 | * Walks the list of IPs on the device and updates the clockgating | |
1668 | * flags for each IP. | |
1669 | * Updates @flags with the feature flags for each hardware IP where | |
1670 | * clockgating is enabled. | |
1671 | */ | |
2990a1fc AD |
1672 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1673 | u32 *flags) | |
6cb2d4e4 HR |
1674 | { |
1675 | int i; | |
1676 | ||
1677 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1678 | if (!adev->ip_blocks[i].status.valid) | |
1679 | continue; | |
1680 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1681 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1682 | } | |
1683 | } | |
1684 | ||
e3ecdffa AD |
1685 | /** |
1686 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1687 | * | |
1688 | * @adev: amdgpu_device pointer | |
1689 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1690 | * | |
1691 | * Waits for the request hardware IP to be idle. | |
1692 | * Returns 0 for success or a negative error code on failure. | |
1693 | */ | |
2990a1fc AD |
1694 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1695 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1696 | { |
1697 | int i, r; | |
1698 | ||
1699 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1700 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1701 | continue; |
a1255107 AD |
1702 | if (adev->ip_blocks[i].version->type == block_type) { |
1703 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1704 | if (r) |
1705 | return r; | |
1706 | break; | |
1707 | } | |
1708 | } | |
1709 | return 0; | |
1710 | ||
1711 | } | |
1712 | ||
e3ecdffa AD |
1713 | /** |
1714 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1715 | * | |
1716 | * @adev: amdgpu_device pointer | |
1717 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1718 | * | |
1719 | * Check if the hardware IP is idle or not. | |
1720 | * Returns true if it the IP is idle, false if not. | |
1721 | */ | |
2990a1fc AD |
1722 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1723 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1724 | { |
1725 | int i; | |
1726 | ||
1727 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1728 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1729 | continue; |
a1255107 AD |
1730 | if (adev->ip_blocks[i].version->type == block_type) |
1731 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1732 | } |
1733 | return true; | |
1734 | ||
1735 | } | |
1736 | ||
e3ecdffa AD |
1737 | /** |
1738 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1739 | * | |
1740 | * @adev: amdgpu_device pointer | |
87e3f136 | 1741 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1742 | * |
1743 | * Returns a pointer to the hardware IP block structure | |
1744 | * if it exists for the asic, otherwise NULL. | |
1745 | */ | |
2990a1fc AD |
1746 | struct amdgpu_ip_block * |
1747 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1748 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1749 | { |
1750 | int i; | |
1751 | ||
1752 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1753 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1754 | return &adev->ip_blocks[i]; |
1755 | ||
1756 | return NULL; | |
1757 | } | |
1758 | ||
1759 | /** | |
2990a1fc | 1760 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1761 | * |
1762 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1763 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1764 | * @major: major version |
1765 | * @minor: minor version | |
1766 | * | |
1767 | * return 0 if equal or greater | |
1768 | * return 1 if smaller or the ip_block doesn't exist | |
1769 | */ | |
2990a1fc AD |
1770 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1771 | enum amd_ip_block_type type, | |
1772 | u32 major, u32 minor) | |
d38ceaf9 | 1773 | { |
2990a1fc | 1774 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1775 | |
a1255107 AD |
1776 | if (ip_block && ((ip_block->version->major > major) || |
1777 | ((ip_block->version->major == major) && | |
1778 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1779 | return 0; |
1780 | ||
1781 | return 1; | |
1782 | } | |
1783 | ||
a1255107 | 1784 | /** |
2990a1fc | 1785 | * amdgpu_device_ip_block_add |
a1255107 AD |
1786 | * |
1787 | * @adev: amdgpu_device pointer | |
1788 | * @ip_block_version: pointer to the IP to add | |
1789 | * | |
1790 | * Adds the IP block driver information to the collection of IPs | |
1791 | * on the asic. | |
1792 | */ | |
2990a1fc AD |
1793 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1794 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1795 | { |
1796 | if (!ip_block_version) | |
1797 | return -EINVAL; | |
1798 | ||
7bd939d0 LG |
1799 | switch (ip_block_version->type) { |
1800 | case AMD_IP_BLOCK_TYPE_VCN: | |
1801 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) | |
1802 | return 0; | |
1803 | break; | |
1804 | case AMD_IP_BLOCK_TYPE_JPEG: | |
1805 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) | |
1806 | return 0; | |
1807 | break; | |
1808 | default: | |
1809 | break; | |
1810 | } | |
1811 | ||
e966a725 | 1812 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1813 | ip_block_version->funcs->name); |
1814 | ||
a1255107 AD |
1815 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1816 | ||
1817 | return 0; | |
1818 | } | |
1819 | ||
e3ecdffa AD |
1820 | /** |
1821 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1822 | * | |
1823 | * @adev: amdgpu_device pointer | |
1824 | * | |
1825 | * Enabled the virtual display feature if the user has enabled it via | |
1826 | * the module parameter virtual_display. This feature provides a virtual | |
1827 | * display hardware on headless boards or in virtualized environments. | |
1828 | * This function parses and validates the configuration string specified by | |
1829 | * the user and configues the virtual display configuration (number of | |
1830 | * virtual connectors, crtcs, etc.) specified. | |
1831 | */ | |
483ef985 | 1832 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1833 | { |
1834 | adev->enable_virtual_display = false; | |
1835 | ||
1836 | if (amdgpu_virtual_display) { | |
8f66090b | 1837 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 1838 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1839 | |
1840 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1841 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1842 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1843 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1844 | if (!strcmp("all", pciaddname) |
1845 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1846 | long num_crtc; |
1847 | int res = -1; | |
1848 | ||
9accf2fd | 1849 | adev->enable_virtual_display = true; |
0f66356d ED |
1850 | |
1851 | if (pciaddname_tmp) | |
1852 | res = kstrtol(pciaddname_tmp, 10, | |
1853 | &num_crtc); | |
1854 | ||
1855 | if (!res) { | |
1856 | if (num_crtc < 1) | |
1857 | num_crtc = 1; | |
1858 | if (num_crtc > 6) | |
1859 | num_crtc = 6; | |
1860 | adev->mode_info.num_crtc = num_crtc; | |
1861 | } else { | |
1862 | adev->mode_info.num_crtc = 1; | |
1863 | } | |
9accf2fd ED |
1864 | break; |
1865 | } | |
1866 | } | |
1867 | ||
0f66356d ED |
1868 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1869 | amdgpu_virtual_display, pci_address_name, | |
1870 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1871 | |
1872 | kfree(pciaddstr); | |
1873 | } | |
1874 | } | |
1875 | ||
e3ecdffa AD |
1876 | /** |
1877 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1878 | * | |
1879 | * @adev: amdgpu_device pointer | |
1880 | * | |
1881 | * Parses the asic configuration parameters specified in the gpu info | |
1882 | * firmware and makes them availale to the driver for use in configuring | |
1883 | * the asic. | |
1884 | * Returns 0 on success, -EINVAL on failure. | |
1885 | */ | |
e2a75f88 AD |
1886 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1887 | { | |
e2a75f88 | 1888 | const char *chip_name; |
c0a43457 | 1889 | char fw_name[40]; |
e2a75f88 AD |
1890 | int err; |
1891 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1892 | ||
ab4fe3e1 HR |
1893 | adev->firmware.gpu_info_fw = NULL; |
1894 | ||
72de33f8 | 1895 | if (adev->mman.discovery_bin) { |
258620d0 | 1896 | amdgpu_discovery_get_gfx_info(adev); |
cc375d8c TY |
1897 | |
1898 | /* | |
1899 | * FIXME: The bounding box is still needed by Navi12, so | |
1900 | * temporarily read it from gpu_info firmware. Should be droped | |
1901 | * when DAL no longer needs it. | |
1902 | */ | |
1903 | if (adev->asic_type != CHIP_NAVI12) | |
1904 | return 0; | |
258620d0 AD |
1905 | } |
1906 | ||
e2a75f88 | 1907 | switch (adev->asic_type) { |
e2a75f88 AD |
1908 | #ifdef CONFIG_DRM_AMDGPU_SI |
1909 | case CHIP_VERDE: | |
1910 | case CHIP_TAHITI: | |
1911 | case CHIP_PITCAIRN: | |
1912 | case CHIP_OLAND: | |
1913 | case CHIP_HAINAN: | |
1914 | #endif | |
1915 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1916 | case CHIP_BONAIRE: | |
1917 | case CHIP_HAWAII: | |
1918 | case CHIP_KAVERI: | |
1919 | case CHIP_KABINI: | |
1920 | case CHIP_MULLINS: | |
1921 | #endif | |
da87c30b AD |
1922 | case CHIP_TOPAZ: |
1923 | case CHIP_TONGA: | |
1924 | case CHIP_FIJI: | |
1925 | case CHIP_POLARIS10: | |
1926 | case CHIP_POLARIS11: | |
1927 | case CHIP_POLARIS12: | |
1928 | case CHIP_VEGAM: | |
1929 | case CHIP_CARRIZO: | |
1930 | case CHIP_STONEY: | |
27c0bc71 | 1931 | case CHIP_VEGA20: |
44b3253a | 1932 | case CHIP_ALDEBARAN: |
84d244a3 JC |
1933 | case CHIP_SIENNA_CICHLID: |
1934 | case CHIP_NAVY_FLOUNDER: | |
eac88a5f | 1935 | case CHIP_DIMGREY_CAVEFISH: |
0e5f4b09 | 1936 | case CHIP_BEIGE_GOBY: |
e2a75f88 AD |
1937 | default: |
1938 | return 0; | |
1939 | case CHIP_VEGA10: | |
1940 | chip_name = "vega10"; | |
1941 | break; | |
3f76dced AD |
1942 | case CHIP_VEGA12: |
1943 | chip_name = "vega12"; | |
1944 | break; | |
2d2e5e7e | 1945 | case CHIP_RAVEN: |
54f78a76 | 1946 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1947 | chip_name = "raven2"; |
54f78a76 | 1948 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1949 | chip_name = "picasso"; |
54c4d17e FX |
1950 | else |
1951 | chip_name = "raven"; | |
2d2e5e7e | 1952 | break; |
65e60f6e LM |
1953 | case CHIP_ARCTURUS: |
1954 | chip_name = "arcturus"; | |
1955 | break; | |
b51a26a0 | 1956 | case CHIP_RENOIR: |
2e62f0b5 PL |
1957 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
1958 | chip_name = "renoir"; | |
1959 | else | |
1960 | chip_name = "green_sardine"; | |
b51a26a0 | 1961 | break; |
23c6268e HR |
1962 | case CHIP_NAVI10: |
1963 | chip_name = "navi10"; | |
1964 | break; | |
ed42cfe1 XY |
1965 | case CHIP_NAVI14: |
1966 | chip_name = "navi14"; | |
1967 | break; | |
42b325e5 XY |
1968 | case CHIP_NAVI12: |
1969 | chip_name = "navi12"; | |
1970 | break; | |
4e52a9f8 HR |
1971 | case CHIP_VANGOGH: |
1972 | chip_name = "vangogh"; | |
1973 | break; | |
8bf84f60 AL |
1974 | case CHIP_YELLOW_CARP: |
1975 | chip_name = "yellow_carp"; | |
1976 | break; | |
e2a75f88 AD |
1977 | } |
1978 | ||
1979 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1980 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1981 | if (err) { |
1982 | dev_err(adev->dev, | |
1983 | "Failed to load gpu_info firmware \"%s\"\n", | |
1984 | fw_name); | |
1985 | goto out; | |
1986 | } | |
ab4fe3e1 | 1987 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1988 | if (err) { |
1989 | dev_err(adev->dev, | |
1990 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1991 | fw_name); | |
1992 | goto out; | |
1993 | } | |
1994 | ||
ab4fe3e1 | 1995 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1996 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1997 | ||
1998 | switch (hdr->version_major) { | |
1999 | case 1: | |
2000 | { | |
2001 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 2002 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
2003 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
2004 | ||
cc375d8c TY |
2005 | /* |
2006 | * Should be droped when DAL no longer needs it. | |
2007 | */ | |
2008 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
2009 | goto parse_soc_bounding_box; |
2010 | ||
b5ab16bf AD |
2011 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
2012 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
2013 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
2014 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 2015 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
2016 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
2017 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
2018 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
2019 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
2020 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 2021 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
2022 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
2023 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
2024 | adev->gfx.cu_info.max_waves_per_simd = |
2025 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
2026 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
2027 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
2028 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 2029 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
2030 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
2031 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
2032 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2033 | adev->gfx.config.num_sc_per_sh = | |
2034 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
2035 | adev->gfx.config.num_packer_per_sc = | |
2036 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
2037 | } | |
ec51d3fa XY |
2038 | |
2039 | parse_soc_bounding_box: | |
ec51d3fa XY |
2040 | /* |
2041 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 2042 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 2043 | */ |
48321c3d HW |
2044 | if (hdr->version_minor == 2) { |
2045 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
2046 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
2047 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2048 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
2049 | } | |
e2a75f88 AD |
2050 | break; |
2051 | } | |
2052 | default: | |
2053 | dev_err(adev->dev, | |
2054 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
2055 | err = -EINVAL; | |
2056 | goto out; | |
2057 | } | |
2058 | out: | |
e2a75f88 AD |
2059 | return err; |
2060 | } | |
2061 | ||
e3ecdffa AD |
2062 | /** |
2063 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
2064 | * | |
2065 | * @adev: amdgpu_device pointer | |
2066 | * | |
2067 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
2068 | * up each asic are discovered each IP's early_init callback is run. This | |
2069 | * is the first stage in initializing the asic. | |
2070 | * Returns 0 on success, negative error code on failure. | |
2071 | */ | |
06ec9070 | 2072 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 2073 | { |
aaa36a97 | 2074 | int i, r; |
d38ceaf9 | 2075 | |
483ef985 | 2076 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 2077 | |
00a979f3 | 2078 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 2079 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
2080 | if (r) |
2081 | return r; | |
00a979f3 WS |
2082 | } |
2083 | ||
d38ceaf9 | 2084 | switch (adev->asic_type) { |
33f34802 KW |
2085 | #ifdef CONFIG_DRM_AMDGPU_SI |
2086 | case CHIP_VERDE: | |
2087 | case CHIP_TAHITI: | |
2088 | case CHIP_PITCAIRN: | |
2089 | case CHIP_OLAND: | |
2090 | case CHIP_HAINAN: | |
295d0daf | 2091 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
2092 | r = si_set_ip_blocks(adev); |
2093 | if (r) | |
2094 | return r; | |
2095 | break; | |
2096 | #endif | |
a2e73f56 AD |
2097 | #ifdef CONFIG_DRM_AMDGPU_CIK |
2098 | case CHIP_BONAIRE: | |
2099 | case CHIP_HAWAII: | |
2100 | case CHIP_KAVERI: | |
2101 | case CHIP_KABINI: | |
2102 | case CHIP_MULLINS: | |
e1ad2d53 | 2103 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 2104 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
2105 | else |
2106 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
2107 | |
2108 | r = cik_set_ip_blocks(adev); | |
2109 | if (r) | |
2110 | return r; | |
2111 | break; | |
2112 | #endif | |
da87c30b AD |
2113 | case CHIP_TOPAZ: |
2114 | case CHIP_TONGA: | |
2115 | case CHIP_FIJI: | |
2116 | case CHIP_POLARIS10: | |
2117 | case CHIP_POLARIS11: | |
2118 | case CHIP_POLARIS12: | |
2119 | case CHIP_VEGAM: | |
2120 | case CHIP_CARRIZO: | |
2121 | case CHIP_STONEY: | |
2122 | if (adev->flags & AMD_IS_APU) | |
2123 | adev->family = AMDGPU_FAMILY_CZ; | |
2124 | else | |
2125 | adev->family = AMDGPU_FAMILY_VI; | |
2126 | ||
2127 | r = vi_set_ip_blocks(adev); | |
2128 | if (r) | |
2129 | return r; | |
2130 | break; | |
d38ceaf9 | 2131 | default: |
63352b7f AD |
2132 | r = amdgpu_discovery_set_ip_blocks(adev); |
2133 | if (r) | |
2134 | return r; | |
2135 | break; | |
d38ceaf9 AD |
2136 | } |
2137 | ||
1884734a | 2138 | amdgpu_amdkfd_device_probe(adev); |
2139 | ||
3b94fb10 | 2140 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2141 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2142 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2143 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2144 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
00f54b97 | 2145 | |
d38ceaf9 AD |
2146 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2147 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
2148 | DRM_ERROR("disabled ip block: %d <%s>\n", |
2149 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 2150 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2151 | } else { |
a1255107 AD |
2152 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2153 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2154 | if (r == -ENOENT) { |
a1255107 | 2155 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2156 | } else if (r) { |
a1255107 AD |
2157 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2158 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2159 | return r; |
2c1a2784 | 2160 | } else { |
a1255107 | 2161 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2162 | } |
974e6b64 | 2163 | } else { |
a1255107 | 2164 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2165 | } |
d38ceaf9 | 2166 | } |
21a249ca AD |
2167 | /* get the vbios after the asic_funcs are set up */ |
2168 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2169 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2170 | if (r) | |
2171 | return r; | |
2172 | ||
21a249ca AD |
2173 | /* Read BIOS */ |
2174 | if (!amdgpu_get_bios(adev)) | |
2175 | return -EINVAL; | |
2176 | ||
2177 | r = amdgpu_atombios_init(adev); | |
2178 | if (r) { | |
2179 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2180 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2181 | return r; | |
2182 | } | |
77eabc6f PJZ |
2183 | |
2184 | /*get pf2vf msg info at it's earliest time*/ | |
2185 | if (amdgpu_sriov_vf(adev)) | |
2186 | amdgpu_virt_init_data_exchange(adev); | |
2187 | ||
21a249ca | 2188 | } |
d38ceaf9 AD |
2189 | } |
2190 | ||
395d1fb9 NH |
2191 | adev->cg_flags &= amdgpu_cg_mask; |
2192 | adev->pg_flags &= amdgpu_pg_mask; | |
2193 | ||
d38ceaf9 AD |
2194 | return 0; |
2195 | } | |
2196 | ||
0a4f2520 RZ |
2197 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2198 | { | |
2199 | int i, r; | |
2200 | ||
2201 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2202 | if (!adev->ip_blocks[i].status.sw) | |
2203 | continue; | |
2204 | if (adev->ip_blocks[i].status.hw) | |
2205 | continue; | |
2206 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2207 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2208 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2209 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2210 | if (r) { | |
2211 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2212 | adev->ip_blocks[i].version->funcs->name, r); | |
2213 | return r; | |
2214 | } | |
2215 | adev->ip_blocks[i].status.hw = true; | |
2216 | } | |
2217 | } | |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2223 | { | |
2224 | int i, r; | |
2225 | ||
2226 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2227 | if (!adev->ip_blocks[i].status.sw) | |
2228 | continue; | |
2229 | if (adev->ip_blocks[i].status.hw) | |
2230 | continue; | |
2231 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2232 | if (r) { | |
2233 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2234 | adev->ip_blocks[i].version->funcs->name, r); | |
2235 | return r; | |
2236 | } | |
2237 | adev->ip_blocks[i].status.hw = true; | |
2238 | } | |
2239 | ||
2240 | return 0; | |
2241 | } | |
2242 | ||
7a3e0bb2 RZ |
2243 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2244 | { | |
2245 | int r = 0; | |
2246 | int i; | |
80f41f84 | 2247 | uint32_t smu_version; |
7a3e0bb2 RZ |
2248 | |
2249 | if (adev->asic_type >= CHIP_VEGA10) { | |
2250 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2251 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2252 | continue; | |
2253 | ||
e3c1b071 | 2254 | if (!adev->ip_blocks[i].status.sw) |
2255 | continue; | |
2256 | ||
482f0e53 ML |
2257 | /* no need to do the fw loading again if already done*/ |
2258 | if (adev->ip_blocks[i].status.hw == true) | |
2259 | break; | |
2260 | ||
53b3f8f4 | 2261 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2262 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2263 | if (r) { | |
2264 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2265 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2266 | return r; |
2267 | } | |
2268 | } else { | |
2269 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2270 | if (r) { | |
2271 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2272 | adev->ip_blocks[i].version->funcs->name, r); | |
2273 | return r; | |
7a3e0bb2 | 2274 | } |
7a3e0bb2 | 2275 | } |
482f0e53 ML |
2276 | |
2277 | adev->ip_blocks[i].status.hw = true; | |
2278 | break; | |
7a3e0bb2 RZ |
2279 | } |
2280 | } | |
482f0e53 | 2281 | |
8973d9ec ED |
2282 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2283 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2284 | |
80f41f84 | 2285 | return r; |
7a3e0bb2 RZ |
2286 | } |
2287 | ||
e3ecdffa AD |
2288 | /** |
2289 | * amdgpu_device_ip_init - run init for hardware IPs | |
2290 | * | |
2291 | * @adev: amdgpu_device pointer | |
2292 | * | |
2293 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2294 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2295 | * are run. sw_init initializes the software state associated with each IP | |
2296 | * and hw_init initializes the hardware associated with each IP. | |
2297 | * Returns 0 on success, negative error code on failure. | |
2298 | */ | |
06ec9070 | 2299 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2300 | { |
2301 | int i, r; | |
2302 | ||
c030f2e4 | 2303 | r = amdgpu_ras_init(adev); |
2304 | if (r) | |
2305 | return r; | |
2306 | ||
d38ceaf9 | 2307 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2308 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2309 | continue; |
a1255107 | 2310 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2311 | if (r) { |
a1255107 AD |
2312 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2313 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2314 | goto init_failed; |
2c1a2784 | 2315 | } |
a1255107 | 2316 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2317 | |
d38ceaf9 | 2318 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2319 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
892deb48 VS |
2320 | /* Try to reserve bad pages early */ |
2321 | if (amdgpu_sriov_vf(adev)) | |
2322 | amdgpu_virt_exchange_data(adev); | |
2323 | ||
06ec9070 | 2324 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2325 | if (r) { |
2326 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2327 | goto init_failed; |
2c1a2784 | 2328 | } |
a1255107 | 2329 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2330 | if (r) { |
2331 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2332 | goto init_failed; |
2c1a2784 | 2333 | } |
06ec9070 | 2334 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2335 | if (r) { |
06ec9070 | 2336 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2337 | goto init_failed; |
2c1a2784 | 2338 | } |
a1255107 | 2339 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2340 | |
2341 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2342 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2343 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2344 | AMDGPU_GEM_DOMAIN_VRAM, | |
2345 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2346 | if (r) { |
2347 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2348 | goto init_failed; |
2493664f ML |
2349 | } |
2350 | } | |
d38ceaf9 AD |
2351 | } |
2352 | } | |
2353 | ||
c9ffa427 | 2354 | if (amdgpu_sriov_vf(adev)) |
892deb48 | 2355 | amdgpu_virt_exchange_data(adev); |
c9ffa427 | 2356 | |
533aed27 AG |
2357 | r = amdgpu_ib_pool_init(adev); |
2358 | if (r) { | |
2359 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2360 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2361 | goto init_failed; | |
2362 | } | |
2363 | ||
c8963ea4 RZ |
2364 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2365 | if (r) | |
72d3f592 | 2366 | goto init_failed; |
0a4f2520 RZ |
2367 | |
2368 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2369 | if (r) | |
72d3f592 | 2370 | goto init_failed; |
0a4f2520 | 2371 | |
7a3e0bb2 RZ |
2372 | r = amdgpu_device_fw_loading(adev); |
2373 | if (r) | |
72d3f592 | 2374 | goto init_failed; |
7a3e0bb2 | 2375 | |
0a4f2520 RZ |
2376 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2377 | if (r) | |
72d3f592 | 2378 | goto init_failed; |
d38ceaf9 | 2379 | |
121a2bc6 AG |
2380 | /* |
2381 | * retired pages will be loaded from eeprom and reserved here, | |
2382 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2383 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2384 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2385 | * |
2386 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2387 | * failure from bad gpu situation and stop amdgpu init process | |
2388 | * accordingly. For other failed cases, it will still release all | |
2389 | * the resource and print error message, rather than returning one | |
2390 | * negative value to upper level. | |
121a2bc6 AG |
2391 | * |
2392 | * Note: theoretically, this should be called before all vram allocations | |
2393 | * to protect retired page from abusing | |
2394 | */ | |
b82e65a9 GC |
2395 | r = amdgpu_ras_recovery_init(adev); |
2396 | if (r) | |
2397 | goto init_failed; | |
121a2bc6 | 2398 | |
3e2e2ab5 HZ |
2399 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2400 | amdgpu_xgmi_add_device(adev); | |
e3c1b071 | 2401 | |
2402 | /* Don't init kfd if whole hive need to be reset during init */ | |
2403 | if (!adev->gmc.xgmi.pending_reset) | |
2404 | amdgpu_amdkfd_device_init(adev); | |
c6332b97 | 2405 | |
bd607166 KR |
2406 | amdgpu_fru_get_product_info(adev); |
2407 | ||
72d3f592 | 2408 | init_failed: |
c9ffa427 | 2409 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2410 | amdgpu_virt_release_full_gpu(adev, true); |
2411 | ||
72d3f592 | 2412 | return r; |
d38ceaf9 AD |
2413 | } |
2414 | ||
e3ecdffa AD |
2415 | /** |
2416 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2417 | * | |
2418 | * @adev: amdgpu_device pointer | |
2419 | * | |
2420 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2421 | * this function before a GPU reset. If the value is retained after a | |
2422 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2423 | */ | |
06ec9070 | 2424 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2425 | { |
2426 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2427 | } | |
2428 | ||
e3ecdffa AD |
2429 | /** |
2430 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2431 | * | |
2432 | * @adev: amdgpu_device pointer | |
2433 | * | |
2434 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2435 | * The driver calls this after a GPU reset to see if the contents of | |
2436 | * VRAM is lost or now. | |
2437 | * returns true if vram is lost, false if not. | |
2438 | */ | |
06ec9070 | 2439 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2440 | { |
dadce777 EQ |
2441 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2442 | AMDGPU_RESET_MAGIC_NUM)) | |
2443 | return true; | |
2444 | ||
53b3f8f4 | 2445 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2446 | return false; |
2447 | ||
2448 | /* | |
2449 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2450 | * always assumed to be lost. | |
2451 | */ | |
2452 | switch (amdgpu_asic_reset_method(adev)) { | |
2453 | case AMD_RESET_METHOD_BACO: | |
2454 | case AMD_RESET_METHOD_MODE1: | |
2455 | return true; | |
2456 | default: | |
2457 | return false; | |
2458 | } | |
0c49e0b8 CZ |
2459 | } |
2460 | ||
e3ecdffa | 2461 | /** |
1112a46b | 2462 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2463 | * |
2464 | * @adev: amdgpu_device pointer | |
b8b72130 | 2465 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2466 | * |
e3ecdffa | 2467 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2468 | * set_clockgating_state callbacks are run. |
2469 | * Late initialization pass enabling clockgating for hardware IPs. | |
2470 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2471 | * Returns 0 on success, negative error code on failure. |
2472 | */ | |
fdd34271 | 2473 | |
5d89bb2d LL |
2474 | int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2475 | enum amd_clockgating_state state) | |
d38ceaf9 | 2476 | { |
1112a46b | 2477 | int i, j, r; |
d38ceaf9 | 2478 | |
4a2ba394 SL |
2479 | if (amdgpu_emu_mode == 1) |
2480 | return 0; | |
2481 | ||
1112a46b RZ |
2482 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2483 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2484 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2485 | continue; |
5d70a549 PV |
2486 | /* skip CG for GFX on S0ix */ |
2487 | if (adev->in_s0ix && | |
2488 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2489 | continue; | |
4a446d55 | 2490 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2491 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2492 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2493 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2494 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2495 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2496 | /* enable clockgating to save power */ |
a1255107 | 2497 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2498 | state); |
4a446d55 AD |
2499 | if (r) { |
2500 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2501 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2502 | return r; |
2503 | } | |
b0b00ff1 | 2504 | } |
d38ceaf9 | 2505 | } |
06b18f61 | 2506 | |
c9f96fd5 RZ |
2507 | return 0; |
2508 | } | |
2509 | ||
5d89bb2d LL |
2510 | int amdgpu_device_set_pg_state(struct amdgpu_device *adev, |
2511 | enum amd_powergating_state state) | |
c9f96fd5 | 2512 | { |
1112a46b | 2513 | int i, j, r; |
06b18f61 | 2514 | |
c9f96fd5 RZ |
2515 | if (amdgpu_emu_mode == 1) |
2516 | return 0; | |
2517 | ||
1112a46b RZ |
2518 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2519 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2520 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 | 2521 | continue; |
5d70a549 PV |
2522 | /* skip PG for GFX on S0ix */ |
2523 | if (adev->in_s0ix && | |
2524 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2525 | continue; | |
c9f96fd5 RZ |
2526 | /* skip CG for VCE/UVD, it's handled specially */ |
2527 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2528 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2529 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2530 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2531 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2532 | /* enable powergating to save power */ | |
2533 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2534 | state); |
c9f96fd5 RZ |
2535 | if (r) { |
2536 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2537 | adev->ip_blocks[i].version->funcs->name, r); | |
2538 | return r; | |
2539 | } | |
2540 | } | |
2541 | } | |
2dc80b00 S |
2542 | return 0; |
2543 | } | |
2544 | ||
beff74bc AD |
2545 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2546 | { | |
2547 | struct amdgpu_gpu_instance *gpu_ins; | |
2548 | struct amdgpu_device *adev; | |
2549 | int i, ret = 0; | |
2550 | ||
2551 | mutex_lock(&mgpu_info.mutex); | |
2552 | ||
2553 | /* | |
2554 | * MGPU fan boost feature should be enabled | |
2555 | * only when there are two or more dGPUs in | |
2556 | * the system | |
2557 | */ | |
2558 | if (mgpu_info.num_dgpu < 2) | |
2559 | goto out; | |
2560 | ||
2561 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2562 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2563 | adev = gpu_ins->adev; | |
2564 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2565 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2566 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2567 | if (ret) | |
2568 | break; | |
2569 | ||
2570 | gpu_ins->mgpu_fan_enabled = 1; | |
2571 | } | |
2572 | } | |
2573 | ||
2574 | out: | |
2575 | mutex_unlock(&mgpu_info.mutex); | |
2576 | ||
2577 | return ret; | |
2578 | } | |
2579 | ||
e3ecdffa AD |
2580 | /** |
2581 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2582 | * | |
2583 | * @adev: amdgpu_device pointer | |
2584 | * | |
2585 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2586 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2587 | * late_init covers any special initialization that an IP requires | |
2588 | * after all of the have been initialized or something that needs to happen | |
2589 | * late in the init process. | |
2590 | * Returns 0 on success, negative error code on failure. | |
2591 | */ | |
06ec9070 | 2592 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2593 | { |
60599a03 | 2594 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2595 | int i = 0, r; |
2596 | ||
2597 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2598 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2599 | continue; |
2600 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2601 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2602 | if (r) { | |
2603 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2604 | adev->ip_blocks[i].version->funcs->name, r); | |
2605 | return r; | |
2606 | } | |
2dc80b00 | 2607 | } |
73f847db | 2608 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2609 | } |
2610 | ||
a891d239 DL |
2611 | amdgpu_ras_set_error_query_ready(adev, true); |
2612 | ||
1112a46b RZ |
2613 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2614 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2615 | |
06ec9070 | 2616 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2617 | |
beff74bc AD |
2618 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2619 | if (r) | |
2620 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2621 | ||
2d02893f | 2622 | /* For XGMI + passthrough configuration on arcturus, enable light SBR */ |
2623 | if (adev->asic_type == CHIP_ARCTURUS && | |
2624 | amdgpu_passthrough(adev) && | |
2625 | adev->gmc.xgmi.num_physical_nodes > 1) | |
2626 | smu_set_light_sbr(&adev->smu, true); | |
60599a03 EQ |
2627 | |
2628 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2629 | mutex_lock(&mgpu_info.mutex); | |
2630 | ||
2631 | /* | |
2632 | * Reset device p-state to low as this was booted with high. | |
2633 | * | |
2634 | * This should be performed only after all devices from the same | |
2635 | * hive get initialized. | |
2636 | * | |
2637 | * However, it's unknown how many device in the hive in advance. | |
2638 | * As this is counted one by one during devices initializations. | |
2639 | * | |
2640 | * So, we wait for all XGMI interlinked devices initialized. | |
2641 | * This may bring some delays as those devices may come from | |
2642 | * different hives. But that should be OK. | |
2643 | */ | |
2644 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2645 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2646 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2647 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2648 | continue; | |
2649 | ||
d84a430d JK |
2650 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2651 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2652 | if (r) { |
2653 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2654 | break; | |
2655 | } | |
2656 | } | |
2657 | } | |
2658 | ||
2659 | mutex_unlock(&mgpu_info.mutex); | |
2660 | } | |
2661 | ||
d38ceaf9 AD |
2662 | return 0; |
2663 | } | |
2664 | ||
613aa3ea LY |
2665 | /** |
2666 | * amdgpu_device_smu_fini_early - smu hw_fini wrapper | |
2667 | * | |
2668 | * @adev: amdgpu_device pointer | |
2669 | * | |
2670 | * For ASICs need to disable SMC first | |
2671 | */ | |
2672 | static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev) | |
2673 | { | |
2674 | int i, r; | |
2675 | ||
2676 | if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)) | |
2677 | return; | |
2678 | ||
2679 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2680 | if (!adev->ip_blocks[i].status.hw) | |
2681 | continue; | |
2682 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2683 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); | |
2684 | /* XXX handle errors */ | |
2685 | if (r) { | |
2686 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
2687 | adev->ip_blocks[i].version->funcs->name, r); | |
2688 | } | |
2689 | adev->ip_blocks[i].status.hw = false; | |
2690 | break; | |
2691 | } | |
2692 | } | |
2693 | } | |
2694 | ||
e9669fb7 | 2695 | static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) |
d38ceaf9 AD |
2696 | { |
2697 | int i, r; | |
2698 | ||
e9669fb7 AG |
2699 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2700 | if (!adev->ip_blocks[i].version->funcs->early_fini) | |
2701 | continue; | |
5278a159 | 2702 | |
e9669fb7 AG |
2703 | r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); |
2704 | if (r) { | |
2705 | DRM_DEBUG("early_fini of IP block <%s> failed %d\n", | |
2706 | adev->ip_blocks[i].version->funcs->name, r); | |
2707 | } | |
2708 | } | |
c030f2e4 | 2709 | |
e9669fb7 | 2710 | amdgpu_amdkfd_suspend(adev, false); |
a82400b5 | 2711 | |
05df1f01 | 2712 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
2713 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2714 | ||
613aa3ea LY |
2715 | /* Workaroud for ASICs need to disable SMC first */ |
2716 | amdgpu_device_smu_fini_early(adev); | |
3e96dbfd | 2717 | |
d38ceaf9 | 2718 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2719 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2720 | continue; |
8201a67a | 2721 | |
a1255107 | 2722 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2723 | /* XXX handle errors */ |
2c1a2784 | 2724 | if (r) { |
a1255107 AD |
2725 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2726 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2727 | } |
8201a67a | 2728 | |
a1255107 | 2729 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2730 | } |
2731 | ||
6effad8a GC |
2732 | if (amdgpu_sriov_vf(adev)) { |
2733 | if (amdgpu_virt_release_full_gpu(adev, false)) | |
2734 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2735 | } | |
2736 | ||
e9669fb7 AG |
2737 | return 0; |
2738 | } | |
2739 | ||
2740 | /** | |
2741 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2742 | * | |
2743 | * @adev: amdgpu_device pointer | |
2744 | * | |
2745 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2746 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2747 | * are run. hw_fini tears down the hardware associated with each IP | |
2748 | * and sw_fini tears down any software state associated with each IP. | |
2749 | * Returns 0 on success, negative error code on failure. | |
2750 | */ | |
2751 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |
2752 | { | |
2753 | int i, r; | |
2754 | ||
2755 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) | |
2756 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2757 | ||
e9669fb7 AG |
2758 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2759 | amdgpu_xgmi_remove_device(adev); | |
2760 | ||
2761 | amdgpu_amdkfd_device_fini_sw(adev); | |
9950cda2 | 2762 | |
d38ceaf9 | 2763 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2764 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2765 | continue; |
c12aba3a ML |
2766 | |
2767 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2768 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2769 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2770 | amdgpu_device_wb_fini(adev); |
2771 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2772 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2773 | } |
2774 | ||
a1255107 | 2775 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2776 | /* XXX handle errors */ |
2c1a2784 | 2777 | if (r) { |
a1255107 AD |
2778 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2779 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2780 | } |
a1255107 AD |
2781 | adev->ip_blocks[i].status.sw = false; |
2782 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2783 | } |
2784 | ||
a6dcfd9c | 2785 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2786 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2787 | continue; |
a1255107 AD |
2788 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2789 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2790 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2791 | } |
2792 | ||
c030f2e4 | 2793 | amdgpu_ras_fini(adev); |
2794 | ||
d38ceaf9 AD |
2795 | return 0; |
2796 | } | |
2797 | ||
e3ecdffa | 2798 | /** |
beff74bc | 2799 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2800 | * |
1112a46b | 2801 | * @work: work_struct. |
e3ecdffa | 2802 | */ |
beff74bc | 2803 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2804 | { |
2805 | struct amdgpu_device *adev = | |
beff74bc | 2806 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2807 | int r; |
2808 | ||
2809 | r = amdgpu_ib_ring_tests(adev); | |
2810 | if (r) | |
2811 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2812 | } |
2813 | ||
1e317b99 RZ |
2814 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2815 | { | |
2816 | struct amdgpu_device *adev = | |
2817 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2818 | ||
90a92662 MD |
2819 | WARN_ON_ONCE(adev->gfx.gfx_off_state); |
2820 | WARN_ON_ONCE(adev->gfx.gfx_off_req_count); | |
2821 | ||
2822 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2823 | adev->gfx.gfx_off_state = true; | |
1e317b99 RZ |
2824 | } |
2825 | ||
e3ecdffa | 2826 | /** |
e7854a03 | 2827 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2828 | * |
2829 | * @adev: amdgpu_device pointer | |
2830 | * | |
2831 | * Main suspend function for hardware IPs. The list of all the hardware | |
2832 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2833 | * suspend callbacks are run. suspend puts the hardware and software state | |
2834 | * in each IP into a state suitable for suspend. | |
2835 | * Returns 0 on success, negative error code on failure. | |
2836 | */ | |
e7854a03 AD |
2837 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2838 | { | |
2839 | int i, r; | |
2840 | ||
50ec83f0 AD |
2841 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2842 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2843 | |
e7854a03 AD |
2844 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2845 | if (!adev->ip_blocks[i].status.valid) | |
2846 | continue; | |
2b9f7848 | 2847 | |
e7854a03 | 2848 | /* displays are handled separately */ |
2b9f7848 ND |
2849 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2850 | continue; | |
2851 | ||
2852 | /* XXX handle errors */ | |
2853 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2854 | /* XXX handle errors */ | |
2855 | if (r) { | |
2856 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2857 | adev->ip_blocks[i].version->funcs->name, r); | |
2858 | return r; | |
e7854a03 | 2859 | } |
2b9f7848 ND |
2860 | |
2861 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2862 | } |
2863 | ||
e7854a03 AD |
2864 | return 0; |
2865 | } | |
2866 | ||
2867 | /** | |
2868 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2869 | * | |
2870 | * @adev: amdgpu_device pointer | |
2871 | * | |
2872 | * Main suspend function for hardware IPs. The list of all the hardware | |
2873 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2874 | * suspend callbacks are run. suspend puts the hardware and software state | |
2875 | * in each IP into a state suitable for suspend. | |
2876 | * Returns 0 on success, negative error code on failure. | |
2877 | */ | |
2878 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2879 | { |
2880 | int i, r; | |
2881 | ||
557f42a2 | 2882 | if (adev->in_s0ix) |
34416931 | 2883 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); |
34416931 | 2884 | |
d38ceaf9 | 2885 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2886 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2887 | continue; |
e7854a03 AD |
2888 | /* displays are handled in phase1 */ |
2889 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2890 | continue; | |
bff77e86 LM |
2891 | /* PSP lost connection when err_event_athub occurs */ |
2892 | if (amdgpu_ras_intr_triggered() && | |
2893 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2894 | adev->ip_blocks[i].status.hw = false; | |
2895 | continue; | |
2896 | } | |
e3c1b071 | 2897 | |
2898 | /* skip unnecessary suspend if we do not initialize them yet */ | |
2899 | if (adev->gmc.xgmi.pending_reset && | |
2900 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2901 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
2902 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2903 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
2904 | adev->ip_blocks[i].status.hw = false; | |
2905 | continue; | |
2906 | } | |
557f42a2 | 2907 | |
32ff160d AD |
2908 | /* skip suspend of gfx and psp for S0ix |
2909 | * gfx is in gfxoff state, so on resume it will exit gfxoff just | |
2910 | * like at runtime. PSP is also part of the always on hardware | |
2911 | * so no need to suspend it. | |
2912 | */ | |
557f42a2 | 2913 | if (adev->in_s0ix && |
32ff160d AD |
2914 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || |
2915 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)) | |
557f42a2 AD |
2916 | continue; |
2917 | ||
d38ceaf9 | 2918 | /* XXX handle errors */ |
a1255107 | 2919 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2920 | /* XXX handle errors */ |
2c1a2784 | 2921 | if (r) { |
a1255107 AD |
2922 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2923 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2924 | } |
876923fb | 2925 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 2926 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
2927 | if(!amdgpu_sriov_vf(adev)){ |
2928 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2929 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
2930 | if (r) { | |
2931 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2932 | adev->mp1_state, r); | |
2933 | return r; | |
2934 | } | |
a3a09142 AD |
2935 | } |
2936 | } | |
d38ceaf9 AD |
2937 | } |
2938 | ||
2939 | return 0; | |
2940 | } | |
2941 | ||
e7854a03 AD |
2942 | /** |
2943 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2944 | * | |
2945 | * @adev: amdgpu_device pointer | |
2946 | * | |
2947 | * Main suspend function for hardware IPs. The list of all the hardware | |
2948 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2949 | * suspend callbacks are run. suspend puts the hardware and software state | |
2950 | * in each IP into a state suitable for suspend. | |
2951 | * Returns 0 on success, negative error code on failure. | |
2952 | */ | |
2953 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2954 | { | |
2955 | int r; | |
2956 | ||
3c73683c JC |
2957 | if (amdgpu_sriov_vf(adev)) { |
2958 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 2959 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 2960 | } |
e7819644 | 2961 | |
e7854a03 AD |
2962 | r = amdgpu_device_ip_suspend_phase1(adev); |
2963 | if (r) | |
2964 | return r; | |
2965 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2966 | ||
e7819644 YT |
2967 | if (amdgpu_sriov_vf(adev)) |
2968 | amdgpu_virt_release_full_gpu(adev, false); | |
2969 | ||
e7854a03 AD |
2970 | return r; |
2971 | } | |
2972 | ||
06ec9070 | 2973 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2974 | { |
2975 | int i, r; | |
2976 | ||
2cb681b6 ML |
2977 | static enum amd_ip_block_type ip_order[] = { |
2978 | AMD_IP_BLOCK_TYPE_GMC, | |
2979 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2980 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2981 | AMD_IP_BLOCK_TYPE_IH, |
2982 | }; | |
a90ad3c2 | 2983 | |
95ea3dbc | 2984 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2cb681b6 ML |
2985 | int j; |
2986 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2987 | |
4cd2a96d J |
2988 | block = &adev->ip_blocks[i]; |
2989 | block->status.hw = false; | |
2cb681b6 | 2990 | |
4cd2a96d | 2991 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 2992 | |
4cd2a96d | 2993 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
2994 | !block->status.valid) |
2995 | continue; | |
2996 | ||
2997 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2998 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2999 | if (r) |
3000 | return r; | |
482f0e53 | 3001 | block->status.hw = true; |
a90ad3c2 ML |
3002 | } |
3003 | } | |
3004 | ||
3005 | return 0; | |
3006 | } | |
3007 | ||
06ec9070 | 3008 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3009 | { |
3010 | int i, r; | |
3011 | ||
2cb681b6 ML |
3012 | static enum amd_ip_block_type ip_order[] = { |
3013 | AMD_IP_BLOCK_TYPE_SMC, | |
3014 | AMD_IP_BLOCK_TYPE_DCE, | |
3015 | AMD_IP_BLOCK_TYPE_GFX, | |
3016 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 3017 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
3018 | AMD_IP_BLOCK_TYPE_VCE, |
3019 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 3020 | }; |
a90ad3c2 | 3021 | |
2cb681b6 ML |
3022 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
3023 | int j; | |
3024 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3025 | |
2cb681b6 ML |
3026 | for (j = 0; j < adev->num_ip_blocks; j++) { |
3027 | block = &adev->ip_blocks[j]; | |
3028 | ||
3029 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
3030 | !block->status.valid || |
3031 | block->status.hw) | |
2cb681b6 ML |
3032 | continue; |
3033 | ||
895bd048 JZ |
3034 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
3035 | r = block->version->funcs->resume(adev); | |
3036 | else | |
3037 | r = block->version->funcs->hw_init(adev); | |
3038 | ||
0aaeefcc | 3039 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3040 | if (r) |
3041 | return r; | |
482f0e53 | 3042 | block->status.hw = true; |
a90ad3c2 ML |
3043 | } |
3044 | } | |
3045 | ||
3046 | return 0; | |
3047 | } | |
3048 | ||
e3ecdffa AD |
3049 | /** |
3050 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
3051 | * | |
3052 | * @adev: amdgpu_device pointer | |
3053 | * | |
3054 | * First resume function for hardware IPs. The list of all the hardware | |
3055 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3056 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
3057 | * after a suspend and updates the software state as necessary. This | |
3058 | * function is also used for restoring the GPU after a GPU reset. | |
3059 | * Returns 0 on success, negative error code on failure. | |
3060 | */ | |
06ec9070 | 3061 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
3062 | { |
3063 | int i, r; | |
3064 | ||
a90ad3c2 | 3065 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 3066 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 3067 | continue; |
a90ad3c2 | 3068 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
3069 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
3070 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 3071 | |
fcf0649f CZ |
3072 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
3073 | if (r) { | |
3074 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
3075 | adev->ip_blocks[i].version->funcs->name, r); | |
3076 | return r; | |
3077 | } | |
482f0e53 | 3078 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
3079 | } |
3080 | } | |
3081 | ||
3082 | return 0; | |
3083 | } | |
3084 | ||
e3ecdffa AD |
3085 | /** |
3086 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
3087 | * | |
3088 | * @adev: amdgpu_device pointer | |
3089 | * | |
3090 | * First resume function for hardware IPs. The list of all the hardware | |
3091 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3092 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
3093 | * functional state after a suspend and updates the software state as | |
3094 | * necessary. This function is also used for restoring the GPU after a GPU | |
3095 | * reset. | |
3096 | * Returns 0 on success, negative error code on failure. | |
3097 | */ | |
06ec9070 | 3098 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
3099 | { |
3100 | int i, r; | |
3101 | ||
3102 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 3103 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 3104 | continue; |
fcf0649f | 3105 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3106 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
3107 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3108 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 3109 | continue; |
a1255107 | 3110 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 3111 | if (r) { |
a1255107 AD |
3112 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
3113 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 3114 | return r; |
2c1a2784 | 3115 | } |
482f0e53 | 3116 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
3117 | } |
3118 | ||
3119 | return 0; | |
3120 | } | |
3121 | ||
e3ecdffa AD |
3122 | /** |
3123 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
3124 | * | |
3125 | * @adev: amdgpu_device pointer | |
3126 | * | |
3127 | * Main resume function for hardware IPs. The hardware IPs | |
3128 | * are split into two resume functions because they are | |
3129 | * are also used in in recovering from a GPU reset and some additional | |
3130 | * steps need to be take between them. In this case (S3/S4) they are | |
3131 | * run sequentially. | |
3132 | * Returns 0 on success, negative error code on failure. | |
3133 | */ | |
06ec9070 | 3134 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
3135 | { |
3136 | int r; | |
3137 | ||
9cec53c1 JZ |
3138 | r = amdgpu_amdkfd_resume_iommu(adev); |
3139 | if (r) | |
3140 | return r; | |
3141 | ||
06ec9070 | 3142 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
3143 | if (r) |
3144 | return r; | |
7a3e0bb2 RZ |
3145 | |
3146 | r = amdgpu_device_fw_loading(adev); | |
3147 | if (r) | |
3148 | return r; | |
3149 | ||
06ec9070 | 3150 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
3151 | |
3152 | return r; | |
3153 | } | |
3154 | ||
e3ecdffa AD |
3155 | /** |
3156 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
3157 | * | |
3158 | * @adev: amdgpu_device pointer | |
3159 | * | |
3160 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
3161 | */ | |
4e99a44e | 3162 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 3163 | { |
6867e1b5 ML |
3164 | if (amdgpu_sriov_vf(adev)) { |
3165 | if (adev->is_atom_fw) { | |
58ff791a | 3166 | if (amdgpu_atomfirmware_gpu_virtualization_supported(adev)) |
6867e1b5 ML |
3167 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; |
3168 | } else { | |
3169 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3170 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3171 | } | |
3172 | ||
3173 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3174 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3175 | } |
048765ad AR |
3176 | } |
3177 | ||
e3ecdffa AD |
3178 | /** |
3179 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3180 | * | |
3181 | * @asic_type: AMD asic type | |
3182 | * | |
3183 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3184 | * returns true if DC has support, false if not. | |
3185 | */ | |
4562236b HW |
3186 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3187 | { | |
3188 | switch (asic_type) { | |
3189 | #if defined(CONFIG_DRM_AMD_DC) | |
64200c46 MR |
3190 | case CHIP_TAHITI: |
3191 | case CHIP_PITCAIRN: | |
3192 | case CHIP_VERDE: | |
3193 | case CHIP_OLAND: | |
2d32ffd6 AD |
3194 | /* |
3195 | * We have systems in the wild with these ASICs that require | |
3196 | * LVDS and VGA support which is not supported with DC. | |
3197 | * | |
3198 | * Fallback to the non-DC driver here by default so as not to | |
3199 | * cause regressions. | |
3200 | */ | |
3201 | #if defined(CONFIG_DRM_AMD_DC_SI) | |
3202 | return amdgpu_dc > 0; | |
3203 | #else | |
3204 | return false; | |
64200c46 | 3205 | #endif |
4562236b | 3206 | case CHIP_BONAIRE: |
0d6fbccb | 3207 | case CHIP_KAVERI: |
367e6687 AD |
3208 | case CHIP_KABINI: |
3209 | case CHIP_MULLINS: | |
d9fda248 HW |
3210 | /* |
3211 | * We have systems in the wild with these ASICs that require | |
3212 | * LVDS and VGA support which is not supported with DC. | |
3213 | * | |
3214 | * Fallback to the non-DC driver here by default so as not to | |
3215 | * cause regressions. | |
3216 | */ | |
3217 | return amdgpu_dc > 0; | |
3218 | case CHIP_HAWAII: | |
4562236b HW |
3219 | case CHIP_CARRIZO: |
3220 | case CHIP_STONEY: | |
4562236b | 3221 | case CHIP_POLARIS10: |
675fd32b | 3222 | case CHIP_POLARIS11: |
2c8ad2d5 | 3223 | case CHIP_POLARIS12: |
675fd32b | 3224 | case CHIP_VEGAM: |
4562236b HW |
3225 | case CHIP_TONGA: |
3226 | case CHIP_FIJI: | |
42f8ffa1 | 3227 | case CHIP_VEGA10: |
dca7b401 | 3228 | case CHIP_VEGA12: |
c6034aa2 | 3229 | case CHIP_VEGA20: |
b86a1aa3 | 3230 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
fd187853 | 3231 | case CHIP_RAVEN: |
b4f199c7 | 3232 | case CHIP_NAVI10: |
8fceceb6 | 3233 | case CHIP_NAVI14: |
078655d9 | 3234 | case CHIP_NAVI12: |
e1c14c43 | 3235 | case CHIP_RENOIR: |
3f68c01b | 3236 | case CHIP_CYAN_SKILLFISH: |
81d9bfb8 | 3237 | case CHIP_SIENNA_CICHLID: |
a6c5308f | 3238 | case CHIP_NAVY_FLOUNDER: |
7cc656e2 | 3239 | case CHIP_DIMGREY_CAVEFISH: |
ddaed58b | 3240 | case CHIP_BEIGE_GOBY: |
84b934bc | 3241 | case CHIP_VANGOGH: |
c8b73f7f | 3242 | case CHIP_YELLOW_CARP: |
42f8ffa1 | 3243 | #endif |
f7f12b25 | 3244 | default: |
fd187853 | 3245 | return amdgpu_dc != 0; |
f7f12b25 | 3246 | #else |
4562236b | 3247 | default: |
93b09a9a | 3248 | if (amdgpu_dc > 0) |
044a48f4 | 3249 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter " |
93b09a9a | 3250 | "but isn't supported by ASIC, ignoring\n"); |
4562236b | 3251 | return false; |
f7f12b25 | 3252 | #endif |
4562236b HW |
3253 | } |
3254 | } | |
3255 | ||
3256 | /** | |
3257 | * amdgpu_device_has_dc_support - check if dc is supported | |
3258 | * | |
982a820b | 3259 | * @adev: amdgpu_device pointer |
4562236b HW |
3260 | * |
3261 | * Returns true for supported, false for not supported | |
3262 | */ | |
3263 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3264 | { | |
abaf210c AS |
3265 | if (amdgpu_sriov_vf(adev) || |
3266 | adev->enable_virtual_display || | |
3267 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) | |
2555039d XY |
3268 | return false; |
3269 | ||
4562236b HW |
3270 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3271 | } | |
3272 | ||
d4535e2c AG |
3273 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) |
3274 | { | |
3275 | struct amdgpu_device *adev = | |
3276 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3277 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3278 | |
c6a6e2db AG |
3279 | /* It's a bug to not have a hive within this function */ |
3280 | if (WARN_ON(!hive)) | |
3281 | return; | |
3282 | ||
3283 | /* | |
3284 | * Use task barrier to synchronize all xgmi reset works across the | |
3285 | * hive. task_barrier_enter and task_barrier_exit will block | |
3286 | * until all the threads running the xgmi reset works reach | |
3287 | * those points. task_barrier_full will do both blocks. | |
3288 | */ | |
3289 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3290 | ||
3291 | task_barrier_enter(&hive->tb); | |
4a580877 | 3292 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3293 | |
3294 | if (adev->asic_reset_res) | |
3295 | goto fail; | |
3296 | ||
3297 | task_barrier_exit(&hive->tb); | |
4a580877 | 3298 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3299 | |
3300 | if (adev->asic_reset_res) | |
3301 | goto fail; | |
43c4d576 | 3302 | |
8bc7b360 HZ |
3303 | if (adev->mmhub.ras_funcs && |
3304 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
3305 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
c6a6e2db AG |
3306 | } else { |
3307 | ||
3308 | task_barrier_full(&hive->tb); | |
3309 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3310 | } | |
ce316fa5 | 3311 | |
c6a6e2db | 3312 | fail: |
d4535e2c | 3313 | if (adev->asic_reset_res) |
fed184e9 | 3314 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3315 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3316 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3317 | } |
3318 | ||
71f98027 AD |
3319 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3320 | { | |
3321 | char *input = amdgpu_lockup_timeout; | |
3322 | char *timeout_setting = NULL; | |
3323 | int index = 0; | |
3324 | long timeout; | |
3325 | int ret = 0; | |
3326 | ||
3327 | /* | |
67387dfe AD |
3328 | * By default timeout for non compute jobs is 10000 |
3329 | * and 60000 for compute jobs. | |
71f98027 | 3330 | * In SR-IOV or passthrough mode, timeout for compute |
b7b2a316 | 3331 | * jobs are 60000 by default. |
71f98027 AD |
3332 | */ |
3333 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3334 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3335 | if (amdgpu_sriov_vf(adev)) |
3336 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3337 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
71f98027 | 3338 | else |
67387dfe | 3339 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 | 3340 | |
f440ff44 | 3341 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3342 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3343 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3344 | ret = kstrtol(timeout_setting, 0, &timeout); |
3345 | if (ret) | |
3346 | return ret; | |
3347 | ||
3348 | if (timeout == 0) { | |
3349 | index++; | |
3350 | continue; | |
3351 | } else if (timeout < 0) { | |
3352 | timeout = MAX_SCHEDULE_TIMEOUT; | |
127aedf9 CK |
3353 | dev_warn(adev->dev, "lockup timeout disabled"); |
3354 | add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK); | |
71f98027 AD |
3355 | } else { |
3356 | timeout = msecs_to_jiffies(timeout); | |
3357 | } | |
3358 | ||
3359 | switch (index++) { | |
3360 | case 0: | |
3361 | adev->gfx_timeout = timeout; | |
3362 | break; | |
3363 | case 1: | |
3364 | adev->compute_timeout = timeout; | |
3365 | break; | |
3366 | case 2: | |
3367 | adev->sdma_timeout = timeout; | |
3368 | break; | |
3369 | case 3: | |
3370 | adev->video_timeout = timeout; | |
3371 | break; | |
3372 | default: | |
3373 | break; | |
3374 | } | |
3375 | } | |
3376 | /* | |
3377 | * There is only one value specified and | |
3378 | * it should apply to all non-compute jobs. | |
3379 | */ | |
bcccee89 | 3380 | if (index == 1) { |
71f98027 | 3381 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3382 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3383 | adev->compute_timeout = adev->gfx_timeout; | |
3384 | } | |
71f98027 AD |
3385 | } |
3386 | ||
3387 | return ret; | |
3388 | } | |
d4535e2c | 3389 | |
4a74c38c PY |
3390 | /** |
3391 | * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU | |
3392 | * | |
3393 | * @adev: amdgpu_device pointer | |
3394 | * | |
3395 | * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode | |
3396 | */ | |
3397 | static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev) | |
3398 | { | |
3399 | struct iommu_domain *domain; | |
3400 | ||
3401 | domain = iommu_get_domain_for_dev(adev->dev); | |
3402 | if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) | |
3403 | adev->ram_is_direct_mapped = true; | |
3404 | } | |
3405 | ||
77f3a5cd ND |
3406 | static const struct attribute *amdgpu_dev_attributes[] = { |
3407 | &dev_attr_product_name.attr, | |
3408 | &dev_attr_product_number.attr, | |
3409 | &dev_attr_serial_number.attr, | |
3410 | &dev_attr_pcie_replay_count.attr, | |
3411 | NULL | |
3412 | }; | |
3413 | ||
d38ceaf9 AD |
3414 | /** |
3415 | * amdgpu_device_init - initialize the driver | |
3416 | * | |
3417 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3418 | * @flags: driver flags |
3419 | * | |
3420 | * Initializes the driver info and hw (all asics). | |
3421 | * Returns 0 for success or an error on failure. | |
3422 | * Called at driver startup. | |
3423 | */ | |
3424 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3425 | uint32_t flags) |
3426 | { | |
8aba21b7 LT |
3427 | struct drm_device *ddev = adev_to_drm(adev); |
3428 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3429 | int r, i; |
b98c6299 | 3430 | bool px = false; |
95844d20 | 3431 | u32 max_MBps; |
d38ceaf9 AD |
3432 | |
3433 | adev->shutdown = false; | |
d38ceaf9 | 3434 | adev->flags = flags; |
4e66d7d2 YZ |
3435 | |
3436 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3437 | adev->asic_type = amdgpu_force_asic_type; | |
3438 | else | |
3439 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3440 | ||
d38ceaf9 | 3441 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3442 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3443 | adev->usec_timeout *= 10; |
770d13b1 | 3444 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3445 | adev->accel_working = false; |
3446 | adev->num_rings = 0; | |
3447 | adev->mman.buffer_funcs = NULL; | |
3448 | adev->mman.buffer_funcs_ring = NULL; | |
3449 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3450 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3451 | adev->gmc.gmc_funcs = NULL; |
7bd939d0 | 3452 | adev->harvest_ip_mask = 0x0; |
f54d1867 | 3453 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3454 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3455 | |
3456 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3457 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3458 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3459 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3460 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3461 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3462 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3463 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3464 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3465 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3466 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3467 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3468 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3469 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3470 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3471 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3472 | ||
3e39ab90 AD |
3473 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3474 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3475 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3476 | |
3477 | /* mutex initialization are all done here so we | |
3478 | * can recall function without having locking issues */ | |
0e5ca0d1 | 3479 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3480 | mutex_init(&adev->pm.mutex); |
3481 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3482 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3483 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3484 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3485 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3486 | mutex_init(&adev->mn_lock); |
e23b74aa | 3487 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3488 | hash_init(adev->mn_hash); |
53b3f8f4 | 3489 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 3490 | init_rwsem(&adev->reset_sem); |
32eaeae0 | 3491 | mutex_init(&adev->psp.mutex); |
bd052211 | 3492 | mutex_init(&adev->notifier_lock); |
d38ceaf9 | 3493 | |
9f6a7857 HR |
3494 | r = amdgpu_device_init_apu_flags(adev); |
3495 | if (r) | |
3496 | return r; | |
3497 | ||
912dfc84 EQ |
3498 | r = amdgpu_device_check_arguments(adev); |
3499 | if (r) | |
3500 | return r; | |
d38ceaf9 | 3501 | |
d38ceaf9 AD |
3502 | spin_lock_init(&adev->mmio_idx_lock); |
3503 | spin_lock_init(&adev->smc_idx_lock); | |
3504 | spin_lock_init(&adev->pcie_idx_lock); | |
3505 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3506 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3507 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3508 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3509 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3510 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3511 | |
0c4e7fa5 CZ |
3512 | INIT_LIST_HEAD(&adev->shadow_list); |
3513 | mutex_init(&adev->shadow_list_lock); | |
3514 | ||
655ce9cb | 3515 | INIT_LIST_HEAD(&adev->reset_list); |
3516 | ||
beff74bc AD |
3517 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3518 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3519 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3520 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3521 | |
d4535e2c AG |
3522 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3523 | ||
d23ee13f | 3524 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3525 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3526 | |
b265bdbd EQ |
3527 | atomic_set(&adev->throttling_logging_enabled, 1); |
3528 | /* | |
3529 | * If throttling continues, logging will be performed every minute | |
3530 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3531 | * throttling interrupt comes every second. Thus, the total logging | |
3532 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3533 | * for throttling interrupt) = 60 seconds. | |
3534 | */ | |
3535 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3536 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3537 | ||
0fa49558 AX |
3538 | /* Registers mapping */ |
3539 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3540 | if (adev->asic_type >= CHIP_BONAIRE) { |
3541 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3542 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3543 | } else { | |
3544 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3545 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3546 | } | |
d38ceaf9 | 3547 | |
6c08e0ef EQ |
3548 | for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++) |
3549 | atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); | |
3550 | ||
d38ceaf9 AD |
3551 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3552 | if (adev->rmmio == NULL) { | |
3553 | return -ENOMEM; | |
3554 | } | |
3555 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3556 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3557 | ||
5494d864 AD |
3558 | amdgpu_device_get_pcie_info(adev); |
3559 | ||
b239c017 JX |
3560 | if (amdgpu_mcbp) |
3561 | DRM_INFO("MCBP is enabled\n"); | |
3562 | ||
5f84cc63 JX |
3563 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
3564 | adev->enable_mes = true; | |
3565 | ||
3aa0115d ML |
3566 | /* detect hw virtualization here */ |
3567 | amdgpu_detect_virtualization(adev); | |
3568 | ||
dffa11b4 ML |
3569 | r = amdgpu_device_get_job_timeout_settings(adev); |
3570 | if (r) { | |
3571 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
4ef87d8f | 3572 | return r; |
a190d1c7 XY |
3573 | } |
3574 | ||
d38ceaf9 | 3575 | /* early init functions */ |
06ec9070 | 3576 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 3577 | if (r) |
4ef87d8f | 3578 | return r; |
d38ceaf9 | 3579 | |
8e6d0b69 | 3580 | /* enable PCIE atomic ops */ |
3581 | if (amdgpu_sriov_vf(adev)) | |
3582 | adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *) | |
3583 | adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_enabled_flags == | |
3584 | (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3585 | else | |
3586 | adev->have_atomics_support = | |
3587 | !pci_enable_atomic_ops_to_root(adev->pdev, | |
3588 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3589 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3590 | if (!adev->have_atomics_support) | |
3591 | dev_info(adev->dev, "PCIE atomic ops is not supported\n"); | |
3592 | ||
6585661d OZ |
3593 | /* doorbell bar mapping and doorbell index init*/ |
3594 | amdgpu_device_doorbell_init(adev); | |
3595 | ||
9475a943 SL |
3596 | if (amdgpu_emu_mode == 1) { |
3597 | /* post the asic on emulation mode */ | |
3598 | emu_soc_asic_init(adev); | |
bfca0289 | 3599 | goto fence_driver_init; |
9475a943 | 3600 | } |
bfca0289 | 3601 | |
04442bf7 LL |
3602 | amdgpu_reset_init(adev); |
3603 | ||
4e99a44e ML |
3604 | /* detect if we are with an SRIOV vbios */ |
3605 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3606 | |
95e8e59e AD |
3607 | /* check if we need to reset the asic |
3608 | * E.g., driver was not cleanly unloaded previously, etc. | |
3609 | */ | |
f14899fd | 3610 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 3611 | if (adev->gmc.xgmi.num_physical_nodes) { |
3612 | dev_info(adev->dev, "Pending hive reset.\n"); | |
3613 | adev->gmc.xgmi.pending_reset = true; | |
3614 | /* Only need to init necessary block for SMU to handle the reset */ | |
3615 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3616 | if (!adev->ip_blocks[i].status.valid) | |
3617 | continue; | |
3618 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3619 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3620 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
3621 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 3622 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 3623 | adev->ip_blocks[i].version->funcs->name); |
3624 | adev->ip_blocks[i].status.hw = true; | |
3625 | } | |
3626 | } | |
3627 | } else { | |
3628 | r = amdgpu_asic_reset(adev); | |
3629 | if (r) { | |
3630 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3631 | goto failed; | |
3632 | } | |
95e8e59e AD |
3633 | } |
3634 | } | |
3635 | ||
8f66090b | 3636 | pci_enable_pcie_error_reporting(adev->pdev); |
c9a6b82f | 3637 | |
d38ceaf9 | 3638 | /* Post card if necessary */ |
39c640c0 | 3639 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3640 | if (!adev->bios) { |
bec86378 | 3641 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3642 | r = -EINVAL; |
3643 | goto failed; | |
d38ceaf9 | 3644 | } |
bec86378 | 3645 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3646 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3647 | if (r) { |
3648 | dev_err(adev->dev, "gpu post error!\n"); | |
3649 | goto failed; | |
3650 | } | |
d38ceaf9 AD |
3651 | } |
3652 | ||
88b64e95 AD |
3653 | if (adev->is_atom_fw) { |
3654 | /* Initialize clocks */ | |
3655 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3656 | if (r) { | |
3657 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3658 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3659 | goto failed; |
3660 | } | |
3661 | } else { | |
a5bde2f9 AD |
3662 | /* Initialize clocks */ |
3663 | r = amdgpu_atombios_get_clock_info(adev); | |
3664 | if (r) { | |
3665 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3666 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3667 | goto failed; |
a5bde2f9 AD |
3668 | } |
3669 | /* init i2c buses */ | |
4562236b HW |
3670 | if (!amdgpu_device_has_dc_support(adev)) |
3671 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3672 | } |
d38ceaf9 | 3673 | |
bfca0289 | 3674 | fence_driver_init: |
d38ceaf9 | 3675 | /* Fence driver */ |
067f44c8 | 3676 | r = amdgpu_fence_driver_sw_init(adev); |
2c1a2784 | 3677 | if (r) { |
067f44c8 | 3678 | dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n"); |
e23b74aa | 3679 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3680 | goto failed; |
2c1a2784 | 3681 | } |
d38ceaf9 AD |
3682 | |
3683 | /* init the mode config */ | |
4a580877 | 3684 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3685 | |
06ec9070 | 3686 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3687 | if (r) { |
8840a387 | 3688 | /* failed in exclusive mode due to timeout */ |
3689 | if (amdgpu_sriov_vf(adev) && | |
3690 | !amdgpu_sriov_runtime(adev) && | |
3691 | amdgpu_virt_mmio_blocked(adev) && | |
3692 | !amdgpu_virt_wait_reset(adev)) { | |
3693 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3694 | /* Don't send request since VF is inactive. */ |
3695 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3696 | adev->virt.ops = NULL; | |
8840a387 | 3697 | r = -EAGAIN; |
970fd197 | 3698 | goto release_ras_con; |
8840a387 | 3699 | } |
06ec9070 | 3700 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3701 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 3702 | goto release_ras_con; |
d38ceaf9 AD |
3703 | } |
3704 | ||
8d35a259 LG |
3705 | amdgpu_fence_driver_hw_init(adev); |
3706 | ||
d69b8971 YZ |
3707 | dev_info(adev->dev, |
3708 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3709 | adev->gfx.config.max_shader_engines, |
3710 | adev->gfx.config.max_sh_per_se, | |
3711 | adev->gfx.config.max_cu_per_sh, | |
3712 | adev->gfx.cu_info.number); | |
3713 | ||
d38ceaf9 AD |
3714 | adev->accel_working = true; |
3715 | ||
e59c0205 AX |
3716 | amdgpu_vm_check_compute_bug(adev); |
3717 | ||
95844d20 MO |
3718 | /* Initialize the buffer migration limit. */ |
3719 | if (amdgpu_moverate >= 0) | |
3720 | max_MBps = amdgpu_moverate; | |
3721 | else | |
3722 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3723 | /* Get a log2 for easy divisions. */ | |
3724 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3725 | ||
d2f52ac8 | 3726 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3727 | if (r) { |
3728 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3729 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3730 | } else |
3731 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3732 | |
5bb23532 | 3733 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3734 | if (r) { |
3735 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3736 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3737 | } else |
3738 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3739 | |
d38ceaf9 AD |
3740 | if ((amdgpu_testing & 1)) { |
3741 | if (adev->accel_working) | |
3742 | amdgpu_test_moves(adev); | |
3743 | else | |
3744 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
3745 | } | |
d38ceaf9 AD |
3746 | if (amdgpu_benchmarking) { |
3747 | if (adev->accel_working) | |
3748 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
3749 | else | |
3750 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
3751 | } | |
3752 | ||
b0adca4d EQ |
3753 | /* |
3754 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3755 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3756 | * gpu instance is counted less. | |
3757 | */ | |
3758 | amdgpu_register_gpu_instance(adev); | |
3759 | ||
d38ceaf9 AD |
3760 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3761 | * explicit gating rather than handling it automatically. | |
3762 | */ | |
e3c1b071 | 3763 | if (!adev->gmc.xgmi.pending_reset) { |
3764 | r = amdgpu_device_ip_late_init(adev); | |
3765 | if (r) { | |
3766 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
3767 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 3768 | goto release_ras_con; |
e3c1b071 | 3769 | } |
3770 | /* must succeed. */ | |
3771 | amdgpu_ras_resume(adev); | |
3772 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
3773 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 3774 | } |
d38ceaf9 | 3775 | |
2c738637 ML |
3776 | if (amdgpu_sriov_vf(adev)) |
3777 | flush_delayed_work(&adev->delayed_init_work); | |
3778 | ||
77f3a5cd | 3779 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 3780 | if (r) |
77f3a5cd | 3781 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 3782 | |
d155bef0 AB |
3783 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3784 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3785 | if (r) |
3786 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3787 | ||
c1dd4aa6 AG |
3788 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
3789 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
3790 | pci_restore_state(pdev); | |
3791 | ||
8c3dd61c KHF |
3792 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3793 | /* this will fail for cards that aren't VGA class devices, just | |
3794 | * ignore it */ | |
3795 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) | |
bf44e8ce | 3796 | vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); |
8c3dd61c KHF |
3797 | |
3798 | if (amdgpu_device_supports_px(ddev)) { | |
3799 | px = true; | |
3800 | vga_switcheroo_register_client(adev->pdev, | |
3801 | &amdgpu_switcheroo_ops, px); | |
3802 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
3803 | } | |
3804 | ||
e3c1b071 | 3805 | if (adev->gmc.xgmi.pending_reset) |
3806 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
3807 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3808 | ||
4a74c38c PY |
3809 | amdgpu_device_check_iommu_direct_map(adev); |
3810 | ||
d38ceaf9 | 3811 | return 0; |
83ba126a | 3812 | |
970fd197 SY |
3813 | release_ras_con: |
3814 | amdgpu_release_ras_context(adev); | |
3815 | ||
83ba126a | 3816 | failed: |
89041940 | 3817 | amdgpu_vf_error_trans_all(adev); |
8840a387 | 3818 | |
83ba126a | 3819 | return r; |
d38ceaf9 AD |
3820 | } |
3821 | ||
07775fc1 AG |
3822 | static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) |
3823 | { | |
3824 | /* Clear all CPU mappings pointing to this device */ | |
3825 | unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); | |
3826 | ||
3827 | /* Unmap all mapped bars - Doorbell, registers and VRAM */ | |
3828 | amdgpu_device_doorbell_fini(adev); | |
3829 | ||
3830 | iounmap(adev->rmmio); | |
3831 | adev->rmmio = NULL; | |
3832 | if (adev->mman.aper_base_kaddr) | |
3833 | iounmap(adev->mman.aper_base_kaddr); | |
3834 | adev->mman.aper_base_kaddr = NULL; | |
3835 | ||
3836 | /* Memory manager related */ | |
3837 | if (!adev->gmc.xgmi.connected_to_cpu) { | |
3838 | arch_phys_wc_del(adev->gmc.vram_mtrr); | |
3839 | arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); | |
3840 | } | |
3841 | } | |
3842 | ||
d38ceaf9 | 3843 | /** |
bbe04dec | 3844 | * amdgpu_device_fini_hw - tear down the driver |
d38ceaf9 AD |
3845 | * |
3846 | * @adev: amdgpu_device pointer | |
3847 | * | |
3848 | * Tear down the driver info (all asics). | |
3849 | * Called at driver shutdown. | |
3850 | */ | |
72c8c97b | 3851 | void amdgpu_device_fini_hw(struct amdgpu_device *adev) |
d38ceaf9 | 3852 | { |
aac89168 | 3853 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3854 | flush_delayed_work(&adev->delayed_init_work); |
691191a2 YW |
3855 | if (adev->mman.initialized) { |
3856 | flush_delayed_work(&adev->mman.bdev.wq); | |
e78b3197 | 3857 | ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); |
691191a2 | 3858 | } |
d0d13fe8 | 3859 | adev->shutdown = true; |
9f875167 | 3860 | |
752c683d ML |
3861 | /* make sure IB test finished before entering exclusive mode |
3862 | * to avoid preemption on IB test | |
3863 | * */ | |
519b8b76 | 3864 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 3865 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
3866 | amdgpu_virt_fini_data_exchange(adev); |
3867 | } | |
752c683d | 3868 | |
e5b03032 ML |
3869 | /* disable all interrupts */ |
3870 | amdgpu_irq_disable_all(adev); | |
ff97cba8 | 3871 | if (adev->mode_info.mode_config_initialized){ |
700de2c8 | 3872 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) |
4a580877 | 3873 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3874 | else |
4a580877 | 3875 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3876 | } |
8d35a259 | 3877 | amdgpu_fence_driver_hw_fini(adev); |
72c8c97b | 3878 | |
7c868b59 YT |
3879 | if (adev->pm_sysfs_en) |
3880 | amdgpu_pm_sysfs_fini(adev); | |
72c8c97b AG |
3881 | if (adev->ucode_sysfs_en) |
3882 | amdgpu_ucode_sysfs_fini(adev); | |
3883 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
3884 | ||
232d1d43 SY |
3885 | /* disable ras feature must before hw fini */ |
3886 | amdgpu_ras_pre_fini(adev); | |
3887 | ||
e9669fb7 | 3888 | amdgpu_device_ip_fini_early(adev); |
d10d0daa | 3889 | |
a3848df6 YW |
3890 | amdgpu_irq_fini_hw(adev); |
3891 | ||
894c6890 AG |
3892 | ttm_device_clear_dma_mappings(&adev->mman.bdev); |
3893 | ||
d10d0daa | 3894 | amdgpu_gart_dummy_page_fini(adev); |
07775fc1 AG |
3895 | |
3896 | amdgpu_device_unmap_mmio(adev); | |
72c8c97b AG |
3897 | } |
3898 | ||
3899 | void amdgpu_device_fini_sw(struct amdgpu_device *adev) | |
3900 | { | |
8d35a259 | 3901 | amdgpu_fence_driver_sw_fini(adev); |
a5c5d8d5 | 3902 | amdgpu_device_ip_fini(adev); |
75e1658e ND |
3903 | release_firmware(adev->firmware.gpu_info_fw); |
3904 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 | 3905 | adev->accel_working = false; |
04442bf7 LL |
3906 | |
3907 | amdgpu_reset_fini(adev); | |
3908 | ||
d38ceaf9 | 3909 | /* free i2c buses */ |
4562236b HW |
3910 | if (!amdgpu_device_has_dc_support(adev)) |
3911 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3912 | |
3913 | if (amdgpu_emu_mode != 1) | |
3914 | amdgpu_atombios_fini(adev); | |
3915 | ||
d38ceaf9 AD |
3916 | kfree(adev->bios); |
3917 | adev->bios = NULL; | |
b98c6299 | 3918 | if (amdgpu_device_supports_px(adev_to_drm(adev))) { |
84c8b22e | 3919 | vga_switcheroo_unregister_client(adev->pdev); |
83ba126a | 3920 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
b98c6299 | 3921 | } |
38d6be81 | 3922 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
b8779475 | 3923 | vga_client_unregister(adev->pdev); |
e9bc1bf7 | 3924 | |
d155bef0 AB |
3925 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3926 | amdgpu_pmu_fini(adev); | |
72de33f8 | 3927 | if (adev->mman.discovery_bin) |
a190d1c7 | 3928 | amdgpu_discovery_fini(adev); |
72c8c97b AG |
3929 | |
3930 | kfree(adev->pci_state); | |
3931 | ||
d38ceaf9 AD |
3932 | } |
3933 | ||
58144d28 ND |
3934 | /** |
3935 | * amdgpu_device_evict_resources - evict device resources | |
3936 | * @adev: amdgpu device object | |
3937 | * | |
3938 | * Evicts all ttm device resources(vram BOs, gart table) from the lru list | |
3939 | * of the vram memory type. Mainly used for evicting device resources | |
3940 | * at suspend time. | |
3941 | * | |
3942 | */ | |
3943 | static void amdgpu_device_evict_resources(struct amdgpu_device *adev) | |
3944 | { | |
3945 | /* No need to evict vram on APUs for suspend to ram */ | |
3946 | if (adev->in_s3 && (adev->flags & AMD_IS_APU)) | |
3947 | return; | |
3948 | ||
3949 | if (amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM)) | |
3950 | DRM_WARN("evicting device resources failed\n"); | |
3951 | ||
3952 | } | |
d38ceaf9 AD |
3953 | |
3954 | /* | |
3955 | * Suspend & resume. | |
3956 | */ | |
3957 | /** | |
810ddc3a | 3958 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3959 | * |
87e3f136 | 3960 | * @dev: drm dev pointer |
87e3f136 | 3961 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
3962 | * |
3963 | * Puts the hw in the suspend state (all asics). | |
3964 | * Returns 0 for success or an error on failure. | |
3965 | * Called at driver suspend. | |
3966 | */ | |
de185019 | 3967 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 3968 | { |
a2e15b0e | 3969 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 3970 | |
d38ceaf9 AD |
3971 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
3972 | return 0; | |
3973 | ||
44779b43 | 3974 | adev->in_suspend = true; |
3fa8f89d S |
3975 | |
3976 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3)) | |
3977 | DRM_WARN("smart shift update failed\n"); | |
3978 | ||
d38ceaf9 AD |
3979 | drm_kms_helper_poll_disable(dev); |
3980 | ||
5f818173 | 3981 | if (fbcon) |
087451f3 | 3982 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); |
5f818173 | 3983 | |
beff74bc | 3984 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3985 | |
5e6932fe | 3986 | amdgpu_ras_suspend(adev); |
3987 | ||
2196927b | 3988 | amdgpu_device_ip_suspend_phase1(adev); |
fe1053b7 | 3989 | |
5d3a2d95 AD |
3990 | if (!adev->in_s0ix) |
3991 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); | |
94fa5660 | 3992 | |
58144d28 ND |
3993 | /* First evict vram memory */ |
3994 | amdgpu_device_evict_resources(adev); | |
d38ceaf9 | 3995 | |
8d35a259 | 3996 | amdgpu_fence_driver_hw_fini(adev); |
d38ceaf9 | 3997 | |
2196927b | 3998 | amdgpu_device_ip_suspend_phase2(adev); |
58144d28 ND |
3999 | /* This second call to evict device resources is to evict |
4000 | * the gart page table using the CPU. | |
a0a71e49 | 4001 | */ |
58144d28 | 4002 | amdgpu_device_evict_resources(adev); |
d38ceaf9 | 4003 | |
d38ceaf9 AD |
4004 | return 0; |
4005 | } | |
4006 | ||
4007 | /** | |
810ddc3a | 4008 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 4009 | * |
87e3f136 | 4010 | * @dev: drm dev pointer |
87e3f136 | 4011 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
4012 | * |
4013 | * Bring the hw back to operating state (all asics). | |
4014 | * Returns 0 for success or an error on failure. | |
4015 | * Called at driver resume. | |
4016 | */ | |
de185019 | 4017 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 4018 | { |
1348969a | 4019 | struct amdgpu_device *adev = drm_to_adev(dev); |
03161a6e | 4020 | int r = 0; |
d38ceaf9 AD |
4021 | |
4022 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
4023 | return 0; | |
4024 | ||
62498733 | 4025 | if (adev->in_s0ix) |
628c36d7 PL |
4026 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry); |
4027 | ||
d38ceaf9 | 4028 | /* post card */ |
39c640c0 | 4029 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 4030 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 4031 | if (r) |
aac89168 | 4032 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 4033 | } |
d38ceaf9 | 4034 | |
06ec9070 | 4035 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 4036 | if (r) { |
aac89168 | 4037 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 4038 | return r; |
e6707218 | 4039 | } |
8d35a259 | 4040 | amdgpu_fence_driver_hw_init(adev); |
5ceb54c6 | 4041 | |
06ec9070 | 4042 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 4043 | if (r) |
4d3b9ae5 | 4044 | return r; |
d38ceaf9 | 4045 | |
beff74bc AD |
4046 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
4047 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
4048 | ||
5d3a2d95 AD |
4049 | if (!adev->in_s0ix) { |
4050 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); | |
4051 | if (r) | |
4052 | return r; | |
4053 | } | |
756e6880 | 4054 | |
96a5d8d4 | 4055 | /* Make sure IB tests flushed */ |
beff74bc | 4056 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 4057 | |
a2e15b0e | 4058 | if (fbcon) |
087451f3 | 4059 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false); |
d38ceaf9 AD |
4060 | |
4061 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 4062 | |
5e6932fe | 4063 | amdgpu_ras_resume(adev); |
4064 | ||
23a1a9e5 L |
4065 | /* |
4066 | * Most of the connector probing functions try to acquire runtime pm | |
4067 | * refs to ensure that the GPU is powered on when connector polling is | |
4068 | * performed. Since we're calling this from a runtime PM callback, | |
4069 | * trying to acquire rpm refs will cause us to deadlock. | |
4070 | * | |
4071 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
4072 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
4073 | */ | |
4074 | #ifdef CONFIG_PM | |
4075 | dev->dev->power.disable_depth++; | |
4076 | #endif | |
4562236b HW |
4077 | if (!amdgpu_device_has_dc_support(adev)) |
4078 | drm_helper_hpd_irq_event(dev); | |
4079 | else | |
4080 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
4081 | #ifdef CONFIG_PM |
4082 | dev->dev->power.disable_depth--; | |
4083 | #endif | |
44779b43 RZ |
4084 | adev->in_suspend = false; |
4085 | ||
3fa8f89d S |
4086 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0)) |
4087 | DRM_WARN("smart shift update failed\n"); | |
4088 | ||
4d3b9ae5 | 4089 | return 0; |
d38ceaf9 AD |
4090 | } |
4091 | ||
e3ecdffa AD |
4092 | /** |
4093 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
4094 | * | |
4095 | * @adev: amdgpu_device pointer | |
4096 | * | |
4097 | * The list of all the hardware IPs that make up the asic is walked and | |
4098 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
4099 | * if the asic is still hung or not. | |
4100 | * Returns true if any of the IPs are still in a hung state, false if not. | |
4101 | */ | |
06ec9070 | 4102 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
4103 | { |
4104 | int i; | |
4105 | bool asic_hang = false; | |
4106 | ||
f993d628 ML |
4107 | if (amdgpu_sriov_vf(adev)) |
4108 | return true; | |
4109 | ||
8bc04c29 AD |
4110 | if (amdgpu_asic_need_full_reset(adev)) |
4111 | return true; | |
4112 | ||
63fbf42f | 4113 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4114 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 4115 | continue; |
a1255107 AD |
4116 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
4117 | adev->ip_blocks[i].status.hang = | |
4118 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
4119 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 4120 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
4121 | asic_hang = true; |
4122 | } | |
4123 | } | |
4124 | return asic_hang; | |
4125 | } | |
4126 | ||
e3ecdffa AD |
4127 | /** |
4128 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
4129 | * | |
4130 | * @adev: amdgpu_device pointer | |
4131 | * | |
4132 | * The list of all the hardware IPs that make up the asic is walked and the | |
4133 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
4134 | * handles any IP specific hardware or software state changes that are | |
4135 | * necessary for a soft reset to succeed. | |
4136 | * Returns 0 on success, negative error code on failure. | |
4137 | */ | |
06ec9070 | 4138 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
4139 | { |
4140 | int i, r = 0; | |
4141 | ||
4142 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4143 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 4144 | continue; |
a1255107 AD |
4145 | if (adev->ip_blocks[i].status.hang && |
4146 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
4147 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
4148 | if (r) |
4149 | return r; | |
4150 | } | |
4151 | } | |
4152 | ||
4153 | return 0; | |
4154 | } | |
4155 | ||
e3ecdffa AD |
4156 | /** |
4157 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
4158 | * | |
4159 | * @adev: amdgpu_device pointer | |
4160 | * | |
4161 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
4162 | * reset is necessary to recover. | |
4163 | * Returns true if a full asic reset is required, false if not. | |
4164 | */ | |
06ec9070 | 4165 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 4166 | { |
da146d3b AD |
4167 | int i; |
4168 | ||
8bc04c29 AD |
4169 | if (amdgpu_asic_need_full_reset(adev)) |
4170 | return true; | |
4171 | ||
da146d3b | 4172 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4173 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 4174 | continue; |
a1255107 AD |
4175 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
4176 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
4177 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
4178 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
4179 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 4180 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 4181 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
4182 | return true; |
4183 | } | |
4184 | } | |
35d782fe CZ |
4185 | } |
4186 | return false; | |
4187 | } | |
4188 | ||
e3ecdffa AD |
4189 | /** |
4190 | * amdgpu_device_ip_soft_reset - do a soft reset | |
4191 | * | |
4192 | * @adev: amdgpu_device pointer | |
4193 | * | |
4194 | * The list of all the hardware IPs that make up the asic is walked and the | |
4195 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
4196 | * IP specific hardware or software state changes that are necessary to soft | |
4197 | * reset the IP. | |
4198 | * Returns 0 on success, negative error code on failure. | |
4199 | */ | |
06ec9070 | 4200 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4201 | { |
4202 | int i, r = 0; | |
4203 | ||
4204 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4205 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4206 | continue; |
a1255107 AD |
4207 | if (adev->ip_blocks[i].status.hang && |
4208 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
4209 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
4210 | if (r) |
4211 | return r; | |
4212 | } | |
4213 | } | |
4214 | ||
4215 | return 0; | |
4216 | } | |
4217 | ||
e3ecdffa AD |
4218 | /** |
4219 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
4220 | * | |
4221 | * @adev: amdgpu_device pointer | |
4222 | * | |
4223 | * The list of all the hardware IPs that make up the asic is walked and the | |
4224 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
4225 | * handles any IP specific hardware or software state changes that are | |
4226 | * necessary after the IP has been soft reset. | |
4227 | * Returns 0 on success, negative error code on failure. | |
4228 | */ | |
06ec9070 | 4229 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4230 | { |
4231 | int i, r = 0; | |
4232 | ||
4233 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4234 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4235 | continue; |
a1255107 AD |
4236 | if (adev->ip_blocks[i].status.hang && |
4237 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
4238 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
4239 | if (r) |
4240 | return r; | |
4241 | } | |
4242 | ||
4243 | return 0; | |
4244 | } | |
4245 | ||
e3ecdffa | 4246 | /** |
c33adbc7 | 4247 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4248 | * |
4249 | * @adev: amdgpu_device pointer | |
4250 | * | |
4251 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4252 | * restore things like GPUVM page tables after a GPU reset where | |
4253 | * the contents of VRAM might be lost. | |
403009bf CK |
4254 | * |
4255 | * Returns: | |
4256 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4257 | */ |
c33adbc7 | 4258 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4259 | { |
c41d1cf6 | 4260 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf | 4261 | struct amdgpu_bo *shadow; |
e18aaea7 | 4262 | struct amdgpu_bo_vm *vmbo; |
403009bf | 4263 | long r = 1, tmo; |
c41d1cf6 ML |
4264 | |
4265 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4266 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4267 | else |
4268 | tmo = msecs_to_jiffies(100); | |
4269 | ||
aac89168 | 4270 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4271 | mutex_lock(&adev->shadow_list_lock); |
e18aaea7 ND |
4272 | list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { |
4273 | shadow = &vmbo->bo; | |
403009bf | 4274 | /* No need to recover an evicted BO */ |
d3116756 CK |
4275 | if (shadow->tbo.resource->mem_type != TTM_PL_TT || |
4276 | shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || | |
4277 | shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) | |
403009bf CK |
4278 | continue; |
4279 | ||
4280 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4281 | if (r) | |
4282 | break; | |
4283 | ||
c41d1cf6 | 4284 | if (fence) { |
1712fb1a | 4285 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4286 | dma_fence_put(fence); |
4287 | fence = next; | |
1712fb1a | 4288 | if (tmo == 0) { |
4289 | r = -ETIMEDOUT; | |
c41d1cf6 | 4290 | break; |
1712fb1a | 4291 | } else if (tmo < 0) { |
4292 | r = tmo; | |
4293 | break; | |
4294 | } | |
403009bf CK |
4295 | } else { |
4296 | fence = next; | |
c41d1cf6 | 4297 | } |
c41d1cf6 ML |
4298 | } |
4299 | mutex_unlock(&adev->shadow_list_lock); | |
4300 | ||
403009bf CK |
4301 | if (fence) |
4302 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4303 | dma_fence_put(fence); |
4304 | ||
1712fb1a | 4305 | if (r < 0 || tmo <= 0) { |
aac89168 | 4306 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4307 | return -EIO; |
4308 | } | |
c41d1cf6 | 4309 | |
aac89168 | 4310 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4311 | return 0; |
c41d1cf6 ML |
4312 | } |
4313 | ||
a90ad3c2 | 4314 | |
e3ecdffa | 4315 | /** |
06ec9070 | 4316 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4317 | * |
982a820b | 4318 | * @adev: amdgpu_device pointer |
87e3f136 | 4319 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4320 | * |
4321 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4322 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4323 | */ |
4324 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4325 | bool from_hypervisor) | |
5740682e ML |
4326 | { |
4327 | int r; | |
a5f67c93 | 4328 | struct amdgpu_hive_info *hive = NULL; |
5740682e | 4329 | |
992110d7 | 4330 | amdgpu_amdkfd_pre_reset(adev); |
4331 | ||
5740682e ML |
4332 | if (from_hypervisor) |
4333 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4334 | else | |
4335 | r = amdgpu_virt_reset_gpu(adev); | |
4336 | if (r) | |
4337 | return r; | |
a90ad3c2 ML |
4338 | |
4339 | /* Resume IP prior to SMC */ | |
06ec9070 | 4340 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4341 | if (r) |
4342 | goto error; | |
a90ad3c2 | 4343 | |
c9ffa427 | 4344 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4345 | /* we need recover gart prior to run SMC/CP/SDMA resume */ |
6c28aed6 | 4346 | amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); |
a90ad3c2 | 4347 | |
7a3e0bb2 RZ |
4348 | r = amdgpu_device_fw_loading(adev); |
4349 | if (r) | |
4350 | return r; | |
4351 | ||
a90ad3c2 | 4352 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4353 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4354 | if (r) |
4355 | goto error; | |
a90ad3c2 | 4356 | |
a5f67c93 ZL |
4357 | hive = amdgpu_get_xgmi_hive(adev); |
4358 | /* Update PSP FW topology after reset */ | |
4359 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) | |
4360 | r = amdgpu_xgmi_update_topology(hive, adev); | |
4361 | ||
4362 | if (hive) | |
4363 | amdgpu_put_xgmi_hive(hive); | |
4364 | ||
4365 | if (!r) { | |
4366 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
4367 | r = amdgpu_ib_ring_tests(adev); | |
4368 | amdgpu_amdkfd_post_reset(adev); | |
4369 | } | |
a90ad3c2 | 4370 | |
abc34253 | 4371 | error: |
c41d1cf6 | 4372 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 4373 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 4374 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 | 4375 | } |
437f3e0b | 4376 | amdgpu_virt_release_full_gpu(adev, true); |
a90ad3c2 ML |
4377 | |
4378 | return r; | |
4379 | } | |
4380 | ||
9a1cddd6 | 4381 | /** |
4382 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
4383 | * | |
982a820b | 4384 | * @adev: amdgpu_device pointer |
9a1cddd6 | 4385 | * |
4386 | * check if there is any job in mirror list | |
4387 | */ | |
4388 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
4389 | { | |
4390 | int i; | |
4391 | struct drm_sched_job *job; | |
4392 | ||
4393 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4394 | struct amdgpu_ring *ring = adev->rings[i]; | |
4395 | ||
4396 | if (!ring || !ring->sched.thread) | |
4397 | continue; | |
4398 | ||
4399 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
4400 | job = list_first_entry_or_null(&ring->sched.pending_list, |
4401 | struct drm_sched_job, list); | |
9a1cddd6 | 4402 | spin_unlock(&ring->sched.job_list_lock); |
4403 | if (job) | |
4404 | return true; | |
4405 | } | |
4406 | return false; | |
4407 | } | |
4408 | ||
12938fad CK |
4409 | /** |
4410 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
4411 | * | |
982a820b | 4412 | * @adev: amdgpu_device pointer |
12938fad CK |
4413 | * |
4414 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
4415 | * a hung GPU. | |
4416 | */ | |
4417 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
4418 | { | |
4419 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4420 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
4421 | return false; |
4422 | } | |
4423 | ||
3ba7b418 AG |
4424 | if (amdgpu_gpu_recovery == 0) |
4425 | goto disabled; | |
4426 | ||
4427 | if (amdgpu_sriov_vf(adev)) | |
4428 | return true; | |
4429 | ||
4430 | if (amdgpu_gpu_recovery == -1) { | |
4431 | switch (adev->asic_type) { | |
fc42d47c AG |
4432 | case CHIP_BONAIRE: |
4433 | case CHIP_HAWAII: | |
3ba7b418 AG |
4434 | case CHIP_TOPAZ: |
4435 | case CHIP_TONGA: | |
4436 | case CHIP_FIJI: | |
4437 | case CHIP_POLARIS10: | |
4438 | case CHIP_POLARIS11: | |
4439 | case CHIP_POLARIS12: | |
4440 | case CHIP_VEGAM: | |
4441 | case CHIP_VEGA20: | |
4442 | case CHIP_VEGA10: | |
4443 | case CHIP_VEGA12: | |
c43b849f | 4444 | case CHIP_RAVEN: |
e9d4cf91 | 4445 | case CHIP_ARCTURUS: |
2cb44fb0 | 4446 | case CHIP_RENOIR: |
658c6639 AD |
4447 | case CHIP_NAVI10: |
4448 | case CHIP_NAVI14: | |
4449 | case CHIP_NAVI12: | |
131a3c74 | 4450 | case CHIP_SIENNA_CICHLID: |
665fe4dc | 4451 | case CHIP_NAVY_FLOUNDER: |
27859ee3 | 4452 | case CHIP_DIMGREY_CAVEFISH: |
a2f55040 | 4453 | case CHIP_BEIGE_GOBY: |
fe68ceef | 4454 | case CHIP_VANGOGH: |
ea4e96a7 | 4455 | case CHIP_ALDEBARAN: |
3ba7b418 AG |
4456 | break; |
4457 | default: | |
4458 | goto disabled; | |
4459 | } | |
12938fad CK |
4460 | } |
4461 | ||
4462 | return true; | |
3ba7b418 AG |
4463 | |
4464 | disabled: | |
aac89168 | 4465 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4466 | return false; |
12938fad CK |
4467 | } |
4468 | ||
5c03e584 FX |
4469 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
4470 | { | |
4471 | u32 i; | |
4472 | int ret = 0; | |
4473 | ||
4474 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
4475 | ||
4476 | dev_info(adev->dev, "GPU mode1 reset\n"); | |
4477 | ||
4478 | /* disable BM */ | |
4479 | pci_clear_master(adev->pdev); | |
4480 | ||
4481 | amdgpu_device_cache_pci_state(adev->pdev); | |
4482 | ||
4483 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
4484 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
4485 | ret = amdgpu_dpm_mode1_reset(adev); | |
4486 | } else { | |
4487 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
4488 | ret = psp_gpu_reset(adev); | |
4489 | } | |
4490 | ||
4491 | if (ret) | |
4492 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
4493 | ||
4494 | amdgpu_device_load_pci_state(adev->pdev); | |
4495 | ||
4496 | /* wait for asic to come out of reset */ | |
4497 | for (i = 0; i < adev->usec_timeout; i++) { | |
4498 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
4499 | ||
4500 | if (memsize != 0xffffffff) | |
4501 | break; | |
4502 | udelay(1); | |
4503 | } | |
4504 | ||
4505 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
4506 | return ret; | |
4507 | } | |
5c6dd71e | 4508 | |
e3c1b071 | 4509 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
04442bf7 | 4510 | struct amdgpu_reset_context *reset_context) |
26bc5340 | 4511 | { |
5c1e6fa4 | 4512 | int i, r = 0; |
04442bf7 LL |
4513 | struct amdgpu_job *job = NULL; |
4514 | bool need_full_reset = | |
4515 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4516 | ||
4517 | if (reset_context->reset_req_dev == adev) | |
4518 | job = reset_context->job; | |
71182665 | 4519 | |
b602ca5f TZ |
4520 | if (amdgpu_sriov_vf(adev)) { |
4521 | /* stop the data exchange thread */ | |
4522 | amdgpu_virt_fini_data_exchange(adev); | |
4523 | } | |
4524 | ||
71182665 | 4525 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4526 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4527 | struct amdgpu_ring *ring = adev->rings[i]; | |
4528 | ||
51687759 | 4529 | if (!ring || !ring->sched.thread) |
0875dc9e | 4530 | continue; |
5740682e | 4531 | |
c530b02f JZ |
4532 | /*clear job fence from fence drv to avoid force_completion |
4533 | *leave NULL and vm flush fence in fence drv */ | |
5c1e6fa4 | 4534 | amdgpu_fence_driver_clear_job_fences(ring); |
c530b02f | 4535 | |
2f9d4084 ML |
4536 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4537 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4538 | } |
d38ceaf9 | 4539 | |
ff99849b | 4540 | if (job && job->vm) |
222b5f04 AG |
4541 | drm_sched_increase_karma(&job->base); |
4542 | ||
04442bf7 | 4543 | r = amdgpu_reset_prepare_hwcontext(adev, reset_context); |
404b277b LL |
4544 | /* If reset handler not implemented, continue; otherwise return */ |
4545 | if (r == -ENOSYS) | |
4546 | r = 0; | |
4547 | else | |
04442bf7 LL |
4548 | return r; |
4549 | ||
1d721ed6 | 4550 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4551 | if (!amdgpu_sriov_vf(adev)) { |
4552 | ||
4553 | if (!need_full_reset) | |
4554 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4555 | ||
4556 | if (!need_full_reset) { | |
4557 | amdgpu_device_ip_pre_soft_reset(adev); | |
4558 | r = amdgpu_device_ip_soft_reset(adev); | |
4559 | amdgpu_device_ip_post_soft_reset(adev); | |
4560 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4561 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4562 | need_full_reset = true; |
4563 | } | |
4564 | } | |
4565 | ||
4566 | if (need_full_reset) | |
4567 | r = amdgpu_device_ip_suspend(adev); | |
04442bf7 LL |
4568 | if (need_full_reset) |
4569 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4570 | else | |
4571 | clear_bit(AMDGPU_NEED_FULL_RESET, | |
4572 | &reset_context->flags); | |
26bc5340 AG |
4573 | } |
4574 | ||
4575 | return r; | |
4576 | } | |
4577 | ||
04442bf7 LL |
4578 | int amdgpu_do_asic_reset(struct list_head *device_list_handle, |
4579 | struct amdgpu_reset_context *reset_context) | |
26bc5340 AG |
4580 | { |
4581 | struct amdgpu_device *tmp_adev = NULL; | |
04442bf7 | 4582 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
26bc5340 AG |
4583 | int r = 0; |
4584 | ||
04442bf7 LL |
4585 | /* Try reset handler method first */ |
4586 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
4587 | reset_list); | |
4588 | r = amdgpu_reset_perform_reset(tmp_adev, reset_context); | |
404b277b LL |
4589 | /* If reset handler not implemented, continue; otherwise return */ |
4590 | if (r == -ENOSYS) | |
4591 | r = 0; | |
4592 | else | |
04442bf7 LL |
4593 | return r; |
4594 | ||
4595 | /* Reset handler not implemented, use the default method */ | |
4596 | need_full_reset = | |
4597 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4598 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); | |
4599 | ||
26bc5340 | 4600 | /* |
655ce9cb | 4601 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
4602 | * to allow proper links negotiation in FW (within 1 sec) |
4603 | */ | |
7ac71382 | 4604 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 4605 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 4606 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4607 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 4608 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 4609 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4610 | r = -EALREADY; |
4611 | } else | |
4612 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4613 | |
041a62bc | 4614 | if (r) { |
aac89168 | 4615 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4616 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4617 | break; |
ce316fa5 LM |
4618 | } |
4619 | } | |
4620 | ||
041a62bc AG |
4621 | /* For XGMI wait for all resets to complete before proceed */ |
4622 | if (!r) { | |
655ce9cb | 4623 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
4624 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
4625 | flush_work(&tmp_adev->xgmi_reset_work); | |
4626 | r = tmp_adev->asic_reset_res; | |
4627 | if (r) | |
4628 | break; | |
ce316fa5 LM |
4629 | } |
4630 | } | |
4631 | } | |
ce316fa5 | 4632 | } |
26bc5340 | 4633 | |
43c4d576 | 4634 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 4635 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8bc7b360 HZ |
4636 | if (tmp_adev->mmhub.ras_funcs && |
4637 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count) | |
4638 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count(tmp_adev); | |
43c4d576 JC |
4639 | } |
4640 | ||
00eaa571 | 4641 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4642 | } |
00eaa571 | 4643 | |
655ce9cb | 4644 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
4645 | if (need_full_reset) { |
4646 | /* post card */ | |
e3c1b071 | 4647 | r = amdgpu_device_asic_init(tmp_adev); |
4648 | if (r) { | |
aac89168 | 4649 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 4650 | } else { |
26bc5340 | 4651 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
9cec53c1 JZ |
4652 | r = amdgpu_amdkfd_resume_iommu(tmp_adev); |
4653 | if (r) | |
4654 | goto out; | |
4655 | ||
26bc5340 AG |
4656 | r = amdgpu_device_ip_resume_phase1(tmp_adev); |
4657 | if (r) | |
4658 | goto out; | |
4659 | ||
4660 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
4661 | if (vram_lost) { | |
77e7f829 | 4662 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4663 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4664 | } |
4665 | ||
6c28aed6 | 4666 | r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT)); |
26bc5340 AG |
4667 | if (r) |
4668 | goto out; | |
4669 | ||
4670 | r = amdgpu_device_fw_loading(tmp_adev); | |
4671 | if (r) | |
4672 | return r; | |
4673 | ||
4674 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4675 | if (r) | |
4676 | goto out; | |
4677 | ||
4678 | if (vram_lost) | |
4679 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4680 | ||
fdafb359 EQ |
4681 | /* |
4682 | * Add this ASIC as tracked as reset was already | |
4683 | * complete successfully. | |
4684 | */ | |
4685 | amdgpu_register_gpu_instance(tmp_adev); | |
4686 | ||
04442bf7 LL |
4687 | if (!reset_context->hive && |
4688 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
e3c1b071 | 4689 | amdgpu_xgmi_add_device(tmp_adev); |
4690 | ||
7c04ca50 | 4691 | r = amdgpu_device_ip_late_init(tmp_adev); |
4692 | if (r) | |
4693 | goto out; | |
4694 | ||
087451f3 | 4695 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false); |
565d1941 | 4696 | |
e8fbaf03 GC |
4697 | /* |
4698 | * The GPU enters bad state once faulty pages | |
4699 | * by ECC has reached the threshold, and ras | |
4700 | * recovery is scheduled next. So add one check | |
4701 | * here to break recovery if it indeed exceeds | |
4702 | * bad page threshold, and remind user to | |
4703 | * retire this GPU or setting one bigger | |
4704 | * bad_page_threshold value to fix this once | |
4705 | * probing driver again. | |
4706 | */ | |
11003c68 | 4707 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
4708 | /* must succeed. */ |
4709 | amdgpu_ras_resume(tmp_adev); | |
4710 | } else { | |
4711 | r = -EINVAL; | |
4712 | goto out; | |
4713 | } | |
e79a04d5 | 4714 | |
26bc5340 | 4715 | /* Update PSP FW topology after reset */ |
04442bf7 LL |
4716 | if (reset_context->hive && |
4717 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4718 | r = amdgpu_xgmi_update_topology( | |
4719 | reset_context->hive, tmp_adev); | |
26bc5340 AG |
4720 | } |
4721 | } | |
4722 | ||
26bc5340 AG |
4723 | out: |
4724 | if (!r) { | |
4725 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4726 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4727 | if (r) { | |
4728 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
26bc5340 AG |
4729 | need_full_reset = true; |
4730 | r = -EAGAIN; | |
4731 | goto end; | |
4732 | } | |
4733 | } | |
4734 | ||
4735 | if (!r) | |
4736 | r = amdgpu_device_recover_vram(tmp_adev); | |
4737 | else | |
4738 | tmp_adev->asic_reset_res = r; | |
4739 | } | |
4740 | ||
4741 | end: | |
04442bf7 LL |
4742 | if (need_full_reset) |
4743 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4744 | else | |
4745 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 AG |
4746 | return r; |
4747 | } | |
4748 | ||
08ebb485 DL |
4749 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, |
4750 | struct amdgpu_hive_info *hive) | |
26bc5340 | 4751 | { |
53b3f8f4 DL |
4752 | if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0) |
4753 | return false; | |
4754 | ||
08ebb485 DL |
4755 | if (hive) { |
4756 | down_write_nest_lock(&adev->reset_sem, &hive->hive_lock); | |
4757 | } else { | |
4758 | down_write(&adev->reset_sem); | |
4759 | } | |
5740682e | 4760 | |
a3a09142 AD |
4761 | switch (amdgpu_asic_reset_method(adev)) { |
4762 | case AMD_RESET_METHOD_MODE1: | |
4763 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4764 | break; | |
4765 | case AMD_RESET_METHOD_MODE2: | |
4766 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4767 | break; | |
4768 | default: | |
4769 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4770 | break; | |
4771 | } | |
1d721ed6 AG |
4772 | |
4773 | return true; | |
26bc5340 | 4774 | } |
d38ceaf9 | 4775 | |
26bc5340 AG |
4776 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
4777 | { | |
89041940 | 4778 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4779 | adev->mp1_state = PP_MP1_STATE_NONE; |
53b3f8f4 | 4780 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 4781 | up_write(&adev->reset_sem); |
26bc5340 AG |
4782 | } |
4783 | ||
91fb309d HC |
4784 | /* |
4785 | * to lockup a list of amdgpu devices in a hive safely, if not a hive | |
4786 | * with multiple nodes, it will be similar as amdgpu_device_lock_adev. | |
4787 | * | |
4788 | * unlock won't require roll back. | |
4789 | */ | |
4790 | static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive) | |
4791 | { | |
4792 | struct amdgpu_device *tmp_adev = NULL; | |
4793 | ||
175ac6ec | 4794 | if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) { |
91fb309d HC |
4795 | if (!hive) { |
4796 | dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes"); | |
4797 | return -ENODEV; | |
4798 | } | |
4799 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4800 | if (!amdgpu_device_lock_adev(tmp_adev, hive)) | |
4801 | goto roll_back; | |
4802 | } | |
4803 | } else if (!amdgpu_device_lock_adev(adev, hive)) | |
4804 | return -EAGAIN; | |
4805 | ||
4806 | return 0; | |
4807 | roll_back: | |
4808 | if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) { | |
4809 | /* | |
4810 | * if the lockup iteration break in the middle of a hive, | |
4811 | * it may means there may has a race issue, | |
4812 | * or a hive device locked up independently. | |
4813 | * we may be in trouble and may not, so will try to roll back | |
4814 | * the lock and give out a warnning. | |
4815 | */ | |
4816 | dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock"); | |
4817 | list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4818 | amdgpu_device_unlock_adev(tmp_adev); | |
4819 | } | |
4820 | } | |
4821 | return -EAGAIN; | |
4822 | } | |
4823 | ||
3f12acc8 EQ |
4824 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4825 | { | |
4826 | struct pci_dev *p = NULL; | |
4827 | ||
4828 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4829 | adev->pdev->bus->number, 1); | |
4830 | if (p) { | |
4831 | pm_runtime_enable(&(p->dev)); | |
4832 | pm_runtime_resume(&(p->dev)); | |
4833 | } | |
4834 | } | |
4835 | ||
4836 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4837 | { | |
4838 | enum amd_reset_method reset_method; | |
4839 | struct pci_dev *p = NULL; | |
4840 | u64 expires; | |
4841 | ||
4842 | /* | |
4843 | * For now, only BACO and mode1 reset are confirmed | |
4844 | * to suffer the audio issue without proper suspended. | |
4845 | */ | |
4846 | reset_method = amdgpu_asic_reset_method(adev); | |
4847 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4848 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4849 | return -EINVAL; | |
4850 | ||
4851 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4852 | adev->pdev->bus->number, 1); | |
4853 | if (!p) | |
4854 | return -ENODEV; | |
4855 | ||
4856 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4857 | if (!expires) | |
4858 | /* | |
4859 | * If we cannot get the audio device autosuspend delay, | |
4860 | * a fixed 4S interval will be used. Considering 3S is | |
4861 | * the audio controller default autosuspend delay setting. | |
4862 | * 4S used here is guaranteed to cover that. | |
4863 | */ | |
54b7feb9 | 4864 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4865 | |
4866 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4867 | if (!pm_runtime_suspend(&(p->dev))) | |
4868 | break; | |
4869 | ||
4870 | if (expires < ktime_get_mono_fast_ns()) { | |
4871 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4872 | /* TODO: abort the succeeding gpu reset? */ | |
4873 | return -ETIMEDOUT; | |
4874 | } | |
4875 | } | |
4876 | ||
4877 | pm_runtime_disable(&(p->dev)); | |
4878 | ||
4879 | return 0; | |
4880 | } | |
4881 | ||
9d8d96be | 4882 | static void amdgpu_device_recheck_guilty_jobs( |
04442bf7 LL |
4883 | struct amdgpu_device *adev, struct list_head *device_list_handle, |
4884 | struct amdgpu_reset_context *reset_context) | |
e6c6338f JZ |
4885 | { |
4886 | int i, r = 0; | |
4887 | ||
4888 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4889 | struct amdgpu_ring *ring = adev->rings[i]; | |
4890 | int ret = 0; | |
4891 | struct drm_sched_job *s_job; | |
4892 | ||
4893 | if (!ring || !ring->sched.thread) | |
4894 | continue; | |
4895 | ||
4896 | s_job = list_first_entry_or_null(&ring->sched.pending_list, | |
4897 | struct drm_sched_job, list); | |
4898 | if (s_job == NULL) | |
4899 | continue; | |
4900 | ||
4901 | /* clear job's guilty and depend the folowing step to decide the real one */ | |
4902 | drm_sched_reset_karma(s_job); | |
38d4e463 JC |
4903 | /* for the real bad job, it will be resubmitted twice, adding a dma_fence_get |
4904 | * to make sure fence is balanced */ | |
4905 | dma_fence_get(s_job->s_fence->parent); | |
e6c6338f JZ |
4906 | drm_sched_resubmit_jobs_ext(&ring->sched, 1); |
4907 | ||
4908 | ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout); | |
4909 | if (ret == 0) { /* timeout */ | |
4910 | DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n", | |
4911 | ring->sched.name, s_job->id); | |
4912 | ||
4913 | /* set guilty */ | |
4914 | drm_sched_increase_karma(s_job); | |
4915 | retry: | |
4916 | /* do hw reset */ | |
4917 | if (amdgpu_sriov_vf(adev)) { | |
4918 | amdgpu_virt_fini_data_exchange(adev); | |
4919 | r = amdgpu_device_reset_sriov(adev, false); | |
4920 | if (r) | |
4921 | adev->asic_reset_res = r; | |
4922 | } else { | |
04442bf7 LL |
4923 | clear_bit(AMDGPU_SKIP_HW_RESET, |
4924 | &reset_context->flags); | |
4925 | r = amdgpu_do_asic_reset(device_list_handle, | |
4926 | reset_context); | |
e6c6338f JZ |
4927 | if (r && r == -EAGAIN) |
4928 | goto retry; | |
4929 | } | |
4930 | ||
4931 | /* | |
4932 | * add reset counter so that the following | |
4933 | * resubmitted job could flush vmid | |
4934 | */ | |
4935 | atomic_inc(&adev->gpu_reset_counter); | |
4936 | continue; | |
4937 | } | |
4938 | ||
4939 | /* got the hw fence, signal finished fence */ | |
4940 | atomic_dec(ring->sched.score); | |
38d4e463 | 4941 | dma_fence_put(s_job->s_fence->parent); |
e6c6338f JZ |
4942 | dma_fence_get(&s_job->s_fence->finished); |
4943 | dma_fence_signal(&s_job->s_fence->finished); | |
4944 | dma_fence_put(&s_job->s_fence->finished); | |
4945 | ||
4946 | /* remove node from list and free the job */ | |
4947 | spin_lock(&ring->sched.job_list_lock); | |
4948 | list_del_init(&s_job->list); | |
4949 | spin_unlock(&ring->sched.job_list_lock); | |
4950 | ring->sched.ops->free_job(s_job); | |
4951 | } | |
4952 | } | |
4953 | ||
26bc5340 AG |
4954 | /** |
4955 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
4956 | * | |
982a820b | 4957 | * @adev: amdgpu_device pointer |
26bc5340 AG |
4958 | * @job: which job trigger hang |
4959 | * | |
4960 | * Attempt to reset the GPU if it has hung (all asics). | |
4961 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
4962 | * Returns 0 for success or an error on failure. | |
4963 | */ | |
4964 | ||
4965 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
4966 | struct amdgpu_job *job) | |
4967 | { | |
1d721ed6 | 4968 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 | 4969 | bool job_signaled = false; |
26bc5340 | 4970 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 4971 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 4972 | int i, r = 0; |
bb5c7235 | 4973 | bool need_emergency_restart = false; |
3f12acc8 | 4974 | bool audio_suspended = false; |
e6c6338f | 4975 | int tmp_vram_lost_counter; |
04442bf7 LL |
4976 | struct amdgpu_reset_context reset_context; |
4977 | ||
4978 | memset(&reset_context, 0, sizeof(reset_context)); | |
26bc5340 | 4979 | |
6e3cd2a9 | 4980 | /* |
bb5c7235 WS |
4981 | * Special case: RAS triggered and full reset isn't supported |
4982 | */ | |
4983 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
4984 | ||
d5ea093e AG |
4985 | /* |
4986 | * Flush RAM to disk so that after reboot | |
4987 | * the user can read log and see why the system rebooted. | |
4988 | */ | |
bb5c7235 | 4989 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
4990 | DRM_WARN("Emergency reboot."); |
4991 | ||
4992 | ksys_sync_helper(); | |
4993 | emergency_restart(); | |
4994 | } | |
4995 | ||
b823821f | 4996 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 4997 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 AG |
4998 | |
4999 | /* | |
1d721ed6 AG |
5000 | * Here we trylock to avoid chain of resets executing from |
5001 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
5002 | * different schedulers for same device while this TO handler is running. | |
5003 | * We always reset all schedulers for device and all devices for XGMI | |
5004 | * hive so that should take care of them too. | |
26bc5340 | 5005 | */ |
175ac6ec ZL |
5006 | if (!amdgpu_sriov_vf(adev)) |
5007 | hive = amdgpu_get_xgmi_hive(adev); | |
53b3f8f4 DL |
5008 | if (hive) { |
5009 | if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) { | |
5010 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
5011 | job ? job->base.id : -1, hive->hive_id); | |
d95e8e97 | 5012 | amdgpu_put_xgmi_hive(hive); |
ff99849b | 5013 | if (job && job->vm) |
91fb309d | 5014 | drm_sched_increase_karma(&job->base); |
53b3f8f4 DL |
5015 | return 0; |
5016 | } | |
5017 | mutex_lock(&hive->hive_lock); | |
1d721ed6 | 5018 | } |
26bc5340 | 5019 | |
04442bf7 LL |
5020 | reset_context.method = AMD_RESET_METHOD_NONE; |
5021 | reset_context.reset_req_dev = adev; | |
5022 | reset_context.job = job; | |
5023 | reset_context.hive = hive; | |
5024 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5025 | ||
91fb309d HC |
5026 | /* |
5027 | * lock the device before we try to operate the linked list | |
5028 | * if didn't get the device lock, don't touch the linked list since | |
5029 | * others may iterating it. | |
5030 | */ | |
5031 | r = amdgpu_device_lock_hive_adev(adev, hive); | |
5032 | if (r) { | |
5033 | dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress", | |
5034 | job ? job->base.id : -1); | |
5035 | ||
5036 | /* even we skipped this reset, still need to set the job to guilty */ | |
ff99849b | 5037 | if (job && job->vm) |
91fb309d HC |
5038 | drm_sched_increase_karma(&job->base); |
5039 | goto skip_recovery; | |
5040 | } | |
5041 | ||
9e94d22c EQ |
5042 | /* |
5043 | * Build list of devices to reset. | |
5044 | * In case we are in XGMI hive mode, resort the device list | |
5045 | * to put adev in the 1st position. | |
5046 | */ | |
5047 | INIT_LIST_HEAD(&device_list); | |
175ac6ec | 5048 | if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) { |
655ce9cb | 5049 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) |
5050 | list_add_tail(&tmp_adev->reset_list, &device_list); | |
5051 | if (!list_is_first(&adev->reset_list, &device_list)) | |
5052 | list_rotate_to_front(&adev->reset_list, &device_list); | |
5053 | device_list_handle = &device_list; | |
26bc5340 | 5054 | } else { |
655ce9cb | 5055 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
5056 | device_list_handle = &device_list; |
5057 | } | |
5058 | ||
1d721ed6 | 5059 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 5060 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
3f12acc8 EQ |
5061 | /* |
5062 | * Try to put the audio codec into suspend state | |
5063 | * before gpu reset started. | |
5064 | * | |
5065 | * Due to the power domain of the graphics device | |
5066 | * is shared with AZ power domain. Without this, | |
5067 | * we may change the audio hardware from behind | |
5068 | * the audio driver's back. That will trigger | |
5069 | * some audio codec errors. | |
5070 | */ | |
5071 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
5072 | audio_suspended = true; | |
5073 | ||
9e94d22c EQ |
5074 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
5075 | ||
52fb44cf EQ |
5076 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
5077 | ||
992110d7 | 5078 | if (!amdgpu_sriov_vf(tmp_adev)) |
5079 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
9e94d22c | 5080 | |
12ffa55d AG |
5081 | /* |
5082 | * Mark these ASICs to be reseted as untracked first | |
5083 | * And add them back after reset completed | |
5084 | */ | |
5085 | amdgpu_unregister_gpu_instance(tmp_adev); | |
5086 | ||
087451f3 | 5087 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); |
565d1941 | 5088 | |
f1c1314b | 5089 | /* disable ras on ALL IPs */ |
bb5c7235 | 5090 | if (!need_emergency_restart && |
b823821f | 5091 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 5092 | amdgpu_ras_suspend(tmp_adev); |
5093 | ||
1d721ed6 AG |
5094 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5095 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5096 | ||
5097 | if (!ring || !ring->sched.thread) | |
5098 | continue; | |
5099 | ||
0b2d2c2e | 5100 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 5101 | |
bb5c7235 | 5102 | if (need_emergency_restart) |
7c6e68c7 | 5103 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 5104 | } |
8f8c80f4 | 5105 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
5106 | } |
5107 | ||
bb5c7235 | 5108 | if (need_emergency_restart) |
7c6e68c7 AG |
5109 | goto skip_sched_resume; |
5110 | ||
1d721ed6 AG |
5111 | /* |
5112 | * Must check guilty signal here since after this point all old | |
5113 | * HW fences are force signaled. | |
5114 | * | |
5115 | * job->base holds a reference to parent fence | |
5116 | */ | |
5117 | if (job && job->base.s_fence->parent && | |
7dd8c205 | 5118 | dma_fence_is_signaled(job->base.s_fence->parent)) { |
1d721ed6 | 5119 | job_signaled = true; |
1d721ed6 AG |
5120 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
5121 | goto skip_hw_reset; | |
5122 | } | |
5123 | ||
26bc5340 | 5124 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 5125 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
04442bf7 | 5126 | r = amdgpu_device_pre_asic_reset(tmp_adev, &reset_context); |
26bc5340 AG |
5127 | /*TODO Should we stop ?*/ |
5128 | if (r) { | |
aac89168 | 5129 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 5130 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
5131 | tmp_adev->asic_reset_res = r; |
5132 | } | |
5133 | } | |
5134 | ||
e6c6338f | 5135 | tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); |
26bc5340 | 5136 | /* Actual ASIC resets if needed.*/ |
4f30d920 | 5137 | /* Host driver will handle XGMI hive reset for SRIOV */ |
26bc5340 AG |
5138 | if (amdgpu_sriov_vf(adev)) { |
5139 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
5140 | if (r) | |
5141 | adev->asic_reset_res = r; | |
5142 | } else { | |
04442bf7 | 5143 | r = amdgpu_do_asic_reset(device_list_handle, &reset_context); |
26bc5340 AG |
5144 | if (r && r == -EAGAIN) |
5145 | goto retry; | |
5146 | } | |
5147 | ||
1d721ed6 AG |
5148 | skip_hw_reset: |
5149 | ||
26bc5340 | 5150 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 5151 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 5152 | |
e6c6338f JZ |
5153 | /* |
5154 | * Sometimes a later bad compute job can block a good gfx job as gfx | |
5155 | * and compute ring share internal GC HW mutually. We add an additional | |
5156 | * guilty jobs recheck step to find the real guilty job, it synchronously | |
5157 | * submits and pends for the first job being signaled. If it gets timeout, | |
5158 | * we identify it as a real guilty job. | |
5159 | */ | |
5160 | if (amdgpu_gpu_recovery == 2 && | |
5161 | !(tmp_vram_lost_counter < atomic_read(&adev->vram_lost_counter))) | |
04442bf7 LL |
5162 | amdgpu_device_recheck_guilty_jobs( |
5163 | tmp_adev, device_list_handle, &reset_context); | |
e6c6338f | 5164 | |
1d721ed6 AG |
5165 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5166 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5167 | ||
5168 | if (!ring || !ring->sched.thread) | |
5169 | continue; | |
5170 | ||
5171 | /* No point to resubmit jobs if we didn't HW reset*/ | |
5172 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
5173 | drm_sched_resubmit_jobs(&ring->sched); | |
5174 | ||
5175 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
5176 | } | |
5177 | ||
700de2c8 | 5178 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) { |
4a580877 | 5179 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
5180 | } |
5181 | ||
5182 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
5183 | |
5184 | if (r) { | |
5185 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 5186 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
5187 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
5188 | } else { | |
12ffa55d | 5189 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
3fa8f89d S |
5190 | if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0)) |
5191 | DRM_WARN("smart shift update failed\n"); | |
26bc5340 | 5192 | } |
7c6e68c7 | 5193 | } |
26bc5340 | 5194 | |
7c6e68c7 | 5195 | skip_sched_resume: |
655ce9cb | 5196 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
992110d7 | 5197 | /* unlock kfd: SRIOV would do it separately */ |
5198 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) | |
5199 | amdgpu_amdkfd_post_reset(tmp_adev); | |
8e2712e7 | 5200 | |
5201 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
5202 | * need to bring up kfd here if it's not be initialized before | |
5203 | */ | |
5204 | if (!adev->kfd.init_complete) | |
5205 | amdgpu_amdkfd_device_init(adev); | |
5206 | ||
3f12acc8 EQ |
5207 | if (audio_suspended) |
5208 | amdgpu_device_resume_display_audio(tmp_adev); | |
26bc5340 AG |
5209 | amdgpu_device_unlock_adev(tmp_adev); |
5210 | } | |
5211 | ||
cbfd17f7 | 5212 | skip_recovery: |
9e94d22c | 5213 | if (hive) { |
53b3f8f4 | 5214 | atomic_set(&hive->in_reset, 0); |
9e94d22c | 5215 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 5216 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 5217 | } |
26bc5340 | 5218 | |
91fb309d | 5219 | if (r && r != -EAGAIN) |
26bc5340 | 5220 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
d38ceaf9 AD |
5221 | return r; |
5222 | } | |
5223 | ||
e3ecdffa AD |
5224 | /** |
5225 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
5226 | * | |
5227 | * @adev: amdgpu_device pointer | |
5228 | * | |
5229 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
5230 | * and lanes) of the slot the device is in. Handles APUs and | |
5231 | * virtualized environments where PCIE config space may not be available. | |
5232 | */ | |
5494d864 | 5233 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 5234 | { |
5d9a6330 | 5235 | struct pci_dev *pdev; |
c5313457 HK |
5236 | enum pci_bus_speed speed_cap, platform_speed_cap; |
5237 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 5238 | |
cd474ba0 AD |
5239 | if (amdgpu_pcie_gen_cap) |
5240 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 5241 | |
cd474ba0 AD |
5242 | if (amdgpu_pcie_lane_cap) |
5243 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 5244 | |
cd474ba0 AD |
5245 | /* covers APUs as well */ |
5246 | if (pci_is_root_bus(adev->pdev->bus)) { | |
5247 | if (adev->pm.pcie_gen_mask == 0) | |
5248 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
5249 | if (adev->pm.pcie_mlw_mask == 0) | |
5250 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 5251 | return; |
cd474ba0 | 5252 | } |
d0dd7f0c | 5253 | |
c5313457 HK |
5254 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
5255 | return; | |
5256 | ||
dbaa922b AD |
5257 | pcie_bandwidth_available(adev->pdev, NULL, |
5258 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 5259 | |
cd474ba0 | 5260 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
5261 | /* asic caps */ |
5262 | pdev = adev->pdev; | |
5263 | speed_cap = pcie_get_speed_cap(pdev); | |
5264 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
5265 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
5266 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
5267 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 5268 | } else { |
2b3a1f51 FX |
5269 | if (speed_cap == PCIE_SPEED_32_0GT) |
5270 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5271 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5272 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5273 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5274 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5275 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5276 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5277 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5278 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5279 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
5280 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
5281 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5282 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5283 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
5284 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
5285 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5286 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5287 | else | |
5288 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5289 | } | |
5290 | /* platform caps */ | |
c5313457 | 5291 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
5292 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5293 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5294 | } else { | |
2b3a1f51 FX |
5295 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
5296 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5297 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5298 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5299 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5300 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5301 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5302 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5303 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5304 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5305 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 5306 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
5307 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5308 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5309 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 5310 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
5311 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5312 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5313 | else | |
5314 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5315 | ||
cd474ba0 AD |
5316 | } |
5317 | } | |
5318 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 5319 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
5320 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
5321 | } else { | |
c5313457 | 5322 | switch (platform_link_width) { |
5d9a6330 | 5323 | case PCIE_LNK_X32: |
cd474ba0 AD |
5324 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
5325 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
5326 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5327 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5328 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5329 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5330 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5331 | break; | |
5d9a6330 | 5332 | case PCIE_LNK_X16: |
cd474ba0 AD |
5333 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5334 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5335 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5336 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5337 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5338 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5339 | break; | |
5d9a6330 | 5340 | case PCIE_LNK_X12: |
cd474ba0 AD |
5341 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5342 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5343 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5344 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5345 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5346 | break; | |
5d9a6330 | 5347 | case PCIE_LNK_X8: |
cd474ba0 AD |
5348 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5349 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5350 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5351 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5352 | break; | |
5d9a6330 | 5353 | case PCIE_LNK_X4: |
cd474ba0 AD |
5354 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5355 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5356 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5357 | break; | |
5d9a6330 | 5358 | case PCIE_LNK_X2: |
cd474ba0 AD |
5359 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5360 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5361 | break; | |
5d9a6330 | 5362 | case PCIE_LNK_X1: |
cd474ba0 AD |
5363 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5364 | break; | |
5365 | default: | |
5366 | break; | |
5367 | } | |
d0dd7f0c AD |
5368 | } |
5369 | } | |
5370 | } | |
d38ceaf9 | 5371 | |
361dbd01 AD |
5372 | int amdgpu_device_baco_enter(struct drm_device *dev) |
5373 | { | |
1348969a | 5374 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5375 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 5376 | |
4a580877 | 5377 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5378 | return -ENOTSUPP; |
5379 | ||
8ab0d6f0 | 5380 | if (ras && adev->ras_enabled && |
acdae216 | 5381 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5382 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
5383 | ||
9530273e | 5384 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
5385 | } |
5386 | ||
5387 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
5388 | { | |
1348969a | 5389 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5390 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 5391 | int ret = 0; |
361dbd01 | 5392 | |
4a580877 | 5393 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5394 | return -ENOTSUPP; |
5395 | ||
9530273e EQ |
5396 | ret = amdgpu_dpm_baco_exit(adev); |
5397 | if (ret) | |
5398 | return ret; | |
7a22677b | 5399 | |
8ab0d6f0 | 5400 | if (ras && adev->ras_enabled && |
acdae216 | 5401 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5402 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
5403 | ||
1bece222 CL |
5404 | if (amdgpu_passthrough(adev) && |
5405 | adev->nbio.funcs->clear_doorbell_interrupt) | |
5406 | adev->nbio.funcs->clear_doorbell_interrupt(adev); | |
5407 | ||
7a22677b | 5408 | return 0; |
361dbd01 | 5409 | } |
c9a6b82f | 5410 | |
acd89fca AG |
5411 | static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev) |
5412 | { | |
5413 | int i; | |
5414 | ||
5415 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5416 | struct amdgpu_ring *ring = adev->rings[i]; | |
5417 | ||
5418 | if (!ring || !ring->sched.thread) | |
5419 | continue; | |
5420 | ||
5421 | cancel_delayed_work_sync(&ring->sched.work_tdr); | |
5422 | } | |
5423 | } | |
5424 | ||
c9a6b82f AG |
5425 | /** |
5426 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
5427 | * @pdev: PCI device struct | |
5428 | * @state: PCI channel state | |
5429 | * | |
5430 | * Description: Called when a PCI error is detected. | |
5431 | * | |
5432 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
5433 | */ | |
5434 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5435 | { | |
5436 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5437 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5438 | int i; |
c9a6b82f AG |
5439 | |
5440 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
5441 | ||
6894305c AG |
5442 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
5443 | DRM_WARN("No support for XGMI hive yet..."); | |
5444 | return PCI_ERS_RESULT_DISCONNECT; | |
5445 | } | |
5446 | ||
e17e27f9 GC |
5447 | adev->pci_channel_state = state; |
5448 | ||
c9a6b82f AG |
5449 | switch (state) { |
5450 | case pci_channel_io_normal: | |
5451 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 5452 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
5453 | case pci_channel_io_frozen: |
5454 | /* | |
acd89fca AG |
5455 | * Cancel and wait for all TDRs in progress if failing to |
5456 | * set adev->in_gpu_reset in amdgpu_device_lock_adev | |
5457 | * | |
5458 | * Locking adev->reset_sem will prevent any external access | |
5459 | * to GPU during PCI error recovery | |
5460 | */ | |
5461 | while (!amdgpu_device_lock_adev(adev, NULL)) | |
5462 | amdgpu_cancel_all_tdr(adev); | |
5463 | ||
5464 | /* | |
5465 | * Block any work scheduling as we do for regular GPU reset | |
5466 | * for the duration of the recovery | |
5467 | */ | |
5468 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5469 | struct amdgpu_ring *ring = adev->rings[i]; | |
5470 | ||
5471 | if (!ring || !ring->sched.thread) | |
5472 | continue; | |
5473 | ||
5474 | drm_sched_stop(&ring->sched, NULL); | |
5475 | } | |
8f8c80f4 | 5476 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
5477 | return PCI_ERS_RESULT_NEED_RESET; |
5478 | case pci_channel_io_perm_failure: | |
5479 | /* Permanent error, prepare for device removal */ | |
5480 | return PCI_ERS_RESULT_DISCONNECT; | |
5481 | } | |
5482 | ||
5483 | return PCI_ERS_RESULT_NEED_RESET; | |
5484 | } | |
5485 | ||
5486 | /** | |
5487 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
5488 | * @pdev: pointer to PCI device | |
5489 | */ | |
5490 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
5491 | { | |
5492 | ||
5493 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
5494 | ||
5495 | /* TODO - dump whatever for debugging purposes */ | |
5496 | ||
5497 | /* This called only if amdgpu_pci_error_detected returns | |
5498 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
5499 | * works, no need to reset slot. | |
5500 | */ | |
5501 | ||
5502 | return PCI_ERS_RESULT_RECOVERED; | |
5503 | } | |
5504 | ||
5505 | /** | |
5506 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
5507 | * @pdev: PCI device struct | |
5508 | * | |
5509 | * Description: This routine is called by the pci error recovery | |
5510 | * code after the PCI slot has been reset, just before we | |
5511 | * should resume normal operations. | |
5512 | */ | |
5513 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
5514 | { | |
5515 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5516 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 5517 | int r, i; |
04442bf7 | 5518 | struct amdgpu_reset_context reset_context; |
362c7b91 | 5519 | u32 memsize; |
7ac71382 | 5520 | struct list_head device_list; |
c9a6b82f AG |
5521 | |
5522 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
5523 | ||
04442bf7 LL |
5524 | memset(&reset_context, 0, sizeof(reset_context)); |
5525 | ||
7ac71382 | 5526 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 5527 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 5528 | |
362c7b91 AG |
5529 | /* wait for asic to come out of reset */ |
5530 | msleep(500); | |
5531 | ||
7ac71382 | 5532 | /* Restore PCI confspace */ |
c1dd4aa6 | 5533 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 5534 | |
362c7b91 AG |
5535 | /* confirm ASIC came out of reset */ |
5536 | for (i = 0; i < adev->usec_timeout; i++) { | |
5537 | memsize = amdgpu_asic_get_config_memsize(adev); | |
5538 | ||
5539 | if (memsize != 0xffffffff) | |
5540 | break; | |
5541 | udelay(1); | |
5542 | } | |
5543 | if (memsize == 0xffffffff) { | |
5544 | r = -ETIME; | |
5545 | goto out; | |
5546 | } | |
5547 | ||
04442bf7 LL |
5548 | reset_context.method = AMD_RESET_METHOD_NONE; |
5549 | reset_context.reset_req_dev = adev; | |
5550 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5551 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); | |
5552 | ||
7afefb81 | 5553 | adev->no_hw_access = true; |
04442bf7 | 5554 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
7afefb81 | 5555 | adev->no_hw_access = false; |
c9a6b82f AG |
5556 | if (r) |
5557 | goto out; | |
5558 | ||
04442bf7 | 5559 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
c9a6b82f AG |
5560 | |
5561 | out: | |
c9a6b82f | 5562 | if (!r) { |
c1dd4aa6 AG |
5563 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
5564 | pci_restore_state(adev->pdev); | |
5565 | ||
c9a6b82f AG |
5566 | DRM_INFO("PCIe error recovery succeeded\n"); |
5567 | } else { | |
5568 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
5569 | amdgpu_device_unlock_adev(adev); | |
5570 | } | |
5571 | ||
5572 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
5573 | } | |
5574 | ||
5575 | /** | |
5576 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
5577 | * @pdev: pointer to PCI device | |
5578 | * | |
5579 | * Called when the error recovery driver tells us that its | |
505199a3 | 5580 | * OK to resume normal operation. |
c9a6b82f AG |
5581 | */ |
5582 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
5583 | { | |
5584 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5585 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5586 | int i; |
c9a6b82f | 5587 | |
c9a6b82f AG |
5588 | |
5589 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca | 5590 | |
e17e27f9 GC |
5591 | /* Only continue execution for the case of pci_channel_io_frozen */ |
5592 | if (adev->pci_channel_state != pci_channel_io_frozen) | |
5593 | return; | |
5594 | ||
acd89fca AG |
5595 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5596 | struct amdgpu_ring *ring = adev->rings[i]; | |
5597 | ||
5598 | if (!ring || !ring->sched.thread) | |
5599 | continue; | |
5600 | ||
5601 | ||
5602 | drm_sched_resubmit_jobs(&ring->sched); | |
5603 | drm_sched_start(&ring->sched, true); | |
5604 | } | |
5605 | ||
5606 | amdgpu_device_unlock_adev(adev); | |
c9a6b82f | 5607 | } |
c1dd4aa6 AG |
5608 | |
5609 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
5610 | { | |
5611 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5612 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5613 | int r; | |
5614 | ||
5615 | r = pci_save_state(pdev); | |
5616 | if (!r) { | |
5617 | kfree(adev->pci_state); | |
5618 | ||
5619 | adev->pci_state = pci_store_saved_state(pdev); | |
5620 | ||
5621 | if (!adev->pci_state) { | |
5622 | DRM_ERROR("Failed to store PCI saved state"); | |
5623 | return false; | |
5624 | } | |
5625 | } else { | |
5626 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
5627 | return false; | |
5628 | } | |
5629 | ||
5630 | return true; | |
5631 | } | |
5632 | ||
5633 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
5634 | { | |
5635 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5636 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5637 | int r; | |
5638 | ||
5639 | if (!adev->pci_state) | |
5640 | return false; | |
5641 | ||
5642 | r = pci_load_saved_state(pdev, adev->pci_state); | |
5643 | ||
5644 | if (!r) { | |
5645 | pci_restore_state(pdev); | |
5646 | } else { | |
5647 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
5648 | return false; | |
5649 | } | |
5650 | ||
5651 | return true; | |
5652 | } | |
5653 | ||
810085dd EH |
5654 | void amdgpu_device_flush_hdp(struct amdgpu_device *adev, |
5655 | struct amdgpu_ring *ring) | |
5656 | { | |
5657 | #ifdef CONFIG_X86_64 | |
5658 | if (adev->flags & AMD_IS_APU) | |
5659 | return; | |
5660 | #endif | |
5661 | if (adev->gmc.xgmi.connected_to_cpu) | |
5662 | return; | |
5663 | ||
5664 | if (ring && ring->funcs->emit_hdp_flush) | |
5665 | amdgpu_ring_emit_hdp_flush(ring); | |
5666 | else | |
5667 | amdgpu_asic_flush_hdp(adev, ring); | |
5668 | } | |
c1dd4aa6 | 5669 | |
810085dd EH |
5670 | void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, |
5671 | struct amdgpu_ring *ring) | |
5672 | { | |
5673 | #ifdef CONFIG_X86_64 | |
5674 | if (adev->flags & AMD_IS_APU) | |
5675 | return; | |
5676 | #endif | |
5677 | if (adev->gmc.xgmi.connected_to_cpu) | |
5678 | return; | |
c1dd4aa6 | 5679 | |
810085dd EH |
5680 | amdgpu_asic_invalidate_hdp(adev, ring); |
5681 | } | |
34f3a4a9 LY |
5682 | |
5683 | /** | |
5684 | * amdgpu_device_halt() - bring hardware to some kind of halt state | |
5685 | * | |
5686 | * @adev: amdgpu_device pointer | |
5687 | * | |
5688 | * Bring hardware to some kind of halt state so that no one can touch it | |
5689 | * any more. It will help to maintain error context when error occurred. | |
5690 | * Compare to a simple hang, the system will keep stable at least for SSH | |
5691 | * access. Then it should be trivial to inspect the hardware state and | |
5692 | * see what's going on. Implemented as following: | |
5693 | * | |
5694 | * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc), | |
5695 | * clears all CPU mappings to device, disallows remappings through page faults | |
5696 | * 2. amdgpu_irq_disable_all() disables all interrupts | |
5697 | * 3. amdgpu_fence_driver_hw_fini() signals all HW fences | |
5698 | * 4. set adev->no_hw_access to avoid potential crashes after setp 5 | |
5699 | * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings | |
5700 | * 6. pci_disable_device() and pci_wait_for_pending_transaction() | |
5701 | * flush any in flight DMA operations | |
5702 | */ | |
5703 | void amdgpu_device_halt(struct amdgpu_device *adev) | |
5704 | { | |
5705 | struct pci_dev *pdev = adev->pdev; | |
e0f943b4 | 5706 | struct drm_device *ddev = adev_to_drm(adev); |
34f3a4a9 LY |
5707 | |
5708 | drm_dev_unplug(ddev); | |
5709 | ||
5710 | amdgpu_irq_disable_all(adev); | |
5711 | ||
5712 | amdgpu_fence_driver_hw_fini(adev); | |
5713 | ||
5714 | adev->no_hw_access = true; | |
5715 | ||
5716 | amdgpu_device_unmap_mmio(adev); | |
5717 | ||
5718 | pci_disable_device(pdev); | |
5719 | pci_wait_for_pending_transaction(pdev); | |
5720 | } |