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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
ba997709 | 58 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 59 | #include "amdgpu_pm.h" |
d38ceaf9 | 60 | |
e2a75f88 | 61 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
2d2e5e7e | 62 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 63 | |
2dc80b00 S |
64 | #define AMDGPU_RESUME_MS 2000 |
65 | ||
d38ceaf9 AD |
66 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); |
67 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
4f0955fc | 68 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev); |
db95e218 | 69 | static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev); |
d38ceaf9 AD |
70 | |
71 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
72 | "TAHITI", |
73 | "PITCAIRN", | |
74 | "VERDE", | |
75 | "OLAND", | |
76 | "HAINAN", | |
d38ceaf9 AD |
77 | "BONAIRE", |
78 | "KAVERI", | |
79 | "KABINI", | |
80 | "HAWAII", | |
81 | "MULLINS", | |
82 | "TOPAZ", | |
83 | "TONGA", | |
48299f95 | 84 | "FIJI", |
d38ceaf9 | 85 | "CARRIZO", |
139f4917 | 86 | "STONEY", |
2cc0c0b5 FC |
87 | "POLARIS10", |
88 | "POLARIS11", | |
c4642a47 | 89 | "POLARIS12", |
d4196f01 | 90 | "VEGA10", |
2ca8a5d2 | 91 | "RAVEN", |
d38ceaf9 AD |
92 | "LAST", |
93 | }; | |
94 | ||
95 | bool amdgpu_device_is_px(struct drm_device *dev) | |
96 | { | |
97 | struct amdgpu_device *adev = dev->dev_private; | |
98 | ||
2f7d10b3 | 99 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
100 | return true; |
101 | return false; | |
102 | } | |
103 | ||
104 | /* | |
105 | * MMIO register access helper functions. | |
106 | */ | |
107 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 108 | uint32_t acc_flags) |
d38ceaf9 | 109 | { |
f4b373f4 TSD |
110 | uint32_t ret; |
111 | ||
43ca8efa | 112 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 113 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 114 | |
15d72fd7 | 115 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 116 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
117 | else { |
118 | unsigned long flags; | |
d38ceaf9 AD |
119 | |
120 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
121 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
122 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
123 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 124 | } |
f4b373f4 TSD |
125 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
126 | return ret; | |
d38ceaf9 AD |
127 | } |
128 | ||
129 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 130 | uint32_t acc_flags) |
d38ceaf9 | 131 | { |
f4b373f4 | 132 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 133 | |
47ed4e1c KW |
134 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
135 | adev->last_mm_index = v; | |
136 | } | |
137 | ||
43ca8efa | 138 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 139 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 140 | |
15d72fd7 | 141 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
142 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
143 | else { | |
144 | unsigned long flags; | |
145 | ||
146 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
147 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
148 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
149 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
150 | } | |
47ed4e1c KW |
151 | |
152 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
153 | udelay(500); | |
154 | } | |
d38ceaf9 AD |
155 | } |
156 | ||
157 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
158 | { | |
159 | if ((reg * 4) < adev->rio_mem_size) | |
160 | return ioread32(adev->rio_mem + (reg * 4)); | |
161 | else { | |
162 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
163 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
164 | } | |
165 | } | |
166 | ||
167 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
168 | { | |
47ed4e1c KW |
169 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
170 | adev->last_mm_index = v; | |
171 | } | |
d38ceaf9 AD |
172 | |
173 | if ((reg * 4) < adev->rio_mem_size) | |
174 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
175 | else { | |
176 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
177 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
178 | } | |
47ed4e1c KW |
179 | |
180 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
181 | udelay(500); | |
182 | } | |
d38ceaf9 AD |
183 | } |
184 | ||
185 | /** | |
186 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
187 | * | |
188 | * @adev: amdgpu_device pointer | |
189 | * @index: doorbell index | |
190 | * | |
191 | * Returns the value in the doorbell aperture at the | |
192 | * requested doorbell index (CIK). | |
193 | */ | |
194 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
195 | { | |
196 | if (index < adev->doorbell.num_doorbells) { | |
197 | return readl(adev->doorbell.ptr + index); | |
198 | } else { | |
199 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
200 | return 0; | |
201 | } | |
202 | } | |
203 | ||
204 | /** | |
205 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
206 | * | |
207 | * @adev: amdgpu_device pointer | |
208 | * @index: doorbell index | |
209 | * @v: value to write | |
210 | * | |
211 | * Writes @v to the doorbell aperture at the | |
212 | * requested doorbell index (CIK). | |
213 | */ | |
214 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
215 | { | |
216 | if (index < adev->doorbell.num_doorbells) { | |
217 | writel(v, adev->doorbell.ptr + index); | |
218 | } else { | |
219 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
220 | } | |
221 | } | |
222 | ||
832be404 KW |
223 | /** |
224 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
225 | * | |
226 | * @adev: amdgpu_device pointer | |
227 | * @index: doorbell index | |
228 | * | |
229 | * Returns the value in the doorbell aperture at the | |
230 | * requested doorbell index (VEGA10+). | |
231 | */ | |
232 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
233 | { | |
234 | if (index < adev->doorbell.num_doorbells) { | |
235 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
236 | } else { | |
237 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
238 | return 0; | |
239 | } | |
240 | } | |
241 | ||
242 | /** | |
243 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
244 | * | |
245 | * @adev: amdgpu_device pointer | |
246 | * @index: doorbell index | |
247 | * @v: value to write | |
248 | * | |
249 | * Writes @v to the doorbell aperture at the | |
250 | * requested doorbell index (VEGA10+). | |
251 | */ | |
252 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
253 | { | |
254 | if (index < adev->doorbell.num_doorbells) { | |
255 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
256 | } else { | |
257 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
258 | } | |
259 | } | |
260 | ||
d38ceaf9 AD |
261 | /** |
262 | * amdgpu_invalid_rreg - dummy reg read function | |
263 | * | |
264 | * @adev: amdgpu device pointer | |
265 | * @reg: offset of register | |
266 | * | |
267 | * Dummy register read function. Used for register blocks | |
268 | * that certain asics don't have (all asics). | |
269 | * Returns the value in the register. | |
270 | */ | |
271 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
272 | { | |
273 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
274 | BUG(); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /** | |
279 | * amdgpu_invalid_wreg - dummy reg write function | |
280 | * | |
281 | * @adev: amdgpu device pointer | |
282 | * @reg: offset of register | |
283 | * @v: value to write to the register | |
284 | * | |
285 | * Dummy register read function. Used for register blocks | |
286 | * that certain asics don't have (all asics). | |
287 | */ | |
288 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
289 | { | |
290 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
291 | reg, v); | |
292 | BUG(); | |
293 | } | |
294 | ||
295 | /** | |
296 | * amdgpu_block_invalid_rreg - dummy reg read function | |
297 | * | |
298 | * @adev: amdgpu device pointer | |
299 | * @block: offset of instance | |
300 | * @reg: offset of register | |
301 | * | |
302 | * Dummy register read function. Used for register blocks | |
303 | * that certain asics don't have (all asics). | |
304 | * Returns the value in the register. | |
305 | */ | |
306 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
307 | uint32_t block, uint32_t reg) | |
308 | { | |
309 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
310 | reg, block); | |
311 | BUG(); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | /** | |
316 | * amdgpu_block_invalid_wreg - dummy reg write function | |
317 | * | |
318 | * @adev: amdgpu device pointer | |
319 | * @block: offset of instance | |
320 | * @reg: offset of register | |
321 | * @v: value to write to the register | |
322 | * | |
323 | * Dummy register read function. Used for register blocks | |
324 | * that certain asics don't have (all asics). | |
325 | */ | |
326 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
327 | uint32_t block, | |
328 | uint32_t reg, uint32_t v) | |
329 | { | |
330 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
331 | reg, block, v); | |
332 | BUG(); | |
333 | } | |
334 | ||
335 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
336 | { | |
a4a02777 CK |
337 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
338 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
339 | &adev->vram_scratch.robj, | |
340 | &adev->vram_scratch.gpu_addr, | |
341 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
342 | } |
343 | ||
344 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
345 | { | |
078af1a3 | 346 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
347 | } |
348 | ||
349 | /** | |
350 | * amdgpu_program_register_sequence - program an array of registers. | |
351 | * | |
352 | * @adev: amdgpu_device pointer | |
353 | * @registers: pointer to the register array | |
354 | * @array_size: size of the register array | |
355 | * | |
356 | * Programs an array or registers with and and or masks. | |
357 | * This is a helper for setting golden registers. | |
358 | */ | |
359 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
360 | const u32 *registers, | |
361 | const u32 array_size) | |
362 | { | |
363 | u32 tmp, reg, and_mask, or_mask; | |
364 | int i; | |
365 | ||
366 | if (array_size % 3) | |
367 | return; | |
368 | ||
369 | for (i = 0; i < array_size; i +=3) { | |
370 | reg = registers[i + 0]; | |
371 | and_mask = registers[i + 1]; | |
372 | or_mask = registers[i + 2]; | |
373 | ||
374 | if (and_mask == 0xffffffff) { | |
375 | tmp = or_mask; | |
376 | } else { | |
377 | tmp = RREG32(reg); | |
378 | tmp &= ~and_mask; | |
379 | tmp |= or_mask; | |
380 | } | |
381 | WREG32(reg, tmp); | |
382 | } | |
383 | } | |
384 | ||
385 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
386 | { | |
387 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
388 | } | |
389 | ||
390 | /* | |
391 | * GPU doorbell aperture helpers function. | |
392 | */ | |
393 | /** | |
394 | * amdgpu_doorbell_init - Init doorbell driver information. | |
395 | * | |
396 | * @adev: amdgpu_device pointer | |
397 | * | |
398 | * Init doorbell driver information (CIK) | |
399 | * Returns 0 on success, error on failure. | |
400 | */ | |
401 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
402 | { | |
705e519e CK |
403 | /* No doorbell on SI hardware generation */ |
404 | if (adev->asic_type < CHIP_BONAIRE) { | |
405 | adev->doorbell.base = 0; | |
406 | adev->doorbell.size = 0; | |
407 | adev->doorbell.num_doorbells = 0; | |
408 | adev->doorbell.ptr = NULL; | |
409 | return 0; | |
410 | } | |
411 | ||
d38ceaf9 AD |
412 | /* doorbell bar mapping */ |
413 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
414 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
415 | ||
edf600da | 416 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
417 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
418 | if (adev->doorbell.num_doorbells == 0) | |
419 | return -EINVAL; | |
420 | ||
8972e5d2 CK |
421 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
422 | adev->doorbell.num_doorbells * | |
423 | sizeof(u32)); | |
424 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 425 | return -ENOMEM; |
d38ceaf9 AD |
426 | |
427 | return 0; | |
428 | } | |
429 | ||
430 | /** | |
431 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
432 | * | |
433 | * @adev: amdgpu_device pointer | |
434 | * | |
435 | * Tear down doorbell driver information (CIK) | |
436 | */ | |
437 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
438 | { | |
439 | iounmap(adev->doorbell.ptr); | |
440 | adev->doorbell.ptr = NULL; | |
441 | } | |
442 | ||
443 | /** | |
444 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
445 | * setup amdkfd | |
446 | * | |
447 | * @adev: amdgpu_device pointer | |
448 | * @aperture_base: output returning doorbell aperture base physical address | |
449 | * @aperture_size: output returning doorbell aperture size in bytes | |
450 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
451 | * | |
452 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
453 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
454 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
455 | */ | |
456 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
457 | phys_addr_t *aperture_base, | |
458 | size_t *aperture_size, | |
459 | size_t *start_offset) | |
460 | { | |
461 | /* | |
462 | * The first num_doorbells are used by amdgpu. | |
463 | * amdkfd takes whatever's left in the aperture. | |
464 | */ | |
465 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
466 | *aperture_base = adev->doorbell.base; | |
467 | *aperture_size = adev->doorbell.size; | |
468 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
469 | } else { | |
470 | *aperture_base = 0; | |
471 | *aperture_size = 0; | |
472 | *start_offset = 0; | |
473 | } | |
474 | } | |
475 | ||
476 | /* | |
477 | * amdgpu_wb_*() | |
455a7bc2 | 478 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 479 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
480 | */ |
481 | ||
482 | /** | |
483 | * amdgpu_wb_fini - Disable Writeback and free memory | |
484 | * | |
485 | * @adev: amdgpu_device pointer | |
486 | * | |
487 | * Disables Writeback and frees the Writeback memory (all asics). | |
488 | * Used at driver shutdown. | |
489 | */ | |
490 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
491 | { | |
492 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
493 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
494 | &adev->wb.gpu_addr, | |
495 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
496 | adev->wb.wb_obj = NULL; |
497 | } | |
498 | } | |
499 | ||
500 | /** | |
501 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
502 | * | |
503 | * @adev: amdgpu_device pointer | |
504 | * | |
455a7bc2 | 505 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
506 | * Used at driver startup. |
507 | * Returns 0 on success or an -error on failure. | |
508 | */ | |
509 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
510 | { | |
511 | int r; | |
512 | ||
513 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
514 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
515 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
516 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
517 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
518 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
519 | if (r) { |
520 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
521 | return r; | |
522 | } | |
d38ceaf9 AD |
523 | |
524 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
525 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
526 | ||
527 | /* clear wb memory */ | |
60a970a6 | 528 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t)); |
d38ceaf9 AD |
529 | } |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
534 | /** | |
535 | * amdgpu_wb_get - Allocate a wb entry | |
536 | * | |
537 | * @adev: amdgpu_device pointer | |
538 | * @wb: wb index | |
539 | * | |
540 | * Allocate a wb slot for use by the driver (all asics). | |
541 | * Returns 0 on success or -EINVAL on failure. | |
542 | */ | |
543 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
544 | { | |
545 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 546 | |
97407b63 | 547 | if (offset < adev->wb.num_wb) { |
7014285a | 548 | __set_bit(offset, adev->wb.used); |
63ae07ca | 549 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
550 | return 0; |
551 | } else { | |
552 | return -EINVAL; | |
553 | } | |
554 | } | |
555 | ||
d38ceaf9 AD |
556 | /** |
557 | * amdgpu_wb_free - Free a wb entry | |
558 | * | |
559 | * @adev: amdgpu_device pointer | |
560 | * @wb: wb index | |
561 | * | |
562 | * Free a wb slot allocated for use by the driver (all asics) | |
563 | */ | |
564 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
565 | { | |
566 | if (wb < adev->wb.num_wb) | |
63ae07ca | 567 | __clear_bit(wb >> 3, adev->wb.used); |
d38ceaf9 AD |
568 | } |
569 | ||
570 | /** | |
571 | * amdgpu_vram_location - try to find VRAM location | |
572 | * @adev: amdgpu device structure holding all necessary informations | |
573 | * @mc: memory controller structure holding memory informations | |
574 | * @base: base address at which to put VRAM | |
575 | * | |
455a7bc2 | 576 | * Function will try to place VRAM at base address provided |
d38ceaf9 AD |
577 | * as parameter (which is so far either PCI aperture address or |
578 | * for IGP TOM base address). | |
579 | * | |
580 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
581 | * address space then we limit the VRAM size to the aperture. | |
582 | * | |
583 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
584 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
585 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
586 | * not IGP. | |
587 | * | |
588 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
589 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
590 | * Novell bug 204882 + along with lots of ubuntu ones | |
591 | * | |
592 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
593 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
594 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
595 | * ones) | |
596 | * | |
597 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
455a7bc2 | 598 | * explicitly check for that though. |
d38ceaf9 AD |
599 | * |
600 | * FIXME: when reducing VRAM size align new size on power of 2. | |
601 | */ | |
602 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
603 | { | |
604 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
605 | ||
606 | mc->vram_start = base; | |
607 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
608 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
609 | mc->real_vram_size = mc->aper_size; | |
610 | mc->mc_vram_size = mc->aper_size; | |
611 | } | |
612 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
613 | if (limit && limit < mc->real_vram_size) | |
614 | mc->real_vram_size = limit; | |
615 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
616 | mc->mc_vram_size >> 20, mc->vram_start, | |
617 | mc->vram_end, mc->real_vram_size >> 20); | |
618 | } | |
619 | ||
620 | /** | |
6f02a696 | 621 | * amdgpu_gart_location - try to find GTT location |
d38ceaf9 AD |
622 | * @adev: amdgpu device structure holding all necessary informations |
623 | * @mc: memory controller structure holding memory informations | |
624 | * | |
625 | * Function will place try to place GTT before or after VRAM. | |
626 | * | |
627 | * If GTT size is bigger than space left then we ajust GTT size. | |
628 | * Thus function will never fails. | |
629 | * | |
630 | * FIXME: when reducing GTT size align new size on power of 2. | |
631 | */ | |
6f02a696 | 632 | void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) |
d38ceaf9 AD |
633 | { |
634 | u64 size_af, size_bf; | |
635 | ||
ed21c047 CK |
636 | size_af = adev->mc.mc_mask - mc->vram_end; |
637 | size_bf = mc->vram_start; | |
d38ceaf9 | 638 | if (size_bf > size_af) { |
6f02a696 | 639 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 640 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 641 | mc->gart_size = size_bf; |
d38ceaf9 | 642 | } |
6f02a696 | 643 | mc->gart_start = 0; |
d38ceaf9 | 644 | } else { |
6f02a696 | 645 | if (mc->gart_size > size_af) { |
d38ceaf9 | 646 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 647 | mc->gart_size = size_af; |
d38ceaf9 | 648 | } |
6f02a696 | 649 | mc->gart_start = mc->vram_end + 1; |
d38ceaf9 | 650 | } |
6f02a696 | 651 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 652 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 653 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
654 | } |
655 | ||
a05502e5 HC |
656 | /* |
657 | * Firmware Reservation functions | |
658 | */ | |
659 | /** | |
660 | * amdgpu_fw_reserve_vram_fini - free fw reserved vram | |
661 | * | |
662 | * @adev: amdgpu_device pointer | |
663 | * | |
664 | * free fw reserved vram if it has been reserved. | |
665 | */ | |
666 | void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev) | |
667 | { | |
668 | amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, | |
669 | NULL, &adev->fw_vram_usage.va); | |
670 | } | |
671 | ||
672 | /** | |
673 | * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw | |
674 | * | |
675 | * @adev: amdgpu_device pointer | |
676 | * | |
677 | * create bo vram reservation from fw. | |
678 | */ | |
679 | int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) | |
680 | { | |
681 | int r = 0; | |
682 | u64 gpu_addr; | |
683 | u64 vram_size = adev->mc.visible_vram_size; | |
684 | ||
685 | adev->fw_vram_usage.va = NULL; | |
686 | adev->fw_vram_usage.reserved_bo = NULL; | |
687 | ||
688 | if (adev->fw_vram_usage.size > 0 && | |
689 | adev->fw_vram_usage.size <= vram_size) { | |
690 | ||
691 | r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, | |
692 | PAGE_SIZE, true, 0, | |
693 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | | |
694 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0, | |
695 | &adev->fw_vram_usage.reserved_bo); | |
696 | if (r) | |
697 | goto error_create; | |
698 | ||
699 | r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false); | |
700 | if (r) | |
701 | goto error_reserve; | |
702 | r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo, | |
703 | AMDGPU_GEM_DOMAIN_VRAM, | |
704 | adev->fw_vram_usage.start_offset, | |
705 | (adev->fw_vram_usage.start_offset + | |
706 | adev->fw_vram_usage.size), &gpu_addr); | |
707 | if (r) | |
708 | goto error_pin; | |
709 | r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, | |
710 | &adev->fw_vram_usage.va); | |
711 | if (r) | |
712 | goto error_kmap; | |
713 | ||
714 | amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); | |
715 | } | |
716 | return r; | |
717 | ||
718 | error_kmap: | |
719 | amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo); | |
720 | error_pin: | |
721 | amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); | |
722 | error_reserve: | |
723 | amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo); | |
724 | error_create: | |
725 | adev->fw_vram_usage.va = NULL; | |
726 | adev->fw_vram_usage.reserved_bo = NULL; | |
727 | return r; | |
728 | } | |
729 | ||
730 | ||
d38ceaf9 AD |
731 | /* |
732 | * GPU helpers function. | |
733 | */ | |
734 | /** | |
c836fec5 | 735 | * amdgpu_need_post - check if the hw need post or not |
d38ceaf9 AD |
736 | * |
737 | * @adev: amdgpu_device pointer | |
738 | * | |
c836fec5 JQ |
739 | * Check if the asic has been initialized (all asics) at driver startup |
740 | * or post is needed if hw reset is performed. | |
741 | * Returns true if need or false if not. | |
d38ceaf9 | 742 | */ |
c836fec5 | 743 | bool amdgpu_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
744 | { |
745 | uint32_t reg; | |
746 | ||
bec86378 ML |
747 | if (amdgpu_sriov_vf(adev)) |
748 | return false; | |
749 | ||
750 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
751 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
752 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
753 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
754 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
755 | */ |
756 | if (adev->asic_type == CHIP_FIJI) { | |
757 | int err; | |
758 | uint32_t fw_ver; | |
759 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
760 | /* force vPost if error occured */ | |
761 | if (err) | |
762 | return true; | |
763 | ||
764 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
765 | if (fw_ver < 0x00160e00) |
766 | return true; | |
bec86378 | 767 | } |
bec86378 | 768 | } |
91fe77eb | 769 | |
770 | if (adev->has_hw_reset) { | |
771 | adev->has_hw_reset = false; | |
772 | return true; | |
773 | } | |
774 | ||
775 | /* bios scratch used on CIK+ */ | |
776 | if (adev->asic_type >= CHIP_BONAIRE) | |
777 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
778 | ||
779 | /* check MEM_SIZE for older asics */ | |
780 | reg = amdgpu_asic_get_config_memsize(adev); | |
781 | ||
782 | if ((reg != 0) && (reg != 0xffffffff)) | |
783 | return false; | |
784 | ||
785 | return true; | |
bec86378 ML |
786 | } |
787 | ||
d38ceaf9 AD |
788 | /** |
789 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
790 | * | |
791 | * @adev: amdgpu_device pointer | |
792 | * | |
793 | * Allocate the dummy page used by the driver (all asics). | |
794 | * This dummy page is used by the driver as a filler for gart entries | |
795 | * when pages are taken out of the GART | |
796 | * Returns 0 on sucess, -ENOMEM on failure. | |
797 | */ | |
798 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
799 | { | |
800 | if (adev->dummy_page.page) | |
801 | return 0; | |
802 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
803 | if (adev->dummy_page.page == NULL) | |
804 | return -ENOMEM; | |
805 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
806 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
807 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
808 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
809 | __free_page(adev->dummy_page.page); | |
810 | adev->dummy_page.page = NULL; | |
811 | return -ENOMEM; | |
812 | } | |
813 | return 0; | |
814 | } | |
815 | ||
816 | /** | |
817 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
818 | * | |
819 | * @adev: amdgpu_device pointer | |
820 | * | |
821 | * Frees the dummy page used by the driver (all asics). | |
822 | */ | |
823 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
824 | { | |
825 | if (adev->dummy_page.page == NULL) | |
826 | return; | |
827 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
828 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
829 | __free_page(adev->dummy_page.page); | |
830 | adev->dummy_page.page = NULL; | |
831 | } | |
832 | ||
833 | ||
834 | /* ATOM accessor methods */ | |
835 | /* | |
836 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
837 | * driver registers callbacks to access registers and the interpreter | |
838 | * in the driver parses the tables and executes then to program specific | |
839 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
840 | * atombios.h, and atom.c | |
841 | */ | |
842 | ||
843 | /** | |
844 | * cail_pll_read - read PLL register | |
845 | * | |
846 | * @info: atom card_info pointer | |
847 | * @reg: PLL register offset | |
848 | * | |
849 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
850 | * Returns the value of the PLL register. | |
851 | */ | |
852 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
853 | { | |
854 | return 0; | |
855 | } | |
856 | ||
857 | /** | |
858 | * cail_pll_write - write PLL register | |
859 | * | |
860 | * @info: atom card_info pointer | |
861 | * @reg: PLL register offset | |
862 | * @val: value to write to the pll register | |
863 | * | |
864 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
865 | */ | |
866 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
867 | { | |
868 | ||
869 | } | |
870 | ||
871 | /** | |
872 | * cail_mc_read - read MC (Memory Controller) register | |
873 | * | |
874 | * @info: atom card_info pointer | |
875 | * @reg: MC register offset | |
876 | * | |
877 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
878 | * Returns the value of the MC register. | |
879 | */ | |
880 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
881 | { | |
882 | return 0; | |
883 | } | |
884 | ||
885 | /** | |
886 | * cail_mc_write - write MC (Memory Controller) register | |
887 | * | |
888 | * @info: atom card_info pointer | |
889 | * @reg: MC register offset | |
890 | * @val: value to write to the pll register | |
891 | * | |
892 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
893 | */ | |
894 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
895 | { | |
896 | ||
897 | } | |
898 | ||
899 | /** | |
900 | * cail_reg_write - write MMIO register | |
901 | * | |
902 | * @info: atom card_info pointer | |
903 | * @reg: MMIO register offset | |
904 | * @val: value to write to the pll register | |
905 | * | |
906 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
907 | */ | |
908 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
909 | { | |
910 | struct amdgpu_device *adev = info->dev->dev_private; | |
911 | ||
912 | WREG32(reg, val); | |
913 | } | |
914 | ||
915 | /** | |
916 | * cail_reg_read - read MMIO register | |
917 | * | |
918 | * @info: atom card_info pointer | |
919 | * @reg: MMIO register offset | |
920 | * | |
921 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
922 | * Returns the value of the MMIO register. | |
923 | */ | |
924 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
925 | { | |
926 | struct amdgpu_device *adev = info->dev->dev_private; | |
927 | uint32_t r; | |
928 | ||
929 | r = RREG32(reg); | |
930 | return r; | |
931 | } | |
932 | ||
933 | /** | |
934 | * cail_ioreg_write - write IO register | |
935 | * | |
936 | * @info: atom card_info pointer | |
937 | * @reg: IO register offset | |
938 | * @val: value to write to the pll register | |
939 | * | |
940 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
941 | */ | |
942 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
943 | { | |
944 | struct amdgpu_device *adev = info->dev->dev_private; | |
945 | ||
946 | WREG32_IO(reg, val); | |
947 | } | |
948 | ||
949 | /** | |
950 | * cail_ioreg_read - read IO register | |
951 | * | |
952 | * @info: atom card_info pointer | |
953 | * @reg: IO register offset | |
954 | * | |
955 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
956 | * Returns the value of the IO register. | |
957 | */ | |
958 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
959 | { | |
960 | struct amdgpu_device *adev = info->dev->dev_private; | |
961 | uint32_t r; | |
962 | ||
963 | r = RREG32_IO(reg); | |
964 | return r; | |
965 | } | |
966 | ||
5b41d94c KR |
967 | static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, |
968 | struct device_attribute *attr, | |
969 | char *buf) | |
970 | { | |
971 | struct drm_device *ddev = dev_get_drvdata(dev); | |
972 | struct amdgpu_device *adev = ddev->dev_private; | |
973 | struct atom_context *ctx = adev->mode_info.atom_context; | |
974 | ||
975 | return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version); | |
976 | } | |
977 | ||
978 | static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, | |
979 | NULL); | |
980 | ||
d38ceaf9 AD |
981 | /** |
982 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
983 | * | |
984 | * @adev: amdgpu_device pointer | |
985 | * | |
986 | * Frees the driver info and register access callbacks for the ATOM | |
987 | * interpreter (r4xx+). | |
988 | * Called at driver shutdown. | |
989 | */ | |
990 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
991 | { | |
89e0ec9f | 992 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 993 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
994 | kfree(adev->mode_info.atom_context->iio); |
995 | } | |
d38ceaf9 AD |
996 | kfree(adev->mode_info.atom_context); |
997 | adev->mode_info.atom_context = NULL; | |
998 | kfree(adev->mode_info.atom_card_info); | |
999 | adev->mode_info.atom_card_info = NULL; | |
5b41d94c | 1000 | device_remove_file(adev->dev, &dev_attr_vbios_version); |
d38ceaf9 AD |
1001 | } |
1002 | ||
1003 | /** | |
1004 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
1005 | * | |
1006 | * @adev: amdgpu_device pointer | |
1007 | * | |
1008 | * Initializes the driver info and register access callbacks for the | |
1009 | * ATOM interpreter (r4xx+). | |
1010 | * Returns 0 on sucess, -ENOMEM on failure. | |
1011 | * Called at driver startup. | |
1012 | */ | |
1013 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
1014 | { | |
1015 | struct card_info *atom_card_info = | |
1016 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
5b41d94c | 1017 | int ret; |
d38ceaf9 AD |
1018 | |
1019 | if (!atom_card_info) | |
1020 | return -ENOMEM; | |
1021 | ||
1022 | adev->mode_info.atom_card_info = atom_card_info; | |
1023 | atom_card_info->dev = adev->ddev; | |
1024 | atom_card_info->reg_read = cail_reg_read; | |
1025 | atom_card_info->reg_write = cail_reg_write; | |
1026 | /* needed for iio ops */ | |
1027 | if (adev->rio_mem) { | |
1028 | atom_card_info->ioreg_read = cail_ioreg_read; | |
1029 | atom_card_info->ioreg_write = cail_ioreg_write; | |
1030 | } else { | |
b64a18c5 | 1031 | DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); |
d38ceaf9 AD |
1032 | atom_card_info->ioreg_read = cail_reg_read; |
1033 | atom_card_info->ioreg_write = cail_reg_write; | |
1034 | } | |
1035 | atom_card_info->mc_read = cail_mc_read; | |
1036 | atom_card_info->mc_write = cail_mc_write; | |
1037 | atom_card_info->pll_read = cail_pll_read; | |
1038 | atom_card_info->pll_write = cail_pll_write; | |
1039 | ||
1040 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
1041 | if (!adev->mode_info.atom_context) { | |
1042 | amdgpu_atombios_fini(adev); | |
1043 | return -ENOMEM; | |
1044 | } | |
1045 | ||
1046 | mutex_init(&adev->mode_info.atom_context->mutex); | |
a5bde2f9 AD |
1047 | if (adev->is_atom_fw) { |
1048 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
1049 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
1050 | } else { | |
1051 | amdgpu_atombios_scratch_regs_init(adev); | |
1052 | amdgpu_atombios_allocate_fb_scratch(adev); | |
1053 | } | |
5b41d94c KR |
1054 | |
1055 | ret = device_create_file(adev->dev, &dev_attr_vbios_version); | |
1056 | if (ret) { | |
1057 | DRM_ERROR("Failed to create device file for VBIOS version\n"); | |
1058 | return ret; | |
1059 | } | |
1060 | ||
d38ceaf9 AD |
1061 | return 0; |
1062 | } | |
1063 | ||
1064 | /* if we get transitioned to only one device, take VGA back */ | |
1065 | /** | |
1066 | * amdgpu_vga_set_decode - enable/disable vga decode | |
1067 | * | |
1068 | * @cookie: amdgpu_device pointer | |
1069 | * @state: enable/disable vga decode | |
1070 | * | |
1071 | * Enable/disable vga decode (all asics). | |
1072 | * Returns VGA resource flags. | |
1073 | */ | |
1074 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
1075 | { | |
1076 | struct amdgpu_device *adev = cookie; | |
1077 | amdgpu_asic_set_vga_state(adev, state); | |
1078 | if (state) | |
1079 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1080 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1081 | else | |
1082 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1083 | } | |
1084 | ||
bab4fee7 | 1085 | static void amdgpu_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1086 | { |
1087 | /* defines number of bits in page table versus page directory, | |
1088 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1089 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1090 | if (amdgpu_vm_block_size == -1) |
1091 | return; | |
a1adf8be | 1092 | |
bab4fee7 | 1093 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1094 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1095 | amdgpu_vm_block_size); | |
bab4fee7 | 1096 | goto def_value; |
a1adf8be CZ |
1097 | } |
1098 | ||
1099 | if (amdgpu_vm_block_size > 24 || | |
1100 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1101 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1102 | amdgpu_vm_block_size); | |
bab4fee7 | 1103 | goto def_value; |
a1adf8be | 1104 | } |
bab4fee7 JZ |
1105 | |
1106 | return; | |
1107 | ||
1108 | def_value: | |
1109 | amdgpu_vm_block_size = -1; | |
a1adf8be CZ |
1110 | } |
1111 | ||
83ca145d ZJ |
1112 | static void amdgpu_check_vm_size(struct amdgpu_device *adev) |
1113 | { | |
64dab074 AD |
1114 | /* no need to check the default value */ |
1115 | if (amdgpu_vm_size == -1) | |
1116 | return; | |
1117 | ||
76117507 | 1118 | if (!is_power_of_2(amdgpu_vm_size)) { |
83ca145d ZJ |
1119 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", |
1120 | amdgpu_vm_size); | |
1121 | goto def_value; | |
1122 | } | |
1123 | ||
1124 | if (amdgpu_vm_size < 1) { | |
1125 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1126 | amdgpu_vm_size); | |
1127 | goto def_value; | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * Max GPUVM size for Cayman, SI, CI VI are 40 bits. | |
1132 | */ | |
1133 | if (amdgpu_vm_size > 1024) { | |
1134 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1135 | amdgpu_vm_size); | |
1136 | goto def_value; | |
1137 | } | |
1138 | ||
1139 | return; | |
1140 | ||
1141 | def_value: | |
bab4fee7 | 1142 | amdgpu_vm_size = -1; |
83ca145d ZJ |
1143 | } |
1144 | ||
d38ceaf9 AD |
1145 | /** |
1146 | * amdgpu_check_arguments - validate module params | |
1147 | * | |
1148 | * @adev: amdgpu_device pointer | |
1149 | * | |
1150 | * Validates certain module parameters and updates | |
1151 | * the associated values used by the driver (all asics). | |
1152 | */ | |
1153 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
1154 | { | |
5b011235 CZ |
1155 | if (amdgpu_sched_jobs < 4) { |
1156 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1157 | amdgpu_sched_jobs); | |
1158 | amdgpu_sched_jobs = 4; | |
76117507 | 1159 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1160 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1161 | amdgpu_sched_jobs); | |
1162 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1163 | } | |
d38ceaf9 | 1164 | |
83e74db6 | 1165 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1166 | /* gart size must be greater or equal to 32M */ |
1167 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1168 | amdgpu_gart_size); | |
83e74db6 | 1169 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1170 | } |
1171 | ||
36d38372 | 1172 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1173 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1174 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1175 | amdgpu_gtt_size); | |
1176 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1177 | } |
1178 | ||
d07f14be RH |
1179 | /* valid range is between 4 and 9 inclusive */ |
1180 | if (amdgpu_vm_fragment_size != -1 && | |
1181 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1182 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1183 | amdgpu_vm_fragment_size = -1; | |
1184 | } | |
1185 | ||
83ca145d | 1186 | amdgpu_check_vm_size(adev); |
d38ceaf9 | 1187 | |
bab4fee7 | 1188 | amdgpu_check_block_size(adev); |
6a7f76e7 | 1189 | |
526bae37 | 1190 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1191 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1192 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1193 | amdgpu_vram_page_split); | |
1194 | amdgpu_vram_page_split = 1024; | |
1195 | } | |
d38ceaf9 AD |
1196 | } |
1197 | ||
1198 | /** | |
1199 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1200 | * | |
1201 | * @pdev: pci dev pointer | |
1694467b | 1202 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1203 | * |
1204 | * Callback for the switcheroo driver. Suspends or resumes the | |
1205 | * the asics before or after it is powered up using ACPI methods. | |
1206 | */ | |
1207 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1208 | { | |
1209 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1210 | ||
1211 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1212 | return; | |
1213 | ||
1214 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1215 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1216 | /* don't suspend or resume card normally */ |
1217 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1218 | ||
810ddc3a | 1219 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1220 | |
d38ceaf9 AD |
1221 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1222 | drm_kms_helper_poll_enable(dev); | |
1223 | } else { | |
7ca85295 | 1224 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1225 | drm_kms_helper_poll_disable(dev); |
1226 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1227 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1228 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1229 | } | |
1230 | } | |
1231 | ||
1232 | /** | |
1233 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1234 | * | |
1235 | * @pdev: pci dev pointer | |
1236 | * | |
1237 | * Callback for the switcheroo driver. Check of the switcheroo | |
1238 | * state can be changed. | |
1239 | * Returns true if the state can be changed, false if not. | |
1240 | */ | |
1241 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1242 | { | |
1243 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1244 | ||
1245 | /* | |
1246 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1247 | * locking inversion with the driver load path. And the access here is | |
1248 | * completely racy anyway. So don't bother with locking for now. | |
1249 | */ | |
1250 | return dev->open_count == 0; | |
1251 | } | |
1252 | ||
1253 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1254 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1255 | .reprobe = NULL, | |
1256 | .can_switch = amdgpu_switcheroo_can_switch, | |
1257 | }; | |
1258 | ||
1259 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1260 | enum amd_ip_block_type block_type, |
1261 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1262 | { |
1263 | int i, r = 0; | |
1264 | ||
1265 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1266 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1267 | continue; |
c722865a RZ |
1268 | if (adev->ip_blocks[i].version->type != block_type) |
1269 | continue; | |
1270 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1271 | continue; | |
1272 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1273 | (void *)adev, state); | |
1274 | if (r) | |
1275 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1276 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1277 | } |
1278 | return r; | |
1279 | } | |
1280 | ||
1281 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1282 | enum amd_ip_block_type block_type, |
1283 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1284 | { |
1285 | int i, r = 0; | |
1286 | ||
1287 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1288 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1289 | continue; |
c722865a RZ |
1290 | if (adev->ip_blocks[i].version->type != block_type) |
1291 | continue; | |
1292 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1293 | continue; | |
1294 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1295 | (void *)adev, state); | |
1296 | if (r) | |
1297 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1298 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1299 | } |
1300 | return r; | |
1301 | } | |
1302 | ||
6cb2d4e4 HR |
1303 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) |
1304 | { | |
1305 | int i; | |
1306 | ||
1307 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1308 | if (!adev->ip_blocks[i].status.valid) | |
1309 | continue; | |
1310 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1311 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1312 | } | |
1313 | } | |
1314 | ||
5dbbb60b AD |
1315 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1316 | enum amd_ip_block_type block_type) | |
1317 | { | |
1318 | int i, r; | |
1319 | ||
1320 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1321 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1322 | continue; |
a1255107 AD |
1323 | if (adev->ip_blocks[i].version->type == block_type) { |
1324 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1325 | if (r) |
1326 | return r; | |
1327 | break; | |
1328 | } | |
1329 | } | |
1330 | return 0; | |
1331 | ||
1332 | } | |
1333 | ||
1334 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1335 | enum amd_ip_block_type block_type) | |
1336 | { | |
1337 | int i; | |
1338 | ||
1339 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1340 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1341 | continue; |
a1255107 AD |
1342 | if (adev->ip_blocks[i].version->type == block_type) |
1343 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1344 | } |
1345 | return true; | |
1346 | ||
1347 | } | |
1348 | ||
a1255107 AD |
1349 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1350 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1351 | { |
1352 | int i; | |
1353 | ||
1354 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1355 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1356 | return &adev->ip_blocks[i]; |
1357 | ||
1358 | return NULL; | |
1359 | } | |
1360 | ||
1361 | /** | |
1362 | * amdgpu_ip_block_version_cmp | |
1363 | * | |
1364 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1365 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1366 | * @major: major version |
1367 | * @minor: minor version | |
1368 | * | |
1369 | * return 0 if equal or greater | |
1370 | * return 1 if smaller or the ip_block doesn't exist | |
1371 | */ | |
1372 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1373 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1374 | u32 major, u32 minor) |
1375 | { | |
a1255107 | 1376 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1377 | |
a1255107 AD |
1378 | if (ip_block && ((ip_block->version->major > major) || |
1379 | ((ip_block->version->major == major) && | |
1380 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1381 | return 0; |
1382 | ||
1383 | return 1; | |
1384 | } | |
1385 | ||
a1255107 AD |
1386 | /** |
1387 | * amdgpu_ip_block_add | |
1388 | * | |
1389 | * @adev: amdgpu_device pointer | |
1390 | * @ip_block_version: pointer to the IP to add | |
1391 | * | |
1392 | * Adds the IP block driver information to the collection of IPs | |
1393 | * on the asic. | |
1394 | */ | |
1395 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1396 | const struct amdgpu_ip_block_version *ip_block_version) | |
1397 | { | |
1398 | if (!ip_block_version) | |
1399 | return -EINVAL; | |
1400 | ||
a0bae357 HR |
1401 | DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks, |
1402 | ip_block_version->funcs->name); | |
1403 | ||
a1255107 AD |
1404 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
483ef985 | 1409 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1410 | { |
1411 | adev->enable_virtual_display = false; | |
1412 | ||
1413 | if (amdgpu_virtual_display) { | |
1414 | struct drm_device *ddev = adev->ddev; | |
1415 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1416 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1417 | |
1418 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1419 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1420 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1421 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1422 | if (!strcmp("all", pciaddname) |
1423 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1424 | long num_crtc; |
1425 | int res = -1; | |
1426 | ||
9accf2fd | 1427 | adev->enable_virtual_display = true; |
0f66356d ED |
1428 | |
1429 | if (pciaddname_tmp) | |
1430 | res = kstrtol(pciaddname_tmp, 10, | |
1431 | &num_crtc); | |
1432 | ||
1433 | if (!res) { | |
1434 | if (num_crtc < 1) | |
1435 | num_crtc = 1; | |
1436 | if (num_crtc > 6) | |
1437 | num_crtc = 6; | |
1438 | adev->mode_info.num_crtc = num_crtc; | |
1439 | } else { | |
1440 | adev->mode_info.num_crtc = 1; | |
1441 | } | |
9accf2fd ED |
1442 | break; |
1443 | } | |
1444 | } | |
1445 | ||
0f66356d ED |
1446 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1447 | amdgpu_virtual_display, pci_address_name, | |
1448 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1449 | |
1450 | kfree(pciaddstr); | |
1451 | } | |
1452 | } | |
1453 | ||
e2a75f88 AD |
1454 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1455 | { | |
e2a75f88 AD |
1456 | const char *chip_name; |
1457 | char fw_name[30]; | |
1458 | int err; | |
1459 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1460 | ||
ab4fe3e1 HR |
1461 | adev->firmware.gpu_info_fw = NULL; |
1462 | ||
e2a75f88 AD |
1463 | switch (adev->asic_type) { |
1464 | case CHIP_TOPAZ: | |
1465 | case CHIP_TONGA: | |
1466 | case CHIP_FIJI: | |
1467 | case CHIP_POLARIS11: | |
1468 | case CHIP_POLARIS10: | |
1469 | case CHIP_POLARIS12: | |
1470 | case CHIP_CARRIZO: | |
1471 | case CHIP_STONEY: | |
1472 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1473 | case CHIP_VERDE: | |
1474 | case CHIP_TAHITI: | |
1475 | case CHIP_PITCAIRN: | |
1476 | case CHIP_OLAND: | |
1477 | case CHIP_HAINAN: | |
1478 | #endif | |
1479 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1480 | case CHIP_BONAIRE: | |
1481 | case CHIP_HAWAII: | |
1482 | case CHIP_KAVERI: | |
1483 | case CHIP_KABINI: | |
1484 | case CHIP_MULLINS: | |
1485 | #endif | |
1486 | default: | |
1487 | return 0; | |
1488 | case CHIP_VEGA10: | |
1489 | chip_name = "vega10"; | |
1490 | break; | |
2d2e5e7e AD |
1491 | case CHIP_RAVEN: |
1492 | chip_name = "raven"; | |
1493 | break; | |
e2a75f88 AD |
1494 | } |
1495 | ||
1496 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1497 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1498 | if (err) { |
1499 | dev_err(adev->dev, | |
1500 | "Failed to load gpu_info firmware \"%s\"\n", | |
1501 | fw_name); | |
1502 | goto out; | |
1503 | } | |
ab4fe3e1 | 1504 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1505 | if (err) { |
1506 | dev_err(adev->dev, | |
1507 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1508 | fw_name); | |
1509 | goto out; | |
1510 | } | |
1511 | ||
ab4fe3e1 | 1512 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1513 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1514 | ||
1515 | switch (hdr->version_major) { | |
1516 | case 1: | |
1517 | { | |
1518 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1519 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1520 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1521 | ||
b5ab16bf AD |
1522 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1523 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1524 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1525 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1526 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1527 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1528 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1529 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1530 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1531 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1532 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1533 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1534 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1535 | adev->gfx.cu_info.max_waves_per_simd = |
1536 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1537 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1538 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1539 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1540 | break; |
1541 | } | |
1542 | default: | |
1543 | dev_err(adev->dev, | |
1544 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1545 | err = -EINVAL; | |
1546 | goto out; | |
1547 | } | |
1548 | out: | |
e2a75f88 AD |
1549 | return err; |
1550 | } | |
1551 | ||
d38ceaf9 AD |
1552 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1553 | { | |
aaa36a97 | 1554 | int i, r; |
d38ceaf9 | 1555 | |
483ef985 | 1556 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1557 | |
d38ceaf9 | 1558 | switch (adev->asic_type) { |
aaa36a97 AD |
1559 | case CHIP_TOPAZ: |
1560 | case CHIP_TONGA: | |
48299f95 | 1561 | case CHIP_FIJI: |
2cc0c0b5 FC |
1562 | case CHIP_POLARIS11: |
1563 | case CHIP_POLARIS10: | |
c4642a47 | 1564 | case CHIP_POLARIS12: |
aaa36a97 | 1565 | case CHIP_CARRIZO: |
39bb0c92 SL |
1566 | case CHIP_STONEY: |
1567 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1568 | adev->family = AMDGPU_FAMILY_CZ; |
1569 | else | |
1570 | adev->family = AMDGPU_FAMILY_VI; | |
1571 | ||
1572 | r = vi_set_ip_blocks(adev); | |
1573 | if (r) | |
1574 | return r; | |
1575 | break; | |
33f34802 KW |
1576 | #ifdef CONFIG_DRM_AMDGPU_SI |
1577 | case CHIP_VERDE: | |
1578 | case CHIP_TAHITI: | |
1579 | case CHIP_PITCAIRN: | |
1580 | case CHIP_OLAND: | |
1581 | case CHIP_HAINAN: | |
295d0daf | 1582 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1583 | r = si_set_ip_blocks(adev); |
1584 | if (r) | |
1585 | return r; | |
1586 | break; | |
1587 | #endif | |
a2e73f56 AD |
1588 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1589 | case CHIP_BONAIRE: | |
1590 | case CHIP_HAWAII: | |
1591 | case CHIP_KAVERI: | |
1592 | case CHIP_KABINI: | |
1593 | case CHIP_MULLINS: | |
1594 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1595 | adev->family = AMDGPU_FAMILY_CI; | |
1596 | else | |
1597 | adev->family = AMDGPU_FAMILY_KV; | |
1598 | ||
1599 | r = cik_set_ip_blocks(adev); | |
1600 | if (r) | |
1601 | return r; | |
1602 | break; | |
1603 | #endif | |
2ca8a5d2 CZ |
1604 | case CHIP_VEGA10: |
1605 | case CHIP_RAVEN: | |
1606 | if (adev->asic_type == CHIP_RAVEN) | |
1607 | adev->family = AMDGPU_FAMILY_RV; | |
1608 | else | |
1609 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1610 | |
1611 | r = soc15_set_ip_blocks(adev); | |
1612 | if (r) | |
1613 | return r; | |
1614 | break; | |
d38ceaf9 AD |
1615 | default: |
1616 | /* FIXME: not supported yet */ | |
1617 | return -EINVAL; | |
1618 | } | |
1619 | ||
e2a75f88 AD |
1620 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1621 | if (r) | |
1622 | return r; | |
1623 | ||
3149d9da XY |
1624 | if (amdgpu_sriov_vf(adev)) { |
1625 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1626 | if (r) | |
1627 | return r; | |
1628 | } | |
1629 | ||
d38ceaf9 AD |
1630 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1631 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1632 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1633 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1634 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1635 | } else { |
a1255107 AD |
1636 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1637 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1638 | if (r == -ENOENT) { |
a1255107 | 1639 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1640 | } else if (r) { |
a1255107 AD |
1641 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1642 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1643 | return r; |
2c1a2784 | 1644 | } else { |
a1255107 | 1645 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1646 | } |
974e6b64 | 1647 | } else { |
a1255107 | 1648 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1649 | } |
d38ceaf9 AD |
1650 | } |
1651 | } | |
1652 | ||
395d1fb9 NH |
1653 | adev->cg_flags &= amdgpu_cg_mask; |
1654 | adev->pg_flags &= amdgpu_pg_mask; | |
1655 | ||
d38ceaf9 AD |
1656 | return 0; |
1657 | } | |
1658 | ||
1659 | static int amdgpu_init(struct amdgpu_device *adev) | |
1660 | { | |
1661 | int i, r; | |
1662 | ||
1663 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1664 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1665 | continue; |
a1255107 | 1666 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1667 | if (r) { |
a1255107 AD |
1668 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1669 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1670 | return r; |
2c1a2784 | 1671 | } |
a1255107 | 1672 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1673 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1674 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1675 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1676 | if (r) { |
1677 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1678 | return r; |
2c1a2784 | 1679 | } |
a1255107 | 1680 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1681 | if (r) { |
1682 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1683 | return r; |
2c1a2784 | 1684 | } |
d38ceaf9 | 1685 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1686 | if (r) { |
1687 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1688 | return r; |
2c1a2784 | 1689 | } |
a1255107 | 1690 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1691 | |
1692 | /* right after GMC hw init, we create CSA */ | |
1693 | if (amdgpu_sriov_vf(adev)) { | |
1694 | r = amdgpu_allocate_static_csa(adev); | |
1695 | if (r) { | |
1696 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1697 | return r; | |
1698 | } | |
1699 | } | |
d38ceaf9 AD |
1700 | } |
1701 | } | |
1702 | ||
1703 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1704 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1705 | continue; |
1706 | /* gmc hw init is done early */ | |
a1255107 | 1707 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1708 | continue; |
a1255107 | 1709 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1710 | if (r) { |
a1255107 AD |
1711 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1712 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1713 | return r; |
2c1a2784 | 1714 | } |
a1255107 | 1715 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1716 | } |
1717 | ||
1718 | return 0; | |
1719 | } | |
1720 | ||
0c49e0b8 CZ |
1721 | static void amdgpu_fill_reset_magic(struct amdgpu_device *adev) |
1722 | { | |
1723 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1724 | } | |
1725 | ||
1726 | static bool amdgpu_check_vram_lost(struct amdgpu_device *adev) | |
1727 | { | |
1728 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1729 | AMDGPU_RESET_MAGIC_NUM); | |
1730 | } | |
1731 | ||
2dc80b00 | 1732 | static int amdgpu_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1733 | { |
1734 | int i = 0, r; | |
1735 | ||
1736 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1737 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1738 | continue; |
4a446d55 | 1739 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1740 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1741 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1742 | /* enable clockgating to save power */ |
a1255107 AD |
1743 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1744 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1745 | if (r) { |
1746 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1747 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1748 | return r; |
1749 | } | |
b0b00ff1 | 1750 | } |
d38ceaf9 | 1751 | } |
2dc80b00 S |
1752 | return 0; |
1753 | } | |
1754 | ||
1755 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1756 | { | |
1757 | int i = 0, r; | |
1758 | ||
1759 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1760 | if (!adev->ip_blocks[i].status.valid) | |
1761 | continue; | |
1762 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1763 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1764 | if (r) { | |
1765 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1766 | adev->ip_blocks[i].version->funcs->name, r); | |
1767 | return r; | |
1768 | } | |
1769 | adev->ip_blocks[i].status.late_initialized = true; | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | mod_delayed_work(system_wq, &adev->late_init_work, | |
1774 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1775 | |
0c49e0b8 | 1776 | amdgpu_fill_reset_magic(adev); |
d38ceaf9 AD |
1777 | |
1778 | return 0; | |
1779 | } | |
1780 | ||
1781 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1782 | { | |
1783 | int i, r; | |
1784 | ||
3e96dbfd AD |
1785 | /* need to disable SMC first */ |
1786 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1787 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1788 | continue; |
a1255107 | 1789 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1790 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1791 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1792 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1793 | if (r) { |
1794 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1795 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1796 | return r; |
1797 | } | |
a1255107 | 1798 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1799 | /* XXX handle errors */ |
1800 | if (r) { | |
1801 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1802 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1803 | } |
a1255107 | 1804 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1805 | break; |
1806 | } | |
1807 | } | |
1808 | ||
d38ceaf9 | 1809 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1810 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1811 | continue; |
a1255107 | 1812 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1813 | amdgpu_wb_fini(adev); |
1814 | amdgpu_vram_scratch_fini(adev); | |
1815 | } | |
8201a67a RZ |
1816 | |
1817 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1818 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
1819 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1820 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1821 | AMD_CG_STATE_UNGATE); | |
1822 | if (r) { | |
1823 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1824 | adev->ip_blocks[i].version->funcs->name, r); | |
1825 | return r; | |
1826 | } | |
2c1a2784 | 1827 | } |
8201a67a | 1828 | |
a1255107 | 1829 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1830 | /* XXX handle errors */ |
2c1a2784 | 1831 | if (r) { |
a1255107 AD |
1832 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1833 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1834 | } |
8201a67a | 1835 | |
a1255107 | 1836 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1837 | } |
1838 | ||
446947b4 WH |
1839 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) |
1840 | amdgpu_ucode_fini_bo(adev); | |
1841 | ||
d38ceaf9 | 1842 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1843 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1844 | continue; |
a1255107 | 1845 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1846 | /* XXX handle errors */ |
2c1a2784 | 1847 | if (r) { |
a1255107 AD |
1848 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1849 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1850 | } |
a1255107 AD |
1851 | adev->ip_blocks[i].status.sw = false; |
1852 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1853 | } |
1854 | ||
a6dcfd9c | 1855 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1856 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1857 | continue; |
a1255107 AD |
1858 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1859 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1860 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1861 | } |
1862 | ||
030308fc | 1863 | if (amdgpu_sriov_vf(adev)) |
3149d9da | 1864 | amdgpu_virt_release_full_gpu(adev, false); |
2493664f | 1865 | |
d38ceaf9 AD |
1866 | return 0; |
1867 | } | |
1868 | ||
2dc80b00 S |
1869 | static void amdgpu_late_init_func_handler(struct work_struct *work) |
1870 | { | |
1871 | struct amdgpu_device *adev = | |
1872 | container_of(work, struct amdgpu_device, late_init_work.work); | |
1873 | amdgpu_late_set_cg_state(adev); | |
1874 | } | |
1875 | ||
faefba95 | 1876 | int amdgpu_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1877 | { |
1878 | int i, r; | |
1879 | ||
e941ea99 XY |
1880 | if (amdgpu_sriov_vf(adev)) |
1881 | amdgpu_virt_request_full_gpu(adev, false); | |
1882 | ||
c5a93a28 FC |
1883 | /* ungate SMC block first */ |
1884 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1885 | AMD_CG_STATE_UNGATE); | |
1886 | if (r) { | |
1887 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1888 | } | |
1889 | ||
d38ceaf9 | 1890 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1891 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1892 | continue; |
1893 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1894 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1895 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1896 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1897 | if (r) { |
a1255107 AD |
1898 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1899 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1900 | } |
2c1a2784 | 1901 | } |
d38ceaf9 | 1902 | /* XXX handle errors */ |
a1255107 | 1903 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1904 | /* XXX handle errors */ |
2c1a2784 | 1905 | if (r) { |
a1255107 AD |
1906 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1907 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1908 | } |
d38ceaf9 AD |
1909 | } |
1910 | ||
e941ea99 XY |
1911 | if (amdgpu_sriov_vf(adev)) |
1912 | amdgpu_virt_release_full_gpu(adev, false); | |
1913 | ||
d38ceaf9 AD |
1914 | return 0; |
1915 | } | |
1916 | ||
e4f0fdcc | 1917 | static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) |
a90ad3c2 ML |
1918 | { |
1919 | int i, r; | |
1920 | ||
2cb681b6 ML |
1921 | static enum amd_ip_block_type ip_order[] = { |
1922 | AMD_IP_BLOCK_TYPE_GMC, | |
1923 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1924 | AMD_IP_BLOCK_TYPE_IH, |
1925 | }; | |
a90ad3c2 | 1926 | |
2cb681b6 ML |
1927 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1928 | int j; | |
1929 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1930 | |
2cb681b6 ML |
1931 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1932 | block = &adev->ip_blocks[j]; | |
1933 | ||
1934 | if (block->version->type != ip_order[i] || | |
1935 | !block->status.valid) | |
1936 | continue; | |
1937 | ||
1938 | r = block->version->funcs->hw_init(adev); | |
1939 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1940 | } |
1941 | } | |
1942 | ||
1943 | return 0; | |
1944 | } | |
1945 | ||
e4f0fdcc | 1946 | static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) |
a90ad3c2 ML |
1947 | { |
1948 | int i, r; | |
1949 | ||
2cb681b6 ML |
1950 | static enum amd_ip_block_type ip_order[] = { |
1951 | AMD_IP_BLOCK_TYPE_SMC, | |
ef4c166d | 1952 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
1953 | AMD_IP_BLOCK_TYPE_DCE, |
1954 | AMD_IP_BLOCK_TYPE_GFX, | |
1955 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
1956 | AMD_IP_BLOCK_TYPE_UVD, |
1957 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 1958 | }; |
a90ad3c2 | 1959 | |
2cb681b6 ML |
1960 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1961 | int j; | |
1962 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1963 | |
2cb681b6 ML |
1964 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1965 | block = &adev->ip_blocks[j]; | |
1966 | ||
1967 | if (block->version->type != ip_order[i] || | |
1968 | !block->status.valid) | |
1969 | continue; | |
1970 | ||
1971 | r = block->version->funcs->hw_init(adev); | |
1972 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
a90ad3c2 ML |
1973 | } |
1974 | } | |
1975 | ||
1976 | return 0; | |
1977 | } | |
1978 | ||
fcf0649f | 1979 | static int amdgpu_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1980 | { |
1981 | int i, r; | |
1982 | ||
a90ad3c2 ML |
1983 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1984 | if (!adev->ip_blocks[i].status.valid) | |
1985 | continue; | |
a90ad3c2 ML |
1986 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
1987 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
fcf0649f CZ |
1988 | adev->ip_blocks[i].version->type == |
1989 | AMD_IP_BLOCK_TYPE_IH) { | |
1990 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1991 | if (r) { | |
1992 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1993 | adev->ip_blocks[i].version->funcs->name, r); | |
1994 | return r; | |
1995 | } | |
a90ad3c2 ML |
1996 | } |
1997 | } | |
1998 | ||
1999 | return 0; | |
2000 | } | |
2001 | ||
fcf0649f | 2002 | static int amdgpu_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2003 | { |
2004 | int i, r; | |
2005 | ||
2006 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2007 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2008 | continue; |
fcf0649f CZ |
2009 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
2010 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2011 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) | |
2012 | continue; | |
a1255107 | 2013 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2014 | if (r) { |
a1255107 AD |
2015 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2016 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2017 | return r; |
2c1a2784 | 2018 | } |
d38ceaf9 AD |
2019 | } |
2020 | ||
2021 | return 0; | |
2022 | } | |
2023 | ||
fcf0649f CZ |
2024 | static int amdgpu_resume(struct amdgpu_device *adev) |
2025 | { | |
2026 | int r; | |
2027 | ||
2028 | r = amdgpu_resume_phase1(adev); | |
2029 | if (r) | |
2030 | return r; | |
2031 | r = amdgpu_resume_phase2(adev); | |
2032 | ||
2033 | return r; | |
2034 | } | |
2035 | ||
4e99a44e | 2036 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2037 | { |
6867e1b5 ML |
2038 | if (amdgpu_sriov_vf(adev)) { |
2039 | if (adev->is_atom_fw) { | |
2040 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2041 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2042 | } else { | |
2043 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2044 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2045 | } | |
2046 | ||
2047 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2048 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2049 | } |
048765ad AR |
2050 | } |
2051 | ||
d38ceaf9 AD |
2052 | /** |
2053 | * amdgpu_device_init - initialize the driver | |
2054 | * | |
2055 | * @adev: amdgpu_device pointer | |
2056 | * @pdev: drm dev pointer | |
2057 | * @pdev: pci dev pointer | |
2058 | * @flags: driver flags | |
2059 | * | |
2060 | * Initializes the driver info and hw (all asics). | |
2061 | * Returns 0 for success or an error on failure. | |
2062 | * Called at driver startup. | |
2063 | */ | |
2064 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2065 | struct drm_device *ddev, | |
2066 | struct pci_dev *pdev, | |
2067 | uint32_t flags) | |
2068 | { | |
2069 | int r, i; | |
2070 | bool runtime = false; | |
95844d20 | 2071 | u32 max_MBps; |
d38ceaf9 AD |
2072 | |
2073 | adev->shutdown = false; | |
2074 | adev->dev = &pdev->dev; | |
2075 | adev->ddev = ddev; | |
2076 | adev->pdev = pdev; | |
2077 | adev->flags = flags; | |
2f7d10b3 | 2078 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2079 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
6f02a696 | 2080 | adev->mc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2081 | adev->accel_working = false; |
2082 | adev->num_rings = 0; | |
2083 | adev->mman.buffer_funcs = NULL; | |
2084 | adev->mman.buffer_funcs_ring = NULL; | |
2085 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2086 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 2087 | adev->gart.gart_funcs = NULL; |
f54d1867 | 2088 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2089 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2090 | |
2091 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2092 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2093 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2094 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2095 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2096 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2097 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2098 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2099 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2100 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2101 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2102 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2103 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2104 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2105 | ||
ccdbb20a | 2106 | |
3e39ab90 AD |
2107 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2108 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2109 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2110 | |
2111 | /* mutex initialization are all done here so we | |
2112 | * can recall function without having locking issues */ | |
d38ceaf9 | 2113 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2114 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2115 | mutex_init(&adev->pm.mutex); |
2116 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2117 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2118 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d38ceaf9 | 2119 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2120 | mutex_init(&adev->mn_lock); |
e23b74aa | 2121 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 AD |
2122 | hash_init(adev->mn_hash); |
2123 | ||
2124 | amdgpu_check_arguments(adev); | |
2125 | ||
d38ceaf9 AD |
2126 | spin_lock_init(&adev->mmio_idx_lock); |
2127 | spin_lock_init(&adev->smc_idx_lock); | |
2128 | spin_lock_init(&adev->pcie_idx_lock); | |
2129 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2130 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2131 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2132 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2133 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2134 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2135 | |
0c4e7fa5 CZ |
2136 | INIT_LIST_HEAD(&adev->shadow_list); |
2137 | mutex_init(&adev->shadow_list_lock); | |
2138 | ||
5c1354bd CZ |
2139 | INIT_LIST_HEAD(&adev->gtt_list); |
2140 | spin_lock_init(&adev->gtt_list_lock); | |
2141 | ||
795f2813 AR |
2142 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2143 | spin_lock_init(&adev->ring_lru_list_lock); | |
2144 | ||
2dc80b00 S |
2145 | INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler); |
2146 | ||
0fa49558 AX |
2147 | /* Registers mapping */ |
2148 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2149 | if (adev->asic_type >= CHIP_BONAIRE) { |
2150 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2151 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2152 | } else { | |
2153 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2154 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2155 | } | |
d38ceaf9 | 2156 | |
d38ceaf9 AD |
2157 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2158 | if (adev->rmmio == NULL) { | |
2159 | return -ENOMEM; | |
2160 | } | |
2161 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2162 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2163 | ||
705e519e CK |
2164 | /* doorbell bar mapping */ |
2165 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
2166 | |
2167 | /* io port mapping */ | |
2168 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2169 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2170 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2171 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2172 | break; | |
2173 | } | |
2174 | } | |
2175 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2176 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 AD |
2177 | |
2178 | /* early init functions */ | |
2179 | r = amdgpu_early_init(adev); | |
2180 | if (r) | |
2181 | return r; | |
2182 | ||
2183 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2184 | /* this will fail for cards that aren't VGA class devices, just | |
2185 | * ignore it */ | |
2186 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
2187 | ||
2188 | if (amdgpu_runtime_pm == 1) | |
2189 | runtime = true; | |
e9bef455 | 2190 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2191 | runtime = true; |
84c8b22e LW |
2192 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2193 | vga_switcheroo_register_client(adev->pdev, | |
2194 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2195 | if (runtime) |
2196 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2197 | ||
2198 | /* Read BIOS */ | |
83ba126a AD |
2199 | if (!amdgpu_get_bios(adev)) { |
2200 | r = -EINVAL; | |
2201 | goto failed; | |
2202 | } | |
f7e9e9fe | 2203 | |
d38ceaf9 | 2204 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2205 | if (r) { |
2206 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
e23b74aa | 2207 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2208 | goto failed; |
2c1a2784 | 2209 | } |
d38ceaf9 | 2210 | |
4e99a44e ML |
2211 | /* detect if we are with an SRIOV vbios */ |
2212 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2213 | |
d38ceaf9 | 2214 | /* Post card if necessary */ |
91fe77eb | 2215 | if (amdgpu_need_post(adev)) { |
d38ceaf9 | 2216 | if (!adev->bios) { |
bec86378 | 2217 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2218 | r = -EINVAL; |
2219 | goto failed; | |
d38ceaf9 | 2220 | } |
bec86378 | 2221 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2222 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2223 | if (r) { | |
2224 | dev_err(adev->dev, "gpu post error!\n"); | |
2225 | goto failed; | |
2226 | } | |
2227 | } else { | |
2228 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
2229 | } |
2230 | ||
88b64e95 AD |
2231 | if (adev->is_atom_fw) { |
2232 | /* Initialize clocks */ | |
2233 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2234 | if (r) { | |
2235 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2236 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2237 | goto failed; |
2238 | } | |
2239 | } else { | |
a5bde2f9 AD |
2240 | /* Initialize clocks */ |
2241 | r = amdgpu_atombios_get_clock_info(adev); | |
2242 | if (r) { | |
2243 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2244 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2245 | goto failed; |
a5bde2f9 AD |
2246 | } |
2247 | /* init i2c buses */ | |
2248 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2249 | } |
d38ceaf9 AD |
2250 | |
2251 | /* Fence driver */ | |
2252 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2253 | if (r) { |
2254 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2255 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2256 | goto failed; |
2c1a2784 | 2257 | } |
d38ceaf9 AD |
2258 | |
2259 | /* init the mode config */ | |
2260 | drm_mode_config_init(adev->ddev); | |
2261 | ||
2262 | r = amdgpu_init(adev); | |
2263 | if (r) { | |
2c1a2784 | 2264 | dev_err(adev->dev, "amdgpu_init failed\n"); |
e23b74aa | 2265 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
d38ceaf9 | 2266 | amdgpu_fini(adev); |
83ba126a | 2267 | goto failed; |
d38ceaf9 AD |
2268 | } |
2269 | ||
2270 | adev->accel_working = true; | |
2271 | ||
e59c0205 AX |
2272 | amdgpu_vm_check_compute_bug(adev); |
2273 | ||
95844d20 MO |
2274 | /* Initialize the buffer migration limit. */ |
2275 | if (amdgpu_moverate >= 0) | |
2276 | max_MBps = amdgpu_moverate; | |
2277 | else | |
2278 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2279 | /* Get a log2 for easy divisions. */ | |
2280 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2281 | ||
d38ceaf9 AD |
2282 | r = amdgpu_ib_pool_init(adev); |
2283 | if (r) { | |
2284 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
e23b74aa | 2285 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2286 | goto failed; |
d38ceaf9 AD |
2287 | } |
2288 | ||
2289 | r = amdgpu_ib_ring_tests(adev); | |
2290 | if (r) | |
2291 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2292 | ||
2dc8f81e HC |
2293 | if (amdgpu_sriov_vf(adev)) |
2294 | amdgpu_virt_init_data_exchange(adev); | |
2295 | ||
9bc92b9c ML |
2296 | amdgpu_fbdev_init(adev); |
2297 | ||
d2f52ac8 RZ |
2298 | r = amdgpu_pm_sysfs_init(adev); |
2299 | if (r) | |
2300 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2301 | ||
d38ceaf9 | 2302 | r = amdgpu_gem_debugfs_init(adev); |
3f14e623 | 2303 | if (r) |
d38ceaf9 | 2304 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2305 | |
2306 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2307 | if (r) |
d38ceaf9 | 2308 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2309 | |
4f0955fc HR |
2310 | r = amdgpu_debugfs_test_ib_ring_init(adev); |
2311 | if (r) | |
2312 | DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r); | |
2313 | ||
50ab2533 | 2314 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2315 | if (r) |
50ab2533 | 2316 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2317 | |
db95e218 KR |
2318 | r = amdgpu_debugfs_vbios_dump_init(adev); |
2319 | if (r) | |
2320 | DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r); | |
2321 | ||
d38ceaf9 AD |
2322 | if ((amdgpu_testing & 1)) { |
2323 | if (adev->accel_working) | |
2324 | amdgpu_test_moves(adev); | |
2325 | else | |
2326 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2327 | } | |
d38ceaf9 AD |
2328 | if (amdgpu_benchmarking) { |
2329 | if (adev->accel_working) | |
2330 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2331 | else | |
2332 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2333 | } | |
2334 | ||
2335 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2336 | * explicit gating rather than handling it automatically. | |
2337 | */ | |
2338 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
2339 | if (r) { |
2340 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
e23b74aa | 2341 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2342 | goto failed; |
2c1a2784 | 2343 | } |
d38ceaf9 AD |
2344 | |
2345 | return 0; | |
83ba126a AD |
2346 | |
2347 | failed: | |
89041940 | 2348 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2349 | if (runtime) |
2350 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
2351 | return r; | |
d38ceaf9 AD |
2352 | } |
2353 | ||
d38ceaf9 AD |
2354 | /** |
2355 | * amdgpu_device_fini - tear down the driver | |
2356 | * | |
2357 | * @adev: amdgpu_device pointer | |
2358 | * | |
2359 | * Tear down the driver info (all asics). | |
2360 | * Called at driver shutdown. | |
2361 | */ | |
2362 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2363 | { | |
2364 | int r; | |
2365 | ||
2366 | DRM_INFO("amdgpu: finishing device.\n"); | |
2367 | adev->shutdown = true; | |
db2c2a97 PD |
2368 | if (adev->mode_info.mode_config_initialized) |
2369 | drm_crtc_force_disable_all(adev->ddev); | |
d38ceaf9 AD |
2370 | /* evict vram memory */ |
2371 | amdgpu_bo_evict_vram(adev); | |
2372 | amdgpu_ib_pool_fini(adev); | |
a05502e5 | 2373 | amdgpu_fw_reserve_vram_fini(adev); |
d38ceaf9 AD |
2374 | amdgpu_fence_driver_fini(adev); |
2375 | amdgpu_fbdev_fini(adev); | |
2376 | r = amdgpu_fini(adev); | |
ab4fe3e1 HR |
2377 | if (adev->firmware.gpu_info_fw) { |
2378 | release_firmware(adev->firmware.gpu_info_fw); | |
2379 | adev->firmware.gpu_info_fw = NULL; | |
2380 | } | |
d38ceaf9 | 2381 | adev->accel_working = false; |
2dc80b00 | 2382 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 AD |
2383 | /* free i2c buses */ |
2384 | amdgpu_i2c_fini(adev); | |
2385 | amdgpu_atombios_fini(adev); | |
2386 | kfree(adev->bios); | |
2387 | adev->bios = NULL; | |
84c8b22e LW |
2388 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2389 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2390 | if (adev->flags & AMD_IS_PX) |
2391 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2392 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2393 | if (adev->rio_mem) | |
2394 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2395 | adev->rio_mem = NULL; | |
2396 | iounmap(adev->rmmio); | |
2397 | adev->rmmio = NULL; | |
705e519e | 2398 | amdgpu_doorbell_fini(adev); |
d2f52ac8 | 2399 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2400 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2401 | } |
2402 | ||
2403 | ||
2404 | /* | |
2405 | * Suspend & resume. | |
2406 | */ | |
2407 | /** | |
810ddc3a | 2408 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2409 | * |
2410 | * @pdev: drm dev pointer | |
2411 | * @state: suspend state | |
2412 | * | |
2413 | * Puts the hw in the suspend state (all asics). | |
2414 | * Returns 0 for success or an error on failure. | |
2415 | * Called at driver suspend. | |
2416 | */ | |
810ddc3a | 2417 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2418 | { |
2419 | struct amdgpu_device *adev; | |
2420 | struct drm_crtc *crtc; | |
2421 | struct drm_connector *connector; | |
5ceb54c6 | 2422 | int r; |
d38ceaf9 AD |
2423 | |
2424 | if (dev == NULL || dev->dev_private == NULL) { | |
2425 | return -ENODEV; | |
2426 | } | |
2427 | ||
2428 | adev = dev->dev_private; | |
2429 | ||
2430 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2431 | return 0; | |
2432 | ||
2433 | drm_kms_helper_poll_disable(dev); | |
2434 | ||
2435 | /* turn off display hw */ | |
4c7fbc39 | 2436 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2437 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2438 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2439 | } | |
4c7fbc39 | 2440 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 2441 | |
ba997709 YZ |
2442 | amdgpu_amdkfd_suspend(adev); |
2443 | ||
756e6880 | 2444 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2445 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2446 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
2447 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
2448 | struct amdgpu_bo *robj; | |
2449 | ||
756e6880 AD |
2450 | if (amdgpu_crtc->cursor_bo) { |
2451 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2452 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2453 | if (r == 0) { |
2454 | amdgpu_bo_unpin(aobj); | |
2455 | amdgpu_bo_unreserve(aobj); | |
2456 | } | |
2457 | } | |
2458 | ||
d38ceaf9 AD |
2459 | if (rfb == NULL || rfb->obj == NULL) { |
2460 | continue; | |
2461 | } | |
2462 | robj = gem_to_amdgpu_bo(rfb->obj); | |
2463 | /* don't unpin kernel fb objects */ | |
2464 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2465 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2466 | if (r == 0) { |
2467 | amdgpu_bo_unpin(robj); | |
2468 | amdgpu_bo_unreserve(robj); | |
2469 | } | |
2470 | } | |
2471 | } | |
2472 | /* evict vram memory */ | |
2473 | amdgpu_bo_evict_vram(adev); | |
2474 | ||
5ceb54c6 | 2475 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
2476 | |
2477 | r = amdgpu_suspend(adev); | |
2478 | ||
a0a71e49 AD |
2479 | /* evict remaining vram memory |
2480 | * This second call to evict vram is to evict the gart page table | |
2481 | * using the CPU. | |
2482 | */ | |
d38ceaf9 AD |
2483 | amdgpu_bo_evict_vram(adev); |
2484 | ||
d05da0e2 | 2485 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
2486 | pci_save_state(dev->pdev); |
2487 | if (suspend) { | |
2488 | /* Shut down the device */ | |
2489 | pci_disable_device(dev->pdev); | |
2490 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2491 | } else { |
2492 | r = amdgpu_asic_reset(adev); | |
2493 | if (r) | |
2494 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2495 | } |
2496 | ||
2497 | if (fbcon) { | |
2498 | console_lock(); | |
2499 | amdgpu_fbdev_set_suspend(adev, 1); | |
2500 | console_unlock(); | |
2501 | } | |
2502 | return 0; | |
2503 | } | |
2504 | ||
2505 | /** | |
810ddc3a | 2506 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2507 | * |
2508 | * @pdev: drm dev pointer | |
2509 | * | |
2510 | * Bring the hw back to operating state (all asics). | |
2511 | * Returns 0 for success or an error on failure. | |
2512 | * Called at driver resume. | |
2513 | */ | |
810ddc3a | 2514 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2515 | { |
2516 | struct drm_connector *connector; | |
2517 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2518 | struct drm_crtc *crtc; |
03161a6e | 2519 | int r = 0; |
d38ceaf9 AD |
2520 | |
2521 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2522 | return 0; | |
2523 | ||
74b0b157 | 2524 | if (fbcon) |
d38ceaf9 | 2525 | console_lock(); |
74b0b157 | 2526 | |
d38ceaf9 AD |
2527 | if (resume) { |
2528 | pci_set_power_state(dev->pdev, PCI_D0); | |
2529 | pci_restore_state(dev->pdev); | |
74b0b157 | 2530 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2531 | if (r) |
2532 | goto unlock; | |
d38ceaf9 | 2533 | } |
d05da0e2 | 2534 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2535 | |
2536 | /* post card */ | |
c836fec5 | 2537 | if (amdgpu_need_post(adev)) { |
74b0b157 | 2538 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2539 | if (r) | |
2540 | DRM_ERROR("amdgpu asic init failed\n"); | |
2541 | } | |
d38ceaf9 AD |
2542 | |
2543 | r = amdgpu_resume(adev); | |
e6707218 | 2544 | if (r) { |
ca198528 | 2545 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); |
03161a6e | 2546 | goto unlock; |
e6707218 | 2547 | } |
5ceb54c6 AD |
2548 | amdgpu_fence_driver_resume(adev); |
2549 | ||
ca198528 FC |
2550 | if (resume) { |
2551 | r = amdgpu_ib_ring_tests(adev); | |
2552 | if (r) | |
2553 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2554 | } | |
d38ceaf9 AD |
2555 | |
2556 | r = amdgpu_late_init(adev); | |
03161a6e HR |
2557 | if (r) |
2558 | goto unlock; | |
d38ceaf9 | 2559 | |
756e6880 AD |
2560 | /* pin cursors */ |
2561 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2562 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2563 | ||
2564 | if (amdgpu_crtc->cursor_bo) { | |
2565 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2566 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2567 | if (r == 0) { |
2568 | r = amdgpu_bo_pin(aobj, | |
2569 | AMDGPU_GEM_DOMAIN_VRAM, | |
2570 | &amdgpu_crtc->cursor_addr); | |
2571 | if (r != 0) | |
2572 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2573 | amdgpu_bo_unreserve(aobj); | |
2574 | } | |
2575 | } | |
2576 | } | |
ba997709 YZ |
2577 | r = amdgpu_amdkfd_resume(adev); |
2578 | if (r) | |
2579 | return r; | |
756e6880 | 2580 | |
d38ceaf9 AD |
2581 | /* blat the mode back in */ |
2582 | if (fbcon) { | |
2583 | drm_helper_resume_force_mode(dev); | |
2584 | /* turn on display hw */ | |
4c7fbc39 | 2585 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2586 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2587 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2588 | } | |
4c7fbc39 | 2589 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2590 | } |
2591 | ||
2592 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2593 | |
2594 | /* | |
2595 | * Most of the connector probing functions try to acquire runtime pm | |
2596 | * refs to ensure that the GPU is powered on when connector polling is | |
2597 | * performed. Since we're calling this from a runtime PM callback, | |
2598 | * trying to acquire rpm refs will cause us to deadlock. | |
2599 | * | |
2600 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2601 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2602 | */ | |
2603 | #ifdef CONFIG_PM | |
2604 | dev->dev->power.disable_depth++; | |
2605 | #endif | |
54fb2a5c | 2606 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2607 | #ifdef CONFIG_PM |
2608 | dev->dev->power.disable_depth--; | |
2609 | #endif | |
d38ceaf9 | 2610 | |
03161a6e | 2611 | if (fbcon) |
d38ceaf9 | 2612 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2613 | |
2614 | unlock: | |
2615 | if (fbcon) | |
d38ceaf9 | 2616 | console_unlock(); |
d38ceaf9 | 2617 | |
03161a6e | 2618 | return r; |
d38ceaf9 AD |
2619 | } |
2620 | ||
63fbf42f CZ |
2621 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2622 | { | |
2623 | int i; | |
2624 | bool asic_hang = false; | |
2625 | ||
f993d628 ML |
2626 | if (amdgpu_sriov_vf(adev)) |
2627 | return true; | |
2628 | ||
63fbf42f | 2629 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2630 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2631 | continue; |
a1255107 AD |
2632 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2633 | adev->ip_blocks[i].status.hang = | |
2634 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2635 | if (adev->ip_blocks[i].status.hang) { | |
2636 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2637 | asic_hang = true; |
2638 | } | |
2639 | } | |
2640 | return asic_hang; | |
2641 | } | |
2642 | ||
4d446656 | 2643 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2644 | { |
2645 | int i, r = 0; | |
2646 | ||
2647 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2648 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2649 | continue; |
a1255107 AD |
2650 | if (adev->ip_blocks[i].status.hang && |
2651 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2652 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2653 | if (r) |
2654 | return r; | |
2655 | } | |
2656 | } | |
2657 | ||
2658 | return 0; | |
2659 | } | |
2660 | ||
35d782fe CZ |
2661 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2662 | { | |
da146d3b AD |
2663 | int i; |
2664 | ||
2665 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2666 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2667 | continue; |
a1255107 AD |
2668 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2669 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2670 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
2671 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
2672 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 2673 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
2674 | DRM_INFO("Some block need full reset!\n"); |
2675 | return true; | |
2676 | } | |
2677 | } | |
35d782fe CZ |
2678 | } |
2679 | return false; | |
2680 | } | |
2681 | ||
2682 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2683 | { | |
2684 | int i, r = 0; | |
2685 | ||
2686 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2687 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2688 | continue; |
a1255107 AD |
2689 | if (adev->ip_blocks[i].status.hang && |
2690 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2691 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2692 | if (r) |
2693 | return r; | |
2694 | } | |
2695 | } | |
2696 | ||
2697 | return 0; | |
2698 | } | |
2699 | ||
2700 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2701 | { | |
2702 | int i, r = 0; | |
2703 | ||
2704 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2705 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2706 | continue; |
a1255107 AD |
2707 | if (adev->ip_blocks[i].status.hang && |
2708 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2709 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2710 | if (r) |
2711 | return r; | |
2712 | } | |
2713 | ||
2714 | return 0; | |
2715 | } | |
2716 | ||
3ad81f16 CZ |
2717 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2718 | { | |
2719 | if (adev->flags & AMD_IS_APU) | |
2720 | return false; | |
2721 | ||
2722 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2723 | } | |
2724 | ||
53cdccd5 CZ |
2725 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2726 | struct amdgpu_ring *ring, | |
2727 | struct amdgpu_bo *bo, | |
f54d1867 | 2728 | struct dma_fence **fence) |
53cdccd5 CZ |
2729 | { |
2730 | uint32_t domain; | |
2731 | int r; | |
2732 | ||
23d2e504 RH |
2733 | if (!bo->shadow) |
2734 | return 0; | |
2735 | ||
1d284797 | 2736 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2737 | if (r) |
2738 | return r; | |
2739 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2740 | /* if bo has been evicted, then no need to recover */ | |
2741 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2742 | r = amdgpu_bo_validate(bo->shadow); |
2743 | if (r) { | |
2744 | DRM_ERROR("bo validate failed!\n"); | |
2745 | goto err; | |
2746 | } | |
2747 | ||
23d2e504 | 2748 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2749 | NULL, fence, true); |
23d2e504 RH |
2750 | if (r) { |
2751 | DRM_ERROR("recover page table failed!\n"); | |
2752 | goto err; | |
2753 | } | |
2754 | } | |
53cdccd5 | 2755 | err: |
23d2e504 RH |
2756 | amdgpu_bo_unreserve(bo); |
2757 | return r; | |
53cdccd5 CZ |
2758 | } |
2759 | ||
a90ad3c2 ML |
2760 | /** |
2761 | * amdgpu_sriov_gpu_reset - reset the asic | |
2762 | * | |
2763 | * @adev: amdgpu device pointer | |
7225f873 | 2764 | * @job: which job trigger hang |
a90ad3c2 ML |
2765 | * |
2766 | * Attempt the reset the GPU if it has hung (all asics). | |
2767 | * for SRIOV case. | |
2768 | * Returns 0 for success or an error on failure. | |
2769 | */ | |
7225f873 | 2770 | int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) |
a90ad3c2 | 2771 | { |
65781c78 | 2772 | int i, j, r = 0; |
a90ad3c2 ML |
2773 | int resched; |
2774 | struct amdgpu_bo *bo, *tmp; | |
2775 | struct amdgpu_ring *ring; | |
2776 | struct dma_fence *fence = NULL, *next = NULL; | |
2777 | ||
147b5983 | 2778 | mutex_lock(&adev->virt.lock_reset); |
a90ad3c2 | 2779 | atomic_inc(&adev->gpu_reset_counter); |
3224a12b | 2780 | adev->in_sriov_reset = true; |
a90ad3c2 ML |
2781 | |
2782 | /* block TTM */ | |
2783 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2784 | ||
65781c78 ML |
2785 | /* we start from the ring trigger GPU hang */ |
2786 | j = job ? job->ring->idx : 0; | |
a90ad3c2 | 2787 | |
65781c78 ML |
2788 | /* block scheduler */ |
2789 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { | |
2790 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2791 | if (!ring || !ring->sched.thread) |
2792 | continue; | |
2793 | ||
2794 | kthread_park(ring->sched.thread); | |
65781c78 ML |
2795 | |
2796 | if (job && j != i) | |
2797 | continue; | |
2798 | ||
4f059ecd | 2799 | /* here give the last chance to check if job removed from mirror-list |
65781c78 | 2800 | * since we already pay some time on kthread_park */ |
4f059ecd | 2801 | if (job && list_empty(&job->base.node)) { |
65781c78 ML |
2802 | kthread_unpark(ring->sched.thread); |
2803 | goto give_up_reset; | |
2804 | } | |
2805 | ||
2806 | if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) | |
2807 | amd_sched_job_kickout(&job->base); | |
2808 | ||
2809 | /* only do job_reset on the hang ring if @job not NULL */ | |
a90ad3c2 | 2810 | amd_sched_hw_job_reset(&ring->sched); |
a90ad3c2 | 2811 | |
65781c78 ML |
2812 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2813 | amdgpu_fence_driver_force_completion_ring(ring); | |
2814 | } | |
a90ad3c2 ML |
2815 | |
2816 | /* request to take full control of GPU before re-initialization */ | |
7225f873 | 2817 | if (job) |
a90ad3c2 ML |
2818 | amdgpu_virt_reset_gpu(adev); |
2819 | else | |
2820 | amdgpu_virt_request_full_gpu(adev, true); | |
2821 | ||
2822 | ||
2823 | /* Resume IP prior to SMC */ | |
e4f0fdcc | 2824 | amdgpu_sriov_reinit_early(adev); |
a90ad3c2 ML |
2825 | |
2826 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
2827 | amdgpu_ttm_recover_gart(adev); | |
2828 | ||
2829 | /* now we are okay to resume SMC/CP/SDMA */ | |
e4f0fdcc | 2830 | amdgpu_sriov_reinit_late(adev); |
a90ad3c2 ML |
2831 | |
2832 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
2833 | ||
2834 | if (amdgpu_ib_ring_tests(adev)) | |
2835 | dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); | |
2836 | ||
2837 | /* release full control of GPU after ib test */ | |
2838 | amdgpu_virt_release_full_gpu(adev, true); | |
2839 | ||
2840 | DRM_INFO("recover vram bo from shadow\n"); | |
2841 | ||
2842 | ring = adev->mman.buffer_funcs_ring; | |
2843 | mutex_lock(&adev->shadow_list_lock); | |
2844 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2845 | next = NULL; |
a90ad3c2 ML |
2846 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2847 | if (fence) { | |
2848 | r = dma_fence_wait(fence, false); | |
2849 | if (r) { | |
2850 | WARN(r, "recovery from shadow isn't completed\n"); | |
2851 | break; | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | dma_fence_put(fence); | |
2856 | fence = next; | |
2857 | } | |
2858 | mutex_unlock(&adev->shadow_list_lock); | |
2859 | ||
2860 | if (fence) { | |
2861 | r = dma_fence_wait(fence, false); | |
2862 | if (r) | |
2863 | WARN(r, "recovery from shadow isn't completed\n"); | |
2864 | } | |
2865 | dma_fence_put(fence); | |
2866 | ||
65781c78 ML |
2867 | for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { |
2868 | ring = adev->rings[i % AMDGPU_MAX_RINGS]; | |
a90ad3c2 ML |
2869 | if (!ring || !ring->sched.thread) |
2870 | continue; | |
2871 | ||
65781c78 ML |
2872 | if (job && j != i) { |
2873 | kthread_unpark(ring->sched.thread); | |
2874 | continue; | |
2875 | } | |
2876 | ||
a90ad3c2 ML |
2877 | amd_sched_job_recovery(&ring->sched); |
2878 | kthread_unpark(ring->sched.thread); | |
2879 | } | |
2880 | ||
2881 | drm_helper_resume_force_mode(adev->ddev); | |
65781c78 | 2882 | give_up_reset: |
a90ad3c2 ML |
2883 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); |
2884 | if (r) { | |
2885 | /* bad news, how to tell it to userspace ? */ | |
2886 | dev_info(adev->dev, "GPU reset failed\n"); | |
65781c78 ML |
2887 | } else { |
2888 | dev_info(adev->dev, "GPU reset successed!\n"); | |
a90ad3c2 ML |
2889 | } |
2890 | ||
3224a12b | 2891 | adev->in_sriov_reset = false; |
147b5983 | 2892 | mutex_unlock(&adev->virt.lock_reset); |
a90ad3c2 ML |
2893 | return r; |
2894 | } | |
2895 | ||
d38ceaf9 AD |
2896 | /** |
2897 | * amdgpu_gpu_reset - reset the asic | |
2898 | * | |
2899 | * @adev: amdgpu device pointer | |
2900 | * | |
2901 | * Attempt the reset the GPU if it has hung (all asics). | |
2902 | * Returns 0 for success or an error on failure. | |
2903 | */ | |
2904 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2905 | { | |
d38ceaf9 AD |
2906 | int i, r; |
2907 | int resched; | |
0c49e0b8 | 2908 | bool need_full_reset, vram_lost = false; |
fb140b29 | 2909 | |
63fbf42f CZ |
2910 | if (!amdgpu_check_soft_reset(adev)) { |
2911 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2912 | return 0; | |
2913 | } | |
d38ceaf9 | 2914 | |
d94aed5a | 2915 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2916 | |
a3c47d6b CZ |
2917 | /* block TTM */ |
2918 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2919 | ||
0875dc9e CZ |
2920 | /* block scheduler */ |
2921 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2922 | struct amdgpu_ring *ring = adev->rings[i]; | |
2923 | ||
51687759 | 2924 | if (!ring || !ring->sched.thread) |
0875dc9e CZ |
2925 | continue; |
2926 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2927 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2928 | } |
2200edac CZ |
2929 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2930 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2931 | |
35d782fe | 2932 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2933 | |
35d782fe CZ |
2934 | if (!need_full_reset) { |
2935 | amdgpu_pre_soft_reset(adev); | |
2936 | r = amdgpu_soft_reset(adev); | |
2937 | amdgpu_post_soft_reset(adev); | |
2938 | if (r || amdgpu_check_soft_reset(adev)) { | |
2939 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2940 | need_full_reset = true; | |
2941 | } | |
f1aa7e08 CZ |
2942 | } |
2943 | ||
35d782fe | 2944 | if (need_full_reset) { |
35d782fe | 2945 | r = amdgpu_suspend(adev); |
bfa99269 | 2946 | |
35d782fe | 2947 | retry: |
d05da0e2 | 2948 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2949 | r = amdgpu_asic_reset(adev); |
d05da0e2 | 2950 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2951 | /* post card */ |
2952 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2953 | ||
2954 | if (!r) { | |
2955 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
fcf0649f CZ |
2956 | r = amdgpu_resume_phase1(adev); |
2957 | if (r) | |
2958 | goto out; | |
0c49e0b8 | 2959 | vram_lost = amdgpu_check_vram_lost(adev); |
f1892138 | 2960 | if (vram_lost) { |
0c49e0b8 | 2961 | DRM_ERROR("VRAM is lost!\n"); |
f1892138 CZ |
2962 | atomic_inc(&adev->vram_lost_counter); |
2963 | } | |
fcf0649f CZ |
2964 | r = amdgpu_ttm_recover_gart(adev); |
2965 | if (r) | |
2966 | goto out; | |
2967 | r = amdgpu_resume_phase2(adev); | |
2968 | if (r) | |
2969 | goto out; | |
0c49e0b8 CZ |
2970 | if (vram_lost) |
2971 | amdgpu_fill_reset_magic(adev); | |
35d782fe | 2972 | } |
d38ceaf9 | 2973 | } |
fcf0649f | 2974 | out: |
d38ceaf9 | 2975 | if (!r) { |
e72cfd58 | 2976 | amdgpu_irq_gpu_reset_resume_helper(adev); |
1f465087 CZ |
2977 | r = amdgpu_ib_ring_tests(adev); |
2978 | if (r) { | |
2979 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2980 | r = amdgpu_suspend(adev); |
53cdccd5 | 2981 | need_full_reset = true; |
40019dc4 | 2982 | goto retry; |
1f465087 | 2983 | } |
53cdccd5 CZ |
2984 | /** |
2985 | * recovery vm page tables, since we cannot depend on VRAM is | |
2986 | * consistent after gpu full reset. | |
2987 | */ | |
2988 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2989 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2990 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2991 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2992 | |
2993 | DRM_INFO("recover vram bo from shadow\n"); | |
2994 | mutex_lock(&adev->shadow_list_lock); | |
2995 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
236763d3 | 2996 | next = NULL; |
53cdccd5 CZ |
2997 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); |
2998 | if (fence) { | |
f54d1867 | 2999 | r = dma_fence_wait(fence, false); |
53cdccd5 | 3000 | if (r) { |
1d7b17b0 | 3001 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 CZ |
3002 | break; |
3003 | } | |
3004 | } | |
1f465087 | 3005 | |
f54d1867 | 3006 | dma_fence_put(fence); |
53cdccd5 CZ |
3007 | fence = next; |
3008 | } | |
3009 | mutex_unlock(&adev->shadow_list_lock); | |
3010 | if (fence) { | |
f54d1867 | 3011 | r = dma_fence_wait(fence, false); |
53cdccd5 | 3012 | if (r) |
1d7b17b0 | 3013 | WARN(r, "recovery from shadow isn't completed\n"); |
53cdccd5 | 3014 | } |
f54d1867 | 3015 | dma_fence_put(fence); |
53cdccd5 | 3016 | } |
d38ceaf9 AD |
3017 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3018 | struct amdgpu_ring *ring = adev->rings[i]; | |
51687759 CZ |
3019 | |
3020 | if (!ring || !ring->sched.thread) | |
d38ceaf9 | 3021 | continue; |
53cdccd5 | 3022 | |
aa1c8900 | 3023 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 3024 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 3025 | } |
d38ceaf9 | 3026 | } else { |
2200edac | 3027 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 3028 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
51687759 | 3029 | if (adev->rings[i] && adev->rings[i]->sched.thread) { |
0875dc9e | 3030 | kthread_unpark(adev->rings[i]->sched.thread); |
0875dc9e | 3031 | } |
d38ceaf9 AD |
3032 | } |
3033 | } | |
3034 | ||
3035 | drm_helper_resume_force_mode(adev->ddev); | |
3036 | ||
3037 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
89041940 | 3038 | if (r) { |
d38ceaf9 AD |
3039 | /* bad news, how to tell it to userspace ? */ |
3040 | dev_info(adev->dev, "GPU reset failed\n"); | |
89041940 GW |
3041 | } |
3042 | else { | |
6643be65 | 3043 | dev_info(adev->dev, "GPU reset successed!\n"); |
89041940 | 3044 | } |
d38ceaf9 | 3045 | |
89041940 | 3046 | amdgpu_vf_error_trans_all(adev); |
d38ceaf9 AD |
3047 | return r; |
3048 | } | |
3049 | ||
d0dd7f0c AD |
3050 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
3051 | { | |
3052 | u32 mask; | |
3053 | int ret; | |
3054 | ||
cd474ba0 AD |
3055 | if (amdgpu_pcie_gen_cap) |
3056 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3057 | |
cd474ba0 AD |
3058 | if (amdgpu_pcie_lane_cap) |
3059 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3060 | |
cd474ba0 AD |
3061 | /* covers APUs as well */ |
3062 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3063 | if (adev->pm.pcie_gen_mask == 0) | |
3064 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3065 | if (adev->pm.pcie_mlw_mask == 0) | |
3066 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3067 | return; |
cd474ba0 | 3068 | } |
d0dd7f0c | 3069 | |
cd474ba0 AD |
3070 | if (adev->pm.pcie_gen_mask == 0) { |
3071 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
3072 | if (!ret) { | |
3073 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3074 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3075 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3076 | ||
3077 | if (mask & DRM_PCIE_SPEED_25) | |
3078 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3079 | if (mask & DRM_PCIE_SPEED_50) | |
3080 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3081 | if (mask & DRM_PCIE_SPEED_80) | |
3082 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3083 | } else { | |
3084 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3085 | } | |
3086 | } | |
3087 | if (adev->pm.pcie_mlw_mask == 0) { | |
3088 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3089 | if (!ret) { | |
3090 | switch (mask) { | |
3091 | case 32: | |
3092 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3093 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3094 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3095 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3096 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3097 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3098 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3099 | break; | |
3100 | case 16: | |
3101 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3102 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3103 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3104 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3105 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3106 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3107 | break; | |
3108 | case 12: | |
3109 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3110 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3111 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3112 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3113 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3114 | break; | |
3115 | case 8: | |
3116 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3117 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3118 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3119 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3120 | break; | |
3121 | case 4: | |
3122 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3123 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3124 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3125 | break; | |
3126 | case 2: | |
3127 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3128 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3129 | break; | |
3130 | case 1: | |
3131 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3132 | break; | |
3133 | default: | |
3134 | break; | |
3135 | } | |
3136 | } else { | |
3137 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3138 | } |
3139 | } | |
3140 | } | |
d38ceaf9 AD |
3141 | |
3142 | /* | |
3143 | * Debugfs | |
3144 | */ | |
3145 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 3146 | const struct drm_info_list *files, |
d38ceaf9 AD |
3147 | unsigned nfiles) |
3148 | { | |
3149 | unsigned i; | |
3150 | ||
3151 | for (i = 0; i < adev->debugfs_count; i++) { | |
3152 | if (adev->debugfs[i].files == files) { | |
3153 | /* Already registered */ | |
3154 | return 0; | |
3155 | } | |
3156 | } | |
3157 | ||
3158 | i = adev->debugfs_count + 1; | |
3159 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
3160 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
3161 | DRM_ERROR("Report so we increase " | |
3162 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
3163 | return -EINVAL; | |
3164 | } | |
3165 | adev->debugfs[adev->debugfs_count].files = files; | |
3166 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
3167 | adev->debugfs_count = i; | |
3168 | #if defined(CONFIG_DEBUG_FS) | |
d38ceaf9 AD |
3169 | drm_debugfs_create_files(files, nfiles, |
3170 | adev->ddev->primary->debugfs_root, | |
3171 | adev->ddev->primary); | |
3172 | #endif | |
3173 | return 0; | |
3174 | } | |
3175 | ||
d38ceaf9 AD |
3176 | #if defined(CONFIG_DEBUG_FS) |
3177 | ||
3178 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
3179 | size_t size, loff_t *pos) | |
3180 | { | |
45063097 | 3181 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3182 | ssize_t result = 0; |
3183 | int r; | |
bd12267d | 3184 | bool pm_pg_lock, use_bank; |
56628159 | 3185 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
3186 | |
3187 | if (size & 0x3 || *pos & 0x3) | |
3188 | return -EINVAL; | |
3189 | ||
bd12267d TSD |
3190 | /* are we reading registers for which a PG lock is necessary? */ |
3191 | pm_pg_lock = (*pos >> 23) & 1; | |
3192 | ||
56628159 | 3193 | if (*pos & (1ULL << 62)) { |
0b968650 TSD |
3194 | se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; |
3195 | sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; | |
3196 | instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; | |
32977f93 TSD |
3197 | |
3198 | if (se_bank == 0x3FF) | |
3199 | se_bank = 0xFFFFFFFF; | |
3200 | if (sh_bank == 0x3FF) | |
3201 | sh_bank = 0xFFFFFFFF; | |
3202 | if (instance_bank == 0x3FF) | |
3203 | instance_bank = 0xFFFFFFFF; | |
56628159 | 3204 | use_bank = 1; |
56628159 TSD |
3205 | } else { |
3206 | use_bank = 0; | |
3207 | } | |
3208 | ||
801a6aa9 | 3209 | *pos &= (1UL << 22) - 1; |
bd12267d | 3210 | |
56628159 | 3211 | if (use_bank) { |
32977f93 TSD |
3212 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
3213 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
3214 | return -EINVAL; |
3215 | mutex_lock(&adev->grbm_idx_mutex); | |
3216 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3217 | sh_bank, instance_bank); | |
3218 | } | |
3219 | ||
bd12267d TSD |
3220 | if (pm_pg_lock) |
3221 | mutex_lock(&adev->pm.mutex); | |
3222 | ||
d38ceaf9 AD |
3223 | while (size) { |
3224 | uint32_t value; | |
3225 | ||
3226 | if (*pos > adev->rmmio_size) | |
56628159 | 3227 | goto end; |
d38ceaf9 AD |
3228 | |
3229 | value = RREG32(*pos >> 2); | |
3230 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
3231 | if (r) { |
3232 | result = r; | |
3233 | goto end; | |
3234 | } | |
d38ceaf9 AD |
3235 | |
3236 | result += 4; | |
3237 | buf += 4; | |
3238 | *pos += 4; | |
3239 | size -= 4; | |
3240 | } | |
3241 | ||
56628159 TSD |
3242 | end: |
3243 | if (use_bank) { | |
3244 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3245 | mutex_unlock(&adev->grbm_idx_mutex); | |
3246 | } | |
3247 | ||
bd12267d TSD |
3248 | if (pm_pg_lock) |
3249 | mutex_unlock(&adev->pm.mutex); | |
3250 | ||
d38ceaf9 AD |
3251 | return result; |
3252 | } | |
3253 | ||
3254 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
3255 | size_t size, loff_t *pos) | |
3256 | { | |
45063097 | 3257 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
3258 | ssize_t result = 0; |
3259 | int r; | |
394fdde2 TSD |
3260 | bool pm_pg_lock, use_bank; |
3261 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
3262 | |
3263 | if (size & 0x3 || *pos & 0x3) | |
3264 | return -EINVAL; | |
3265 | ||
394fdde2 TSD |
3266 | /* are we reading registers for which a PG lock is necessary? */ |
3267 | pm_pg_lock = (*pos >> 23) & 1; | |
3268 | ||
3269 | if (*pos & (1ULL << 62)) { | |
0b968650 TSD |
3270 | se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; |
3271 | sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; | |
3272 | instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; | |
394fdde2 TSD |
3273 | |
3274 | if (se_bank == 0x3FF) | |
3275 | se_bank = 0xFFFFFFFF; | |
3276 | if (sh_bank == 0x3FF) | |
3277 | sh_bank = 0xFFFFFFFF; | |
3278 | if (instance_bank == 0x3FF) | |
3279 | instance_bank = 0xFFFFFFFF; | |
3280 | use_bank = 1; | |
3281 | } else { | |
3282 | use_bank = 0; | |
3283 | } | |
3284 | ||
801a6aa9 | 3285 | *pos &= (1UL << 22) - 1; |
394fdde2 TSD |
3286 | |
3287 | if (use_bank) { | |
3288 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
3289 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
3290 | return -EINVAL; | |
3291 | mutex_lock(&adev->grbm_idx_mutex); | |
3292 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
3293 | sh_bank, instance_bank); | |
3294 | } | |
3295 | ||
3296 | if (pm_pg_lock) | |
3297 | mutex_lock(&adev->pm.mutex); | |
3298 | ||
d38ceaf9 AD |
3299 | while (size) { |
3300 | uint32_t value; | |
3301 | ||
3302 | if (*pos > adev->rmmio_size) | |
3303 | return result; | |
3304 | ||
3305 | r = get_user(value, (uint32_t *)buf); | |
3306 | if (r) | |
3307 | return r; | |
3308 | ||
3309 | WREG32(*pos >> 2, value); | |
3310 | ||
3311 | result += 4; | |
3312 | buf += 4; | |
3313 | *pos += 4; | |
3314 | size -= 4; | |
3315 | } | |
3316 | ||
394fdde2 TSD |
3317 | if (use_bank) { |
3318 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
3319 | mutex_unlock(&adev->grbm_idx_mutex); | |
3320 | } | |
3321 | ||
3322 | if (pm_pg_lock) | |
3323 | mutex_unlock(&adev->pm.mutex); | |
3324 | ||
d38ceaf9 AD |
3325 | return result; |
3326 | } | |
3327 | ||
adcec288 TSD |
3328 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
3329 | size_t size, loff_t *pos) | |
3330 | { | |
45063097 | 3331 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3332 | ssize_t result = 0; |
3333 | int r; | |
3334 | ||
3335 | if (size & 0x3 || *pos & 0x3) | |
3336 | return -EINVAL; | |
3337 | ||
3338 | while (size) { | |
3339 | uint32_t value; | |
3340 | ||
3341 | value = RREG32_PCIE(*pos >> 2); | |
3342 | r = put_user(value, (uint32_t *)buf); | |
3343 | if (r) | |
3344 | return r; | |
3345 | ||
3346 | result += 4; | |
3347 | buf += 4; | |
3348 | *pos += 4; | |
3349 | size -= 4; | |
3350 | } | |
3351 | ||
3352 | return result; | |
3353 | } | |
3354 | ||
3355 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
3356 | size_t size, loff_t *pos) | |
3357 | { | |
45063097 | 3358 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3359 | ssize_t result = 0; |
3360 | int r; | |
3361 | ||
3362 | if (size & 0x3 || *pos & 0x3) | |
3363 | return -EINVAL; | |
3364 | ||
3365 | while (size) { | |
3366 | uint32_t value; | |
3367 | ||
3368 | r = get_user(value, (uint32_t *)buf); | |
3369 | if (r) | |
3370 | return r; | |
3371 | ||
3372 | WREG32_PCIE(*pos >> 2, value); | |
3373 | ||
3374 | result += 4; | |
3375 | buf += 4; | |
3376 | *pos += 4; | |
3377 | size -= 4; | |
3378 | } | |
3379 | ||
3380 | return result; | |
3381 | } | |
3382 | ||
3383 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
3384 | size_t size, loff_t *pos) | |
3385 | { | |
45063097 | 3386 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3387 | ssize_t result = 0; |
3388 | int r; | |
3389 | ||
3390 | if (size & 0x3 || *pos & 0x3) | |
3391 | return -EINVAL; | |
3392 | ||
3393 | while (size) { | |
3394 | uint32_t value; | |
3395 | ||
3396 | value = RREG32_DIDT(*pos >> 2); | |
3397 | r = put_user(value, (uint32_t *)buf); | |
3398 | if (r) | |
3399 | return r; | |
3400 | ||
3401 | result += 4; | |
3402 | buf += 4; | |
3403 | *pos += 4; | |
3404 | size -= 4; | |
3405 | } | |
3406 | ||
3407 | return result; | |
3408 | } | |
3409 | ||
3410 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
3411 | size_t size, loff_t *pos) | |
3412 | { | |
45063097 | 3413 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3414 | ssize_t result = 0; |
3415 | int r; | |
3416 | ||
3417 | if (size & 0x3 || *pos & 0x3) | |
3418 | return -EINVAL; | |
3419 | ||
3420 | while (size) { | |
3421 | uint32_t value; | |
3422 | ||
3423 | r = get_user(value, (uint32_t *)buf); | |
3424 | if (r) | |
3425 | return r; | |
3426 | ||
3427 | WREG32_DIDT(*pos >> 2, value); | |
3428 | ||
3429 | result += 4; | |
3430 | buf += 4; | |
3431 | *pos += 4; | |
3432 | size -= 4; | |
3433 | } | |
3434 | ||
3435 | return result; | |
3436 | } | |
3437 | ||
3438 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
3439 | size_t size, loff_t *pos) | |
3440 | { | |
45063097 | 3441 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3442 | ssize_t result = 0; |
3443 | int r; | |
3444 | ||
3445 | if (size & 0x3 || *pos & 0x3) | |
3446 | return -EINVAL; | |
3447 | ||
3448 | while (size) { | |
3449 | uint32_t value; | |
3450 | ||
6fc0deaf | 3451 | value = RREG32_SMC(*pos); |
adcec288 TSD |
3452 | r = put_user(value, (uint32_t *)buf); |
3453 | if (r) | |
3454 | return r; | |
3455 | ||
3456 | result += 4; | |
3457 | buf += 4; | |
3458 | *pos += 4; | |
3459 | size -= 4; | |
3460 | } | |
3461 | ||
3462 | return result; | |
3463 | } | |
3464 | ||
3465 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
3466 | size_t size, loff_t *pos) | |
3467 | { | |
45063097 | 3468 | struct amdgpu_device *adev = file_inode(f)->i_private; |
adcec288 TSD |
3469 | ssize_t result = 0; |
3470 | int r; | |
3471 | ||
3472 | if (size & 0x3 || *pos & 0x3) | |
3473 | return -EINVAL; | |
3474 | ||
3475 | while (size) { | |
3476 | uint32_t value; | |
3477 | ||
3478 | r = get_user(value, (uint32_t *)buf); | |
3479 | if (r) | |
3480 | return r; | |
3481 | ||
6fc0deaf | 3482 | WREG32_SMC(*pos, value); |
adcec288 TSD |
3483 | |
3484 | result += 4; | |
3485 | buf += 4; | |
3486 | *pos += 4; | |
3487 | size -= 4; | |
3488 | } | |
3489 | ||
3490 | return result; | |
3491 | } | |
3492 | ||
1e051413 TSD |
3493 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
3494 | size_t size, loff_t *pos) | |
3495 | { | |
45063097 | 3496 | struct amdgpu_device *adev = file_inode(f)->i_private; |
1e051413 TSD |
3497 | ssize_t result = 0; |
3498 | int r; | |
3499 | uint32_t *config, no_regs = 0; | |
3500 | ||
3501 | if (size & 0x3 || *pos & 0x3) | |
3502 | return -EINVAL; | |
3503 | ||
ecab7668 | 3504 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
3505 | if (!config) |
3506 | return -ENOMEM; | |
3507 | ||
3508 | /* version, increment each time something is added */ | |
9a999359 | 3509 | config[no_regs++] = 3; |
1e051413 TSD |
3510 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
3511 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
3512 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
3513 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
3514 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
3515 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
3516 | config[no_regs++] = adev->gfx.config.max_gprs; | |
3517 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
3518 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
3519 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
3520 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
3521 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
3522 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
3523 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
3524 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
3525 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
3526 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
3527 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
3528 | config[no_regs++] = adev->gfx.config.num_gpus; | |
3529 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
3530 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
3531 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
3532 | config[no_regs++] = adev->gfx.config.num_rbs; | |
3533 | ||
89a8f309 TSD |
3534 | /* rev==1 */ |
3535 | config[no_regs++] = adev->rev_id; | |
3536 | config[no_regs++] = adev->pg_flags; | |
3537 | config[no_regs++] = adev->cg_flags; | |
3538 | ||
e9f11dc8 TSD |
3539 | /* rev==2 */ |
3540 | config[no_regs++] = adev->family; | |
3541 | config[no_regs++] = adev->external_rev_id; | |
3542 | ||
9a999359 TSD |
3543 | /* rev==3 */ |
3544 | config[no_regs++] = adev->pdev->device; | |
3545 | config[no_regs++] = adev->pdev->revision; | |
3546 | config[no_regs++] = adev->pdev->subsystem_device; | |
3547 | config[no_regs++] = adev->pdev->subsystem_vendor; | |
3548 | ||
1e051413 TSD |
3549 | while (size && (*pos < no_regs * 4)) { |
3550 | uint32_t value; | |
3551 | ||
3552 | value = config[*pos >> 2]; | |
3553 | r = put_user(value, (uint32_t *)buf); | |
3554 | if (r) { | |
3555 | kfree(config); | |
3556 | return r; | |
3557 | } | |
3558 | ||
3559 | result += 4; | |
3560 | buf += 4; | |
3561 | *pos += 4; | |
3562 | size -= 4; | |
3563 | } | |
3564 | ||
3565 | kfree(config); | |
3566 | return result; | |
3567 | } | |
3568 | ||
f2cdaf20 TSD |
3569 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
3570 | size_t size, loff_t *pos) | |
3571 | { | |
45063097 | 3572 | struct amdgpu_device *adev = file_inode(f)->i_private; |
9f8df7d7 TSD |
3573 | int idx, x, outsize, r, valuesize; |
3574 | uint32_t values[16]; | |
f2cdaf20 | 3575 | |
9f8df7d7 | 3576 | if (size & 3 || *pos & 0x3) |
f2cdaf20 TSD |
3577 | return -EINVAL; |
3578 | ||
3cbc614f SP |
3579 | if (amdgpu_dpm == 0) |
3580 | return -EINVAL; | |
3581 | ||
f2cdaf20 TSD |
3582 | /* convert offset to sensor number */ |
3583 | idx = *pos >> 2; | |
3584 | ||
9f8df7d7 | 3585 | valuesize = sizeof(values); |
f2cdaf20 | 3586 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) |
cd4d7464 | 3587 | r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); |
f2cdaf20 TSD |
3588 | else |
3589 | return -EINVAL; | |
3590 | ||
9f8df7d7 TSD |
3591 | if (size > valuesize) |
3592 | return -EINVAL; | |
3593 | ||
3594 | outsize = 0; | |
3595 | x = 0; | |
3596 | if (!r) { | |
3597 | while (size) { | |
3598 | r = put_user(values[x++], (int32_t *)buf); | |
3599 | buf += 4; | |
3600 | size -= 4; | |
3601 | outsize += 4; | |
3602 | } | |
3603 | } | |
f2cdaf20 | 3604 | |
9f8df7d7 | 3605 | return !r ? outsize : r; |
f2cdaf20 | 3606 | } |
1e051413 | 3607 | |
273d7aa1 TSD |
3608 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
3609 | size_t size, loff_t *pos) | |
3610 | { | |
3611 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3612 | int r, x; | |
3613 | ssize_t result=0; | |
472259f0 | 3614 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
3615 | |
3616 | if (size & 3 || *pos & 3) | |
3617 | return -EINVAL; | |
3618 | ||
3619 | /* decode offset */ | |
0b968650 TSD |
3620 | offset = (*pos & GENMASK_ULL(6, 0)); |
3621 | se = (*pos & GENMASK_ULL(14, 7)) >> 7; | |
3622 | sh = (*pos & GENMASK_ULL(22, 15)) >> 15; | |
3623 | cu = (*pos & GENMASK_ULL(30, 23)) >> 23; | |
3624 | wave = (*pos & GENMASK_ULL(36, 31)) >> 31; | |
3625 | simd = (*pos & GENMASK_ULL(44, 37)) >> 37; | |
273d7aa1 TSD |
3626 | |
3627 | /* switch to the specific se/sh/cu */ | |
3628 | mutex_lock(&adev->grbm_idx_mutex); | |
3629 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3630 | ||
3631 | x = 0; | |
472259f0 TSD |
3632 | if (adev->gfx.funcs->read_wave_data) |
3633 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
3634 | |
3635 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3636 | mutex_unlock(&adev->grbm_idx_mutex); | |
3637 | ||
5ecfb3b8 TSD |
3638 | if (!x) |
3639 | return -EINVAL; | |
3640 | ||
472259f0 | 3641 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
3642 | uint32_t value; |
3643 | ||
472259f0 | 3644 | value = data[offset >> 2]; |
273d7aa1 TSD |
3645 | r = put_user(value, (uint32_t *)buf); |
3646 | if (r) | |
3647 | return r; | |
3648 | ||
3649 | result += 4; | |
3650 | buf += 4; | |
472259f0 | 3651 | offset += 4; |
273d7aa1 TSD |
3652 | size -= 4; |
3653 | } | |
3654 | ||
3655 | return result; | |
3656 | } | |
3657 | ||
c5a60ce8 TSD |
3658 | static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, |
3659 | size_t size, loff_t *pos) | |
3660 | { | |
3661 | struct amdgpu_device *adev = f->f_inode->i_private; | |
3662 | int r; | |
3663 | ssize_t result = 0; | |
3664 | uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; | |
3665 | ||
3666 | if (size & 3 || *pos & 3) | |
3667 | return -EINVAL; | |
3668 | ||
3669 | /* decode offset */ | |
0b968650 TSD |
3670 | offset = *pos & GENMASK_ULL(11, 0); |
3671 | se = (*pos & GENMASK_ULL(19, 12)) >> 12; | |
3672 | sh = (*pos & GENMASK_ULL(27, 20)) >> 20; | |
3673 | cu = (*pos & GENMASK_ULL(35, 28)) >> 28; | |
3674 | wave = (*pos & GENMASK_ULL(43, 36)) >> 36; | |
3675 | simd = (*pos & GENMASK_ULL(51, 44)) >> 44; | |
3676 | thread = (*pos & GENMASK_ULL(59, 52)) >> 52; | |
3677 | bank = (*pos & GENMASK_ULL(61, 60)) >> 60; | |
c5a60ce8 TSD |
3678 | |
3679 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | |
3680 | if (!data) | |
3681 | return -ENOMEM; | |
3682 | ||
3683 | /* switch to the specific se/sh/cu */ | |
3684 | mutex_lock(&adev->grbm_idx_mutex); | |
3685 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
3686 | ||
3687 | if (bank == 0) { | |
3688 | if (adev->gfx.funcs->read_wave_vgprs) | |
3689 | adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); | |
3690 | } else { | |
3691 | if (adev->gfx.funcs->read_wave_sgprs) | |
3692 | adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); | |
3693 | } | |
3694 | ||
3695 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
3696 | mutex_unlock(&adev->grbm_idx_mutex); | |
3697 | ||
3698 | while (size) { | |
3699 | uint32_t value; | |
3700 | ||
3701 | value = data[offset++]; | |
3702 | r = put_user(value, (uint32_t *)buf); | |
3703 | if (r) { | |
3704 | result = r; | |
3705 | goto err; | |
3706 | } | |
3707 | ||
3708 | result += 4; | |
3709 | buf += 4; | |
3710 | size -= 4; | |
3711 | } | |
3712 | ||
3713 | err: | |
3714 | kfree(data); | |
3715 | return result; | |
3716 | } | |
3717 | ||
d38ceaf9 AD |
3718 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
3719 | .owner = THIS_MODULE, | |
3720 | .read = amdgpu_debugfs_regs_read, | |
3721 | .write = amdgpu_debugfs_regs_write, | |
3722 | .llseek = default_llseek | |
3723 | }; | |
adcec288 TSD |
3724 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3725 | .owner = THIS_MODULE, | |
3726 | .read = amdgpu_debugfs_regs_didt_read, | |
3727 | .write = amdgpu_debugfs_regs_didt_write, | |
3728 | .llseek = default_llseek | |
3729 | }; | |
3730 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3731 | .owner = THIS_MODULE, | |
3732 | .read = amdgpu_debugfs_regs_pcie_read, | |
3733 | .write = amdgpu_debugfs_regs_pcie_write, | |
3734 | .llseek = default_llseek | |
3735 | }; | |
3736 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3737 | .owner = THIS_MODULE, | |
3738 | .read = amdgpu_debugfs_regs_smc_read, | |
3739 | .write = amdgpu_debugfs_regs_smc_write, | |
3740 | .llseek = default_llseek | |
3741 | }; | |
3742 | ||
1e051413 TSD |
3743 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3744 | .owner = THIS_MODULE, | |
3745 | .read = amdgpu_debugfs_gca_config_read, | |
3746 | .llseek = default_llseek | |
3747 | }; | |
3748 | ||
f2cdaf20 TSD |
3749 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3750 | .owner = THIS_MODULE, | |
3751 | .read = amdgpu_debugfs_sensor_read, | |
3752 | .llseek = default_llseek | |
3753 | }; | |
3754 | ||
273d7aa1 TSD |
3755 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3756 | .owner = THIS_MODULE, | |
3757 | .read = amdgpu_debugfs_wave_read, | |
3758 | .llseek = default_llseek | |
3759 | }; | |
c5a60ce8 TSD |
3760 | static const struct file_operations amdgpu_debugfs_gpr_fops = { |
3761 | .owner = THIS_MODULE, | |
3762 | .read = amdgpu_debugfs_gpr_read, | |
3763 | .llseek = default_llseek | |
3764 | }; | |
273d7aa1 | 3765 | |
adcec288 TSD |
3766 | static const struct file_operations *debugfs_regs[] = { |
3767 | &amdgpu_debugfs_regs_fops, | |
3768 | &amdgpu_debugfs_regs_didt_fops, | |
3769 | &amdgpu_debugfs_regs_pcie_fops, | |
3770 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3771 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3772 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3773 | &amdgpu_debugfs_wave_fops, |
c5a60ce8 | 3774 | &amdgpu_debugfs_gpr_fops, |
adcec288 TSD |
3775 | }; |
3776 | ||
3777 | static const char *debugfs_regs_names[] = { | |
3778 | "amdgpu_regs", | |
3779 | "amdgpu_regs_didt", | |
3780 | "amdgpu_regs_pcie", | |
3781 | "amdgpu_regs_smc", | |
1e051413 | 3782 | "amdgpu_gca_config", |
f2cdaf20 | 3783 | "amdgpu_sensors", |
273d7aa1 | 3784 | "amdgpu_wave", |
c5a60ce8 | 3785 | "amdgpu_gpr", |
adcec288 | 3786 | }; |
d38ceaf9 AD |
3787 | |
3788 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3789 | { | |
3790 | struct drm_minor *minor = adev->ddev->primary; | |
3791 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3792 | unsigned i, j; |
3793 | ||
3794 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3795 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3796 | S_IFREG | S_IRUGO, root, | |
3797 | adev, debugfs_regs[i]); | |
3798 | if (IS_ERR(ent)) { | |
3799 | for (j = 0; j < i; j++) { | |
3800 | debugfs_remove(adev->debugfs_regs[i]); | |
3801 | adev->debugfs_regs[i] = NULL; | |
3802 | } | |
3803 | return PTR_ERR(ent); | |
3804 | } | |
d38ceaf9 | 3805 | |
adcec288 TSD |
3806 | if (!i) |
3807 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3808 | adev->debugfs_regs[i] = ent; | |
3809 | } | |
d38ceaf9 AD |
3810 | |
3811 | return 0; | |
3812 | } | |
3813 | ||
3814 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3815 | { | |
adcec288 TSD |
3816 | unsigned i; |
3817 | ||
3818 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3819 | if (adev->debugfs_regs[i]) { | |
3820 | debugfs_remove(adev->debugfs_regs[i]); | |
3821 | adev->debugfs_regs[i] = NULL; | |
3822 | } | |
3823 | } | |
d38ceaf9 AD |
3824 | } |
3825 | ||
4f0955fc HR |
3826 | static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) |
3827 | { | |
3828 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3829 | struct drm_device *dev = node->minor->dev; | |
3830 | struct amdgpu_device *adev = dev->dev_private; | |
3831 | int r = 0, i; | |
3832 | ||
3833 | /* hold on the scheduler */ | |
3834 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3835 | struct amdgpu_ring *ring = adev->rings[i]; | |
3836 | ||
3837 | if (!ring || !ring->sched.thread) | |
3838 | continue; | |
3839 | kthread_park(ring->sched.thread); | |
3840 | } | |
3841 | ||
3842 | seq_printf(m, "run ib test:\n"); | |
3843 | r = amdgpu_ib_ring_tests(adev); | |
3844 | if (r) | |
3845 | seq_printf(m, "ib ring tests failed (%d).\n", r); | |
3846 | else | |
3847 | seq_printf(m, "ib ring tests passed.\n"); | |
3848 | ||
3849 | /* go on the scheduler */ | |
3850 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
3851 | struct amdgpu_ring *ring = adev->rings[i]; | |
3852 | ||
3853 | if (!ring || !ring->sched.thread) | |
3854 | continue; | |
3855 | kthread_unpark(ring->sched.thread); | |
3856 | } | |
3857 | ||
3858 | return 0; | |
3859 | } | |
3860 | ||
3861 | static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = { | |
3862 | {"amdgpu_test_ib", &amdgpu_debugfs_test_ib} | |
3863 | }; | |
3864 | ||
3865 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) | |
3866 | { | |
3867 | return amdgpu_debugfs_add_files(adev, | |
3868 | amdgpu_debugfs_test_ib_ring_list, 1); | |
3869 | } | |
3870 | ||
d38ceaf9 AD |
3871 | int amdgpu_debugfs_init(struct drm_minor *minor) |
3872 | { | |
3873 | return 0; | |
3874 | } | |
db95e218 KR |
3875 | |
3876 | static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) | |
3877 | { | |
3878 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3879 | struct drm_device *dev = node->minor->dev; | |
3880 | struct amdgpu_device *adev = dev->dev_private; | |
3881 | ||
3882 | seq_write(m, adev->bios, adev->bios_size); | |
3883 | return 0; | |
3884 | } | |
3885 | ||
db95e218 KR |
3886 | static const struct drm_info_list amdgpu_vbios_dump_list[] = { |
3887 | {"amdgpu_vbios", | |
3888 | amdgpu_debugfs_get_vbios_dump, | |
3889 | 0, NULL}, | |
3890 | }; | |
3891 | ||
db95e218 KR |
3892 | static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) |
3893 | { | |
3894 | return amdgpu_debugfs_add_files(adev, | |
3895 | amdgpu_vbios_dump_list, 1); | |
3896 | } | |
7cebc728 | 3897 | #else |
27bad5b9 | 3898 | static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev) |
4f0955fc HR |
3899 | { |
3900 | return 0; | |
3901 | } | |
7cebc728 AK |
3902 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) |
3903 | { | |
3904 | return 0; | |
3905 | } | |
db95e218 KR |
3906 | static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev) |
3907 | { | |
3908 | return 0; | |
3909 | } | |
7cebc728 | 3910 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } |
d38ceaf9 | 3911 | #endif |