Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
4a74c38c | 33 | #include <linux/iommu.h> |
901e2be2 | 34 | #include <linux/pci.h> |
08a2fd23 | 35 | #include <linux/pci-p2pdma.h> |
d37a3929 | 36 | #include <linux/apple-gmux.h> |
fdf2f6c5 | 37 | |
b7cdb41e | 38 | #include <drm/drm_aperture.h> |
4562236b | 39 | #include <drm/drm_atomic_helper.h> |
973ad627 | 40 | #include <drm/drm_crtc_helper.h> |
45b64fd9 | 41 | #include <drm/drm_fb_helper.h> |
fcd70cd3 | 42 | #include <drm/drm_probe_helper.h> |
d38ceaf9 | 43 | #include <drm/amdgpu_drm.h> |
7b1c6263 | 44 | #include <linux/device.h> |
d38ceaf9 AD |
45 | #include <linux/vgaarb.h> |
46 | #include <linux/vga_switcheroo.h> | |
47 | #include <linux/efi.h> | |
48 | #include "amdgpu.h" | |
f4b373f4 | 49 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
50 | #include "amdgpu_i2c.h" |
51 | #include "atom.h" | |
52 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 53 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 54 | #include "amd_pcie.h" |
33f34802 KW |
55 | #ifdef CONFIG_DRM_AMDGPU_SI |
56 | #include "si.h" | |
57 | #endif | |
a2e73f56 AD |
58 | #ifdef CONFIG_DRM_AMDGPU_CIK |
59 | #include "cik.h" | |
60 | #endif | |
aaa36a97 | 61 | #include "vi.h" |
460826e6 | 62 | #include "soc15.h" |
0a5b8c7b | 63 | #include "nv.h" |
d38ceaf9 | 64 | #include "bif/bif_4_1_d.h" |
bec86378 | 65 | #include <linux/firmware.h> |
89041940 | 66 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 67 | |
ba997709 | 68 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 69 | #include "amdgpu_pm.h" |
d38ceaf9 | 70 | |
5183411b | 71 | #include "amdgpu_xgmi.h" |
c030f2e4 | 72 | #include "amdgpu_ras.h" |
9c7c85f7 | 73 | #include "amdgpu_pmu.h" |
bd607166 | 74 | #include "amdgpu_fru_eeprom.h" |
04442bf7 | 75 | #include "amdgpu_reset.h" |
85150626 | 76 | #include "amdgpu_virt.h" |
5183411b | 77 | |
d5ea093e | 78 | #include <linux/suspend.h> |
c6a6e2db | 79 | #include <drm/task_barrier.h> |
3f12acc8 | 80 | #include <linux/pm_runtime.h> |
d5ea093e | 81 | |
f89f8c6b AG |
82 | #include <drm/drm_drv.h> |
83 | ||
3ad5dcfe KHF |
84 | #if IS_ENABLED(CONFIG_X86) |
85 | #include <asm/intel-family.h> | |
86 | #endif | |
87 | ||
e2a75f88 | 88 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 89 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 90 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 91 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 92 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 93 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
42b325e5 | 94 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
e2a75f88 | 95 | |
2dc80b00 | 96 | #define AMDGPU_RESUME_MS 2000 |
7258fa31 SK |
97 | #define AMDGPU_MAX_RETRY_LIMIT 2 |
98 | #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL) | |
ad390542 HZ |
99 | #define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2) |
100 | #define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2) | |
101 | #define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2) | |
2dc80b00 | 102 | |
b7cdb41e ML |
103 | static const struct drm_driver amdgpu_kms_driver; |
104 | ||
050091ab | 105 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
106 | "TAHITI", |
107 | "PITCAIRN", | |
108 | "VERDE", | |
109 | "OLAND", | |
110 | "HAINAN", | |
d38ceaf9 AD |
111 | "BONAIRE", |
112 | "KAVERI", | |
113 | "KABINI", | |
114 | "HAWAII", | |
115 | "MULLINS", | |
116 | "TOPAZ", | |
117 | "TONGA", | |
48299f95 | 118 | "FIJI", |
d38ceaf9 | 119 | "CARRIZO", |
139f4917 | 120 | "STONEY", |
2cc0c0b5 FC |
121 | "POLARIS10", |
122 | "POLARIS11", | |
c4642a47 | 123 | "POLARIS12", |
48ff108d | 124 | "VEGAM", |
d4196f01 | 125 | "VEGA10", |
8fab806a | 126 | "VEGA12", |
956fcddc | 127 | "VEGA20", |
2ca8a5d2 | 128 | "RAVEN", |
d6c3b24e | 129 | "ARCTURUS", |
1eee4228 | 130 | "RENOIR", |
d46b417a | 131 | "ALDEBARAN", |
852a6626 | 132 | "NAVI10", |
d0f56dc2 | 133 | "CYAN_SKILLFISH", |
87dbad02 | 134 | "NAVI14", |
9802f5d7 | 135 | "NAVI12", |
ccaf72d3 | 136 | "SIENNA_CICHLID", |
ddd8fbe7 | 137 | "NAVY_FLOUNDER", |
4f1e9a76 | 138 | "VANGOGH", |
a2468e04 | 139 | "DIMGREY_CAVEFISH", |
6f169591 | 140 | "BEIGE_GOBY", |
ee9236b7 | 141 | "YELLOW_CARP", |
3ae695d6 | 142 | "IP DISCOVERY", |
d38ceaf9 AD |
143 | "LAST", |
144 | }; | |
145 | ||
dcea6e65 KR |
146 | /** |
147 | * DOC: pcie_replay_count | |
148 | * | |
149 | * The amdgpu driver provides a sysfs API for reporting the total number | |
150 | * of PCIe replays (NAKs) | |
151 | * The file pcie_replay_count is used for this and returns the total | |
152 | * number of replays as a sum of the NAKs generated and NAKs received | |
153 | */ | |
154 | ||
155 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
156 | struct device_attribute *attr, char *buf) | |
157 | { | |
158 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 159 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
160 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
161 | ||
36000c7a | 162 | return sysfs_emit(buf, "%llu\n", cnt); |
dcea6e65 KR |
163 | } |
164 | ||
b8920e1e | 165 | static DEVICE_ATTR(pcie_replay_count, 0444, |
dcea6e65 KR |
166 | amdgpu_device_get_pcie_replay_count, NULL); |
167 | ||
af39e6f4 LL |
168 | static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj, |
169 | struct bin_attribute *attr, char *buf, | |
170 | loff_t ppos, size_t count) | |
171 | { | |
172 | struct device *dev = kobj_to_dev(kobj); | |
173 | struct drm_device *ddev = dev_get_drvdata(dev); | |
174 | struct amdgpu_device *adev = drm_to_adev(ddev); | |
175 | ssize_t bytes_read; | |
176 | ||
177 | switch (ppos) { | |
178 | case AMDGPU_SYS_REG_STATE_XGMI: | |
179 | bytes_read = amdgpu_asic_get_reg_state( | |
180 | adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count); | |
181 | break; | |
182 | case AMDGPU_SYS_REG_STATE_WAFL: | |
183 | bytes_read = amdgpu_asic_get_reg_state( | |
184 | adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count); | |
185 | break; | |
186 | case AMDGPU_SYS_REG_STATE_PCIE: | |
187 | bytes_read = amdgpu_asic_get_reg_state( | |
188 | adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count); | |
189 | break; | |
190 | case AMDGPU_SYS_REG_STATE_USR: | |
191 | bytes_read = amdgpu_asic_get_reg_state( | |
192 | adev, AMDGPU_REG_STATE_TYPE_USR, buf, count); | |
193 | break; | |
194 | case AMDGPU_SYS_REG_STATE_USR_1: | |
195 | bytes_read = amdgpu_asic_get_reg_state( | |
196 | adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count); | |
197 | break; | |
198 | default: | |
199 | return -EINVAL; | |
200 | } | |
201 | ||
202 | return bytes_read; | |
203 | } | |
204 | ||
205 | BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL, | |
206 | AMDGPU_SYS_REG_STATE_END); | |
207 | ||
208 | int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev) | |
209 | { | |
210 | int ret; | |
211 | ||
212 | if (!amdgpu_asic_get_reg_state_supported(adev)) | |
213 | return 0; | |
214 | ||
215 | ret = sysfs_create_bin_file(&adev->dev->kobj, &bin_attr_reg_state); | |
216 | ||
217 | return ret; | |
218 | } | |
219 | ||
220 | void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev) | |
221 | { | |
222 | if (!amdgpu_asic_get_reg_state_supported(adev)) | |
223 | return; | |
224 | sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state); | |
225 | } | |
226 | ||
4798db85 LL |
227 | /** |
228 | * DOC: board_info | |
229 | * | |
230 | * The amdgpu driver provides a sysfs API for giving board related information. | |
231 | * It provides the form factor information in the format | |
232 | * | |
233 | * type : form factor | |
234 | * | |
235 | * Possible form factor values | |
236 | * | |
237 | * - "cem" - PCIE CEM card | |
238 | * - "oam" - Open Compute Accelerator Module | |
239 | * - "unknown" - Not known | |
240 | * | |
241 | */ | |
242 | ||
76da73f0 LL |
243 | static ssize_t amdgpu_device_get_board_info(struct device *dev, |
244 | struct device_attribute *attr, | |
245 | char *buf) | |
246 | { | |
247 | struct drm_device *ddev = dev_get_drvdata(dev); | |
248 | struct amdgpu_device *adev = drm_to_adev(ddev); | |
249 | enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM; | |
250 | const char *pkg; | |
251 | ||
252 | if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type) | |
253 | pkg_type = adev->smuio.funcs->get_pkg_type(adev); | |
254 | ||
255 | switch (pkg_type) { | |
256 | case AMDGPU_PKG_TYPE_CEM: | |
257 | pkg = "cem"; | |
258 | break; | |
259 | case AMDGPU_PKG_TYPE_OAM: | |
260 | pkg = "oam"; | |
261 | break; | |
262 | default: | |
263 | pkg = "unknown"; | |
264 | break; | |
265 | } | |
266 | ||
267 | return sysfs_emit(buf, "%s : %s\n", "type", pkg); | |
268 | } | |
269 | ||
270 | static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL); | |
271 | ||
272 | static struct attribute *amdgpu_board_attrs[] = { | |
273 | &dev_attr_board_info.attr, | |
274 | NULL, | |
275 | }; | |
276 | ||
277 | static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj, | |
278 | struct attribute *attr, int n) | |
279 | { | |
280 | struct device *dev = kobj_to_dev(kobj); | |
281 | struct drm_device *ddev = dev_get_drvdata(dev); | |
282 | struct amdgpu_device *adev = drm_to_adev(ddev); | |
283 | ||
284 | if (adev->flags & AMD_IS_APU) | |
285 | return 0; | |
286 | ||
287 | return attr->mode; | |
288 | } | |
289 | ||
290 | static const struct attribute_group amdgpu_board_attrs_group = { | |
291 | .attrs = amdgpu_board_attrs, | |
292 | .is_visible = amdgpu_board_attrs_is_visible | |
293 | }; | |
294 | ||
5494d864 AD |
295 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
296 | ||
bd607166 | 297 | |
fd496ca8 | 298 | /** |
b98c6299 | 299 | * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control |
fd496ca8 AD |
300 | * |
301 | * @dev: drm_device pointer | |
302 | * | |
b98c6299 | 303 | * Returns true if the device is a dGPU with ATPX power control, |
fd496ca8 AD |
304 | * otherwise return false. |
305 | */ | |
b98c6299 | 306 | bool amdgpu_device_supports_px(struct drm_device *dev) |
fd496ca8 AD |
307 | { |
308 | struct amdgpu_device *adev = drm_to_adev(dev); | |
309 | ||
b98c6299 | 310 | if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid()) |
fd496ca8 AD |
311 | return true; |
312 | return false; | |
313 | } | |
314 | ||
e3ecdffa | 315 | /** |
0330b848 | 316 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
317 | * |
318 | * @dev: drm_device pointer | |
319 | * | |
b98c6299 | 320 | * Returns true if the device is a dGPU with ACPI power control, |
e3ecdffa AD |
321 | * otherwise return false. |
322 | */ | |
31af062a | 323 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 324 | { |
1348969a | 325 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 326 | |
b98c6299 AD |
327 | if (adev->has_pr3 || |
328 | ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid())) | |
d38ceaf9 AD |
329 | return true; |
330 | return false; | |
331 | } | |
332 | ||
a69cba42 AD |
333 | /** |
334 | * amdgpu_device_supports_baco - Does the device support BACO | |
335 | * | |
336 | * @dev: drm_device pointer | |
337 | * | |
338 | * Returns true if the device supporte BACO, | |
339 | * otherwise return false. | |
340 | */ | |
341 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
342 | { | |
1348969a | 343 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
344 | |
345 | return amdgpu_asic_supports_baco(adev); | |
346 | } | |
347 | ||
3fa8f89d S |
348 | /** |
349 | * amdgpu_device_supports_smart_shift - Is the device dGPU with | |
350 | * smart shift support | |
351 | * | |
352 | * @dev: drm_device pointer | |
353 | * | |
354 | * Returns true if the device is a dGPU with Smart Shift support, | |
355 | * otherwise returns false. | |
356 | */ | |
357 | bool amdgpu_device_supports_smart_shift(struct drm_device *dev) | |
358 | { | |
359 | return (amdgpu_device_supports_boco(dev) && | |
360 | amdgpu_acpi_is_power_shift_control_supported()); | |
361 | } | |
362 | ||
6e3cd2a9 MCC |
363 | /* |
364 | * VRAM access helper functions | |
365 | */ | |
366 | ||
e35e2b11 | 367 | /** |
048af66b | 368 | * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA |
e35e2b11 TY |
369 | * |
370 | * @adev: amdgpu_device pointer | |
371 | * @pos: offset of the buffer in vram | |
372 | * @buf: virtual address of the buffer in system memory | |
373 | * @size: read/write size, sizeof(@buf) must > @size | |
374 | * @write: true - write to vram, otherwise - read from vram | |
375 | */ | |
048af66b KW |
376 | void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, |
377 | void *buf, size_t size, bool write) | |
e35e2b11 | 378 | { |
e35e2b11 | 379 | unsigned long flags; |
048af66b KW |
380 | uint32_t hi = ~0, tmp = 0; |
381 | uint32_t *data = buf; | |
ce05ac56 | 382 | uint64_t last; |
f89f8c6b | 383 | int idx; |
ce05ac56 | 384 | |
c58a863b | 385 | if (!drm_dev_enter(adev_to_drm(adev), &idx)) |
f89f8c6b | 386 | return; |
9d11eb0d | 387 | |
048af66b KW |
388 | BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4)); |
389 | ||
390 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
391 | for (last = pos + size; pos < last; pos += 4) { | |
392 | tmp = pos >> 31; | |
393 | ||
394 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); | |
395 | if (tmp != hi) { | |
396 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
397 | hi = tmp; | |
398 | } | |
399 | if (write) | |
400 | WREG32_NO_KIQ(mmMM_DATA, *data++); | |
401 | else | |
402 | *data++ = RREG32_NO_KIQ(mmMM_DATA); | |
403 | } | |
404 | ||
405 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
406 | drm_dev_exit(idx); | |
407 | } | |
408 | ||
409 | /** | |
bbe04dec | 410 | * amdgpu_device_aper_access - access vram by vram aperature |
048af66b KW |
411 | * |
412 | * @adev: amdgpu_device pointer | |
413 | * @pos: offset of the buffer in vram | |
414 | * @buf: virtual address of the buffer in system memory | |
415 | * @size: read/write size, sizeof(@buf) must > @size | |
416 | * @write: true - write to vram, otherwise - read from vram | |
417 | * | |
418 | * The return value means how many bytes have been transferred. | |
419 | */ | |
420 | size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, | |
421 | void *buf, size_t size, bool write) | |
422 | { | |
9d11eb0d | 423 | #ifdef CONFIG_64BIT |
048af66b KW |
424 | void __iomem *addr; |
425 | size_t count = 0; | |
426 | uint64_t last; | |
427 | ||
428 | if (!adev->mman.aper_base_kaddr) | |
429 | return 0; | |
430 | ||
9d11eb0d CK |
431 | last = min(pos + size, adev->gmc.visible_vram_size); |
432 | if (last > pos) { | |
048af66b KW |
433 | addr = adev->mman.aper_base_kaddr + pos; |
434 | count = last - pos; | |
9d11eb0d CK |
435 | |
436 | if (write) { | |
437 | memcpy_toio(addr, buf, count); | |
4c452b5c SS |
438 | /* Make sure HDP write cache flush happens without any reordering |
439 | * after the system memory contents are sent over PCIe device | |
440 | */ | |
9d11eb0d | 441 | mb(); |
810085dd | 442 | amdgpu_device_flush_hdp(adev, NULL); |
9d11eb0d | 443 | } else { |
810085dd | 444 | amdgpu_device_invalidate_hdp(adev, NULL); |
4c452b5c SS |
445 | /* Make sure HDP read cache is invalidated before issuing a read |
446 | * to the PCIe device | |
447 | */ | |
9d11eb0d CK |
448 | mb(); |
449 | memcpy_fromio(buf, addr, count); | |
450 | } | |
451 | ||
9d11eb0d | 452 | } |
048af66b KW |
453 | |
454 | return count; | |
455 | #else | |
456 | return 0; | |
9d11eb0d | 457 | #endif |
048af66b | 458 | } |
9d11eb0d | 459 | |
048af66b KW |
460 | /** |
461 | * amdgpu_device_vram_access - read/write a buffer in vram | |
462 | * | |
463 | * @adev: amdgpu_device pointer | |
464 | * @pos: offset of the buffer in vram | |
465 | * @buf: virtual address of the buffer in system memory | |
466 | * @size: read/write size, sizeof(@buf) must > @size | |
467 | * @write: true - write to vram, otherwise - read from vram | |
468 | */ | |
469 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
470 | void *buf, size_t size, bool write) | |
471 | { | |
472 | size_t count; | |
e35e2b11 | 473 | |
048af66b KW |
474 | /* try to using vram apreature to access vram first */ |
475 | count = amdgpu_device_aper_access(adev, pos, buf, size, write); | |
476 | size -= count; | |
477 | if (size) { | |
478 | /* using MM to access rest vram */ | |
479 | pos += count; | |
480 | buf += count; | |
481 | amdgpu_device_mm_access(adev, pos, buf, size, write); | |
e35e2b11 TY |
482 | } |
483 | } | |
484 | ||
d38ceaf9 | 485 | /* |
f7ee1874 | 486 | * register access helper functions. |
d38ceaf9 | 487 | */ |
56b53c0b DL |
488 | |
489 | /* Check if hw access should be skipped because of hotplug or device error */ | |
490 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
491 | { | |
7afefb81 | 492 | if (adev->no_hw_access) |
56b53c0b DL |
493 | return true; |
494 | ||
495 | #ifdef CONFIG_LOCKDEP | |
496 | /* | |
497 | * This is a bit complicated to understand, so worth a comment. What we assert | |
498 | * here is that the GPU reset is not running on another thread in parallel. | |
499 | * | |
500 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
501 | * we know that the reset is not running in paralell. | |
502 | * | |
503 | * If the trylock fails we assert that we are either already holding the read | |
504 | * side of the lock or are the reset thread itself and hold the write side of | |
505 | * the lock. | |
506 | */ | |
507 | if (in_task()) { | |
d0fb18b5 AG |
508 | if (down_read_trylock(&adev->reset_domain->sem)) |
509 | up_read(&adev->reset_domain->sem); | |
56b53c0b | 510 | else |
d0fb18b5 | 511 | lockdep_assert_held(&adev->reset_domain->sem); |
56b53c0b DL |
512 | } |
513 | #endif | |
514 | return false; | |
515 | } | |
516 | ||
e3ecdffa | 517 | /** |
f7ee1874 | 518 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
519 | * |
520 | * @adev: amdgpu_device pointer | |
521 | * @reg: dword aligned register offset | |
522 | * @acc_flags: access flags which require special behavior | |
523 | * | |
524 | * Returns the 32 bit value from the offset specified. | |
525 | */ | |
f7ee1874 HZ |
526 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
527 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 528 | { |
f4b373f4 TSD |
529 | uint32_t ret; |
530 | ||
56b53c0b | 531 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
532 | return 0; |
533 | ||
f7ee1874 HZ |
534 | if ((reg * 4) < adev->rmmio_size) { |
535 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
536 | amdgpu_sriov_runtime(adev) && | |
d0fb18b5 | 537 | down_read_trylock(&adev->reset_domain->sem)) { |
85150626 | 538 | ret = amdgpu_kiq_rreg(adev, reg, 0); |
d0fb18b5 | 539 | up_read(&adev->reset_domain->sem); |
f7ee1874 HZ |
540 | } else { |
541 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
542 | } | |
543 | } else { | |
544 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 545 | } |
bc992ba5 | 546 | |
f7ee1874 | 547 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 548 | |
f4b373f4 | 549 | return ret; |
d38ceaf9 AD |
550 | } |
551 | ||
421a2a30 ML |
552 | /* |
553 | * MMIO register read with bytes helper functions | |
554 | * @offset:bytes offset from MMIO start | |
b8920e1e | 555 | */ |
421a2a30 | 556 | |
e3ecdffa AD |
557 | /** |
558 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
559 | * | |
560 | * @adev: amdgpu_device pointer | |
561 | * @offset: byte aligned register offset | |
562 | * | |
563 | * Returns the 8 bit value from the offset specified. | |
564 | */ | |
7cbbc745 AG |
565 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
566 | { | |
56b53c0b | 567 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
568 | return 0; |
569 | ||
421a2a30 ML |
570 | if (offset < adev->rmmio_size) |
571 | return (readb(adev->rmmio + offset)); | |
572 | BUG(); | |
573 | } | |
574 | ||
85150626 VL |
575 | |
576 | /** | |
577 | * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC | |
578 | * | |
579 | * @adev: amdgpu_device pointer | |
580 | * @reg: dword aligned register offset | |
581 | * @acc_flags: access flags which require special behavior | |
582 | * @xcc_id: xcc accelerated compute core id | |
583 | * | |
584 | * Returns the 32 bit value from the offset specified. | |
585 | */ | |
586 | uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, | |
587 | uint32_t reg, uint32_t acc_flags, | |
588 | uint32_t xcc_id) | |
589 | { | |
590 | uint32_t ret, rlcg_flag; | |
591 | ||
592 | if (amdgpu_device_skip_hw_access(adev)) | |
593 | return 0; | |
594 | ||
595 | if ((reg * 4) < adev->rmmio_size) { | |
596 | if (amdgpu_sriov_vf(adev) && | |
597 | !amdgpu_sriov_runtime(adev) && | |
598 | adev->gfx.rlc.rlcg_reg_access_supported && | |
599 | amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, | |
600 | GC_HWIP, false, | |
601 | &rlcg_flag)) { | |
602 | ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id); | |
603 | } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
604 | amdgpu_sriov_runtime(adev) && | |
605 | down_read_trylock(&adev->reset_domain->sem)) { | |
606 | ret = amdgpu_kiq_rreg(adev, reg, xcc_id); | |
607 | up_read(&adev->reset_domain->sem); | |
608 | } else { | |
609 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
610 | } | |
611 | } else { | |
612 | ret = adev->pcie_rreg(adev, reg * 4); | |
613 | } | |
614 | ||
615 | return ret; | |
616 | } | |
617 | ||
421a2a30 ML |
618 | /* |
619 | * MMIO register write with bytes helper functions | |
620 | * @offset:bytes offset from MMIO start | |
621 | * @value: the value want to be written to the register | |
b8920e1e SS |
622 | */ |
623 | ||
e3ecdffa AD |
624 | /** |
625 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
626 | * | |
627 | * @adev: amdgpu_device pointer | |
628 | * @offset: byte aligned register offset | |
629 | * @value: 8 bit value to write | |
630 | * | |
631 | * Writes the value specified to the offset specified. | |
632 | */ | |
7cbbc745 AG |
633 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
634 | { | |
56b53c0b | 635 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
636 | return; |
637 | ||
421a2a30 ML |
638 | if (offset < adev->rmmio_size) |
639 | writeb(value, adev->rmmio + offset); | |
640 | else | |
641 | BUG(); | |
642 | } | |
643 | ||
e3ecdffa | 644 | /** |
f7ee1874 | 645 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
646 | * |
647 | * @adev: amdgpu_device pointer | |
648 | * @reg: dword aligned register offset | |
649 | * @v: 32 bit value to write to the register | |
650 | * @acc_flags: access flags which require special behavior | |
651 | * | |
652 | * Writes the value specified to the offset specified. | |
653 | */ | |
f7ee1874 HZ |
654 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
655 | uint32_t reg, uint32_t v, | |
656 | uint32_t acc_flags) | |
d38ceaf9 | 657 | { |
56b53c0b | 658 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
659 | return; |
660 | ||
f7ee1874 HZ |
661 | if ((reg * 4) < adev->rmmio_size) { |
662 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
663 | amdgpu_sriov_runtime(adev) && | |
d0fb18b5 | 664 | down_read_trylock(&adev->reset_domain->sem)) { |
85150626 | 665 | amdgpu_kiq_wreg(adev, reg, v, 0); |
d0fb18b5 | 666 | up_read(&adev->reset_domain->sem); |
f7ee1874 HZ |
667 | } else { |
668 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
669 | } | |
670 | } else { | |
671 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 672 | } |
bc992ba5 | 673 | |
f7ee1874 | 674 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 675 | } |
d38ceaf9 | 676 | |
03f2abb0 | 677 | /** |
4cc9f86f | 678 | * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range |
2e0cc4d4 | 679 | * |
71579346 RB |
680 | * @adev: amdgpu_device pointer |
681 | * @reg: mmio/rlc register | |
682 | * @v: value to write | |
8057a9d6 | 683 | * @xcc_id: xcc accelerated compute core id |
71579346 RB |
684 | * |
685 | * this function is invoked only for the debugfs register access | |
03f2abb0 | 686 | */ |
f7ee1874 | 687 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
8ed49dd1 VL |
688 | uint32_t reg, uint32_t v, |
689 | uint32_t xcc_id) | |
2e0cc4d4 | 690 | { |
56b53c0b | 691 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
692 | return; |
693 | ||
2e0cc4d4 | 694 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
695 | adev->gfx.rlc.funcs && |
696 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 | 697 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
8ed49dd1 | 698 | return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); |
4cc9f86f TSD |
699 | } else if ((reg * 4) >= adev->rmmio_size) { |
700 | adev->pcie_wreg(adev, reg * 4, v); | |
f7ee1874 HZ |
701 | } else { |
702 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 703 | } |
d38ceaf9 AD |
704 | } |
705 | ||
85150626 VL |
706 | /** |
707 | * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC | |
708 | * | |
709 | * @adev: amdgpu_device pointer | |
710 | * @reg: dword aligned register offset | |
711 | * @v: 32 bit value to write to the register | |
712 | * @acc_flags: access flags which require special behavior | |
713 | * @xcc_id: xcc accelerated compute core id | |
714 | * | |
715 | * Writes the value specified to the offset specified. | |
716 | */ | |
717 | void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, | |
718 | uint32_t reg, uint32_t v, | |
719 | uint32_t acc_flags, uint32_t xcc_id) | |
720 | { | |
721 | uint32_t rlcg_flag; | |
722 | ||
723 | if (amdgpu_device_skip_hw_access(adev)) | |
724 | return; | |
725 | ||
726 | if ((reg * 4) < adev->rmmio_size) { | |
727 | if (amdgpu_sriov_vf(adev) && | |
728 | !amdgpu_sriov_runtime(adev) && | |
729 | adev->gfx.rlc.rlcg_reg_access_supported && | |
730 | amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, | |
731 | GC_HWIP, true, | |
732 | &rlcg_flag)) { | |
733 | amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id); | |
734 | } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
735 | amdgpu_sriov_runtime(adev) && | |
736 | down_read_trylock(&adev->reset_domain->sem)) { | |
737 | amdgpu_kiq_wreg(adev, reg, v, xcc_id); | |
738 | up_read(&adev->reset_domain->sem); | |
739 | } else { | |
740 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
741 | } | |
742 | } else { | |
743 | adev->pcie_wreg(adev, reg * 4, v); | |
744 | } | |
745 | } | |
746 | ||
1bba3683 HZ |
747 | /** |
748 | * amdgpu_device_indirect_rreg - read an indirect register | |
749 | * | |
750 | * @adev: amdgpu_device pointer | |
22f453fb | 751 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
752 | * |
753 | * Returns the value of indirect register @reg_addr | |
754 | */ | |
755 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
1bba3683 HZ |
756 | u32 reg_addr) |
757 | { | |
65ba96e9 | 758 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
759 | void __iomem *pcie_index_offset; |
760 | void __iomem *pcie_data_offset; | |
65ba96e9 HZ |
761 | u32 r; |
762 | ||
763 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
764 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
1bba3683 HZ |
765 | |
766 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
767 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
768 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
769 | ||
770 | writel(reg_addr, pcie_index_offset); | |
771 | readl(pcie_index_offset); | |
772 | r = readl(pcie_data_offset); | |
773 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
774 | ||
775 | return r; | |
776 | } | |
777 | ||
0c552ed3 LM |
778 | u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, |
779 | u64 reg_addr) | |
780 | { | |
781 | unsigned long flags, pcie_index, pcie_index_hi, pcie_data; | |
782 | u32 r; | |
783 | void __iomem *pcie_index_offset; | |
784 | void __iomem *pcie_index_hi_offset; | |
785 | void __iomem *pcie_data_offset; | |
786 | ||
ad390542 HZ |
787 | if (unlikely(!adev->nbio.funcs)) { |
788 | pcie_index = AMDGPU_PCIE_INDEX_FALLBACK; | |
789 | pcie_data = AMDGPU_PCIE_DATA_FALLBACK; | |
790 | } else { | |
791 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
792 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
793 | } | |
794 | ||
795 | if (reg_addr >> 32) { | |
796 | if (unlikely(!adev->nbio.funcs)) | |
797 | pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK; | |
798 | else | |
799 | pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); | |
800 | } else { | |
0c552ed3 | 801 | pcie_index_hi = 0; |
ad390542 | 802 | } |
0c552ed3 LM |
803 | |
804 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
805 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
806 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
807 | if (pcie_index_hi != 0) | |
808 | pcie_index_hi_offset = (void __iomem *)adev->rmmio + | |
809 | pcie_index_hi * 4; | |
810 | ||
811 | writel(reg_addr, pcie_index_offset); | |
812 | readl(pcie_index_offset); | |
813 | if (pcie_index_hi != 0) { | |
814 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
815 | readl(pcie_index_hi_offset); | |
816 | } | |
817 | r = readl(pcie_data_offset); | |
818 | ||
819 | /* clear the high bits */ | |
820 | if (pcie_index_hi != 0) { | |
821 | writel(0, pcie_index_hi_offset); | |
822 | readl(pcie_index_hi_offset); | |
823 | } | |
824 | ||
825 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
826 | ||
827 | return r; | |
828 | } | |
829 | ||
1bba3683 HZ |
830 | /** |
831 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
832 | * | |
833 | * @adev: amdgpu_device pointer | |
22f453fb | 834 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
835 | * |
836 | * Returns the value of indirect register @reg_addr | |
837 | */ | |
838 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
1bba3683 HZ |
839 | u32 reg_addr) |
840 | { | |
65ba96e9 | 841 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
842 | void __iomem *pcie_index_offset; |
843 | void __iomem *pcie_data_offset; | |
65ba96e9 HZ |
844 | u64 r; |
845 | ||
846 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
847 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
1bba3683 HZ |
848 | |
849 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
850 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
851 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
852 | ||
853 | /* read low 32 bits */ | |
854 | writel(reg_addr, pcie_index_offset); | |
855 | readl(pcie_index_offset); | |
856 | r = readl(pcie_data_offset); | |
857 | /* read high 32 bits */ | |
858 | writel(reg_addr + 4, pcie_index_offset); | |
859 | readl(pcie_index_offset); | |
860 | r |= ((u64)readl(pcie_data_offset) << 32); | |
861 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
862 | ||
863 | return r; | |
864 | } | |
865 | ||
a76b2870 CL |
866 | u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, |
867 | u64 reg_addr) | |
868 | { | |
869 | unsigned long flags, pcie_index, pcie_data; | |
870 | unsigned long pcie_index_hi = 0; | |
871 | void __iomem *pcie_index_offset; | |
872 | void __iomem *pcie_index_hi_offset; | |
873 | void __iomem *pcie_data_offset; | |
874 | u64 r; | |
875 | ||
876 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
877 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
878 | if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) | |
879 | pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); | |
880 | ||
881 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
882 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
883 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
884 | if (pcie_index_hi != 0) | |
885 | pcie_index_hi_offset = (void __iomem *)adev->rmmio + | |
886 | pcie_index_hi * 4; | |
887 | ||
888 | /* read low 32 bits */ | |
889 | writel(reg_addr, pcie_index_offset); | |
890 | readl(pcie_index_offset); | |
891 | if (pcie_index_hi != 0) { | |
892 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
893 | readl(pcie_index_hi_offset); | |
894 | } | |
895 | r = readl(pcie_data_offset); | |
896 | /* read high 32 bits */ | |
897 | writel(reg_addr + 4, pcie_index_offset); | |
898 | readl(pcie_index_offset); | |
899 | if (pcie_index_hi != 0) { | |
900 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
901 | readl(pcie_index_hi_offset); | |
902 | } | |
903 | r |= ((u64)readl(pcie_data_offset) << 32); | |
904 | ||
905 | /* clear the high bits */ | |
906 | if (pcie_index_hi != 0) { | |
907 | writel(0, pcie_index_hi_offset); | |
908 | readl(pcie_index_hi_offset); | |
909 | } | |
910 | ||
911 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
912 | ||
913 | return r; | |
914 | } | |
915 | ||
1bba3683 HZ |
916 | /** |
917 | * amdgpu_device_indirect_wreg - write an indirect register address | |
918 | * | |
919 | * @adev: amdgpu_device pointer | |
1bba3683 HZ |
920 | * @reg_addr: indirect register offset |
921 | * @reg_data: indirect register data | |
922 | * | |
923 | */ | |
924 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
1bba3683 HZ |
925 | u32 reg_addr, u32 reg_data) |
926 | { | |
65ba96e9 | 927 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
928 | void __iomem *pcie_index_offset; |
929 | void __iomem *pcie_data_offset; | |
930 | ||
65ba96e9 HZ |
931 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); |
932 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
933 | ||
1bba3683 HZ |
934 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
935 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
936 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
937 | ||
938 | writel(reg_addr, pcie_index_offset); | |
939 | readl(pcie_index_offset); | |
940 | writel(reg_data, pcie_data_offset); | |
941 | readl(pcie_data_offset); | |
942 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
943 | } | |
944 | ||
0c552ed3 LM |
945 | void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, |
946 | u64 reg_addr, u32 reg_data) | |
947 | { | |
948 | unsigned long flags, pcie_index, pcie_index_hi, pcie_data; | |
949 | void __iomem *pcie_index_offset; | |
950 | void __iomem *pcie_index_hi_offset; | |
951 | void __iomem *pcie_data_offset; | |
952 | ||
953 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
954 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
d57e24aa | 955 | if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) |
0c552ed3 LM |
956 | pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); |
957 | else | |
958 | pcie_index_hi = 0; | |
959 | ||
960 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
961 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
962 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
963 | if (pcie_index_hi != 0) | |
964 | pcie_index_hi_offset = (void __iomem *)adev->rmmio + | |
965 | pcie_index_hi * 4; | |
966 | ||
967 | writel(reg_addr, pcie_index_offset); | |
968 | readl(pcie_index_offset); | |
969 | if (pcie_index_hi != 0) { | |
970 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
971 | readl(pcie_index_hi_offset); | |
972 | } | |
973 | writel(reg_data, pcie_data_offset); | |
974 | readl(pcie_data_offset); | |
975 | ||
976 | /* clear the high bits */ | |
977 | if (pcie_index_hi != 0) { | |
978 | writel(0, pcie_index_hi_offset); | |
979 | readl(pcie_index_hi_offset); | |
980 | } | |
981 | ||
982 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
983 | } | |
984 | ||
1bba3683 HZ |
985 | /** |
986 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
987 | * | |
988 | * @adev: amdgpu_device pointer | |
1bba3683 HZ |
989 | * @reg_addr: indirect register offset |
990 | * @reg_data: indirect register data | |
991 | * | |
992 | */ | |
993 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
1bba3683 HZ |
994 | u32 reg_addr, u64 reg_data) |
995 | { | |
65ba96e9 | 996 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
997 | void __iomem *pcie_index_offset; |
998 | void __iomem *pcie_data_offset; | |
999 | ||
65ba96e9 HZ |
1000 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); |
1001 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
1002 | ||
1bba3683 HZ |
1003 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
1004 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
1005 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
1006 | ||
1007 | /* write low 32 bits */ | |
1008 | writel(reg_addr, pcie_index_offset); | |
1009 | readl(pcie_index_offset); | |
1010 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
1011 | readl(pcie_data_offset); | |
1012 | /* write high 32 bits */ | |
1013 | writel(reg_addr + 4, pcie_index_offset); | |
1014 | readl(pcie_index_offset); | |
1015 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
1016 | readl(pcie_data_offset); | |
1017 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
1018 | } | |
1019 | ||
a76b2870 CL |
1020 | void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, |
1021 | u64 reg_addr, u64 reg_data) | |
1022 | { | |
1023 | unsigned long flags, pcie_index, pcie_data; | |
1024 | unsigned long pcie_index_hi = 0; | |
1025 | void __iomem *pcie_index_offset; | |
1026 | void __iomem *pcie_index_hi_offset; | |
1027 | void __iomem *pcie_data_offset; | |
1028 | ||
1029 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
1030 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
1031 | if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) | |
1032 | pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); | |
1033 | ||
1034 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
1035 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
1036 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
1037 | if (pcie_index_hi != 0) | |
1038 | pcie_index_hi_offset = (void __iomem *)adev->rmmio + | |
1039 | pcie_index_hi * 4; | |
1040 | ||
1041 | /* write low 32 bits */ | |
1042 | writel(reg_addr, pcie_index_offset); | |
1043 | readl(pcie_index_offset); | |
1044 | if (pcie_index_hi != 0) { | |
1045 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
1046 | readl(pcie_index_hi_offset); | |
1047 | } | |
1048 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
1049 | readl(pcie_data_offset); | |
1050 | /* write high 32 bits */ | |
1051 | writel(reg_addr + 4, pcie_index_offset); | |
1052 | readl(pcie_index_offset); | |
1053 | if (pcie_index_hi != 0) { | |
1054 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
1055 | readl(pcie_index_hi_offset); | |
1056 | } | |
1057 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
1058 | readl(pcie_data_offset); | |
1059 | ||
1060 | /* clear the high bits */ | |
1061 | if (pcie_index_hi != 0) { | |
1062 | writel(0, pcie_index_hi_offset); | |
1063 | readl(pcie_index_hi_offset); | |
1064 | } | |
1065 | ||
1066 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
1067 | } | |
1068 | ||
dabc114e HZ |
1069 | /** |
1070 | * amdgpu_device_get_rev_id - query device rev_id | |
1071 | * | |
1072 | * @adev: amdgpu_device pointer | |
1073 | * | |
1074 | * Return device rev_id | |
1075 | */ | |
1076 | u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) | |
1077 | { | |
1078 | return adev->nbio.funcs->get_rev_id(adev); | |
1079 | } | |
1080 | ||
d38ceaf9 AD |
1081 | /** |
1082 | * amdgpu_invalid_rreg - dummy reg read function | |
1083 | * | |
982a820b | 1084 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
1085 | * @reg: offset of register |
1086 | * | |
1087 | * Dummy register read function. Used for register blocks | |
1088 | * that certain asics don't have (all asics). | |
1089 | * Returns the value in the register. | |
1090 | */ | |
1091 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
1092 | { | |
1093 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
1094 | BUG(); | |
1095 | return 0; | |
1096 | } | |
1097 | ||
0c552ed3 LM |
1098 | static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg) |
1099 | { | |
1100 | DRM_ERROR("Invalid callback to read register 0x%llX\n", reg); | |
1101 | BUG(); | |
1102 | return 0; | |
1103 | } | |
1104 | ||
d38ceaf9 AD |
1105 | /** |
1106 | * amdgpu_invalid_wreg - dummy reg write function | |
1107 | * | |
982a820b | 1108 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
1109 | * @reg: offset of register |
1110 | * @v: value to write to the register | |
1111 | * | |
1112 | * Dummy register read function. Used for register blocks | |
1113 | * that certain asics don't have (all asics). | |
1114 | */ | |
1115 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
1116 | { | |
1117 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
1118 | reg, v); | |
1119 | BUG(); | |
1120 | } | |
1121 | ||
0c552ed3 LM |
1122 | static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v) |
1123 | { | |
1124 | DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n", | |
1125 | reg, v); | |
1126 | BUG(); | |
1127 | } | |
1128 | ||
4fa1c6a6 TZ |
1129 | /** |
1130 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
1131 | * | |
982a820b | 1132 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
1133 | * @reg: offset of register |
1134 | * | |
1135 | * Dummy register read function. Used for register blocks | |
1136 | * that certain asics don't have (all asics). | |
1137 | * Returns the value in the register. | |
1138 | */ | |
1139 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
1140 | { | |
1141 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
1142 | BUG(); | |
1143 | return 0; | |
1144 | } | |
1145 | ||
a76b2870 CL |
1146 | static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg) |
1147 | { | |
1148 | DRM_ERROR("Invalid callback to read register 0x%llX\n", reg); | |
1149 | BUG(); | |
1150 | return 0; | |
1151 | } | |
1152 | ||
4fa1c6a6 TZ |
1153 | /** |
1154 | * amdgpu_invalid_wreg64 - dummy reg write function | |
1155 | * | |
982a820b | 1156 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
1157 | * @reg: offset of register |
1158 | * @v: value to write to the register | |
1159 | * | |
1160 | * Dummy register read function. Used for register blocks | |
1161 | * that certain asics don't have (all asics). | |
1162 | */ | |
1163 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
1164 | { | |
1165 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
1166 | reg, v); | |
1167 | BUG(); | |
1168 | } | |
1169 | ||
a76b2870 CL |
1170 | static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v) |
1171 | { | |
1172 | DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n", | |
1173 | reg, v); | |
1174 | BUG(); | |
1175 | } | |
1176 | ||
d38ceaf9 AD |
1177 | /** |
1178 | * amdgpu_block_invalid_rreg - dummy reg read function | |
1179 | * | |
982a820b | 1180 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
1181 | * @block: offset of instance |
1182 | * @reg: offset of register | |
1183 | * | |
1184 | * Dummy register read function. Used for register blocks | |
1185 | * that certain asics don't have (all asics). | |
1186 | * Returns the value in the register. | |
1187 | */ | |
1188 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
1189 | uint32_t block, uint32_t reg) | |
1190 | { | |
1191 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
1192 | reg, block); | |
1193 | BUG(); | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | /** | |
1198 | * amdgpu_block_invalid_wreg - dummy reg write function | |
1199 | * | |
982a820b | 1200 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
1201 | * @block: offset of instance |
1202 | * @reg: offset of register | |
1203 | * @v: value to write to the register | |
1204 | * | |
1205 | * Dummy register read function. Used for register blocks | |
1206 | * that certain asics don't have (all asics). | |
1207 | */ | |
1208 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
1209 | uint32_t block, | |
1210 | uint32_t reg, uint32_t v) | |
1211 | { | |
1212 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
1213 | reg, block, v); | |
1214 | BUG(); | |
1215 | } | |
1216 | ||
4d2997ab AD |
1217 | /** |
1218 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
1219 | * | |
982a820b | 1220 | * @adev: amdgpu_device pointer |
4d2997ab AD |
1221 | * |
1222 | * Does any asic specific work and then calls atom asic init. | |
1223 | */ | |
1224 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
1225 | { | |
7656168a LL |
1226 | int ret; |
1227 | ||
4d2997ab AD |
1228 | amdgpu_asic_pre_asic_init(adev); |
1229 | ||
4e8303cf LL |
1230 | if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || |
1231 | amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { | |
7656168a LL |
1232 | amdgpu_psp_wait_for_bootloader(adev); |
1233 | ret = amdgpu_atomfirmware_asic_init(adev, true); | |
1234 | return ret; | |
1235 | } else { | |
85d1bcc6 | 1236 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); |
7656168a LL |
1237 | } |
1238 | ||
1239 | return 0; | |
4d2997ab AD |
1240 | } |
1241 | ||
e3ecdffa | 1242 | /** |
7ccfd79f | 1243 | * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page |
e3ecdffa | 1244 | * |
982a820b | 1245 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
1246 | * |
1247 | * Allocates a scratch page of VRAM for use by various things in the | |
1248 | * driver. | |
1249 | */ | |
7ccfd79f | 1250 | static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 1251 | { |
7ccfd79f CK |
1252 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, |
1253 | AMDGPU_GEM_DOMAIN_VRAM | | |
1254 | AMDGPU_GEM_DOMAIN_GTT, | |
1255 | &adev->mem_scratch.robj, | |
1256 | &adev->mem_scratch.gpu_addr, | |
1257 | (void **)&adev->mem_scratch.ptr); | |
d38ceaf9 AD |
1258 | } |
1259 | ||
e3ecdffa | 1260 | /** |
7ccfd79f | 1261 | * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page |
e3ecdffa | 1262 | * |
982a820b | 1263 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
1264 | * |
1265 | * Frees the VRAM scratch page. | |
1266 | */ | |
7ccfd79f | 1267 | static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 1268 | { |
7ccfd79f | 1269 | amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
1270 | } |
1271 | ||
1272 | /** | |
9c3f2b54 | 1273 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
1274 | * |
1275 | * @adev: amdgpu_device pointer | |
1276 | * @registers: pointer to the register array | |
1277 | * @array_size: size of the register array | |
1278 | * | |
b8920e1e | 1279 | * Programs an array or registers with and or masks. |
d38ceaf9 AD |
1280 | * This is a helper for setting golden registers. |
1281 | */ | |
9c3f2b54 AD |
1282 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
1283 | const u32 *registers, | |
1284 | const u32 array_size) | |
d38ceaf9 AD |
1285 | { |
1286 | u32 tmp, reg, and_mask, or_mask; | |
1287 | int i; | |
1288 | ||
1289 | if (array_size % 3) | |
1290 | return; | |
1291 | ||
47fc644f | 1292 | for (i = 0; i < array_size; i += 3) { |
d38ceaf9 AD |
1293 | reg = registers[i + 0]; |
1294 | and_mask = registers[i + 1]; | |
1295 | or_mask = registers[i + 2]; | |
1296 | ||
1297 | if (and_mask == 0xffffffff) { | |
1298 | tmp = or_mask; | |
1299 | } else { | |
1300 | tmp = RREG32(reg); | |
1301 | tmp &= ~and_mask; | |
e0d07657 HZ |
1302 | if (adev->family >= AMDGPU_FAMILY_AI) |
1303 | tmp |= (or_mask & and_mask); | |
1304 | else | |
1305 | tmp |= or_mask; | |
d38ceaf9 AD |
1306 | } |
1307 | WREG32(reg, tmp); | |
1308 | } | |
1309 | } | |
1310 | ||
e3ecdffa AD |
1311 | /** |
1312 | * amdgpu_device_pci_config_reset - reset the GPU | |
1313 | * | |
1314 | * @adev: amdgpu_device pointer | |
1315 | * | |
1316 | * Resets the GPU using the pci config reset sequence. | |
1317 | * Only applicable to asics prior to vega10. | |
1318 | */ | |
8111c387 | 1319 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
1320 | { |
1321 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
1322 | } | |
1323 | ||
af484df8 AD |
1324 | /** |
1325 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
1326 | * | |
1327 | * @adev: amdgpu_device pointer | |
1328 | * | |
1329 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
1330 | */ | |
1331 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
1332 | { | |
1333 | return pci_reset_function(adev->pdev); | |
1334 | } | |
1335 | ||
d38ceaf9 | 1336 | /* |
06ec9070 | 1337 | * amdgpu_device_wb_*() |
455a7bc2 | 1338 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1339 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1340 | */ |
1341 | ||
1342 | /** | |
06ec9070 | 1343 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1344 | * |
1345 | * @adev: amdgpu_device pointer | |
1346 | * | |
1347 | * Disables Writeback and frees the Writeback memory (all asics). | |
1348 | * Used at driver shutdown. | |
1349 | */ | |
06ec9070 | 1350 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1351 | { |
1352 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1353 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1354 | &adev->wb.gpu_addr, | |
1355 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1356 | adev->wb.wb_obj = NULL; |
1357 | } | |
1358 | } | |
1359 | ||
1360 | /** | |
03f2abb0 | 1361 | * amdgpu_device_wb_init - Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1362 | * |
1363 | * @adev: amdgpu_device pointer | |
1364 | * | |
455a7bc2 | 1365 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1366 | * Used at driver startup. |
1367 | * Returns 0 on success or an -error on failure. | |
1368 | */ | |
06ec9070 | 1369 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1370 | { |
1371 | int r; | |
1372 | ||
1373 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1374 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1375 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1376 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1377 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1378 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1379 | if (r) { |
1380 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1381 | return r; | |
1382 | } | |
d38ceaf9 AD |
1383 | |
1384 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1385 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1386 | ||
1387 | /* clear wb memory */ | |
73469585 | 1388 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1389 | } |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | /** | |
131b4b36 | 1395 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1396 | * |
1397 | * @adev: amdgpu_device pointer | |
1398 | * @wb: wb index | |
1399 | * | |
1400 | * Allocate a wb slot for use by the driver (all asics). | |
1401 | * Returns 0 on success or -EINVAL on failure. | |
1402 | */ | |
131b4b36 | 1403 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1404 | { |
1405 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1406 | |
97407b63 | 1407 | if (offset < adev->wb.num_wb) { |
7014285a | 1408 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1409 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1410 | return 0; |
1411 | } else { | |
1412 | return -EINVAL; | |
1413 | } | |
1414 | } | |
1415 | ||
d38ceaf9 | 1416 | /** |
131b4b36 | 1417 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1418 | * |
1419 | * @adev: amdgpu_device pointer | |
1420 | * @wb: wb index | |
1421 | * | |
1422 | * Free a wb slot allocated for use by the driver (all asics) | |
1423 | */ | |
131b4b36 | 1424 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1425 | { |
73469585 | 1426 | wb >>= 3; |
d38ceaf9 | 1427 | if (wb < adev->wb.num_wb) |
73469585 | 1428 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1429 | } |
1430 | ||
d6895ad3 CK |
1431 | /** |
1432 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1433 | * | |
1434 | * @adev: amdgpu_device pointer | |
1435 | * | |
1436 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1437 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1438 | * driver loading by returning -ENODEV. | |
1439 | */ | |
1440 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1441 | { | |
453f617a | 1442 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1443 | struct pci_bus *root; |
1444 | struct resource *res; | |
b8920e1e | 1445 | unsigned int i; |
d6895ad3 CK |
1446 | u16 cmd; |
1447 | int r; | |
1448 | ||
822130b5 AB |
1449 | if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) |
1450 | return 0; | |
1451 | ||
0c03b912 | 1452 | /* Bypass for VF */ |
1453 | if (amdgpu_sriov_vf(adev)) | |
1454 | return 0; | |
1455 | ||
e372baeb MJ |
1456 | /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */ |
1457 | if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR)) | |
1458 | DRM_WARN("System can't access extended configuration space,please check!!\n"); | |
1459 | ||
b7221f2b AD |
1460 | /* skip if the bios has already enabled large BAR */ |
1461 | if (adev->gmc.real_vram_size && | |
1462 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1463 | return 0; | |
1464 | ||
31b8adab CK |
1465 | /* Check if the root BUS has 64bit memory resources */ |
1466 | root = adev->pdev->bus; | |
1467 | while (root->parent) | |
1468 | root = root->parent; | |
1469 | ||
1470 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1471 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1472 | res->start > 0x100000000ull) |
1473 | break; | |
1474 | } | |
1475 | ||
1476 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1477 | if (!res) | |
1478 | return 0; | |
1479 | ||
453f617a ND |
1480 | /* Limit the BAR size to what is available */ |
1481 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1482 | rbar_size); | |
1483 | ||
d6895ad3 CK |
1484 | /* Disable memory decoding while we change the BAR addresses and size */ |
1485 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1486 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1487 | cmd & ~PCI_COMMAND_MEMORY); | |
1488 | ||
1489 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
43c064db | 1490 | amdgpu_doorbell_fini(adev); |
d6895ad3 CK |
1491 | if (adev->asic_type >= CHIP_BONAIRE) |
1492 | pci_release_resource(adev->pdev, 2); | |
1493 | ||
1494 | pci_release_resource(adev->pdev, 0); | |
1495 | ||
1496 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1497 | if (r == -ENOSPC) | |
1498 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1499 | else if (r && r != -ENOTSUPP) | |
1500 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1501 | ||
1502 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1503 | ||
1504 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1505 | * using the device. | |
1506 | */ | |
43c064db | 1507 | r = amdgpu_doorbell_init(adev); |
d6895ad3 CK |
1508 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1509 | return -ENODEV; | |
1510 | ||
1511 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1512 | ||
1513 | return 0; | |
1514 | } | |
a05502e5 | 1515 | |
9535a86a SZ |
1516 | static bool amdgpu_device_read_bios(struct amdgpu_device *adev) |
1517 | { | |
b8920e1e | 1518 | if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) |
9535a86a | 1519 | return false; |
9535a86a SZ |
1520 | |
1521 | return true; | |
1522 | } | |
1523 | ||
d38ceaf9 AD |
1524 | /* |
1525 | * GPU helpers function. | |
1526 | */ | |
1527 | /** | |
39c640c0 | 1528 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1529 | * |
1530 | * @adev: amdgpu_device pointer | |
1531 | * | |
c836fec5 JQ |
1532 | * Check if the asic has been initialized (all asics) at driver startup |
1533 | * or post is needed if hw reset is performed. | |
1534 | * Returns true if need or false if not. | |
d38ceaf9 | 1535 | */ |
39c640c0 | 1536 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1537 | { |
1538 | uint32_t reg; | |
1539 | ||
bec86378 ML |
1540 | if (amdgpu_sriov_vf(adev)) |
1541 | return false; | |
1542 | ||
9535a86a SZ |
1543 | if (!amdgpu_device_read_bios(adev)) |
1544 | return false; | |
1545 | ||
bec86378 | 1546 | if (amdgpu_passthrough(adev)) { |
1da2c326 ML |
1547 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1548 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1549 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1550 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1551 | */ |
1552 | if (adev->asic_type == CHIP_FIJI) { | |
1553 | int err; | |
1554 | uint32_t fw_ver; | |
b8920e1e | 1555 | |
bec86378 ML |
1556 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); |
1557 | /* force vPost if error occured */ | |
1558 | if (err) | |
1559 | return true; | |
1560 | ||
1561 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
8a44fdd3 | 1562 | release_firmware(adev->pm.fw); |
1da2c326 ML |
1563 | if (fw_ver < 0x00160e00) |
1564 | return true; | |
bec86378 | 1565 | } |
bec86378 | 1566 | } |
91fe77eb | 1567 | |
e3c1b071 | 1568 | /* Don't post if we need to reset whole hive on init */ |
1569 | if (adev->gmc.xgmi.pending_reset) | |
1570 | return false; | |
1571 | ||
91fe77eb | 1572 | if (adev->has_hw_reset) { |
1573 | adev->has_hw_reset = false; | |
1574 | return true; | |
1575 | } | |
1576 | ||
1577 | /* bios scratch used on CIK+ */ | |
1578 | if (adev->asic_type >= CHIP_BONAIRE) | |
1579 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1580 | ||
1581 | /* check MEM_SIZE for older asics */ | |
1582 | reg = amdgpu_asic_get_config_memsize(adev); | |
1583 | ||
1584 | if ((reg != 0) && (reg != 0xffffffff)) | |
1585 | return false; | |
1586 | ||
1587 | return true; | |
bec86378 ML |
1588 | } |
1589 | ||
5d1eb4c4 | 1590 | /* |
bb0f8429 ML |
1591 | * Check whether seamless boot is supported. |
1592 | * | |
7f4ce7b5 ML |
1593 | * So far we only support seamless boot on DCE 3.0 or later. |
1594 | * If users report that it works on older ASICS as well, we may | |
1595 | * loosen this. | |
bb0f8429 ML |
1596 | */ |
1597 | bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) | |
1598 | { | |
5dc270d3 ML |
1599 | switch (amdgpu_seamless) { |
1600 | case -1: | |
1601 | break; | |
1602 | case 1: | |
1603 | return true; | |
1604 | case 0: | |
1605 | return false; | |
1606 | default: | |
1607 | DRM_ERROR("Invalid value for amdgpu.seamless: %d\n", | |
1608 | amdgpu_seamless); | |
1609 | return false; | |
1610 | } | |
1611 | ||
3657a1d5 ML |
1612 | if (!(adev->flags & AMD_IS_APU)) |
1613 | return false; | |
1614 | ||
5dc270d3 ML |
1615 | if (adev->mman.keep_stolen_vga_memory) |
1616 | return false; | |
1617 | ||
ed342a2e | 1618 | return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0); |
bb0f8429 ML |
1619 | } |
1620 | ||
5d1eb4c4 | 1621 | /* |
2757a848 ML |
1622 | * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids |
1623 | * don't support dynamic speed switching. Until we have confirmation from Intel | |
1624 | * that a specific host supports it, it's safer that we keep it disabled for all. | |
5d1eb4c4 ML |
1625 | * |
1626 | * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/ | |
1627 | * https://gitlab.freedesktop.org/drm/amd/-/issues/2663 | |
1628 | */ | |
d9b3a066 | 1629 | static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) |
5d1eb4c4 ML |
1630 | { |
1631 | #if IS_ENABLED(CONFIG_X86) | |
1632 | struct cpuinfo_x86 *c = &cpu_data(0); | |
1633 | ||
d9b3a066 ML |
1634 | /* eGPU change speeds based on USB4 fabric conditions */ |
1635 | if (dev_is_removable(adev->dev)) | |
1636 | return true; | |
1637 | ||
5d1eb4c4 ML |
1638 | if (c->x86_vendor == X86_VENDOR_INTEL) |
1639 | return false; | |
1640 | #endif | |
1641 | return true; | |
1642 | } | |
1643 | ||
0ab5d711 ML |
1644 | /** |
1645 | * amdgpu_device_should_use_aspm - check if the device should program ASPM | |
1646 | * | |
1647 | * @adev: amdgpu_device pointer | |
1648 | * | |
1649 | * Confirm whether the module parameter and pcie bridge agree that ASPM should | |
1650 | * be set for this device. | |
1651 | * | |
1652 | * Returns true if it should be used or false if not. | |
1653 | */ | |
1654 | bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) | |
1655 | { | |
1656 | switch (amdgpu_aspm) { | |
1657 | case -1: | |
1658 | break; | |
1659 | case 0: | |
1660 | return false; | |
1661 | case 1: | |
1662 | return true; | |
1663 | default: | |
1664 | return false; | |
1665 | } | |
1a6513de ML |
1666 | if (adev->flags & AMD_IS_APU) |
1667 | return false; | |
2757a848 ML |
1668 | if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) |
1669 | return false; | |
0ab5d711 ML |
1670 | return pcie_aspm_enabled(adev->pdev); |
1671 | } | |
1672 | ||
d38ceaf9 AD |
1673 | /* if we get transitioned to only one device, take VGA back */ |
1674 | /** | |
06ec9070 | 1675 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 | 1676 | * |
bf44e8ce | 1677 | * @pdev: PCI device pointer |
d38ceaf9 AD |
1678 | * @state: enable/disable vga decode |
1679 | * | |
1680 | * Enable/disable vga decode (all asics). | |
1681 | * Returns VGA resource flags. | |
1682 | */ | |
bf44e8ce CH |
1683 | static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, |
1684 | bool state) | |
d38ceaf9 | 1685 | { |
bf44e8ce | 1686 | struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); |
b8920e1e | 1687 | |
d38ceaf9 AD |
1688 | amdgpu_asic_set_vga_state(adev, state); |
1689 | if (state) | |
1690 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1691 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1692 | else | |
1693 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1694 | } | |
1695 | ||
e3ecdffa AD |
1696 | /** |
1697 | * amdgpu_device_check_block_size - validate the vm block size | |
1698 | * | |
1699 | * @adev: amdgpu_device pointer | |
1700 | * | |
1701 | * Validates the vm block size specified via module parameter. | |
1702 | * The vm block size defines number of bits in page table versus page directory, | |
1703 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1704 | * page table and the remaining bits are in the page directory. | |
1705 | */ | |
06ec9070 | 1706 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1707 | { |
1708 | /* defines number of bits in page table versus page directory, | |
1709 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
b8920e1e SS |
1710 | * page table and the remaining bits are in the page directory |
1711 | */ | |
bab4fee7 JZ |
1712 | if (amdgpu_vm_block_size == -1) |
1713 | return; | |
a1adf8be | 1714 | |
bab4fee7 | 1715 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1716 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1717 | amdgpu_vm_block_size); | |
97489129 | 1718 | amdgpu_vm_block_size = -1; |
a1adf8be | 1719 | } |
a1adf8be CZ |
1720 | } |
1721 | ||
e3ecdffa AD |
1722 | /** |
1723 | * amdgpu_device_check_vm_size - validate the vm size | |
1724 | * | |
1725 | * @adev: amdgpu_device pointer | |
1726 | * | |
1727 | * Validates the vm size in GB specified via module parameter. | |
1728 | * The VM size is the size of the GPU virtual memory space in GB. | |
1729 | */ | |
06ec9070 | 1730 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1731 | { |
64dab074 AD |
1732 | /* no need to check the default value */ |
1733 | if (amdgpu_vm_size == -1) | |
1734 | return; | |
1735 | ||
83ca145d ZJ |
1736 | if (amdgpu_vm_size < 1) { |
1737 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1738 | amdgpu_vm_size); | |
f3368128 | 1739 | amdgpu_vm_size = -1; |
83ca145d | 1740 | } |
83ca145d ZJ |
1741 | } |
1742 | ||
7951e376 RZ |
1743 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1744 | { | |
1745 | struct sysinfo si; | |
a9d4fe2f | 1746 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1747 | uint64_t total_memory; |
1748 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1749 | uint64_t dram_size_three_GB = 0xB8000000; | |
1750 | ||
1751 | if (amdgpu_smu_memory_pool_size == 0) | |
1752 | return; | |
1753 | ||
1754 | if (!is_os_64) { | |
1755 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1756 | goto def_value; | |
1757 | } | |
1758 | si_meminfo(&si); | |
1759 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1760 | ||
1761 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1762 | (amdgpu_smu_memory_pool_size == 2)) { | |
1763 | if (total_memory < dram_size_three_GB) | |
1764 | goto def_value1; | |
1765 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1766 | (amdgpu_smu_memory_pool_size == 8)) { | |
1767 | if (total_memory < dram_size_seven_GB) | |
1768 | goto def_value1; | |
1769 | } else { | |
1770 | DRM_WARN("Smu memory pool size not supported\n"); | |
1771 | goto def_value; | |
1772 | } | |
1773 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1774 | ||
1775 | return; | |
1776 | ||
1777 | def_value1: | |
1778 | DRM_WARN("No enough system memory\n"); | |
1779 | def_value: | |
1780 | adev->pm.smu_prv_buffer_size = 0; | |
1781 | } | |
1782 | ||
9f6a7857 HR |
1783 | static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) |
1784 | { | |
1785 | if (!(adev->flags & AMD_IS_APU) || | |
1786 | adev->asic_type < CHIP_RAVEN) | |
1787 | return 0; | |
1788 | ||
1789 | switch (adev->asic_type) { | |
1790 | case CHIP_RAVEN: | |
1791 | if (adev->pdev->device == 0x15dd) | |
1792 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1793 | if (adev->pdev->device == 0x15d8) | |
1794 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
1795 | break; | |
1796 | case CHIP_RENOIR: | |
1797 | if ((adev->pdev->device == 0x1636) || | |
1798 | (adev->pdev->device == 0x164c)) | |
1799 | adev->apu_flags |= AMD_APU_IS_RENOIR; | |
1800 | else | |
1801 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1802 | break; | |
1803 | case CHIP_VANGOGH: | |
1804 | adev->apu_flags |= AMD_APU_IS_VANGOGH; | |
1805 | break; | |
1806 | case CHIP_YELLOW_CARP: | |
1807 | break; | |
d0f56dc2 | 1808 | case CHIP_CYAN_SKILLFISH: |
dfcc3e8c AD |
1809 | if ((adev->pdev->device == 0x13FE) || |
1810 | (adev->pdev->device == 0x143F)) | |
d0f56dc2 TZ |
1811 | adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2; |
1812 | break; | |
9f6a7857 | 1813 | default: |
4eaf21b7 | 1814 | break; |
9f6a7857 HR |
1815 | } |
1816 | ||
1817 | return 0; | |
1818 | } | |
1819 | ||
d38ceaf9 | 1820 | /** |
06ec9070 | 1821 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1822 | * |
1823 | * @adev: amdgpu_device pointer | |
1824 | * | |
1825 | * Validates certain module parameters and updates | |
1826 | * the associated values used by the driver (all asics). | |
1827 | */ | |
912dfc84 | 1828 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1829 | { |
5b011235 CZ |
1830 | if (amdgpu_sched_jobs < 4) { |
1831 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1832 | amdgpu_sched_jobs); | |
1833 | amdgpu_sched_jobs = 4; | |
47fc644f | 1834 | } else if (!is_power_of_2(amdgpu_sched_jobs)) { |
5b011235 CZ |
1835 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1836 | amdgpu_sched_jobs); | |
1837 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1838 | } | |
d38ceaf9 | 1839 | |
83e74db6 | 1840 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1841 | /* gart size must be greater or equal to 32M */ |
1842 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1843 | amdgpu_gart_size); | |
83e74db6 | 1844 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1845 | } |
1846 | ||
36d38372 | 1847 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1848 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1849 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1850 | amdgpu_gtt_size); | |
1851 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1852 | } |
1853 | ||
d07f14be RH |
1854 | /* valid range is between 4 and 9 inclusive */ |
1855 | if (amdgpu_vm_fragment_size != -1 && | |
1856 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1857 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1858 | amdgpu_vm_fragment_size = -1; | |
1859 | } | |
1860 | ||
5d5bd5e3 KW |
1861 | if (amdgpu_sched_hw_submission < 2) { |
1862 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1863 | amdgpu_sched_hw_submission); | |
1864 | amdgpu_sched_hw_submission = 2; | |
1865 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1866 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1867 | amdgpu_sched_hw_submission); | |
1868 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1869 | } | |
1870 | ||
2656fd23 AG |
1871 | if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) { |
1872 | dev_warn(adev->dev, "invalid option for reset method, reverting to default\n"); | |
1873 | amdgpu_reset_method = -1; | |
1874 | } | |
1875 | ||
7951e376 RZ |
1876 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1877 | ||
06ec9070 | 1878 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1879 | |
06ec9070 | 1880 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1881 | |
19aede77 | 1882 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1883 | |
e3c00faa | 1884 | return 0; |
d38ceaf9 AD |
1885 | } |
1886 | ||
1887 | /** | |
1888 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1889 | * | |
1890 | * @pdev: pci dev pointer | |
1694467b | 1891 | * @state: vga_switcheroo state |
d38ceaf9 | 1892 | * |
12024b17 | 1893 | * Callback for the switcheroo driver. Suspends or resumes |
d38ceaf9 AD |
1894 | * the asics before or after it is powered up using ACPI methods. |
1895 | */ | |
8aba21b7 LT |
1896 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1897 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1898 | { |
1899 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1900 | int r; |
d38ceaf9 | 1901 | |
b98c6299 | 1902 | if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1903 | return; |
1904 | ||
1905 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1906 | pr_info("switched on\n"); |
d38ceaf9 AD |
1907 | /* don't suspend or resume card normally */ |
1908 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1909 | ||
8f66090b TZ |
1910 | pci_set_power_state(pdev, PCI_D0); |
1911 | amdgpu_device_load_pci_state(pdev); | |
1912 | r = pci_enable_device(pdev); | |
de185019 AD |
1913 | if (r) |
1914 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1915 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1916 | |
d38ceaf9 | 1917 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1918 | } else { |
dd4fa6c1 | 1919 | pr_info("switched off\n"); |
d38ceaf9 | 1920 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
5095d541 | 1921 | amdgpu_device_prepare(dev); |
de185019 | 1922 | amdgpu_device_suspend(dev, true); |
8f66090b | 1923 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1924 | /* Shut down the device */ |
8f66090b TZ |
1925 | pci_disable_device(pdev); |
1926 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1927 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1928 | } | |
1929 | } | |
1930 | ||
1931 | /** | |
1932 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1933 | * | |
1934 | * @pdev: pci dev pointer | |
1935 | * | |
1936 | * Callback for the switcheroo driver. Check of the switcheroo | |
1937 | * state can be changed. | |
1938 | * Returns true if the state can be changed, false if not. | |
1939 | */ | |
1940 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1941 | { | |
1942 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1943 | ||
b8920e1e | 1944 | /* |
d38ceaf9 AD |
1945 | * FIXME: open_count is protected by drm_global_mutex but that would lead to |
1946 | * locking inversion with the driver load path. And the access here is | |
1947 | * completely racy anyway. So don't bother with locking for now. | |
1948 | */ | |
7e13ad89 | 1949 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1950 | } |
1951 | ||
1952 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1953 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1954 | .reprobe = NULL, | |
1955 | .can_switch = amdgpu_switcheroo_can_switch, | |
1956 | }; | |
1957 | ||
e3ecdffa AD |
1958 | /** |
1959 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1960 | * | |
87e3f136 | 1961 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1962 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1963 | * @state: clockgating state (gate or ungate) | |
1964 | * | |
1965 | * Sets the requested clockgating state for all instances of | |
1966 | * the hardware IP specified. | |
1967 | * Returns the error code from the last instance. | |
1968 | */ | |
43fa561f | 1969 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1970 | enum amd_ip_block_type block_type, |
1971 | enum amd_clockgating_state state) | |
d38ceaf9 | 1972 | { |
43fa561f | 1973 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1974 | int i, r = 0; |
1975 | ||
1976 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1977 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1978 | continue; |
c722865a RZ |
1979 | if (adev->ip_blocks[i].version->type != block_type) |
1980 | continue; | |
1981 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1982 | continue; | |
1983 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1984 | (void *)adev, state); | |
1985 | if (r) | |
1986 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1987 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1988 | } |
1989 | return r; | |
1990 | } | |
1991 | ||
e3ecdffa AD |
1992 | /** |
1993 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1994 | * | |
87e3f136 | 1995 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1996 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1997 | * @state: powergating state (gate or ungate) | |
1998 | * | |
1999 | * Sets the requested powergating state for all instances of | |
2000 | * the hardware IP specified. | |
2001 | * Returns the error code from the last instance. | |
2002 | */ | |
43fa561f | 2003 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
2004 | enum amd_ip_block_type block_type, |
2005 | enum amd_powergating_state state) | |
d38ceaf9 | 2006 | { |
43fa561f | 2007 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
2008 | int i, r = 0; |
2009 | ||
2010 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2011 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 2012 | continue; |
c722865a RZ |
2013 | if (adev->ip_blocks[i].version->type != block_type) |
2014 | continue; | |
2015 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
2016 | continue; | |
2017 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
2018 | (void *)adev, state); | |
2019 | if (r) | |
2020 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
2021 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
2022 | } |
2023 | return r; | |
2024 | } | |
2025 | ||
e3ecdffa AD |
2026 | /** |
2027 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
2028 | * | |
2029 | * @adev: amdgpu_device pointer | |
2030 | * @flags: clockgating feature flags | |
2031 | * | |
2032 | * Walks the list of IPs on the device and updates the clockgating | |
2033 | * flags for each IP. | |
2034 | * Updates @flags with the feature flags for each hardware IP where | |
2035 | * clockgating is enabled. | |
2036 | */ | |
2990a1fc | 2037 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
25faeddc | 2038 | u64 *flags) |
6cb2d4e4 HR |
2039 | { |
2040 | int i; | |
2041 | ||
2042 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2043 | if (!adev->ip_blocks[i].status.valid) | |
2044 | continue; | |
2045 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
2046 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
2047 | } | |
2048 | } | |
2049 | ||
e3ecdffa AD |
2050 | /** |
2051 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
2052 | * | |
2053 | * @adev: amdgpu_device pointer | |
2054 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
2055 | * | |
2056 | * Waits for the request hardware IP to be idle. | |
2057 | * Returns 0 for success or a negative error code on failure. | |
2058 | */ | |
2990a1fc AD |
2059 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
2060 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
2061 | { |
2062 | int i, r; | |
2063 | ||
2064 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2065 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 2066 | continue; |
a1255107 AD |
2067 | if (adev->ip_blocks[i].version->type == block_type) { |
2068 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
2069 | if (r) |
2070 | return r; | |
2071 | break; | |
2072 | } | |
2073 | } | |
2074 | return 0; | |
2075 | ||
2076 | } | |
2077 | ||
e3ecdffa AD |
2078 | /** |
2079 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
2080 | * | |
2081 | * @adev: amdgpu_device pointer | |
2082 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
2083 | * | |
2084 | * Check if the hardware IP is idle or not. | |
2085 | * Returns true if it the IP is idle, false if not. | |
2086 | */ | |
2990a1fc AD |
2087 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
2088 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
2089 | { |
2090 | int i; | |
2091 | ||
2092 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2093 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 2094 | continue; |
a1255107 AD |
2095 | if (adev->ip_blocks[i].version->type == block_type) |
2096 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
2097 | } |
2098 | return true; | |
2099 | ||
2100 | } | |
2101 | ||
e3ecdffa AD |
2102 | /** |
2103 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
2104 | * | |
2105 | * @adev: amdgpu_device pointer | |
87e3f136 | 2106 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
2107 | * |
2108 | * Returns a pointer to the hardware IP block structure | |
2109 | * if it exists for the asic, otherwise NULL. | |
2110 | */ | |
2990a1fc AD |
2111 | struct amdgpu_ip_block * |
2112 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
2113 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
2114 | { |
2115 | int i; | |
2116 | ||
2117 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 2118 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
2119 | return &adev->ip_blocks[i]; |
2120 | ||
2121 | return NULL; | |
2122 | } | |
2123 | ||
2124 | /** | |
2990a1fc | 2125 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
2126 | * |
2127 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 2128 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
2129 | * @major: major version |
2130 | * @minor: minor version | |
2131 | * | |
2132 | * return 0 if equal or greater | |
2133 | * return 1 if smaller or the ip_block doesn't exist | |
2134 | */ | |
2990a1fc AD |
2135 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
2136 | enum amd_ip_block_type type, | |
2137 | u32 major, u32 minor) | |
d38ceaf9 | 2138 | { |
2990a1fc | 2139 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 2140 | |
a1255107 AD |
2141 | if (ip_block && ((ip_block->version->major > major) || |
2142 | ((ip_block->version->major == major) && | |
2143 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
2144 | return 0; |
2145 | ||
2146 | return 1; | |
2147 | } | |
2148 | ||
a1255107 | 2149 | /** |
2990a1fc | 2150 | * amdgpu_device_ip_block_add |
a1255107 AD |
2151 | * |
2152 | * @adev: amdgpu_device pointer | |
2153 | * @ip_block_version: pointer to the IP to add | |
2154 | * | |
2155 | * Adds the IP block driver information to the collection of IPs | |
2156 | * on the asic. | |
2157 | */ | |
2990a1fc AD |
2158 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
2159 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
2160 | { |
2161 | if (!ip_block_version) | |
2162 | return -EINVAL; | |
2163 | ||
7bd939d0 LG |
2164 | switch (ip_block_version->type) { |
2165 | case AMD_IP_BLOCK_TYPE_VCN: | |
2166 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) | |
2167 | return 0; | |
2168 | break; | |
2169 | case AMD_IP_BLOCK_TYPE_JPEG: | |
2170 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) | |
2171 | return 0; | |
2172 | break; | |
2173 | default: | |
2174 | break; | |
2175 | } | |
2176 | ||
e966a725 | 2177 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
2178 | ip_block_version->funcs->name); |
2179 | ||
a1255107 AD |
2180 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
2181 | ||
2182 | return 0; | |
2183 | } | |
2184 | ||
e3ecdffa AD |
2185 | /** |
2186 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
2187 | * | |
2188 | * @adev: amdgpu_device pointer | |
2189 | * | |
2190 | * Enabled the virtual display feature if the user has enabled it via | |
2191 | * the module parameter virtual_display. This feature provides a virtual | |
2192 | * display hardware on headless boards or in virtualized environments. | |
2193 | * This function parses and validates the configuration string specified by | |
2194 | * the user and configues the virtual display configuration (number of | |
2195 | * virtual connectors, crtcs, etc.) specified. | |
2196 | */ | |
483ef985 | 2197 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
2198 | { |
2199 | adev->enable_virtual_display = false; | |
2200 | ||
2201 | if (amdgpu_virtual_display) { | |
8f66090b | 2202 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 2203 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
2204 | |
2205 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
2206 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
2207 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
2208 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
2209 | if (!strcmp("all", pciaddname) |
2210 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
2211 | long num_crtc; |
2212 | int res = -1; | |
2213 | ||
9accf2fd | 2214 | adev->enable_virtual_display = true; |
0f66356d ED |
2215 | |
2216 | if (pciaddname_tmp) | |
2217 | res = kstrtol(pciaddname_tmp, 10, | |
2218 | &num_crtc); | |
2219 | ||
2220 | if (!res) { | |
2221 | if (num_crtc < 1) | |
2222 | num_crtc = 1; | |
2223 | if (num_crtc > 6) | |
2224 | num_crtc = 6; | |
2225 | adev->mode_info.num_crtc = num_crtc; | |
2226 | } else { | |
2227 | adev->mode_info.num_crtc = 1; | |
2228 | } | |
9accf2fd ED |
2229 | break; |
2230 | } | |
2231 | } | |
2232 | ||
0f66356d ED |
2233 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
2234 | amdgpu_virtual_display, pci_address_name, | |
2235 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
2236 | |
2237 | kfree(pciaddstr); | |
2238 | } | |
2239 | } | |
2240 | ||
25263da3 AD |
2241 | void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev) |
2242 | { | |
2243 | if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) { | |
2244 | adev->mode_info.num_crtc = 1; | |
2245 | adev->enable_virtual_display = true; | |
2246 | DRM_INFO("virtual_display:%d, num_crtc:%d\n", | |
2247 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
2248 | } | |
2249 | } | |
2250 | ||
e3ecdffa AD |
2251 | /** |
2252 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
2253 | * | |
2254 | * @adev: amdgpu_device pointer | |
2255 | * | |
2256 | * Parses the asic configuration parameters specified in the gpu info | |
2257 | * firmware and makes them availale to the driver for use in configuring | |
2258 | * the asic. | |
2259 | * Returns 0 on success, -EINVAL on failure. | |
2260 | */ | |
e2a75f88 AD |
2261 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
2262 | { | |
e2a75f88 | 2263 | const char *chip_name; |
c0a43457 | 2264 | char fw_name[40]; |
e2a75f88 AD |
2265 | int err; |
2266 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
2267 | ||
ab4fe3e1 HR |
2268 | adev->firmware.gpu_info_fw = NULL; |
2269 | ||
fb915c87 AD |
2270 | if (adev->mman.discovery_bin) |
2271 | return 0; | |
258620d0 | 2272 | |
e2a75f88 | 2273 | switch (adev->asic_type) { |
e2a75f88 AD |
2274 | default: |
2275 | return 0; | |
2276 | case CHIP_VEGA10: | |
2277 | chip_name = "vega10"; | |
2278 | break; | |
3f76dced AD |
2279 | case CHIP_VEGA12: |
2280 | chip_name = "vega12"; | |
2281 | break; | |
2d2e5e7e | 2282 | case CHIP_RAVEN: |
54f78a76 | 2283 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 2284 | chip_name = "raven2"; |
54f78a76 | 2285 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 2286 | chip_name = "picasso"; |
54c4d17e FX |
2287 | else |
2288 | chip_name = "raven"; | |
2d2e5e7e | 2289 | break; |
65e60f6e LM |
2290 | case CHIP_ARCTURUS: |
2291 | chip_name = "arcturus"; | |
2292 | break; | |
42b325e5 XY |
2293 | case CHIP_NAVI12: |
2294 | chip_name = "navi12"; | |
2295 | break; | |
e2a75f88 AD |
2296 | } |
2297 | ||
2298 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
b31d3063 | 2299 | err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name); |
e2a75f88 AD |
2300 | if (err) { |
2301 | dev_err(adev->dev, | |
b31d3063 | 2302 | "Failed to get gpu_info firmware \"%s\"\n", |
e2a75f88 AD |
2303 | fw_name); |
2304 | goto out; | |
2305 | } | |
2306 | ||
ab4fe3e1 | 2307 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
2308 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
2309 | ||
2310 | switch (hdr->version_major) { | |
2311 | case 1: | |
2312 | { | |
2313 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 2314 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
2315 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
2316 | ||
cc375d8c TY |
2317 | /* |
2318 | * Should be droped when DAL no longer needs it. | |
2319 | */ | |
2320 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
2321 | goto parse_soc_bounding_box; |
2322 | ||
b5ab16bf AD |
2323 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
2324 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
2325 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
2326 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 2327 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
2328 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
2329 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
2330 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
2331 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
2332 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 2333 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
2334 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
2335 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
2336 | adev->gfx.cu_info.max_waves_per_simd = |
2337 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
2338 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
2339 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
2340 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 2341 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
2342 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
2343 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
2344 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2345 | adev->gfx.config.num_sc_per_sh = | |
2346 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
2347 | adev->gfx.config.num_packer_per_sc = | |
2348 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
2349 | } | |
ec51d3fa XY |
2350 | |
2351 | parse_soc_bounding_box: | |
ec51d3fa XY |
2352 | /* |
2353 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 2354 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 2355 | */ |
48321c3d HW |
2356 | if (hdr->version_minor == 2) { |
2357 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
2358 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
2359 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2360 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
2361 | } | |
e2a75f88 AD |
2362 | break; |
2363 | } | |
2364 | default: | |
2365 | dev_err(adev->dev, | |
2366 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
2367 | err = -EINVAL; | |
2368 | goto out; | |
2369 | } | |
2370 | out: | |
e2a75f88 AD |
2371 | return err; |
2372 | } | |
2373 | ||
e3ecdffa AD |
2374 | /** |
2375 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
2376 | * | |
2377 | * @adev: amdgpu_device pointer | |
2378 | * | |
2379 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
2380 | * up each asic are discovered each IP's early_init callback is run. This | |
2381 | * is the first stage in initializing the asic. | |
2382 | * Returns 0 on success, negative error code on failure. | |
2383 | */ | |
06ec9070 | 2384 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 2385 | { |
901e2be2 | 2386 | struct pci_dev *parent; |
aaa36a97 | 2387 | int i, r; |
ced69502 | 2388 | bool total; |
d38ceaf9 | 2389 | |
483ef985 | 2390 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 2391 | |
00a979f3 | 2392 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 2393 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
2394 | if (r) |
2395 | return r; | |
00a979f3 WS |
2396 | } |
2397 | ||
d38ceaf9 | 2398 | switch (adev->asic_type) { |
33f34802 KW |
2399 | #ifdef CONFIG_DRM_AMDGPU_SI |
2400 | case CHIP_VERDE: | |
2401 | case CHIP_TAHITI: | |
2402 | case CHIP_PITCAIRN: | |
2403 | case CHIP_OLAND: | |
2404 | case CHIP_HAINAN: | |
295d0daf | 2405 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
2406 | r = si_set_ip_blocks(adev); |
2407 | if (r) | |
2408 | return r; | |
2409 | break; | |
2410 | #endif | |
a2e73f56 AD |
2411 | #ifdef CONFIG_DRM_AMDGPU_CIK |
2412 | case CHIP_BONAIRE: | |
2413 | case CHIP_HAWAII: | |
2414 | case CHIP_KAVERI: | |
2415 | case CHIP_KABINI: | |
2416 | case CHIP_MULLINS: | |
e1ad2d53 | 2417 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 2418 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
2419 | else |
2420 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
2421 | |
2422 | r = cik_set_ip_blocks(adev); | |
2423 | if (r) | |
2424 | return r; | |
2425 | break; | |
2426 | #endif | |
da87c30b AD |
2427 | case CHIP_TOPAZ: |
2428 | case CHIP_TONGA: | |
2429 | case CHIP_FIJI: | |
2430 | case CHIP_POLARIS10: | |
2431 | case CHIP_POLARIS11: | |
2432 | case CHIP_POLARIS12: | |
2433 | case CHIP_VEGAM: | |
2434 | case CHIP_CARRIZO: | |
2435 | case CHIP_STONEY: | |
2436 | if (adev->flags & AMD_IS_APU) | |
2437 | adev->family = AMDGPU_FAMILY_CZ; | |
2438 | else | |
2439 | adev->family = AMDGPU_FAMILY_VI; | |
2440 | ||
2441 | r = vi_set_ip_blocks(adev); | |
2442 | if (r) | |
2443 | return r; | |
2444 | break; | |
d38ceaf9 | 2445 | default: |
63352b7f AD |
2446 | r = amdgpu_discovery_set_ip_blocks(adev); |
2447 | if (r) | |
2448 | return r; | |
2449 | break; | |
d38ceaf9 AD |
2450 | } |
2451 | ||
901e2be2 AD |
2452 | if (amdgpu_has_atpx() && |
2453 | (amdgpu_is_atpx_hybrid() || | |
2454 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
2455 | ((adev->flags & AMD_IS_APU) == 0) && | |
7b1c6263 | 2456 | !dev_is_removable(&adev->pdev->dev)) |
901e2be2 AD |
2457 | adev->flags |= AMD_IS_PX; |
2458 | ||
85ac2021 | 2459 | if (!(adev->flags & AMD_IS_APU)) { |
c4c8955b | 2460 | parent = pcie_find_root_port(adev->pdev); |
85ac2021 AD |
2461 | adev->has_pr3 = parent ? pci_pr3_present(parent) : false; |
2462 | } | |
901e2be2 | 2463 | |
1884734a | 2464 | |
3b94fb10 | 2465 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2466 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2467 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2468 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2469 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
d9b3a066 | 2470 | if (!amdgpu_device_pcie_dynamic_switching_supported(adev)) |
fbf1035b | 2471 | adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK; |
00f54b97 | 2472 | |
ced69502 | 2473 | total = true; |
d38ceaf9 AD |
2474 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2475 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
0c451baf | 2476 | DRM_WARN("disabled ip block: %d <%s>\n", |
ed8cf00c | 2477 | i, adev->ip_blocks[i].version->funcs->name); |
a1255107 | 2478 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2479 | } else { |
a1255107 AD |
2480 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2481 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2482 | if (r == -ENOENT) { |
a1255107 | 2483 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2484 | } else if (r) { |
a1255107 AD |
2485 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2486 | adev->ip_blocks[i].version->funcs->name, r); | |
ced69502 | 2487 | total = false; |
2c1a2784 | 2488 | } else { |
a1255107 | 2489 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2490 | } |
974e6b64 | 2491 | } else { |
a1255107 | 2492 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2493 | } |
d38ceaf9 | 2494 | } |
21a249ca AD |
2495 | /* get the vbios after the asic_funcs are set up */ |
2496 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2497 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2498 | if (r) | |
2499 | return r; | |
2500 | ||
21a249ca | 2501 | /* Read BIOS */ |
9535a86a SZ |
2502 | if (amdgpu_device_read_bios(adev)) { |
2503 | if (!amdgpu_get_bios(adev)) | |
2504 | return -EINVAL; | |
21a249ca | 2505 | |
9535a86a SZ |
2506 | r = amdgpu_atombios_init(adev); |
2507 | if (r) { | |
2508 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2509 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2510 | return r; | |
2511 | } | |
21a249ca | 2512 | } |
77eabc6f PJZ |
2513 | |
2514 | /*get pf2vf msg info at it's earliest time*/ | |
2515 | if (amdgpu_sriov_vf(adev)) | |
2516 | amdgpu_virt_init_data_exchange(adev); | |
2517 | ||
21a249ca | 2518 | } |
d38ceaf9 | 2519 | } |
ced69502 ML |
2520 | if (!total) |
2521 | return -ENODEV; | |
d38ceaf9 | 2522 | |
00fa4035 | 2523 | amdgpu_amdkfd_device_probe(adev); |
395d1fb9 NH |
2524 | adev->cg_flags &= amdgpu_cg_mask; |
2525 | adev->pg_flags &= amdgpu_pg_mask; | |
2526 | ||
d38ceaf9 AD |
2527 | return 0; |
2528 | } | |
2529 | ||
0a4f2520 RZ |
2530 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2531 | { | |
2532 | int i, r; | |
2533 | ||
2534 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2535 | if (!adev->ip_blocks[i].status.sw) | |
2536 | continue; | |
2537 | if (adev->ip_blocks[i].status.hw) | |
2538 | continue; | |
2539 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2540 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2541 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2542 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2543 | if (r) { | |
2544 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2545 | adev->ip_blocks[i].version->funcs->name, r); | |
2546 | return r; | |
2547 | } | |
2548 | adev->ip_blocks[i].status.hw = true; | |
2549 | } | |
2550 | } | |
2551 | ||
2552 | return 0; | |
2553 | } | |
2554 | ||
2555 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2556 | { | |
2557 | int i, r; | |
2558 | ||
2559 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2560 | if (!adev->ip_blocks[i].status.sw) | |
2561 | continue; | |
2562 | if (adev->ip_blocks[i].status.hw) | |
2563 | continue; | |
2564 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2565 | if (r) { | |
2566 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2567 | adev->ip_blocks[i].version->funcs->name, r); | |
2568 | return r; | |
2569 | } | |
2570 | adev->ip_blocks[i].status.hw = true; | |
2571 | } | |
2572 | ||
2573 | return 0; | |
2574 | } | |
2575 | ||
7a3e0bb2 RZ |
2576 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2577 | { | |
2578 | int r = 0; | |
2579 | int i; | |
80f41f84 | 2580 | uint32_t smu_version; |
7a3e0bb2 RZ |
2581 | |
2582 | if (adev->asic_type >= CHIP_VEGA10) { | |
2583 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2584 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2585 | continue; | |
2586 | ||
e3c1b071 | 2587 | if (!adev->ip_blocks[i].status.sw) |
2588 | continue; | |
2589 | ||
482f0e53 ML |
2590 | /* no need to do the fw loading again if already done*/ |
2591 | if (adev->ip_blocks[i].status.hw == true) | |
2592 | break; | |
2593 | ||
53b3f8f4 | 2594 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2595 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2596 | if (r) { | |
2597 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2598 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2599 | return r; |
2600 | } | |
2601 | } else { | |
2602 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2603 | if (r) { | |
2604 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2605 | adev->ip_blocks[i].version->funcs->name, r); | |
2606 | return r; | |
7a3e0bb2 | 2607 | } |
7a3e0bb2 | 2608 | } |
482f0e53 ML |
2609 | |
2610 | adev->ip_blocks[i].status.hw = true; | |
2611 | break; | |
7a3e0bb2 RZ |
2612 | } |
2613 | } | |
482f0e53 | 2614 | |
8973d9ec ED |
2615 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2616 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2617 | |
80f41f84 | 2618 | return r; |
7a3e0bb2 RZ |
2619 | } |
2620 | ||
5fd8518d AG |
2621 | static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) |
2622 | { | |
2623 | long timeout; | |
2624 | int r, i; | |
2625 | ||
2626 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2627 | struct amdgpu_ring *ring = adev->rings[i]; | |
2628 | ||
2629 | /* No need to setup the GPU scheduler for rings that don't need it */ | |
2630 | if (!ring || ring->no_scheduler) | |
2631 | continue; | |
2632 | ||
2633 | switch (ring->funcs->type) { | |
2634 | case AMDGPU_RING_TYPE_GFX: | |
2635 | timeout = adev->gfx_timeout; | |
2636 | break; | |
2637 | case AMDGPU_RING_TYPE_COMPUTE: | |
2638 | timeout = adev->compute_timeout; | |
2639 | break; | |
2640 | case AMDGPU_RING_TYPE_SDMA: | |
2641 | timeout = adev->sdma_timeout; | |
2642 | break; | |
2643 | default: | |
2644 | timeout = adev->video_timeout; | |
2645 | break; | |
2646 | } | |
2647 | ||
a6149f03 | 2648 | r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL, |
56e44960 | 2649 | DRM_SCHED_PRIORITY_COUNT, |
11f25c84 | 2650 | ring->num_hw_submission, 0, |
8ab62eda JG |
2651 | timeout, adev->reset_domain->wq, |
2652 | ring->sched_score, ring->name, | |
2653 | adev->dev); | |
5fd8518d AG |
2654 | if (r) { |
2655 | DRM_ERROR("Failed to create scheduler on ring %s.\n", | |
2656 | ring->name); | |
2657 | return r; | |
2658 | } | |
037b98a2 AD |
2659 | r = amdgpu_uvd_entity_init(adev, ring); |
2660 | if (r) { | |
2661 | DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n", | |
2662 | ring->name); | |
2663 | return r; | |
2664 | } | |
2665 | r = amdgpu_vce_entity_init(adev, ring); | |
2666 | if (r) { | |
2667 | DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n", | |
2668 | ring->name); | |
2669 | return r; | |
2670 | } | |
5fd8518d AG |
2671 | } |
2672 | ||
d425c6f4 JZ |
2673 | amdgpu_xcp_update_partition_sched_list(adev); |
2674 | ||
5fd8518d AG |
2675 | return 0; |
2676 | } | |
2677 | ||
2678 | ||
e3ecdffa AD |
2679 | /** |
2680 | * amdgpu_device_ip_init - run init for hardware IPs | |
2681 | * | |
2682 | * @adev: amdgpu_device pointer | |
2683 | * | |
2684 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2685 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2686 | * are run. sw_init initializes the software state associated with each IP | |
2687 | * and hw_init initializes the hardware associated with each IP. | |
2688 | * Returns 0 on success, negative error code on failure. | |
2689 | */ | |
06ec9070 | 2690 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2691 | { |
2692 | int i, r; | |
2693 | ||
c030f2e4 | 2694 | r = amdgpu_ras_init(adev); |
2695 | if (r) | |
2696 | return r; | |
2697 | ||
d38ceaf9 | 2698 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2699 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2700 | continue; |
a1255107 | 2701 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2702 | if (r) { |
a1255107 AD |
2703 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2704 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2705 | goto init_failed; |
2c1a2784 | 2706 | } |
a1255107 | 2707 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2708 | |
c1c39032 AD |
2709 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { |
2710 | /* need to do common hw init early so everything is set up for gmc */ | |
2711 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); | |
2712 | if (r) { | |
2713 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
2714 | goto init_failed; | |
2715 | } | |
2716 | adev->ip_blocks[i].status.hw = true; | |
2717 | } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
2718 | /* need to do gmc hw init early so we can allocate gpu mem */ | |
892deb48 VS |
2719 | /* Try to reserve bad pages early */ |
2720 | if (amdgpu_sriov_vf(adev)) | |
2721 | amdgpu_virt_exchange_data(adev); | |
2722 | ||
7ccfd79f | 2723 | r = amdgpu_device_mem_scratch_init(adev); |
2c1a2784 | 2724 | if (r) { |
7ccfd79f | 2725 | DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r); |
72d3f592 | 2726 | goto init_failed; |
2c1a2784 | 2727 | } |
a1255107 | 2728 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2729 | if (r) { |
2730 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2731 | goto init_failed; |
2c1a2784 | 2732 | } |
06ec9070 | 2733 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2734 | if (r) { |
06ec9070 | 2735 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2736 | goto init_failed; |
2c1a2784 | 2737 | } |
a1255107 | 2738 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2739 | |
2740 | /* right after GMC hw init, we create CSA */ | |
02ff519e | 2741 | if (adev->gfx.mcbp) { |
1e256e27 | 2742 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
58ab2c08 CK |
2743 | AMDGPU_GEM_DOMAIN_VRAM | |
2744 | AMDGPU_GEM_DOMAIN_GTT, | |
2745 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2746 | if (r) { |
2747 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2748 | goto init_failed; |
2493664f ML |
2749 | } |
2750 | } | |
c8031019 APS |
2751 | |
2752 | r = amdgpu_seq64_init(adev); | |
2753 | if (r) { | |
2754 | DRM_ERROR("allocate seq64 failed %d\n", r); | |
2755 | goto init_failed; | |
2756 | } | |
d38ceaf9 AD |
2757 | } |
2758 | } | |
2759 | ||
c9ffa427 | 2760 | if (amdgpu_sriov_vf(adev)) |
22c16d25 | 2761 | amdgpu_virt_init_data_exchange(adev); |
c9ffa427 | 2762 | |
533aed27 AG |
2763 | r = amdgpu_ib_pool_init(adev); |
2764 | if (r) { | |
2765 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2766 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2767 | goto init_failed; | |
2768 | } | |
2769 | ||
c8963ea4 RZ |
2770 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2771 | if (r) | |
72d3f592 | 2772 | goto init_failed; |
0a4f2520 RZ |
2773 | |
2774 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2775 | if (r) | |
72d3f592 | 2776 | goto init_failed; |
0a4f2520 | 2777 | |
7a3e0bb2 RZ |
2778 | r = amdgpu_device_fw_loading(adev); |
2779 | if (r) | |
72d3f592 | 2780 | goto init_failed; |
7a3e0bb2 | 2781 | |
0a4f2520 RZ |
2782 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2783 | if (r) | |
72d3f592 | 2784 | goto init_failed; |
d38ceaf9 | 2785 | |
121a2bc6 AG |
2786 | /* |
2787 | * retired pages will be loaded from eeprom and reserved here, | |
2788 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2789 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2790 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2791 | * |
2792 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2793 | * failure from bad gpu situation and stop amdgpu init process | |
2794 | * accordingly. For other failed cases, it will still release all | |
2795 | * the resource and print error message, rather than returning one | |
2796 | * negative value to upper level. | |
121a2bc6 AG |
2797 | * |
2798 | * Note: theoretically, this should be called before all vram allocations | |
2799 | * to protect retired page from abusing | |
2800 | */ | |
b82e65a9 GC |
2801 | r = amdgpu_ras_recovery_init(adev); |
2802 | if (r) | |
2803 | goto init_failed; | |
121a2bc6 | 2804 | |
cfbb6b00 AG |
2805 | /** |
2806 | * In case of XGMI grab extra reference for reset domain for this device | |
2807 | */ | |
a4c63caf | 2808 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
cfbb6b00 | 2809 | if (amdgpu_xgmi_add_device(adev) == 0) { |
46c67660 | 2810 | if (!amdgpu_sriov_vf(adev)) { |
2efc30f0 VC |
2811 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
2812 | ||
dfd0287b LH |
2813 | if (WARN_ON(!hive)) { |
2814 | r = -ENOENT; | |
2815 | goto init_failed; | |
2816 | } | |
2817 | ||
46c67660 | 2818 | if (!hive->reset_domain || |
2819 | !amdgpu_reset_get_reset_domain(hive->reset_domain)) { | |
2820 | r = -ENOENT; | |
2821 | amdgpu_put_xgmi_hive(hive); | |
2822 | goto init_failed; | |
2823 | } | |
2824 | ||
2825 | /* Drop the early temporary reset domain we created for device */ | |
2826 | amdgpu_reset_put_reset_domain(adev->reset_domain); | |
2827 | adev->reset_domain = hive->reset_domain; | |
9dfa4860 | 2828 | amdgpu_put_xgmi_hive(hive); |
cfbb6b00 | 2829 | } |
a4c63caf AG |
2830 | } |
2831 | } | |
2832 | ||
5fd8518d AG |
2833 | r = amdgpu_device_init_schedulers(adev); |
2834 | if (r) | |
2835 | goto init_failed; | |
e3c1b071 | 2836 | |
b7043800 AD |
2837 | if (adev->mman.buffer_funcs_ring->sched.ready) |
2838 | amdgpu_ttm_set_buffer_funcs_status(adev, true); | |
2839 | ||
e3c1b071 | 2840 | /* Don't init kfd if whole hive need to be reset during init */ |
84b4dd3f PY |
2841 | if (!adev->gmc.xgmi.pending_reset) { |
2842 | kgd2kfd_init_zone_device(adev); | |
e3c1b071 | 2843 | amdgpu_amdkfd_device_init(adev); |
84b4dd3f | 2844 | } |
c6332b97 | 2845 | |
bd607166 KR |
2846 | amdgpu_fru_get_product_info(adev); |
2847 | ||
72d3f592 | 2848 | init_failed: |
c6332b97 | 2849 | |
72d3f592 | 2850 | return r; |
d38ceaf9 AD |
2851 | } |
2852 | ||
e3ecdffa AD |
2853 | /** |
2854 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2855 | * | |
2856 | * @adev: amdgpu_device pointer | |
2857 | * | |
2858 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2859 | * this function before a GPU reset. If the value is retained after a | |
2860 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2861 | */ | |
06ec9070 | 2862 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2863 | { |
2864 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2865 | } | |
2866 | ||
e3ecdffa AD |
2867 | /** |
2868 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2869 | * | |
2870 | * @adev: amdgpu_device pointer | |
2871 | * | |
2872 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2873 | * The driver calls this after a GPU reset to see if the contents of | |
2874 | * VRAM is lost or now. | |
2875 | * returns true if vram is lost, false if not. | |
2876 | */ | |
06ec9070 | 2877 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2878 | { |
dadce777 EQ |
2879 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2880 | AMDGPU_RESET_MAGIC_NUM)) | |
2881 | return true; | |
2882 | ||
53b3f8f4 | 2883 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2884 | return false; |
2885 | ||
2886 | /* | |
2887 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2888 | * always assumed to be lost. | |
2889 | */ | |
2890 | switch (amdgpu_asic_reset_method(adev)) { | |
2891 | case AMD_RESET_METHOD_BACO: | |
2892 | case AMD_RESET_METHOD_MODE1: | |
2893 | return true; | |
2894 | default: | |
2895 | return false; | |
2896 | } | |
0c49e0b8 CZ |
2897 | } |
2898 | ||
e3ecdffa | 2899 | /** |
1112a46b | 2900 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2901 | * |
2902 | * @adev: amdgpu_device pointer | |
b8b72130 | 2903 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2904 | * |
e3ecdffa | 2905 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2906 | * set_clockgating_state callbacks are run. |
2907 | * Late initialization pass enabling clockgating for hardware IPs. | |
2908 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2909 | * Returns 0 on success, negative error code on failure. |
2910 | */ | |
fdd34271 | 2911 | |
5d89bb2d LL |
2912 | int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2913 | enum amd_clockgating_state state) | |
d38ceaf9 | 2914 | { |
1112a46b | 2915 | int i, j, r; |
d38ceaf9 | 2916 | |
4a2ba394 SL |
2917 | if (amdgpu_emu_mode == 1) |
2918 | return 0; | |
2919 | ||
1112a46b RZ |
2920 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2921 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2922 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2923 | continue; |
47198eb7 | 2924 | /* skip CG for GFX, SDMA on S0ix */ |
5d70a549 | 2925 | if (adev->in_s0ix && |
47198eb7 AD |
2926 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || |
2927 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) | |
5d70a549 | 2928 | continue; |
4a446d55 | 2929 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2930 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2931 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2932 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2933 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2934 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2935 | /* enable clockgating to save power */ |
a1255107 | 2936 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2937 | state); |
4a446d55 AD |
2938 | if (r) { |
2939 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2940 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2941 | return r; |
2942 | } | |
b0b00ff1 | 2943 | } |
d38ceaf9 | 2944 | } |
06b18f61 | 2945 | |
c9f96fd5 RZ |
2946 | return 0; |
2947 | } | |
2948 | ||
5d89bb2d LL |
2949 | int amdgpu_device_set_pg_state(struct amdgpu_device *adev, |
2950 | enum amd_powergating_state state) | |
c9f96fd5 | 2951 | { |
1112a46b | 2952 | int i, j, r; |
06b18f61 | 2953 | |
c9f96fd5 RZ |
2954 | if (amdgpu_emu_mode == 1) |
2955 | return 0; | |
2956 | ||
1112a46b RZ |
2957 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2958 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2959 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 | 2960 | continue; |
47198eb7 | 2961 | /* skip PG for GFX, SDMA on S0ix */ |
5d70a549 | 2962 | if (adev->in_s0ix && |
47198eb7 AD |
2963 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || |
2964 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) | |
5d70a549 | 2965 | continue; |
c9f96fd5 RZ |
2966 | /* skip CG for VCE/UVD, it's handled specially */ |
2967 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2968 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2969 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2970 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2971 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2972 | /* enable powergating to save power */ | |
2973 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2974 | state); |
c9f96fd5 RZ |
2975 | if (r) { |
2976 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2977 | adev->ip_blocks[i].version->funcs->name, r); | |
2978 | return r; | |
2979 | } | |
2980 | } | |
2981 | } | |
2dc80b00 S |
2982 | return 0; |
2983 | } | |
2984 | ||
beff74bc AD |
2985 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2986 | { | |
2987 | struct amdgpu_gpu_instance *gpu_ins; | |
2988 | struct amdgpu_device *adev; | |
2989 | int i, ret = 0; | |
2990 | ||
2991 | mutex_lock(&mgpu_info.mutex); | |
2992 | ||
2993 | /* | |
2994 | * MGPU fan boost feature should be enabled | |
2995 | * only when there are two or more dGPUs in | |
2996 | * the system | |
2997 | */ | |
2998 | if (mgpu_info.num_dgpu < 2) | |
2999 | goto out; | |
3000 | ||
3001 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
3002 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
3003 | adev = gpu_ins->adev; | |
3004 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 3005 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
3006 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
3007 | if (ret) | |
3008 | break; | |
3009 | ||
3010 | gpu_ins->mgpu_fan_enabled = 1; | |
3011 | } | |
3012 | } | |
3013 | ||
3014 | out: | |
3015 | mutex_unlock(&mgpu_info.mutex); | |
3016 | ||
3017 | return ret; | |
3018 | } | |
3019 | ||
e3ecdffa AD |
3020 | /** |
3021 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
3022 | * | |
3023 | * @adev: amdgpu_device pointer | |
3024 | * | |
3025 | * Late initialization pass for hardware IPs. The list of all the hardware | |
3026 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
3027 | * late_init covers any special initialization that an IP requires | |
3028 | * after all of the have been initialized or something that needs to happen | |
3029 | * late in the init process. | |
3030 | * Returns 0 on success, negative error code on failure. | |
3031 | */ | |
06ec9070 | 3032 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 3033 | { |
60599a03 | 3034 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
3035 | int i = 0, r; |
3036 | ||
3037 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 3038 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
3039 | continue; |
3040 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
3041 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
3042 | if (r) { | |
3043 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
3044 | adev->ip_blocks[i].version->funcs->name, r); | |
3045 | return r; | |
3046 | } | |
2dc80b00 | 3047 | } |
73f847db | 3048 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
3049 | } |
3050 | ||
867e24ca | 3051 | r = amdgpu_ras_late_init(adev); |
3052 | if (r) { | |
3053 | DRM_ERROR("amdgpu_ras_late_init failed %d", r); | |
3054 | return r; | |
3055 | } | |
3056 | ||
a891d239 DL |
3057 | amdgpu_ras_set_error_query_ready(adev, true); |
3058 | ||
1112a46b RZ |
3059 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
3060 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 3061 | |
06ec9070 | 3062 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 3063 | |
beff74bc AD |
3064 | r = amdgpu_device_enable_mgpu_fan_boost(); |
3065 | if (r) | |
3066 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
3067 | ||
4da8b639 | 3068 | /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */ |
47fc644f SS |
3069 | if (amdgpu_passthrough(adev) && |
3070 | ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) || | |
3071 | adev->asic_type == CHIP_ALDEBARAN)) | |
bc143d8b | 3072 | amdgpu_dpm_handle_passthrough_sbr(adev, true); |
60599a03 EQ |
3073 | |
3074 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
3075 | mutex_lock(&mgpu_info.mutex); | |
3076 | ||
3077 | /* | |
3078 | * Reset device p-state to low as this was booted with high. | |
3079 | * | |
3080 | * This should be performed only after all devices from the same | |
3081 | * hive get initialized. | |
3082 | * | |
3083 | * However, it's unknown how many device in the hive in advance. | |
3084 | * As this is counted one by one during devices initializations. | |
3085 | * | |
3086 | * So, we wait for all XGMI interlinked devices initialized. | |
3087 | * This may bring some delays as those devices may come from | |
3088 | * different hives. But that should be OK. | |
3089 | */ | |
3090 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
3091 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
3092 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
3093 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
3094 | continue; | |
3095 | ||
d84a430d JK |
3096 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
3097 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
3098 | if (r) { |
3099 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
3100 | break; | |
3101 | } | |
3102 | } | |
3103 | } | |
3104 | ||
3105 | mutex_unlock(&mgpu_info.mutex); | |
3106 | } | |
3107 | ||
d38ceaf9 AD |
3108 | return 0; |
3109 | } | |
3110 | ||
613aa3ea LY |
3111 | /** |
3112 | * amdgpu_device_smu_fini_early - smu hw_fini wrapper | |
3113 | * | |
3114 | * @adev: amdgpu_device pointer | |
3115 | * | |
3116 | * For ASICs need to disable SMC first | |
3117 | */ | |
3118 | static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev) | |
3119 | { | |
3120 | int i, r; | |
3121 | ||
4e8303cf | 3122 | if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0)) |
613aa3ea LY |
3123 | return; |
3124 | ||
3125 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3126 | if (!adev->ip_blocks[i].status.hw) | |
3127 | continue; | |
3128 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
3129 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); | |
3130 | /* XXX handle errors */ | |
3131 | if (r) { | |
3132 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
3133 | adev->ip_blocks[i].version->funcs->name, r); | |
3134 | } | |
3135 | adev->ip_blocks[i].status.hw = false; | |
3136 | break; | |
3137 | } | |
3138 | } | |
3139 | } | |
3140 | ||
e9669fb7 | 3141 | static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) |
d38ceaf9 AD |
3142 | { |
3143 | int i, r; | |
3144 | ||
e9669fb7 AG |
3145 | for (i = 0; i < adev->num_ip_blocks; i++) { |
3146 | if (!adev->ip_blocks[i].version->funcs->early_fini) | |
3147 | continue; | |
5278a159 | 3148 | |
e9669fb7 AG |
3149 | r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); |
3150 | if (r) { | |
3151 | DRM_DEBUG("early_fini of IP block <%s> failed %d\n", | |
3152 | adev->ip_blocks[i].version->funcs->name, r); | |
3153 | } | |
3154 | } | |
c030f2e4 | 3155 | |
05df1f01 | 3156 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
3157 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
3158 | ||
7270e895 TY |
3159 | amdgpu_amdkfd_suspend(adev, false); |
3160 | ||
613aa3ea LY |
3161 | /* Workaroud for ASICs need to disable SMC first */ |
3162 | amdgpu_device_smu_fini_early(adev); | |
3e96dbfd | 3163 | |
d38ceaf9 | 3164 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 3165 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 3166 | continue; |
8201a67a | 3167 | |
a1255107 | 3168 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 3169 | /* XXX handle errors */ |
2c1a2784 | 3170 | if (r) { |
a1255107 AD |
3171 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
3172 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 3173 | } |
8201a67a | 3174 | |
a1255107 | 3175 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
3176 | } |
3177 | ||
6effad8a GC |
3178 | if (amdgpu_sriov_vf(adev)) { |
3179 | if (amdgpu_virt_release_full_gpu(adev, false)) | |
3180 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
3181 | } | |
3182 | ||
e9669fb7 AG |
3183 | return 0; |
3184 | } | |
3185 | ||
3186 | /** | |
3187 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
3188 | * | |
3189 | * @adev: amdgpu_device pointer | |
3190 | * | |
3191 | * Main teardown pass for hardware IPs. The list of all the hardware | |
3192 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
3193 | * are run. hw_fini tears down the hardware associated with each IP | |
3194 | * and sw_fini tears down any software state associated with each IP. | |
3195 | * Returns 0 on success, negative error code on failure. | |
3196 | */ | |
3197 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |
3198 | { | |
3199 | int i, r; | |
3200 | ||
3201 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) | |
3202 | amdgpu_virt_release_ras_err_handler_data(adev); | |
3203 | ||
e9669fb7 AG |
3204 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
3205 | amdgpu_xgmi_remove_device(adev); | |
3206 | ||
c004d44e | 3207 | amdgpu_amdkfd_device_fini_sw(adev); |
9950cda2 | 3208 | |
d38ceaf9 | 3209 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 3210 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 3211 | continue; |
c12aba3a ML |
3212 | |
3213 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 3214 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 3215 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a | 3216 | amdgpu_device_wb_fini(adev); |
7ccfd79f | 3217 | amdgpu_device_mem_scratch_fini(adev); |
533aed27 | 3218 | amdgpu_ib_pool_fini(adev); |
c8031019 | 3219 | amdgpu_seq64_fini(adev); |
c12aba3a ML |
3220 | } |
3221 | ||
a1255107 | 3222 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 3223 | /* XXX handle errors */ |
2c1a2784 | 3224 | if (r) { |
a1255107 AD |
3225 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
3226 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 3227 | } |
a1255107 AD |
3228 | adev->ip_blocks[i].status.sw = false; |
3229 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
3230 | } |
3231 | ||
a6dcfd9c | 3232 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 3233 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 3234 | continue; |
a1255107 AD |
3235 | if (adev->ip_blocks[i].version->funcs->late_fini) |
3236 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
3237 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
3238 | } |
3239 | ||
c030f2e4 | 3240 | amdgpu_ras_fini(adev); |
3241 | ||
d38ceaf9 AD |
3242 | return 0; |
3243 | } | |
3244 | ||
e3ecdffa | 3245 | /** |
beff74bc | 3246 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 3247 | * |
1112a46b | 3248 | * @work: work_struct. |
e3ecdffa | 3249 | */ |
beff74bc | 3250 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
3251 | { |
3252 | struct amdgpu_device *adev = | |
beff74bc | 3253 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
3254 | int r; |
3255 | ||
3256 | r = amdgpu_ib_ring_tests(adev); | |
3257 | if (r) | |
3258 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
3259 | } |
3260 | ||
1e317b99 RZ |
3261 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
3262 | { | |
3263 | struct amdgpu_device *adev = | |
3264 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
3265 | ||
90a92662 MD |
3266 | WARN_ON_ONCE(adev->gfx.gfx_off_state); |
3267 | WARN_ON_ONCE(adev->gfx.gfx_off_req_count); | |
3268 | ||
3269 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
3270 | adev->gfx.gfx_off_state = true; | |
1e317b99 RZ |
3271 | } |
3272 | ||
e3ecdffa | 3273 | /** |
e7854a03 | 3274 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
3275 | * |
3276 | * @adev: amdgpu_device pointer | |
3277 | * | |
3278 | * Main suspend function for hardware IPs. The list of all the hardware | |
3279 | * IPs that make up the asic is walked, clockgating is disabled and the | |
3280 | * suspend callbacks are run. suspend puts the hardware and software state | |
3281 | * in each IP into a state suitable for suspend. | |
3282 | * Returns 0 on success, negative error code on failure. | |
3283 | */ | |
e7854a03 AD |
3284 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
3285 | { | |
3286 | int i, r; | |
3287 | ||
50ec83f0 AD |
3288 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
3289 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 3290 | |
b31d6ada EQ |
3291 | /* |
3292 | * Per PMFW team's suggestion, driver needs to handle gfxoff | |
3293 | * and df cstate features disablement for gpu reset(e.g. Mode1Reset) | |
3294 | * scenario. Add the missing df cstate disablement here. | |
3295 | */ | |
3296 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
3297 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
3298 | ||
e7854a03 AD |
3299 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
3300 | if (!adev->ip_blocks[i].status.valid) | |
3301 | continue; | |
2b9f7848 | 3302 | |
e7854a03 | 3303 | /* displays are handled separately */ |
2b9f7848 ND |
3304 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
3305 | continue; | |
3306 | ||
3307 | /* XXX handle errors */ | |
3308 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
3309 | /* XXX handle errors */ | |
3310 | if (r) { | |
3311 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
3312 | adev->ip_blocks[i].version->funcs->name, r); | |
3313 | return r; | |
e7854a03 | 3314 | } |
2b9f7848 ND |
3315 | |
3316 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
3317 | } |
3318 | ||
e7854a03 AD |
3319 | return 0; |
3320 | } | |
3321 | ||
3322 | /** | |
3323 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
3324 | * | |
3325 | * @adev: amdgpu_device pointer | |
3326 | * | |
3327 | * Main suspend function for hardware IPs. The list of all the hardware | |
3328 | * IPs that make up the asic is walked, clockgating is disabled and the | |
3329 | * suspend callbacks are run. suspend puts the hardware and software state | |
3330 | * in each IP into a state suitable for suspend. | |
3331 | * Returns 0 on success, negative error code on failure. | |
3332 | */ | |
3333 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
3334 | { |
3335 | int i, r; | |
3336 | ||
557f42a2 | 3337 | if (adev->in_s0ix) |
bc143d8b | 3338 | amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry); |
34416931 | 3339 | |
d38ceaf9 | 3340 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 3341 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 3342 | continue; |
e7854a03 AD |
3343 | /* displays are handled in phase1 */ |
3344 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
3345 | continue; | |
bff77e86 LM |
3346 | /* PSP lost connection when err_event_athub occurs */ |
3347 | if (amdgpu_ras_intr_triggered() && | |
3348 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
3349 | adev->ip_blocks[i].status.hw = false; | |
3350 | continue; | |
3351 | } | |
e3c1b071 | 3352 | |
3353 | /* skip unnecessary suspend if we do not initialize them yet */ | |
3354 | if (adev->gmc.xgmi.pending_reset && | |
3355 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3356 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
3357 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3358 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
3359 | adev->ip_blocks[i].status.hw = false; | |
3360 | continue; | |
3361 | } | |
557f42a2 | 3362 | |
afa6646b | 3363 | /* skip suspend of gfx/mes and psp for S0ix |
32ff160d AD |
3364 | * gfx is in gfxoff state, so on resume it will exit gfxoff just |
3365 | * like at runtime. PSP is also part of the always on hardware | |
3366 | * so no need to suspend it. | |
3367 | */ | |
557f42a2 | 3368 | if (adev->in_s0ix && |
32ff160d | 3369 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || |
afa6646b AD |
3370 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || |
3371 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES)) | |
557f42a2 AD |
3372 | continue; |
3373 | ||
2a7798ea AD |
3374 | /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */ |
3375 | if (adev->in_s0ix && | |
4e8303cf LL |
3376 | (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= |
3377 | IP_VERSION(5, 0, 0)) && | |
3378 | (adev->ip_blocks[i].version->type == | |
3379 | AMD_IP_BLOCK_TYPE_SDMA)) | |
2a7798ea AD |
3380 | continue; |
3381 | ||
e11c7750 TH |
3382 | /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot. |
3383 | * These are in TMR, hence are expected to be reused by PSP-TOS to reload | |
3384 | * from this location and RLC Autoload automatically also gets loaded | |
3385 | * from here based on PMFW -> PSP message during re-init sequence. | |
3386 | * Therefore, the psp suspend & resume should be skipped to avoid destroy | |
3387 | * the TMR and reload FWs again for IMU enabled APU ASICs. | |
3388 | */ | |
3389 | if (amdgpu_in_reset(adev) && | |
3390 | (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs && | |
3391 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
3392 | continue; | |
3393 | ||
d38ceaf9 | 3394 | /* XXX handle errors */ |
a1255107 | 3395 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 3396 | /* XXX handle errors */ |
2c1a2784 | 3397 | if (r) { |
a1255107 AD |
3398 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
3399 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 3400 | } |
876923fb | 3401 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 3402 | /* handle putting the SMC in the appropriate state */ |
47fc644f | 3403 | if (!amdgpu_sriov_vf(adev)) { |
86b93fd6 JZ |
3404 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3405 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
3406 | if (r) { | |
3407 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
3408 | adev->mp1_state, r); | |
3409 | return r; | |
3410 | } | |
a3a09142 AD |
3411 | } |
3412 | } | |
d38ceaf9 AD |
3413 | } |
3414 | ||
3415 | return 0; | |
3416 | } | |
3417 | ||
e7854a03 AD |
3418 | /** |
3419 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
3420 | * | |
3421 | * @adev: amdgpu_device pointer | |
3422 | * | |
3423 | * Main suspend function for hardware IPs. The list of all the hardware | |
3424 | * IPs that make up the asic is walked, clockgating is disabled and the | |
3425 | * suspend callbacks are run. suspend puts the hardware and software state | |
3426 | * in each IP into a state suitable for suspend. | |
3427 | * Returns 0 on success, negative error code on failure. | |
3428 | */ | |
3429 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
3430 | { | |
3431 | int r; | |
3432 | ||
3c73683c JC |
3433 | if (amdgpu_sriov_vf(adev)) { |
3434 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 3435 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 3436 | } |
e7819644 | 3437 | |
b7043800 AD |
3438 | amdgpu_ttm_set_buffer_funcs_status(adev, false); |
3439 | ||
e7854a03 AD |
3440 | r = amdgpu_device_ip_suspend_phase1(adev); |
3441 | if (r) | |
3442 | return r; | |
3443 | r = amdgpu_device_ip_suspend_phase2(adev); | |
3444 | ||
e7819644 YT |
3445 | if (amdgpu_sriov_vf(adev)) |
3446 | amdgpu_virt_release_full_gpu(adev, false); | |
3447 | ||
e7854a03 AD |
3448 | return r; |
3449 | } | |
3450 | ||
06ec9070 | 3451 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3452 | { |
3453 | int i, r; | |
3454 | ||
2cb681b6 | 3455 | static enum amd_ip_block_type ip_order[] = { |
2cb681b6 | 3456 | AMD_IP_BLOCK_TYPE_COMMON, |
c1c39032 | 3457 | AMD_IP_BLOCK_TYPE_GMC, |
39186aef | 3458 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
3459 | AMD_IP_BLOCK_TYPE_IH, |
3460 | }; | |
a90ad3c2 | 3461 | |
95ea3dbc | 3462 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2cb681b6 ML |
3463 | int j; |
3464 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3465 | |
4cd2a96d J |
3466 | block = &adev->ip_blocks[i]; |
3467 | block->status.hw = false; | |
2cb681b6 | 3468 | |
4cd2a96d | 3469 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 3470 | |
4cd2a96d | 3471 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
3472 | !block->status.valid) |
3473 | continue; | |
3474 | ||
3475 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 3476 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3477 | if (r) |
3478 | return r; | |
482f0e53 | 3479 | block->status.hw = true; |
a90ad3c2 ML |
3480 | } |
3481 | } | |
3482 | ||
3483 | return 0; | |
3484 | } | |
3485 | ||
06ec9070 | 3486 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3487 | { |
3488 | int i, r; | |
3489 | ||
2cb681b6 ML |
3490 | static enum amd_ip_block_type ip_order[] = { |
3491 | AMD_IP_BLOCK_TYPE_SMC, | |
3492 | AMD_IP_BLOCK_TYPE_DCE, | |
3493 | AMD_IP_BLOCK_TYPE_GFX, | |
3494 | AMD_IP_BLOCK_TYPE_SDMA, | |
ec64350d | 3495 | AMD_IP_BLOCK_TYPE_MES, |
257deb8c | 3496 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 | 3497 | AMD_IP_BLOCK_TYPE_VCE, |
d2cdc014 YZ |
3498 | AMD_IP_BLOCK_TYPE_VCN, |
3499 | AMD_IP_BLOCK_TYPE_JPEG | |
2cb681b6 | 3500 | }; |
a90ad3c2 | 3501 | |
2cb681b6 ML |
3502 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
3503 | int j; | |
3504 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3505 | |
2cb681b6 ML |
3506 | for (j = 0; j < adev->num_ip_blocks; j++) { |
3507 | block = &adev->ip_blocks[j]; | |
3508 | ||
3509 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
3510 | !block->status.valid || |
3511 | block->status.hw) | |
2cb681b6 ML |
3512 | continue; |
3513 | ||
895bd048 JZ |
3514 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
3515 | r = block->version->funcs->resume(adev); | |
3516 | else | |
3517 | r = block->version->funcs->hw_init(adev); | |
3518 | ||
0aaeefcc | 3519 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3520 | if (r) |
3521 | return r; | |
482f0e53 | 3522 | block->status.hw = true; |
a90ad3c2 ML |
3523 | } |
3524 | } | |
3525 | ||
3526 | return 0; | |
3527 | } | |
3528 | ||
e3ecdffa AD |
3529 | /** |
3530 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
3531 | * | |
3532 | * @adev: amdgpu_device pointer | |
3533 | * | |
3534 | * First resume function for hardware IPs. The list of all the hardware | |
3535 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3536 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
3537 | * after a suspend and updates the software state as necessary. This | |
3538 | * function is also used for restoring the GPU after a GPU reset. | |
3539 | * Returns 0 on success, negative error code on failure. | |
3540 | */ | |
06ec9070 | 3541 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
3542 | { |
3543 | int i, r; | |
3544 | ||
a90ad3c2 | 3545 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 3546 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 3547 | continue; |
a90ad3c2 | 3548 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3549 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
d7274ec7 BZ |
3550 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3551 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) { | |
482f0e53 | 3552 | |
fcf0649f CZ |
3553 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
3554 | if (r) { | |
3555 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
3556 | adev->ip_blocks[i].version->funcs->name, r); | |
3557 | return r; | |
3558 | } | |
482f0e53 | 3559 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
3560 | } |
3561 | } | |
3562 | ||
3563 | return 0; | |
3564 | } | |
3565 | ||
e3ecdffa AD |
3566 | /** |
3567 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
3568 | * | |
3569 | * @adev: amdgpu_device pointer | |
3570 | * | |
3571 | * First resume function for hardware IPs. The list of all the hardware | |
3572 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3573 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
3574 | * functional state after a suspend and updates the software state as | |
3575 | * necessary. This function is also used for restoring the GPU after a GPU | |
3576 | * reset. | |
3577 | * Returns 0 on success, negative error code on failure. | |
3578 | */ | |
06ec9070 | 3579 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
3580 | { |
3581 | int i, r; | |
3582 | ||
3583 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 3584 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 3585 | continue; |
fcf0649f | 3586 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3587 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
3588 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3589 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 3590 | continue; |
a1255107 | 3591 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 3592 | if (r) { |
a1255107 AD |
3593 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
3594 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 3595 | return r; |
2c1a2784 | 3596 | } |
482f0e53 | 3597 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
3598 | } |
3599 | ||
3600 | return 0; | |
3601 | } | |
3602 | ||
e3ecdffa AD |
3603 | /** |
3604 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
3605 | * | |
3606 | * @adev: amdgpu_device pointer | |
3607 | * | |
3608 | * Main resume function for hardware IPs. The hardware IPs | |
3609 | * are split into two resume functions because they are | |
b8920e1e | 3610 | * also used in recovering from a GPU reset and some additional |
e3ecdffa AD |
3611 | * steps need to be take between them. In this case (S3/S4) they are |
3612 | * run sequentially. | |
3613 | * Returns 0 on success, negative error code on failure. | |
3614 | */ | |
06ec9070 | 3615 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
3616 | { |
3617 | int r; | |
3618 | ||
06ec9070 | 3619 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
3620 | if (r) |
3621 | return r; | |
7a3e0bb2 RZ |
3622 | |
3623 | r = amdgpu_device_fw_loading(adev); | |
3624 | if (r) | |
3625 | return r; | |
3626 | ||
06ec9070 | 3627 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f | 3628 | |
b7043800 AD |
3629 | if (adev->mman.buffer_funcs_ring->sched.ready) |
3630 | amdgpu_ttm_set_buffer_funcs_status(adev, true); | |
3631 | ||
fcf0649f CZ |
3632 | return r; |
3633 | } | |
3634 | ||
e3ecdffa AD |
3635 | /** |
3636 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
3637 | * | |
3638 | * @adev: amdgpu_device pointer | |
3639 | * | |
3640 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
3641 | */ | |
4e99a44e | 3642 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 3643 | { |
6867e1b5 ML |
3644 | if (amdgpu_sriov_vf(adev)) { |
3645 | if (adev->is_atom_fw) { | |
58ff791a | 3646 | if (amdgpu_atomfirmware_gpu_virtualization_supported(adev)) |
6867e1b5 ML |
3647 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; |
3648 | } else { | |
3649 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3650 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3651 | } | |
3652 | ||
3653 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3654 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3655 | } |
048765ad AR |
3656 | } |
3657 | ||
e3ecdffa AD |
3658 | /** |
3659 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3660 | * | |
3661 | * @asic_type: AMD asic type | |
3662 | * | |
3663 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3664 | * returns true if DC has support, false if not. | |
3665 | */ | |
4562236b HW |
3666 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3667 | { | |
3668 | switch (asic_type) { | |
0637d417 AD |
3669 | #ifdef CONFIG_DRM_AMDGPU_SI |
3670 | case CHIP_HAINAN: | |
3671 | #endif | |
3672 | case CHIP_TOPAZ: | |
3673 | /* chips with no display hardware */ | |
3674 | return false; | |
4562236b | 3675 | #if defined(CONFIG_DRM_AMD_DC) |
64200c46 MR |
3676 | case CHIP_TAHITI: |
3677 | case CHIP_PITCAIRN: | |
3678 | case CHIP_VERDE: | |
3679 | case CHIP_OLAND: | |
2d32ffd6 AD |
3680 | /* |
3681 | * We have systems in the wild with these ASICs that require | |
3682 | * LVDS and VGA support which is not supported with DC. | |
3683 | * | |
3684 | * Fallback to the non-DC driver here by default so as not to | |
3685 | * cause regressions. | |
3686 | */ | |
3687 | #if defined(CONFIG_DRM_AMD_DC_SI) | |
3688 | return amdgpu_dc > 0; | |
3689 | #else | |
3690 | return false; | |
64200c46 | 3691 | #endif |
4562236b | 3692 | case CHIP_BONAIRE: |
0d6fbccb | 3693 | case CHIP_KAVERI: |
367e6687 AD |
3694 | case CHIP_KABINI: |
3695 | case CHIP_MULLINS: | |
d9fda248 HW |
3696 | /* |
3697 | * We have systems in the wild with these ASICs that require | |
b5a0168e | 3698 | * VGA support which is not supported with DC. |
d9fda248 HW |
3699 | * |
3700 | * Fallback to the non-DC driver here by default so as not to | |
3701 | * cause regressions. | |
3702 | */ | |
3703 | return amdgpu_dc > 0; | |
f7f12b25 | 3704 | default: |
fd187853 | 3705 | return amdgpu_dc != 0; |
f7f12b25 | 3706 | #else |
4562236b | 3707 | default: |
93b09a9a | 3708 | if (amdgpu_dc > 0) |
b8920e1e | 3709 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n"); |
4562236b | 3710 | return false; |
f7f12b25 | 3711 | #endif |
4562236b HW |
3712 | } |
3713 | } | |
3714 | ||
3715 | /** | |
3716 | * amdgpu_device_has_dc_support - check if dc is supported | |
3717 | * | |
982a820b | 3718 | * @adev: amdgpu_device pointer |
4562236b HW |
3719 | * |
3720 | * Returns true for supported, false for not supported | |
3721 | */ | |
3722 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3723 | { | |
25263da3 | 3724 | if (adev->enable_virtual_display || |
abaf210c | 3725 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) |
2555039d XY |
3726 | return false; |
3727 | ||
4562236b HW |
3728 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3729 | } | |
3730 | ||
d4535e2c AG |
3731 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) |
3732 | { | |
3733 | struct amdgpu_device *adev = | |
3734 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3735 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3736 | |
c6a6e2db AG |
3737 | /* It's a bug to not have a hive within this function */ |
3738 | if (WARN_ON(!hive)) | |
3739 | return; | |
3740 | ||
3741 | /* | |
3742 | * Use task barrier to synchronize all xgmi reset works across the | |
3743 | * hive. task_barrier_enter and task_barrier_exit will block | |
3744 | * until all the threads running the xgmi reset works reach | |
3745 | * those points. task_barrier_full will do both blocks. | |
3746 | */ | |
3747 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3748 | ||
3749 | task_barrier_enter(&hive->tb); | |
4a580877 | 3750 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3751 | |
3752 | if (adev->asic_reset_res) | |
3753 | goto fail; | |
3754 | ||
3755 | task_barrier_exit(&hive->tb); | |
4a580877 | 3756 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3757 | |
3758 | if (adev->asic_reset_res) | |
3759 | goto fail; | |
43c4d576 | 3760 | |
21226f02 | 3761 | amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); |
c6a6e2db AG |
3762 | } else { |
3763 | ||
3764 | task_barrier_full(&hive->tb); | |
3765 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3766 | } | |
ce316fa5 | 3767 | |
c6a6e2db | 3768 | fail: |
d4535e2c | 3769 | if (adev->asic_reset_res) |
fed184e9 | 3770 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3771 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3772 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3773 | } |
3774 | ||
71f98027 AD |
3775 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3776 | { | |
3777 | char *input = amdgpu_lockup_timeout; | |
3778 | char *timeout_setting = NULL; | |
3779 | int index = 0; | |
3780 | long timeout; | |
3781 | int ret = 0; | |
3782 | ||
3783 | /* | |
67387dfe AD |
3784 | * By default timeout for non compute jobs is 10000 |
3785 | * and 60000 for compute jobs. | |
71f98027 | 3786 | * In SR-IOV or passthrough mode, timeout for compute |
b7b2a316 | 3787 | * jobs are 60000 by default. |
71f98027 AD |
3788 | */ |
3789 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3790 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3791 | if (amdgpu_sriov_vf(adev)) |
3792 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3793 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
71f98027 | 3794 | else |
67387dfe | 3795 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 | 3796 | |
f440ff44 | 3797 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3798 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3799 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3800 | ret = kstrtol(timeout_setting, 0, &timeout); |
3801 | if (ret) | |
3802 | return ret; | |
3803 | ||
3804 | if (timeout == 0) { | |
3805 | index++; | |
3806 | continue; | |
3807 | } else if (timeout < 0) { | |
3808 | timeout = MAX_SCHEDULE_TIMEOUT; | |
127aedf9 CK |
3809 | dev_warn(adev->dev, "lockup timeout disabled"); |
3810 | add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK); | |
71f98027 AD |
3811 | } else { |
3812 | timeout = msecs_to_jiffies(timeout); | |
3813 | } | |
3814 | ||
3815 | switch (index++) { | |
3816 | case 0: | |
3817 | adev->gfx_timeout = timeout; | |
3818 | break; | |
3819 | case 1: | |
3820 | adev->compute_timeout = timeout; | |
3821 | break; | |
3822 | case 2: | |
3823 | adev->sdma_timeout = timeout; | |
3824 | break; | |
3825 | case 3: | |
3826 | adev->video_timeout = timeout; | |
3827 | break; | |
3828 | default: | |
3829 | break; | |
3830 | } | |
3831 | } | |
3832 | /* | |
3833 | * There is only one value specified and | |
3834 | * it should apply to all non-compute jobs. | |
3835 | */ | |
bcccee89 | 3836 | if (index == 1) { |
71f98027 | 3837 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3838 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3839 | adev->compute_timeout = adev->gfx_timeout; | |
3840 | } | |
71f98027 AD |
3841 | } |
3842 | ||
3843 | return ret; | |
3844 | } | |
d4535e2c | 3845 | |
4a74c38c PY |
3846 | /** |
3847 | * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU | |
3848 | * | |
3849 | * @adev: amdgpu_device pointer | |
3850 | * | |
3851 | * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode | |
3852 | */ | |
3853 | static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev) | |
3854 | { | |
3855 | struct iommu_domain *domain; | |
3856 | ||
3857 | domain = iommu_get_domain_for_dev(adev->dev); | |
3858 | if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) | |
3859 | adev->ram_is_direct_mapped = true; | |
3860 | } | |
3861 | ||
77f3a5cd | 3862 | static const struct attribute *amdgpu_dev_attributes[] = { |
77f3a5cd ND |
3863 | &dev_attr_pcie_replay_count.attr, |
3864 | NULL | |
3865 | }; | |
3866 | ||
02ff519e AD |
3867 | static void amdgpu_device_set_mcbp(struct amdgpu_device *adev) |
3868 | { | |
3869 | if (amdgpu_mcbp == 1) | |
3870 | adev->gfx.mcbp = true; | |
1e9e15dc JZ |
3871 | else if (amdgpu_mcbp == 0) |
3872 | adev->gfx.mcbp = false; | |
50a7c876 | 3873 | |
02ff519e AD |
3874 | if (amdgpu_sriov_vf(adev)) |
3875 | adev->gfx.mcbp = true; | |
3876 | ||
3877 | if (adev->gfx.mcbp) | |
3878 | DRM_INFO("MCBP is enabled\n"); | |
3879 | } | |
3880 | ||
d38ceaf9 AD |
3881 | /** |
3882 | * amdgpu_device_init - initialize the driver | |
3883 | * | |
3884 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3885 | * @flags: driver flags |
3886 | * | |
3887 | * Initializes the driver info and hw (all asics). | |
3888 | * Returns 0 for success or an error on failure. | |
3889 | * Called at driver startup. | |
3890 | */ | |
3891 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3892 | uint32_t flags) |
3893 | { | |
8aba21b7 LT |
3894 | struct drm_device *ddev = adev_to_drm(adev); |
3895 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3896 | int r, i; |
b98c6299 | 3897 | bool px = false; |
95844d20 | 3898 | u32 max_MBps; |
59e9fff1 | 3899 | int tmp; |
d38ceaf9 AD |
3900 | |
3901 | adev->shutdown = false; | |
d38ceaf9 | 3902 | adev->flags = flags; |
4e66d7d2 YZ |
3903 | |
3904 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3905 | adev->asic_type = amdgpu_force_asic_type; | |
3906 | else | |
3907 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3908 | ||
d38ceaf9 | 3909 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3910 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3911 | adev->usec_timeout *= 10; |
770d13b1 | 3912 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3913 | adev->accel_working = false; |
3914 | adev->num_rings = 0; | |
68ce8b24 | 3915 | RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub()); |
d38ceaf9 AD |
3916 | adev->mman.buffer_funcs = NULL; |
3917 | adev->mman.buffer_funcs_ring = NULL; | |
3918 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3919 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3920 | adev->gmc.gmc_funcs = NULL; |
7bd939d0 | 3921 | adev->harvest_ip_mask = 0x0; |
f54d1867 | 3922 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3923 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3924 | |
3925 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3926 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3927 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3928 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
0c552ed3 LM |
3929 | adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; |
3930 | adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext; | |
36b9a952 HR |
3931 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3932 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3933 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3934 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
a76b2870 CL |
3935 | adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; |
3936 | adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; | |
d38ceaf9 AD |
3937 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3938 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3939 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3940 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3941 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3942 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3943 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3944 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3945 | ||
3e39ab90 AD |
3946 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3947 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3948 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3949 | |
3950 | /* mutex initialization are all done here so we | |
b8920e1e SS |
3951 | * can recall function without having locking issues |
3952 | */ | |
0e5ca0d1 | 3953 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3954 | mutex_init(&adev->pm.mutex); |
3955 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3956 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3957 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3958 | mutex_init(&adev->gfx.gfx_off_mutex); |
98a54e88 | 3959 | mutex_init(&adev->gfx.partition_mutex); |
d38ceaf9 | 3960 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3961 | mutex_init(&adev->mn_lock); |
e23b74aa | 3962 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3963 | hash_init(adev->mn_hash); |
32eaeae0 | 3964 | mutex_init(&adev->psp.mutex); |
bd052211 | 3965 | mutex_init(&adev->notifier_lock); |
8cda7a4f | 3966 | mutex_init(&adev->pm.stable_pstate_ctx_lock); |
f113cc32 | 3967 | mutex_init(&adev->benchmark_mutex); |
d38ceaf9 | 3968 | |
ab3b9de6 | 3969 | amdgpu_device_init_apu_flags(adev); |
9f6a7857 | 3970 | |
912dfc84 EQ |
3971 | r = amdgpu_device_check_arguments(adev); |
3972 | if (r) | |
3973 | return r; | |
d38ceaf9 | 3974 | |
d38ceaf9 AD |
3975 | spin_lock_init(&adev->mmio_idx_lock); |
3976 | spin_lock_init(&adev->smc_idx_lock); | |
3977 | spin_lock_init(&adev->pcie_idx_lock); | |
3978 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3979 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3980 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3981 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3982 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3983 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3984 | |
0c4e7fa5 CZ |
3985 | INIT_LIST_HEAD(&adev->shadow_list); |
3986 | mutex_init(&adev->shadow_list_lock); | |
3987 | ||
655ce9cb | 3988 | INIT_LIST_HEAD(&adev->reset_list); |
3989 | ||
6492e1b0 | 3990 | INIT_LIST_HEAD(&adev->ras_list); |
3991 | ||
3e38b634 EQ |
3992 | INIT_LIST_HEAD(&adev->pm.od_kobj_list); |
3993 | ||
beff74bc AD |
3994 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3995 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3996 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3997 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3998 | |
d4535e2c AG |
3999 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
4000 | ||
d23ee13f | 4001 | adev->gfx.gfx_off_req_count = 1; |
0ad7347a AA |
4002 | adev->gfx.gfx_off_residency = 0; |
4003 | adev->gfx.gfx_off_entrycount = 0; | |
b6e79d9a | 4004 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 4005 | |
b265bdbd EQ |
4006 | atomic_set(&adev->throttling_logging_enabled, 1); |
4007 | /* | |
4008 | * If throttling continues, logging will be performed every minute | |
4009 | * to avoid log flooding. "-1" is subtracted since the thermal | |
4010 | * throttling interrupt comes every second. Thus, the total logging | |
4011 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
4012 | * for throttling interrupt) = 60 seconds. | |
4013 | */ | |
4014 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
4015 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
4016 | ||
0fa49558 AX |
4017 | /* Registers mapping */ |
4018 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
4019 | if (adev->asic_type >= CHIP_BONAIRE) { |
4020 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
4021 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
4022 | } else { | |
4023 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
4024 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
4025 | } | |
d38ceaf9 | 4026 | |
6c08e0ef EQ |
4027 | for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++) |
4028 | atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); | |
4029 | ||
d38ceaf9 | 4030 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
b8920e1e | 4031 | if (!adev->rmmio) |
d38ceaf9 | 4032 | return -ENOMEM; |
b8920e1e | 4033 | |
d38ceaf9 | 4034 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); |
b8920e1e | 4035 | DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size); |
d38ceaf9 | 4036 | |
436afdfa PY |
4037 | /* |
4038 | * Reset domain needs to be present early, before XGMI hive discovered | |
4039 | * (if any) and intitialized to use reset sem and in_gpu reset flag | |
4040 | * early on during init and before calling to RREG32. | |
4041 | */ | |
4042 | adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev"); | |
eb4f1398 SS |
4043 | if (!adev->reset_domain) { |
4044 | r = -ENOMEM; | |
4045 | goto unmap_memory; | |
4046 | } | |
436afdfa | 4047 | |
3aa0115d ML |
4048 | /* detect hw virtualization here */ |
4049 | amdgpu_detect_virtualization(adev); | |
4050 | ||
04e85958 TL |
4051 | amdgpu_device_get_pcie_info(adev); |
4052 | ||
dffa11b4 ML |
4053 | r = amdgpu_device_get_job_timeout_settings(adev); |
4054 | if (r) { | |
4055 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
eb4f1398 | 4056 | goto unmap_memory; |
a190d1c7 XY |
4057 | } |
4058 | ||
bf909454 PEPP |
4059 | amdgpu_device_set_mcbp(adev); |
4060 | ||
d38ceaf9 | 4061 | /* early init functions */ |
06ec9070 | 4062 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 4063 | if (r) |
eb4f1398 | 4064 | goto unmap_memory; |
d38ceaf9 | 4065 | |
b7cdb41e ML |
4066 | /* Get rid of things like offb */ |
4067 | r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver); | |
4068 | if (r) | |
eb4f1398 | 4069 | goto unmap_memory; |
b7cdb41e | 4070 | |
4d33e704 SK |
4071 | /* Enable TMZ based on IP_VERSION */ |
4072 | amdgpu_gmc_tmz_set(adev); | |
4073 | ||
957b0787 | 4074 | amdgpu_gmc_noretry_set(adev); |
4a0165f0 VS |
4075 | /* Need to get xgmi info early to decide the reset behavior*/ |
4076 | if (adev->gmc.xgmi.supported) { | |
4077 | r = adev->gfxhub.funcs->get_xgmi_info(adev); | |
4078 | if (r) | |
eb4f1398 | 4079 | goto unmap_memory; |
4a0165f0 VS |
4080 | } |
4081 | ||
8e6d0b69 | 4082 | /* enable PCIE atomic ops */ |
b4520bfd GW |
4083 | if (amdgpu_sriov_vf(adev)) { |
4084 | if (adev->virt.fw_reserve.p_pf2vf) | |
4085 | adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *) | |
4086 | adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags == | |
4087 | (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
0e768043 YZ |
4088 | /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a |
4089 | * internal path natively support atomics, set have_atomics_support to true. | |
4090 | */ | |
b4520bfd | 4091 | } else if ((adev->flags & AMD_IS_APU) && |
4e8303cf LL |
4092 | (amdgpu_ip_version(adev, GC_HWIP, 0) > |
4093 | IP_VERSION(9, 0, 0))) { | |
0e768043 | 4094 | adev->have_atomics_support = true; |
b4520bfd | 4095 | } else { |
8e6d0b69 | 4096 | adev->have_atomics_support = |
4097 | !pci_enable_atomic_ops_to_root(adev->pdev, | |
4098 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
4099 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
b4520bfd GW |
4100 | } |
4101 | ||
8e6d0b69 | 4102 | if (!adev->have_atomics_support) |
4103 | dev_info(adev->dev, "PCIE atomic ops is not supported\n"); | |
4104 | ||
6585661d | 4105 | /* doorbell bar mapping and doorbell index init*/ |
43c064db | 4106 | amdgpu_doorbell_init(adev); |
6585661d | 4107 | |
9475a943 SL |
4108 | if (amdgpu_emu_mode == 1) { |
4109 | /* post the asic on emulation mode */ | |
4110 | emu_soc_asic_init(adev); | |
bfca0289 | 4111 | goto fence_driver_init; |
9475a943 | 4112 | } |
bfca0289 | 4113 | |
04442bf7 LL |
4114 | amdgpu_reset_init(adev); |
4115 | ||
4e99a44e | 4116 | /* detect if we are with an SRIOV vbios */ |
b4520bfd GW |
4117 | if (adev->bios) |
4118 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 4119 | |
95e8e59e AD |
4120 | /* check if we need to reset the asic |
4121 | * E.g., driver was not cleanly unloaded previously, etc. | |
4122 | */ | |
f14899fd | 4123 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 4124 | if (adev->gmc.xgmi.num_physical_nodes) { |
4125 | dev_info(adev->dev, "Pending hive reset.\n"); | |
4126 | adev->gmc.xgmi.pending_reset = true; | |
4127 | /* Only need to init necessary block for SMU to handle the reset */ | |
4128 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
4129 | if (!adev->ip_blocks[i].status.valid) | |
4130 | continue; | |
4131 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
4132 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
4133 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
4134 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 4135 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 4136 | adev->ip_blocks[i].version->funcs->name); |
4137 | adev->ip_blocks[i].status.hw = true; | |
4138 | } | |
4139 | } | |
4140 | } else { | |
7055c585 ML |
4141 | tmp = amdgpu_reset_method; |
4142 | /* It should do a default reset when loading or reloading the driver, | |
4143 | * regardless of the module parameter reset_method. | |
4144 | */ | |
4145 | amdgpu_reset_method = AMD_RESET_METHOD_NONE; | |
4146 | r = amdgpu_asic_reset(adev); | |
4147 | amdgpu_reset_method = tmp; | |
e3c1b071 | 4148 | if (r) { |
4149 | dev_err(adev->dev, "asic reset on init failed\n"); | |
4150 | goto failed; | |
4151 | } | |
95e8e59e AD |
4152 | } |
4153 | } | |
4154 | ||
d38ceaf9 | 4155 | /* Post card if necessary */ |
39c640c0 | 4156 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 4157 | if (!adev->bios) { |
bec86378 | 4158 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
4159 | r = -EINVAL; |
4160 | goto failed; | |
d38ceaf9 | 4161 | } |
bec86378 | 4162 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 4163 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
4164 | if (r) { |
4165 | dev_err(adev->dev, "gpu post error!\n"); | |
4166 | goto failed; | |
4167 | } | |
d38ceaf9 AD |
4168 | } |
4169 | ||
9535a86a SZ |
4170 | if (adev->bios) { |
4171 | if (adev->is_atom_fw) { | |
4172 | /* Initialize clocks */ | |
4173 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
4174 | if (r) { | |
4175 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
4176 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); | |
4177 | goto failed; | |
4178 | } | |
4179 | } else { | |
4180 | /* Initialize clocks */ | |
4181 | r = amdgpu_atombios_get_clock_info(adev); | |
4182 | if (r) { | |
4183 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
4184 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); | |
4185 | goto failed; | |
4186 | } | |
4187 | /* init i2c buses */ | |
4188 | if (!amdgpu_device_has_dc_support(adev)) | |
4189 | amdgpu_atombios_i2c_init(adev); | |
a5bde2f9 | 4190 | } |
2c1a2784 | 4191 | } |
d38ceaf9 | 4192 | |
bfca0289 | 4193 | fence_driver_init: |
d38ceaf9 | 4194 | /* Fence driver */ |
067f44c8 | 4195 | r = amdgpu_fence_driver_sw_init(adev); |
2c1a2784 | 4196 | if (r) { |
067f44c8 | 4197 | dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n"); |
e23b74aa | 4198 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 4199 | goto failed; |
2c1a2784 | 4200 | } |
d38ceaf9 AD |
4201 | |
4202 | /* init the mode config */ | |
4a580877 | 4203 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 4204 | |
06ec9070 | 4205 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 4206 | if (r) { |
06ec9070 | 4207 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 4208 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 4209 | goto release_ras_con; |
d38ceaf9 AD |
4210 | } |
4211 | ||
8d35a259 LG |
4212 | amdgpu_fence_driver_hw_init(adev); |
4213 | ||
d69b8971 YZ |
4214 | dev_info(adev->dev, |
4215 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
4216 | adev->gfx.config.max_shader_engines, |
4217 | adev->gfx.config.max_sh_per_se, | |
4218 | adev->gfx.config.max_cu_per_sh, | |
4219 | adev->gfx.cu_info.number); | |
4220 | ||
d38ceaf9 AD |
4221 | adev->accel_working = true; |
4222 | ||
e59c0205 AX |
4223 | amdgpu_vm_check_compute_bug(adev); |
4224 | ||
95844d20 MO |
4225 | /* Initialize the buffer migration limit. */ |
4226 | if (amdgpu_moverate >= 0) | |
4227 | max_MBps = amdgpu_moverate; | |
4228 | else | |
4229 | max_MBps = 8; /* Allow 8 MB/s. */ | |
4230 | /* Get a log2 for easy divisions. */ | |
4231 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
4232 | ||
b0adca4d EQ |
4233 | /* |
4234 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
4235 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
4236 | * gpu instance is counted less. | |
4237 | */ | |
4238 | amdgpu_register_gpu_instance(adev); | |
4239 | ||
d38ceaf9 AD |
4240 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
4241 | * explicit gating rather than handling it automatically. | |
4242 | */ | |
e3c1b071 | 4243 | if (!adev->gmc.xgmi.pending_reset) { |
4244 | r = amdgpu_device_ip_late_init(adev); | |
4245 | if (r) { | |
4246 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
4247 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 4248 | goto release_ras_con; |
e3c1b071 | 4249 | } |
4250 | /* must succeed. */ | |
4251 | amdgpu_ras_resume(adev); | |
4252 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
4253 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 4254 | } |
d38ceaf9 | 4255 | |
38eecbe0 CL |
4256 | if (amdgpu_sriov_vf(adev)) { |
4257 | amdgpu_virt_release_full_gpu(adev, true); | |
2c738637 | 4258 | flush_delayed_work(&adev->delayed_init_work); |
38eecbe0 | 4259 | } |
2c738637 | 4260 | |
90bcb9b5 EQ |
4261 | /* |
4262 | * Place those sysfs registering after `late_init`. As some of those | |
4263 | * operations performed in `late_init` might affect the sysfs | |
4264 | * interfaces creating. | |
4265 | */ | |
4266 | r = amdgpu_atombios_sysfs_init(adev); | |
4267 | if (r) | |
4268 | drm_err(&adev->ddev, | |
4269 | "registering atombios sysfs failed (%d).\n", r); | |
4270 | ||
4271 | r = amdgpu_pm_sysfs_init(adev); | |
4272 | if (r) | |
4273 | DRM_ERROR("registering pm sysfs failed (%d).\n", r); | |
4274 | ||
4275 | r = amdgpu_ucode_sysfs_init(adev); | |
4276 | if (r) { | |
4277 | adev->ucode_sysfs_en = false; | |
4278 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); | |
4279 | } else | |
4280 | adev->ucode_sysfs_en = true; | |
4281 | ||
77f3a5cd | 4282 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 4283 | if (r) |
77f3a5cd | 4284 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 4285 | |
76da73f0 LL |
4286 | r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group); |
4287 | if (r) | |
4288 | dev_err(adev->dev, | |
4289 | "Could not create amdgpu board attributes\n"); | |
4290 | ||
7957ec80 | 4291 | amdgpu_fru_sysfs_init(adev); |
af39e6f4 | 4292 | amdgpu_reg_state_sysfs_init(adev); |
7957ec80 | 4293 | |
d155bef0 AB |
4294 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
4295 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
4296 | if (r) |
4297 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
4298 | ||
c1dd4aa6 AG |
4299 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
4300 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
4301 | pci_restore_state(pdev); | |
4302 | ||
8c3dd61c KHF |
4303 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
4304 | /* this will fail for cards that aren't VGA class devices, just | |
b8920e1e SS |
4305 | * ignore it |
4306 | */ | |
8c3dd61c | 4307 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
bf44e8ce | 4308 | vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); |
8c3dd61c | 4309 | |
d37a3929 OC |
4310 | px = amdgpu_device_supports_px(ddev); |
4311 | ||
7b1c6263 | 4312 | if (px || (!dev_is_removable(&adev->pdev->dev) && |
d37a3929 | 4313 | apple_gmux_detect(NULL, NULL))) |
8c3dd61c KHF |
4314 | vga_switcheroo_register_client(adev->pdev, |
4315 | &amdgpu_switcheroo_ops, px); | |
d37a3929 OC |
4316 | |
4317 | if (px) | |
8c3dd61c | 4318 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); |
8c3dd61c | 4319 | |
e3c1b071 | 4320 | if (adev->gmc.xgmi.pending_reset) |
4321 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
4322 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
4323 | ||
4a74c38c PY |
4324 | amdgpu_device_check_iommu_direct_map(adev); |
4325 | ||
d38ceaf9 | 4326 | return 0; |
83ba126a | 4327 | |
970fd197 | 4328 | release_ras_con: |
38eecbe0 CL |
4329 | if (amdgpu_sriov_vf(adev)) |
4330 | amdgpu_virt_release_full_gpu(adev, true); | |
4331 | ||
4332 | /* failed in exclusive mode due to timeout */ | |
4333 | if (amdgpu_sriov_vf(adev) && | |
4334 | !amdgpu_sriov_runtime(adev) && | |
4335 | amdgpu_virt_mmio_blocked(adev) && | |
4336 | !amdgpu_virt_wait_reset(adev)) { | |
4337 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
4338 | /* Don't send request since VF is inactive. */ | |
4339 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
4340 | adev->virt.ops = NULL; | |
4341 | r = -EAGAIN; | |
4342 | } | |
970fd197 SY |
4343 | amdgpu_release_ras_context(adev); |
4344 | ||
83ba126a | 4345 | failed: |
89041940 | 4346 | amdgpu_vf_error_trans_all(adev); |
8840a387 | 4347 | |
eb4f1398 SS |
4348 | unmap_memory: |
4349 | iounmap(adev->rmmio); | |
83ba126a | 4350 | return r; |
d38ceaf9 AD |
4351 | } |
4352 | ||
07775fc1 AG |
4353 | static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) |
4354 | { | |
62d5f9f7 | 4355 | |
07775fc1 AG |
4356 | /* Clear all CPU mappings pointing to this device */ |
4357 | unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); | |
4358 | ||
4359 | /* Unmap all mapped bars - Doorbell, registers and VRAM */ | |
43c064db | 4360 | amdgpu_doorbell_fini(adev); |
07775fc1 AG |
4361 | |
4362 | iounmap(adev->rmmio); | |
4363 | adev->rmmio = NULL; | |
4364 | if (adev->mman.aper_base_kaddr) | |
4365 | iounmap(adev->mman.aper_base_kaddr); | |
4366 | adev->mman.aper_base_kaddr = NULL; | |
4367 | ||
4368 | /* Memory manager related */ | |
a0ba1279 | 4369 | if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { |
07775fc1 AG |
4370 | arch_phys_wc_del(adev->gmc.vram_mtrr); |
4371 | arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); | |
4372 | } | |
4373 | } | |
4374 | ||
d38ceaf9 | 4375 | /** |
bbe04dec | 4376 | * amdgpu_device_fini_hw - tear down the driver |
d38ceaf9 AD |
4377 | * |
4378 | * @adev: amdgpu_device pointer | |
4379 | * | |
4380 | * Tear down the driver info (all asics). | |
4381 | * Called at driver shutdown. | |
4382 | */ | |
72c8c97b | 4383 | void amdgpu_device_fini_hw(struct amdgpu_device *adev) |
d38ceaf9 | 4384 | { |
aac89168 | 4385 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 4386 | flush_delayed_work(&adev->delayed_init_work); |
d0d13fe8 | 4387 | adev->shutdown = true; |
9f875167 | 4388 | |
752c683d ML |
4389 | /* make sure IB test finished before entering exclusive mode |
4390 | * to avoid preemption on IB test | |
b8920e1e | 4391 | */ |
519b8b76 | 4392 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 4393 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
4394 | amdgpu_virt_fini_data_exchange(adev); |
4395 | } | |
752c683d | 4396 | |
e5b03032 ML |
4397 | /* disable all interrupts */ |
4398 | amdgpu_irq_disable_all(adev); | |
47fc644f | 4399 | if (adev->mode_info.mode_config_initialized) { |
1053b9c9 | 4400 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) |
4a580877 | 4401 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 4402 | else |
4a580877 | 4403 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 4404 | } |
8d35a259 | 4405 | amdgpu_fence_driver_hw_fini(adev); |
72c8c97b | 4406 | |
cd3a8a59 | 4407 | if (adev->mman.initialized) |
9bff18d1 | 4408 | drain_workqueue(adev->mman.bdev.wq); |
98f56188 | 4409 | |
53e9d836 | 4410 | if (adev->pm.sysfs_initialized) |
7c868b59 | 4411 | amdgpu_pm_sysfs_fini(adev); |
72c8c97b AG |
4412 | if (adev->ucode_sysfs_en) |
4413 | amdgpu_ucode_sysfs_fini(adev); | |
4414 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
7957ec80 | 4415 | amdgpu_fru_sysfs_fini(adev); |
72c8c97b | 4416 | |
af39e6f4 LL |
4417 | amdgpu_reg_state_sysfs_fini(adev); |
4418 | ||
232d1d43 SY |
4419 | /* disable ras feature must before hw fini */ |
4420 | amdgpu_ras_pre_fini(adev); | |
4421 | ||
b7043800 AD |
4422 | amdgpu_ttm_set_buffer_funcs_status(adev, false); |
4423 | ||
e9669fb7 | 4424 | amdgpu_device_ip_fini_early(adev); |
d10d0daa | 4425 | |
a3848df6 YW |
4426 | amdgpu_irq_fini_hw(adev); |
4427 | ||
b6fd6e0f SK |
4428 | if (adev->mman.initialized) |
4429 | ttm_device_clear_dma_mappings(&adev->mman.bdev); | |
894c6890 | 4430 | |
d10d0daa | 4431 | amdgpu_gart_dummy_page_fini(adev); |
07775fc1 | 4432 | |
39934d3e VP |
4433 | if (drm_dev_is_unplugged(adev_to_drm(adev))) |
4434 | amdgpu_device_unmap_mmio(adev); | |
87172e89 | 4435 | |
72c8c97b AG |
4436 | } |
4437 | ||
4438 | void amdgpu_device_fini_sw(struct amdgpu_device *adev) | |
4439 | { | |
62d5f9f7 | 4440 | int idx; |
d37a3929 | 4441 | bool px; |
62d5f9f7 | 4442 | |
8d35a259 | 4443 | amdgpu_fence_driver_sw_fini(adev); |
a5c5d8d5 | 4444 | amdgpu_device_ip_fini(adev); |
b31d3063 | 4445 | amdgpu_ucode_release(&adev->firmware.gpu_info_fw); |
d38ceaf9 | 4446 | adev->accel_working = false; |
68ce8b24 | 4447 | dma_fence_put(rcu_dereference_protected(adev->gang_submit, true)); |
04442bf7 LL |
4448 | |
4449 | amdgpu_reset_fini(adev); | |
4450 | ||
d38ceaf9 | 4451 | /* free i2c buses */ |
4562236b HW |
4452 | if (!amdgpu_device_has_dc_support(adev)) |
4453 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
4454 | |
4455 | if (amdgpu_emu_mode != 1) | |
4456 | amdgpu_atombios_fini(adev); | |
4457 | ||
d38ceaf9 AD |
4458 | kfree(adev->bios); |
4459 | adev->bios = NULL; | |
d37a3929 | 4460 | |
8a2b5139 LL |
4461 | kfree(adev->fru_info); |
4462 | adev->fru_info = NULL; | |
4463 | ||
d37a3929 OC |
4464 | px = amdgpu_device_supports_px(adev_to_drm(adev)); |
4465 | ||
7b1c6263 | 4466 | if (px || (!dev_is_removable(&adev->pdev->dev) && |
d37a3929 | 4467 | apple_gmux_detect(NULL, NULL))) |
84c8b22e | 4468 | vga_switcheroo_unregister_client(adev->pdev); |
d37a3929 OC |
4469 | |
4470 | if (px) | |
83ba126a | 4471 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
d37a3929 | 4472 | |
38d6be81 | 4473 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
b8779475 | 4474 | vga_client_unregister(adev->pdev); |
e9bc1bf7 | 4475 | |
62d5f9f7 LS |
4476 | if (drm_dev_enter(adev_to_drm(adev), &idx)) { |
4477 | ||
4478 | iounmap(adev->rmmio); | |
4479 | adev->rmmio = NULL; | |
43c064db | 4480 | amdgpu_doorbell_fini(adev); |
62d5f9f7 LS |
4481 | drm_dev_exit(idx); |
4482 | } | |
4483 | ||
d155bef0 AB |
4484 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
4485 | amdgpu_pmu_fini(adev); | |
72de33f8 | 4486 | if (adev->mman.discovery_bin) |
a190d1c7 | 4487 | amdgpu_discovery_fini(adev); |
72c8c97b | 4488 | |
cfbb6b00 AG |
4489 | amdgpu_reset_put_reset_domain(adev->reset_domain); |
4490 | adev->reset_domain = NULL; | |
4491 | ||
72c8c97b AG |
4492 | kfree(adev->pci_state); |
4493 | ||
d38ceaf9 AD |
4494 | } |
4495 | ||
58144d28 ND |
4496 | /** |
4497 | * amdgpu_device_evict_resources - evict device resources | |
4498 | * @adev: amdgpu device object | |
4499 | * | |
4500 | * Evicts all ttm device resources(vram BOs, gart table) from the lru list | |
4501 | * of the vram memory type. Mainly used for evicting device resources | |
4502 | * at suspend time. | |
4503 | * | |
4504 | */ | |
7863c155 | 4505 | static int amdgpu_device_evict_resources(struct amdgpu_device *adev) |
58144d28 | 4506 | { |
7863c155 ML |
4507 | int ret; |
4508 | ||
e53d9665 ML |
4509 | /* No need to evict vram on APUs for suspend to ram or s2idle */ |
4510 | if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU)) | |
7863c155 | 4511 | return 0; |
58144d28 | 4512 | |
7863c155 ML |
4513 | ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM); |
4514 | if (ret) | |
58144d28 | 4515 | DRM_WARN("evicting device resources failed\n"); |
7863c155 | 4516 | return ret; |
58144d28 | 4517 | } |
d38ceaf9 AD |
4518 | |
4519 | /* | |
4520 | * Suspend & resume. | |
4521 | */ | |
5095d541 ML |
4522 | /** |
4523 | * amdgpu_device_prepare - prepare for device suspend | |
4524 | * | |
4525 | * @dev: drm dev pointer | |
4526 | * | |
4527 | * Prepare to put the hw in the suspend state (all asics). | |
4528 | * Returns 0 for success or an error on failure. | |
4529 | * Called at driver suspend. | |
4530 | */ | |
4531 | int amdgpu_device_prepare(struct drm_device *dev) | |
4532 | { | |
4533 | struct amdgpu_device *adev = drm_to_adev(dev); | |
cb11ca32 | 4534 | int i, r; |
5095d541 | 4535 | |
226db360 ML |
4536 | amdgpu_choose_low_power_state(adev); |
4537 | ||
5095d541 ML |
4538 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
4539 | return 0; | |
4540 | ||
4541 | /* Evict the majority of BOs before starting suspend sequence */ | |
4542 | r = amdgpu_device_evict_resources(adev); | |
4543 | if (r) | |
226db360 | 4544 | goto unprepare; |
5095d541 | 4545 | |
cb11ca32 ML |
4546 | for (i = 0; i < adev->num_ip_blocks; i++) { |
4547 | if (!adev->ip_blocks[i].status.valid) | |
4548 | continue; | |
4549 | if (!adev->ip_blocks[i].version->funcs->prepare_suspend) | |
4550 | continue; | |
4551 | r = adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev); | |
4552 | if (r) | |
226db360 | 4553 | goto unprepare; |
cb11ca32 ML |
4554 | } |
4555 | ||
5095d541 | 4556 | return 0; |
226db360 ML |
4557 | |
4558 | unprepare: | |
4559 | adev->in_s0ix = adev->in_s3 = false; | |
4560 | ||
4561 | return r; | |
5095d541 ML |
4562 | } |
4563 | ||
d38ceaf9 | 4564 | /** |
810ddc3a | 4565 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 4566 | * |
87e3f136 | 4567 | * @dev: drm dev pointer |
87e3f136 | 4568 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
4569 | * |
4570 | * Puts the hw in the suspend state (all asics). | |
4571 | * Returns 0 for success or an error on failure. | |
4572 | * Called at driver suspend. | |
4573 | */ | |
de185019 | 4574 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 4575 | { |
a2e15b0e | 4576 | struct amdgpu_device *adev = drm_to_adev(dev); |
d7274ec7 | 4577 | int r = 0; |
d38ceaf9 | 4578 | |
d38ceaf9 AD |
4579 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
4580 | return 0; | |
4581 | ||
44779b43 | 4582 | adev->in_suspend = true; |
3fa8f89d | 4583 | |
d7274ec7 BZ |
4584 | if (amdgpu_sriov_vf(adev)) { |
4585 | amdgpu_virt_fini_data_exchange(adev); | |
4586 | r = amdgpu_virt_request_full_gpu(adev, false); | |
4587 | if (r) | |
4588 | return r; | |
4589 | } | |
4590 | ||
3fa8f89d S |
4591 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3)) |
4592 | DRM_WARN("smart shift update failed\n"); | |
4593 | ||
5f818173 | 4594 | if (fbcon) |
087451f3 | 4595 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); |
5f818173 | 4596 | |
beff74bc | 4597 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 4598 | |
5e6932fe | 4599 | amdgpu_ras_suspend(adev); |
4600 | ||
2196927b | 4601 | amdgpu_device_ip_suspend_phase1(adev); |
fe1053b7 | 4602 | |
c004d44e | 4603 | if (!adev->in_s0ix) |
5d3a2d95 | 4604 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); |
94fa5660 | 4605 | |
7863c155 ML |
4606 | r = amdgpu_device_evict_resources(adev); |
4607 | if (r) | |
4608 | return r; | |
d38ceaf9 | 4609 | |
dab96d8b AD |
4610 | amdgpu_ttm_set_buffer_funcs_status(adev, false); |
4611 | ||
8d35a259 | 4612 | amdgpu_fence_driver_hw_fini(adev); |
d38ceaf9 | 4613 | |
2196927b | 4614 | amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 4615 | |
d7274ec7 BZ |
4616 | if (amdgpu_sriov_vf(adev)) |
4617 | amdgpu_virt_release_full_gpu(adev, false); | |
4618 | ||
2e9b1523 PY |
4619 | r = amdgpu_dpm_notify_rlc_state(adev, false); |
4620 | if (r) | |
4621 | return r; | |
4622 | ||
d38ceaf9 AD |
4623 | return 0; |
4624 | } | |
4625 | ||
4626 | /** | |
810ddc3a | 4627 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 4628 | * |
87e3f136 | 4629 | * @dev: drm dev pointer |
87e3f136 | 4630 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
4631 | * |
4632 | * Bring the hw back to operating state (all asics). | |
4633 | * Returns 0 for success or an error on failure. | |
4634 | * Called at driver resume. | |
4635 | */ | |
de185019 | 4636 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 4637 | { |
1348969a | 4638 | struct amdgpu_device *adev = drm_to_adev(dev); |
03161a6e | 4639 | int r = 0; |
d38ceaf9 | 4640 | |
d7274ec7 BZ |
4641 | if (amdgpu_sriov_vf(adev)) { |
4642 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4643 | if (r) | |
4644 | return r; | |
4645 | } | |
4646 | ||
d38ceaf9 AD |
4647 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
4648 | return 0; | |
4649 | ||
62498733 | 4650 | if (adev->in_s0ix) |
bc143d8b | 4651 | amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry); |
628c36d7 | 4652 | |
d38ceaf9 | 4653 | /* post card */ |
39c640c0 | 4654 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 4655 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 4656 | if (r) |
aac89168 | 4657 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 4658 | } |
d38ceaf9 | 4659 | |
06ec9070 | 4660 | r = amdgpu_device_ip_resume(adev); |
d7274ec7 | 4661 | |
e6707218 | 4662 | if (r) { |
aac89168 | 4663 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
3c22c1ea | 4664 | goto exit; |
e6707218 | 4665 | } |
8d35a259 | 4666 | amdgpu_fence_driver_hw_init(adev); |
5ceb54c6 | 4667 | |
c004d44e | 4668 | if (!adev->in_s0ix) { |
5d3a2d95 AD |
4669 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); |
4670 | if (r) | |
3c22c1ea | 4671 | goto exit; |
5d3a2d95 | 4672 | } |
756e6880 | 4673 | |
8ed79c40 TH |
4674 | r = amdgpu_device_ip_late_init(adev); |
4675 | if (r) | |
4676 | goto exit; | |
4677 | ||
4678 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
4679 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3c22c1ea SF |
4680 | exit: |
4681 | if (amdgpu_sriov_vf(adev)) { | |
4682 | amdgpu_virt_init_data_exchange(adev); | |
4683 | amdgpu_virt_release_full_gpu(adev, true); | |
4684 | } | |
4685 | ||
4686 | if (r) | |
4687 | return r; | |
4688 | ||
96a5d8d4 | 4689 | /* Make sure IB tests flushed */ |
beff74bc | 4690 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 4691 | |
a2e15b0e | 4692 | if (fbcon) |
087451f3 | 4693 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false); |
d38ceaf9 | 4694 | |
5e6932fe | 4695 | amdgpu_ras_resume(adev); |
4696 | ||
d09ef243 AD |
4697 | if (adev->mode_info.num_crtc) { |
4698 | /* | |
4699 | * Most of the connector probing functions try to acquire runtime pm | |
4700 | * refs to ensure that the GPU is powered on when connector polling is | |
4701 | * performed. Since we're calling this from a runtime PM callback, | |
4702 | * trying to acquire rpm refs will cause us to deadlock. | |
4703 | * | |
4704 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
4705 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
4706 | */ | |
23a1a9e5 | 4707 | #ifdef CONFIG_PM |
d09ef243 | 4708 | dev->dev->power.disable_depth++; |
23a1a9e5 | 4709 | #endif |
d09ef243 AD |
4710 | if (!adev->dc_enabled) |
4711 | drm_helper_hpd_irq_event(dev); | |
4712 | else | |
4713 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 | 4714 | #ifdef CONFIG_PM |
d09ef243 | 4715 | dev->dev->power.disable_depth--; |
23a1a9e5 | 4716 | #endif |
d09ef243 | 4717 | } |
44779b43 RZ |
4718 | adev->in_suspend = false; |
4719 | ||
dc907c9d JX |
4720 | if (adev->enable_mes) |
4721 | amdgpu_mes_self_test(adev); | |
4722 | ||
3fa8f89d S |
4723 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0)) |
4724 | DRM_WARN("smart shift update failed\n"); | |
4725 | ||
4d3b9ae5 | 4726 | return 0; |
d38ceaf9 AD |
4727 | } |
4728 | ||
e3ecdffa AD |
4729 | /** |
4730 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
4731 | * | |
4732 | * @adev: amdgpu_device pointer | |
4733 | * | |
4734 | * The list of all the hardware IPs that make up the asic is walked and | |
4735 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
4736 | * if the asic is still hung or not. | |
4737 | * Returns true if any of the IPs are still in a hung state, false if not. | |
4738 | */ | |
06ec9070 | 4739 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
4740 | { |
4741 | int i; | |
4742 | bool asic_hang = false; | |
4743 | ||
f993d628 ML |
4744 | if (amdgpu_sriov_vf(adev)) |
4745 | return true; | |
4746 | ||
8bc04c29 AD |
4747 | if (amdgpu_asic_need_full_reset(adev)) |
4748 | return true; | |
4749 | ||
63fbf42f | 4750 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4751 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 4752 | continue; |
a1255107 AD |
4753 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
4754 | adev->ip_blocks[i].status.hang = | |
4755 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
4756 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 4757 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
4758 | asic_hang = true; |
4759 | } | |
4760 | } | |
4761 | return asic_hang; | |
4762 | } | |
4763 | ||
e3ecdffa AD |
4764 | /** |
4765 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
4766 | * | |
4767 | * @adev: amdgpu_device pointer | |
4768 | * | |
4769 | * The list of all the hardware IPs that make up the asic is walked and the | |
4770 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
4771 | * handles any IP specific hardware or software state changes that are | |
4772 | * necessary for a soft reset to succeed. | |
4773 | * Returns 0 on success, negative error code on failure. | |
4774 | */ | |
06ec9070 | 4775 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
4776 | { |
4777 | int i, r = 0; | |
4778 | ||
4779 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4780 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 4781 | continue; |
a1255107 AD |
4782 | if (adev->ip_blocks[i].status.hang && |
4783 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
4784 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
4785 | if (r) |
4786 | return r; | |
4787 | } | |
4788 | } | |
4789 | ||
4790 | return 0; | |
4791 | } | |
4792 | ||
e3ecdffa AD |
4793 | /** |
4794 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
4795 | * | |
4796 | * @adev: amdgpu_device pointer | |
4797 | * | |
4798 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
4799 | * reset is necessary to recover. | |
4800 | * Returns true if a full asic reset is required, false if not. | |
4801 | */ | |
06ec9070 | 4802 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 4803 | { |
da146d3b AD |
4804 | int i; |
4805 | ||
8bc04c29 AD |
4806 | if (amdgpu_asic_need_full_reset(adev)) |
4807 | return true; | |
4808 | ||
da146d3b | 4809 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4810 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 4811 | continue; |
a1255107 AD |
4812 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
4813 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
4814 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
4815 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
4816 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 4817 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 4818 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
4819 | return true; |
4820 | } | |
4821 | } | |
35d782fe CZ |
4822 | } |
4823 | return false; | |
4824 | } | |
4825 | ||
e3ecdffa AD |
4826 | /** |
4827 | * amdgpu_device_ip_soft_reset - do a soft reset | |
4828 | * | |
4829 | * @adev: amdgpu_device pointer | |
4830 | * | |
4831 | * The list of all the hardware IPs that make up the asic is walked and the | |
4832 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
4833 | * IP specific hardware or software state changes that are necessary to soft | |
4834 | * reset the IP. | |
4835 | * Returns 0 on success, negative error code on failure. | |
4836 | */ | |
06ec9070 | 4837 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4838 | { |
4839 | int i, r = 0; | |
4840 | ||
4841 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4842 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4843 | continue; |
a1255107 AD |
4844 | if (adev->ip_blocks[i].status.hang && |
4845 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
4846 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
4847 | if (r) |
4848 | return r; | |
4849 | } | |
4850 | } | |
4851 | ||
4852 | return 0; | |
4853 | } | |
4854 | ||
e3ecdffa AD |
4855 | /** |
4856 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
4857 | * | |
4858 | * @adev: amdgpu_device pointer | |
4859 | * | |
4860 | * The list of all the hardware IPs that make up the asic is walked and the | |
4861 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
4862 | * handles any IP specific hardware or software state changes that are | |
4863 | * necessary after the IP has been soft reset. | |
4864 | * Returns 0 on success, negative error code on failure. | |
4865 | */ | |
06ec9070 | 4866 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4867 | { |
4868 | int i, r = 0; | |
4869 | ||
4870 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4871 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4872 | continue; |
a1255107 AD |
4873 | if (adev->ip_blocks[i].status.hang && |
4874 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
4875 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
4876 | if (r) |
4877 | return r; | |
4878 | } | |
4879 | ||
4880 | return 0; | |
4881 | } | |
4882 | ||
e3ecdffa | 4883 | /** |
c33adbc7 | 4884 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4885 | * |
4886 | * @adev: amdgpu_device pointer | |
4887 | * | |
4888 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4889 | * restore things like GPUVM page tables after a GPU reset where | |
4890 | * the contents of VRAM might be lost. | |
403009bf CK |
4891 | * |
4892 | * Returns: | |
4893 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4894 | */ |
c33adbc7 | 4895 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4896 | { |
c41d1cf6 | 4897 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf | 4898 | struct amdgpu_bo *shadow; |
e18aaea7 | 4899 | struct amdgpu_bo_vm *vmbo; |
403009bf | 4900 | long r = 1, tmo; |
c41d1cf6 ML |
4901 | |
4902 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4903 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4904 | else |
4905 | tmo = msecs_to_jiffies(100); | |
4906 | ||
aac89168 | 4907 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4908 | mutex_lock(&adev->shadow_list_lock); |
e18aaea7 | 4909 | list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { |
4994d1f0 LC |
4910 | /* If vm is compute context or adev is APU, shadow will be NULL */ |
4911 | if (!vmbo->shadow) | |
4912 | continue; | |
4913 | shadow = vmbo->shadow; | |
4914 | ||
403009bf | 4915 | /* No need to recover an evicted BO */ |
d3116756 CK |
4916 | if (shadow->tbo.resource->mem_type != TTM_PL_TT || |
4917 | shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || | |
4918 | shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) | |
403009bf CK |
4919 | continue; |
4920 | ||
4921 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4922 | if (r) | |
4923 | break; | |
4924 | ||
c41d1cf6 | 4925 | if (fence) { |
1712fb1a | 4926 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4927 | dma_fence_put(fence); |
4928 | fence = next; | |
1712fb1a | 4929 | if (tmo == 0) { |
4930 | r = -ETIMEDOUT; | |
c41d1cf6 | 4931 | break; |
1712fb1a | 4932 | } else if (tmo < 0) { |
4933 | r = tmo; | |
4934 | break; | |
4935 | } | |
403009bf CK |
4936 | } else { |
4937 | fence = next; | |
c41d1cf6 | 4938 | } |
c41d1cf6 ML |
4939 | } |
4940 | mutex_unlock(&adev->shadow_list_lock); | |
4941 | ||
403009bf CK |
4942 | if (fence) |
4943 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4944 | dma_fence_put(fence); |
4945 | ||
1712fb1a | 4946 | if (r < 0 || tmo <= 0) { |
aac89168 | 4947 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4948 | return -EIO; |
4949 | } | |
c41d1cf6 | 4950 | |
aac89168 | 4951 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4952 | return 0; |
c41d1cf6 ML |
4953 | } |
4954 | ||
a90ad3c2 | 4955 | |
e3ecdffa | 4956 | /** |
06ec9070 | 4957 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4958 | * |
982a820b | 4959 | * @adev: amdgpu_device pointer |
87e3f136 | 4960 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4961 | * |
4962 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4963 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4964 | */ |
4965 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4966 | bool from_hypervisor) | |
5740682e ML |
4967 | { |
4968 | int r; | |
a5f67c93 | 4969 | struct amdgpu_hive_info *hive = NULL; |
7258fa31 | 4970 | int retry_limit = 0; |
5740682e | 4971 | |
7258fa31 | 4972 | retry: |
c004d44e | 4973 | amdgpu_amdkfd_pre_reset(adev); |
428890a3 | 4974 | |
5740682e ML |
4975 | if (from_hypervisor) |
4976 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4977 | else | |
4978 | r = amdgpu_virt_reset_gpu(adev); | |
4979 | if (r) | |
4980 | return r; | |
f734b213 | 4981 | amdgpu_irq_gpu_reset_resume_helper(adev); |
a90ad3c2 | 4982 | |
83f24a8f HC |
4983 | /* some sw clean up VF needs to do before recover */ |
4984 | amdgpu_virt_post_reset(adev); | |
4985 | ||
a90ad3c2 | 4986 | /* Resume IP prior to SMC */ |
06ec9070 | 4987 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4988 | if (r) |
4989 | goto error; | |
a90ad3c2 | 4990 | |
c9ffa427 | 4991 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4992 | |
7a3e0bb2 RZ |
4993 | r = amdgpu_device_fw_loading(adev); |
4994 | if (r) | |
4995 | return r; | |
4996 | ||
a90ad3c2 | 4997 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4998 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4999 | if (r) |
5000 | goto error; | |
a90ad3c2 | 5001 | |
a5f67c93 ZL |
5002 | hive = amdgpu_get_xgmi_hive(adev); |
5003 | /* Update PSP FW topology after reset */ | |
5004 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) | |
5005 | r = amdgpu_xgmi_update_topology(hive, adev); | |
5006 | ||
5007 | if (hive) | |
5008 | amdgpu_put_xgmi_hive(hive); | |
5009 | ||
5010 | if (!r) { | |
a5f67c93 | 5011 | r = amdgpu_ib_ring_tests(adev); |
9c12f5cd | 5012 | |
c004d44e | 5013 | amdgpu_amdkfd_post_reset(adev); |
a5f67c93 | 5014 | } |
a90ad3c2 | 5015 | |
abc34253 | 5016 | error: |
c41d1cf6 | 5017 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 5018 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 5019 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 | 5020 | } |
437f3e0b | 5021 | amdgpu_virt_release_full_gpu(adev, true); |
a90ad3c2 | 5022 | |
7258fa31 SK |
5023 | if (AMDGPU_RETRY_SRIOV_RESET(r)) { |
5024 | if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) { | |
5025 | retry_limit++; | |
5026 | goto retry; | |
5027 | } else | |
5028 | DRM_ERROR("GPU reset retry is beyond the retry limit\n"); | |
5029 | } | |
5030 | ||
a90ad3c2 ML |
5031 | return r; |
5032 | } | |
5033 | ||
9a1cddd6 | 5034 | /** |
5035 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
5036 | * | |
982a820b | 5037 | * @adev: amdgpu_device pointer |
9a1cddd6 | 5038 | * |
5039 | * check if there is any job in mirror list | |
5040 | */ | |
5041 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
5042 | { | |
5043 | int i; | |
5044 | struct drm_sched_job *job; | |
5045 | ||
5046 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5047 | struct amdgpu_ring *ring = adev->rings[i]; | |
5048 | ||
9749c868 | 5049 | if (!amdgpu_ring_sched_ready(ring)) |
9a1cddd6 | 5050 | continue; |
5051 | ||
5052 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
5053 | job = list_first_entry_or_null(&ring->sched.pending_list, |
5054 | struct drm_sched_job, list); | |
9a1cddd6 | 5055 | spin_unlock(&ring->sched.job_list_lock); |
5056 | if (job) | |
5057 | return true; | |
5058 | } | |
5059 | return false; | |
5060 | } | |
5061 | ||
12938fad CK |
5062 | /** |
5063 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
5064 | * | |
982a820b | 5065 | * @adev: amdgpu_device pointer |
12938fad CK |
5066 | * |
5067 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
5068 | * a hung GPU. | |
5069 | */ | |
5070 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
5071 | { | |
12938fad | 5072 | |
3ba7b418 AG |
5073 | if (amdgpu_gpu_recovery == 0) |
5074 | goto disabled; | |
5075 | ||
1a11a65d YC |
5076 | /* Skip soft reset check in fatal error mode */ |
5077 | if (!amdgpu_ras_is_poison_mode_supported(adev)) | |
5078 | return true; | |
5079 | ||
3ba7b418 AG |
5080 | if (amdgpu_sriov_vf(adev)) |
5081 | return true; | |
5082 | ||
5083 | if (amdgpu_gpu_recovery == -1) { | |
5084 | switch (adev->asic_type) { | |
b3523c45 AD |
5085 | #ifdef CONFIG_DRM_AMDGPU_SI |
5086 | case CHIP_VERDE: | |
5087 | case CHIP_TAHITI: | |
5088 | case CHIP_PITCAIRN: | |
5089 | case CHIP_OLAND: | |
5090 | case CHIP_HAINAN: | |
5091 | #endif | |
5092 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
5093 | case CHIP_KAVERI: | |
5094 | case CHIP_KABINI: | |
5095 | case CHIP_MULLINS: | |
5096 | #endif | |
5097 | case CHIP_CARRIZO: | |
5098 | case CHIP_STONEY: | |
5099 | case CHIP_CYAN_SKILLFISH: | |
3ba7b418 | 5100 | goto disabled; |
b3523c45 AD |
5101 | default: |
5102 | break; | |
3ba7b418 | 5103 | } |
12938fad CK |
5104 | } |
5105 | ||
5106 | return true; | |
3ba7b418 AG |
5107 | |
5108 | disabled: | |
aac89168 | 5109 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 5110 | return false; |
12938fad CK |
5111 | } |
5112 | ||
5c03e584 FX |
5113 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
5114 | { | |
47fc644f SS |
5115 | u32 i; |
5116 | int ret = 0; | |
5c03e584 | 5117 | |
47fc644f | 5118 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); |
5c03e584 | 5119 | |
47fc644f | 5120 | dev_info(adev->dev, "GPU mode1 reset\n"); |
5c03e584 | 5121 | |
47fc644f SS |
5122 | /* disable BM */ |
5123 | pci_clear_master(adev->pdev); | |
5c03e584 | 5124 | |
47fc644f | 5125 | amdgpu_device_cache_pci_state(adev->pdev); |
5c03e584 | 5126 | |
47fc644f SS |
5127 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { |
5128 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
5129 | ret = amdgpu_dpm_mode1_reset(adev); | |
5130 | } else { | |
5131 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
5132 | ret = psp_gpu_reset(adev); | |
5133 | } | |
5c03e584 | 5134 | |
47fc644f | 5135 | if (ret) |
7d442437 | 5136 | goto mode1_reset_failed; |
5c03e584 | 5137 | |
47fc644f | 5138 | amdgpu_device_load_pci_state(adev->pdev); |
7656168a LL |
5139 | ret = amdgpu_psp_wait_for_bootloader(adev); |
5140 | if (ret) | |
7d442437 | 5141 | goto mode1_reset_failed; |
5c03e584 | 5142 | |
47fc644f SS |
5143 | /* wait for asic to come out of reset */ |
5144 | for (i = 0; i < adev->usec_timeout; i++) { | |
5145 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
5c03e584 | 5146 | |
47fc644f SS |
5147 | if (memsize != 0xffffffff) |
5148 | break; | |
5149 | udelay(1); | |
5150 | } | |
5c03e584 | 5151 | |
7d442437 HZ |
5152 | if (i >= adev->usec_timeout) { |
5153 | ret = -ETIMEDOUT; | |
5154 | goto mode1_reset_failed; | |
5155 | } | |
5156 | ||
47fc644f | 5157 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); |
7656168a | 5158 | |
7d442437 HZ |
5159 | return 0; |
5160 | ||
5161 | mode1_reset_failed: | |
5162 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
47fc644f | 5163 | return ret; |
5c03e584 | 5164 | } |
5c6dd71e | 5165 | |
e3c1b071 | 5166 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
04442bf7 | 5167 | struct amdgpu_reset_context *reset_context) |
26bc5340 | 5168 | { |
5c1e6fa4 | 5169 | int i, r = 0; |
04442bf7 LL |
5170 | struct amdgpu_job *job = NULL; |
5171 | bool need_full_reset = | |
5172 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
5173 | ||
5174 | if (reset_context->reset_req_dev == adev) | |
5175 | job = reset_context->job; | |
71182665 | 5176 | |
b602ca5f TZ |
5177 | if (amdgpu_sriov_vf(adev)) { |
5178 | /* stop the data exchange thread */ | |
5179 | amdgpu_virt_fini_data_exchange(adev); | |
5180 | } | |
5181 | ||
9e225fb9 AG |
5182 | amdgpu_fence_driver_isr_toggle(adev, true); |
5183 | ||
71182665 | 5184 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
5185 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5186 | struct amdgpu_ring *ring = adev->rings[i]; | |
5187 | ||
9749c868 | 5188 | if (!amdgpu_ring_sched_ready(ring)) |
0875dc9e | 5189 | continue; |
5740682e | 5190 | |
b8920e1e SS |
5191 | /* Clear job fence from fence drv to avoid force_completion |
5192 | * leave NULL and vm flush fence in fence drv | |
5193 | */ | |
5c1e6fa4 | 5194 | amdgpu_fence_driver_clear_job_fences(ring); |
c530b02f | 5195 | |
2f9d4084 ML |
5196 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
5197 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 5198 | } |
d38ceaf9 | 5199 | |
9e225fb9 AG |
5200 | amdgpu_fence_driver_isr_toggle(adev, false); |
5201 | ||
ff99849b | 5202 | if (job && job->vm) |
222b5f04 AG |
5203 | drm_sched_increase_karma(&job->base); |
5204 | ||
04442bf7 | 5205 | r = amdgpu_reset_prepare_hwcontext(adev, reset_context); |
404b277b | 5206 | /* If reset handler not implemented, continue; otherwise return */ |
b8920e1e | 5207 | if (r == -EOPNOTSUPP) |
404b277b LL |
5208 | r = 0; |
5209 | else | |
04442bf7 LL |
5210 | return r; |
5211 | ||
1d721ed6 | 5212 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
5213 | if (!amdgpu_sriov_vf(adev)) { |
5214 | ||
5215 | if (!need_full_reset) | |
5216 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
5217 | ||
360cd081 LG |
5218 | if (!need_full_reset && amdgpu_gpu_recovery && |
5219 | amdgpu_device_ip_check_soft_reset(adev)) { | |
26bc5340 AG |
5220 | amdgpu_device_ip_pre_soft_reset(adev); |
5221 | r = amdgpu_device_ip_soft_reset(adev); | |
5222 | amdgpu_device_ip_post_soft_reset(adev); | |
5223 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 5224 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
5225 | need_full_reset = true; |
5226 | } | |
5227 | } | |
5228 | ||
5229 | if (need_full_reset) | |
5230 | r = amdgpu_device_ip_suspend(adev); | |
04442bf7 LL |
5231 | if (need_full_reset) |
5232 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
5233 | else | |
5234 | clear_bit(AMDGPU_NEED_FULL_RESET, | |
5235 | &reset_context->flags); | |
26bc5340 AG |
5236 | } |
5237 | ||
5238 | return r; | |
5239 | } | |
5240 | ||
15fd09a0 SA |
5241 | static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev) |
5242 | { | |
15fd09a0 SA |
5243 | int i; |
5244 | ||
38a15ad9 | 5245 | lockdep_assert_held(&adev->reset_domain->sem); |
15fd09a0 | 5246 | |
2d6a2a28 AA |
5247 | for (i = 0; i < adev->reset_info.num_regs; i++) { |
5248 | adev->reset_info.reset_dump_reg_value[i] = | |
5249 | RREG32(adev->reset_info.reset_dump_reg_list[i]); | |
3d8785f6 | 5250 | |
2d6a2a28 AA |
5251 | trace_amdgpu_reset_reg_dumps(adev->reset_info.reset_dump_reg_list[i], |
5252 | adev->reset_info.reset_dump_reg_value[i]); | |
3d8785f6 SA |
5253 | } |
5254 | ||
15fd09a0 | 5255 | return 0; |
3d8785f6 | 5256 | } |
3d8785f6 | 5257 | |
04442bf7 LL |
5258 | int amdgpu_do_asic_reset(struct list_head *device_list_handle, |
5259 | struct amdgpu_reset_context *reset_context) | |
26bc5340 AG |
5260 | { |
5261 | struct amdgpu_device *tmp_adev = NULL; | |
04442bf7 | 5262 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
26bc5340 AG |
5263 | int r = 0; |
5264 | ||
04442bf7 LL |
5265 | /* Try reset handler method first */ |
5266 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
5267 | reset_list); | |
15fd09a0 | 5268 | amdgpu_reset_reg_dumps(tmp_adev); |
0a83bb35 LL |
5269 | |
5270 | reset_context->reset_device_list = device_list_handle; | |
04442bf7 | 5271 | r = amdgpu_reset_perform_reset(tmp_adev, reset_context); |
404b277b | 5272 | /* If reset handler not implemented, continue; otherwise return */ |
b8920e1e | 5273 | if (r == -EOPNOTSUPP) |
404b277b LL |
5274 | r = 0; |
5275 | else | |
04442bf7 LL |
5276 | return r; |
5277 | ||
5278 | /* Reset handler not implemented, use the default method */ | |
5279 | need_full_reset = | |
5280 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
5281 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); | |
5282 | ||
26bc5340 | 5283 | /* |
655ce9cb | 5284 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
5285 | * to allow proper links negotiation in FW (within 1 sec) |
5286 | */ | |
7ac71382 | 5287 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 5288 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 5289 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 5290 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 5291 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 5292 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
5293 | r = -EALREADY; |
5294 | } else | |
5295 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 5296 | |
041a62bc | 5297 | if (r) { |
aac89168 | 5298 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 5299 | r, adev_to_drm(tmp_adev)->unique); |
19349072 | 5300 | goto out; |
ce316fa5 LM |
5301 | } |
5302 | } | |
5303 | ||
041a62bc AG |
5304 | /* For XGMI wait for all resets to complete before proceed */ |
5305 | if (!r) { | |
655ce9cb | 5306 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
5307 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
5308 | flush_work(&tmp_adev->xgmi_reset_work); | |
5309 | r = tmp_adev->asic_reset_res; | |
5310 | if (r) | |
5311 | break; | |
ce316fa5 LM |
5312 | } |
5313 | } | |
5314 | } | |
ce316fa5 | 5315 | } |
26bc5340 | 5316 | |
43c4d576 | 5317 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 5318 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
21226f02 | 5319 | amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB); |
43c4d576 JC |
5320 | } |
5321 | ||
00eaa571 | 5322 | amdgpu_ras_intr_cleared(); |
43c4d576 | 5323 | } |
00eaa571 | 5324 | |
655ce9cb | 5325 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
5326 | if (need_full_reset) { |
5327 | /* post card */ | |
1b6ef74b | 5328 | amdgpu_ras_set_fed(tmp_adev, false); |
e3c1b071 | 5329 | r = amdgpu_device_asic_init(tmp_adev); |
5330 | if (r) { | |
aac89168 | 5331 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 5332 | } else { |
26bc5340 | 5333 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
9cec53c1 | 5334 | |
26bc5340 AG |
5335 | r = amdgpu_device_ip_resume_phase1(tmp_adev); |
5336 | if (r) | |
5337 | goto out; | |
5338 | ||
5339 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
a7691785 AA |
5340 | |
5341 | amdgpu_coredump(tmp_adev, vram_lost, reset_context); | |
5342 | ||
26bc5340 | 5343 | if (vram_lost) { |
77e7f829 | 5344 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 5345 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
5346 | } |
5347 | ||
26bc5340 AG |
5348 | r = amdgpu_device_fw_loading(tmp_adev); |
5349 | if (r) | |
5350 | return r; | |
5351 | ||
c45e38f2 LL |
5352 | r = amdgpu_xcp_restore_partition_mode( |
5353 | tmp_adev->xcp_mgr); | |
5354 | if (r) | |
5355 | goto out; | |
5356 | ||
26bc5340 AG |
5357 | r = amdgpu_device_ip_resume_phase2(tmp_adev); |
5358 | if (r) | |
5359 | goto out; | |
5360 | ||
b7043800 AD |
5361 | if (tmp_adev->mman.buffer_funcs_ring->sched.ready) |
5362 | amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); | |
5363 | ||
26bc5340 AG |
5364 | if (vram_lost) |
5365 | amdgpu_device_fill_reset_magic(tmp_adev); | |
5366 | ||
fdafb359 EQ |
5367 | /* |
5368 | * Add this ASIC as tracked as reset was already | |
5369 | * complete successfully. | |
5370 | */ | |
5371 | amdgpu_register_gpu_instance(tmp_adev); | |
5372 | ||
04442bf7 LL |
5373 | if (!reset_context->hive && |
5374 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
e3c1b071 | 5375 | amdgpu_xgmi_add_device(tmp_adev); |
5376 | ||
7c04ca50 | 5377 | r = amdgpu_device_ip_late_init(tmp_adev); |
5378 | if (r) | |
5379 | goto out; | |
5380 | ||
087451f3 | 5381 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false); |
565d1941 | 5382 | |
e8fbaf03 GC |
5383 | /* |
5384 | * The GPU enters bad state once faulty pages | |
5385 | * by ECC has reached the threshold, and ras | |
5386 | * recovery is scheduled next. So add one check | |
5387 | * here to break recovery if it indeed exceeds | |
5388 | * bad page threshold, and remind user to | |
5389 | * retire this GPU or setting one bigger | |
5390 | * bad_page_threshold value to fix this once | |
5391 | * probing driver again. | |
5392 | */ | |
11003c68 | 5393 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
5394 | /* must succeed. */ |
5395 | amdgpu_ras_resume(tmp_adev); | |
5396 | } else { | |
5397 | r = -EINVAL; | |
5398 | goto out; | |
5399 | } | |
e79a04d5 | 5400 | |
26bc5340 | 5401 | /* Update PSP FW topology after reset */ |
04442bf7 LL |
5402 | if (reset_context->hive && |
5403 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
5404 | r = amdgpu_xgmi_update_topology( | |
5405 | reset_context->hive, tmp_adev); | |
26bc5340 AG |
5406 | } |
5407 | } | |
5408 | ||
26bc5340 AG |
5409 | out: |
5410 | if (!r) { | |
5411 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
5412 | r = amdgpu_ib_ring_tests(tmp_adev); | |
5413 | if (r) { | |
5414 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
26bc5340 AG |
5415 | need_full_reset = true; |
5416 | r = -EAGAIN; | |
5417 | goto end; | |
5418 | } | |
5419 | } | |
5420 | ||
5421 | if (!r) | |
5422 | r = amdgpu_device_recover_vram(tmp_adev); | |
5423 | else | |
5424 | tmp_adev->asic_reset_res = r; | |
5425 | } | |
5426 | ||
5427 | end: | |
04442bf7 LL |
5428 | if (need_full_reset) |
5429 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
5430 | else | |
5431 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 AG |
5432 | return r; |
5433 | } | |
5434 | ||
e923be99 | 5435 | static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev) |
26bc5340 | 5436 | { |
5740682e | 5437 | |
a3a09142 AD |
5438 | switch (amdgpu_asic_reset_method(adev)) { |
5439 | case AMD_RESET_METHOD_MODE1: | |
5440 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
5441 | break; | |
5442 | case AMD_RESET_METHOD_MODE2: | |
5443 | adev->mp1_state = PP_MP1_STATE_RESET; | |
5444 | break; | |
5445 | default: | |
5446 | adev->mp1_state = PP_MP1_STATE_NONE; | |
5447 | break; | |
5448 | } | |
26bc5340 | 5449 | } |
d38ceaf9 | 5450 | |
e923be99 | 5451 | static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev) |
26bc5340 | 5452 | { |
89041940 | 5453 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 5454 | adev->mp1_state = PP_MP1_STATE_NONE; |
91fb309d HC |
5455 | } |
5456 | ||
3f12acc8 EQ |
5457 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
5458 | { | |
5459 | struct pci_dev *p = NULL; | |
5460 | ||
5461 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
5462 | adev->pdev->bus->number, 1); | |
5463 | if (p) { | |
5464 | pm_runtime_enable(&(p->dev)); | |
5465 | pm_runtime_resume(&(p->dev)); | |
5466 | } | |
b85e285e YY |
5467 | |
5468 | pci_dev_put(p); | |
3f12acc8 EQ |
5469 | } |
5470 | ||
5471 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
5472 | { | |
5473 | enum amd_reset_method reset_method; | |
5474 | struct pci_dev *p = NULL; | |
5475 | u64 expires; | |
5476 | ||
5477 | /* | |
5478 | * For now, only BACO and mode1 reset are confirmed | |
5479 | * to suffer the audio issue without proper suspended. | |
5480 | */ | |
5481 | reset_method = amdgpu_asic_reset_method(adev); | |
5482 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
5483 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
5484 | return -EINVAL; | |
5485 | ||
5486 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
5487 | adev->pdev->bus->number, 1); | |
5488 | if (!p) | |
5489 | return -ENODEV; | |
5490 | ||
5491 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
5492 | if (!expires) | |
5493 | /* | |
5494 | * If we cannot get the audio device autosuspend delay, | |
5495 | * a fixed 4S interval will be used. Considering 3S is | |
5496 | * the audio controller default autosuspend delay setting. | |
5497 | * 4S used here is guaranteed to cover that. | |
5498 | */ | |
54b7feb9 | 5499 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
5500 | |
5501 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
5502 | if (!pm_runtime_suspend(&(p->dev))) | |
5503 | break; | |
5504 | ||
5505 | if (expires < ktime_get_mono_fast_ns()) { | |
5506 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
b85e285e | 5507 | pci_dev_put(p); |
3f12acc8 EQ |
5508 | /* TODO: abort the succeeding gpu reset? */ |
5509 | return -ETIMEDOUT; | |
5510 | } | |
5511 | } | |
5512 | ||
5513 | pm_runtime_disable(&(p->dev)); | |
5514 | ||
b85e285e | 5515 | pci_dev_put(p); |
3f12acc8 EQ |
5516 | return 0; |
5517 | } | |
5518 | ||
d193b12b | 5519 | static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) |
247c7b0d AG |
5520 | { |
5521 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
5522 | ||
5523 | #if defined(CONFIG_DEBUG_FS) | |
5524 | if (!amdgpu_sriov_vf(adev)) | |
5525 | cancel_work(&adev->reset_work); | |
5526 | #endif | |
5527 | ||
5528 | if (adev->kfd.dev) | |
5529 | cancel_work(&adev->kfd.reset_work); | |
5530 | ||
5531 | if (amdgpu_sriov_vf(adev)) | |
5532 | cancel_work(&adev->virt.flr_work); | |
5533 | ||
5534 | if (con && adev->ras_enabled) | |
5535 | cancel_work(&con->recovery_work); | |
5536 | ||
5537 | } | |
5538 | ||
26bc5340 | 5539 | /** |
6e9c65f7 | 5540 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler |
26bc5340 | 5541 | * |
982a820b | 5542 | * @adev: amdgpu_device pointer |
26bc5340 | 5543 | * @job: which job trigger hang |
80bd2de1 | 5544 | * @reset_context: amdgpu reset context pointer |
26bc5340 AG |
5545 | * |
5546 | * Attempt to reset the GPU if it has hung (all asics). | |
5547 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
5548 | * Returns 0 for success or an error on failure. | |
5549 | */ | |
5550 | ||
cf727044 | 5551 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
f1549c09 LG |
5552 | struct amdgpu_job *job, |
5553 | struct amdgpu_reset_context *reset_context) | |
26bc5340 | 5554 | { |
1d721ed6 | 5555 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 | 5556 | bool job_signaled = false; |
26bc5340 | 5557 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 5558 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 5559 | int i, r = 0; |
bb5c7235 | 5560 | bool need_emergency_restart = false; |
3f12acc8 | 5561 | bool audio_suspended = false; |
26bc5340 | 5562 | |
6e3cd2a9 | 5563 | /* |
bb5c7235 WS |
5564 | * Special case: RAS triggered and full reset isn't supported |
5565 | */ | |
5566 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
5567 | ||
d5ea093e AG |
5568 | /* |
5569 | * Flush RAM to disk so that after reboot | |
5570 | * the user can read log and see why the system rebooted. | |
5571 | */ | |
80285ae1 SY |
5572 | if (need_emergency_restart && amdgpu_ras_get_context(adev) && |
5573 | amdgpu_ras_get_context(adev)->reboot) { | |
d5ea093e AG |
5574 | DRM_WARN("Emergency reboot."); |
5575 | ||
5576 | ksys_sync_helper(); | |
5577 | emergency_restart(); | |
5578 | } | |
5579 | ||
b823821f | 5580 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 5581 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 | 5582 | |
175ac6ec ZL |
5583 | if (!amdgpu_sriov_vf(adev)) |
5584 | hive = amdgpu_get_xgmi_hive(adev); | |
681260df | 5585 | if (hive) |
53b3f8f4 | 5586 | mutex_lock(&hive->hive_lock); |
26bc5340 | 5587 | |
f1549c09 LG |
5588 | reset_context->job = job; |
5589 | reset_context->hive = hive; | |
9e94d22c EQ |
5590 | /* |
5591 | * Build list of devices to reset. | |
5592 | * In case we are in XGMI hive mode, resort the device list | |
5593 | * to put adev in the 1st position. | |
5594 | */ | |
5595 | INIT_LIST_HEAD(&device_list); | |
175ac6ec | 5596 | if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) { |
83d29a5f | 5597 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { |
655ce9cb | 5598 | list_add_tail(&tmp_adev->reset_list, &device_list); |
087a3e13 | 5599 | if (adev->shutdown) |
83d29a5f YC |
5600 | tmp_adev->shutdown = true; |
5601 | } | |
655ce9cb | 5602 | if (!list_is_first(&adev->reset_list, &device_list)) |
5603 | list_rotate_to_front(&adev->reset_list, &device_list); | |
5604 | device_list_handle = &device_list; | |
26bc5340 | 5605 | } else { |
655ce9cb | 5606 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
5607 | device_list_handle = &device_list; |
5608 | } | |
5609 | ||
e923be99 AG |
5610 | /* We need to lock reset domain only once both for XGMI and single device */ |
5611 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
5612 | reset_list); | |
3675c2f2 | 5613 | amdgpu_device_lock_reset_domain(tmp_adev->reset_domain); |
e923be99 | 5614 | |
1d721ed6 | 5615 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 5616 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
f287a3c5 | 5617 | |
e923be99 | 5618 | amdgpu_device_set_mp1_state(tmp_adev); |
f287a3c5 | 5619 | |
3f12acc8 EQ |
5620 | /* |
5621 | * Try to put the audio codec into suspend state | |
5622 | * before gpu reset started. | |
5623 | * | |
5624 | * Due to the power domain of the graphics device | |
5625 | * is shared with AZ power domain. Without this, | |
5626 | * we may change the audio hardware from behind | |
5627 | * the audio driver's back. That will trigger | |
5628 | * some audio codec errors. | |
5629 | */ | |
5630 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
5631 | audio_suspended = true; | |
5632 | ||
9e94d22c EQ |
5633 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
5634 | ||
52fb44cf EQ |
5635 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
5636 | ||
c004d44e | 5637 | if (!amdgpu_sriov_vf(tmp_adev)) |
428890a3 | 5638 | amdgpu_amdkfd_pre_reset(tmp_adev); |
9e94d22c | 5639 | |
12ffa55d AG |
5640 | /* |
5641 | * Mark these ASICs to be reseted as untracked first | |
5642 | * And add them back after reset completed | |
5643 | */ | |
5644 | amdgpu_unregister_gpu_instance(tmp_adev); | |
5645 | ||
163d4cd2 | 5646 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true); |
565d1941 | 5647 | |
f1c1314b | 5648 | /* disable ras on ALL IPs */ |
bb5c7235 | 5649 | if (!need_emergency_restart && |
b823821f | 5650 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 5651 | amdgpu_ras_suspend(tmp_adev); |
5652 | ||
1d721ed6 AG |
5653 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5654 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5655 | ||
9749c868 | 5656 | if (!amdgpu_ring_sched_ready(ring)) |
1d721ed6 AG |
5657 | continue; |
5658 | ||
0b2d2c2e | 5659 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 5660 | |
bb5c7235 | 5661 | if (need_emergency_restart) |
7c6e68c7 | 5662 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 5663 | } |
8f8c80f4 | 5664 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
5665 | } |
5666 | ||
bb5c7235 | 5667 | if (need_emergency_restart) |
7c6e68c7 AG |
5668 | goto skip_sched_resume; |
5669 | ||
1d721ed6 AG |
5670 | /* |
5671 | * Must check guilty signal here since after this point all old | |
5672 | * HW fences are force signaled. | |
5673 | * | |
5674 | * job->base holds a reference to parent fence | |
5675 | */ | |
f6a3f660 | 5676 | if (job && dma_fence_is_signaled(&job->hw_fence)) { |
1d721ed6 | 5677 | job_signaled = true; |
1d721ed6 AG |
5678 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
5679 | goto skip_hw_reset; | |
5680 | } | |
5681 | ||
26bc5340 | 5682 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 5683 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
f1549c09 | 5684 | r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); |
26bc5340 AG |
5685 | /*TODO Should we stop ?*/ |
5686 | if (r) { | |
aac89168 | 5687 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 5688 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
5689 | tmp_adev->asic_reset_res = r; |
5690 | } | |
247c7b0d AG |
5691 | |
5692 | /* | |
5693 | * Drop all pending non scheduler resets. Scheduler resets | |
5694 | * were already dropped during drm_sched_stop | |
5695 | */ | |
d193b12b | 5696 | amdgpu_device_stop_pending_resets(tmp_adev); |
26bc5340 AG |
5697 | } |
5698 | ||
5699 | /* Actual ASIC resets if needed.*/ | |
4f30d920 | 5700 | /* Host driver will handle XGMI hive reset for SRIOV */ |
26bc5340 AG |
5701 | if (amdgpu_sriov_vf(adev)) { |
5702 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
5703 | if (r) | |
5704 | adev->asic_reset_res = r; | |
950d6425 | 5705 | |
28606c4e | 5706 | /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */ |
4e8303cf LL |
5707 | if (amdgpu_ip_version(adev, GC_HWIP, 0) == |
5708 | IP_VERSION(9, 4, 2) || | |
adb4d6a4 | 5709 | amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || |
4e8303cf | 5710 | amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) |
950d6425 | 5711 | amdgpu_ras_resume(adev); |
26bc5340 | 5712 | } else { |
f1549c09 | 5713 | r = amdgpu_do_asic_reset(device_list_handle, reset_context); |
b98a1648 | 5714 | if (r && r == -EAGAIN) |
26bc5340 AG |
5715 | goto retry; |
5716 | } | |
5717 | ||
1d721ed6 AG |
5718 | skip_hw_reset: |
5719 | ||
26bc5340 | 5720 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 5721 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 5722 | |
1d721ed6 AG |
5723 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5724 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5725 | ||
9749c868 | 5726 | if (!amdgpu_ring_sched_ready(ring)) |
1d721ed6 AG |
5727 | continue; |
5728 | ||
6868a2c4 | 5729 | drm_sched_start(&ring->sched, true); |
1d721ed6 AG |
5730 | } |
5731 | ||
b8920e1e | 5732 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) |
4a580877 | 5733 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 | 5734 | |
7258fa31 SK |
5735 | if (tmp_adev->asic_reset_res) |
5736 | r = tmp_adev->asic_reset_res; | |
5737 | ||
1d721ed6 | 5738 | tmp_adev->asic_reset_res = 0; |
26bc5340 AG |
5739 | |
5740 | if (r) { | |
5741 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 5742 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
5743 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
5744 | } else { | |
12ffa55d | 5745 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
3fa8f89d S |
5746 | if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0)) |
5747 | DRM_WARN("smart shift update failed\n"); | |
26bc5340 | 5748 | } |
7c6e68c7 | 5749 | } |
26bc5340 | 5750 | |
7c6e68c7 | 5751 | skip_sched_resume: |
655ce9cb | 5752 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
428890a3 | 5753 | /* unlock kfd: SRIOV would do it separately */ |
c004d44e | 5754 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
428890a3 | 5755 | amdgpu_amdkfd_post_reset(tmp_adev); |
8e2712e7 | 5756 | |
5757 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
5758 | * need to bring up kfd here if it's not be initialized before | |
5759 | */ | |
5760 | if (!adev->kfd.init_complete) | |
5761 | amdgpu_amdkfd_device_init(adev); | |
5762 | ||
3f12acc8 EQ |
5763 | if (audio_suspended) |
5764 | amdgpu_device_resume_display_audio(tmp_adev); | |
e923be99 AG |
5765 | |
5766 | amdgpu_device_unset_mp1_state(tmp_adev); | |
d293470e YC |
5767 | |
5768 | amdgpu_ras_set_error_query_ready(tmp_adev, true); | |
26bc5340 AG |
5769 | } |
5770 | ||
e923be99 AG |
5771 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, |
5772 | reset_list); | |
5773 | amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain); | |
5774 | ||
9e94d22c | 5775 | if (hive) { |
9e94d22c | 5776 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 5777 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 5778 | } |
26bc5340 | 5779 | |
f287a3c5 | 5780 | if (r) |
26bc5340 | 5781 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
ab9a0b1f AG |
5782 | |
5783 | atomic_set(&adev->reset_domain->reset_res, r); | |
d38ceaf9 AD |
5784 | return r; |
5785 | } | |
5786 | ||
466a7d11 ML |
5787 | /** |
5788 | * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner | |
5789 | * | |
5790 | * @adev: amdgpu_device pointer | |
5791 | * @speed: pointer to the speed of the link | |
5792 | * @width: pointer to the width of the link | |
5793 | * | |
5794 | * Evaluate the hierarchy to find the speed and bandwidth capabilities of the | |
5795 | * first physical partner to an AMD dGPU. | |
5796 | * This will exclude any virtual switches and links. | |
5797 | */ | |
5798 | static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev, | |
5799 | enum pci_bus_speed *speed, | |
5800 | enum pcie_link_width *width) | |
5801 | { | |
5802 | struct pci_dev *parent = adev->pdev; | |
5803 | ||
5804 | if (!speed || !width) | |
5805 | return; | |
5806 | ||
5807 | *speed = PCI_SPEED_UNKNOWN; | |
5808 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
5809 | ||
5810 | while ((parent = pci_upstream_bridge(parent))) { | |
5811 | /* skip upstream/downstream switches internal to dGPU*/ | |
5812 | if (parent->vendor == PCI_VENDOR_ID_ATI) | |
5813 | continue; | |
5814 | *speed = pcie_get_speed_cap(parent); | |
5815 | *width = pcie_get_width_cap(parent); | |
5816 | break; | |
5817 | } | |
5818 | } | |
5819 | ||
e3ecdffa AD |
5820 | /** |
5821 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
5822 | * | |
5823 | * @adev: amdgpu_device pointer | |
5824 | * | |
5825 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
5826 | * and lanes) of the slot the device is in. Handles APUs and | |
5827 | * virtualized environments where PCIE config space may not be available. | |
5828 | */ | |
5494d864 | 5829 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 5830 | { |
5d9a6330 | 5831 | struct pci_dev *pdev; |
c5313457 HK |
5832 | enum pci_bus_speed speed_cap, platform_speed_cap; |
5833 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 5834 | |
cd474ba0 AD |
5835 | if (amdgpu_pcie_gen_cap) |
5836 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 5837 | |
cd474ba0 AD |
5838 | if (amdgpu_pcie_lane_cap) |
5839 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 5840 | |
cd474ba0 | 5841 | /* covers APUs as well */ |
04e85958 | 5842 | if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) { |
cd474ba0 AD |
5843 | if (adev->pm.pcie_gen_mask == 0) |
5844 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
5845 | if (adev->pm.pcie_mlw_mask == 0) | |
5846 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 5847 | return; |
cd474ba0 | 5848 | } |
d0dd7f0c | 5849 | |
c5313457 HK |
5850 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
5851 | return; | |
5852 | ||
466a7d11 ML |
5853 | amdgpu_device_partner_bandwidth(adev, &platform_speed_cap, |
5854 | &platform_link_width); | |
c5313457 | 5855 | |
cd474ba0 | 5856 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
5857 | /* asic caps */ |
5858 | pdev = adev->pdev; | |
5859 | speed_cap = pcie_get_speed_cap(pdev); | |
5860 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
5861 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
5862 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
5863 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 5864 | } else { |
2b3a1f51 FX |
5865 | if (speed_cap == PCIE_SPEED_32_0GT) |
5866 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5867 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5868 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5869 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5870 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5871 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5872 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5873 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5874 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5875 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
5876 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
5877 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5878 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5879 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
5880 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
5881 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5882 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5883 | else | |
5884 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5885 | } | |
5886 | /* platform caps */ | |
c5313457 | 5887 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
5888 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5889 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5890 | } else { | |
2b3a1f51 FX |
5891 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
5892 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5893 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5894 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5895 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5896 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5897 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5898 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5899 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5900 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5901 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 5902 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
5903 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5904 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5905 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 5906 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
5907 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5908 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5909 | else | |
5910 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5911 | ||
cd474ba0 AD |
5912 | } |
5913 | } | |
5914 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 5915 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
5916 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
5917 | } else { | |
c5313457 | 5918 | switch (platform_link_width) { |
5d9a6330 | 5919 | case PCIE_LNK_X32: |
cd474ba0 AD |
5920 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
5921 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
5922 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5923 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5924 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5925 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5926 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5927 | break; | |
5d9a6330 | 5928 | case PCIE_LNK_X16: |
cd474ba0 AD |
5929 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5930 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5931 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5932 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5933 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5934 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5935 | break; | |
5d9a6330 | 5936 | case PCIE_LNK_X12: |
cd474ba0 AD |
5937 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5938 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5939 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5940 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5941 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5942 | break; | |
5d9a6330 | 5943 | case PCIE_LNK_X8: |
cd474ba0 AD |
5944 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5945 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5946 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5947 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5948 | break; | |
5d9a6330 | 5949 | case PCIE_LNK_X4: |
cd474ba0 AD |
5950 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5951 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5952 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5953 | break; | |
5d9a6330 | 5954 | case PCIE_LNK_X2: |
cd474ba0 AD |
5955 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5956 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5957 | break; | |
5d9a6330 | 5958 | case PCIE_LNK_X1: |
cd474ba0 AD |
5959 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5960 | break; | |
5961 | default: | |
5962 | break; | |
5963 | } | |
d0dd7f0c AD |
5964 | } |
5965 | } | |
5966 | } | |
d38ceaf9 | 5967 | |
08a2fd23 RE |
5968 | /** |
5969 | * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR | |
5970 | * | |
5971 | * @adev: amdgpu_device pointer | |
5972 | * @peer_adev: amdgpu_device pointer for peer device trying to access @adev | |
5973 | * | |
5974 | * Return true if @peer_adev can access (DMA) @adev through the PCIe | |
5975 | * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of | |
5976 | * @peer_adev. | |
5977 | */ | |
5978 | bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, | |
5979 | struct amdgpu_device *peer_adev) | |
5980 | { | |
5981 | #ifdef CONFIG_HSA_AMD_P2P | |
5982 | uint64_t address_mask = peer_adev->dev->dma_mask ? | |
5983 | ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1); | |
5984 | resource_size_t aper_limit = | |
5985 | adev->gmc.aper_base + adev->gmc.aper_size - 1; | |
bb66ecbf LL |
5986 | bool p2p_access = |
5987 | !adev->gmc.xgmi.connected_to_cpu && | |
5988 | !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); | |
08a2fd23 RE |
5989 | |
5990 | return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && | |
5991 | adev->gmc.real_vram_size == adev->gmc.visible_vram_size && | |
5992 | !(adev->gmc.aper_base & address_mask || | |
5993 | aper_limit & address_mask)); | |
5994 | #else | |
5995 | return false; | |
5996 | #endif | |
5997 | } | |
5998 | ||
361dbd01 AD |
5999 | int amdgpu_device_baco_enter(struct drm_device *dev) |
6000 | { | |
1348969a | 6001 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 6002 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 6003 | |
6ab68650 | 6004 | if (!amdgpu_device_supports_baco(dev)) |
361dbd01 AD |
6005 | return -ENOTSUPP; |
6006 | ||
8ab0d6f0 | 6007 | if (ras && adev->ras_enabled && |
acdae216 | 6008 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
6009 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
6010 | ||
9530273e | 6011 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
6012 | } |
6013 | ||
6014 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
6015 | { | |
1348969a | 6016 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 6017 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 6018 | int ret = 0; |
361dbd01 | 6019 | |
6ab68650 | 6020 | if (!amdgpu_device_supports_baco(dev)) |
361dbd01 AD |
6021 | return -ENOTSUPP; |
6022 | ||
9530273e EQ |
6023 | ret = amdgpu_dpm_baco_exit(adev); |
6024 | if (ret) | |
6025 | return ret; | |
7a22677b | 6026 | |
8ab0d6f0 | 6027 | if (ras && adev->ras_enabled && |
acdae216 | 6028 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
6029 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
6030 | ||
1bece222 CL |
6031 | if (amdgpu_passthrough(adev) && |
6032 | adev->nbio.funcs->clear_doorbell_interrupt) | |
6033 | adev->nbio.funcs->clear_doorbell_interrupt(adev); | |
6034 | ||
7a22677b | 6035 | return 0; |
361dbd01 | 6036 | } |
c9a6b82f AG |
6037 | |
6038 | /** | |
6039 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
6040 | * @pdev: PCI device struct | |
6041 | * @state: PCI channel state | |
6042 | * | |
6043 | * Description: Called when a PCI error is detected. | |
6044 | * | |
6045 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
6046 | */ | |
6047 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
6048 | { | |
6049 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6050 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 6051 | int i; |
c9a6b82f AG |
6052 | |
6053 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
6054 | ||
6894305c AG |
6055 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
6056 | DRM_WARN("No support for XGMI hive yet..."); | |
6057 | return PCI_ERS_RESULT_DISCONNECT; | |
6058 | } | |
6059 | ||
e17e27f9 GC |
6060 | adev->pci_channel_state = state; |
6061 | ||
c9a6b82f AG |
6062 | switch (state) { |
6063 | case pci_channel_io_normal: | |
6064 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 6065 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
6066 | case pci_channel_io_frozen: |
6067 | /* | |
d0fb18b5 | 6068 | * Locking adev->reset_domain->sem will prevent any external access |
acd89fca AG |
6069 | * to GPU during PCI error recovery |
6070 | */ | |
3675c2f2 | 6071 | amdgpu_device_lock_reset_domain(adev->reset_domain); |
e923be99 | 6072 | amdgpu_device_set_mp1_state(adev); |
acd89fca AG |
6073 | |
6074 | /* | |
6075 | * Block any work scheduling as we do for regular GPU reset | |
6076 | * for the duration of the recovery | |
6077 | */ | |
6078 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
6079 | struct amdgpu_ring *ring = adev->rings[i]; | |
6080 | ||
9749c868 | 6081 | if (!amdgpu_ring_sched_ready(ring)) |
acd89fca AG |
6082 | continue; |
6083 | ||
6084 | drm_sched_stop(&ring->sched, NULL); | |
6085 | } | |
8f8c80f4 | 6086 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
6087 | return PCI_ERS_RESULT_NEED_RESET; |
6088 | case pci_channel_io_perm_failure: | |
6089 | /* Permanent error, prepare for device removal */ | |
6090 | return PCI_ERS_RESULT_DISCONNECT; | |
6091 | } | |
6092 | ||
6093 | return PCI_ERS_RESULT_NEED_RESET; | |
6094 | } | |
6095 | ||
6096 | /** | |
6097 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
6098 | * @pdev: pointer to PCI device | |
6099 | */ | |
6100 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
6101 | { | |
6102 | ||
6103 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
6104 | ||
6105 | /* TODO - dump whatever for debugging purposes */ | |
6106 | ||
6107 | /* This called only if amdgpu_pci_error_detected returns | |
6108 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
6109 | * works, no need to reset slot. | |
6110 | */ | |
6111 | ||
6112 | return PCI_ERS_RESULT_RECOVERED; | |
6113 | } | |
6114 | ||
6115 | /** | |
6116 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
6117 | * @pdev: PCI device struct | |
6118 | * | |
6119 | * Description: This routine is called by the pci error recovery | |
6120 | * code after the PCI slot has been reset, just before we | |
6121 | * should resume normal operations. | |
6122 | */ | |
6123 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
6124 | { | |
6125 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6126 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 6127 | int r, i; |
04442bf7 | 6128 | struct amdgpu_reset_context reset_context; |
362c7b91 | 6129 | u32 memsize; |
7ac71382 | 6130 | struct list_head device_list; |
601429cc SY |
6131 | struct amdgpu_hive_info *hive; |
6132 | int hive_ras_recovery = 0; | |
6133 | struct amdgpu_ras *ras; | |
6134 | ||
6135 | /* PCI error slot reset should be skipped During RAS recovery */ | |
6136 | hive = amdgpu_get_xgmi_hive(adev); | |
6137 | if (hive) { | |
6138 | hive_ras_recovery = atomic_read(&hive->ras_recovery); | |
6139 | amdgpu_put_xgmi_hive(hive); | |
6140 | } | |
6141 | ras = amdgpu_ras_get_context(adev); | |
6142 | if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) && | |
6143 | ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery)) | |
6144 | return PCI_ERS_RESULT_RECOVERED; | |
c9a6b82f AG |
6145 | |
6146 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
6147 | ||
04442bf7 LL |
6148 | memset(&reset_context, 0, sizeof(reset_context)); |
6149 | ||
7ac71382 | 6150 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 6151 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 6152 | |
362c7b91 AG |
6153 | /* wait for asic to come out of reset */ |
6154 | msleep(500); | |
6155 | ||
7ac71382 | 6156 | /* Restore PCI confspace */ |
c1dd4aa6 | 6157 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 6158 | |
362c7b91 AG |
6159 | /* confirm ASIC came out of reset */ |
6160 | for (i = 0; i < adev->usec_timeout; i++) { | |
6161 | memsize = amdgpu_asic_get_config_memsize(adev); | |
6162 | ||
6163 | if (memsize != 0xffffffff) | |
6164 | break; | |
6165 | udelay(1); | |
6166 | } | |
6167 | if (memsize == 0xffffffff) { | |
6168 | r = -ETIME; | |
6169 | goto out; | |
6170 | } | |
6171 | ||
04442bf7 LL |
6172 | reset_context.method = AMD_RESET_METHOD_NONE; |
6173 | reset_context.reset_req_dev = adev; | |
6174 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
6175 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); | |
6176 | ||
7afefb81 | 6177 | adev->no_hw_access = true; |
04442bf7 | 6178 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
7afefb81 | 6179 | adev->no_hw_access = false; |
c9a6b82f AG |
6180 | if (r) |
6181 | goto out; | |
6182 | ||
04442bf7 | 6183 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
c9a6b82f AG |
6184 | |
6185 | out: | |
c9a6b82f | 6186 | if (!r) { |
c1dd4aa6 AG |
6187 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
6188 | pci_restore_state(adev->pdev); | |
6189 | ||
c9a6b82f AG |
6190 | DRM_INFO("PCIe error recovery succeeded\n"); |
6191 | } else { | |
6192 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
e923be99 AG |
6193 | amdgpu_device_unset_mp1_state(adev); |
6194 | amdgpu_device_unlock_reset_domain(adev->reset_domain); | |
c9a6b82f AG |
6195 | } |
6196 | ||
6197 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
6198 | } | |
6199 | ||
6200 | /** | |
6201 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
6202 | * @pdev: pointer to PCI device | |
6203 | * | |
6204 | * Called when the error recovery driver tells us that its | |
505199a3 | 6205 | * OK to resume normal operation. |
c9a6b82f AG |
6206 | */ |
6207 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
6208 | { | |
6209 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6210 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 6211 | int i; |
c9a6b82f | 6212 | |
c9a6b82f AG |
6213 | |
6214 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca | 6215 | |
e17e27f9 GC |
6216 | /* Only continue execution for the case of pci_channel_io_frozen */ |
6217 | if (adev->pci_channel_state != pci_channel_io_frozen) | |
6218 | return; | |
6219 | ||
acd89fca AG |
6220 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
6221 | struct amdgpu_ring *ring = adev->rings[i]; | |
6222 | ||
9749c868 | 6223 | if (!amdgpu_ring_sched_ready(ring)) |
acd89fca AG |
6224 | continue; |
6225 | ||
acd89fca AG |
6226 | drm_sched_start(&ring->sched, true); |
6227 | } | |
6228 | ||
e923be99 AG |
6229 | amdgpu_device_unset_mp1_state(adev); |
6230 | amdgpu_device_unlock_reset_domain(adev->reset_domain); | |
c9a6b82f | 6231 | } |
c1dd4aa6 AG |
6232 | |
6233 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
6234 | { | |
6235 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6236 | struct amdgpu_device *adev = drm_to_adev(dev); | |
6237 | int r; | |
6238 | ||
6239 | r = pci_save_state(pdev); | |
6240 | if (!r) { | |
6241 | kfree(adev->pci_state); | |
6242 | ||
6243 | adev->pci_state = pci_store_saved_state(pdev); | |
6244 | ||
6245 | if (!adev->pci_state) { | |
6246 | DRM_ERROR("Failed to store PCI saved state"); | |
6247 | return false; | |
6248 | } | |
6249 | } else { | |
6250 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
6251 | return false; | |
6252 | } | |
6253 | ||
6254 | return true; | |
6255 | } | |
6256 | ||
6257 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
6258 | { | |
6259 | struct drm_device *dev = pci_get_drvdata(pdev); | |
6260 | struct amdgpu_device *adev = drm_to_adev(dev); | |
6261 | int r; | |
6262 | ||
6263 | if (!adev->pci_state) | |
6264 | return false; | |
6265 | ||
6266 | r = pci_load_saved_state(pdev, adev->pci_state); | |
6267 | ||
6268 | if (!r) { | |
6269 | pci_restore_state(pdev); | |
6270 | } else { | |
6271 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
6272 | return false; | |
6273 | } | |
6274 | ||
6275 | return true; | |
6276 | } | |
6277 | ||
810085dd EH |
6278 | void amdgpu_device_flush_hdp(struct amdgpu_device *adev, |
6279 | struct amdgpu_ring *ring) | |
6280 | { | |
6281 | #ifdef CONFIG_X86_64 | |
b818a5d3 | 6282 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
6283 | return; |
6284 | #endif | |
6285 | if (adev->gmc.xgmi.connected_to_cpu) | |
6286 | return; | |
6287 | ||
6288 | if (ring && ring->funcs->emit_hdp_flush) | |
6289 | amdgpu_ring_emit_hdp_flush(ring); | |
6290 | else | |
6291 | amdgpu_asic_flush_hdp(adev, ring); | |
6292 | } | |
c1dd4aa6 | 6293 | |
810085dd EH |
6294 | void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, |
6295 | struct amdgpu_ring *ring) | |
6296 | { | |
6297 | #ifdef CONFIG_X86_64 | |
b818a5d3 | 6298 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
6299 | return; |
6300 | #endif | |
6301 | if (adev->gmc.xgmi.connected_to_cpu) | |
6302 | return; | |
c1dd4aa6 | 6303 | |
810085dd EH |
6304 | amdgpu_asic_invalidate_hdp(adev, ring); |
6305 | } | |
34f3a4a9 | 6306 | |
89a7a870 AG |
6307 | int amdgpu_in_reset(struct amdgpu_device *adev) |
6308 | { | |
6309 | return atomic_read(&adev->reset_domain->in_gpu_reset); | |
53a17b6b TZ |
6310 | } |
6311 | ||
34f3a4a9 LY |
6312 | /** |
6313 | * amdgpu_device_halt() - bring hardware to some kind of halt state | |
6314 | * | |
6315 | * @adev: amdgpu_device pointer | |
6316 | * | |
6317 | * Bring hardware to some kind of halt state so that no one can touch it | |
6318 | * any more. It will help to maintain error context when error occurred. | |
6319 | * Compare to a simple hang, the system will keep stable at least for SSH | |
6320 | * access. Then it should be trivial to inspect the hardware state and | |
6321 | * see what's going on. Implemented as following: | |
6322 | * | |
6323 | * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc), | |
6324 | * clears all CPU mappings to device, disallows remappings through page faults | |
6325 | * 2. amdgpu_irq_disable_all() disables all interrupts | |
6326 | * 3. amdgpu_fence_driver_hw_fini() signals all HW fences | |
6327 | * 4. set adev->no_hw_access to avoid potential crashes after setp 5 | |
6328 | * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings | |
6329 | * 6. pci_disable_device() and pci_wait_for_pending_transaction() | |
6330 | * flush any in flight DMA operations | |
6331 | */ | |
6332 | void amdgpu_device_halt(struct amdgpu_device *adev) | |
6333 | { | |
6334 | struct pci_dev *pdev = adev->pdev; | |
e0f943b4 | 6335 | struct drm_device *ddev = adev_to_drm(adev); |
34f3a4a9 | 6336 | |
2c1c7ba4 | 6337 | amdgpu_xcp_dev_unplug(adev); |
34f3a4a9 LY |
6338 | drm_dev_unplug(ddev); |
6339 | ||
6340 | amdgpu_irq_disable_all(adev); | |
6341 | ||
6342 | amdgpu_fence_driver_hw_fini(adev); | |
6343 | ||
6344 | adev->no_hw_access = true; | |
6345 | ||
6346 | amdgpu_device_unmap_mmio(adev); | |
6347 | ||
6348 | pci_disable_device(pdev); | |
6349 | pci_wait_for_pending_transaction(pdev); | |
6350 | } | |
86700a40 XD |
6351 | |
6352 | u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, | |
6353 | u32 reg) | |
6354 | { | |
6355 | unsigned long flags, address, data; | |
6356 | u32 r; | |
6357 | ||
6358 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
6359 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
6360 | ||
6361 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
6362 | WREG32(address, reg * 4); | |
6363 | (void)RREG32(address); | |
6364 | r = RREG32(data); | |
6365 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
6366 | return r; | |
6367 | } | |
6368 | ||
6369 | void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, | |
6370 | u32 reg, u32 v) | |
6371 | { | |
6372 | unsigned long flags, address, data; | |
6373 | ||
6374 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
6375 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
6376 | ||
6377 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
6378 | WREG32(address, reg * 4); | |
6379 | (void)RREG32(address); | |
6380 | WREG32(data, v); | |
6381 | (void)RREG32(data); | |
6382 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
6383 | } | |
68ce8b24 CK |
6384 | |
6385 | /** | |
6386 | * amdgpu_device_switch_gang - switch to a new gang | |
6387 | * @adev: amdgpu_device pointer | |
6388 | * @gang: the gang to switch to | |
6389 | * | |
6390 | * Try to switch to a new gang. | |
6391 | * Returns: NULL if we switched to the new gang or a reference to the current | |
6392 | * gang leader. | |
6393 | */ | |
6394 | struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, | |
6395 | struct dma_fence *gang) | |
6396 | { | |
6397 | struct dma_fence *old = NULL; | |
6398 | ||
6399 | do { | |
6400 | dma_fence_put(old); | |
6401 | rcu_read_lock(); | |
6402 | old = dma_fence_get_rcu_safe(&adev->gang_submit); | |
6403 | rcu_read_unlock(); | |
6404 | ||
6405 | if (old == gang) | |
6406 | break; | |
6407 | ||
6408 | if (!dma_fence_is_signaled(old)) | |
6409 | return old; | |
6410 | ||
6411 | } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit, | |
6412 | old, gang) != old); | |
6413 | ||
6414 | dma_fence_put(old); | |
6415 | return NULL; | |
6416 | } | |
220c8cc8 AD |
6417 | |
6418 | bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev) | |
6419 | { | |
6420 | switch (adev->asic_type) { | |
6421 | #ifdef CONFIG_DRM_AMDGPU_SI | |
6422 | case CHIP_HAINAN: | |
6423 | #endif | |
6424 | case CHIP_TOPAZ: | |
6425 | /* chips with no display hardware */ | |
6426 | return false; | |
6427 | #ifdef CONFIG_DRM_AMDGPU_SI | |
6428 | case CHIP_TAHITI: | |
6429 | case CHIP_PITCAIRN: | |
6430 | case CHIP_VERDE: | |
6431 | case CHIP_OLAND: | |
6432 | #endif | |
6433 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
6434 | case CHIP_BONAIRE: | |
6435 | case CHIP_HAWAII: | |
6436 | case CHIP_KAVERI: | |
6437 | case CHIP_KABINI: | |
6438 | case CHIP_MULLINS: | |
6439 | #endif | |
6440 | case CHIP_TONGA: | |
6441 | case CHIP_FIJI: | |
6442 | case CHIP_POLARIS10: | |
6443 | case CHIP_POLARIS11: | |
6444 | case CHIP_POLARIS12: | |
6445 | case CHIP_VEGAM: | |
6446 | case CHIP_CARRIZO: | |
6447 | case CHIP_STONEY: | |
6448 | /* chips with display hardware */ | |
6449 | return true; | |
6450 | default: | |
6451 | /* IP discovery */ | |
4e8303cf | 6452 | if (!amdgpu_ip_version(adev, DCE_HWIP, 0) || |
220c8cc8 AD |
6453 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) |
6454 | return false; | |
6455 | return true; | |
6456 | } | |
6457 | } | |
81283fee JZ |
6458 | |
6459 | uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, | |
6460 | uint32_t inst, uint32_t reg_addr, char reg_name[], | |
6461 | uint32_t expected_value, uint32_t mask) | |
6462 | { | |
6463 | uint32_t ret = 0; | |
6464 | uint32_t old_ = 0; | |
6465 | uint32_t tmp_ = RREG32(reg_addr); | |
6466 | uint32_t loop = adev->usec_timeout; | |
6467 | ||
6468 | while ((tmp_ & (mask)) != (expected_value)) { | |
6469 | if (old_ != tmp_) { | |
6470 | loop = adev->usec_timeout; | |
6471 | old_ = tmp_; | |
6472 | } else | |
6473 | udelay(1); | |
6474 | tmp_ = RREG32(reg_addr); | |
6475 | loop--; | |
6476 | if (!loop) { | |
6477 | DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn", | |
6478 | inst, reg_name, (uint32_t)expected_value, | |
6479 | (uint32_t)(tmp_ & (mask))); | |
6480 | ret = -ETIMEDOUT; | |
6481 | break; | |
6482 | } | |
6483 | } | |
6484 | return ret; | |
6485 | } |