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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
d0dd7f0c | 43 | #include "amd_pcie.h" |
33f34802 KW |
44 | #ifdef CONFIG_DRM_AMDGPU_SI |
45 | #include "si.h" | |
46 | #endif | |
a2e73f56 AD |
47 | #ifdef CONFIG_DRM_AMDGPU_CIK |
48 | #include "cik.h" | |
49 | #endif | |
aaa36a97 | 50 | #include "vi.h" |
d38ceaf9 | 51 | #include "bif/bif_4_1_d.h" |
9accf2fd | 52 | #include <linux/pci.h> |
bec86378 | 53 | #include <linux/firmware.h> |
d38ceaf9 AD |
54 | |
55 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
56 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
57 | ||
58 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
59 | "TAHITI", |
60 | "PITCAIRN", | |
61 | "VERDE", | |
62 | "OLAND", | |
63 | "HAINAN", | |
d38ceaf9 AD |
64 | "BONAIRE", |
65 | "KAVERI", | |
66 | "KABINI", | |
67 | "HAWAII", | |
68 | "MULLINS", | |
69 | "TOPAZ", | |
70 | "TONGA", | |
48299f95 | 71 | "FIJI", |
d38ceaf9 | 72 | "CARRIZO", |
139f4917 | 73 | "STONEY", |
2cc0c0b5 FC |
74 | "POLARIS10", |
75 | "POLARIS11", | |
d38ceaf9 AD |
76 | "LAST", |
77 | }; | |
78 | ||
79 | bool amdgpu_device_is_px(struct drm_device *dev) | |
80 | { | |
81 | struct amdgpu_device *adev = dev->dev_private; | |
82 | ||
2f7d10b3 | 83 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
84 | return true; |
85 | return false; | |
86 | } | |
87 | ||
88 | /* | |
89 | * MMIO register access helper functions. | |
90 | */ | |
91 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
92 | bool always_indirect) | |
93 | { | |
f4b373f4 TSD |
94 | uint32_t ret; |
95 | ||
d38ceaf9 | 96 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
f4b373f4 | 97 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
98 | else { |
99 | unsigned long flags; | |
d38ceaf9 AD |
100 | |
101 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
102 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
103 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
104 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 105 | } |
f4b373f4 TSD |
106 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
107 | return ret; | |
d38ceaf9 AD |
108 | } |
109 | ||
110 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
111 | bool always_indirect) | |
112 | { | |
f4b373f4 | 113 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 114 | |
d38ceaf9 AD |
115 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
116 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
117 | else { | |
118 | unsigned long flags; | |
119 | ||
120 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
121 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
122 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
123 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
124 | } | |
125 | } | |
126 | ||
127 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
128 | { | |
129 | if ((reg * 4) < adev->rio_mem_size) | |
130 | return ioread32(adev->rio_mem + (reg * 4)); | |
131 | else { | |
132 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
133 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
134 | } | |
135 | } | |
136 | ||
137 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
138 | { | |
139 | ||
140 | if ((reg * 4) < adev->rio_mem_size) | |
141 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
142 | else { | |
143 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
144 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
145 | } | |
146 | } | |
147 | ||
148 | /** | |
149 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
150 | * | |
151 | * @adev: amdgpu_device pointer | |
152 | * @index: doorbell index | |
153 | * | |
154 | * Returns the value in the doorbell aperture at the | |
155 | * requested doorbell index (CIK). | |
156 | */ | |
157 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
158 | { | |
159 | if (index < adev->doorbell.num_doorbells) { | |
160 | return readl(adev->doorbell.ptr + index); | |
161 | } else { | |
162 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
163 | return 0; | |
164 | } | |
165 | } | |
166 | ||
167 | /** | |
168 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
169 | * | |
170 | * @adev: amdgpu_device pointer | |
171 | * @index: doorbell index | |
172 | * @v: value to write | |
173 | * | |
174 | * Writes @v to the doorbell aperture at the | |
175 | * requested doorbell index (CIK). | |
176 | */ | |
177 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
178 | { | |
179 | if (index < adev->doorbell.num_doorbells) { | |
180 | writel(v, adev->doorbell.ptr + index); | |
181 | } else { | |
182 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
183 | } | |
184 | } | |
185 | ||
186 | /** | |
187 | * amdgpu_invalid_rreg - dummy reg read function | |
188 | * | |
189 | * @adev: amdgpu device pointer | |
190 | * @reg: offset of register | |
191 | * | |
192 | * Dummy register read function. Used for register blocks | |
193 | * that certain asics don't have (all asics). | |
194 | * Returns the value in the register. | |
195 | */ | |
196 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
197 | { | |
198 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
199 | BUG(); | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /** | |
204 | * amdgpu_invalid_wreg - dummy reg write function | |
205 | * | |
206 | * @adev: amdgpu device pointer | |
207 | * @reg: offset of register | |
208 | * @v: value to write to the register | |
209 | * | |
210 | * Dummy register read function. Used for register blocks | |
211 | * that certain asics don't have (all asics). | |
212 | */ | |
213 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
214 | { | |
215 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
216 | reg, v); | |
217 | BUG(); | |
218 | } | |
219 | ||
220 | /** | |
221 | * amdgpu_block_invalid_rreg - dummy reg read function | |
222 | * | |
223 | * @adev: amdgpu device pointer | |
224 | * @block: offset of instance | |
225 | * @reg: offset of register | |
226 | * | |
227 | * Dummy register read function. Used for register blocks | |
228 | * that certain asics don't have (all asics). | |
229 | * Returns the value in the register. | |
230 | */ | |
231 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
232 | uint32_t block, uint32_t reg) | |
233 | { | |
234 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
235 | reg, block); | |
236 | BUG(); | |
237 | return 0; | |
238 | } | |
239 | ||
240 | /** | |
241 | * amdgpu_block_invalid_wreg - dummy reg write function | |
242 | * | |
243 | * @adev: amdgpu device pointer | |
244 | * @block: offset of instance | |
245 | * @reg: offset of register | |
246 | * @v: value to write to the register | |
247 | * | |
248 | * Dummy register read function. Used for register blocks | |
249 | * that certain asics don't have (all asics). | |
250 | */ | |
251 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
252 | uint32_t block, | |
253 | uint32_t reg, uint32_t v) | |
254 | { | |
255 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
256 | reg, block, v); | |
257 | BUG(); | |
258 | } | |
259 | ||
260 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
261 | { | |
262 | int r; | |
263 | ||
264 | if (adev->vram_scratch.robj == NULL) { | |
265 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 266 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
267 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
268 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 269 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
270 | if (r) { |
271 | return r; | |
272 | } | |
273 | } | |
274 | ||
275 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
276 | if (unlikely(r != 0)) | |
277 | return r; | |
278 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
279 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
280 | if (r) { | |
281 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
282 | return r; | |
283 | } | |
284 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
285 | (void **)&adev->vram_scratch.ptr); | |
286 | if (r) | |
287 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
288 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
289 | ||
290 | return r; | |
291 | } | |
292 | ||
293 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
294 | { | |
295 | int r; | |
296 | ||
297 | if (adev->vram_scratch.robj == NULL) { | |
298 | return; | |
299 | } | |
300 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
301 | if (likely(r == 0)) { | |
302 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
303 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
304 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
305 | } | |
306 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
307 | } | |
308 | ||
309 | /** | |
310 | * amdgpu_program_register_sequence - program an array of registers. | |
311 | * | |
312 | * @adev: amdgpu_device pointer | |
313 | * @registers: pointer to the register array | |
314 | * @array_size: size of the register array | |
315 | * | |
316 | * Programs an array or registers with and and or masks. | |
317 | * This is a helper for setting golden registers. | |
318 | */ | |
319 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
320 | const u32 *registers, | |
321 | const u32 array_size) | |
322 | { | |
323 | u32 tmp, reg, and_mask, or_mask; | |
324 | int i; | |
325 | ||
326 | if (array_size % 3) | |
327 | return; | |
328 | ||
329 | for (i = 0; i < array_size; i +=3) { | |
330 | reg = registers[i + 0]; | |
331 | and_mask = registers[i + 1]; | |
332 | or_mask = registers[i + 2]; | |
333 | ||
334 | if (and_mask == 0xffffffff) { | |
335 | tmp = or_mask; | |
336 | } else { | |
337 | tmp = RREG32(reg); | |
338 | tmp &= ~and_mask; | |
339 | tmp |= or_mask; | |
340 | } | |
341 | WREG32(reg, tmp); | |
342 | } | |
343 | } | |
344 | ||
345 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
346 | { | |
347 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
348 | } | |
349 | ||
350 | /* | |
351 | * GPU doorbell aperture helpers function. | |
352 | */ | |
353 | /** | |
354 | * amdgpu_doorbell_init - Init doorbell driver information. | |
355 | * | |
356 | * @adev: amdgpu_device pointer | |
357 | * | |
358 | * Init doorbell driver information (CIK) | |
359 | * Returns 0 on success, error on failure. | |
360 | */ | |
361 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
362 | { | |
363 | /* doorbell bar mapping */ | |
364 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
365 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
366 | ||
edf600da | 367 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
368 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
369 | if (adev->doorbell.num_doorbells == 0) | |
370 | return -EINVAL; | |
371 | ||
372 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
373 | if (adev->doorbell.ptr == NULL) { | |
374 | return -ENOMEM; | |
375 | } | |
376 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
377 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | /** | |
383 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
384 | * | |
385 | * @adev: amdgpu_device pointer | |
386 | * | |
387 | * Tear down doorbell driver information (CIK) | |
388 | */ | |
389 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
390 | { | |
391 | iounmap(adev->doorbell.ptr); | |
392 | adev->doorbell.ptr = NULL; | |
393 | } | |
394 | ||
395 | /** | |
396 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
397 | * setup amdkfd | |
398 | * | |
399 | * @adev: amdgpu_device pointer | |
400 | * @aperture_base: output returning doorbell aperture base physical address | |
401 | * @aperture_size: output returning doorbell aperture size in bytes | |
402 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
403 | * | |
404 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
405 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
406 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
407 | */ | |
408 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
409 | phys_addr_t *aperture_base, | |
410 | size_t *aperture_size, | |
411 | size_t *start_offset) | |
412 | { | |
413 | /* | |
414 | * The first num_doorbells are used by amdgpu. | |
415 | * amdkfd takes whatever's left in the aperture. | |
416 | */ | |
417 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
418 | *aperture_base = adev->doorbell.base; | |
419 | *aperture_size = adev->doorbell.size; | |
420 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
421 | } else { | |
422 | *aperture_base = 0; | |
423 | *aperture_size = 0; | |
424 | *start_offset = 0; | |
425 | } | |
426 | } | |
427 | ||
428 | /* | |
429 | * amdgpu_wb_*() | |
430 | * Writeback is the the method by which the the GPU updates special pages | |
431 | * in memory with the status of certain GPU events (fences, ring pointers, | |
432 | * etc.). | |
433 | */ | |
434 | ||
435 | /** | |
436 | * amdgpu_wb_fini - Disable Writeback and free memory | |
437 | * | |
438 | * @adev: amdgpu_device pointer | |
439 | * | |
440 | * Disables Writeback and frees the Writeback memory (all asics). | |
441 | * Used at driver shutdown. | |
442 | */ | |
443 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
444 | { | |
445 | if (adev->wb.wb_obj) { | |
446 | if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) { | |
447 | amdgpu_bo_kunmap(adev->wb.wb_obj); | |
448 | amdgpu_bo_unpin(adev->wb.wb_obj); | |
449 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
450 | } | |
451 | amdgpu_bo_unref(&adev->wb.wb_obj); | |
452 | adev->wb.wb = NULL; | |
453 | adev->wb.wb_obj = NULL; | |
454 | } | |
455 | } | |
456 | ||
457 | /** | |
458 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
459 | * | |
460 | * @adev: amdgpu_device pointer | |
461 | * | |
462 | * Disables Writeback and frees the Writeback memory (all asics). | |
463 | * Used at driver startup. | |
464 | * Returns 0 on success or an -error on failure. | |
465 | */ | |
466 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
467 | { | |
468 | int r; | |
469 | ||
470 | if (adev->wb.wb_obj == NULL) { | |
471 | r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true, | |
72d7668b CK |
472 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, |
473 | &adev->wb.wb_obj); | |
d38ceaf9 AD |
474 | if (r) { |
475 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
476 | return r; | |
477 | } | |
478 | r = amdgpu_bo_reserve(adev->wb.wb_obj, false); | |
479 | if (unlikely(r != 0)) { | |
480 | amdgpu_wb_fini(adev); | |
481 | return r; | |
482 | } | |
483 | r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT, | |
484 | &adev->wb.gpu_addr); | |
485 | if (r) { | |
486 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
487 | dev_warn(adev->dev, "(%d) pin WB bo failed\n", r); | |
488 | amdgpu_wb_fini(adev); | |
489 | return r; | |
490 | } | |
491 | r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb); | |
492 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
493 | if (r) { | |
494 | dev_warn(adev->dev, "(%d) map WB bo failed\n", r); | |
495 | amdgpu_wb_fini(adev); | |
496 | return r; | |
497 | } | |
498 | ||
499 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
500 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
501 | ||
502 | /* clear wb memory */ | |
503 | memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE); | |
504 | } | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
509 | /** | |
510 | * amdgpu_wb_get - Allocate a wb entry | |
511 | * | |
512 | * @adev: amdgpu_device pointer | |
513 | * @wb: wb index | |
514 | * | |
515 | * Allocate a wb slot for use by the driver (all asics). | |
516 | * Returns 0 on success or -EINVAL on failure. | |
517 | */ | |
518 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
519 | { | |
520 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
521 | if (offset < adev->wb.num_wb) { | |
522 | __set_bit(offset, adev->wb.used); | |
523 | *wb = offset; | |
524 | return 0; | |
525 | } else { | |
526 | return -EINVAL; | |
527 | } | |
528 | } | |
529 | ||
530 | /** | |
531 | * amdgpu_wb_free - Free a wb entry | |
532 | * | |
533 | * @adev: amdgpu_device pointer | |
534 | * @wb: wb index | |
535 | * | |
536 | * Free a wb slot allocated for use by the driver (all asics) | |
537 | */ | |
538 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
539 | { | |
540 | if (wb < adev->wb.num_wb) | |
541 | __clear_bit(wb, adev->wb.used); | |
542 | } | |
543 | ||
544 | /** | |
545 | * amdgpu_vram_location - try to find VRAM location | |
546 | * @adev: amdgpu device structure holding all necessary informations | |
547 | * @mc: memory controller structure holding memory informations | |
548 | * @base: base address at which to put VRAM | |
549 | * | |
550 | * Function will place try to place VRAM at base address provided | |
551 | * as parameter (which is so far either PCI aperture address or | |
552 | * for IGP TOM base address). | |
553 | * | |
554 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
555 | * address space then we limit the VRAM size to the aperture. | |
556 | * | |
557 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
558 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
559 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
560 | * not IGP. | |
561 | * | |
562 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
563 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
564 | * Novell bug 204882 + along with lots of ubuntu ones | |
565 | * | |
566 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
567 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
568 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
569 | * ones) | |
570 | * | |
571 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
572 | * explicitly check for that thought. | |
573 | * | |
574 | * FIXME: when reducing VRAM size align new size on power of 2. | |
575 | */ | |
576 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
577 | { | |
578 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
579 | ||
580 | mc->vram_start = base; | |
581 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
582 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
583 | mc->real_vram_size = mc->aper_size; | |
584 | mc->mc_vram_size = mc->aper_size; | |
585 | } | |
586 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
587 | if (limit && limit < mc->real_vram_size) | |
588 | mc->real_vram_size = limit; | |
589 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
590 | mc->mc_vram_size >> 20, mc->vram_start, | |
591 | mc->vram_end, mc->real_vram_size >> 20); | |
592 | } | |
593 | ||
594 | /** | |
595 | * amdgpu_gtt_location - try to find GTT location | |
596 | * @adev: amdgpu device structure holding all necessary informations | |
597 | * @mc: memory controller structure holding memory informations | |
598 | * | |
599 | * Function will place try to place GTT before or after VRAM. | |
600 | * | |
601 | * If GTT size is bigger than space left then we ajust GTT size. | |
602 | * Thus function will never fails. | |
603 | * | |
604 | * FIXME: when reducing GTT size align new size on power of 2. | |
605 | */ | |
606 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
607 | { | |
608 | u64 size_af, size_bf; | |
609 | ||
610 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
611 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
612 | if (size_bf > size_af) { | |
613 | if (mc->gtt_size > size_bf) { | |
614 | dev_warn(adev->dev, "limiting GTT\n"); | |
615 | mc->gtt_size = size_bf; | |
616 | } | |
617 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; | |
618 | } else { | |
619 | if (mc->gtt_size > size_af) { | |
620 | dev_warn(adev->dev, "limiting GTT\n"); | |
621 | mc->gtt_size = size_af; | |
622 | } | |
623 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
624 | } | |
625 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
626 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
627 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
628 | } | |
629 | ||
630 | /* | |
631 | * GPU helpers function. | |
632 | */ | |
633 | /** | |
634 | * amdgpu_card_posted - check if the hw has already been initialized | |
635 | * | |
636 | * @adev: amdgpu_device pointer | |
637 | * | |
638 | * Check if the asic has been initialized (all asics). | |
639 | * Used at driver startup. | |
640 | * Returns true if initialized or false if not. | |
641 | */ | |
642 | bool amdgpu_card_posted(struct amdgpu_device *adev) | |
643 | { | |
644 | uint32_t reg; | |
645 | ||
646 | /* then check MEM_SIZE, in case the crtcs are off */ | |
647 | reg = RREG32(mmCONFIG_MEMSIZE); | |
648 | ||
649 | if (reg) | |
650 | return true; | |
651 | ||
652 | return false; | |
653 | ||
654 | } | |
655 | ||
bec86378 ML |
656 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
657 | { | |
658 | if (amdgpu_sriov_vf(adev)) | |
659 | return false; | |
660 | ||
661 | if (amdgpu_passthrough(adev)) { | |
662 | /* for FIJI: In whole GPU pass-through virtualization case | |
663 | * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH) | |
664 | * so amdgpu_card_posted return false and driver will incorrectly skip vPost. | |
665 | * but if we force vPost do in pass-through case, the driver reload will hang. | |
666 | * whether doing vPost depends on amdgpu_card_posted if smc version is above | |
667 | * 00160e00 for FIJI. | |
668 | */ | |
669 | if (adev->asic_type == CHIP_FIJI) { | |
670 | int err; | |
671 | uint32_t fw_ver; | |
672 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
673 | /* force vPost if error occured */ | |
674 | if (err) | |
675 | return true; | |
676 | ||
677 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
678 | if (fw_ver >= 0x00160e00) | |
679 | return !amdgpu_card_posted(adev); | |
680 | } | |
681 | } else { | |
682 | /* in bare-metal case, amdgpu_card_posted return false | |
683 | * after system reboot/boot, and return true if driver | |
684 | * reloaded. | |
685 | * we shouldn't do vPost after driver reload otherwise GPU | |
686 | * could hang. | |
687 | */ | |
688 | if (amdgpu_card_posted(adev)) | |
689 | return false; | |
690 | } | |
691 | ||
692 | /* we assume vPost is neede for all other cases */ | |
693 | return true; | |
694 | } | |
695 | ||
d38ceaf9 AD |
696 | /** |
697 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
698 | * | |
699 | * @adev: amdgpu_device pointer | |
700 | * | |
701 | * Allocate the dummy page used by the driver (all asics). | |
702 | * This dummy page is used by the driver as a filler for gart entries | |
703 | * when pages are taken out of the GART | |
704 | * Returns 0 on sucess, -ENOMEM on failure. | |
705 | */ | |
706 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
707 | { | |
708 | if (adev->dummy_page.page) | |
709 | return 0; | |
710 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
711 | if (adev->dummy_page.page == NULL) | |
712 | return -ENOMEM; | |
713 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
714 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
715 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
716 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
717 | __free_page(adev->dummy_page.page); | |
718 | adev->dummy_page.page = NULL; | |
719 | return -ENOMEM; | |
720 | } | |
721 | return 0; | |
722 | } | |
723 | ||
724 | /** | |
725 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
726 | * | |
727 | * @adev: amdgpu_device pointer | |
728 | * | |
729 | * Frees the dummy page used by the driver (all asics). | |
730 | */ | |
731 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
732 | { | |
733 | if (adev->dummy_page.page == NULL) | |
734 | return; | |
735 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
736 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
737 | __free_page(adev->dummy_page.page); | |
738 | adev->dummy_page.page = NULL; | |
739 | } | |
740 | ||
741 | ||
742 | /* ATOM accessor methods */ | |
743 | /* | |
744 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
745 | * driver registers callbacks to access registers and the interpreter | |
746 | * in the driver parses the tables and executes then to program specific | |
747 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
748 | * atombios.h, and atom.c | |
749 | */ | |
750 | ||
751 | /** | |
752 | * cail_pll_read - read PLL register | |
753 | * | |
754 | * @info: atom card_info pointer | |
755 | * @reg: PLL register offset | |
756 | * | |
757 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
758 | * Returns the value of the PLL register. | |
759 | */ | |
760 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
761 | { | |
762 | return 0; | |
763 | } | |
764 | ||
765 | /** | |
766 | * cail_pll_write - write PLL register | |
767 | * | |
768 | * @info: atom card_info pointer | |
769 | * @reg: PLL register offset | |
770 | * @val: value to write to the pll register | |
771 | * | |
772 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
773 | */ | |
774 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
775 | { | |
776 | ||
777 | } | |
778 | ||
779 | /** | |
780 | * cail_mc_read - read MC (Memory Controller) register | |
781 | * | |
782 | * @info: atom card_info pointer | |
783 | * @reg: MC register offset | |
784 | * | |
785 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
786 | * Returns the value of the MC register. | |
787 | */ | |
788 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
789 | { | |
790 | return 0; | |
791 | } | |
792 | ||
793 | /** | |
794 | * cail_mc_write - write MC (Memory Controller) register | |
795 | * | |
796 | * @info: atom card_info pointer | |
797 | * @reg: MC register offset | |
798 | * @val: value to write to the pll register | |
799 | * | |
800 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
801 | */ | |
802 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
803 | { | |
804 | ||
805 | } | |
806 | ||
807 | /** | |
808 | * cail_reg_write - write MMIO register | |
809 | * | |
810 | * @info: atom card_info pointer | |
811 | * @reg: MMIO register offset | |
812 | * @val: value to write to the pll register | |
813 | * | |
814 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
815 | */ | |
816 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
817 | { | |
818 | struct amdgpu_device *adev = info->dev->dev_private; | |
819 | ||
820 | WREG32(reg, val); | |
821 | } | |
822 | ||
823 | /** | |
824 | * cail_reg_read - read MMIO register | |
825 | * | |
826 | * @info: atom card_info pointer | |
827 | * @reg: MMIO register offset | |
828 | * | |
829 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
830 | * Returns the value of the MMIO register. | |
831 | */ | |
832 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
833 | { | |
834 | struct amdgpu_device *adev = info->dev->dev_private; | |
835 | uint32_t r; | |
836 | ||
837 | r = RREG32(reg); | |
838 | return r; | |
839 | } | |
840 | ||
841 | /** | |
842 | * cail_ioreg_write - write IO register | |
843 | * | |
844 | * @info: atom card_info pointer | |
845 | * @reg: IO register offset | |
846 | * @val: value to write to the pll register | |
847 | * | |
848 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
849 | */ | |
850 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
851 | { | |
852 | struct amdgpu_device *adev = info->dev->dev_private; | |
853 | ||
854 | WREG32_IO(reg, val); | |
855 | } | |
856 | ||
857 | /** | |
858 | * cail_ioreg_read - read IO register | |
859 | * | |
860 | * @info: atom card_info pointer | |
861 | * @reg: IO register offset | |
862 | * | |
863 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
864 | * Returns the value of the IO register. | |
865 | */ | |
866 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
867 | { | |
868 | struct amdgpu_device *adev = info->dev->dev_private; | |
869 | uint32_t r; | |
870 | ||
871 | r = RREG32_IO(reg); | |
872 | return r; | |
873 | } | |
874 | ||
875 | /** | |
876 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
877 | * | |
878 | * @adev: amdgpu_device pointer | |
879 | * | |
880 | * Frees the driver info and register access callbacks for the ATOM | |
881 | * interpreter (r4xx+). | |
882 | * Called at driver shutdown. | |
883 | */ | |
884 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
885 | { | |
89e0ec9f | 886 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 887 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
888 | kfree(adev->mode_info.atom_context->iio); |
889 | } | |
d38ceaf9 AD |
890 | kfree(adev->mode_info.atom_context); |
891 | adev->mode_info.atom_context = NULL; | |
892 | kfree(adev->mode_info.atom_card_info); | |
893 | adev->mode_info.atom_card_info = NULL; | |
894 | } | |
895 | ||
896 | /** | |
897 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
898 | * | |
899 | * @adev: amdgpu_device pointer | |
900 | * | |
901 | * Initializes the driver info and register access callbacks for the | |
902 | * ATOM interpreter (r4xx+). | |
903 | * Returns 0 on sucess, -ENOMEM on failure. | |
904 | * Called at driver startup. | |
905 | */ | |
906 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
907 | { | |
908 | struct card_info *atom_card_info = | |
909 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
910 | ||
911 | if (!atom_card_info) | |
912 | return -ENOMEM; | |
913 | ||
914 | adev->mode_info.atom_card_info = atom_card_info; | |
915 | atom_card_info->dev = adev->ddev; | |
916 | atom_card_info->reg_read = cail_reg_read; | |
917 | atom_card_info->reg_write = cail_reg_write; | |
918 | /* needed for iio ops */ | |
919 | if (adev->rio_mem) { | |
920 | atom_card_info->ioreg_read = cail_ioreg_read; | |
921 | atom_card_info->ioreg_write = cail_ioreg_write; | |
922 | } else { | |
923 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
924 | atom_card_info->ioreg_read = cail_reg_read; | |
925 | atom_card_info->ioreg_write = cail_reg_write; | |
926 | } | |
927 | atom_card_info->mc_read = cail_mc_read; | |
928 | atom_card_info->mc_write = cail_mc_write; | |
929 | atom_card_info->pll_read = cail_pll_read; | |
930 | atom_card_info->pll_write = cail_pll_write; | |
931 | ||
932 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
933 | if (!adev->mode_info.atom_context) { | |
934 | amdgpu_atombios_fini(adev); | |
935 | return -ENOMEM; | |
936 | } | |
937 | ||
938 | mutex_init(&adev->mode_info.atom_context->mutex); | |
939 | amdgpu_atombios_scratch_regs_init(adev); | |
940 | amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); | |
941 | return 0; | |
942 | } | |
943 | ||
944 | /* if we get transitioned to only one device, take VGA back */ | |
945 | /** | |
946 | * amdgpu_vga_set_decode - enable/disable vga decode | |
947 | * | |
948 | * @cookie: amdgpu_device pointer | |
949 | * @state: enable/disable vga decode | |
950 | * | |
951 | * Enable/disable vga decode (all asics). | |
952 | * Returns VGA resource flags. | |
953 | */ | |
954 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
955 | { | |
956 | struct amdgpu_device *adev = cookie; | |
957 | amdgpu_asic_set_vga_state(adev, state); | |
958 | if (state) | |
959 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
960 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
961 | else | |
962 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
963 | } | |
964 | ||
965 | /** | |
966 | * amdgpu_check_pot_argument - check that argument is a power of two | |
967 | * | |
968 | * @arg: value to check | |
969 | * | |
970 | * Validates that a certain argument is a power of two (all asics). | |
971 | * Returns true if argument is valid. | |
972 | */ | |
973 | static bool amdgpu_check_pot_argument(int arg) | |
974 | { | |
975 | return (arg & (arg - 1)) == 0; | |
976 | } | |
977 | ||
978 | /** | |
979 | * amdgpu_check_arguments - validate module params | |
980 | * | |
981 | * @adev: amdgpu_device pointer | |
982 | * | |
983 | * Validates certain module parameters and updates | |
984 | * the associated values used by the driver (all asics). | |
985 | */ | |
986 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
987 | { | |
5b011235 CZ |
988 | if (amdgpu_sched_jobs < 4) { |
989 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
990 | amdgpu_sched_jobs); | |
991 | amdgpu_sched_jobs = 4; | |
992 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
993 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
994 | amdgpu_sched_jobs); | |
995 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
996 | } | |
d38ceaf9 AD |
997 | |
998 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 999 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
1000 | if (amdgpu_gart_size < 32) { |
1001 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1002 | amdgpu_gart_size); | |
1003 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
1004 | } |
1005 | } | |
1006 | ||
1007 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
1008 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
1009 | amdgpu_vm_size); | |
8dacc127 | 1010 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1011 | } |
1012 | ||
1013 | if (amdgpu_vm_size < 1) { | |
1014 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1015 | amdgpu_vm_size); | |
8dacc127 | 1016 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1017 | } |
1018 | ||
1019 | /* | |
1020 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
1021 | */ | |
1022 | if (amdgpu_vm_size > 1024) { | |
1023 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1024 | amdgpu_vm_size); | |
8dacc127 | 1025 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1026 | } |
1027 | ||
1028 | /* defines number of bits in page table versus page directory, | |
1029 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1030 | * page table and the remaining bits are in the page directory */ | |
1031 | if (amdgpu_vm_block_size == -1) { | |
1032 | ||
1033 | /* Total bits covered by PD + PTs */ | |
1034 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
1035 | ||
1036 | /* Make sure the PD is 4K in size up to 8GB address space. | |
1037 | Above that split equal between PD and PTs */ | |
1038 | if (amdgpu_vm_size <= 8) | |
1039 | amdgpu_vm_block_size = bits - 9; | |
1040 | else | |
1041 | amdgpu_vm_block_size = (bits + 3) / 2; | |
1042 | ||
1043 | } else if (amdgpu_vm_block_size < 9) { | |
1044 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
1045 | amdgpu_vm_block_size); | |
1046 | amdgpu_vm_block_size = 9; | |
1047 | } | |
1048 | ||
1049 | if (amdgpu_vm_block_size > 24 || | |
1050 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1051 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1052 | amdgpu_vm_block_size); | |
1053 | amdgpu_vm_block_size = 9; | |
1054 | } | |
6a7f76e7 CK |
1055 | |
1056 | if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) || | |
1057 | !amdgpu_check_pot_argument(amdgpu_vram_page_split)) { | |
1058 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", | |
1059 | amdgpu_vram_page_split); | |
1060 | amdgpu_vram_page_split = 1024; | |
1061 | } | |
d38ceaf9 AD |
1062 | } |
1063 | ||
1064 | /** | |
1065 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1066 | * | |
1067 | * @pdev: pci dev pointer | |
1694467b | 1068 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1069 | * |
1070 | * Callback for the switcheroo driver. Suspends or resumes the | |
1071 | * the asics before or after it is powered up using ACPI methods. | |
1072 | */ | |
1073 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1074 | { | |
1075 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1076 | ||
1077 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1078 | return; | |
1079 | ||
1080 | if (state == VGA_SWITCHEROO_ON) { | |
1081 | unsigned d3_delay = dev->pdev->d3_delay; | |
1082 | ||
1083 | printk(KERN_INFO "amdgpu: switched on\n"); | |
1084 | /* don't suspend or resume card normally */ | |
1085 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1086 | ||
810ddc3a | 1087 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1088 | |
1089 | dev->pdev->d3_delay = d3_delay; | |
1090 | ||
1091 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1092 | drm_kms_helper_poll_enable(dev); | |
1093 | } else { | |
1094 | printk(KERN_INFO "amdgpu: switched off\n"); | |
1095 | drm_kms_helper_poll_disable(dev); | |
1096 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1097 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1098 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1099 | } | |
1100 | } | |
1101 | ||
1102 | /** | |
1103 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1104 | * | |
1105 | * @pdev: pci dev pointer | |
1106 | * | |
1107 | * Callback for the switcheroo driver. Check of the switcheroo | |
1108 | * state can be changed. | |
1109 | * Returns true if the state can be changed, false if not. | |
1110 | */ | |
1111 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1112 | { | |
1113 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1114 | ||
1115 | /* | |
1116 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1117 | * locking inversion with the driver load path. And the access here is | |
1118 | * completely racy anyway. So don't bother with locking for now. | |
1119 | */ | |
1120 | return dev->open_count == 0; | |
1121 | } | |
1122 | ||
1123 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1124 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1125 | .reprobe = NULL, | |
1126 | .can_switch = amdgpu_switcheroo_can_switch, | |
1127 | }; | |
1128 | ||
1129 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1130 | enum amd_ip_block_type block_type, |
1131 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1132 | { |
1133 | int i, r = 0; | |
1134 | ||
1135 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1136 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1137 | continue; |
a1255107 AD |
1138 | if (adev->ip_blocks[i].version->type == block_type) { |
1139 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1140 | state); | |
d38ceaf9 AD |
1141 | if (r) |
1142 | return r; | |
a225bf1c | 1143 | break; |
d38ceaf9 AD |
1144 | } |
1145 | } | |
1146 | return r; | |
1147 | } | |
1148 | ||
1149 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1150 | enum amd_ip_block_type block_type, |
1151 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1152 | { |
1153 | int i, r = 0; | |
1154 | ||
1155 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1156 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1157 | continue; |
a1255107 AD |
1158 | if (adev->ip_blocks[i].version->type == block_type) { |
1159 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1160 | state); | |
d38ceaf9 AD |
1161 | if (r) |
1162 | return r; | |
a225bf1c | 1163 | break; |
d38ceaf9 AD |
1164 | } |
1165 | } | |
1166 | return r; | |
1167 | } | |
1168 | ||
5dbbb60b AD |
1169 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1170 | enum amd_ip_block_type block_type) | |
1171 | { | |
1172 | int i, r; | |
1173 | ||
1174 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1175 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1176 | continue; |
a1255107 AD |
1177 | if (adev->ip_blocks[i].version->type == block_type) { |
1178 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1179 | if (r) |
1180 | return r; | |
1181 | break; | |
1182 | } | |
1183 | } | |
1184 | return 0; | |
1185 | ||
1186 | } | |
1187 | ||
1188 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1189 | enum amd_ip_block_type block_type) | |
1190 | { | |
1191 | int i; | |
1192 | ||
1193 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1194 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1195 | continue; |
a1255107 AD |
1196 | if (adev->ip_blocks[i].version->type == block_type) |
1197 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1198 | } |
1199 | return true; | |
1200 | ||
1201 | } | |
1202 | ||
a1255107 AD |
1203 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1204 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1205 | { |
1206 | int i; | |
1207 | ||
1208 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1209 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1210 | return &adev->ip_blocks[i]; |
1211 | ||
1212 | return NULL; | |
1213 | } | |
1214 | ||
1215 | /** | |
1216 | * amdgpu_ip_block_version_cmp | |
1217 | * | |
1218 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1219 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1220 | * @major: major version |
1221 | * @minor: minor version | |
1222 | * | |
1223 | * return 0 if equal or greater | |
1224 | * return 1 if smaller or the ip_block doesn't exist | |
1225 | */ | |
1226 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1227 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1228 | u32 major, u32 minor) |
1229 | { | |
a1255107 | 1230 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1231 | |
a1255107 AD |
1232 | if (ip_block && ((ip_block->version->major > major) || |
1233 | ((ip_block->version->major == major) && | |
1234 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1235 | return 0; |
1236 | ||
1237 | return 1; | |
1238 | } | |
1239 | ||
a1255107 AD |
1240 | /** |
1241 | * amdgpu_ip_block_add | |
1242 | * | |
1243 | * @adev: amdgpu_device pointer | |
1244 | * @ip_block_version: pointer to the IP to add | |
1245 | * | |
1246 | * Adds the IP block driver information to the collection of IPs | |
1247 | * on the asic. | |
1248 | */ | |
1249 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1250 | const struct amdgpu_ip_block_version *ip_block_version) | |
1251 | { | |
1252 | if (!ip_block_version) | |
1253 | return -EINVAL; | |
1254 | ||
1255 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
483ef985 | 1260 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1261 | { |
1262 | adev->enable_virtual_display = false; | |
1263 | ||
1264 | if (amdgpu_virtual_display) { | |
1265 | struct drm_device *ddev = adev->ddev; | |
1266 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1267 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1268 | |
1269 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1270 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1271 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1272 | pciaddname = strsep(&pciaddname_tmp, ","); | |
9accf2fd | 1273 | if (!strcmp(pci_address_name, pciaddname)) { |
0f66356d ED |
1274 | long num_crtc; |
1275 | int res = -1; | |
1276 | ||
9accf2fd | 1277 | adev->enable_virtual_display = true; |
0f66356d ED |
1278 | |
1279 | if (pciaddname_tmp) | |
1280 | res = kstrtol(pciaddname_tmp, 10, | |
1281 | &num_crtc); | |
1282 | ||
1283 | if (!res) { | |
1284 | if (num_crtc < 1) | |
1285 | num_crtc = 1; | |
1286 | if (num_crtc > 6) | |
1287 | num_crtc = 6; | |
1288 | adev->mode_info.num_crtc = num_crtc; | |
1289 | } else { | |
1290 | adev->mode_info.num_crtc = 1; | |
1291 | } | |
9accf2fd ED |
1292 | break; |
1293 | } | |
1294 | } | |
1295 | ||
0f66356d ED |
1296 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1297 | amdgpu_virtual_display, pci_address_name, | |
1298 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1299 | |
1300 | kfree(pciaddstr); | |
1301 | } | |
1302 | } | |
1303 | ||
d38ceaf9 AD |
1304 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1305 | { | |
aaa36a97 | 1306 | int i, r; |
d38ceaf9 | 1307 | |
483ef985 | 1308 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1309 | |
d38ceaf9 | 1310 | switch (adev->asic_type) { |
aaa36a97 AD |
1311 | case CHIP_TOPAZ: |
1312 | case CHIP_TONGA: | |
48299f95 | 1313 | case CHIP_FIJI: |
2cc0c0b5 FC |
1314 | case CHIP_POLARIS11: |
1315 | case CHIP_POLARIS10: | |
aaa36a97 | 1316 | case CHIP_CARRIZO: |
39bb0c92 SL |
1317 | case CHIP_STONEY: |
1318 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1319 | adev->family = AMDGPU_FAMILY_CZ; |
1320 | else | |
1321 | adev->family = AMDGPU_FAMILY_VI; | |
1322 | ||
1323 | r = vi_set_ip_blocks(adev); | |
1324 | if (r) | |
1325 | return r; | |
1326 | break; | |
33f34802 KW |
1327 | #ifdef CONFIG_DRM_AMDGPU_SI |
1328 | case CHIP_VERDE: | |
1329 | case CHIP_TAHITI: | |
1330 | case CHIP_PITCAIRN: | |
1331 | case CHIP_OLAND: | |
1332 | case CHIP_HAINAN: | |
295d0daf | 1333 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1334 | r = si_set_ip_blocks(adev); |
1335 | if (r) | |
1336 | return r; | |
1337 | break; | |
1338 | #endif | |
a2e73f56 AD |
1339 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1340 | case CHIP_BONAIRE: | |
1341 | case CHIP_HAWAII: | |
1342 | case CHIP_KAVERI: | |
1343 | case CHIP_KABINI: | |
1344 | case CHIP_MULLINS: | |
1345 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1346 | adev->family = AMDGPU_FAMILY_CI; | |
1347 | else | |
1348 | adev->family = AMDGPU_FAMILY_KV; | |
1349 | ||
1350 | r = cik_set_ip_blocks(adev); | |
1351 | if (r) | |
1352 | return r; | |
1353 | break; | |
1354 | #endif | |
d38ceaf9 AD |
1355 | default: |
1356 | /* FIXME: not supported yet */ | |
1357 | return -EINVAL; | |
1358 | } | |
1359 | ||
d38ceaf9 AD |
1360 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1361 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1362 | DRM_ERROR("disabled ip block: %d\n", i); | |
a1255107 | 1363 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1364 | } else { |
a1255107 AD |
1365 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1366 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1367 | if (r == -ENOENT) { |
a1255107 | 1368 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1369 | } else if (r) { |
a1255107 AD |
1370 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1371 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1372 | return r; |
2c1a2784 | 1373 | } else { |
a1255107 | 1374 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1375 | } |
974e6b64 | 1376 | } else { |
a1255107 | 1377 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1378 | } |
d38ceaf9 AD |
1379 | } |
1380 | } | |
1381 | ||
395d1fb9 NH |
1382 | adev->cg_flags &= amdgpu_cg_mask; |
1383 | adev->pg_flags &= amdgpu_pg_mask; | |
1384 | ||
d38ceaf9 AD |
1385 | return 0; |
1386 | } | |
1387 | ||
1388 | static int amdgpu_init(struct amdgpu_device *adev) | |
1389 | { | |
1390 | int i, r; | |
1391 | ||
1392 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1393 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1394 | continue; |
a1255107 | 1395 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1396 | if (r) { |
a1255107 AD |
1397 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1398 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1399 | return r; |
2c1a2784 | 1400 | } |
a1255107 | 1401 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1402 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1403 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1404 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1405 | if (r) { |
1406 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1407 | return r; |
2c1a2784 | 1408 | } |
a1255107 | 1409 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1410 | if (r) { |
1411 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1412 | return r; |
2c1a2784 | 1413 | } |
d38ceaf9 | 1414 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1415 | if (r) { |
1416 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1417 | return r; |
2c1a2784 | 1418 | } |
a1255107 | 1419 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1420 | } |
1421 | } | |
1422 | ||
1423 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1424 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1425 | continue; |
1426 | /* gmc hw init is done early */ | |
a1255107 | 1427 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1428 | continue; |
a1255107 | 1429 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1430 | if (r) { |
a1255107 AD |
1431 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1432 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1433 | return r; |
2c1a2784 | 1434 | } |
a1255107 | 1435 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1436 | } |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | ||
1441 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1442 | { | |
1443 | int i = 0, r; | |
1444 | ||
1445 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1446 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1447 | continue; |
a1255107 AD |
1448 | if (adev->ip_blocks[i].version->funcs->late_init) { |
1449 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2c1a2784 | 1450 | if (r) { |
a1255107 AD |
1451 | DRM_ERROR("late_init of IP block <%s> failed %d\n", |
1452 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1453 | return r; |
2c1a2784 | 1454 | } |
a1255107 | 1455 | adev->ip_blocks[i].status.late_initialized = true; |
d38ceaf9 | 1456 | } |
4a446d55 | 1457 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1458 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1459 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1460 | /* enable clockgating to save power */ |
a1255107 AD |
1461 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1462 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1463 | if (r) { |
1464 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1465 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1466 | return r; |
1467 | } | |
b0b00ff1 | 1468 | } |
d38ceaf9 AD |
1469 | } |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1475 | { | |
1476 | int i, r; | |
1477 | ||
3e96dbfd AD |
1478 | /* need to disable SMC first */ |
1479 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1480 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1481 | continue; |
a1255107 | 1482 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1483 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1484 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1485 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1486 | if (r) { |
1487 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1488 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1489 | return r; |
1490 | } | |
a1255107 | 1491 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1492 | /* XXX handle errors */ |
1493 | if (r) { | |
1494 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1495 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1496 | } |
a1255107 | 1497 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1498 | break; |
1499 | } | |
1500 | } | |
1501 | ||
d38ceaf9 | 1502 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1503 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1504 | continue; |
a1255107 | 1505 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1506 | amdgpu_wb_fini(adev); |
1507 | amdgpu_vram_scratch_fini(adev); | |
1508 | } | |
1509 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
a1255107 AD |
1510 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1511 | AMD_CG_STATE_UNGATE); | |
2c1a2784 | 1512 | if (r) { |
a1255107 AD |
1513 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1514 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1515 | return r; |
2c1a2784 | 1516 | } |
a1255107 | 1517 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1518 | /* XXX handle errors */ |
2c1a2784 | 1519 | if (r) { |
a1255107 AD |
1520 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1521 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1522 | } |
a1255107 | 1523 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1524 | } |
1525 | ||
1526 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1527 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1528 | continue; |
a1255107 | 1529 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1530 | /* XXX handle errors */ |
2c1a2784 | 1531 | if (r) { |
a1255107 AD |
1532 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1533 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1534 | } |
a1255107 AD |
1535 | adev->ip_blocks[i].status.sw = false; |
1536 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1537 | } |
1538 | ||
a6dcfd9c | 1539 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1540 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1541 | continue; |
a1255107 AD |
1542 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1543 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1544 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1545 | } |
1546 | ||
d38ceaf9 AD |
1547 | return 0; |
1548 | } | |
1549 | ||
1550 | static int amdgpu_suspend(struct amdgpu_device *adev) | |
1551 | { | |
1552 | int i, r; | |
1553 | ||
c5a93a28 FC |
1554 | /* ungate SMC block first */ |
1555 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1556 | AMD_CG_STATE_UNGATE); | |
1557 | if (r) { | |
1558 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1559 | } | |
1560 | ||
d38ceaf9 | 1561 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1562 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1563 | continue; |
1564 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1565 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1566 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1567 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1568 | if (r) { |
a1255107 AD |
1569 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1570 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1571 | } |
2c1a2784 | 1572 | } |
d38ceaf9 | 1573 | /* XXX handle errors */ |
a1255107 | 1574 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1575 | /* XXX handle errors */ |
2c1a2784 | 1576 | if (r) { |
a1255107 AD |
1577 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1578 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1579 | } |
d38ceaf9 AD |
1580 | } |
1581 | ||
1582 | return 0; | |
1583 | } | |
1584 | ||
1585 | static int amdgpu_resume(struct amdgpu_device *adev) | |
1586 | { | |
1587 | int i, r; | |
1588 | ||
1589 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1590 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1591 | continue; |
a1255107 | 1592 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1593 | if (r) { |
a1255107 AD |
1594 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1595 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1596 | return r; |
2c1a2784 | 1597 | } |
d38ceaf9 AD |
1598 | } |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
4e99a44e | 1603 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1604 | { |
4e99a44e ML |
1605 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) |
1606 | adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
048765ad AR |
1607 | } |
1608 | ||
d38ceaf9 AD |
1609 | /** |
1610 | * amdgpu_device_init - initialize the driver | |
1611 | * | |
1612 | * @adev: amdgpu_device pointer | |
1613 | * @pdev: drm dev pointer | |
1614 | * @pdev: pci dev pointer | |
1615 | * @flags: driver flags | |
1616 | * | |
1617 | * Initializes the driver info and hw (all asics). | |
1618 | * Returns 0 for success or an error on failure. | |
1619 | * Called at driver startup. | |
1620 | */ | |
1621 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1622 | struct drm_device *ddev, | |
1623 | struct pci_dev *pdev, | |
1624 | uint32_t flags) | |
1625 | { | |
1626 | int r, i; | |
1627 | bool runtime = false; | |
95844d20 | 1628 | u32 max_MBps; |
d38ceaf9 AD |
1629 | |
1630 | adev->shutdown = false; | |
1631 | adev->dev = &pdev->dev; | |
1632 | adev->ddev = ddev; | |
1633 | adev->pdev = pdev; | |
1634 | adev->flags = flags; | |
2f7d10b3 | 1635 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1636 | adev->is_atom_bios = false; |
1637 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; | |
1638 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1639 | adev->accel_working = false; | |
1640 | adev->num_rings = 0; | |
1641 | adev->mman.buffer_funcs = NULL; | |
1642 | adev->mman.buffer_funcs_ring = NULL; | |
1643 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1644 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 AD |
1645 | adev->gart.gart_funcs = NULL; |
1646 | adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); | |
1647 | ||
1648 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1649 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1650 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1651 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
1652 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
1653 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1654 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
1655 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1656 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1657 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
1658 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
1659 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1660 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
1661 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1662 | ||
ccdbb20a | 1663 | |
3e39ab90 AD |
1664 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1665 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1666 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1667 | |
1668 | /* mutex initialization are all done here so we | |
1669 | * can recall function without having locking issues */ | |
8d0a7cea | 1670 | mutex_init(&adev->vm_manager.lock); |
d38ceaf9 | 1671 | atomic_set(&adev->irq.ih.lock, 0); |
d38ceaf9 AD |
1672 | mutex_init(&adev->pm.mutex); |
1673 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1674 | mutex_init(&adev->srbm_mutex); | |
1675 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
1676 | mutex_init(&adev->mn_lock); |
1677 | hash_init(adev->mn_hash); | |
1678 | ||
1679 | amdgpu_check_arguments(adev); | |
1680 | ||
1681 | /* Registers mapping */ | |
1682 | /* TODO: block userspace mapping of io register */ | |
1683 | spin_lock_init(&adev->mmio_idx_lock); | |
1684 | spin_lock_init(&adev->smc_idx_lock); | |
1685 | spin_lock_init(&adev->pcie_idx_lock); | |
1686 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1687 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 1688 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 1689 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 1690 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 1691 | |
0c4e7fa5 CZ |
1692 | INIT_LIST_HEAD(&adev->shadow_list); |
1693 | mutex_init(&adev->shadow_list_lock); | |
1694 | ||
5c1354bd CZ |
1695 | INIT_LIST_HEAD(&adev->gtt_list); |
1696 | spin_lock_init(&adev->gtt_list_lock); | |
1697 | ||
da69c161 KW |
1698 | if (adev->asic_type >= CHIP_BONAIRE) { |
1699 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1700 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1701 | } else { | |
1702 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
1703 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
1704 | } | |
d38ceaf9 | 1705 | |
d38ceaf9 AD |
1706 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
1707 | if (adev->rmmio == NULL) { | |
1708 | return -ENOMEM; | |
1709 | } | |
1710 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1711 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1712 | ||
da69c161 KW |
1713 | if (adev->asic_type >= CHIP_BONAIRE) |
1714 | /* doorbell bar mapping */ | |
1715 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
1716 | |
1717 | /* io port mapping */ | |
1718 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1719 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1720 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1721 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1722 | break; | |
1723 | } | |
1724 | } | |
1725 | if (adev->rio_mem == NULL) | |
1726 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
1727 | ||
1728 | /* early init functions */ | |
1729 | r = amdgpu_early_init(adev); | |
1730 | if (r) | |
1731 | return r; | |
1732 | ||
1733 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1734 | /* this will fail for cards that aren't VGA class devices, just | |
1735 | * ignore it */ | |
1736 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1737 | ||
1738 | if (amdgpu_runtime_pm == 1) | |
1739 | runtime = true; | |
e9bef455 | 1740 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 AD |
1741 | runtime = true; |
1742 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1743 | if (runtime) | |
1744 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1745 | ||
1746 | /* Read BIOS */ | |
83ba126a AD |
1747 | if (!amdgpu_get_bios(adev)) { |
1748 | r = -EINVAL; | |
1749 | goto failed; | |
1750 | } | |
d38ceaf9 AD |
1751 | /* Must be an ATOMBIOS */ |
1752 | if (!adev->is_atom_bios) { | |
1753 | dev_err(adev->dev, "Expecting atombios for GPU\n"); | |
83ba126a AD |
1754 | r = -EINVAL; |
1755 | goto failed; | |
d38ceaf9 AD |
1756 | } |
1757 | r = amdgpu_atombios_init(adev); | |
2c1a2784 AD |
1758 | if (r) { |
1759 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 1760 | goto failed; |
2c1a2784 | 1761 | } |
d38ceaf9 | 1762 | |
4e99a44e ML |
1763 | /* detect if we are with an SRIOV vbios */ |
1764 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 1765 | |
d38ceaf9 | 1766 | /* Post card if necessary */ |
bec86378 | 1767 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 1768 | if (!adev->bios) { |
bec86378 | 1769 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
1770 | r = -EINVAL; |
1771 | goto failed; | |
d38ceaf9 | 1772 | } |
bec86378 | 1773 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
1774 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
1775 | if (r) { | |
1776 | dev_err(adev->dev, "gpu post error!\n"); | |
1777 | goto failed; | |
1778 | } | |
1779 | } else { | |
1780 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
1781 | } |
1782 | ||
1783 | /* Initialize clocks */ | |
1784 | r = amdgpu_atombios_get_clock_info(adev); | |
2c1a2784 AD |
1785 | if (r) { |
1786 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
83ba126a | 1787 | goto failed; |
2c1a2784 | 1788 | } |
d38ceaf9 AD |
1789 | /* init i2c buses */ |
1790 | amdgpu_atombios_i2c_init(adev); | |
1791 | ||
1792 | /* Fence driver */ | |
1793 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1794 | if (r) { |
1795 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 1796 | goto failed; |
2c1a2784 | 1797 | } |
d38ceaf9 AD |
1798 | |
1799 | /* init the mode config */ | |
1800 | drm_mode_config_init(adev->ddev); | |
1801 | ||
1802 | r = amdgpu_init(adev); | |
1803 | if (r) { | |
2c1a2784 | 1804 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 1805 | amdgpu_fini(adev); |
83ba126a | 1806 | goto failed; |
d38ceaf9 AD |
1807 | } |
1808 | ||
1809 | adev->accel_working = true; | |
1810 | ||
95844d20 MO |
1811 | /* Initialize the buffer migration limit. */ |
1812 | if (amdgpu_moverate >= 0) | |
1813 | max_MBps = amdgpu_moverate; | |
1814 | else | |
1815 | max_MBps = 8; /* Allow 8 MB/s. */ | |
1816 | /* Get a log2 for easy divisions. */ | |
1817 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
1818 | ||
d38ceaf9 AD |
1819 | amdgpu_fbdev_init(adev); |
1820 | ||
1821 | r = amdgpu_ib_pool_init(adev); | |
1822 | if (r) { | |
1823 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 1824 | goto failed; |
d38ceaf9 AD |
1825 | } |
1826 | ||
1827 | r = amdgpu_ib_ring_tests(adev); | |
1828 | if (r) | |
1829 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1830 | ||
1831 | r = amdgpu_gem_debugfs_init(adev); | |
1832 | if (r) { | |
1833 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); | |
1834 | } | |
1835 | ||
1836 | r = amdgpu_debugfs_regs_init(adev); | |
1837 | if (r) { | |
1838 | DRM_ERROR("registering register debugfs failed (%d).\n", r); | |
1839 | } | |
1840 | ||
50ab2533 HR |
1841 | r = amdgpu_debugfs_firmware_init(adev); |
1842 | if (r) { | |
1843 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); | |
1844 | return r; | |
1845 | } | |
1846 | ||
d38ceaf9 AD |
1847 | if ((amdgpu_testing & 1)) { |
1848 | if (adev->accel_working) | |
1849 | amdgpu_test_moves(adev); | |
1850 | else | |
1851 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
1852 | } | |
1853 | if ((amdgpu_testing & 2)) { | |
1854 | if (adev->accel_working) | |
1855 | amdgpu_test_syncing(adev); | |
1856 | else | |
1857 | DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); | |
1858 | } | |
1859 | if (amdgpu_benchmarking) { | |
1860 | if (adev->accel_working) | |
1861 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
1862 | else | |
1863 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
1864 | } | |
1865 | ||
1866 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
1867 | * explicit gating rather than handling it automatically. | |
1868 | */ | |
1869 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
1870 | if (r) { |
1871 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 1872 | goto failed; |
2c1a2784 | 1873 | } |
d38ceaf9 AD |
1874 | |
1875 | return 0; | |
83ba126a AD |
1876 | |
1877 | failed: | |
1878 | if (runtime) | |
1879 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
1880 | return r; | |
d38ceaf9 AD |
1881 | } |
1882 | ||
1883 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev); | |
1884 | ||
1885 | /** | |
1886 | * amdgpu_device_fini - tear down the driver | |
1887 | * | |
1888 | * @adev: amdgpu_device pointer | |
1889 | * | |
1890 | * Tear down the driver info (all asics). | |
1891 | * Called at driver shutdown. | |
1892 | */ | |
1893 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
1894 | { | |
1895 | int r; | |
1896 | ||
1897 | DRM_INFO("amdgpu: finishing device.\n"); | |
1898 | adev->shutdown = true; | |
a951ed85 | 1899 | drm_crtc_force_disable_all(adev->ddev); |
d38ceaf9 AD |
1900 | /* evict vram memory */ |
1901 | amdgpu_bo_evict_vram(adev); | |
1902 | amdgpu_ib_pool_fini(adev); | |
1903 | amdgpu_fence_driver_fini(adev); | |
1904 | amdgpu_fbdev_fini(adev); | |
1905 | r = amdgpu_fini(adev); | |
d38ceaf9 AD |
1906 | adev->accel_working = false; |
1907 | /* free i2c buses */ | |
1908 | amdgpu_i2c_fini(adev); | |
1909 | amdgpu_atombios_fini(adev); | |
1910 | kfree(adev->bios); | |
1911 | adev->bios = NULL; | |
1912 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
1913 | if (adev->flags & AMD_IS_PX) |
1914 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
1915 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
1916 | if (adev->rio_mem) | |
1917 | pci_iounmap(adev->pdev, adev->rio_mem); | |
1918 | adev->rio_mem = NULL; | |
1919 | iounmap(adev->rmmio); | |
1920 | adev->rmmio = NULL; | |
da69c161 KW |
1921 | if (adev->asic_type >= CHIP_BONAIRE) |
1922 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 AD |
1923 | amdgpu_debugfs_regs_cleanup(adev); |
1924 | amdgpu_debugfs_remove_files(adev); | |
1925 | } | |
1926 | ||
1927 | ||
1928 | /* | |
1929 | * Suspend & resume. | |
1930 | */ | |
1931 | /** | |
810ddc3a | 1932 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
1933 | * |
1934 | * @pdev: drm dev pointer | |
1935 | * @state: suspend state | |
1936 | * | |
1937 | * Puts the hw in the suspend state (all asics). | |
1938 | * Returns 0 for success or an error on failure. | |
1939 | * Called at driver suspend. | |
1940 | */ | |
810ddc3a | 1941 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
1942 | { |
1943 | struct amdgpu_device *adev; | |
1944 | struct drm_crtc *crtc; | |
1945 | struct drm_connector *connector; | |
5ceb54c6 | 1946 | int r; |
d38ceaf9 AD |
1947 | |
1948 | if (dev == NULL || dev->dev_private == NULL) { | |
1949 | return -ENODEV; | |
1950 | } | |
1951 | ||
1952 | adev = dev->dev_private; | |
1953 | ||
1954 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1955 | return 0; | |
1956 | ||
1957 | drm_kms_helper_poll_disable(dev); | |
1958 | ||
1959 | /* turn off display hw */ | |
4c7fbc39 | 1960 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
1961 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1962 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
1963 | } | |
4c7fbc39 | 1964 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 1965 | |
756e6880 | 1966 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 1967 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 1968 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
1969 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
1970 | struct amdgpu_bo *robj; | |
1971 | ||
756e6880 AD |
1972 | if (amdgpu_crtc->cursor_bo) { |
1973 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
1974 | r = amdgpu_bo_reserve(aobj, false); | |
1975 | if (r == 0) { | |
1976 | amdgpu_bo_unpin(aobj); | |
1977 | amdgpu_bo_unreserve(aobj); | |
1978 | } | |
1979 | } | |
1980 | ||
d38ceaf9 AD |
1981 | if (rfb == NULL || rfb->obj == NULL) { |
1982 | continue; | |
1983 | } | |
1984 | robj = gem_to_amdgpu_bo(rfb->obj); | |
1985 | /* don't unpin kernel fb objects */ | |
1986 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
1987 | r = amdgpu_bo_reserve(robj, false); | |
1988 | if (r == 0) { | |
1989 | amdgpu_bo_unpin(robj); | |
1990 | amdgpu_bo_unreserve(robj); | |
1991 | } | |
1992 | } | |
1993 | } | |
1994 | /* evict vram memory */ | |
1995 | amdgpu_bo_evict_vram(adev); | |
1996 | ||
5ceb54c6 | 1997 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
1998 | |
1999 | r = amdgpu_suspend(adev); | |
2000 | ||
a0a71e49 AD |
2001 | /* evict remaining vram memory |
2002 | * This second call to evict vram is to evict the gart page table | |
2003 | * using the CPU. | |
2004 | */ | |
d38ceaf9 AD |
2005 | amdgpu_bo_evict_vram(adev); |
2006 | ||
2007 | pci_save_state(dev->pdev); | |
2008 | if (suspend) { | |
2009 | /* Shut down the device */ | |
2010 | pci_disable_device(dev->pdev); | |
2011 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2012 | } else { |
2013 | r = amdgpu_asic_reset(adev); | |
2014 | if (r) | |
2015 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2016 | } |
2017 | ||
2018 | if (fbcon) { | |
2019 | console_lock(); | |
2020 | amdgpu_fbdev_set_suspend(adev, 1); | |
2021 | console_unlock(); | |
2022 | } | |
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | /** | |
810ddc3a | 2027 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2028 | * |
2029 | * @pdev: drm dev pointer | |
2030 | * | |
2031 | * Bring the hw back to operating state (all asics). | |
2032 | * Returns 0 for success or an error on failure. | |
2033 | * Called at driver resume. | |
2034 | */ | |
810ddc3a | 2035 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2036 | { |
2037 | struct drm_connector *connector; | |
2038 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2039 | struct drm_crtc *crtc; |
d38ceaf9 AD |
2040 | int r; |
2041 | ||
2042 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2043 | return 0; | |
2044 | ||
74b0b157 | 2045 | if (fbcon) |
d38ceaf9 | 2046 | console_lock(); |
74b0b157 | 2047 | |
d38ceaf9 AD |
2048 | if (resume) { |
2049 | pci_set_power_state(dev->pdev, PCI_D0); | |
2050 | pci_restore_state(dev->pdev); | |
74b0b157 | 2051 | r = pci_enable_device(dev->pdev); |
2052 | if (r) { | |
d38ceaf9 AD |
2053 | if (fbcon) |
2054 | console_unlock(); | |
74b0b157 | 2055 | return r; |
d38ceaf9 AD |
2056 | } |
2057 | } | |
2058 | ||
2059 | /* post card */ | |
74b0b157 | 2060 | if (!amdgpu_card_posted(adev) || !resume) { |
2061 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2062 | if (r) | |
2063 | DRM_ERROR("amdgpu asic init failed\n"); | |
2064 | } | |
d38ceaf9 AD |
2065 | |
2066 | r = amdgpu_resume(adev); | |
ca198528 FC |
2067 | if (r) |
2068 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); | |
d38ceaf9 | 2069 | |
5ceb54c6 AD |
2070 | amdgpu_fence_driver_resume(adev); |
2071 | ||
ca198528 FC |
2072 | if (resume) { |
2073 | r = amdgpu_ib_ring_tests(adev); | |
2074 | if (r) | |
2075 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2076 | } | |
d38ceaf9 AD |
2077 | |
2078 | r = amdgpu_late_init(adev); | |
2079 | if (r) | |
2080 | return r; | |
2081 | ||
756e6880 AD |
2082 | /* pin cursors */ |
2083 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2084 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2085 | ||
2086 | if (amdgpu_crtc->cursor_bo) { | |
2087 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2088 | r = amdgpu_bo_reserve(aobj, false); | |
2089 | if (r == 0) { | |
2090 | r = amdgpu_bo_pin(aobj, | |
2091 | AMDGPU_GEM_DOMAIN_VRAM, | |
2092 | &amdgpu_crtc->cursor_addr); | |
2093 | if (r != 0) | |
2094 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2095 | amdgpu_bo_unreserve(aobj); | |
2096 | } | |
2097 | } | |
2098 | } | |
2099 | ||
d38ceaf9 AD |
2100 | /* blat the mode back in */ |
2101 | if (fbcon) { | |
2102 | drm_helper_resume_force_mode(dev); | |
2103 | /* turn on display hw */ | |
4c7fbc39 | 2104 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2105 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2106 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2107 | } | |
4c7fbc39 | 2108 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2109 | } |
2110 | ||
2111 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2112 | |
2113 | /* | |
2114 | * Most of the connector probing functions try to acquire runtime pm | |
2115 | * refs to ensure that the GPU is powered on when connector polling is | |
2116 | * performed. Since we're calling this from a runtime PM callback, | |
2117 | * trying to acquire rpm refs will cause us to deadlock. | |
2118 | * | |
2119 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2120 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2121 | */ | |
2122 | #ifdef CONFIG_PM | |
2123 | dev->dev->power.disable_depth++; | |
2124 | #endif | |
54fb2a5c | 2125 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2126 | #ifdef CONFIG_PM |
2127 | dev->dev->power.disable_depth--; | |
2128 | #endif | |
d38ceaf9 AD |
2129 | |
2130 | if (fbcon) { | |
2131 | amdgpu_fbdev_set_suspend(adev, 0); | |
2132 | console_unlock(); | |
2133 | } | |
2134 | ||
2135 | return 0; | |
2136 | } | |
2137 | ||
63fbf42f CZ |
2138 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2139 | { | |
2140 | int i; | |
2141 | bool asic_hang = false; | |
2142 | ||
2143 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2144 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2145 | continue; |
a1255107 AD |
2146 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2147 | adev->ip_blocks[i].status.hang = | |
2148 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2149 | if (adev->ip_blocks[i].status.hang) { | |
2150 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2151 | asic_hang = true; |
2152 | } | |
2153 | } | |
2154 | return asic_hang; | |
2155 | } | |
2156 | ||
4d446656 | 2157 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2158 | { |
2159 | int i, r = 0; | |
2160 | ||
2161 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2162 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2163 | continue; |
a1255107 AD |
2164 | if (adev->ip_blocks[i].status.hang && |
2165 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2166 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2167 | if (r) |
2168 | return r; | |
2169 | } | |
2170 | } | |
2171 | ||
2172 | return 0; | |
2173 | } | |
2174 | ||
35d782fe CZ |
2175 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2176 | { | |
da146d3b AD |
2177 | int i; |
2178 | ||
2179 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2180 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2181 | continue; |
a1255107 AD |
2182 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2183 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2184 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2185 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2186 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2187 | DRM_INFO("Some block need full reset!\n"); |
2188 | return true; | |
2189 | } | |
2190 | } | |
35d782fe CZ |
2191 | } |
2192 | return false; | |
2193 | } | |
2194 | ||
2195 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2196 | { | |
2197 | int i, r = 0; | |
2198 | ||
2199 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2200 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2201 | continue; |
a1255107 AD |
2202 | if (adev->ip_blocks[i].status.hang && |
2203 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2204 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2205 | if (r) |
2206 | return r; | |
2207 | } | |
2208 | } | |
2209 | ||
2210 | return 0; | |
2211 | } | |
2212 | ||
2213 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2214 | { | |
2215 | int i, r = 0; | |
2216 | ||
2217 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2218 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2219 | continue; |
a1255107 AD |
2220 | if (adev->ip_blocks[i].status.hang && |
2221 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2222 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2223 | if (r) |
2224 | return r; | |
2225 | } | |
2226 | ||
2227 | return 0; | |
2228 | } | |
2229 | ||
3ad81f16 CZ |
2230 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2231 | { | |
2232 | if (adev->flags & AMD_IS_APU) | |
2233 | return false; | |
2234 | ||
2235 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2236 | } | |
2237 | ||
53cdccd5 CZ |
2238 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2239 | struct amdgpu_ring *ring, | |
2240 | struct amdgpu_bo *bo, | |
2241 | struct fence **fence) | |
2242 | { | |
2243 | uint32_t domain; | |
2244 | int r; | |
2245 | ||
2246 | if (!bo->shadow) | |
2247 | return 0; | |
2248 | ||
2249 | r = amdgpu_bo_reserve(bo, false); | |
2250 | if (r) | |
2251 | return r; | |
2252 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2253 | /* if bo has been evicted, then no need to recover */ | |
2254 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
2255 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, | |
2256 | NULL, fence, true); | |
2257 | if (r) { | |
2258 | DRM_ERROR("recover page table failed!\n"); | |
2259 | goto err; | |
2260 | } | |
2261 | } | |
2262 | err: | |
2263 | amdgpu_bo_unreserve(bo); | |
2264 | return r; | |
2265 | } | |
2266 | ||
d38ceaf9 AD |
2267 | /** |
2268 | * amdgpu_gpu_reset - reset the asic | |
2269 | * | |
2270 | * @adev: amdgpu device pointer | |
2271 | * | |
2272 | * Attempt the reset the GPU if it has hung (all asics). | |
2273 | * Returns 0 for success or an error on failure. | |
2274 | */ | |
2275 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2276 | { | |
d38ceaf9 AD |
2277 | int i, r; |
2278 | int resched; | |
35d782fe | 2279 | bool need_full_reset; |
d38ceaf9 | 2280 | |
63fbf42f CZ |
2281 | if (!amdgpu_check_soft_reset(adev)) { |
2282 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2283 | return 0; | |
2284 | } | |
d38ceaf9 | 2285 | |
d94aed5a | 2286 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2287 | |
a3c47d6b CZ |
2288 | /* block TTM */ |
2289 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2290 | ||
0875dc9e CZ |
2291 | /* block scheduler */ |
2292 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2293 | struct amdgpu_ring *ring = adev->rings[i]; | |
2294 | ||
2295 | if (!ring) | |
2296 | continue; | |
2297 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2298 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2299 | } |
2200edac CZ |
2300 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2301 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2302 | |
35d782fe | 2303 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2304 | |
35d782fe CZ |
2305 | if (!need_full_reset) { |
2306 | amdgpu_pre_soft_reset(adev); | |
2307 | r = amdgpu_soft_reset(adev); | |
2308 | amdgpu_post_soft_reset(adev); | |
2309 | if (r || amdgpu_check_soft_reset(adev)) { | |
2310 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2311 | need_full_reset = true; | |
2312 | } | |
f1aa7e08 CZ |
2313 | } |
2314 | ||
35d782fe CZ |
2315 | if (need_full_reset) { |
2316 | /* save scratch */ | |
2317 | amdgpu_atombios_scratch_regs_save(adev); | |
2318 | r = amdgpu_suspend(adev); | |
bfa99269 | 2319 | |
35d782fe CZ |
2320 | retry: |
2321 | /* Disable fb access */ | |
2322 | if (adev->mode_info.num_crtc) { | |
2323 | struct amdgpu_mode_mc_save save; | |
2324 | amdgpu_display_stop_mc_access(adev, &save); | |
2325 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
2326 | } | |
2327 | ||
2328 | r = amdgpu_asic_reset(adev); | |
2329 | /* post card */ | |
2330 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2331 | ||
2332 | if (!r) { | |
2333 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
2334 | r = amdgpu_resume(adev); | |
2335 | } | |
2336 | /* restore scratch */ | |
2337 | amdgpu_atombios_scratch_regs_restore(adev); | |
d38ceaf9 | 2338 | } |
d38ceaf9 | 2339 | if (!r) { |
e72cfd58 | 2340 | amdgpu_irq_gpu_reset_resume_helper(adev); |
2c0d7318 CZ |
2341 | if (need_full_reset && amdgpu_need_backup(adev)) { |
2342 | r = amdgpu_ttm_recover_gart(adev); | |
2343 | if (r) | |
2344 | DRM_ERROR("gart recovery failed!!!\n"); | |
2345 | } | |
1f465087 CZ |
2346 | r = amdgpu_ib_ring_tests(adev); |
2347 | if (r) { | |
2348 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2349 | r = amdgpu_suspend(adev); |
53cdccd5 | 2350 | need_full_reset = true; |
40019dc4 | 2351 | goto retry; |
1f465087 | 2352 | } |
53cdccd5 CZ |
2353 | /** |
2354 | * recovery vm page tables, since we cannot depend on VRAM is | |
2355 | * consistent after gpu full reset. | |
2356 | */ | |
2357 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2358 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2359 | struct amdgpu_bo *bo, *tmp; | |
2360 | struct fence *fence = NULL, *next = NULL; | |
2361 | ||
2362 | DRM_INFO("recover vram bo from shadow\n"); | |
2363 | mutex_lock(&adev->shadow_list_lock); | |
2364 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2365 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); | |
2366 | if (fence) { | |
2367 | r = fence_wait(fence, false); | |
2368 | if (r) { | |
2369 | WARN(r, "recovery from shadow isn't comleted\n"); | |
2370 | break; | |
2371 | } | |
2372 | } | |
1f465087 | 2373 | |
53cdccd5 CZ |
2374 | fence_put(fence); |
2375 | fence = next; | |
2376 | } | |
2377 | mutex_unlock(&adev->shadow_list_lock); | |
2378 | if (fence) { | |
2379 | r = fence_wait(fence, false); | |
2380 | if (r) | |
2381 | WARN(r, "recovery from shadow isn't comleted\n"); | |
2382 | } | |
2383 | fence_put(fence); | |
2384 | } | |
d38ceaf9 AD |
2385 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2386 | struct amdgpu_ring *ring = adev->rings[i]; | |
2387 | if (!ring) | |
2388 | continue; | |
53cdccd5 | 2389 | |
aa1c8900 | 2390 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2391 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2392 | } |
d38ceaf9 | 2393 | } else { |
2200edac | 2394 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2395 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
0875dc9e CZ |
2396 | if (adev->rings[i]) { |
2397 | kthread_unpark(adev->rings[i]->sched.thread); | |
0875dc9e | 2398 | } |
d38ceaf9 AD |
2399 | } |
2400 | } | |
2401 | ||
2402 | drm_helper_resume_force_mode(adev->ddev); | |
2403 | ||
2404 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2405 | if (r) { | |
2406 | /* bad news, how to tell it to userspace ? */ | |
2407 | dev_info(adev->dev, "GPU reset failed\n"); | |
2408 | } | |
2409 | ||
d38ceaf9 AD |
2410 | return r; |
2411 | } | |
2412 | ||
d0dd7f0c AD |
2413 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2414 | { | |
2415 | u32 mask; | |
2416 | int ret; | |
2417 | ||
cd474ba0 AD |
2418 | if (amdgpu_pcie_gen_cap) |
2419 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2420 | |
cd474ba0 AD |
2421 | if (amdgpu_pcie_lane_cap) |
2422 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2423 | |
cd474ba0 AD |
2424 | /* covers APUs as well */ |
2425 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2426 | if (adev->pm.pcie_gen_mask == 0) | |
2427 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2428 | if (adev->pm.pcie_mlw_mask == 0) | |
2429 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2430 | return; |
cd474ba0 | 2431 | } |
d0dd7f0c | 2432 | |
cd474ba0 AD |
2433 | if (adev->pm.pcie_gen_mask == 0) { |
2434 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2435 | if (!ret) { | |
2436 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2437 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2438 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2439 | ||
2440 | if (mask & DRM_PCIE_SPEED_25) | |
2441 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2442 | if (mask & DRM_PCIE_SPEED_50) | |
2443 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2444 | if (mask & DRM_PCIE_SPEED_80) | |
2445 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2446 | } else { | |
2447 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2448 | } | |
2449 | } | |
2450 | if (adev->pm.pcie_mlw_mask == 0) { | |
2451 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2452 | if (!ret) { | |
2453 | switch (mask) { | |
2454 | case 32: | |
2455 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2456 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2457 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2458 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2459 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2460 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2461 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2462 | break; | |
2463 | case 16: | |
2464 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2465 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2466 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2467 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2468 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2469 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2470 | break; | |
2471 | case 12: | |
2472 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2473 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2474 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2475 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2476 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2477 | break; | |
2478 | case 8: | |
2479 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2480 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2481 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2482 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2483 | break; | |
2484 | case 4: | |
2485 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2486 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2487 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2488 | break; | |
2489 | case 2: | |
2490 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2491 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2492 | break; | |
2493 | case 1: | |
2494 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2495 | break; | |
2496 | default: | |
2497 | break; | |
2498 | } | |
2499 | } else { | |
2500 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2501 | } |
2502 | } | |
2503 | } | |
d38ceaf9 AD |
2504 | |
2505 | /* | |
2506 | * Debugfs | |
2507 | */ | |
2508 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 2509 | const struct drm_info_list *files, |
d38ceaf9 AD |
2510 | unsigned nfiles) |
2511 | { | |
2512 | unsigned i; | |
2513 | ||
2514 | for (i = 0; i < adev->debugfs_count; i++) { | |
2515 | if (adev->debugfs[i].files == files) { | |
2516 | /* Already registered */ | |
2517 | return 0; | |
2518 | } | |
2519 | } | |
2520 | ||
2521 | i = adev->debugfs_count + 1; | |
2522 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
2523 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
2524 | DRM_ERROR("Report so we increase " | |
2525 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
2526 | return -EINVAL; | |
2527 | } | |
2528 | adev->debugfs[adev->debugfs_count].files = files; | |
2529 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
2530 | adev->debugfs_count = i; | |
2531 | #if defined(CONFIG_DEBUG_FS) | |
2532 | drm_debugfs_create_files(files, nfiles, | |
2533 | adev->ddev->control->debugfs_root, | |
2534 | adev->ddev->control); | |
2535 | drm_debugfs_create_files(files, nfiles, | |
2536 | adev->ddev->primary->debugfs_root, | |
2537 | adev->ddev->primary); | |
2538 | #endif | |
2539 | return 0; | |
2540 | } | |
2541 | ||
2542 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) | |
2543 | { | |
2544 | #if defined(CONFIG_DEBUG_FS) | |
2545 | unsigned i; | |
2546 | ||
2547 | for (i = 0; i < adev->debugfs_count; i++) { | |
2548 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2549 | adev->debugfs[i].num_files, | |
2550 | adev->ddev->control); | |
2551 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2552 | adev->debugfs[i].num_files, | |
2553 | adev->ddev->primary); | |
2554 | } | |
2555 | #endif | |
2556 | } | |
2557 | ||
2558 | #if defined(CONFIG_DEBUG_FS) | |
2559 | ||
2560 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
2561 | size_t size, loff_t *pos) | |
2562 | { | |
2563 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2564 | ssize_t result = 0; | |
2565 | int r; | |
bd12267d | 2566 | bool pm_pg_lock, use_bank; |
56628159 | 2567 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
2568 | |
2569 | if (size & 0x3 || *pos & 0x3) | |
2570 | return -EINVAL; | |
2571 | ||
bd12267d TSD |
2572 | /* are we reading registers for which a PG lock is necessary? */ |
2573 | pm_pg_lock = (*pos >> 23) & 1; | |
2574 | ||
56628159 TSD |
2575 | if (*pos & (1ULL << 62)) { |
2576 | se_bank = (*pos >> 24) & 0x3FF; | |
2577 | sh_bank = (*pos >> 34) & 0x3FF; | |
2578 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
2579 | |
2580 | if (se_bank == 0x3FF) | |
2581 | se_bank = 0xFFFFFFFF; | |
2582 | if (sh_bank == 0x3FF) | |
2583 | sh_bank = 0xFFFFFFFF; | |
2584 | if (instance_bank == 0x3FF) | |
2585 | instance_bank = 0xFFFFFFFF; | |
56628159 | 2586 | use_bank = 1; |
56628159 TSD |
2587 | } else { |
2588 | use_bank = 0; | |
2589 | } | |
2590 | ||
bd12267d TSD |
2591 | *pos &= 0x3FFFF; |
2592 | ||
56628159 | 2593 | if (use_bank) { |
32977f93 TSD |
2594 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
2595 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
2596 | return -EINVAL; |
2597 | mutex_lock(&adev->grbm_idx_mutex); | |
2598 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2599 | sh_bank, instance_bank); | |
2600 | } | |
2601 | ||
bd12267d TSD |
2602 | if (pm_pg_lock) |
2603 | mutex_lock(&adev->pm.mutex); | |
2604 | ||
d38ceaf9 AD |
2605 | while (size) { |
2606 | uint32_t value; | |
2607 | ||
2608 | if (*pos > adev->rmmio_size) | |
56628159 | 2609 | goto end; |
d38ceaf9 AD |
2610 | |
2611 | value = RREG32(*pos >> 2); | |
2612 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
2613 | if (r) { |
2614 | result = r; | |
2615 | goto end; | |
2616 | } | |
d38ceaf9 AD |
2617 | |
2618 | result += 4; | |
2619 | buf += 4; | |
2620 | *pos += 4; | |
2621 | size -= 4; | |
2622 | } | |
2623 | ||
56628159 TSD |
2624 | end: |
2625 | if (use_bank) { | |
2626 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2627 | mutex_unlock(&adev->grbm_idx_mutex); | |
2628 | } | |
2629 | ||
bd12267d TSD |
2630 | if (pm_pg_lock) |
2631 | mutex_unlock(&adev->pm.mutex); | |
2632 | ||
d38ceaf9 AD |
2633 | return result; |
2634 | } | |
2635 | ||
2636 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
2637 | size_t size, loff_t *pos) | |
2638 | { | |
2639 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2640 | ssize_t result = 0; | |
2641 | int r; | |
2642 | ||
2643 | if (size & 0x3 || *pos & 0x3) | |
2644 | return -EINVAL; | |
2645 | ||
2646 | while (size) { | |
2647 | uint32_t value; | |
2648 | ||
2649 | if (*pos > adev->rmmio_size) | |
2650 | return result; | |
2651 | ||
2652 | r = get_user(value, (uint32_t *)buf); | |
2653 | if (r) | |
2654 | return r; | |
2655 | ||
2656 | WREG32(*pos >> 2, value); | |
2657 | ||
2658 | result += 4; | |
2659 | buf += 4; | |
2660 | *pos += 4; | |
2661 | size -= 4; | |
2662 | } | |
2663 | ||
2664 | return result; | |
2665 | } | |
2666 | ||
adcec288 TSD |
2667 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
2668 | size_t size, loff_t *pos) | |
2669 | { | |
2670 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2671 | ssize_t result = 0; | |
2672 | int r; | |
2673 | ||
2674 | if (size & 0x3 || *pos & 0x3) | |
2675 | return -EINVAL; | |
2676 | ||
2677 | while (size) { | |
2678 | uint32_t value; | |
2679 | ||
2680 | value = RREG32_PCIE(*pos >> 2); | |
2681 | r = put_user(value, (uint32_t *)buf); | |
2682 | if (r) | |
2683 | return r; | |
2684 | ||
2685 | result += 4; | |
2686 | buf += 4; | |
2687 | *pos += 4; | |
2688 | size -= 4; | |
2689 | } | |
2690 | ||
2691 | return result; | |
2692 | } | |
2693 | ||
2694 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
2695 | size_t size, loff_t *pos) | |
2696 | { | |
2697 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2698 | ssize_t result = 0; | |
2699 | int r; | |
2700 | ||
2701 | if (size & 0x3 || *pos & 0x3) | |
2702 | return -EINVAL; | |
2703 | ||
2704 | while (size) { | |
2705 | uint32_t value; | |
2706 | ||
2707 | r = get_user(value, (uint32_t *)buf); | |
2708 | if (r) | |
2709 | return r; | |
2710 | ||
2711 | WREG32_PCIE(*pos >> 2, value); | |
2712 | ||
2713 | result += 4; | |
2714 | buf += 4; | |
2715 | *pos += 4; | |
2716 | size -= 4; | |
2717 | } | |
2718 | ||
2719 | return result; | |
2720 | } | |
2721 | ||
2722 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
2723 | size_t size, loff_t *pos) | |
2724 | { | |
2725 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2726 | ssize_t result = 0; | |
2727 | int r; | |
2728 | ||
2729 | if (size & 0x3 || *pos & 0x3) | |
2730 | return -EINVAL; | |
2731 | ||
2732 | while (size) { | |
2733 | uint32_t value; | |
2734 | ||
2735 | value = RREG32_DIDT(*pos >> 2); | |
2736 | r = put_user(value, (uint32_t *)buf); | |
2737 | if (r) | |
2738 | return r; | |
2739 | ||
2740 | result += 4; | |
2741 | buf += 4; | |
2742 | *pos += 4; | |
2743 | size -= 4; | |
2744 | } | |
2745 | ||
2746 | return result; | |
2747 | } | |
2748 | ||
2749 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
2750 | size_t size, loff_t *pos) | |
2751 | { | |
2752 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2753 | ssize_t result = 0; | |
2754 | int r; | |
2755 | ||
2756 | if (size & 0x3 || *pos & 0x3) | |
2757 | return -EINVAL; | |
2758 | ||
2759 | while (size) { | |
2760 | uint32_t value; | |
2761 | ||
2762 | r = get_user(value, (uint32_t *)buf); | |
2763 | if (r) | |
2764 | return r; | |
2765 | ||
2766 | WREG32_DIDT(*pos >> 2, value); | |
2767 | ||
2768 | result += 4; | |
2769 | buf += 4; | |
2770 | *pos += 4; | |
2771 | size -= 4; | |
2772 | } | |
2773 | ||
2774 | return result; | |
2775 | } | |
2776 | ||
2777 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
2778 | size_t size, loff_t *pos) | |
2779 | { | |
2780 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2781 | ssize_t result = 0; | |
2782 | int r; | |
2783 | ||
2784 | if (size & 0x3 || *pos & 0x3) | |
2785 | return -EINVAL; | |
2786 | ||
2787 | while (size) { | |
2788 | uint32_t value; | |
2789 | ||
6fc0deaf | 2790 | value = RREG32_SMC(*pos); |
adcec288 TSD |
2791 | r = put_user(value, (uint32_t *)buf); |
2792 | if (r) | |
2793 | return r; | |
2794 | ||
2795 | result += 4; | |
2796 | buf += 4; | |
2797 | *pos += 4; | |
2798 | size -= 4; | |
2799 | } | |
2800 | ||
2801 | return result; | |
2802 | } | |
2803 | ||
2804 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
2805 | size_t size, loff_t *pos) | |
2806 | { | |
2807 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2808 | ssize_t result = 0; | |
2809 | int r; | |
2810 | ||
2811 | if (size & 0x3 || *pos & 0x3) | |
2812 | return -EINVAL; | |
2813 | ||
2814 | while (size) { | |
2815 | uint32_t value; | |
2816 | ||
2817 | r = get_user(value, (uint32_t *)buf); | |
2818 | if (r) | |
2819 | return r; | |
2820 | ||
6fc0deaf | 2821 | WREG32_SMC(*pos, value); |
adcec288 TSD |
2822 | |
2823 | result += 4; | |
2824 | buf += 4; | |
2825 | *pos += 4; | |
2826 | size -= 4; | |
2827 | } | |
2828 | ||
2829 | return result; | |
2830 | } | |
2831 | ||
1e051413 TSD |
2832 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
2833 | size_t size, loff_t *pos) | |
2834 | { | |
2835 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2836 | ssize_t result = 0; | |
2837 | int r; | |
2838 | uint32_t *config, no_regs = 0; | |
2839 | ||
2840 | if (size & 0x3 || *pos & 0x3) | |
2841 | return -EINVAL; | |
2842 | ||
ecab7668 | 2843 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
2844 | if (!config) |
2845 | return -ENOMEM; | |
2846 | ||
2847 | /* version, increment each time something is added */ | |
e9f11dc8 | 2848 | config[no_regs++] = 2; |
1e051413 TSD |
2849 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
2850 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
2851 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
2852 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
2853 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
2854 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
2855 | config[no_regs++] = adev->gfx.config.max_gprs; | |
2856 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
2857 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
2858 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
2859 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
2860 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
2861 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
2862 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
2863 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
2864 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
2865 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
2866 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
2867 | config[no_regs++] = adev->gfx.config.num_gpus; | |
2868 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
2869 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
2870 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
2871 | config[no_regs++] = adev->gfx.config.num_rbs; | |
2872 | ||
89a8f309 TSD |
2873 | /* rev==1 */ |
2874 | config[no_regs++] = adev->rev_id; | |
2875 | config[no_regs++] = adev->pg_flags; | |
2876 | config[no_regs++] = adev->cg_flags; | |
2877 | ||
e9f11dc8 TSD |
2878 | /* rev==2 */ |
2879 | config[no_regs++] = adev->family; | |
2880 | config[no_regs++] = adev->external_rev_id; | |
2881 | ||
1e051413 TSD |
2882 | while (size && (*pos < no_regs * 4)) { |
2883 | uint32_t value; | |
2884 | ||
2885 | value = config[*pos >> 2]; | |
2886 | r = put_user(value, (uint32_t *)buf); | |
2887 | if (r) { | |
2888 | kfree(config); | |
2889 | return r; | |
2890 | } | |
2891 | ||
2892 | result += 4; | |
2893 | buf += 4; | |
2894 | *pos += 4; | |
2895 | size -= 4; | |
2896 | } | |
2897 | ||
2898 | kfree(config); | |
2899 | return result; | |
2900 | } | |
2901 | ||
f2cdaf20 TSD |
2902 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
2903 | size_t size, loff_t *pos) | |
2904 | { | |
2905 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2906 | int idx, r; | |
2907 | int32_t value; | |
2908 | ||
2909 | if (size != 4 || *pos & 0x3) | |
2910 | return -EINVAL; | |
2911 | ||
2912 | /* convert offset to sensor number */ | |
2913 | idx = *pos >> 2; | |
2914 | ||
2915 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) | |
2916 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value); | |
2917 | else | |
2918 | return -EINVAL; | |
2919 | ||
2920 | if (!r) | |
2921 | r = put_user(value, (int32_t *)buf); | |
2922 | ||
2923 | return !r ? 4 : r; | |
2924 | } | |
1e051413 | 2925 | |
273d7aa1 TSD |
2926 | static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t SQ_INDEX, uint32_t SQ_DATA, uint32_t simd, uint32_t wave, uint32_t address) |
2927 | { | |
2928 | WREG32(SQ_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); | |
2929 | return RREG32(SQ_DATA); | |
2930 | } | |
2931 | ||
2932 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, | |
2933 | size_t size, loff_t *pos) | |
2934 | { | |
2935 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2936 | int r, x; | |
2937 | ssize_t result=0; | |
2938 | uint32_t offset, se, sh, cu, wave, simd, data[16]; | |
2939 | ||
2940 | if (size & 3 || *pos & 3) | |
2941 | return -EINVAL; | |
2942 | ||
2943 | /* decode offset */ | |
2944 | offset = (*pos & 0x7F); | |
2945 | se = ((*pos >> 7) & 0xFF); | |
2946 | sh = ((*pos >> 15) & 0xFF); | |
2947 | cu = ((*pos >> 23) & 0xFF); | |
2948 | wave = ((*pos >> 31) & 0xFF); | |
2949 | simd = ((*pos >> 37) & 0xFF); | |
2950 | *pos &= 0x7F; | |
2951 | ||
2952 | /* switch to the specific se/sh/cu */ | |
2953 | mutex_lock(&adev->grbm_idx_mutex); | |
2954 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
2955 | ||
2956 | x = 0; | |
2957 | if (adev->family == AMDGPU_FAMILY_CZ || adev->family == AMDGPU_FAMILY_VI) { | |
2958 | /* type 0 wave data */ | |
2959 | data[x++] = 0; | |
2960 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x12); | |
2961 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x18); | |
2962 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x19); | |
2963 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27E); | |
2964 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27F); | |
2965 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x14); | |
2966 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1A); | |
2967 | data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1B); | |
273d7aa1 TSD |
2968 | } |
2969 | ||
2970 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
2971 | mutex_unlock(&adev->grbm_idx_mutex); | |
2972 | ||
5ecfb3b8 TSD |
2973 | if (!x) |
2974 | return -EINVAL; | |
2975 | ||
273d7aa1 TSD |
2976 | while (size && (*pos < x * 4)) { |
2977 | uint32_t value; | |
2978 | ||
2979 | value = data[*pos >> 2]; | |
2980 | r = put_user(value, (uint32_t *)buf); | |
2981 | if (r) | |
2982 | return r; | |
2983 | ||
2984 | result += 4; | |
2985 | buf += 4; | |
2986 | *pos += 4; | |
2987 | size -= 4; | |
2988 | } | |
2989 | ||
2990 | return result; | |
2991 | } | |
2992 | ||
d38ceaf9 AD |
2993 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
2994 | .owner = THIS_MODULE, | |
2995 | .read = amdgpu_debugfs_regs_read, | |
2996 | .write = amdgpu_debugfs_regs_write, | |
2997 | .llseek = default_llseek | |
2998 | }; | |
adcec288 TSD |
2999 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3000 | .owner = THIS_MODULE, | |
3001 | .read = amdgpu_debugfs_regs_didt_read, | |
3002 | .write = amdgpu_debugfs_regs_didt_write, | |
3003 | .llseek = default_llseek | |
3004 | }; | |
3005 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3006 | .owner = THIS_MODULE, | |
3007 | .read = amdgpu_debugfs_regs_pcie_read, | |
3008 | .write = amdgpu_debugfs_regs_pcie_write, | |
3009 | .llseek = default_llseek | |
3010 | }; | |
3011 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3012 | .owner = THIS_MODULE, | |
3013 | .read = amdgpu_debugfs_regs_smc_read, | |
3014 | .write = amdgpu_debugfs_regs_smc_write, | |
3015 | .llseek = default_llseek | |
3016 | }; | |
3017 | ||
1e051413 TSD |
3018 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3019 | .owner = THIS_MODULE, | |
3020 | .read = amdgpu_debugfs_gca_config_read, | |
3021 | .llseek = default_llseek | |
3022 | }; | |
3023 | ||
f2cdaf20 TSD |
3024 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3025 | .owner = THIS_MODULE, | |
3026 | .read = amdgpu_debugfs_sensor_read, | |
3027 | .llseek = default_llseek | |
3028 | }; | |
3029 | ||
273d7aa1 TSD |
3030 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3031 | .owner = THIS_MODULE, | |
3032 | .read = amdgpu_debugfs_wave_read, | |
3033 | .llseek = default_llseek | |
3034 | }; | |
3035 | ||
adcec288 TSD |
3036 | static const struct file_operations *debugfs_regs[] = { |
3037 | &amdgpu_debugfs_regs_fops, | |
3038 | &amdgpu_debugfs_regs_didt_fops, | |
3039 | &amdgpu_debugfs_regs_pcie_fops, | |
3040 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3041 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3042 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3043 | &amdgpu_debugfs_wave_fops, |
adcec288 TSD |
3044 | }; |
3045 | ||
3046 | static const char *debugfs_regs_names[] = { | |
3047 | "amdgpu_regs", | |
3048 | "amdgpu_regs_didt", | |
3049 | "amdgpu_regs_pcie", | |
3050 | "amdgpu_regs_smc", | |
1e051413 | 3051 | "amdgpu_gca_config", |
f2cdaf20 | 3052 | "amdgpu_sensors", |
273d7aa1 | 3053 | "amdgpu_wave", |
adcec288 | 3054 | }; |
d38ceaf9 AD |
3055 | |
3056 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3057 | { | |
3058 | struct drm_minor *minor = adev->ddev->primary; | |
3059 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3060 | unsigned i, j; |
3061 | ||
3062 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3063 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3064 | S_IFREG | S_IRUGO, root, | |
3065 | adev, debugfs_regs[i]); | |
3066 | if (IS_ERR(ent)) { | |
3067 | for (j = 0; j < i; j++) { | |
3068 | debugfs_remove(adev->debugfs_regs[i]); | |
3069 | adev->debugfs_regs[i] = NULL; | |
3070 | } | |
3071 | return PTR_ERR(ent); | |
3072 | } | |
d38ceaf9 | 3073 | |
adcec288 TSD |
3074 | if (!i) |
3075 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3076 | adev->debugfs_regs[i] = ent; | |
3077 | } | |
d38ceaf9 AD |
3078 | |
3079 | return 0; | |
3080 | } | |
3081 | ||
3082 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3083 | { | |
adcec288 TSD |
3084 | unsigned i; |
3085 | ||
3086 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3087 | if (adev->debugfs_regs[i]) { | |
3088 | debugfs_remove(adev->debugfs_regs[i]); | |
3089 | adev->debugfs_regs[i] = NULL; | |
3090 | } | |
3091 | } | |
d38ceaf9 AD |
3092 | } |
3093 | ||
3094 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
3095 | { | |
3096 | return 0; | |
3097 | } | |
3098 | ||
3099 | void amdgpu_debugfs_cleanup(struct drm_minor *minor) | |
3100 | { | |
3101 | } | |
7cebc728 AK |
3102 | #else |
3103 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3104 | { | |
3105 | return 0; | |
3106 | } | |
3107 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3108 | #endif |