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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc_helper.h> | |
4562236b | 33 | #include <drm/drm_atomic_helper.h> |
d38ceaf9 AD |
34 | #include <drm/amdgpu_drm.h> |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 43 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 44 | #include "amd_pcie.h" |
33f34802 KW |
45 | #ifdef CONFIG_DRM_AMDGPU_SI |
46 | #include "si.h" | |
47 | #endif | |
a2e73f56 AD |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK |
49 | #include "cik.h" | |
50 | #endif | |
aaa36a97 | 51 | #include "vi.h" |
460826e6 | 52 | #include "soc15.h" |
d38ceaf9 | 53 | #include "bif/bif_4_1_d.h" |
9accf2fd | 54 | #include <linux/pci.h> |
bec86378 | 55 | #include <linux/firmware.h> |
89041940 | 56 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 57 | |
ba997709 | 58 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 59 | #include "amdgpu_pm.h" |
d38ceaf9 | 60 | |
e2a75f88 | 61 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 62 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 63 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 64 | |
2dc80b00 S |
65 | #define AMDGPU_RESUME_MS 2000 |
66 | ||
d38ceaf9 | 67 | static const char *amdgpu_asic_name[] = { |
da69c161 KW |
68 | "TAHITI", |
69 | "PITCAIRN", | |
70 | "VERDE", | |
71 | "OLAND", | |
72 | "HAINAN", | |
d38ceaf9 AD |
73 | "BONAIRE", |
74 | "KAVERI", | |
75 | "KABINI", | |
76 | "HAWAII", | |
77 | "MULLINS", | |
78 | "TOPAZ", | |
79 | "TONGA", | |
48299f95 | 80 | "FIJI", |
d38ceaf9 | 81 | "CARRIZO", |
139f4917 | 82 | "STONEY", |
2cc0c0b5 FC |
83 | "POLARIS10", |
84 | "POLARIS11", | |
c4642a47 | 85 | "POLARIS12", |
d4196f01 | 86 | "VEGA10", |
8fab806a | 87 | "VEGA12", |
2ca8a5d2 | 88 | "RAVEN", |
d38ceaf9 AD |
89 | "LAST", |
90 | }; | |
91 | ||
5494d864 AD |
92 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
93 | ||
e3ecdffa AD |
94 | /** |
95 | * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control | |
96 | * | |
97 | * @dev: drm_device pointer | |
98 | * | |
99 | * Returns true if the device is a dGPU with HG/PX power control, | |
100 | * otherwise return false. | |
101 | */ | |
d38ceaf9 AD |
102 | bool amdgpu_device_is_px(struct drm_device *dev) |
103 | { | |
104 | struct amdgpu_device *adev = dev->dev_private; | |
105 | ||
2f7d10b3 | 106 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
107 | return true; |
108 | return false; | |
109 | } | |
110 | ||
111 | /* | |
112 | * MMIO register access helper functions. | |
113 | */ | |
e3ecdffa AD |
114 | /** |
115 | * amdgpu_mm_rreg - read a memory mapped IO register | |
116 | * | |
117 | * @adev: amdgpu_device pointer | |
118 | * @reg: dword aligned register offset | |
119 | * @acc_flags: access flags which require special behavior | |
120 | * | |
121 | * Returns the 32 bit value from the offset specified. | |
122 | */ | |
d38ceaf9 | 123 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
15d72fd7 | 124 | uint32_t acc_flags) |
d38ceaf9 | 125 | { |
f4b373f4 TSD |
126 | uint32_t ret; |
127 | ||
43ca8efa | 128 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 129 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 130 | |
15d72fd7 | 131 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 132 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
133 | else { |
134 | unsigned long flags; | |
d38ceaf9 AD |
135 | |
136 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
137 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
138 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
139 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 140 | } |
f4b373f4 TSD |
141 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
142 | return ret; | |
d38ceaf9 AD |
143 | } |
144 | ||
421a2a30 ML |
145 | /* |
146 | * MMIO register read with bytes helper functions | |
147 | * @offset:bytes offset from MMIO start | |
148 | * | |
149 | */ | |
150 | ||
e3ecdffa AD |
151 | /** |
152 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
153 | * | |
154 | * @adev: amdgpu_device pointer | |
155 | * @offset: byte aligned register offset | |
156 | * | |
157 | * Returns the 8 bit value from the offset specified. | |
158 | */ | |
421a2a30 ML |
159 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
160 | if (offset < adev->rmmio_size) | |
161 | return (readb(adev->rmmio + offset)); | |
162 | BUG(); | |
163 | } | |
164 | ||
165 | /* | |
166 | * MMIO register write with bytes helper functions | |
167 | * @offset:bytes offset from MMIO start | |
168 | * @value: the value want to be written to the register | |
169 | * | |
170 | */ | |
e3ecdffa AD |
171 | /** |
172 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
173 | * | |
174 | * @adev: amdgpu_device pointer | |
175 | * @offset: byte aligned register offset | |
176 | * @value: 8 bit value to write | |
177 | * | |
178 | * Writes the value specified to the offset specified. | |
179 | */ | |
421a2a30 ML |
180 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
181 | if (offset < adev->rmmio_size) | |
182 | writeb(value, adev->rmmio + offset); | |
183 | else | |
184 | BUG(); | |
185 | } | |
186 | ||
e3ecdffa AD |
187 | /** |
188 | * amdgpu_mm_wreg - write to a memory mapped IO register | |
189 | * | |
190 | * @adev: amdgpu_device pointer | |
191 | * @reg: dword aligned register offset | |
192 | * @v: 32 bit value to write to the register | |
193 | * @acc_flags: access flags which require special behavior | |
194 | * | |
195 | * Writes the value specified to the offset specified. | |
196 | */ | |
d38ceaf9 | 197 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 198 | uint32_t acc_flags) |
d38ceaf9 | 199 | { |
f4b373f4 | 200 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 201 | |
47ed4e1c KW |
202 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
203 | adev->last_mm_index = v; | |
204 | } | |
205 | ||
43ca8efa | 206 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 207 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 208 | |
15d72fd7 | 209 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
210 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
211 | else { | |
212 | unsigned long flags; | |
213 | ||
214 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
215 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
216 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
217 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
218 | } | |
47ed4e1c KW |
219 | |
220 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
221 | udelay(500); | |
222 | } | |
d38ceaf9 AD |
223 | } |
224 | ||
e3ecdffa AD |
225 | /** |
226 | * amdgpu_io_rreg - read an IO register | |
227 | * | |
228 | * @adev: amdgpu_device pointer | |
229 | * @reg: dword aligned register offset | |
230 | * | |
231 | * Returns the 32 bit value from the offset specified. | |
232 | */ | |
d38ceaf9 AD |
233 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
234 | { | |
235 | if ((reg * 4) < adev->rio_mem_size) | |
236 | return ioread32(adev->rio_mem + (reg * 4)); | |
237 | else { | |
238 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
239 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
240 | } | |
241 | } | |
242 | ||
e3ecdffa AD |
243 | /** |
244 | * amdgpu_io_wreg - write to an IO register | |
245 | * | |
246 | * @adev: amdgpu_device pointer | |
247 | * @reg: dword aligned register offset | |
248 | * @v: 32 bit value to write to the register | |
249 | * | |
250 | * Writes the value specified to the offset specified. | |
251 | */ | |
d38ceaf9 AD |
252 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
253 | { | |
47ed4e1c KW |
254 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
255 | adev->last_mm_index = v; | |
256 | } | |
d38ceaf9 AD |
257 | |
258 | if ((reg * 4) < adev->rio_mem_size) | |
259 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
260 | else { | |
261 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
262 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
263 | } | |
47ed4e1c KW |
264 | |
265 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
266 | udelay(500); | |
267 | } | |
d38ceaf9 AD |
268 | } |
269 | ||
270 | /** | |
271 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
272 | * | |
273 | * @adev: amdgpu_device pointer | |
274 | * @index: doorbell index | |
275 | * | |
276 | * Returns the value in the doorbell aperture at the | |
277 | * requested doorbell index (CIK). | |
278 | */ | |
279 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
280 | { | |
281 | if (index < adev->doorbell.num_doorbells) { | |
282 | return readl(adev->doorbell.ptr + index); | |
283 | } else { | |
284 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
285 | return 0; | |
286 | } | |
287 | } | |
288 | ||
289 | /** | |
290 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
291 | * | |
292 | * @adev: amdgpu_device pointer | |
293 | * @index: doorbell index | |
294 | * @v: value to write | |
295 | * | |
296 | * Writes @v to the doorbell aperture at the | |
297 | * requested doorbell index (CIK). | |
298 | */ | |
299 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
300 | { | |
301 | if (index < adev->doorbell.num_doorbells) { | |
302 | writel(v, adev->doorbell.ptr + index); | |
303 | } else { | |
304 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
305 | } | |
306 | } | |
307 | ||
832be404 KW |
308 | /** |
309 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
310 | * | |
311 | * @adev: amdgpu_device pointer | |
312 | * @index: doorbell index | |
313 | * | |
314 | * Returns the value in the doorbell aperture at the | |
315 | * requested doorbell index (VEGA10+). | |
316 | */ | |
317 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
318 | { | |
319 | if (index < adev->doorbell.num_doorbells) { | |
320 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
321 | } else { | |
322 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
323 | return 0; | |
324 | } | |
325 | } | |
326 | ||
327 | /** | |
328 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
329 | * | |
330 | * @adev: amdgpu_device pointer | |
331 | * @index: doorbell index | |
332 | * @v: value to write | |
333 | * | |
334 | * Writes @v to the doorbell aperture at the | |
335 | * requested doorbell index (VEGA10+). | |
336 | */ | |
337 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
338 | { | |
339 | if (index < adev->doorbell.num_doorbells) { | |
340 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
341 | } else { | |
342 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
343 | } | |
344 | } | |
345 | ||
d38ceaf9 AD |
346 | /** |
347 | * amdgpu_invalid_rreg - dummy reg read function | |
348 | * | |
349 | * @adev: amdgpu device pointer | |
350 | * @reg: offset of register | |
351 | * | |
352 | * Dummy register read function. Used for register blocks | |
353 | * that certain asics don't have (all asics). | |
354 | * Returns the value in the register. | |
355 | */ | |
356 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
357 | { | |
358 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
359 | BUG(); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | /** | |
364 | * amdgpu_invalid_wreg - dummy reg write function | |
365 | * | |
366 | * @adev: amdgpu device pointer | |
367 | * @reg: offset of register | |
368 | * @v: value to write to the register | |
369 | * | |
370 | * Dummy register read function. Used for register blocks | |
371 | * that certain asics don't have (all asics). | |
372 | */ | |
373 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
374 | { | |
375 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
376 | reg, v); | |
377 | BUG(); | |
378 | } | |
379 | ||
380 | /** | |
381 | * amdgpu_block_invalid_rreg - dummy reg read function | |
382 | * | |
383 | * @adev: amdgpu device pointer | |
384 | * @block: offset of instance | |
385 | * @reg: offset of register | |
386 | * | |
387 | * Dummy register read function. Used for register blocks | |
388 | * that certain asics don't have (all asics). | |
389 | * Returns the value in the register. | |
390 | */ | |
391 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
392 | uint32_t block, uint32_t reg) | |
393 | { | |
394 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
395 | reg, block); | |
396 | BUG(); | |
397 | return 0; | |
398 | } | |
399 | ||
400 | /** | |
401 | * amdgpu_block_invalid_wreg - dummy reg write function | |
402 | * | |
403 | * @adev: amdgpu device pointer | |
404 | * @block: offset of instance | |
405 | * @reg: offset of register | |
406 | * @v: value to write to the register | |
407 | * | |
408 | * Dummy register read function. Used for register blocks | |
409 | * that certain asics don't have (all asics). | |
410 | */ | |
411 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
412 | uint32_t block, | |
413 | uint32_t reg, uint32_t v) | |
414 | { | |
415 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
416 | reg, block, v); | |
417 | BUG(); | |
418 | } | |
419 | ||
e3ecdffa AD |
420 | /** |
421 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
422 | * | |
423 | * @adev: amdgpu device pointer | |
424 | * | |
425 | * Allocates a scratch page of VRAM for use by various things in the | |
426 | * driver. | |
427 | */ | |
06ec9070 | 428 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 429 | { |
a4a02777 CK |
430 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
431 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
432 | &adev->vram_scratch.robj, | |
433 | &adev->vram_scratch.gpu_addr, | |
434 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
435 | } |
436 | ||
e3ecdffa AD |
437 | /** |
438 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
439 | * | |
440 | * @adev: amdgpu device pointer | |
441 | * | |
442 | * Frees the VRAM scratch page. | |
443 | */ | |
06ec9070 | 444 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 445 | { |
078af1a3 | 446 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
447 | } |
448 | ||
449 | /** | |
9c3f2b54 | 450 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
451 | * |
452 | * @adev: amdgpu_device pointer | |
453 | * @registers: pointer to the register array | |
454 | * @array_size: size of the register array | |
455 | * | |
456 | * Programs an array or registers with and and or masks. | |
457 | * This is a helper for setting golden registers. | |
458 | */ | |
9c3f2b54 AD |
459 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
460 | const u32 *registers, | |
461 | const u32 array_size) | |
d38ceaf9 AD |
462 | { |
463 | u32 tmp, reg, and_mask, or_mask; | |
464 | int i; | |
465 | ||
466 | if (array_size % 3) | |
467 | return; | |
468 | ||
469 | for (i = 0; i < array_size; i +=3) { | |
470 | reg = registers[i + 0]; | |
471 | and_mask = registers[i + 1]; | |
472 | or_mask = registers[i + 2]; | |
473 | ||
474 | if (and_mask == 0xffffffff) { | |
475 | tmp = or_mask; | |
476 | } else { | |
477 | tmp = RREG32(reg); | |
478 | tmp &= ~and_mask; | |
479 | tmp |= or_mask; | |
480 | } | |
481 | WREG32(reg, tmp); | |
482 | } | |
483 | } | |
484 | ||
e3ecdffa AD |
485 | /** |
486 | * amdgpu_device_pci_config_reset - reset the GPU | |
487 | * | |
488 | * @adev: amdgpu_device pointer | |
489 | * | |
490 | * Resets the GPU using the pci config reset sequence. | |
491 | * Only applicable to asics prior to vega10. | |
492 | */ | |
8111c387 | 493 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
494 | { |
495 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
496 | } | |
497 | ||
498 | /* | |
499 | * GPU doorbell aperture helpers function. | |
500 | */ | |
501 | /** | |
06ec9070 | 502 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
503 | * |
504 | * @adev: amdgpu_device pointer | |
505 | * | |
506 | * Init doorbell driver information (CIK) | |
507 | * Returns 0 on success, error on failure. | |
508 | */ | |
06ec9070 | 509 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 510 | { |
705e519e CK |
511 | /* No doorbell on SI hardware generation */ |
512 | if (adev->asic_type < CHIP_BONAIRE) { | |
513 | adev->doorbell.base = 0; | |
514 | adev->doorbell.size = 0; | |
515 | adev->doorbell.num_doorbells = 0; | |
516 | adev->doorbell.ptr = NULL; | |
517 | return 0; | |
518 | } | |
519 | ||
d6895ad3 CK |
520 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
521 | return -EINVAL; | |
522 | ||
d38ceaf9 AD |
523 | /* doorbell bar mapping */ |
524 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
525 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
526 | ||
edf600da | 527 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
528 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
529 | if (adev->doorbell.num_doorbells == 0) | |
530 | return -EINVAL; | |
531 | ||
8972e5d2 CK |
532 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
533 | adev->doorbell.num_doorbells * | |
534 | sizeof(u32)); | |
535 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 536 | return -ENOMEM; |
d38ceaf9 AD |
537 | |
538 | return 0; | |
539 | } | |
540 | ||
541 | /** | |
06ec9070 | 542 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
543 | * |
544 | * @adev: amdgpu_device pointer | |
545 | * | |
546 | * Tear down doorbell driver information (CIK) | |
547 | */ | |
06ec9070 | 548 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
549 | { |
550 | iounmap(adev->doorbell.ptr); | |
551 | adev->doorbell.ptr = NULL; | |
552 | } | |
553 | ||
22cb0164 | 554 | |
d38ceaf9 AD |
555 | |
556 | /* | |
06ec9070 | 557 | * amdgpu_device_wb_*() |
455a7bc2 | 558 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 559 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
560 | */ |
561 | ||
562 | /** | |
06ec9070 | 563 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
564 | * |
565 | * @adev: amdgpu_device pointer | |
566 | * | |
567 | * Disables Writeback and frees the Writeback memory (all asics). | |
568 | * Used at driver shutdown. | |
569 | */ | |
06ec9070 | 570 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
571 | { |
572 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
573 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
574 | &adev->wb.gpu_addr, | |
575 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
576 | adev->wb.wb_obj = NULL; |
577 | } | |
578 | } | |
579 | ||
580 | /** | |
06ec9070 | 581 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
582 | * |
583 | * @adev: amdgpu_device pointer | |
584 | * | |
455a7bc2 | 585 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
586 | * Used at driver startup. |
587 | * Returns 0 on success or an -error on failure. | |
588 | */ | |
06ec9070 | 589 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
590 | { |
591 | int r; | |
592 | ||
593 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
594 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
595 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
596 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
597 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
598 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
599 | if (r) { |
600 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
601 | return r; | |
602 | } | |
d38ceaf9 AD |
603 | |
604 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
605 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
606 | ||
607 | /* clear wb memory */ | |
73469585 | 608 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
609 | } |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
614 | /** | |
131b4b36 | 615 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
616 | * |
617 | * @adev: amdgpu_device pointer | |
618 | * @wb: wb index | |
619 | * | |
620 | * Allocate a wb slot for use by the driver (all asics). | |
621 | * Returns 0 on success or -EINVAL on failure. | |
622 | */ | |
131b4b36 | 623 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
624 | { |
625 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 626 | |
97407b63 | 627 | if (offset < adev->wb.num_wb) { |
7014285a | 628 | __set_bit(offset, adev->wb.used); |
63ae07ca | 629 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
630 | return 0; |
631 | } else { | |
632 | return -EINVAL; | |
633 | } | |
634 | } | |
635 | ||
d38ceaf9 | 636 | /** |
131b4b36 | 637 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
638 | * |
639 | * @adev: amdgpu_device pointer | |
640 | * @wb: wb index | |
641 | * | |
642 | * Free a wb slot allocated for use by the driver (all asics) | |
643 | */ | |
131b4b36 | 644 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 645 | { |
73469585 | 646 | wb >>= 3; |
d38ceaf9 | 647 | if (wb < adev->wb.num_wb) |
73469585 | 648 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
649 | } |
650 | ||
651 | /** | |
2543e28a | 652 | * amdgpu_device_vram_location - try to find VRAM location |
e3ecdffa | 653 | * |
d38ceaf9 AD |
654 | * @adev: amdgpu device structure holding all necessary informations |
655 | * @mc: memory controller structure holding memory informations | |
656 | * @base: base address at which to put VRAM | |
657 | * | |
455a7bc2 | 658 | * Function will try to place VRAM at base address provided |
3d647c8f | 659 | * as parameter. |
d38ceaf9 | 660 | */ |
2543e28a | 661 | void amdgpu_device_vram_location(struct amdgpu_device *adev, |
770d13b1 | 662 | struct amdgpu_gmc *mc, u64 base) |
d38ceaf9 AD |
663 | { |
664 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
665 | ||
666 | mc->vram_start = base; | |
d38ceaf9 AD |
667 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
668 | if (limit && limit < mc->real_vram_size) | |
669 | mc->real_vram_size = limit; | |
670 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
671 | mc->mc_vram_size >> 20, mc->vram_start, | |
672 | mc->vram_end, mc->real_vram_size >> 20); | |
673 | } | |
674 | ||
675 | /** | |
2543e28a | 676 | * amdgpu_device_gart_location - try to find GTT location |
e3ecdffa | 677 | * |
d38ceaf9 AD |
678 | * @adev: amdgpu device structure holding all necessary informations |
679 | * @mc: memory controller structure holding memory informations | |
680 | * | |
681 | * Function will place try to place GTT before or after VRAM. | |
682 | * | |
683 | * If GTT size is bigger than space left then we ajust GTT size. | |
684 | * Thus function will never fails. | |
685 | * | |
686 | * FIXME: when reducing GTT size align new size on power of 2. | |
687 | */ | |
2543e28a | 688 | void amdgpu_device_gart_location(struct amdgpu_device *adev, |
770d13b1 | 689 | struct amdgpu_gmc *mc) |
d38ceaf9 AD |
690 | { |
691 | u64 size_af, size_bf; | |
692 | ||
770d13b1 | 693 | size_af = adev->gmc.mc_mask - mc->vram_end; |
ed21c047 | 694 | size_bf = mc->vram_start; |
d38ceaf9 | 695 | if (size_bf > size_af) { |
6f02a696 | 696 | if (mc->gart_size > size_bf) { |
d38ceaf9 | 697 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 698 | mc->gart_size = size_bf; |
d38ceaf9 | 699 | } |
6f02a696 | 700 | mc->gart_start = 0; |
d38ceaf9 | 701 | } else { |
6f02a696 | 702 | if (mc->gart_size > size_af) { |
d38ceaf9 | 703 | dev_warn(adev->dev, "limiting GTT\n"); |
6f02a696 | 704 | mc->gart_size = size_af; |
d38ceaf9 | 705 | } |
b98f1b9e CK |
706 | /* VCE doesn't like it when BOs cross a 4GB segment, so align |
707 | * the GART base on a 4GB boundary as well. | |
708 | */ | |
709 | mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL); | |
d38ceaf9 | 710 | } |
6f02a696 | 711 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
d38ceaf9 | 712 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 713 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
714 | } |
715 | ||
d6895ad3 CK |
716 | /** |
717 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
718 | * | |
719 | * @adev: amdgpu_device pointer | |
720 | * | |
721 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
722 | * to fail, but if any of the BARs is not accessible after the size we abort | |
723 | * driver loading by returning -ENODEV. | |
724 | */ | |
725 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
726 | { | |
770d13b1 | 727 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 728 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
729 | struct pci_bus *root; |
730 | struct resource *res; | |
731 | unsigned i; | |
d6895ad3 CK |
732 | u16 cmd; |
733 | int r; | |
734 | ||
0c03b912 | 735 | /* Bypass for VF */ |
736 | if (amdgpu_sriov_vf(adev)) | |
737 | return 0; | |
738 | ||
31b8adab CK |
739 | /* Check if the root BUS has 64bit memory resources */ |
740 | root = adev->pdev->bus; | |
741 | while (root->parent) | |
742 | root = root->parent; | |
743 | ||
744 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 745 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
746 | res->start > 0x100000000ull) |
747 | break; | |
748 | } | |
749 | ||
750 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
751 | if (!res) | |
752 | return 0; | |
753 | ||
d6895ad3 CK |
754 | /* Disable memory decoding while we change the BAR addresses and size */ |
755 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
756 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
757 | cmd & ~PCI_COMMAND_MEMORY); | |
758 | ||
759 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 760 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
761 | if (adev->asic_type >= CHIP_BONAIRE) |
762 | pci_release_resource(adev->pdev, 2); | |
763 | ||
764 | pci_release_resource(adev->pdev, 0); | |
765 | ||
766 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
767 | if (r == -ENOSPC) | |
768 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
769 | else if (r && r != -ENOTSUPP) | |
770 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
771 | ||
772 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
773 | ||
774 | /* When the doorbell or fb BAR isn't available we have no chance of | |
775 | * using the device. | |
776 | */ | |
06ec9070 | 777 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
778 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
779 | return -ENODEV; | |
780 | ||
781 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
782 | ||
783 | return 0; | |
784 | } | |
a05502e5 | 785 | |
d38ceaf9 AD |
786 | /* |
787 | * GPU helpers function. | |
788 | */ | |
789 | /** | |
39c640c0 | 790 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
791 | * |
792 | * @adev: amdgpu_device pointer | |
793 | * | |
c836fec5 JQ |
794 | * Check if the asic has been initialized (all asics) at driver startup |
795 | * or post is needed if hw reset is performed. | |
796 | * Returns true if need or false if not. | |
d38ceaf9 | 797 | */ |
39c640c0 | 798 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
799 | { |
800 | uint32_t reg; | |
801 | ||
bec86378 ML |
802 | if (amdgpu_sriov_vf(adev)) |
803 | return false; | |
804 | ||
805 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
806 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
807 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
808 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
809 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
810 | */ |
811 | if (adev->asic_type == CHIP_FIJI) { | |
812 | int err; | |
813 | uint32_t fw_ver; | |
814 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
815 | /* force vPost if error occured */ | |
816 | if (err) | |
817 | return true; | |
818 | ||
819 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
820 | if (fw_ver < 0x00160e00) |
821 | return true; | |
bec86378 | 822 | } |
bec86378 | 823 | } |
91fe77eb | 824 | |
825 | if (adev->has_hw_reset) { | |
826 | adev->has_hw_reset = false; | |
827 | return true; | |
828 | } | |
829 | ||
830 | /* bios scratch used on CIK+ */ | |
831 | if (adev->asic_type >= CHIP_BONAIRE) | |
832 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
833 | ||
834 | /* check MEM_SIZE for older asics */ | |
835 | reg = amdgpu_asic_get_config_memsize(adev); | |
836 | ||
837 | if ((reg != 0) && (reg != 0xffffffff)) | |
838 | return false; | |
839 | ||
840 | return true; | |
bec86378 ML |
841 | } |
842 | ||
d38ceaf9 AD |
843 | /* if we get transitioned to only one device, take VGA back */ |
844 | /** | |
06ec9070 | 845 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
846 | * |
847 | * @cookie: amdgpu_device pointer | |
848 | * @state: enable/disable vga decode | |
849 | * | |
850 | * Enable/disable vga decode (all asics). | |
851 | * Returns VGA resource flags. | |
852 | */ | |
06ec9070 | 853 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
854 | { |
855 | struct amdgpu_device *adev = cookie; | |
856 | amdgpu_asic_set_vga_state(adev, state); | |
857 | if (state) | |
858 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
859 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
860 | else | |
861 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
862 | } | |
863 | ||
e3ecdffa AD |
864 | /** |
865 | * amdgpu_device_check_block_size - validate the vm block size | |
866 | * | |
867 | * @adev: amdgpu_device pointer | |
868 | * | |
869 | * Validates the vm block size specified via module parameter. | |
870 | * The vm block size defines number of bits in page table versus page directory, | |
871 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
872 | * page table and the remaining bits are in the page directory. | |
873 | */ | |
06ec9070 | 874 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
875 | { |
876 | /* defines number of bits in page table versus page directory, | |
877 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
878 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
879 | if (amdgpu_vm_block_size == -1) |
880 | return; | |
a1adf8be | 881 | |
bab4fee7 | 882 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
883 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
884 | amdgpu_vm_block_size); | |
97489129 | 885 | amdgpu_vm_block_size = -1; |
a1adf8be | 886 | } |
a1adf8be CZ |
887 | } |
888 | ||
e3ecdffa AD |
889 | /** |
890 | * amdgpu_device_check_vm_size - validate the vm size | |
891 | * | |
892 | * @adev: amdgpu_device pointer | |
893 | * | |
894 | * Validates the vm size in GB specified via module parameter. | |
895 | * The VM size is the size of the GPU virtual memory space in GB. | |
896 | */ | |
06ec9070 | 897 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 898 | { |
64dab074 AD |
899 | /* no need to check the default value */ |
900 | if (amdgpu_vm_size == -1) | |
901 | return; | |
902 | ||
83ca145d ZJ |
903 | if (amdgpu_vm_size < 1) { |
904 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
905 | amdgpu_vm_size); | |
f3368128 | 906 | amdgpu_vm_size = -1; |
83ca145d | 907 | } |
83ca145d ZJ |
908 | } |
909 | ||
d38ceaf9 | 910 | /** |
06ec9070 | 911 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
912 | * |
913 | * @adev: amdgpu_device pointer | |
914 | * | |
915 | * Validates certain module parameters and updates | |
916 | * the associated values used by the driver (all asics). | |
917 | */ | |
06ec9070 | 918 | static void amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 919 | { |
5b011235 CZ |
920 | if (amdgpu_sched_jobs < 4) { |
921 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
922 | amdgpu_sched_jobs); | |
923 | amdgpu_sched_jobs = 4; | |
76117507 | 924 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
925 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
926 | amdgpu_sched_jobs); | |
927 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
928 | } | |
d38ceaf9 | 929 | |
83e74db6 | 930 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
931 | /* gart size must be greater or equal to 32M */ |
932 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
933 | amdgpu_gart_size); | |
83e74db6 | 934 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
935 | } |
936 | ||
36d38372 | 937 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 938 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
939 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
940 | amdgpu_gtt_size); | |
941 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
942 | } |
943 | ||
d07f14be RH |
944 | /* valid range is between 4 and 9 inclusive */ |
945 | if (amdgpu_vm_fragment_size != -1 && | |
946 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
947 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
948 | amdgpu_vm_fragment_size = -1; | |
949 | } | |
950 | ||
06ec9070 | 951 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 952 | |
06ec9070 | 953 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 954 | |
526bae37 | 955 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 956 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
957 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
958 | amdgpu_vram_page_split); | |
959 | amdgpu_vram_page_split = 1024; | |
960 | } | |
8854695a AG |
961 | |
962 | if (amdgpu_lockup_timeout == 0) { | |
963 | dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n"); | |
964 | amdgpu_lockup_timeout = 10000; | |
965 | } | |
19aede77 AD |
966 | |
967 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); | |
d38ceaf9 AD |
968 | } |
969 | ||
970 | /** | |
971 | * amdgpu_switcheroo_set_state - set switcheroo state | |
972 | * | |
973 | * @pdev: pci dev pointer | |
1694467b | 974 | * @state: vga_switcheroo state |
d38ceaf9 AD |
975 | * |
976 | * Callback for the switcheroo driver. Suspends or resumes the | |
977 | * the asics before or after it is powered up using ACPI methods. | |
978 | */ | |
979 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
980 | { | |
981 | struct drm_device *dev = pci_get_drvdata(pdev); | |
982 | ||
983 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
984 | return; | |
985 | ||
986 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 987 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
988 | /* don't suspend or resume card normally */ |
989 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
990 | ||
810ddc3a | 991 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 992 | |
d38ceaf9 AD |
993 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
994 | drm_kms_helper_poll_enable(dev); | |
995 | } else { | |
7ca85295 | 996 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
997 | drm_kms_helper_poll_disable(dev); |
998 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 999 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1000 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1001 | } | |
1002 | } | |
1003 | ||
1004 | /** | |
1005 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1006 | * | |
1007 | * @pdev: pci dev pointer | |
1008 | * | |
1009 | * Callback for the switcheroo driver. Check of the switcheroo | |
1010 | * state can be changed. | |
1011 | * Returns true if the state can be changed, false if not. | |
1012 | */ | |
1013 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1014 | { | |
1015 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1016 | ||
1017 | /* | |
1018 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1019 | * locking inversion with the driver load path. And the access here is | |
1020 | * completely racy anyway. So don't bother with locking for now. | |
1021 | */ | |
1022 | return dev->open_count == 0; | |
1023 | } | |
1024 | ||
1025 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1026 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1027 | .reprobe = NULL, | |
1028 | .can_switch = amdgpu_switcheroo_can_switch, | |
1029 | }; | |
1030 | ||
e3ecdffa AD |
1031 | /** |
1032 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1033 | * | |
1034 | * @adev: amdgpu_device pointer | |
1035 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1036 | * @state: clockgating state (gate or ungate) | |
1037 | * | |
1038 | * Sets the requested clockgating state for all instances of | |
1039 | * the hardware IP specified. | |
1040 | * Returns the error code from the last instance. | |
1041 | */ | |
43fa561f | 1042 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1043 | enum amd_ip_block_type block_type, |
1044 | enum amd_clockgating_state state) | |
d38ceaf9 | 1045 | { |
43fa561f | 1046 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1047 | int i, r = 0; |
1048 | ||
1049 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1050 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1051 | continue; |
c722865a RZ |
1052 | if (adev->ip_blocks[i].version->type != block_type) |
1053 | continue; | |
1054 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1055 | continue; | |
1056 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1057 | (void *)adev, state); | |
1058 | if (r) | |
1059 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1060 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1061 | } |
1062 | return r; | |
1063 | } | |
1064 | ||
e3ecdffa AD |
1065 | /** |
1066 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1067 | * | |
1068 | * @adev: amdgpu_device pointer | |
1069 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1070 | * @state: powergating state (gate or ungate) | |
1071 | * | |
1072 | * Sets the requested powergating state for all instances of | |
1073 | * the hardware IP specified. | |
1074 | * Returns the error code from the last instance. | |
1075 | */ | |
43fa561f | 1076 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1077 | enum amd_ip_block_type block_type, |
1078 | enum amd_powergating_state state) | |
d38ceaf9 | 1079 | { |
43fa561f | 1080 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1081 | int i, r = 0; |
1082 | ||
1083 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1084 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1085 | continue; |
c722865a RZ |
1086 | if (adev->ip_blocks[i].version->type != block_type) |
1087 | continue; | |
1088 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1089 | continue; | |
1090 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1091 | (void *)adev, state); | |
1092 | if (r) | |
1093 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1094 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1095 | } |
1096 | return r; | |
1097 | } | |
1098 | ||
e3ecdffa AD |
1099 | /** |
1100 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1101 | * | |
1102 | * @adev: amdgpu_device pointer | |
1103 | * @flags: clockgating feature flags | |
1104 | * | |
1105 | * Walks the list of IPs on the device and updates the clockgating | |
1106 | * flags for each IP. | |
1107 | * Updates @flags with the feature flags for each hardware IP where | |
1108 | * clockgating is enabled. | |
1109 | */ | |
2990a1fc AD |
1110 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1111 | u32 *flags) | |
6cb2d4e4 HR |
1112 | { |
1113 | int i; | |
1114 | ||
1115 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1116 | if (!adev->ip_blocks[i].status.valid) | |
1117 | continue; | |
1118 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1119 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1120 | } | |
1121 | } | |
1122 | ||
e3ecdffa AD |
1123 | /** |
1124 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1125 | * | |
1126 | * @adev: amdgpu_device pointer | |
1127 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1128 | * | |
1129 | * Waits for the request hardware IP to be idle. | |
1130 | * Returns 0 for success or a negative error code on failure. | |
1131 | */ | |
2990a1fc AD |
1132 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1133 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1134 | { |
1135 | int i, r; | |
1136 | ||
1137 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1138 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1139 | continue; |
a1255107 AD |
1140 | if (adev->ip_blocks[i].version->type == block_type) { |
1141 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1142 | if (r) |
1143 | return r; | |
1144 | break; | |
1145 | } | |
1146 | } | |
1147 | return 0; | |
1148 | ||
1149 | } | |
1150 | ||
e3ecdffa AD |
1151 | /** |
1152 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1153 | * | |
1154 | * @adev: amdgpu_device pointer | |
1155 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1156 | * | |
1157 | * Check if the hardware IP is idle or not. | |
1158 | * Returns true if it the IP is idle, false if not. | |
1159 | */ | |
2990a1fc AD |
1160 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1161 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1162 | { |
1163 | int i; | |
1164 | ||
1165 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1166 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1167 | continue; |
a1255107 AD |
1168 | if (adev->ip_blocks[i].version->type == block_type) |
1169 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1170 | } |
1171 | return true; | |
1172 | ||
1173 | } | |
1174 | ||
e3ecdffa AD |
1175 | /** |
1176 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1177 | * | |
1178 | * @adev: amdgpu_device pointer | |
1179 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1180 | * | |
1181 | * Returns a pointer to the hardware IP block structure | |
1182 | * if it exists for the asic, otherwise NULL. | |
1183 | */ | |
2990a1fc AD |
1184 | struct amdgpu_ip_block * |
1185 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1186 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1187 | { |
1188 | int i; | |
1189 | ||
1190 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1191 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1192 | return &adev->ip_blocks[i]; |
1193 | ||
1194 | return NULL; | |
1195 | } | |
1196 | ||
1197 | /** | |
2990a1fc | 1198 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1199 | * |
1200 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1201 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1202 | * @major: major version |
1203 | * @minor: minor version | |
1204 | * | |
1205 | * return 0 if equal or greater | |
1206 | * return 1 if smaller or the ip_block doesn't exist | |
1207 | */ | |
2990a1fc AD |
1208 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1209 | enum amd_ip_block_type type, | |
1210 | u32 major, u32 minor) | |
d38ceaf9 | 1211 | { |
2990a1fc | 1212 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1213 | |
a1255107 AD |
1214 | if (ip_block && ((ip_block->version->major > major) || |
1215 | ((ip_block->version->major == major) && | |
1216 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1217 | return 0; |
1218 | ||
1219 | return 1; | |
1220 | } | |
1221 | ||
a1255107 | 1222 | /** |
2990a1fc | 1223 | * amdgpu_device_ip_block_add |
a1255107 AD |
1224 | * |
1225 | * @adev: amdgpu_device pointer | |
1226 | * @ip_block_version: pointer to the IP to add | |
1227 | * | |
1228 | * Adds the IP block driver information to the collection of IPs | |
1229 | * on the asic. | |
1230 | */ | |
2990a1fc AD |
1231 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1232 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1233 | { |
1234 | if (!ip_block_version) | |
1235 | return -EINVAL; | |
1236 | ||
e966a725 | 1237 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1238 | ip_block_version->funcs->name); |
1239 | ||
a1255107 AD |
1240 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
e3ecdffa AD |
1245 | /** |
1246 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1247 | * | |
1248 | * @adev: amdgpu_device pointer | |
1249 | * | |
1250 | * Enabled the virtual display feature if the user has enabled it via | |
1251 | * the module parameter virtual_display. This feature provides a virtual | |
1252 | * display hardware on headless boards or in virtualized environments. | |
1253 | * This function parses and validates the configuration string specified by | |
1254 | * the user and configues the virtual display configuration (number of | |
1255 | * virtual connectors, crtcs, etc.) specified. | |
1256 | */ | |
483ef985 | 1257 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1258 | { |
1259 | adev->enable_virtual_display = false; | |
1260 | ||
1261 | if (amdgpu_virtual_display) { | |
1262 | struct drm_device *ddev = adev->ddev; | |
1263 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1264 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1265 | |
1266 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1267 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1268 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1269 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1270 | if (!strcmp("all", pciaddname) |
1271 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1272 | long num_crtc; |
1273 | int res = -1; | |
1274 | ||
9accf2fd | 1275 | adev->enable_virtual_display = true; |
0f66356d ED |
1276 | |
1277 | if (pciaddname_tmp) | |
1278 | res = kstrtol(pciaddname_tmp, 10, | |
1279 | &num_crtc); | |
1280 | ||
1281 | if (!res) { | |
1282 | if (num_crtc < 1) | |
1283 | num_crtc = 1; | |
1284 | if (num_crtc > 6) | |
1285 | num_crtc = 6; | |
1286 | adev->mode_info.num_crtc = num_crtc; | |
1287 | } else { | |
1288 | adev->mode_info.num_crtc = 1; | |
1289 | } | |
9accf2fd ED |
1290 | break; |
1291 | } | |
1292 | } | |
1293 | ||
0f66356d ED |
1294 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1295 | amdgpu_virtual_display, pci_address_name, | |
1296 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1297 | |
1298 | kfree(pciaddstr); | |
1299 | } | |
1300 | } | |
1301 | ||
e3ecdffa AD |
1302 | /** |
1303 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1304 | * | |
1305 | * @adev: amdgpu_device pointer | |
1306 | * | |
1307 | * Parses the asic configuration parameters specified in the gpu info | |
1308 | * firmware and makes them availale to the driver for use in configuring | |
1309 | * the asic. | |
1310 | * Returns 0 on success, -EINVAL on failure. | |
1311 | */ | |
e2a75f88 AD |
1312 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1313 | { | |
e2a75f88 AD |
1314 | const char *chip_name; |
1315 | char fw_name[30]; | |
1316 | int err; | |
1317 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1318 | ||
ab4fe3e1 HR |
1319 | adev->firmware.gpu_info_fw = NULL; |
1320 | ||
e2a75f88 AD |
1321 | switch (adev->asic_type) { |
1322 | case CHIP_TOPAZ: | |
1323 | case CHIP_TONGA: | |
1324 | case CHIP_FIJI: | |
1325 | case CHIP_POLARIS11: | |
1326 | case CHIP_POLARIS10: | |
1327 | case CHIP_POLARIS12: | |
1328 | case CHIP_CARRIZO: | |
1329 | case CHIP_STONEY: | |
1330 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1331 | case CHIP_VERDE: | |
1332 | case CHIP_TAHITI: | |
1333 | case CHIP_PITCAIRN: | |
1334 | case CHIP_OLAND: | |
1335 | case CHIP_HAINAN: | |
1336 | #endif | |
1337 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1338 | case CHIP_BONAIRE: | |
1339 | case CHIP_HAWAII: | |
1340 | case CHIP_KAVERI: | |
1341 | case CHIP_KABINI: | |
1342 | case CHIP_MULLINS: | |
1343 | #endif | |
1344 | default: | |
1345 | return 0; | |
1346 | case CHIP_VEGA10: | |
1347 | chip_name = "vega10"; | |
1348 | break; | |
3f76dced AD |
1349 | case CHIP_VEGA12: |
1350 | chip_name = "vega12"; | |
1351 | break; | |
2d2e5e7e AD |
1352 | case CHIP_RAVEN: |
1353 | chip_name = "raven"; | |
1354 | break; | |
e2a75f88 AD |
1355 | } |
1356 | ||
1357 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1358 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1359 | if (err) { |
1360 | dev_err(adev->dev, | |
1361 | "Failed to load gpu_info firmware \"%s\"\n", | |
1362 | fw_name); | |
1363 | goto out; | |
1364 | } | |
ab4fe3e1 | 1365 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1366 | if (err) { |
1367 | dev_err(adev->dev, | |
1368 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1369 | fw_name); | |
1370 | goto out; | |
1371 | } | |
1372 | ||
ab4fe3e1 | 1373 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1374 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1375 | ||
1376 | switch (hdr->version_major) { | |
1377 | case 1: | |
1378 | { | |
1379 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1380 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1381 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1382 | ||
b5ab16bf AD |
1383 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1384 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1385 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1386 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1387 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1388 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1389 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1390 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1391 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1392 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1393 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1394 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1395 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1396 | adev->gfx.cu_info.max_waves_per_simd = |
1397 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1398 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1399 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1400 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1401 | break; |
1402 | } | |
1403 | default: | |
1404 | dev_err(adev->dev, | |
1405 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1406 | err = -EINVAL; | |
1407 | goto out; | |
1408 | } | |
1409 | out: | |
e2a75f88 AD |
1410 | return err; |
1411 | } | |
1412 | ||
e3ecdffa AD |
1413 | /** |
1414 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1415 | * | |
1416 | * @adev: amdgpu_device pointer | |
1417 | * | |
1418 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1419 | * up each asic are discovered each IP's early_init callback is run. This | |
1420 | * is the first stage in initializing the asic. | |
1421 | * Returns 0 on success, negative error code on failure. | |
1422 | */ | |
06ec9070 | 1423 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1424 | { |
aaa36a97 | 1425 | int i, r; |
d38ceaf9 | 1426 | |
483ef985 | 1427 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1428 | |
d38ceaf9 | 1429 | switch (adev->asic_type) { |
aaa36a97 AD |
1430 | case CHIP_TOPAZ: |
1431 | case CHIP_TONGA: | |
48299f95 | 1432 | case CHIP_FIJI: |
2cc0c0b5 FC |
1433 | case CHIP_POLARIS11: |
1434 | case CHIP_POLARIS10: | |
c4642a47 | 1435 | case CHIP_POLARIS12: |
aaa36a97 | 1436 | case CHIP_CARRIZO: |
39bb0c92 SL |
1437 | case CHIP_STONEY: |
1438 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1439 | adev->family = AMDGPU_FAMILY_CZ; |
1440 | else | |
1441 | adev->family = AMDGPU_FAMILY_VI; | |
1442 | ||
1443 | r = vi_set_ip_blocks(adev); | |
1444 | if (r) | |
1445 | return r; | |
1446 | break; | |
33f34802 KW |
1447 | #ifdef CONFIG_DRM_AMDGPU_SI |
1448 | case CHIP_VERDE: | |
1449 | case CHIP_TAHITI: | |
1450 | case CHIP_PITCAIRN: | |
1451 | case CHIP_OLAND: | |
1452 | case CHIP_HAINAN: | |
295d0daf | 1453 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1454 | r = si_set_ip_blocks(adev); |
1455 | if (r) | |
1456 | return r; | |
1457 | break; | |
1458 | #endif | |
a2e73f56 AD |
1459 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1460 | case CHIP_BONAIRE: | |
1461 | case CHIP_HAWAII: | |
1462 | case CHIP_KAVERI: | |
1463 | case CHIP_KABINI: | |
1464 | case CHIP_MULLINS: | |
1465 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1466 | adev->family = AMDGPU_FAMILY_CI; | |
1467 | else | |
1468 | adev->family = AMDGPU_FAMILY_KV; | |
1469 | ||
1470 | r = cik_set_ip_blocks(adev); | |
1471 | if (r) | |
1472 | return r; | |
1473 | break; | |
1474 | #endif | |
e48a3cd9 AD |
1475 | case CHIP_VEGA10: |
1476 | case CHIP_VEGA12: | |
1477 | case CHIP_RAVEN: | |
2ca8a5d2 CZ |
1478 | if (adev->asic_type == CHIP_RAVEN) |
1479 | adev->family = AMDGPU_FAMILY_RV; | |
1480 | else | |
1481 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1482 | |
1483 | r = soc15_set_ip_blocks(adev); | |
1484 | if (r) | |
1485 | return r; | |
1486 | break; | |
d38ceaf9 AD |
1487 | default: |
1488 | /* FIXME: not supported yet */ | |
1489 | return -EINVAL; | |
1490 | } | |
1491 | ||
e2a75f88 AD |
1492 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1493 | if (r) | |
1494 | return r; | |
1495 | ||
1884734a | 1496 | amdgpu_amdkfd_device_probe(adev); |
1497 | ||
3149d9da XY |
1498 | if (amdgpu_sriov_vf(adev)) { |
1499 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1500 | if (r) | |
5ffa61c1 | 1501 | return -EAGAIN; |
3149d9da XY |
1502 | } |
1503 | ||
d38ceaf9 AD |
1504 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1505 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1506 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1507 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1508 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1509 | } else { |
a1255107 AD |
1510 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1511 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1512 | if (r == -ENOENT) { |
a1255107 | 1513 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1514 | } else if (r) { |
a1255107 AD |
1515 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1516 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1517 | return r; |
2c1a2784 | 1518 | } else { |
a1255107 | 1519 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1520 | } |
974e6b64 | 1521 | } else { |
a1255107 | 1522 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1523 | } |
d38ceaf9 AD |
1524 | } |
1525 | } | |
1526 | ||
395d1fb9 NH |
1527 | adev->cg_flags &= amdgpu_cg_mask; |
1528 | adev->pg_flags &= amdgpu_pg_mask; | |
1529 | ||
d38ceaf9 AD |
1530 | return 0; |
1531 | } | |
1532 | ||
e3ecdffa AD |
1533 | /** |
1534 | * amdgpu_device_ip_init - run init for hardware IPs | |
1535 | * | |
1536 | * @adev: amdgpu_device pointer | |
1537 | * | |
1538 | * Main initialization pass for hardware IPs. The list of all the hardware | |
1539 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
1540 | * are run. sw_init initializes the software state associated with each IP | |
1541 | * and hw_init initializes the hardware associated with each IP. | |
1542 | * Returns 0 on success, negative error code on failure. | |
1543 | */ | |
06ec9070 | 1544 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1545 | { |
1546 | int i, r; | |
1547 | ||
1548 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1549 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1550 | continue; |
a1255107 | 1551 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1552 | if (r) { |
a1255107 AD |
1553 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1554 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1555 | return r; |
2c1a2784 | 1556 | } |
a1255107 | 1557 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 1558 | |
d38ceaf9 | 1559 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1560 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 1561 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
1562 | if (r) { |
1563 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1564 | return r; |
2c1a2784 | 1565 | } |
a1255107 | 1566 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1567 | if (r) { |
1568 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1569 | return r; |
2c1a2784 | 1570 | } |
06ec9070 | 1571 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 1572 | if (r) { |
06ec9070 | 1573 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
d38ceaf9 | 1574 | return r; |
2c1a2784 | 1575 | } |
a1255107 | 1576 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1577 | |
1578 | /* right after GMC hw init, we create CSA */ | |
1579 | if (amdgpu_sriov_vf(adev)) { | |
1580 | r = amdgpu_allocate_static_csa(adev); | |
1581 | if (r) { | |
1582 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1583 | return r; | |
1584 | } | |
1585 | } | |
d38ceaf9 AD |
1586 | } |
1587 | } | |
1588 | ||
1589 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1590 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1591 | continue; |
bfca0289 | 1592 | if (adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1593 | continue; |
a1255107 | 1594 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1595 | if (r) { |
a1255107 AD |
1596 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1597 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1598 | return r; |
2c1a2784 | 1599 | } |
a1255107 | 1600 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1601 | } |
1602 | ||
1884734a | 1603 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1604 | |
1605 | if (amdgpu_sriov_vf(adev)) | |
1606 | amdgpu_virt_release_full_gpu(adev, true); | |
1607 | ||
d38ceaf9 AD |
1608 | return 0; |
1609 | } | |
1610 | ||
e3ecdffa AD |
1611 | /** |
1612 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
1613 | * | |
1614 | * @adev: amdgpu_device pointer | |
1615 | * | |
1616 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
1617 | * this function before a GPU reset. If the value is retained after a | |
1618 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
1619 | */ | |
06ec9070 | 1620 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1621 | { |
1622 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1623 | } | |
1624 | ||
e3ecdffa AD |
1625 | /** |
1626 | * amdgpu_device_check_vram_lost - check if vram is valid | |
1627 | * | |
1628 | * @adev: amdgpu_device pointer | |
1629 | * | |
1630 | * Checks the reset magic value written to the gart pointer in VRAM. | |
1631 | * The driver calls this after a GPU reset to see if the contents of | |
1632 | * VRAM is lost or now. | |
1633 | * returns true if vram is lost, false if not. | |
1634 | */ | |
06ec9070 | 1635 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1636 | { |
1637 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1638 | AMDGPU_RESET_MAGIC_NUM); | |
1639 | } | |
1640 | ||
e3ecdffa AD |
1641 | /** |
1642 | * amdgpu_device_ip_late_set_cg_state - late init for clockgating | |
1643 | * | |
1644 | * @adev: amdgpu_device pointer | |
1645 | * | |
1646 | * Late initialization pass enabling clockgating for hardware IPs. | |
1647 | * The list of all the hardware IPs that make up the asic is walked and the | |
1648 | * set_clockgating_state callbacks are run. This stage is run late | |
1649 | * in the init process. | |
1650 | * Returns 0 on success, negative error code on failure. | |
1651 | */ | |
06ec9070 | 1652 | static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) |
d38ceaf9 AD |
1653 | { |
1654 | int i = 0, r; | |
1655 | ||
4a2ba394 SL |
1656 | if (amdgpu_emu_mode == 1) |
1657 | return 0; | |
1658 | ||
2c773de2 S |
1659 | r = amdgpu_ib_ring_tests(adev); |
1660 | if (r) | |
1661 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1662 | ||
d38ceaf9 | 1663 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 1664 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1665 | continue; |
4a446d55 | 1666 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 1667 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 RZ |
1668 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
1669 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { | |
4a446d55 | 1670 | /* enable clockgating to save power */ |
a1255107 AD |
1671 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1672 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1673 | if (r) { |
1674 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1675 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1676 | return r; |
1677 | } | |
b0b00ff1 | 1678 | } |
d38ceaf9 | 1679 | } |
2dc80b00 S |
1680 | return 0; |
1681 | } | |
1682 | ||
e3ecdffa AD |
1683 | /** |
1684 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
1685 | * | |
1686 | * @adev: amdgpu_device pointer | |
1687 | * | |
1688 | * Late initialization pass for hardware IPs. The list of all the hardware | |
1689 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
1690 | * late_init covers any special initialization that an IP requires | |
1691 | * after all of the have been initialized or something that needs to happen | |
1692 | * late in the init process. | |
1693 | * Returns 0 on success, negative error code on failure. | |
1694 | */ | |
06ec9070 | 1695 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 S |
1696 | { |
1697 | int i = 0, r; | |
1698 | ||
1699 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1700 | if (!adev->ip_blocks[i].status.valid) | |
1701 | continue; | |
1702 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1703 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1704 | if (r) { | |
1705 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1706 | adev->ip_blocks[i].version->funcs->name, r); | |
1707 | return r; | |
1708 | } | |
1709 | adev->ip_blocks[i].status.late_initialized = true; | |
1710 | } | |
1711 | } | |
1712 | ||
2c773de2 S |
1713 | queue_delayed_work(system_wq, &adev->late_init_work, |
1714 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1715 | |
06ec9070 | 1716 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 AD |
1717 | |
1718 | return 0; | |
1719 | } | |
1720 | ||
e3ecdffa AD |
1721 | /** |
1722 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
1723 | * | |
1724 | * @adev: amdgpu_device pointer | |
1725 | * | |
1726 | * Main teardown pass for hardware IPs. The list of all the hardware | |
1727 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
1728 | * are run. hw_fini tears down the hardware associated with each IP | |
1729 | * and sw_fini tears down any software state associated with each IP. | |
1730 | * Returns 0 on success, negative error code on failure. | |
1731 | */ | |
06ec9070 | 1732 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1733 | { |
1734 | int i, r; | |
1735 | ||
1884734a | 1736 | amdgpu_amdkfd_device_fini(adev); |
3e96dbfd AD |
1737 | /* need to disable SMC first */ |
1738 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1739 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1740 | continue; |
57716327 RZ |
1741 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC && |
1742 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { | |
3e96dbfd | 1743 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1744 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1745 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1746 | if (r) { |
1747 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1748 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1749 | return r; |
1750 | } | |
a1255107 | 1751 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1752 | /* XXX handle errors */ |
1753 | if (r) { | |
1754 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1755 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1756 | } |
a1255107 | 1757 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1758 | break; |
1759 | } | |
1760 | } | |
1761 | ||
d38ceaf9 | 1762 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1763 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1764 | continue; |
8201a67a RZ |
1765 | |
1766 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
81ce8bea RZ |
1767 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
1768 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { | |
8201a67a RZ |
1769 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
1770 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1771 | AMD_CG_STATE_UNGATE); | |
1772 | if (r) { | |
1773 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1774 | adev->ip_blocks[i].version->funcs->name, r); | |
1775 | return r; | |
1776 | } | |
2c1a2784 | 1777 | } |
8201a67a | 1778 | |
a1255107 | 1779 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1780 | /* XXX handle errors */ |
2c1a2784 | 1781 | if (r) { |
a1255107 AD |
1782 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1783 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1784 | } |
8201a67a | 1785 | |
a1255107 | 1786 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1787 | } |
1788 | ||
9950cda2 | 1789 | |
d38ceaf9 | 1790 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1791 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1792 | continue; |
c12aba3a ML |
1793 | |
1794 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
1795 | amdgpu_free_static_csa(adev); | |
1796 | amdgpu_device_wb_fini(adev); | |
1797 | amdgpu_device_vram_scratch_fini(adev); | |
1798 | } | |
1799 | ||
a1255107 | 1800 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1801 | /* XXX handle errors */ |
2c1a2784 | 1802 | if (r) { |
a1255107 AD |
1803 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1804 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1805 | } |
a1255107 AD |
1806 | adev->ip_blocks[i].status.sw = false; |
1807 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1808 | } |
1809 | ||
a6dcfd9c | 1810 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1811 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1812 | continue; |
a1255107 AD |
1813 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1814 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1815 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1816 | } |
1817 | ||
030308fc | 1818 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
1819 | if (amdgpu_virt_release_full_gpu(adev, false)) |
1820 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 1821 | |
d38ceaf9 AD |
1822 | return 0; |
1823 | } | |
1824 | ||
e3ecdffa AD |
1825 | /** |
1826 | * amdgpu_device_ip_late_init_func_handler - work handler for clockgating | |
1827 | * | |
1828 | * @work: work_struct | |
1829 | * | |
1830 | * Work handler for amdgpu_device_ip_late_set_cg_state. We put the | |
1831 | * clockgating setup into a worker thread to speed up driver init and | |
1832 | * resume from suspend. | |
1833 | */ | |
06ec9070 | 1834 | static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) |
2dc80b00 S |
1835 | { |
1836 | struct amdgpu_device *adev = | |
1837 | container_of(work, struct amdgpu_device, late_init_work.work); | |
06ec9070 | 1838 | amdgpu_device_ip_late_set_cg_state(adev); |
2dc80b00 S |
1839 | } |
1840 | ||
e3ecdffa AD |
1841 | /** |
1842 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
1843 | * | |
1844 | * @adev: amdgpu_device pointer | |
1845 | * | |
1846 | * Main suspend function for hardware IPs. The list of all the hardware | |
1847 | * IPs that make up the asic is walked, clockgating is disabled and the | |
1848 | * suspend callbacks are run. suspend puts the hardware and software state | |
1849 | * in each IP into a state suitable for suspend. | |
1850 | * Returns 0 on success, negative error code on failure. | |
1851 | */ | |
cdd61df6 | 1852 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) |
d38ceaf9 AD |
1853 | { |
1854 | int i, r; | |
1855 | ||
e941ea99 XY |
1856 | if (amdgpu_sriov_vf(adev)) |
1857 | amdgpu_virt_request_full_gpu(adev, false); | |
1858 | ||
c5a93a28 | 1859 | /* ungate SMC block first */ |
2990a1fc AD |
1860 | r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, |
1861 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1862 | if (r) { |
2990a1fc | 1863 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r); |
c5a93a28 FC |
1864 | } |
1865 | ||
d38ceaf9 | 1866 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1867 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1868 | continue; |
1869 | /* ungate blocks so that suspend can properly shut them down */ | |
5b2a3d2c | 1870 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_SMC && |
57716327 | 1871 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
a1255107 AD |
1872 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1873 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1874 | if (r) { |
a1255107 AD |
1875 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1876 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1877 | } |
2c1a2784 | 1878 | } |
d38ceaf9 | 1879 | /* XXX handle errors */ |
a1255107 | 1880 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1881 | /* XXX handle errors */ |
2c1a2784 | 1882 | if (r) { |
a1255107 AD |
1883 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1884 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1885 | } |
d38ceaf9 AD |
1886 | } |
1887 | ||
e941ea99 XY |
1888 | if (amdgpu_sriov_vf(adev)) |
1889 | amdgpu_virt_release_full_gpu(adev, false); | |
1890 | ||
d38ceaf9 AD |
1891 | return 0; |
1892 | } | |
1893 | ||
06ec9070 | 1894 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1895 | { |
1896 | int i, r; | |
1897 | ||
2cb681b6 ML |
1898 | static enum amd_ip_block_type ip_order[] = { |
1899 | AMD_IP_BLOCK_TYPE_GMC, | |
1900 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
1901 | AMD_IP_BLOCK_TYPE_IH, |
1902 | }; | |
a90ad3c2 | 1903 | |
2cb681b6 ML |
1904 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1905 | int j; | |
1906 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1907 | |
2cb681b6 ML |
1908 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1909 | block = &adev->ip_blocks[j]; | |
1910 | ||
1911 | if (block->version->type != ip_order[i] || | |
1912 | !block->status.valid) | |
1913 | continue; | |
1914 | ||
1915 | r = block->version->funcs->hw_init(adev); | |
1916 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
c41d1cf6 ML |
1917 | if (r) |
1918 | return r; | |
a90ad3c2 ML |
1919 | } |
1920 | } | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | ||
06ec9070 | 1925 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
1926 | { |
1927 | int i, r; | |
1928 | ||
2cb681b6 ML |
1929 | static enum amd_ip_block_type ip_order[] = { |
1930 | AMD_IP_BLOCK_TYPE_SMC, | |
ef4c166d | 1931 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
1932 | AMD_IP_BLOCK_TYPE_DCE, |
1933 | AMD_IP_BLOCK_TYPE_GFX, | |
1934 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
1935 | AMD_IP_BLOCK_TYPE_UVD, |
1936 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 1937 | }; |
a90ad3c2 | 1938 | |
2cb681b6 ML |
1939 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
1940 | int j; | |
1941 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 1942 | |
2cb681b6 ML |
1943 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1944 | block = &adev->ip_blocks[j]; | |
1945 | ||
1946 | if (block->version->type != ip_order[i] || | |
1947 | !block->status.valid) | |
1948 | continue; | |
1949 | ||
1950 | r = block->version->funcs->hw_init(adev); | |
1951 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed"); | |
c41d1cf6 ML |
1952 | if (r) |
1953 | return r; | |
a90ad3c2 ML |
1954 | } |
1955 | } | |
1956 | ||
1957 | return 0; | |
1958 | } | |
1959 | ||
e3ecdffa AD |
1960 | /** |
1961 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
1962 | * | |
1963 | * @adev: amdgpu_device pointer | |
1964 | * | |
1965 | * First resume function for hardware IPs. The list of all the hardware | |
1966 | * IPs that make up the asic is walked and the resume callbacks are run for | |
1967 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
1968 | * after a suspend and updates the software state as necessary. This | |
1969 | * function is also used for restoring the GPU after a GPU reset. | |
1970 | * Returns 0 on success, negative error code on failure. | |
1971 | */ | |
06ec9070 | 1972 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
1973 | { |
1974 | int i, r; | |
1975 | ||
a90ad3c2 ML |
1976 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1977 | if (!adev->ip_blocks[i].status.valid) | |
1978 | continue; | |
a90ad3c2 | 1979 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
1980 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
1981 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
fcf0649f CZ |
1982 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
1983 | if (r) { | |
1984 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1985 | adev->ip_blocks[i].version->funcs->name, r); | |
1986 | return r; | |
1987 | } | |
a90ad3c2 ML |
1988 | } |
1989 | } | |
1990 | ||
1991 | return 0; | |
1992 | } | |
1993 | ||
e3ecdffa AD |
1994 | /** |
1995 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
1996 | * | |
1997 | * @adev: amdgpu_device pointer | |
1998 | * | |
1999 | * First resume function for hardware IPs. The list of all the hardware | |
2000 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2001 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2002 | * functional state after a suspend and updates the software state as | |
2003 | * necessary. This function is also used for restoring the GPU after a GPU | |
2004 | * reset. | |
2005 | * Returns 0 on success, negative error code on failure. | |
2006 | */ | |
06ec9070 | 2007 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2008 | { |
2009 | int i, r; | |
2010 | ||
2011 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2012 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2013 | continue; |
fcf0649f | 2014 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2015 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2016 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) | |
fcf0649f | 2017 | continue; |
a1255107 | 2018 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2019 | if (r) { |
a1255107 AD |
2020 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2021 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2022 | return r; |
2c1a2784 | 2023 | } |
d38ceaf9 AD |
2024 | } |
2025 | ||
2026 | return 0; | |
2027 | } | |
2028 | ||
e3ecdffa AD |
2029 | /** |
2030 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2031 | * | |
2032 | * @adev: amdgpu_device pointer | |
2033 | * | |
2034 | * Main resume function for hardware IPs. The hardware IPs | |
2035 | * are split into two resume functions because they are | |
2036 | * are also used in in recovering from a GPU reset and some additional | |
2037 | * steps need to be take between them. In this case (S3/S4) they are | |
2038 | * run sequentially. | |
2039 | * Returns 0 on success, negative error code on failure. | |
2040 | */ | |
06ec9070 | 2041 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2042 | { |
2043 | int r; | |
2044 | ||
06ec9070 | 2045 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2046 | if (r) |
2047 | return r; | |
06ec9070 | 2048 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2049 | |
2050 | return r; | |
2051 | } | |
2052 | ||
e3ecdffa AD |
2053 | /** |
2054 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2055 | * | |
2056 | * @adev: amdgpu_device pointer | |
2057 | * | |
2058 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2059 | */ | |
4e99a44e | 2060 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2061 | { |
6867e1b5 ML |
2062 | if (amdgpu_sriov_vf(adev)) { |
2063 | if (adev->is_atom_fw) { | |
2064 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2065 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2066 | } else { | |
2067 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2068 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2069 | } | |
2070 | ||
2071 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2072 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2073 | } |
048765ad AR |
2074 | } |
2075 | ||
e3ecdffa AD |
2076 | /** |
2077 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2078 | * | |
2079 | * @asic_type: AMD asic type | |
2080 | * | |
2081 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2082 | * returns true if DC has support, false if not. | |
2083 | */ | |
4562236b HW |
2084 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2085 | { | |
2086 | switch (asic_type) { | |
2087 | #if defined(CONFIG_DRM_AMD_DC) | |
2088 | case CHIP_BONAIRE: | |
2089 | case CHIP_HAWAII: | |
0d6fbccb | 2090 | case CHIP_KAVERI: |
367e6687 AD |
2091 | case CHIP_KABINI: |
2092 | case CHIP_MULLINS: | |
4562236b HW |
2093 | case CHIP_CARRIZO: |
2094 | case CHIP_STONEY: | |
2095 | case CHIP_POLARIS11: | |
2096 | case CHIP_POLARIS10: | |
2c8ad2d5 | 2097 | case CHIP_POLARIS12: |
4562236b HW |
2098 | case CHIP_TONGA: |
2099 | case CHIP_FIJI: | |
42f8ffa1 | 2100 | case CHIP_VEGA10: |
dca7b401 | 2101 | case CHIP_VEGA12: |
42f8ffa1 | 2102 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
fd187853 | 2103 | case CHIP_RAVEN: |
42f8ffa1 | 2104 | #endif |
fd187853 | 2105 | return amdgpu_dc != 0; |
4562236b HW |
2106 | #endif |
2107 | default: | |
2108 | return false; | |
2109 | } | |
2110 | } | |
2111 | ||
2112 | /** | |
2113 | * amdgpu_device_has_dc_support - check if dc is supported | |
2114 | * | |
2115 | * @adev: amdgpu_device_pointer | |
2116 | * | |
2117 | * Returns true for supported, false for not supported | |
2118 | */ | |
2119 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2120 | { | |
2555039d XY |
2121 | if (amdgpu_sriov_vf(adev)) |
2122 | return false; | |
2123 | ||
4562236b HW |
2124 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2125 | } | |
2126 | ||
d38ceaf9 AD |
2127 | /** |
2128 | * amdgpu_device_init - initialize the driver | |
2129 | * | |
2130 | * @adev: amdgpu_device pointer | |
2131 | * @pdev: drm dev pointer | |
2132 | * @pdev: pci dev pointer | |
2133 | * @flags: driver flags | |
2134 | * | |
2135 | * Initializes the driver info and hw (all asics). | |
2136 | * Returns 0 for success or an error on failure. | |
2137 | * Called at driver startup. | |
2138 | */ | |
2139 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2140 | struct drm_device *ddev, | |
2141 | struct pci_dev *pdev, | |
2142 | uint32_t flags) | |
2143 | { | |
2144 | int r, i; | |
2145 | bool runtime = false; | |
95844d20 | 2146 | u32 max_MBps; |
d38ceaf9 AD |
2147 | |
2148 | adev->shutdown = false; | |
2149 | adev->dev = &pdev->dev; | |
2150 | adev->ddev = ddev; | |
2151 | adev->pdev = pdev; | |
2152 | adev->flags = flags; | |
2f7d10b3 | 2153 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2154 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 SL |
2155 | if (amdgpu_emu_mode == 1) |
2156 | adev->usec_timeout *= 2; | |
770d13b1 | 2157 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2158 | adev->accel_working = false; |
2159 | adev->num_rings = 0; | |
2160 | adev->mman.buffer_funcs = NULL; | |
2161 | adev->mman.buffer_funcs_ring = NULL; | |
2162 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 2163 | adev->vm_manager.vm_pte_num_rings = 0; |
132f34e4 | 2164 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 2165 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2166 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2167 | |
2168 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2169 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2170 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2171 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2172 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2173 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2174 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2175 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2176 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2177 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2178 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2179 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2180 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2181 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2182 | ||
3e39ab90 AD |
2183 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2184 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2185 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2186 | |
2187 | /* mutex initialization are all done here so we | |
2188 | * can recall function without having locking issues */ | |
d38ceaf9 | 2189 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2190 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2191 | mutex_init(&adev->pm.mutex); |
2192 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2193 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2194 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d38ceaf9 | 2195 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2196 | mutex_init(&adev->mn_lock); |
e23b74aa | 2197 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 2198 | hash_init(adev->mn_hash); |
13a752e3 | 2199 | mutex_init(&adev->lock_reset); |
d38ceaf9 | 2200 | |
06ec9070 | 2201 | amdgpu_device_check_arguments(adev); |
d38ceaf9 | 2202 | |
d38ceaf9 AD |
2203 | spin_lock_init(&adev->mmio_idx_lock); |
2204 | spin_lock_init(&adev->smc_idx_lock); | |
2205 | spin_lock_init(&adev->pcie_idx_lock); | |
2206 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2207 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2208 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2209 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2210 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2211 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2212 | |
0c4e7fa5 CZ |
2213 | INIT_LIST_HEAD(&adev->shadow_list); |
2214 | mutex_init(&adev->shadow_list_lock); | |
2215 | ||
795f2813 AR |
2216 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2217 | spin_lock_init(&adev->ring_lru_list_lock); | |
2218 | ||
06ec9070 AD |
2219 | INIT_DELAYED_WORK(&adev->late_init_work, |
2220 | amdgpu_device_ip_late_init_func_handler); | |
2dc80b00 | 2221 | |
0fa49558 AX |
2222 | /* Registers mapping */ |
2223 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2224 | if (adev->asic_type >= CHIP_BONAIRE) { |
2225 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2226 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2227 | } else { | |
2228 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2229 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2230 | } | |
d38ceaf9 | 2231 | |
d38ceaf9 AD |
2232 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2233 | if (adev->rmmio == NULL) { | |
2234 | return -ENOMEM; | |
2235 | } | |
2236 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2237 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2238 | ||
705e519e | 2239 | /* doorbell bar mapping */ |
06ec9070 | 2240 | amdgpu_device_doorbell_init(adev); |
d38ceaf9 AD |
2241 | |
2242 | /* io port mapping */ | |
2243 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2244 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2245 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2246 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2247 | break; | |
2248 | } | |
2249 | } | |
2250 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2251 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 2252 | |
5494d864 AD |
2253 | amdgpu_device_get_pcie_info(adev); |
2254 | ||
d38ceaf9 | 2255 | /* early init functions */ |
06ec9070 | 2256 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
2257 | if (r) |
2258 | return r; | |
2259 | ||
2260 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2261 | /* this will fail for cards that aren't VGA class devices, just | |
2262 | * ignore it */ | |
06ec9070 | 2263 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 2264 | |
e9bef455 | 2265 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2266 | runtime = true; |
84c8b22e LW |
2267 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2268 | vga_switcheroo_register_client(adev->pdev, | |
2269 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2270 | if (runtime) |
2271 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2272 | ||
9475a943 SL |
2273 | if (amdgpu_emu_mode == 1) { |
2274 | /* post the asic on emulation mode */ | |
2275 | emu_soc_asic_init(adev); | |
bfca0289 | 2276 | goto fence_driver_init; |
9475a943 | 2277 | } |
bfca0289 | 2278 | |
d38ceaf9 | 2279 | /* Read BIOS */ |
83ba126a AD |
2280 | if (!amdgpu_get_bios(adev)) { |
2281 | r = -EINVAL; | |
2282 | goto failed; | |
2283 | } | |
f7e9e9fe | 2284 | |
d38ceaf9 | 2285 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2286 | if (r) { |
2287 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
e23b74aa | 2288 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2289 | goto failed; |
2c1a2784 | 2290 | } |
d38ceaf9 | 2291 | |
4e99a44e ML |
2292 | /* detect if we are with an SRIOV vbios */ |
2293 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2294 | |
d38ceaf9 | 2295 | /* Post card if necessary */ |
39c640c0 | 2296 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 2297 | if (!adev->bios) { |
bec86378 | 2298 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2299 | r = -EINVAL; |
2300 | goto failed; | |
d38ceaf9 | 2301 | } |
bec86378 | 2302 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2303 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2304 | if (r) { | |
2305 | dev_err(adev->dev, "gpu post error!\n"); | |
2306 | goto failed; | |
2307 | } | |
d38ceaf9 AD |
2308 | } |
2309 | ||
88b64e95 AD |
2310 | if (adev->is_atom_fw) { |
2311 | /* Initialize clocks */ | |
2312 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2313 | if (r) { | |
2314 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2315 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2316 | goto failed; |
2317 | } | |
2318 | } else { | |
a5bde2f9 AD |
2319 | /* Initialize clocks */ |
2320 | r = amdgpu_atombios_get_clock_info(adev); | |
2321 | if (r) { | |
2322 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2323 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2324 | goto failed; |
a5bde2f9 AD |
2325 | } |
2326 | /* init i2c buses */ | |
4562236b HW |
2327 | if (!amdgpu_device_has_dc_support(adev)) |
2328 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2329 | } |
d38ceaf9 | 2330 | |
bfca0289 | 2331 | fence_driver_init: |
d38ceaf9 AD |
2332 | /* Fence driver */ |
2333 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2334 | if (r) { |
2335 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2336 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2337 | goto failed; |
2c1a2784 | 2338 | } |
d38ceaf9 AD |
2339 | |
2340 | /* init the mode config */ | |
2341 | drm_mode_config_init(adev->ddev); | |
2342 | ||
06ec9070 | 2343 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 2344 | if (r) { |
8840a387 | 2345 | /* failed in exclusive mode due to timeout */ |
2346 | if (amdgpu_sriov_vf(adev) && | |
2347 | !amdgpu_sriov_runtime(adev) && | |
2348 | amdgpu_virt_mmio_blocked(adev) && | |
2349 | !amdgpu_virt_wait_reset(adev)) { | |
2350 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
2351 | /* Don't send request since VF is inactive. */ |
2352 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
2353 | adev->virt.ops = NULL; | |
8840a387 | 2354 | r = -EAGAIN; |
2355 | goto failed; | |
2356 | } | |
06ec9070 | 2357 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 2358 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
83ba126a | 2359 | goto failed; |
d38ceaf9 AD |
2360 | } |
2361 | ||
2362 | adev->accel_working = true; | |
2363 | ||
e59c0205 AX |
2364 | amdgpu_vm_check_compute_bug(adev); |
2365 | ||
95844d20 MO |
2366 | /* Initialize the buffer migration limit. */ |
2367 | if (amdgpu_moverate >= 0) | |
2368 | max_MBps = amdgpu_moverate; | |
2369 | else | |
2370 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2371 | /* Get a log2 for easy divisions. */ | |
2372 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2373 | ||
d38ceaf9 AD |
2374 | r = amdgpu_ib_pool_init(adev); |
2375 | if (r) { | |
2376 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
e23b74aa | 2377 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2378 | goto failed; |
d38ceaf9 AD |
2379 | } |
2380 | ||
2dc8f81e HC |
2381 | if (amdgpu_sriov_vf(adev)) |
2382 | amdgpu_virt_init_data_exchange(adev); | |
2383 | ||
9bc92b9c ML |
2384 | amdgpu_fbdev_init(adev); |
2385 | ||
d2f52ac8 RZ |
2386 | r = amdgpu_pm_sysfs_init(adev); |
2387 | if (r) | |
2388 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2389 | ||
75758255 | 2390 | r = amdgpu_debugfs_gem_init(adev); |
3f14e623 | 2391 | if (r) |
d38ceaf9 | 2392 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2393 | |
2394 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2395 | if (r) |
d38ceaf9 | 2396 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2397 | |
50ab2533 | 2398 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2399 | if (r) |
50ab2533 | 2400 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2401 | |
763efb6c | 2402 | r = amdgpu_debugfs_init(adev); |
db95e218 | 2403 | if (r) |
763efb6c | 2404 | DRM_ERROR("Creating debugfs files failed (%d).\n", r); |
db95e218 | 2405 | |
d38ceaf9 AD |
2406 | if ((amdgpu_testing & 1)) { |
2407 | if (adev->accel_working) | |
2408 | amdgpu_test_moves(adev); | |
2409 | else | |
2410 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2411 | } | |
d38ceaf9 AD |
2412 | if (amdgpu_benchmarking) { |
2413 | if (adev->accel_working) | |
2414 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2415 | else | |
2416 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2417 | } | |
2418 | ||
2419 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2420 | * explicit gating rather than handling it automatically. | |
2421 | */ | |
06ec9070 | 2422 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 2423 | if (r) { |
06ec9070 | 2424 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 2425 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2426 | goto failed; |
2c1a2784 | 2427 | } |
d38ceaf9 AD |
2428 | |
2429 | return 0; | |
83ba126a AD |
2430 | |
2431 | failed: | |
89041940 | 2432 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2433 | if (runtime) |
2434 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 2435 | |
83ba126a | 2436 | return r; |
d38ceaf9 AD |
2437 | } |
2438 | ||
d38ceaf9 AD |
2439 | /** |
2440 | * amdgpu_device_fini - tear down the driver | |
2441 | * | |
2442 | * @adev: amdgpu_device pointer | |
2443 | * | |
2444 | * Tear down the driver info (all asics). | |
2445 | * Called at driver shutdown. | |
2446 | */ | |
2447 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2448 | { | |
2449 | int r; | |
2450 | ||
2451 | DRM_INFO("amdgpu: finishing device.\n"); | |
2452 | adev->shutdown = true; | |
e5b03032 ML |
2453 | /* disable all interrupts */ |
2454 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
2455 | if (adev->mode_info.mode_config_initialized){ |
2456 | if (!amdgpu_device_has_dc_support(adev)) | |
2457 | drm_crtc_force_disable_all(adev->ddev); | |
2458 | else | |
2459 | drm_atomic_helper_shutdown(adev->ddev); | |
2460 | } | |
d38ceaf9 AD |
2461 | amdgpu_ib_pool_fini(adev); |
2462 | amdgpu_fence_driver_fini(adev); | |
58e955d9 | 2463 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2464 | amdgpu_fbdev_fini(adev); |
06ec9070 | 2465 | r = amdgpu_device_ip_fini(adev); |
ab4fe3e1 HR |
2466 | if (adev->firmware.gpu_info_fw) { |
2467 | release_firmware(adev->firmware.gpu_info_fw); | |
2468 | adev->firmware.gpu_info_fw = NULL; | |
2469 | } | |
d38ceaf9 | 2470 | adev->accel_working = false; |
2dc80b00 | 2471 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 | 2472 | /* free i2c buses */ |
4562236b HW |
2473 | if (!amdgpu_device_has_dc_support(adev)) |
2474 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
2475 | |
2476 | if (amdgpu_emu_mode != 1) | |
2477 | amdgpu_atombios_fini(adev); | |
2478 | ||
d38ceaf9 AD |
2479 | kfree(adev->bios); |
2480 | adev->bios = NULL; | |
84c8b22e LW |
2481 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2482 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2483 | if (adev->flags & AMD_IS_PX) |
2484 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2485 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2486 | if (adev->rio_mem) | |
2487 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2488 | adev->rio_mem = NULL; | |
2489 | iounmap(adev->rmmio); | |
2490 | adev->rmmio = NULL; | |
06ec9070 | 2491 | amdgpu_device_doorbell_fini(adev); |
d38ceaf9 | 2492 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2493 | } |
2494 | ||
2495 | ||
2496 | /* | |
2497 | * Suspend & resume. | |
2498 | */ | |
2499 | /** | |
810ddc3a | 2500 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
2501 | * |
2502 | * @pdev: drm dev pointer | |
2503 | * @state: suspend state | |
2504 | * | |
2505 | * Puts the hw in the suspend state (all asics). | |
2506 | * Returns 0 for success or an error on failure. | |
2507 | * Called at driver suspend. | |
2508 | */ | |
810ddc3a | 2509 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2510 | { |
2511 | struct amdgpu_device *adev; | |
2512 | struct drm_crtc *crtc; | |
2513 | struct drm_connector *connector; | |
5ceb54c6 | 2514 | int r; |
d38ceaf9 AD |
2515 | |
2516 | if (dev == NULL || dev->dev_private == NULL) { | |
2517 | return -ENODEV; | |
2518 | } | |
2519 | ||
2520 | adev = dev->dev_private; | |
2521 | ||
2522 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2523 | return 0; | |
2524 | ||
2525 | drm_kms_helper_poll_disable(dev); | |
2526 | ||
4562236b HW |
2527 | if (!amdgpu_device_has_dc_support(adev)) { |
2528 | /* turn off display hw */ | |
2529 | drm_modeset_lock_all(dev); | |
2530 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2531 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2532 | } | |
2533 | drm_modeset_unlock_all(dev); | |
d38ceaf9 AD |
2534 | } |
2535 | ||
ba997709 YZ |
2536 | amdgpu_amdkfd_suspend(adev); |
2537 | ||
756e6880 | 2538 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 2539 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 2540 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
e68d14dd | 2541 | struct drm_framebuffer *fb = crtc->primary->fb; |
d38ceaf9 AD |
2542 | struct amdgpu_bo *robj; |
2543 | ||
756e6880 AD |
2544 | if (amdgpu_crtc->cursor_bo) { |
2545 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2546 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2547 | if (r == 0) { |
2548 | amdgpu_bo_unpin(aobj); | |
2549 | amdgpu_bo_unreserve(aobj); | |
2550 | } | |
2551 | } | |
2552 | ||
e68d14dd | 2553 | if (fb == NULL || fb->obj[0] == NULL) { |
d38ceaf9 AD |
2554 | continue; |
2555 | } | |
e68d14dd | 2556 | robj = gem_to_amdgpu_bo(fb->obj[0]); |
d38ceaf9 AD |
2557 | /* don't unpin kernel fb objects */ |
2558 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
7a6901d7 | 2559 | r = amdgpu_bo_reserve(robj, true); |
d38ceaf9 AD |
2560 | if (r == 0) { |
2561 | amdgpu_bo_unpin(robj); | |
2562 | amdgpu_bo_unreserve(robj); | |
2563 | } | |
2564 | } | |
2565 | } | |
2566 | /* evict vram memory */ | |
2567 | amdgpu_bo_evict_vram(adev); | |
2568 | ||
5ceb54c6 | 2569 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 2570 | |
cdd61df6 | 2571 | r = amdgpu_device_ip_suspend(adev); |
d38ceaf9 | 2572 | |
a0a71e49 AD |
2573 | /* evict remaining vram memory |
2574 | * This second call to evict vram is to evict the gart page table | |
2575 | * using the CPU. | |
2576 | */ | |
d38ceaf9 AD |
2577 | amdgpu_bo_evict_vram(adev); |
2578 | ||
2579 | pci_save_state(dev->pdev); | |
2580 | if (suspend) { | |
2581 | /* Shut down the device */ | |
2582 | pci_disable_device(dev->pdev); | |
2583 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2584 | } else { |
2585 | r = amdgpu_asic_reset(adev); | |
2586 | if (r) | |
2587 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2588 | } |
2589 | ||
2590 | if (fbcon) { | |
2591 | console_lock(); | |
2592 | amdgpu_fbdev_set_suspend(adev, 1); | |
2593 | console_unlock(); | |
2594 | } | |
2595 | return 0; | |
2596 | } | |
2597 | ||
2598 | /** | |
810ddc3a | 2599 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2600 | * |
2601 | * @pdev: drm dev pointer | |
2602 | * | |
2603 | * Bring the hw back to operating state (all asics). | |
2604 | * Returns 0 for success or an error on failure. | |
2605 | * Called at driver resume. | |
2606 | */ | |
810ddc3a | 2607 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2608 | { |
2609 | struct drm_connector *connector; | |
2610 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2611 | struct drm_crtc *crtc; |
03161a6e | 2612 | int r = 0; |
d38ceaf9 AD |
2613 | |
2614 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2615 | return 0; | |
2616 | ||
74b0b157 | 2617 | if (fbcon) |
d38ceaf9 | 2618 | console_lock(); |
74b0b157 | 2619 | |
d38ceaf9 AD |
2620 | if (resume) { |
2621 | pci_set_power_state(dev->pdev, PCI_D0); | |
2622 | pci_restore_state(dev->pdev); | |
74b0b157 | 2623 | r = pci_enable_device(dev->pdev); |
03161a6e HR |
2624 | if (r) |
2625 | goto unlock; | |
d38ceaf9 AD |
2626 | } |
2627 | ||
2628 | /* post card */ | |
39c640c0 | 2629 | if (amdgpu_device_need_post(adev)) { |
74b0b157 | 2630 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2631 | if (r) | |
2632 | DRM_ERROR("amdgpu asic init failed\n"); | |
2633 | } | |
d38ceaf9 | 2634 | |
06ec9070 | 2635 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 2636 | if (r) { |
06ec9070 | 2637 | DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); |
03161a6e | 2638 | goto unlock; |
e6707218 | 2639 | } |
5ceb54c6 AD |
2640 | amdgpu_fence_driver_resume(adev); |
2641 | ||
d38ceaf9 | 2642 | |
06ec9070 | 2643 | r = amdgpu_device_ip_late_init(adev); |
03161a6e HR |
2644 | if (r) |
2645 | goto unlock; | |
d38ceaf9 | 2646 | |
756e6880 AD |
2647 | /* pin cursors */ |
2648 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2649 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2650 | ||
2651 | if (amdgpu_crtc->cursor_bo) { | |
2652 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
7a6901d7 | 2653 | r = amdgpu_bo_reserve(aobj, true); |
756e6880 AD |
2654 | if (r == 0) { |
2655 | r = amdgpu_bo_pin(aobj, | |
2656 | AMDGPU_GEM_DOMAIN_VRAM, | |
2657 | &amdgpu_crtc->cursor_addr); | |
2658 | if (r != 0) | |
2659 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2660 | amdgpu_bo_unreserve(aobj); | |
2661 | } | |
2662 | } | |
2663 | } | |
ba997709 YZ |
2664 | r = amdgpu_amdkfd_resume(adev); |
2665 | if (r) | |
2666 | return r; | |
756e6880 | 2667 | |
d38ceaf9 AD |
2668 | /* blat the mode back in */ |
2669 | if (fbcon) { | |
4562236b HW |
2670 | if (!amdgpu_device_has_dc_support(adev)) { |
2671 | /* pre DCE11 */ | |
2672 | drm_helper_resume_force_mode(dev); | |
2673 | ||
2674 | /* turn on display hw */ | |
2675 | drm_modeset_lock_all(dev); | |
2676 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2677 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2678 | } | |
2679 | drm_modeset_unlock_all(dev); | |
d38ceaf9 AD |
2680 | } |
2681 | } | |
2682 | ||
2683 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2684 | |
2685 | /* | |
2686 | * Most of the connector probing functions try to acquire runtime pm | |
2687 | * refs to ensure that the GPU is powered on when connector polling is | |
2688 | * performed. Since we're calling this from a runtime PM callback, | |
2689 | * trying to acquire rpm refs will cause us to deadlock. | |
2690 | * | |
2691 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2692 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2693 | */ | |
2694 | #ifdef CONFIG_PM | |
2695 | dev->dev->power.disable_depth++; | |
2696 | #endif | |
4562236b HW |
2697 | if (!amdgpu_device_has_dc_support(adev)) |
2698 | drm_helper_hpd_irq_event(dev); | |
2699 | else | |
2700 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
2701 | #ifdef CONFIG_PM |
2702 | dev->dev->power.disable_depth--; | |
2703 | #endif | |
d38ceaf9 | 2704 | |
03161a6e | 2705 | if (fbcon) |
d38ceaf9 | 2706 | amdgpu_fbdev_set_suspend(adev, 0); |
03161a6e HR |
2707 | |
2708 | unlock: | |
2709 | if (fbcon) | |
d38ceaf9 | 2710 | console_unlock(); |
d38ceaf9 | 2711 | |
03161a6e | 2712 | return r; |
d38ceaf9 AD |
2713 | } |
2714 | ||
e3ecdffa AD |
2715 | /** |
2716 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
2717 | * | |
2718 | * @adev: amdgpu_device pointer | |
2719 | * | |
2720 | * The list of all the hardware IPs that make up the asic is walked and | |
2721 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
2722 | * if the asic is still hung or not. | |
2723 | * Returns true if any of the IPs are still in a hung state, false if not. | |
2724 | */ | |
06ec9070 | 2725 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
2726 | { |
2727 | int i; | |
2728 | bool asic_hang = false; | |
2729 | ||
f993d628 ML |
2730 | if (amdgpu_sriov_vf(adev)) |
2731 | return true; | |
2732 | ||
8bc04c29 AD |
2733 | if (amdgpu_asic_need_full_reset(adev)) |
2734 | return true; | |
2735 | ||
63fbf42f | 2736 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2737 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2738 | continue; |
a1255107 AD |
2739 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2740 | adev->ip_blocks[i].status.hang = | |
2741 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2742 | if (adev->ip_blocks[i].status.hang) { | |
2743 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2744 | asic_hang = true; |
2745 | } | |
2746 | } | |
2747 | return asic_hang; | |
2748 | } | |
2749 | ||
e3ecdffa AD |
2750 | /** |
2751 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
2752 | * | |
2753 | * @adev: amdgpu_device pointer | |
2754 | * | |
2755 | * The list of all the hardware IPs that make up the asic is walked and the | |
2756 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
2757 | * handles any IP specific hardware or software state changes that are | |
2758 | * necessary for a soft reset to succeed. | |
2759 | * Returns 0 on success, negative error code on failure. | |
2760 | */ | |
06ec9070 | 2761 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2762 | { |
2763 | int i, r = 0; | |
2764 | ||
2765 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2766 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2767 | continue; |
a1255107 AD |
2768 | if (adev->ip_blocks[i].status.hang && |
2769 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2770 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2771 | if (r) |
2772 | return r; | |
2773 | } | |
2774 | } | |
2775 | ||
2776 | return 0; | |
2777 | } | |
2778 | ||
e3ecdffa AD |
2779 | /** |
2780 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
2781 | * | |
2782 | * @adev: amdgpu_device pointer | |
2783 | * | |
2784 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
2785 | * reset is necessary to recover. | |
2786 | * Returns true if a full asic reset is required, false if not. | |
2787 | */ | |
06ec9070 | 2788 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 2789 | { |
da146d3b AD |
2790 | int i; |
2791 | ||
8bc04c29 AD |
2792 | if (amdgpu_asic_need_full_reset(adev)) |
2793 | return true; | |
2794 | ||
da146d3b | 2795 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2796 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2797 | continue; |
a1255107 AD |
2798 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2799 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2800 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
2801 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
2802 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 2803 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
2804 | DRM_INFO("Some block need full reset!\n"); |
2805 | return true; | |
2806 | } | |
2807 | } | |
35d782fe CZ |
2808 | } |
2809 | return false; | |
2810 | } | |
2811 | ||
e3ecdffa AD |
2812 | /** |
2813 | * amdgpu_device_ip_soft_reset - do a soft reset | |
2814 | * | |
2815 | * @adev: amdgpu_device pointer | |
2816 | * | |
2817 | * The list of all the hardware IPs that make up the asic is walked and the | |
2818 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
2819 | * IP specific hardware or software state changes that are necessary to soft | |
2820 | * reset the IP. | |
2821 | * Returns 0 on success, negative error code on failure. | |
2822 | */ | |
06ec9070 | 2823 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2824 | { |
2825 | int i, r = 0; | |
2826 | ||
2827 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2828 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2829 | continue; |
a1255107 AD |
2830 | if (adev->ip_blocks[i].status.hang && |
2831 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2832 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2833 | if (r) |
2834 | return r; | |
2835 | } | |
2836 | } | |
2837 | ||
2838 | return 0; | |
2839 | } | |
2840 | ||
e3ecdffa AD |
2841 | /** |
2842 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
2843 | * | |
2844 | * @adev: amdgpu_device pointer | |
2845 | * | |
2846 | * The list of all the hardware IPs that make up the asic is walked and the | |
2847 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
2848 | * handles any IP specific hardware or software state changes that are | |
2849 | * necessary after the IP has been soft reset. | |
2850 | * Returns 0 on success, negative error code on failure. | |
2851 | */ | |
06ec9070 | 2852 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
2853 | { |
2854 | int i, r = 0; | |
2855 | ||
2856 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2857 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2858 | continue; |
a1255107 AD |
2859 | if (adev->ip_blocks[i].status.hang && |
2860 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2861 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2862 | if (r) |
2863 | return r; | |
2864 | } | |
2865 | ||
2866 | return 0; | |
2867 | } | |
2868 | ||
e3ecdffa AD |
2869 | /** |
2870 | * amdgpu_device_recover_vram_from_shadow - restore shadowed VRAM buffers | |
2871 | * | |
2872 | * @adev: amdgpu_device pointer | |
2873 | * @ring: amdgpu_ring for the engine handling the buffer operations | |
2874 | * @bo: amdgpu_bo buffer whose shadow is being restored | |
2875 | * @fence: dma_fence associated with the operation | |
2876 | * | |
2877 | * Restores the VRAM buffer contents from the shadow in GTT. Used to | |
2878 | * restore things like GPUVM page tables after a GPU reset where | |
2879 | * the contents of VRAM might be lost. | |
2880 | * Returns 0 on success, negative error code on failure. | |
2881 | */ | |
06ec9070 AD |
2882 | static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev, |
2883 | struct amdgpu_ring *ring, | |
2884 | struct amdgpu_bo *bo, | |
2885 | struct dma_fence **fence) | |
53cdccd5 CZ |
2886 | { |
2887 | uint32_t domain; | |
2888 | int r; | |
2889 | ||
23d2e504 RH |
2890 | if (!bo->shadow) |
2891 | return 0; | |
2892 | ||
1d284797 | 2893 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
2894 | if (r) |
2895 | return r; | |
2896 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2897 | /* if bo has been evicted, then no need to recover */ | |
2898 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
2899 | r = amdgpu_bo_validate(bo->shadow); |
2900 | if (r) { | |
2901 | DRM_ERROR("bo validate failed!\n"); | |
2902 | goto err; | |
2903 | } | |
2904 | ||
23d2e504 | 2905 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 2906 | NULL, fence, true); |
23d2e504 RH |
2907 | if (r) { |
2908 | DRM_ERROR("recover page table failed!\n"); | |
2909 | goto err; | |
2910 | } | |
2911 | } | |
53cdccd5 | 2912 | err: |
23d2e504 RH |
2913 | amdgpu_bo_unreserve(bo); |
2914 | return r; | |
53cdccd5 CZ |
2915 | } |
2916 | ||
e3ecdffa AD |
2917 | /** |
2918 | * amdgpu_device_handle_vram_lost - Handle the loss of VRAM contents | |
2919 | * | |
2920 | * @adev: amdgpu_device pointer | |
2921 | * | |
2922 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
2923 | * restore things like GPUVM page tables after a GPU reset where | |
2924 | * the contents of VRAM might be lost. | |
2925 | * Returns 0 on success, 1 on failure. | |
2926 | */ | |
c41d1cf6 ML |
2927 | static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev) |
2928 | { | |
2929 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2930 | struct amdgpu_bo *bo, *tmp; | |
2931 | struct dma_fence *fence = NULL, *next = NULL; | |
2932 | long r = 1; | |
2933 | int i = 0; | |
2934 | long tmo; | |
2935 | ||
2936 | if (amdgpu_sriov_runtime(adev)) | |
2937 | tmo = msecs_to_jiffies(amdgpu_lockup_timeout); | |
2938 | else | |
2939 | tmo = msecs_to_jiffies(100); | |
2940 | ||
2941 | DRM_INFO("recover vram bo from shadow start\n"); | |
2942 | mutex_lock(&adev->shadow_list_lock); | |
2943 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2944 | next = NULL; | |
2945 | amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next); | |
2946 | if (fence) { | |
2947 | r = dma_fence_wait_timeout(fence, false, tmo); | |
2948 | if (r == 0) | |
2949 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
2950 | else if (r < 0) | |
2951 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
2952 | if (r < 1) { | |
2953 | dma_fence_put(fence); | |
2954 | fence = next; | |
2955 | break; | |
2956 | } | |
2957 | i++; | |
2958 | } | |
2959 | ||
2960 | dma_fence_put(fence); | |
2961 | fence = next; | |
2962 | } | |
2963 | mutex_unlock(&adev->shadow_list_lock); | |
2964 | ||
2965 | if (fence) { | |
2966 | r = dma_fence_wait_timeout(fence, false, tmo); | |
2967 | if (r == 0) | |
2968 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
2969 | else if (r < 0) | |
2970 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
2971 | ||
2972 | } | |
2973 | dma_fence_put(fence); | |
2974 | ||
2975 | if (r > 0) | |
2976 | DRM_INFO("recover vram bo from shadow done\n"); | |
2977 | else | |
2978 | DRM_ERROR("recover vram bo from shadow failed\n"); | |
2979 | ||
e3ecdffa | 2980 | return (r > 0) ? 0 : 1; |
c41d1cf6 ML |
2981 | } |
2982 | ||
e3ecdffa | 2983 | /** |
06ec9070 | 2984 | * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough |
a90ad3c2 ML |
2985 | * |
2986 | * @adev: amdgpu device pointer | |
a90ad3c2 | 2987 | * |
5740682e ML |
2988 | * attempt to do soft-reset or full-reset and reinitialize Asic |
2989 | * return 0 means successed otherwise failed | |
e3ecdffa | 2990 | */ |
c41d1cf6 | 2991 | static int amdgpu_device_reset(struct amdgpu_device *adev) |
a90ad3c2 | 2992 | { |
5740682e ML |
2993 | bool need_full_reset, vram_lost = 0; |
2994 | int r; | |
a90ad3c2 | 2995 | |
06ec9070 | 2996 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); |
a90ad3c2 | 2997 | |
5740682e | 2998 | if (!need_full_reset) { |
06ec9070 AD |
2999 | amdgpu_device_ip_pre_soft_reset(adev); |
3000 | r = amdgpu_device_ip_soft_reset(adev); | |
3001 | amdgpu_device_ip_post_soft_reset(adev); | |
3002 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
5740682e ML |
3003 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); |
3004 | need_full_reset = true; | |
3005 | } | |
5740682e | 3006 | } |
a90ad3c2 | 3007 | |
5740682e | 3008 | if (need_full_reset) { |
cdd61df6 | 3009 | r = amdgpu_device_ip_suspend(adev); |
a90ad3c2 | 3010 | |
5740682e | 3011 | retry: |
5740682e | 3012 | r = amdgpu_asic_reset(adev); |
5740682e ML |
3013 | /* post card */ |
3014 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
65781c78 | 3015 | |
5740682e ML |
3016 | if (!r) { |
3017 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
06ec9070 | 3018 | r = amdgpu_device_ip_resume_phase1(adev); |
5740682e ML |
3019 | if (r) |
3020 | goto out; | |
65781c78 | 3021 | |
06ec9070 | 3022 | vram_lost = amdgpu_device_check_vram_lost(adev); |
5740682e ML |
3023 | if (vram_lost) { |
3024 | DRM_ERROR("VRAM is lost!\n"); | |
3025 | atomic_inc(&adev->vram_lost_counter); | |
3026 | } | |
3027 | ||
c1c7ce8f CK |
3028 | r = amdgpu_gtt_mgr_recover( |
3029 | &adev->mman.bdev.man[TTM_PL_TT]); | |
5740682e ML |
3030 | if (r) |
3031 | goto out; | |
3032 | ||
06ec9070 | 3033 | r = amdgpu_device_ip_resume_phase2(adev); |
5740682e ML |
3034 | if (r) |
3035 | goto out; | |
3036 | ||
3037 | if (vram_lost) | |
06ec9070 | 3038 | amdgpu_device_fill_reset_magic(adev); |
65781c78 | 3039 | } |
5740682e | 3040 | } |
65781c78 | 3041 | |
5740682e ML |
3042 | out: |
3043 | if (!r) { | |
3044 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
3045 | r = amdgpu_ib_ring_tests(adev); | |
3046 | if (r) { | |
3047 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
cdd61df6 | 3048 | r = amdgpu_device_ip_suspend(adev); |
5740682e ML |
3049 | need_full_reset = true; |
3050 | goto retry; | |
3051 | } | |
3052 | } | |
65781c78 | 3053 | |
c41d1cf6 ML |
3054 | if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost)) |
3055 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 | 3056 | |
5740682e ML |
3057 | return r; |
3058 | } | |
a90ad3c2 | 3059 | |
e3ecdffa | 3060 | /** |
06ec9070 | 3061 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3062 | * |
3063 | * @adev: amdgpu device pointer | |
5740682e ML |
3064 | * |
3065 | * do VF FLR and reinitialize Asic | |
3066 | * return 0 means successed otherwise failed | |
e3ecdffa AD |
3067 | */ |
3068 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3069 | bool from_hypervisor) | |
5740682e ML |
3070 | { |
3071 | int r; | |
3072 | ||
3073 | if (from_hypervisor) | |
3074 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3075 | else | |
3076 | r = amdgpu_virt_reset_gpu(adev); | |
3077 | if (r) | |
3078 | return r; | |
a90ad3c2 ML |
3079 | |
3080 | /* Resume IP prior to SMC */ | |
06ec9070 | 3081 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3082 | if (r) |
3083 | goto error; | |
a90ad3c2 ML |
3084 | |
3085 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 3086 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 ML |
3087 | |
3088 | /* now we are okay to resume SMC/CP/SDMA */ | |
06ec9070 | 3089 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
c41d1cf6 | 3090 | amdgpu_virt_release_full_gpu(adev, true); |
5740682e ML |
3091 | if (r) |
3092 | goto error; | |
a90ad3c2 ML |
3093 | |
3094 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3095 | r = amdgpu_ib_ring_tests(adev); |
a90ad3c2 | 3096 | |
c41d1cf6 ML |
3097 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
3098 | atomic_inc(&adev->vram_lost_counter); | |
3099 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 ML |
3100 | } |
3101 | ||
c41d1cf6 ML |
3102 | error: |
3103 | ||
a90ad3c2 ML |
3104 | return r; |
3105 | } | |
3106 | ||
d38ceaf9 | 3107 | /** |
5f152b5e | 3108 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler |
d38ceaf9 AD |
3109 | * |
3110 | * @adev: amdgpu device pointer | |
5740682e | 3111 | * @job: which job trigger hang |
dcebf026 | 3112 | * @force forces reset regardless of amdgpu_gpu_recovery |
d38ceaf9 | 3113 | * |
5740682e | 3114 | * Attempt to reset the GPU if it has hung (all asics). |
d38ceaf9 AD |
3115 | * Returns 0 for success or an error on failure. |
3116 | */ | |
5f152b5e AD |
3117 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
3118 | struct amdgpu_job *job, bool force) | |
d38ceaf9 | 3119 | { |
4562236b | 3120 | struct drm_atomic_state *state = NULL; |
5740682e | 3121 | int i, r, resched; |
fb140b29 | 3122 | |
54bc1398 | 3123 | if (!force && !amdgpu_device_ip_check_soft_reset(adev)) { |
63fbf42f CZ |
3124 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); |
3125 | return 0; | |
3126 | } | |
d38ceaf9 | 3127 | |
dcebf026 AG |
3128 | if (!force && (amdgpu_gpu_recovery == 0 || |
3129 | (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) { | |
3130 | DRM_INFO("GPU recovery disabled.\n"); | |
3131 | return 0; | |
3132 | } | |
3133 | ||
5740682e ML |
3134 | dev_info(adev->dev, "GPU reset begin!\n"); |
3135 | ||
13a752e3 | 3136 | mutex_lock(&adev->lock_reset); |
d94aed5a | 3137 | atomic_inc(&adev->gpu_reset_counter); |
13a752e3 | 3138 | adev->in_gpu_reset = 1; |
d38ceaf9 | 3139 | |
a3c47d6b CZ |
3140 | /* block TTM */ |
3141 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
71182665 | 3142 | |
4562236b HW |
3143 | /* store modesetting */ |
3144 | if (amdgpu_device_has_dc_support(adev)) | |
3145 | state = drm_atomic_helper_suspend(adev->ddev); | |
a3c47d6b | 3146 | |
71182665 | 3147 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
3148 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3149 | struct amdgpu_ring *ring = adev->rings[i]; | |
3150 | ||
51687759 | 3151 | if (!ring || !ring->sched.thread) |
0875dc9e | 3152 | continue; |
5740682e | 3153 | |
71182665 ML |
3154 | kthread_park(ring->sched.thread); |
3155 | ||
5740682e ML |
3156 | if (job && job->ring->idx != i) |
3157 | continue; | |
3158 | ||
1b1f42d8 | 3159 | drm_sched_hw_job_reset(&ring->sched, &job->base); |
5740682e | 3160 | |
2f9d4084 ML |
3161 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
3162 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 3163 | } |
d38ceaf9 | 3164 | |
5740682e | 3165 | if (amdgpu_sriov_vf(adev)) |
c41d1cf6 | 3166 | r = amdgpu_device_reset_sriov(adev, job ? false : true); |
5740682e | 3167 | else |
c41d1cf6 | 3168 | r = amdgpu_device_reset(adev); |
5740682e | 3169 | |
71182665 ML |
3170 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3171 | struct amdgpu_ring *ring = adev->rings[i]; | |
53cdccd5 | 3172 | |
71182665 ML |
3173 | if (!ring || !ring->sched.thread) |
3174 | continue; | |
5740682e | 3175 | |
71182665 ML |
3176 | /* only need recovery sched of the given job's ring |
3177 | * or all rings (in the case @job is NULL) | |
3178 | * after above amdgpu_reset accomplished | |
3179 | */ | |
3180 | if ((!job || job->ring->idx == i) && !r) | |
1b1f42d8 | 3181 | drm_sched_job_recovery(&ring->sched); |
5740682e | 3182 | |
71182665 | 3183 | kthread_unpark(ring->sched.thread); |
d38ceaf9 AD |
3184 | } |
3185 | ||
4562236b | 3186 | if (amdgpu_device_has_dc_support(adev)) { |
5740682e ML |
3187 | if (drm_atomic_helper_resume(adev->ddev, state)) |
3188 | dev_info(adev->dev, "drm resume failed:%d\n", r); | |
5740682e | 3189 | } else { |
4562236b | 3190 | drm_helper_resume_force_mode(adev->ddev); |
5740682e | 3191 | } |
d38ceaf9 AD |
3192 | |
3193 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
5740682e | 3194 | |
89041940 | 3195 | if (r) { |
d38ceaf9 | 3196 | /* bad news, how to tell it to userspace ? */ |
5740682e ML |
3197 | dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); |
3198 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); | |
3199 | } else { | |
3200 | dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter)); | |
89041940 | 3201 | } |
d38ceaf9 | 3202 | |
89041940 | 3203 | amdgpu_vf_error_trans_all(adev); |
13a752e3 ML |
3204 | adev->in_gpu_reset = 0; |
3205 | mutex_unlock(&adev->lock_reset); | |
d38ceaf9 AD |
3206 | return r; |
3207 | } | |
3208 | ||
e3ecdffa AD |
3209 | /** |
3210 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
3211 | * | |
3212 | * @adev: amdgpu_device pointer | |
3213 | * | |
3214 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
3215 | * and lanes) of the slot the device is in. Handles APUs and | |
3216 | * virtualized environments where PCIE config space may not be available. | |
3217 | */ | |
5494d864 | 3218 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c AD |
3219 | { |
3220 | u32 mask; | |
3221 | int ret; | |
3222 | ||
cd474ba0 AD |
3223 | if (amdgpu_pcie_gen_cap) |
3224 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3225 | |
cd474ba0 AD |
3226 | if (amdgpu_pcie_lane_cap) |
3227 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3228 | |
cd474ba0 AD |
3229 | /* covers APUs as well */ |
3230 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3231 | if (adev->pm.pcie_gen_mask == 0) | |
3232 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3233 | if (adev->pm.pcie_mlw_mask == 0) | |
3234 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3235 | return; |
cd474ba0 | 3236 | } |
d0dd7f0c | 3237 | |
cd474ba0 AD |
3238 | if (adev->pm.pcie_gen_mask == 0) { |
3239 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
3240 | if (!ret) { | |
3241 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3242 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3243 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3244 | ||
3245 | if (mask & DRM_PCIE_SPEED_25) | |
3246 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3247 | if (mask & DRM_PCIE_SPEED_50) | |
3248 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
3249 | if (mask & DRM_PCIE_SPEED_80) | |
3250 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
3251 | } else { | |
3252 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3253 | } | |
3254 | } | |
3255 | if (adev->pm.pcie_mlw_mask == 0) { | |
3256 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
3257 | if (!ret) { | |
3258 | switch (mask) { | |
3259 | case 32: | |
3260 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
3261 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3262 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3263 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3264 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3265 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3266 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3267 | break; | |
3268 | case 16: | |
3269 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3270 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3271 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3272 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3273 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3274 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3275 | break; | |
3276 | case 12: | |
3277 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3278 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3279 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3280 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3281 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3282 | break; | |
3283 | case 8: | |
3284 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3285 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3286 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3287 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3288 | break; | |
3289 | case 4: | |
3290 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3291 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3292 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3293 | break; | |
3294 | case 2: | |
3295 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3296 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3297 | break; | |
3298 | case 1: | |
3299 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
3300 | break; | |
3301 | default: | |
3302 | break; | |
3303 | } | |
3304 | } else { | |
3305 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
3306 | } |
3307 | } | |
3308 | } | |
d38ceaf9 | 3309 |