Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
4a74c38c | 33 | #include <linux/iommu.h> |
901e2be2 | 34 | #include <linux/pci.h> |
3d8785f6 SA |
35 | #include <linux/devcoredump.h> |
36 | #include <generated/utsrelease.h> | |
08a2fd23 | 37 | #include <linux/pci-p2pdma.h> |
d37a3929 | 38 | #include <linux/apple-gmux.h> |
fdf2f6c5 | 39 | |
b7cdb41e | 40 | #include <drm/drm_aperture.h> |
4562236b | 41 | #include <drm/drm_atomic_helper.h> |
973ad627 | 42 | #include <drm/drm_crtc_helper.h> |
45b64fd9 | 43 | #include <drm/drm_fb_helper.h> |
fcd70cd3 | 44 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
45 | #include <drm/amdgpu_drm.h> |
46 | #include <linux/vgaarb.h> | |
47 | #include <linux/vga_switcheroo.h> | |
48 | #include <linux/efi.h> | |
49 | #include "amdgpu.h" | |
f4b373f4 | 50 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
51 | #include "amdgpu_i2c.h" |
52 | #include "atom.h" | |
53 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 54 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 55 | #include "amd_pcie.h" |
33f34802 KW |
56 | #ifdef CONFIG_DRM_AMDGPU_SI |
57 | #include "si.h" | |
58 | #endif | |
a2e73f56 AD |
59 | #ifdef CONFIG_DRM_AMDGPU_CIK |
60 | #include "cik.h" | |
61 | #endif | |
aaa36a97 | 62 | #include "vi.h" |
460826e6 | 63 | #include "soc15.h" |
0a5b8c7b | 64 | #include "nv.h" |
d38ceaf9 | 65 | #include "bif/bif_4_1_d.h" |
bec86378 | 66 | #include <linux/firmware.h> |
89041940 | 67 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 68 | |
ba997709 | 69 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 70 | #include "amdgpu_pm.h" |
d38ceaf9 | 71 | |
5183411b | 72 | #include "amdgpu_xgmi.h" |
c030f2e4 | 73 | #include "amdgpu_ras.h" |
9c7c85f7 | 74 | #include "amdgpu_pmu.h" |
bd607166 | 75 | #include "amdgpu_fru_eeprom.h" |
04442bf7 | 76 | #include "amdgpu_reset.h" |
5183411b | 77 | |
d5ea093e | 78 | #include <linux/suspend.h> |
c6a6e2db | 79 | #include <drm/task_barrier.h> |
3f12acc8 | 80 | #include <linux/pm_runtime.h> |
d5ea093e | 81 | |
f89f8c6b AG |
82 | #include <drm/drm_drv.h> |
83 | ||
3ad5dcfe KHF |
84 | #if IS_ENABLED(CONFIG_X86) |
85 | #include <asm/intel-family.h> | |
86 | #endif | |
87 | ||
e2a75f88 | 88 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 89 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 90 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 91 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 92 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 93 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
42b325e5 | 94 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
e2a75f88 | 95 | |
2dc80b00 | 96 | #define AMDGPU_RESUME_MS 2000 |
7258fa31 SK |
97 | #define AMDGPU_MAX_RETRY_LIMIT 2 |
98 | #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL) | |
2dc80b00 | 99 | |
b7cdb41e ML |
100 | static const struct drm_driver amdgpu_kms_driver; |
101 | ||
050091ab | 102 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
103 | "TAHITI", |
104 | "PITCAIRN", | |
105 | "VERDE", | |
106 | "OLAND", | |
107 | "HAINAN", | |
d38ceaf9 AD |
108 | "BONAIRE", |
109 | "KAVERI", | |
110 | "KABINI", | |
111 | "HAWAII", | |
112 | "MULLINS", | |
113 | "TOPAZ", | |
114 | "TONGA", | |
48299f95 | 115 | "FIJI", |
d38ceaf9 | 116 | "CARRIZO", |
139f4917 | 117 | "STONEY", |
2cc0c0b5 FC |
118 | "POLARIS10", |
119 | "POLARIS11", | |
c4642a47 | 120 | "POLARIS12", |
48ff108d | 121 | "VEGAM", |
d4196f01 | 122 | "VEGA10", |
8fab806a | 123 | "VEGA12", |
956fcddc | 124 | "VEGA20", |
2ca8a5d2 | 125 | "RAVEN", |
d6c3b24e | 126 | "ARCTURUS", |
1eee4228 | 127 | "RENOIR", |
d46b417a | 128 | "ALDEBARAN", |
852a6626 | 129 | "NAVI10", |
d0f56dc2 | 130 | "CYAN_SKILLFISH", |
87dbad02 | 131 | "NAVI14", |
9802f5d7 | 132 | "NAVI12", |
ccaf72d3 | 133 | "SIENNA_CICHLID", |
ddd8fbe7 | 134 | "NAVY_FLOUNDER", |
4f1e9a76 | 135 | "VANGOGH", |
a2468e04 | 136 | "DIMGREY_CAVEFISH", |
6f169591 | 137 | "BEIGE_GOBY", |
ee9236b7 | 138 | "YELLOW_CARP", |
3ae695d6 | 139 | "IP DISCOVERY", |
d38ceaf9 AD |
140 | "LAST", |
141 | }; | |
142 | ||
dcea6e65 KR |
143 | /** |
144 | * DOC: pcie_replay_count | |
145 | * | |
146 | * The amdgpu driver provides a sysfs API for reporting the total number | |
147 | * of PCIe replays (NAKs) | |
148 | * The file pcie_replay_count is used for this and returns the total | |
149 | * number of replays as a sum of the NAKs generated and NAKs received | |
150 | */ | |
151 | ||
152 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
153 | struct device_attribute *attr, char *buf) | |
154 | { | |
155 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 156 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
157 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
158 | ||
36000c7a | 159 | return sysfs_emit(buf, "%llu\n", cnt); |
dcea6e65 KR |
160 | } |
161 | ||
b8920e1e | 162 | static DEVICE_ATTR(pcie_replay_count, 0444, |
dcea6e65 KR |
163 | amdgpu_device_get_pcie_replay_count, NULL); |
164 | ||
5494d864 AD |
165 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
166 | ||
bd607166 | 167 | |
fd496ca8 | 168 | /** |
b98c6299 | 169 | * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control |
fd496ca8 AD |
170 | * |
171 | * @dev: drm_device pointer | |
172 | * | |
b98c6299 | 173 | * Returns true if the device is a dGPU with ATPX power control, |
fd496ca8 AD |
174 | * otherwise return false. |
175 | */ | |
b98c6299 | 176 | bool amdgpu_device_supports_px(struct drm_device *dev) |
fd496ca8 AD |
177 | { |
178 | struct amdgpu_device *adev = drm_to_adev(dev); | |
179 | ||
b98c6299 | 180 | if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid()) |
fd496ca8 AD |
181 | return true; |
182 | return false; | |
183 | } | |
184 | ||
e3ecdffa | 185 | /** |
0330b848 | 186 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
187 | * |
188 | * @dev: drm_device pointer | |
189 | * | |
b98c6299 | 190 | * Returns true if the device is a dGPU with ACPI power control, |
e3ecdffa AD |
191 | * otherwise return false. |
192 | */ | |
31af062a | 193 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 194 | { |
1348969a | 195 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 196 | |
b98c6299 AD |
197 | if (adev->has_pr3 || |
198 | ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid())) | |
d38ceaf9 AD |
199 | return true; |
200 | return false; | |
201 | } | |
202 | ||
a69cba42 AD |
203 | /** |
204 | * amdgpu_device_supports_baco - Does the device support BACO | |
205 | * | |
206 | * @dev: drm_device pointer | |
207 | * | |
208 | * Returns true if the device supporte BACO, | |
209 | * otherwise return false. | |
210 | */ | |
211 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
212 | { | |
1348969a | 213 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
214 | |
215 | return amdgpu_asic_supports_baco(adev); | |
216 | } | |
217 | ||
3fa8f89d S |
218 | /** |
219 | * amdgpu_device_supports_smart_shift - Is the device dGPU with | |
220 | * smart shift support | |
221 | * | |
222 | * @dev: drm_device pointer | |
223 | * | |
224 | * Returns true if the device is a dGPU with Smart Shift support, | |
225 | * otherwise returns false. | |
226 | */ | |
227 | bool amdgpu_device_supports_smart_shift(struct drm_device *dev) | |
228 | { | |
229 | return (amdgpu_device_supports_boco(dev) && | |
230 | amdgpu_acpi_is_power_shift_control_supported()); | |
231 | } | |
232 | ||
6e3cd2a9 MCC |
233 | /* |
234 | * VRAM access helper functions | |
235 | */ | |
236 | ||
e35e2b11 | 237 | /** |
048af66b | 238 | * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA |
e35e2b11 TY |
239 | * |
240 | * @adev: amdgpu_device pointer | |
241 | * @pos: offset of the buffer in vram | |
242 | * @buf: virtual address of the buffer in system memory | |
243 | * @size: read/write size, sizeof(@buf) must > @size | |
244 | * @write: true - write to vram, otherwise - read from vram | |
245 | */ | |
048af66b KW |
246 | void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, |
247 | void *buf, size_t size, bool write) | |
e35e2b11 | 248 | { |
e35e2b11 | 249 | unsigned long flags; |
048af66b KW |
250 | uint32_t hi = ~0, tmp = 0; |
251 | uint32_t *data = buf; | |
ce05ac56 | 252 | uint64_t last; |
f89f8c6b | 253 | int idx; |
ce05ac56 | 254 | |
c58a863b | 255 | if (!drm_dev_enter(adev_to_drm(adev), &idx)) |
f89f8c6b | 256 | return; |
9d11eb0d | 257 | |
048af66b KW |
258 | BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4)); |
259 | ||
260 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
261 | for (last = pos + size; pos < last; pos += 4) { | |
262 | tmp = pos >> 31; | |
263 | ||
264 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); | |
265 | if (tmp != hi) { | |
266 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
267 | hi = tmp; | |
268 | } | |
269 | if (write) | |
270 | WREG32_NO_KIQ(mmMM_DATA, *data++); | |
271 | else | |
272 | *data++ = RREG32_NO_KIQ(mmMM_DATA); | |
273 | } | |
274 | ||
275 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
276 | drm_dev_exit(idx); | |
277 | } | |
278 | ||
279 | /** | |
bbe04dec | 280 | * amdgpu_device_aper_access - access vram by vram aperature |
048af66b KW |
281 | * |
282 | * @adev: amdgpu_device pointer | |
283 | * @pos: offset of the buffer in vram | |
284 | * @buf: virtual address of the buffer in system memory | |
285 | * @size: read/write size, sizeof(@buf) must > @size | |
286 | * @write: true - write to vram, otherwise - read from vram | |
287 | * | |
288 | * The return value means how many bytes have been transferred. | |
289 | */ | |
290 | size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, | |
291 | void *buf, size_t size, bool write) | |
292 | { | |
9d11eb0d | 293 | #ifdef CONFIG_64BIT |
048af66b KW |
294 | void __iomem *addr; |
295 | size_t count = 0; | |
296 | uint64_t last; | |
297 | ||
298 | if (!adev->mman.aper_base_kaddr) | |
299 | return 0; | |
300 | ||
9d11eb0d CK |
301 | last = min(pos + size, adev->gmc.visible_vram_size); |
302 | if (last > pos) { | |
048af66b KW |
303 | addr = adev->mman.aper_base_kaddr + pos; |
304 | count = last - pos; | |
9d11eb0d CK |
305 | |
306 | if (write) { | |
307 | memcpy_toio(addr, buf, count); | |
4c452b5c SS |
308 | /* Make sure HDP write cache flush happens without any reordering |
309 | * after the system memory contents are sent over PCIe device | |
310 | */ | |
9d11eb0d | 311 | mb(); |
810085dd | 312 | amdgpu_device_flush_hdp(adev, NULL); |
9d11eb0d | 313 | } else { |
810085dd | 314 | amdgpu_device_invalidate_hdp(adev, NULL); |
4c452b5c SS |
315 | /* Make sure HDP read cache is invalidated before issuing a read |
316 | * to the PCIe device | |
317 | */ | |
9d11eb0d CK |
318 | mb(); |
319 | memcpy_fromio(buf, addr, count); | |
320 | } | |
321 | ||
9d11eb0d | 322 | } |
048af66b KW |
323 | |
324 | return count; | |
325 | #else | |
326 | return 0; | |
9d11eb0d | 327 | #endif |
048af66b | 328 | } |
9d11eb0d | 329 | |
048af66b KW |
330 | /** |
331 | * amdgpu_device_vram_access - read/write a buffer in vram | |
332 | * | |
333 | * @adev: amdgpu_device pointer | |
334 | * @pos: offset of the buffer in vram | |
335 | * @buf: virtual address of the buffer in system memory | |
336 | * @size: read/write size, sizeof(@buf) must > @size | |
337 | * @write: true - write to vram, otherwise - read from vram | |
338 | */ | |
339 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
340 | void *buf, size_t size, bool write) | |
341 | { | |
342 | size_t count; | |
e35e2b11 | 343 | |
048af66b KW |
344 | /* try to using vram apreature to access vram first */ |
345 | count = amdgpu_device_aper_access(adev, pos, buf, size, write); | |
346 | size -= count; | |
347 | if (size) { | |
348 | /* using MM to access rest vram */ | |
349 | pos += count; | |
350 | buf += count; | |
351 | amdgpu_device_mm_access(adev, pos, buf, size, write); | |
e35e2b11 TY |
352 | } |
353 | } | |
354 | ||
d38ceaf9 | 355 | /* |
f7ee1874 | 356 | * register access helper functions. |
d38ceaf9 | 357 | */ |
56b53c0b DL |
358 | |
359 | /* Check if hw access should be skipped because of hotplug or device error */ | |
360 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
361 | { | |
7afefb81 | 362 | if (adev->no_hw_access) |
56b53c0b DL |
363 | return true; |
364 | ||
365 | #ifdef CONFIG_LOCKDEP | |
366 | /* | |
367 | * This is a bit complicated to understand, so worth a comment. What we assert | |
368 | * here is that the GPU reset is not running on another thread in parallel. | |
369 | * | |
370 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
371 | * we know that the reset is not running in paralell. | |
372 | * | |
373 | * If the trylock fails we assert that we are either already holding the read | |
374 | * side of the lock or are the reset thread itself and hold the write side of | |
375 | * the lock. | |
376 | */ | |
377 | if (in_task()) { | |
d0fb18b5 AG |
378 | if (down_read_trylock(&adev->reset_domain->sem)) |
379 | up_read(&adev->reset_domain->sem); | |
56b53c0b | 380 | else |
d0fb18b5 | 381 | lockdep_assert_held(&adev->reset_domain->sem); |
56b53c0b DL |
382 | } |
383 | #endif | |
384 | return false; | |
385 | } | |
386 | ||
e3ecdffa | 387 | /** |
f7ee1874 | 388 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
389 | * |
390 | * @adev: amdgpu_device pointer | |
391 | * @reg: dword aligned register offset | |
392 | * @acc_flags: access flags which require special behavior | |
393 | * | |
394 | * Returns the 32 bit value from the offset specified. | |
395 | */ | |
f7ee1874 HZ |
396 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
397 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 398 | { |
f4b373f4 TSD |
399 | uint32_t ret; |
400 | ||
56b53c0b | 401 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
402 | return 0; |
403 | ||
f7ee1874 HZ |
404 | if ((reg * 4) < adev->rmmio_size) { |
405 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
406 | amdgpu_sriov_runtime(adev) && | |
d0fb18b5 | 407 | down_read_trylock(&adev->reset_domain->sem)) { |
f7ee1874 | 408 | ret = amdgpu_kiq_rreg(adev, reg); |
d0fb18b5 | 409 | up_read(&adev->reset_domain->sem); |
f7ee1874 HZ |
410 | } else { |
411 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
412 | } | |
413 | } else { | |
414 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 415 | } |
bc992ba5 | 416 | |
f7ee1874 | 417 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 418 | |
f4b373f4 | 419 | return ret; |
d38ceaf9 AD |
420 | } |
421 | ||
421a2a30 ML |
422 | /* |
423 | * MMIO register read with bytes helper functions | |
424 | * @offset:bytes offset from MMIO start | |
b8920e1e | 425 | */ |
421a2a30 | 426 | |
e3ecdffa AD |
427 | /** |
428 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
429 | * | |
430 | * @adev: amdgpu_device pointer | |
431 | * @offset: byte aligned register offset | |
432 | * | |
433 | * Returns the 8 bit value from the offset specified. | |
434 | */ | |
7cbbc745 AG |
435 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
436 | { | |
56b53c0b | 437 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
438 | return 0; |
439 | ||
421a2a30 ML |
440 | if (offset < adev->rmmio_size) |
441 | return (readb(adev->rmmio + offset)); | |
442 | BUG(); | |
443 | } | |
444 | ||
445 | /* | |
446 | * MMIO register write with bytes helper functions | |
447 | * @offset:bytes offset from MMIO start | |
448 | * @value: the value want to be written to the register | |
b8920e1e SS |
449 | */ |
450 | ||
e3ecdffa AD |
451 | /** |
452 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
453 | * | |
454 | * @adev: amdgpu_device pointer | |
455 | * @offset: byte aligned register offset | |
456 | * @value: 8 bit value to write | |
457 | * | |
458 | * Writes the value specified to the offset specified. | |
459 | */ | |
7cbbc745 AG |
460 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
461 | { | |
56b53c0b | 462 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
463 | return; |
464 | ||
421a2a30 ML |
465 | if (offset < adev->rmmio_size) |
466 | writeb(value, adev->rmmio + offset); | |
467 | else | |
468 | BUG(); | |
469 | } | |
470 | ||
e3ecdffa | 471 | /** |
f7ee1874 | 472 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
473 | * |
474 | * @adev: amdgpu_device pointer | |
475 | * @reg: dword aligned register offset | |
476 | * @v: 32 bit value to write to the register | |
477 | * @acc_flags: access flags which require special behavior | |
478 | * | |
479 | * Writes the value specified to the offset specified. | |
480 | */ | |
f7ee1874 HZ |
481 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
482 | uint32_t reg, uint32_t v, | |
483 | uint32_t acc_flags) | |
d38ceaf9 | 484 | { |
56b53c0b | 485 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
486 | return; |
487 | ||
f7ee1874 HZ |
488 | if ((reg * 4) < adev->rmmio_size) { |
489 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
490 | amdgpu_sriov_runtime(adev) && | |
d0fb18b5 | 491 | down_read_trylock(&adev->reset_domain->sem)) { |
f7ee1874 | 492 | amdgpu_kiq_wreg(adev, reg, v); |
d0fb18b5 | 493 | up_read(&adev->reset_domain->sem); |
f7ee1874 HZ |
494 | } else { |
495 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
496 | } | |
497 | } else { | |
498 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 499 | } |
bc992ba5 | 500 | |
f7ee1874 | 501 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 502 | } |
d38ceaf9 | 503 | |
03f2abb0 | 504 | /** |
4cc9f86f | 505 | * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range |
2e0cc4d4 | 506 | * |
71579346 RB |
507 | * @adev: amdgpu_device pointer |
508 | * @reg: mmio/rlc register | |
509 | * @v: value to write | |
8057a9d6 | 510 | * @xcc_id: xcc accelerated compute core id |
71579346 RB |
511 | * |
512 | * this function is invoked only for the debugfs register access | |
03f2abb0 | 513 | */ |
f7ee1874 | 514 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
8ed49dd1 VL |
515 | uint32_t reg, uint32_t v, |
516 | uint32_t xcc_id) | |
2e0cc4d4 | 517 | { |
56b53c0b | 518 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
519 | return; |
520 | ||
2e0cc4d4 | 521 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
522 | adev->gfx.rlc.funcs && |
523 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 | 524 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
8ed49dd1 | 525 | return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); |
4cc9f86f TSD |
526 | } else if ((reg * 4) >= adev->rmmio_size) { |
527 | adev->pcie_wreg(adev, reg * 4, v); | |
f7ee1874 HZ |
528 | } else { |
529 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 530 | } |
d38ceaf9 AD |
531 | } |
532 | ||
1bba3683 HZ |
533 | /** |
534 | * amdgpu_device_indirect_rreg - read an indirect register | |
535 | * | |
536 | * @adev: amdgpu_device pointer | |
22f453fb | 537 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
538 | * |
539 | * Returns the value of indirect register @reg_addr | |
540 | */ | |
541 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
1bba3683 HZ |
542 | u32 reg_addr) |
543 | { | |
65ba96e9 | 544 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
545 | void __iomem *pcie_index_offset; |
546 | void __iomem *pcie_data_offset; | |
65ba96e9 HZ |
547 | u32 r; |
548 | ||
549 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
550 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
1bba3683 HZ |
551 | |
552 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
553 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
554 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
555 | ||
556 | writel(reg_addr, pcie_index_offset); | |
557 | readl(pcie_index_offset); | |
558 | r = readl(pcie_data_offset); | |
559 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
560 | ||
561 | return r; | |
562 | } | |
563 | ||
0c552ed3 LM |
564 | u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, |
565 | u64 reg_addr) | |
566 | { | |
567 | unsigned long flags, pcie_index, pcie_index_hi, pcie_data; | |
568 | u32 r; | |
569 | void __iomem *pcie_index_offset; | |
570 | void __iomem *pcie_index_hi_offset; | |
571 | void __iomem *pcie_data_offset; | |
572 | ||
573 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
574 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
575 | if (adev->nbio.funcs->get_pcie_index_hi_offset) | |
576 | pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); | |
577 | else | |
578 | pcie_index_hi = 0; | |
579 | ||
580 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
581 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
582 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
583 | if (pcie_index_hi != 0) | |
584 | pcie_index_hi_offset = (void __iomem *)adev->rmmio + | |
585 | pcie_index_hi * 4; | |
586 | ||
587 | writel(reg_addr, pcie_index_offset); | |
588 | readl(pcie_index_offset); | |
589 | if (pcie_index_hi != 0) { | |
590 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
591 | readl(pcie_index_hi_offset); | |
592 | } | |
593 | r = readl(pcie_data_offset); | |
594 | ||
595 | /* clear the high bits */ | |
596 | if (pcie_index_hi != 0) { | |
597 | writel(0, pcie_index_hi_offset); | |
598 | readl(pcie_index_hi_offset); | |
599 | } | |
600 | ||
601 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
602 | ||
603 | return r; | |
604 | } | |
605 | ||
1bba3683 HZ |
606 | /** |
607 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
608 | * | |
609 | * @adev: amdgpu_device pointer | |
22f453fb | 610 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
611 | * |
612 | * Returns the value of indirect register @reg_addr | |
613 | */ | |
614 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
1bba3683 HZ |
615 | u32 reg_addr) |
616 | { | |
65ba96e9 | 617 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
618 | void __iomem *pcie_index_offset; |
619 | void __iomem *pcie_data_offset; | |
65ba96e9 HZ |
620 | u64 r; |
621 | ||
622 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
623 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
1bba3683 HZ |
624 | |
625 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
626 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
627 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
628 | ||
629 | /* read low 32 bits */ | |
630 | writel(reg_addr, pcie_index_offset); | |
631 | readl(pcie_index_offset); | |
632 | r = readl(pcie_data_offset); | |
633 | /* read high 32 bits */ | |
634 | writel(reg_addr + 4, pcie_index_offset); | |
635 | readl(pcie_index_offset); | |
636 | r |= ((u64)readl(pcie_data_offset) << 32); | |
637 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
638 | ||
639 | return r; | |
640 | } | |
641 | ||
642 | /** | |
643 | * amdgpu_device_indirect_wreg - write an indirect register address | |
644 | * | |
645 | * @adev: amdgpu_device pointer | |
1bba3683 HZ |
646 | * @reg_addr: indirect register offset |
647 | * @reg_data: indirect register data | |
648 | * | |
649 | */ | |
650 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
1bba3683 HZ |
651 | u32 reg_addr, u32 reg_data) |
652 | { | |
65ba96e9 | 653 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
654 | void __iomem *pcie_index_offset; |
655 | void __iomem *pcie_data_offset; | |
656 | ||
65ba96e9 HZ |
657 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); |
658 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
659 | ||
1bba3683 HZ |
660 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
661 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
662 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
663 | ||
664 | writel(reg_addr, pcie_index_offset); | |
665 | readl(pcie_index_offset); | |
666 | writel(reg_data, pcie_data_offset); | |
667 | readl(pcie_data_offset); | |
668 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
669 | } | |
670 | ||
0c552ed3 LM |
671 | void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, |
672 | u64 reg_addr, u32 reg_data) | |
673 | { | |
674 | unsigned long flags, pcie_index, pcie_index_hi, pcie_data; | |
675 | void __iomem *pcie_index_offset; | |
676 | void __iomem *pcie_index_hi_offset; | |
677 | void __iomem *pcie_data_offset; | |
678 | ||
679 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); | |
680 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
681 | if (adev->nbio.funcs->get_pcie_index_hi_offset) | |
682 | pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); | |
683 | else | |
684 | pcie_index_hi = 0; | |
685 | ||
686 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
687 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
688 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
689 | if (pcie_index_hi != 0) | |
690 | pcie_index_hi_offset = (void __iomem *)adev->rmmio + | |
691 | pcie_index_hi * 4; | |
692 | ||
693 | writel(reg_addr, pcie_index_offset); | |
694 | readl(pcie_index_offset); | |
695 | if (pcie_index_hi != 0) { | |
696 | writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); | |
697 | readl(pcie_index_hi_offset); | |
698 | } | |
699 | writel(reg_data, pcie_data_offset); | |
700 | readl(pcie_data_offset); | |
701 | ||
702 | /* clear the high bits */ | |
703 | if (pcie_index_hi != 0) { | |
704 | writel(0, pcie_index_hi_offset); | |
705 | readl(pcie_index_hi_offset); | |
706 | } | |
707 | ||
708 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
709 | } | |
710 | ||
1bba3683 HZ |
711 | /** |
712 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
713 | * | |
714 | * @adev: amdgpu_device pointer | |
1bba3683 HZ |
715 | * @reg_addr: indirect register offset |
716 | * @reg_data: indirect register data | |
717 | * | |
718 | */ | |
719 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
1bba3683 HZ |
720 | u32 reg_addr, u64 reg_data) |
721 | { | |
65ba96e9 | 722 | unsigned long flags, pcie_index, pcie_data; |
1bba3683 HZ |
723 | void __iomem *pcie_index_offset; |
724 | void __iomem *pcie_data_offset; | |
725 | ||
65ba96e9 HZ |
726 | pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); |
727 | pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
728 | ||
1bba3683 HZ |
729 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
730 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
731 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
732 | ||
733 | /* write low 32 bits */ | |
734 | writel(reg_addr, pcie_index_offset); | |
735 | readl(pcie_index_offset); | |
736 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
737 | readl(pcie_data_offset); | |
738 | /* write high 32 bits */ | |
739 | writel(reg_addr + 4, pcie_index_offset); | |
740 | readl(pcie_index_offset); | |
741 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
742 | readl(pcie_data_offset); | |
743 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
744 | } | |
745 | ||
dabc114e HZ |
746 | /** |
747 | * amdgpu_device_get_rev_id - query device rev_id | |
748 | * | |
749 | * @adev: amdgpu_device pointer | |
750 | * | |
751 | * Return device rev_id | |
752 | */ | |
753 | u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) | |
754 | { | |
755 | return adev->nbio.funcs->get_rev_id(adev); | |
756 | } | |
757 | ||
d38ceaf9 AD |
758 | /** |
759 | * amdgpu_invalid_rreg - dummy reg read function | |
760 | * | |
982a820b | 761 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
762 | * @reg: offset of register |
763 | * | |
764 | * Dummy register read function. Used for register blocks | |
765 | * that certain asics don't have (all asics). | |
766 | * Returns the value in the register. | |
767 | */ | |
768 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
769 | { | |
770 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
771 | BUG(); | |
772 | return 0; | |
773 | } | |
774 | ||
0c552ed3 LM |
775 | static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg) |
776 | { | |
777 | DRM_ERROR("Invalid callback to read register 0x%llX\n", reg); | |
778 | BUG(); | |
779 | return 0; | |
780 | } | |
781 | ||
d38ceaf9 AD |
782 | /** |
783 | * amdgpu_invalid_wreg - dummy reg write function | |
784 | * | |
982a820b | 785 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
786 | * @reg: offset of register |
787 | * @v: value to write to the register | |
788 | * | |
789 | * Dummy register read function. Used for register blocks | |
790 | * that certain asics don't have (all asics). | |
791 | */ | |
792 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
793 | { | |
794 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
795 | reg, v); | |
796 | BUG(); | |
797 | } | |
798 | ||
0c552ed3 LM |
799 | static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v) |
800 | { | |
801 | DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n", | |
802 | reg, v); | |
803 | BUG(); | |
804 | } | |
805 | ||
4fa1c6a6 TZ |
806 | /** |
807 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
808 | * | |
982a820b | 809 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
810 | * @reg: offset of register |
811 | * | |
812 | * Dummy register read function. Used for register blocks | |
813 | * that certain asics don't have (all asics). | |
814 | * Returns the value in the register. | |
815 | */ | |
816 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
817 | { | |
818 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
819 | BUG(); | |
820 | return 0; | |
821 | } | |
822 | ||
823 | /** | |
824 | * amdgpu_invalid_wreg64 - dummy reg write function | |
825 | * | |
982a820b | 826 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
827 | * @reg: offset of register |
828 | * @v: value to write to the register | |
829 | * | |
830 | * Dummy register read function. Used for register blocks | |
831 | * that certain asics don't have (all asics). | |
832 | */ | |
833 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
834 | { | |
835 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
836 | reg, v); | |
837 | BUG(); | |
838 | } | |
839 | ||
d38ceaf9 AD |
840 | /** |
841 | * amdgpu_block_invalid_rreg - dummy reg read function | |
842 | * | |
982a820b | 843 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
844 | * @block: offset of instance |
845 | * @reg: offset of register | |
846 | * | |
847 | * Dummy register read function. Used for register blocks | |
848 | * that certain asics don't have (all asics). | |
849 | * Returns the value in the register. | |
850 | */ | |
851 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
852 | uint32_t block, uint32_t reg) | |
853 | { | |
854 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
855 | reg, block); | |
856 | BUG(); | |
857 | return 0; | |
858 | } | |
859 | ||
860 | /** | |
861 | * amdgpu_block_invalid_wreg - dummy reg write function | |
862 | * | |
982a820b | 863 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
864 | * @block: offset of instance |
865 | * @reg: offset of register | |
866 | * @v: value to write to the register | |
867 | * | |
868 | * Dummy register read function. Used for register blocks | |
869 | * that certain asics don't have (all asics). | |
870 | */ | |
871 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
872 | uint32_t block, | |
873 | uint32_t reg, uint32_t v) | |
874 | { | |
875 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
876 | reg, block, v); | |
877 | BUG(); | |
878 | } | |
879 | ||
4d2997ab AD |
880 | /** |
881 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
882 | * | |
982a820b | 883 | * @adev: amdgpu_device pointer |
4d2997ab AD |
884 | * |
885 | * Does any asic specific work and then calls atom asic init. | |
886 | */ | |
887 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
888 | { | |
15c5c5f5 LL |
889 | int ret; |
890 | ||
4d2997ab AD |
891 | amdgpu_asic_pre_asic_init(adev); |
892 | ||
5db392a0 | 893 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) || |
15c5c5f5 LL |
894 | adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) { |
895 | amdgpu_psp_wait_for_bootloader(adev); | |
896 | ret = amdgpu_atomfirmware_asic_init(adev, true); | |
897 | return ret; | |
898 | } else { | |
85d1bcc6 | 899 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); |
15c5c5f5 LL |
900 | } |
901 | ||
902 | return 0; | |
4d2997ab AD |
903 | } |
904 | ||
e3ecdffa | 905 | /** |
7ccfd79f | 906 | * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page |
e3ecdffa | 907 | * |
982a820b | 908 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
909 | * |
910 | * Allocates a scratch page of VRAM for use by various things in the | |
911 | * driver. | |
912 | */ | |
7ccfd79f | 913 | static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 914 | { |
7ccfd79f CK |
915 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, |
916 | AMDGPU_GEM_DOMAIN_VRAM | | |
917 | AMDGPU_GEM_DOMAIN_GTT, | |
918 | &adev->mem_scratch.robj, | |
919 | &adev->mem_scratch.gpu_addr, | |
920 | (void **)&adev->mem_scratch.ptr); | |
d38ceaf9 AD |
921 | } |
922 | ||
e3ecdffa | 923 | /** |
7ccfd79f | 924 | * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page |
e3ecdffa | 925 | * |
982a820b | 926 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
927 | * |
928 | * Frees the VRAM scratch page. | |
929 | */ | |
7ccfd79f | 930 | static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 931 | { |
7ccfd79f | 932 | amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
933 | } |
934 | ||
935 | /** | |
9c3f2b54 | 936 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
937 | * |
938 | * @adev: amdgpu_device pointer | |
939 | * @registers: pointer to the register array | |
940 | * @array_size: size of the register array | |
941 | * | |
b8920e1e | 942 | * Programs an array or registers with and or masks. |
d38ceaf9 AD |
943 | * This is a helper for setting golden registers. |
944 | */ | |
9c3f2b54 AD |
945 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
946 | const u32 *registers, | |
947 | const u32 array_size) | |
d38ceaf9 AD |
948 | { |
949 | u32 tmp, reg, and_mask, or_mask; | |
950 | int i; | |
951 | ||
952 | if (array_size % 3) | |
953 | return; | |
954 | ||
47fc644f | 955 | for (i = 0; i < array_size; i += 3) { |
d38ceaf9 AD |
956 | reg = registers[i + 0]; |
957 | and_mask = registers[i + 1]; | |
958 | or_mask = registers[i + 2]; | |
959 | ||
960 | if (and_mask == 0xffffffff) { | |
961 | tmp = or_mask; | |
962 | } else { | |
963 | tmp = RREG32(reg); | |
964 | tmp &= ~and_mask; | |
e0d07657 HZ |
965 | if (adev->family >= AMDGPU_FAMILY_AI) |
966 | tmp |= (or_mask & and_mask); | |
967 | else | |
968 | tmp |= or_mask; | |
d38ceaf9 AD |
969 | } |
970 | WREG32(reg, tmp); | |
971 | } | |
972 | } | |
973 | ||
e3ecdffa AD |
974 | /** |
975 | * amdgpu_device_pci_config_reset - reset the GPU | |
976 | * | |
977 | * @adev: amdgpu_device pointer | |
978 | * | |
979 | * Resets the GPU using the pci config reset sequence. | |
980 | * Only applicable to asics prior to vega10. | |
981 | */ | |
8111c387 | 982 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
983 | { |
984 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
985 | } | |
986 | ||
af484df8 AD |
987 | /** |
988 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
989 | * | |
990 | * @adev: amdgpu_device pointer | |
991 | * | |
992 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
993 | */ | |
994 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
995 | { | |
996 | return pci_reset_function(adev->pdev); | |
997 | } | |
998 | ||
d38ceaf9 | 999 | /* |
06ec9070 | 1000 | * amdgpu_device_wb_*() |
455a7bc2 | 1001 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1002 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1003 | */ |
1004 | ||
1005 | /** | |
06ec9070 | 1006 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1007 | * |
1008 | * @adev: amdgpu_device pointer | |
1009 | * | |
1010 | * Disables Writeback and frees the Writeback memory (all asics). | |
1011 | * Used at driver shutdown. | |
1012 | */ | |
06ec9070 | 1013 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1014 | { |
1015 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1016 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1017 | &adev->wb.gpu_addr, | |
1018 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1019 | adev->wb.wb_obj = NULL; |
1020 | } | |
1021 | } | |
1022 | ||
1023 | /** | |
03f2abb0 | 1024 | * amdgpu_device_wb_init - Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1025 | * |
1026 | * @adev: amdgpu_device pointer | |
1027 | * | |
455a7bc2 | 1028 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1029 | * Used at driver startup. |
1030 | * Returns 0 on success or an -error on failure. | |
1031 | */ | |
06ec9070 | 1032 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1033 | { |
1034 | int r; | |
1035 | ||
1036 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1037 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1038 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1039 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1040 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1041 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1042 | if (r) { |
1043 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1044 | return r; | |
1045 | } | |
d38ceaf9 AD |
1046 | |
1047 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1048 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1049 | ||
1050 | /* clear wb memory */ | |
73469585 | 1051 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1052 | } |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | /** | |
131b4b36 | 1058 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1059 | * |
1060 | * @adev: amdgpu_device pointer | |
1061 | * @wb: wb index | |
1062 | * | |
1063 | * Allocate a wb slot for use by the driver (all asics). | |
1064 | * Returns 0 on success or -EINVAL on failure. | |
1065 | */ | |
131b4b36 | 1066 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1067 | { |
1068 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1069 | |
97407b63 | 1070 | if (offset < adev->wb.num_wb) { |
7014285a | 1071 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1072 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1073 | return 0; |
1074 | } else { | |
1075 | return -EINVAL; | |
1076 | } | |
1077 | } | |
1078 | ||
d38ceaf9 | 1079 | /** |
131b4b36 | 1080 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1081 | * |
1082 | * @adev: amdgpu_device pointer | |
1083 | * @wb: wb index | |
1084 | * | |
1085 | * Free a wb slot allocated for use by the driver (all asics) | |
1086 | */ | |
131b4b36 | 1087 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1088 | { |
73469585 | 1089 | wb >>= 3; |
d38ceaf9 | 1090 | if (wb < adev->wb.num_wb) |
73469585 | 1091 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1092 | } |
1093 | ||
d6895ad3 CK |
1094 | /** |
1095 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1096 | * | |
1097 | * @adev: amdgpu_device pointer | |
1098 | * | |
1099 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1100 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1101 | * driver loading by returning -ENODEV. | |
1102 | */ | |
1103 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1104 | { | |
453f617a | 1105 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1106 | struct pci_bus *root; |
1107 | struct resource *res; | |
b8920e1e | 1108 | unsigned int i; |
d6895ad3 CK |
1109 | u16 cmd; |
1110 | int r; | |
1111 | ||
822130b5 AB |
1112 | if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) |
1113 | return 0; | |
1114 | ||
0c03b912 | 1115 | /* Bypass for VF */ |
1116 | if (amdgpu_sriov_vf(adev)) | |
1117 | return 0; | |
1118 | ||
b7221f2b AD |
1119 | /* skip if the bios has already enabled large BAR */ |
1120 | if (adev->gmc.real_vram_size && | |
1121 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1122 | return 0; | |
1123 | ||
31b8adab CK |
1124 | /* Check if the root BUS has 64bit memory resources */ |
1125 | root = adev->pdev->bus; | |
1126 | while (root->parent) | |
1127 | root = root->parent; | |
1128 | ||
1129 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1130 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1131 | res->start > 0x100000000ull) |
1132 | break; | |
1133 | } | |
1134 | ||
1135 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1136 | if (!res) | |
1137 | return 0; | |
1138 | ||
453f617a ND |
1139 | /* Limit the BAR size to what is available */ |
1140 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1141 | rbar_size); | |
1142 | ||
d6895ad3 CK |
1143 | /* Disable memory decoding while we change the BAR addresses and size */ |
1144 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1145 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1146 | cmd & ~PCI_COMMAND_MEMORY); | |
1147 | ||
1148 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
43c064db | 1149 | amdgpu_doorbell_fini(adev); |
d6895ad3 CK |
1150 | if (adev->asic_type >= CHIP_BONAIRE) |
1151 | pci_release_resource(adev->pdev, 2); | |
1152 | ||
1153 | pci_release_resource(adev->pdev, 0); | |
1154 | ||
1155 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1156 | if (r == -ENOSPC) | |
1157 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1158 | else if (r && r != -ENOTSUPP) | |
1159 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1160 | ||
1161 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1162 | ||
1163 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1164 | * using the device. | |
1165 | */ | |
43c064db | 1166 | r = amdgpu_doorbell_init(adev); |
d6895ad3 CK |
1167 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1168 | return -ENODEV; | |
1169 | ||
1170 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1171 | ||
1172 | return 0; | |
1173 | } | |
a05502e5 | 1174 | |
9535a86a SZ |
1175 | static bool amdgpu_device_read_bios(struct amdgpu_device *adev) |
1176 | { | |
b8920e1e | 1177 | if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) |
9535a86a | 1178 | return false; |
9535a86a SZ |
1179 | |
1180 | return true; | |
1181 | } | |
1182 | ||
d38ceaf9 AD |
1183 | /* |
1184 | * GPU helpers function. | |
1185 | */ | |
1186 | /** | |
39c640c0 | 1187 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1188 | * |
1189 | * @adev: amdgpu_device pointer | |
1190 | * | |
c836fec5 JQ |
1191 | * Check if the asic has been initialized (all asics) at driver startup |
1192 | * or post is needed if hw reset is performed. | |
1193 | * Returns true if need or false if not. | |
d38ceaf9 | 1194 | */ |
39c640c0 | 1195 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1196 | { |
1197 | uint32_t reg; | |
1198 | ||
bec86378 ML |
1199 | if (amdgpu_sriov_vf(adev)) |
1200 | return false; | |
1201 | ||
9535a86a SZ |
1202 | if (!amdgpu_device_read_bios(adev)) |
1203 | return false; | |
1204 | ||
bec86378 | 1205 | if (amdgpu_passthrough(adev)) { |
1da2c326 ML |
1206 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1207 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1208 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1209 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1210 | */ |
1211 | if (adev->asic_type == CHIP_FIJI) { | |
1212 | int err; | |
1213 | uint32_t fw_ver; | |
b8920e1e | 1214 | |
bec86378 ML |
1215 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); |
1216 | /* force vPost if error occured */ | |
1217 | if (err) | |
1218 | return true; | |
1219 | ||
1220 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1221 | if (fw_ver < 0x00160e00) |
1222 | return true; | |
bec86378 | 1223 | } |
bec86378 | 1224 | } |
91fe77eb | 1225 | |
e3c1b071 | 1226 | /* Don't post if we need to reset whole hive on init */ |
1227 | if (adev->gmc.xgmi.pending_reset) | |
1228 | return false; | |
1229 | ||
91fe77eb | 1230 | if (adev->has_hw_reset) { |
1231 | adev->has_hw_reset = false; | |
1232 | return true; | |
1233 | } | |
1234 | ||
1235 | /* bios scratch used on CIK+ */ | |
1236 | if (adev->asic_type >= CHIP_BONAIRE) | |
1237 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1238 | ||
1239 | /* check MEM_SIZE for older asics */ | |
1240 | reg = amdgpu_asic_get_config_memsize(adev); | |
1241 | ||
1242 | if ((reg != 0) && (reg != 0xffffffff)) | |
1243 | return false; | |
1244 | ||
1245 | return true; | |
bec86378 ML |
1246 | } |
1247 | ||
70e64c4d ML |
1248 | /* |
1249 | * On APUs with >= 64GB white flickering has been observed w/ SG enabled. | |
1250 | * Disable S/G on such systems until we have a proper fix. | |
1251 | * https://gitlab.freedesktop.org/drm/amd/-/issues/2354 | |
1252 | * https://gitlab.freedesktop.org/drm/amd/-/issues/2735 | |
1253 | */ | |
1254 | bool amdgpu_sg_display_supported(struct amdgpu_device *adev) | |
1255 | { | |
1256 | switch (amdgpu_sg_display) { | |
1257 | case -1: | |
1258 | break; | |
1259 | case 0: | |
1260 | return false; | |
1261 | case 1: | |
1262 | return true; | |
1263 | default: | |
1264 | return false; | |
1265 | } | |
1266 | if ((totalram_pages() << (PAGE_SHIFT - 10)) + | |
1267 | (adev->gmc.real_vram_size / 1024) >= 64000000) { | |
1268 | DRM_WARN("Disabling S/G due to >=64GB RAM\n"); | |
1269 | return false; | |
1270 | } | |
1271 | return true; | |
1272 | } | |
1273 | ||
5d1eb4c4 ML |
1274 | /* |
1275 | * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic | |
1276 | * speed switching. Until we have confirmation from Intel that a specific host | |
1277 | * supports it, it's safer that we keep it disabled for all. | |
1278 | * | |
1279 | * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/ | |
1280 | * https://gitlab.freedesktop.org/drm/amd/-/issues/2663 | |
1281 | */ | |
1282 | bool amdgpu_device_pcie_dynamic_switching_supported(void) | |
1283 | { | |
1284 | #if IS_ENABLED(CONFIG_X86) | |
1285 | struct cpuinfo_x86 *c = &cpu_data(0); | |
1286 | ||
1287 | if (c->x86_vendor == X86_VENDOR_INTEL) | |
1288 | return false; | |
1289 | #endif | |
1290 | return true; | |
1291 | } | |
1292 | ||
0ab5d711 ML |
1293 | /** |
1294 | * amdgpu_device_should_use_aspm - check if the device should program ASPM | |
1295 | * | |
1296 | * @adev: amdgpu_device pointer | |
1297 | * | |
1298 | * Confirm whether the module parameter and pcie bridge agree that ASPM should | |
1299 | * be set for this device. | |
1300 | * | |
1301 | * Returns true if it should be used or false if not. | |
1302 | */ | |
1303 | bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) | |
1304 | { | |
1305 | switch (amdgpu_aspm) { | |
1306 | case -1: | |
1307 | break; | |
1308 | case 0: | |
1309 | return false; | |
1310 | case 1: | |
1311 | return true; | |
1312 | default: | |
1313 | return false; | |
1314 | } | |
1315 | return pcie_aspm_enabled(adev->pdev); | |
1316 | } | |
1317 | ||
3ad5dcfe KHF |
1318 | bool amdgpu_device_aspm_support_quirk(void) |
1319 | { | |
1320 | #if IS_ENABLED(CONFIG_X86) | |
1321 | struct cpuinfo_x86 *c = &cpu_data(0); | |
1322 | ||
1323 | return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE); | |
1324 | #else | |
1325 | return true; | |
1326 | #endif | |
1327 | } | |
1328 | ||
d38ceaf9 AD |
1329 | /* if we get transitioned to only one device, take VGA back */ |
1330 | /** | |
06ec9070 | 1331 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 | 1332 | * |
bf44e8ce | 1333 | * @pdev: PCI device pointer |
d38ceaf9 AD |
1334 | * @state: enable/disable vga decode |
1335 | * | |
1336 | * Enable/disable vga decode (all asics). | |
1337 | * Returns VGA resource flags. | |
1338 | */ | |
bf44e8ce CH |
1339 | static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, |
1340 | bool state) | |
d38ceaf9 | 1341 | { |
bf44e8ce | 1342 | struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); |
b8920e1e | 1343 | |
d38ceaf9 AD |
1344 | amdgpu_asic_set_vga_state(adev, state); |
1345 | if (state) | |
1346 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1347 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1348 | else | |
1349 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1350 | } | |
1351 | ||
e3ecdffa AD |
1352 | /** |
1353 | * amdgpu_device_check_block_size - validate the vm block size | |
1354 | * | |
1355 | * @adev: amdgpu_device pointer | |
1356 | * | |
1357 | * Validates the vm block size specified via module parameter. | |
1358 | * The vm block size defines number of bits in page table versus page directory, | |
1359 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1360 | * page table and the remaining bits are in the page directory. | |
1361 | */ | |
06ec9070 | 1362 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1363 | { |
1364 | /* defines number of bits in page table versus page directory, | |
1365 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
b8920e1e SS |
1366 | * page table and the remaining bits are in the page directory |
1367 | */ | |
bab4fee7 JZ |
1368 | if (amdgpu_vm_block_size == -1) |
1369 | return; | |
a1adf8be | 1370 | |
bab4fee7 | 1371 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1372 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1373 | amdgpu_vm_block_size); | |
97489129 | 1374 | amdgpu_vm_block_size = -1; |
a1adf8be | 1375 | } |
a1adf8be CZ |
1376 | } |
1377 | ||
e3ecdffa AD |
1378 | /** |
1379 | * amdgpu_device_check_vm_size - validate the vm size | |
1380 | * | |
1381 | * @adev: amdgpu_device pointer | |
1382 | * | |
1383 | * Validates the vm size in GB specified via module parameter. | |
1384 | * The VM size is the size of the GPU virtual memory space in GB. | |
1385 | */ | |
06ec9070 | 1386 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1387 | { |
64dab074 AD |
1388 | /* no need to check the default value */ |
1389 | if (amdgpu_vm_size == -1) | |
1390 | return; | |
1391 | ||
83ca145d ZJ |
1392 | if (amdgpu_vm_size < 1) { |
1393 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1394 | amdgpu_vm_size); | |
f3368128 | 1395 | amdgpu_vm_size = -1; |
83ca145d | 1396 | } |
83ca145d ZJ |
1397 | } |
1398 | ||
7951e376 RZ |
1399 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1400 | { | |
1401 | struct sysinfo si; | |
a9d4fe2f | 1402 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1403 | uint64_t total_memory; |
1404 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1405 | uint64_t dram_size_three_GB = 0xB8000000; | |
1406 | ||
1407 | if (amdgpu_smu_memory_pool_size == 0) | |
1408 | return; | |
1409 | ||
1410 | if (!is_os_64) { | |
1411 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1412 | goto def_value; | |
1413 | } | |
1414 | si_meminfo(&si); | |
1415 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1416 | ||
1417 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1418 | (amdgpu_smu_memory_pool_size == 2)) { | |
1419 | if (total_memory < dram_size_three_GB) | |
1420 | goto def_value1; | |
1421 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1422 | (amdgpu_smu_memory_pool_size == 8)) { | |
1423 | if (total_memory < dram_size_seven_GB) | |
1424 | goto def_value1; | |
1425 | } else { | |
1426 | DRM_WARN("Smu memory pool size not supported\n"); | |
1427 | goto def_value; | |
1428 | } | |
1429 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1430 | ||
1431 | return; | |
1432 | ||
1433 | def_value1: | |
1434 | DRM_WARN("No enough system memory\n"); | |
1435 | def_value: | |
1436 | adev->pm.smu_prv_buffer_size = 0; | |
1437 | } | |
1438 | ||
9f6a7857 HR |
1439 | static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) |
1440 | { | |
1441 | if (!(adev->flags & AMD_IS_APU) || | |
1442 | adev->asic_type < CHIP_RAVEN) | |
1443 | return 0; | |
1444 | ||
1445 | switch (adev->asic_type) { | |
1446 | case CHIP_RAVEN: | |
1447 | if (adev->pdev->device == 0x15dd) | |
1448 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1449 | if (adev->pdev->device == 0x15d8) | |
1450 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
1451 | break; | |
1452 | case CHIP_RENOIR: | |
1453 | if ((adev->pdev->device == 0x1636) || | |
1454 | (adev->pdev->device == 0x164c)) | |
1455 | adev->apu_flags |= AMD_APU_IS_RENOIR; | |
1456 | else | |
1457 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1458 | break; | |
1459 | case CHIP_VANGOGH: | |
1460 | adev->apu_flags |= AMD_APU_IS_VANGOGH; | |
1461 | break; | |
1462 | case CHIP_YELLOW_CARP: | |
1463 | break; | |
d0f56dc2 | 1464 | case CHIP_CYAN_SKILLFISH: |
dfcc3e8c AD |
1465 | if ((adev->pdev->device == 0x13FE) || |
1466 | (adev->pdev->device == 0x143F)) | |
d0f56dc2 TZ |
1467 | adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2; |
1468 | break; | |
9f6a7857 | 1469 | default: |
4eaf21b7 | 1470 | break; |
9f6a7857 HR |
1471 | } |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
d38ceaf9 | 1476 | /** |
06ec9070 | 1477 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1478 | * |
1479 | * @adev: amdgpu_device pointer | |
1480 | * | |
1481 | * Validates certain module parameters and updates | |
1482 | * the associated values used by the driver (all asics). | |
1483 | */ | |
912dfc84 | 1484 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1485 | { |
5b011235 CZ |
1486 | if (amdgpu_sched_jobs < 4) { |
1487 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1488 | amdgpu_sched_jobs); | |
1489 | amdgpu_sched_jobs = 4; | |
47fc644f | 1490 | } else if (!is_power_of_2(amdgpu_sched_jobs)) { |
5b011235 CZ |
1491 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1492 | amdgpu_sched_jobs); | |
1493 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1494 | } | |
d38ceaf9 | 1495 | |
83e74db6 | 1496 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1497 | /* gart size must be greater or equal to 32M */ |
1498 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1499 | amdgpu_gart_size); | |
83e74db6 | 1500 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1501 | } |
1502 | ||
36d38372 | 1503 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1504 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1505 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1506 | amdgpu_gtt_size); | |
1507 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1508 | } |
1509 | ||
d07f14be RH |
1510 | /* valid range is between 4 and 9 inclusive */ |
1511 | if (amdgpu_vm_fragment_size != -1 && | |
1512 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1513 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1514 | amdgpu_vm_fragment_size = -1; | |
1515 | } | |
1516 | ||
5d5bd5e3 KW |
1517 | if (amdgpu_sched_hw_submission < 2) { |
1518 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1519 | amdgpu_sched_hw_submission); | |
1520 | amdgpu_sched_hw_submission = 2; | |
1521 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1522 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1523 | amdgpu_sched_hw_submission); | |
1524 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1525 | } | |
1526 | ||
2656fd23 AG |
1527 | if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) { |
1528 | dev_warn(adev->dev, "invalid option for reset method, reverting to default\n"); | |
1529 | amdgpu_reset_method = -1; | |
1530 | } | |
1531 | ||
7951e376 RZ |
1532 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1533 | ||
06ec9070 | 1534 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1535 | |
06ec9070 | 1536 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1537 | |
19aede77 | 1538 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1539 | |
e3c00faa | 1540 | return 0; |
d38ceaf9 AD |
1541 | } |
1542 | ||
1543 | /** | |
1544 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1545 | * | |
1546 | * @pdev: pci dev pointer | |
1694467b | 1547 | * @state: vga_switcheroo state |
d38ceaf9 | 1548 | * |
12024b17 | 1549 | * Callback for the switcheroo driver. Suspends or resumes |
d38ceaf9 AD |
1550 | * the asics before or after it is powered up using ACPI methods. |
1551 | */ | |
8aba21b7 LT |
1552 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1553 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1554 | { |
1555 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1556 | int r; |
d38ceaf9 | 1557 | |
b98c6299 | 1558 | if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1559 | return; |
1560 | ||
1561 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1562 | pr_info("switched on\n"); |
d38ceaf9 AD |
1563 | /* don't suspend or resume card normally */ |
1564 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1565 | ||
8f66090b TZ |
1566 | pci_set_power_state(pdev, PCI_D0); |
1567 | amdgpu_device_load_pci_state(pdev); | |
1568 | r = pci_enable_device(pdev); | |
de185019 AD |
1569 | if (r) |
1570 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1571 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1572 | |
d38ceaf9 | 1573 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1574 | } else { |
dd4fa6c1 | 1575 | pr_info("switched off\n"); |
d38ceaf9 | 1576 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
de185019 | 1577 | amdgpu_device_suspend(dev, true); |
8f66090b | 1578 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1579 | /* Shut down the device */ |
8f66090b TZ |
1580 | pci_disable_device(pdev); |
1581 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1582 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1583 | } | |
1584 | } | |
1585 | ||
1586 | /** | |
1587 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1588 | * | |
1589 | * @pdev: pci dev pointer | |
1590 | * | |
1591 | * Callback for the switcheroo driver. Check of the switcheroo | |
1592 | * state can be changed. | |
1593 | * Returns true if the state can be changed, false if not. | |
1594 | */ | |
1595 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1596 | { | |
1597 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1598 | ||
b8920e1e | 1599 | /* |
d38ceaf9 AD |
1600 | * FIXME: open_count is protected by drm_global_mutex but that would lead to |
1601 | * locking inversion with the driver load path. And the access here is | |
1602 | * completely racy anyway. So don't bother with locking for now. | |
1603 | */ | |
7e13ad89 | 1604 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1605 | } |
1606 | ||
1607 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1608 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1609 | .reprobe = NULL, | |
1610 | .can_switch = amdgpu_switcheroo_can_switch, | |
1611 | }; | |
1612 | ||
e3ecdffa AD |
1613 | /** |
1614 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1615 | * | |
87e3f136 | 1616 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1617 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1618 | * @state: clockgating state (gate or ungate) | |
1619 | * | |
1620 | * Sets the requested clockgating state for all instances of | |
1621 | * the hardware IP specified. | |
1622 | * Returns the error code from the last instance. | |
1623 | */ | |
43fa561f | 1624 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1625 | enum amd_ip_block_type block_type, |
1626 | enum amd_clockgating_state state) | |
d38ceaf9 | 1627 | { |
43fa561f | 1628 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1629 | int i, r = 0; |
1630 | ||
1631 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1632 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1633 | continue; |
c722865a RZ |
1634 | if (adev->ip_blocks[i].version->type != block_type) |
1635 | continue; | |
1636 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1637 | continue; | |
1638 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1639 | (void *)adev, state); | |
1640 | if (r) | |
1641 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1642 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1643 | } |
1644 | return r; | |
1645 | } | |
1646 | ||
e3ecdffa AD |
1647 | /** |
1648 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1649 | * | |
87e3f136 | 1650 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1651 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1652 | * @state: powergating state (gate or ungate) | |
1653 | * | |
1654 | * Sets the requested powergating state for all instances of | |
1655 | * the hardware IP specified. | |
1656 | * Returns the error code from the last instance. | |
1657 | */ | |
43fa561f | 1658 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1659 | enum amd_ip_block_type block_type, |
1660 | enum amd_powergating_state state) | |
d38ceaf9 | 1661 | { |
43fa561f | 1662 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1663 | int i, r = 0; |
1664 | ||
1665 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1666 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1667 | continue; |
c722865a RZ |
1668 | if (adev->ip_blocks[i].version->type != block_type) |
1669 | continue; | |
1670 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1671 | continue; | |
1672 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1673 | (void *)adev, state); | |
1674 | if (r) | |
1675 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1676 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1677 | } |
1678 | return r; | |
1679 | } | |
1680 | ||
e3ecdffa AD |
1681 | /** |
1682 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1683 | * | |
1684 | * @adev: amdgpu_device pointer | |
1685 | * @flags: clockgating feature flags | |
1686 | * | |
1687 | * Walks the list of IPs on the device and updates the clockgating | |
1688 | * flags for each IP. | |
1689 | * Updates @flags with the feature flags for each hardware IP where | |
1690 | * clockgating is enabled. | |
1691 | */ | |
2990a1fc | 1692 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
25faeddc | 1693 | u64 *flags) |
6cb2d4e4 HR |
1694 | { |
1695 | int i; | |
1696 | ||
1697 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1698 | if (!adev->ip_blocks[i].status.valid) | |
1699 | continue; | |
1700 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1701 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1702 | } | |
1703 | } | |
1704 | ||
e3ecdffa AD |
1705 | /** |
1706 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1707 | * | |
1708 | * @adev: amdgpu_device pointer | |
1709 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1710 | * | |
1711 | * Waits for the request hardware IP to be idle. | |
1712 | * Returns 0 for success or a negative error code on failure. | |
1713 | */ | |
2990a1fc AD |
1714 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1715 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1716 | { |
1717 | int i, r; | |
1718 | ||
1719 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1720 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1721 | continue; |
a1255107 AD |
1722 | if (adev->ip_blocks[i].version->type == block_type) { |
1723 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1724 | if (r) |
1725 | return r; | |
1726 | break; | |
1727 | } | |
1728 | } | |
1729 | return 0; | |
1730 | ||
1731 | } | |
1732 | ||
e3ecdffa AD |
1733 | /** |
1734 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1735 | * | |
1736 | * @adev: amdgpu_device pointer | |
1737 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1738 | * | |
1739 | * Check if the hardware IP is idle or not. | |
1740 | * Returns true if it the IP is idle, false if not. | |
1741 | */ | |
2990a1fc AD |
1742 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1743 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1744 | { |
1745 | int i; | |
1746 | ||
1747 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1748 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1749 | continue; |
a1255107 AD |
1750 | if (adev->ip_blocks[i].version->type == block_type) |
1751 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1752 | } |
1753 | return true; | |
1754 | ||
1755 | } | |
1756 | ||
e3ecdffa AD |
1757 | /** |
1758 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1759 | * | |
1760 | * @adev: amdgpu_device pointer | |
87e3f136 | 1761 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1762 | * |
1763 | * Returns a pointer to the hardware IP block structure | |
1764 | * if it exists for the asic, otherwise NULL. | |
1765 | */ | |
2990a1fc AD |
1766 | struct amdgpu_ip_block * |
1767 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1768 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1769 | { |
1770 | int i; | |
1771 | ||
1772 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1773 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1774 | return &adev->ip_blocks[i]; |
1775 | ||
1776 | return NULL; | |
1777 | } | |
1778 | ||
1779 | /** | |
2990a1fc | 1780 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1781 | * |
1782 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1783 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1784 | * @major: major version |
1785 | * @minor: minor version | |
1786 | * | |
1787 | * return 0 if equal or greater | |
1788 | * return 1 if smaller or the ip_block doesn't exist | |
1789 | */ | |
2990a1fc AD |
1790 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1791 | enum amd_ip_block_type type, | |
1792 | u32 major, u32 minor) | |
d38ceaf9 | 1793 | { |
2990a1fc | 1794 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1795 | |
a1255107 AD |
1796 | if (ip_block && ((ip_block->version->major > major) || |
1797 | ((ip_block->version->major == major) && | |
1798 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1799 | return 0; |
1800 | ||
1801 | return 1; | |
1802 | } | |
1803 | ||
a1255107 | 1804 | /** |
2990a1fc | 1805 | * amdgpu_device_ip_block_add |
a1255107 AD |
1806 | * |
1807 | * @adev: amdgpu_device pointer | |
1808 | * @ip_block_version: pointer to the IP to add | |
1809 | * | |
1810 | * Adds the IP block driver information to the collection of IPs | |
1811 | * on the asic. | |
1812 | */ | |
2990a1fc AD |
1813 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1814 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1815 | { |
1816 | if (!ip_block_version) | |
1817 | return -EINVAL; | |
1818 | ||
7bd939d0 LG |
1819 | switch (ip_block_version->type) { |
1820 | case AMD_IP_BLOCK_TYPE_VCN: | |
1821 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) | |
1822 | return 0; | |
1823 | break; | |
1824 | case AMD_IP_BLOCK_TYPE_JPEG: | |
1825 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) | |
1826 | return 0; | |
1827 | break; | |
1828 | default: | |
1829 | break; | |
1830 | } | |
1831 | ||
e966a725 | 1832 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1833 | ip_block_version->funcs->name); |
1834 | ||
a1255107 AD |
1835 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1836 | ||
1837 | return 0; | |
1838 | } | |
1839 | ||
e3ecdffa AD |
1840 | /** |
1841 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1842 | * | |
1843 | * @adev: amdgpu_device pointer | |
1844 | * | |
1845 | * Enabled the virtual display feature if the user has enabled it via | |
1846 | * the module parameter virtual_display. This feature provides a virtual | |
1847 | * display hardware on headless boards or in virtualized environments. | |
1848 | * This function parses and validates the configuration string specified by | |
1849 | * the user and configues the virtual display configuration (number of | |
1850 | * virtual connectors, crtcs, etc.) specified. | |
1851 | */ | |
483ef985 | 1852 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1853 | { |
1854 | adev->enable_virtual_display = false; | |
1855 | ||
1856 | if (amdgpu_virtual_display) { | |
8f66090b | 1857 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 1858 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1859 | |
1860 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1861 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1862 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1863 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1864 | if (!strcmp("all", pciaddname) |
1865 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1866 | long num_crtc; |
1867 | int res = -1; | |
1868 | ||
9accf2fd | 1869 | adev->enable_virtual_display = true; |
0f66356d ED |
1870 | |
1871 | if (pciaddname_tmp) | |
1872 | res = kstrtol(pciaddname_tmp, 10, | |
1873 | &num_crtc); | |
1874 | ||
1875 | if (!res) { | |
1876 | if (num_crtc < 1) | |
1877 | num_crtc = 1; | |
1878 | if (num_crtc > 6) | |
1879 | num_crtc = 6; | |
1880 | adev->mode_info.num_crtc = num_crtc; | |
1881 | } else { | |
1882 | adev->mode_info.num_crtc = 1; | |
1883 | } | |
9accf2fd ED |
1884 | break; |
1885 | } | |
1886 | } | |
1887 | ||
0f66356d ED |
1888 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1889 | amdgpu_virtual_display, pci_address_name, | |
1890 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1891 | |
1892 | kfree(pciaddstr); | |
1893 | } | |
1894 | } | |
1895 | ||
25263da3 AD |
1896 | void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev) |
1897 | { | |
1898 | if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) { | |
1899 | adev->mode_info.num_crtc = 1; | |
1900 | adev->enable_virtual_display = true; | |
1901 | DRM_INFO("virtual_display:%d, num_crtc:%d\n", | |
1902 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
1903 | } | |
1904 | } | |
1905 | ||
e3ecdffa AD |
1906 | /** |
1907 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1908 | * | |
1909 | * @adev: amdgpu_device pointer | |
1910 | * | |
1911 | * Parses the asic configuration parameters specified in the gpu info | |
1912 | * firmware and makes them availale to the driver for use in configuring | |
1913 | * the asic. | |
1914 | * Returns 0 on success, -EINVAL on failure. | |
1915 | */ | |
e2a75f88 AD |
1916 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1917 | { | |
e2a75f88 | 1918 | const char *chip_name; |
c0a43457 | 1919 | char fw_name[40]; |
e2a75f88 AD |
1920 | int err; |
1921 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1922 | ||
ab4fe3e1 HR |
1923 | adev->firmware.gpu_info_fw = NULL; |
1924 | ||
72de33f8 | 1925 | if (adev->mman.discovery_bin) { |
cc375d8c TY |
1926 | /* |
1927 | * FIXME: The bounding box is still needed by Navi12, so | |
e24d0e91 | 1928 | * temporarily read it from gpu_info firmware. Should be dropped |
cc375d8c TY |
1929 | * when DAL no longer needs it. |
1930 | */ | |
1931 | if (adev->asic_type != CHIP_NAVI12) | |
1932 | return 0; | |
258620d0 AD |
1933 | } |
1934 | ||
e2a75f88 | 1935 | switch (adev->asic_type) { |
e2a75f88 AD |
1936 | default: |
1937 | return 0; | |
1938 | case CHIP_VEGA10: | |
1939 | chip_name = "vega10"; | |
1940 | break; | |
3f76dced AD |
1941 | case CHIP_VEGA12: |
1942 | chip_name = "vega12"; | |
1943 | break; | |
2d2e5e7e | 1944 | case CHIP_RAVEN: |
54f78a76 | 1945 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1946 | chip_name = "raven2"; |
54f78a76 | 1947 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1948 | chip_name = "picasso"; |
54c4d17e FX |
1949 | else |
1950 | chip_name = "raven"; | |
2d2e5e7e | 1951 | break; |
65e60f6e LM |
1952 | case CHIP_ARCTURUS: |
1953 | chip_name = "arcturus"; | |
1954 | break; | |
42b325e5 XY |
1955 | case CHIP_NAVI12: |
1956 | chip_name = "navi12"; | |
1957 | break; | |
e2a75f88 AD |
1958 | } |
1959 | ||
1960 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
b31d3063 | 1961 | err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name); |
e2a75f88 AD |
1962 | if (err) { |
1963 | dev_err(adev->dev, | |
b31d3063 | 1964 | "Failed to get gpu_info firmware \"%s\"\n", |
e2a75f88 AD |
1965 | fw_name); |
1966 | goto out; | |
1967 | } | |
1968 | ||
ab4fe3e1 | 1969 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1970 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1971 | ||
1972 | switch (hdr->version_major) { | |
1973 | case 1: | |
1974 | { | |
1975 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1976 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1977 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1978 | ||
cc375d8c TY |
1979 | /* |
1980 | * Should be droped when DAL no longer needs it. | |
1981 | */ | |
1982 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
1983 | goto parse_soc_bounding_box; |
1984 | ||
b5ab16bf AD |
1985 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1986 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1987 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1988 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1989 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1990 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1991 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1992 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1993 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1994 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1995 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1996 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1997 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1998 | adev->gfx.cu_info.max_waves_per_simd = |
1999 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
2000 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
2001 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
2002 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 2003 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
2004 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
2005 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
2006 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2007 | adev->gfx.config.num_sc_per_sh = | |
2008 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
2009 | adev->gfx.config.num_packer_per_sc = | |
2010 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
2011 | } | |
ec51d3fa XY |
2012 | |
2013 | parse_soc_bounding_box: | |
ec51d3fa XY |
2014 | /* |
2015 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 2016 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 2017 | */ |
48321c3d HW |
2018 | if (hdr->version_minor == 2) { |
2019 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
2020 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
2021 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2022 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
2023 | } | |
e2a75f88 AD |
2024 | break; |
2025 | } | |
2026 | default: | |
2027 | dev_err(adev->dev, | |
2028 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
2029 | err = -EINVAL; | |
2030 | goto out; | |
2031 | } | |
2032 | out: | |
e2a75f88 AD |
2033 | return err; |
2034 | } | |
2035 | ||
e3ecdffa AD |
2036 | /** |
2037 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
2038 | * | |
2039 | * @adev: amdgpu_device pointer | |
2040 | * | |
2041 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
2042 | * up each asic are discovered each IP's early_init callback is run. This | |
2043 | * is the first stage in initializing the asic. | |
2044 | * Returns 0 on success, negative error code on failure. | |
2045 | */ | |
06ec9070 | 2046 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 2047 | { |
901e2be2 AD |
2048 | struct drm_device *dev = adev_to_drm(adev); |
2049 | struct pci_dev *parent; | |
aaa36a97 | 2050 | int i, r; |
ced69502 | 2051 | bool total; |
d38ceaf9 | 2052 | |
483ef985 | 2053 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 2054 | |
00a979f3 | 2055 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 2056 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
2057 | if (r) |
2058 | return r; | |
00a979f3 WS |
2059 | } |
2060 | ||
d38ceaf9 | 2061 | switch (adev->asic_type) { |
33f34802 KW |
2062 | #ifdef CONFIG_DRM_AMDGPU_SI |
2063 | case CHIP_VERDE: | |
2064 | case CHIP_TAHITI: | |
2065 | case CHIP_PITCAIRN: | |
2066 | case CHIP_OLAND: | |
2067 | case CHIP_HAINAN: | |
295d0daf | 2068 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
2069 | r = si_set_ip_blocks(adev); |
2070 | if (r) | |
2071 | return r; | |
2072 | break; | |
2073 | #endif | |
a2e73f56 AD |
2074 | #ifdef CONFIG_DRM_AMDGPU_CIK |
2075 | case CHIP_BONAIRE: | |
2076 | case CHIP_HAWAII: | |
2077 | case CHIP_KAVERI: | |
2078 | case CHIP_KABINI: | |
2079 | case CHIP_MULLINS: | |
e1ad2d53 | 2080 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 2081 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
2082 | else |
2083 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
2084 | |
2085 | r = cik_set_ip_blocks(adev); | |
2086 | if (r) | |
2087 | return r; | |
2088 | break; | |
2089 | #endif | |
da87c30b AD |
2090 | case CHIP_TOPAZ: |
2091 | case CHIP_TONGA: | |
2092 | case CHIP_FIJI: | |
2093 | case CHIP_POLARIS10: | |
2094 | case CHIP_POLARIS11: | |
2095 | case CHIP_POLARIS12: | |
2096 | case CHIP_VEGAM: | |
2097 | case CHIP_CARRIZO: | |
2098 | case CHIP_STONEY: | |
2099 | if (adev->flags & AMD_IS_APU) | |
2100 | adev->family = AMDGPU_FAMILY_CZ; | |
2101 | else | |
2102 | adev->family = AMDGPU_FAMILY_VI; | |
2103 | ||
2104 | r = vi_set_ip_blocks(adev); | |
2105 | if (r) | |
2106 | return r; | |
2107 | break; | |
d38ceaf9 | 2108 | default: |
63352b7f AD |
2109 | r = amdgpu_discovery_set_ip_blocks(adev); |
2110 | if (r) | |
2111 | return r; | |
2112 | break; | |
d38ceaf9 AD |
2113 | } |
2114 | ||
901e2be2 AD |
2115 | if (amdgpu_has_atpx() && |
2116 | (amdgpu_is_atpx_hybrid() || | |
2117 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
2118 | ((adev->flags & AMD_IS_APU) == 0) && | |
2119 | !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) | |
2120 | adev->flags |= AMD_IS_PX; | |
2121 | ||
85ac2021 AD |
2122 | if (!(adev->flags & AMD_IS_APU)) { |
2123 | parent = pci_upstream_bridge(adev->pdev); | |
2124 | adev->has_pr3 = parent ? pci_pr3_present(parent) : false; | |
2125 | } | |
901e2be2 | 2126 | |
1884734a | 2127 | |
3b94fb10 | 2128 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2129 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2130 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2131 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2132 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
00f54b97 | 2133 | |
ced69502 | 2134 | total = true; |
d38ceaf9 AD |
2135 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2136 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
0c451baf | 2137 | DRM_WARN("disabled ip block: %d <%s>\n", |
ed8cf00c | 2138 | i, adev->ip_blocks[i].version->funcs->name); |
a1255107 | 2139 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2140 | } else { |
a1255107 AD |
2141 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2142 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2143 | if (r == -ENOENT) { |
a1255107 | 2144 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2145 | } else if (r) { |
a1255107 AD |
2146 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2147 | adev->ip_blocks[i].version->funcs->name, r); | |
ced69502 | 2148 | total = false; |
2c1a2784 | 2149 | } else { |
a1255107 | 2150 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2151 | } |
974e6b64 | 2152 | } else { |
a1255107 | 2153 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2154 | } |
d38ceaf9 | 2155 | } |
21a249ca AD |
2156 | /* get the vbios after the asic_funcs are set up */ |
2157 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2158 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2159 | if (r) | |
2160 | return r; | |
2161 | ||
21a249ca | 2162 | /* Read BIOS */ |
9535a86a SZ |
2163 | if (amdgpu_device_read_bios(adev)) { |
2164 | if (!amdgpu_get_bios(adev)) | |
2165 | return -EINVAL; | |
21a249ca | 2166 | |
9535a86a SZ |
2167 | r = amdgpu_atombios_init(adev); |
2168 | if (r) { | |
2169 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2170 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2171 | return r; | |
2172 | } | |
21a249ca | 2173 | } |
77eabc6f PJZ |
2174 | |
2175 | /*get pf2vf msg info at it's earliest time*/ | |
2176 | if (amdgpu_sriov_vf(adev)) | |
2177 | amdgpu_virt_init_data_exchange(adev); | |
2178 | ||
21a249ca | 2179 | } |
d38ceaf9 | 2180 | } |
ced69502 ML |
2181 | if (!total) |
2182 | return -ENODEV; | |
d38ceaf9 | 2183 | |
00fa4035 | 2184 | amdgpu_amdkfd_device_probe(adev); |
395d1fb9 NH |
2185 | adev->cg_flags &= amdgpu_cg_mask; |
2186 | adev->pg_flags &= amdgpu_pg_mask; | |
2187 | ||
d38ceaf9 AD |
2188 | return 0; |
2189 | } | |
2190 | ||
0a4f2520 RZ |
2191 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2192 | { | |
2193 | int i, r; | |
2194 | ||
2195 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2196 | if (!adev->ip_blocks[i].status.sw) | |
2197 | continue; | |
2198 | if (adev->ip_blocks[i].status.hw) | |
2199 | continue; | |
2200 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2201 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2202 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2203 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2204 | if (r) { | |
2205 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2206 | adev->ip_blocks[i].version->funcs->name, r); | |
2207 | return r; | |
2208 | } | |
2209 | adev->ip_blocks[i].status.hw = true; | |
2210 | } | |
2211 | } | |
2212 | ||
2213 | return 0; | |
2214 | } | |
2215 | ||
2216 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2217 | { | |
2218 | int i, r; | |
2219 | ||
2220 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2221 | if (!adev->ip_blocks[i].status.sw) | |
2222 | continue; | |
2223 | if (adev->ip_blocks[i].status.hw) | |
2224 | continue; | |
2225 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2226 | if (r) { | |
2227 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2228 | adev->ip_blocks[i].version->funcs->name, r); | |
2229 | return r; | |
2230 | } | |
2231 | adev->ip_blocks[i].status.hw = true; | |
2232 | } | |
2233 | ||
2234 | return 0; | |
2235 | } | |
2236 | ||
7a3e0bb2 RZ |
2237 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2238 | { | |
2239 | int r = 0; | |
2240 | int i; | |
80f41f84 | 2241 | uint32_t smu_version; |
7a3e0bb2 RZ |
2242 | |
2243 | if (adev->asic_type >= CHIP_VEGA10) { | |
2244 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2245 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2246 | continue; | |
2247 | ||
e3c1b071 | 2248 | if (!adev->ip_blocks[i].status.sw) |
2249 | continue; | |
2250 | ||
482f0e53 ML |
2251 | /* no need to do the fw loading again if already done*/ |
2252 | if (adev->ip_blocks[i].status.hw == true) | |
2253 | break; | |
2254 | ||
53b3f8f4 | 2255 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2256 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2257 | if (r) { | |
2258 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2259 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2260 | return r; |
2261 | } | |
2262 | } else { | |
2263 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2264 | if (r) { | |
2265 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2266 | adev->ip_blocks[i].version->funcs->name, r); | |
2267 | return r; | |
7a3e0bb2 | 2268 | } |
7a3e0bb2 | 2269 | } |
482f0e53 ML |
2270 | |
2271 | adev->ip_blocks[i].status.hw = true; | |
2272 | break; | |
7a3e0bb2 RZ |
2273 | } |
2274 | } | |
482f0e53 | 2275 | |
8973d9ec ED |
2276 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2277 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2278 | |
80f41f84 | 2279 | return r; |
7a3e0bb2 RZ |
2280 | } |
2281 | ||
5fd8518d AG |
2282 | static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) |
2283 | { | |
2284 | long timeout; | |
2285 | int r, i; | |
2286 | ||
2287 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2288 | struct amdgpu_ring *ring = adev->rings[i]; | |
2289 | ||
2290 | /* No need to setup the GPU scheduler for rings that don't need it */ | |
2291 | if (!ring || ring->no_scheduler) | |
2292 | continue; | |
2293 | ||
2294 | switch (ring->funcs->type) { | |
2295 | case AMDGPU_RING_TYPE_GFX: | |
2296 | timeout = adev->gfx_timeout; | |
2297 | break; | |
2298 | case AMDGPU_RING_TYPE_COMPUTE: | |
2299 | timeout = adev->compute_timeout; | |
2300 | break; | |
2301 | case AMDGPU_RING_TYPE_SDMA: | |
2302 | timeout = adev->sdma_timeout; | |
2303 | break; | |
2304 | default: | |
2305 | timeout = adev->video_timeout; | |
2306 | break; | |
2307 | } | |
2308 | ||
2309 | r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, | |
11f25c84 | 2310 | ring->num_hw_submission, 0, |
8ab62eda JG |
2311 | timeout, adev->reset_domain->wq, |
2312 | ring->sched_score, ring->name, | |
2313 | adev->dev); | |
5fd8518d AG |
2314 | if (r) { |
2315 | DRM_ERROR("Failed to create scheduler on ring %s.\n", | |
2316 | ring->name); | |
2317 | return r; | |
2318 | } | |
2319 | } | |
2320 | ||
d425c6f4 JZ |
2321 | amdgpu_xcp_update_partition_sched_list(adev); |
2322 | ||
5fd8518d AG |
2323 | return 0; |
2324 | } | |
2325 | ||
2326 | ||
e3ecdffa AD |
2327 | /** |
2328 | * amdgpu_device_ip_init - run init for hardware IPs | |
2329 | * | |
2330 | * @adev: amdgpu_device pointer | |
2331 | * | |
2332 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2333 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2334 | * are run. sw_init initializes the software state associated with each IP | |
2335 | * and hw_init initializes the hardware associated with each IP. | |
2336 | * Returns 0 on success, negative error code on failure. | |
2337 | */ | |
06ec9070 | 2338 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2339 | { |
2340 | int i, r; | |
2341 | ||
c030f2e4 | 2342 | r = amdgpu_ras_init(adev); |
2343 | if (r) | |
2344 | return r; | |
2345 | ||
d38ceaf9 | 2346 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2347 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2348 | continue; |
a1255107 | 2349 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2350 | if (r) { |
a1255107 AD |
2351 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2352 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2353 | goto init_failed; |
2c1a2784 | 2354 | } |
a1255107 | 2355 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2356 | |
c1c39032 AD |
2357 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { |
2358 | /* need to do common hw init early so everything is set up for gmc */ | |
2359 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); | |
2360 | if (r) { | |
2361 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
2362 | goto init_failed; | |
2363 | } | |
2364 | adev->ip_blocks[i].status.hw = true; | |
2365 | } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
2366 | /* need to do gmc hw init early so we can allocate gpu mem */ | |
892deb48 VS |
2367 | /* Try to reserve bad pages early */ |
2368 | if (amdgpu_sriov_vf(adev)) | |
2369 | amdgpu_virt_exchange_data(adev); | |
2370 | ||
7ccfd79f | 2371 | r = amdgpu_device_mem_scratch_init(adev); |
2c1a2784 | 2372 | if (r) { |
7ccfd79f | 2373 | DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r); |
72d3f592 | 2374 | goto init_failed; |
2c1a2784 | 2375 | } |
a1255107 | 2376 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2377 | if (r) { |
2378 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2379 | goto init_failed; |
2c1a2784 | 2380 | } |
06ec9070 | 2381 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2382 | if (r) { |
06ec9070 | 2383 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2384 | goto init_failed; |
2c1a2784 | 2385 | } |
a1255107 | 2386 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2387 | |
2388 | /* right after GMC hw init, we create CSA */ | |
02ff519e | 2389 | if (adev->gfx.mcbp) { |
1e256e27 | 2390 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
58ab2c08 CK |
2391 | AMDGPU_GEM_DOMAIN_VRAM | |
2392 | AMDGPU_GEM_DOMAIN_GTT, | |
2393 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2394 | if (r) { |
2395 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2396 | goto init_failed; |
2493664f ML |
2397 | } |
2398 | } | |
d38ceaf9 AD |
2399 | } |
2400 | } | |
2401 | ||
c9ffa427 | 2402 | if (amdgpu_sriov_vf(adev)) |
22c16d25 | 2403 | amdgpu_virt_init_data_exchange(adev); |
c9ffa427 | 2404 | |
533aed27 AG |
2405 | r = amdgpu_ib_pool_init(adev); |
2406 | if (r) { | |
2407 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2408 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2409 | goto init_failed; | |
2410 | } | |
2411 | ||
c8963ea4 RZ |
2412 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2413 | if (r) | |
72d3f592 | 2414 | goto init_failed; |
0a4f2520 RZ |
2415 | |
2416 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2417 | if (r) | |
72d3f592 | 2418 | goto init_failed; |
0a4f2520 | 2419 | |
7a3e0bb2 RZ |
2420 | r = amdgpu_device_fw_loading(adev); |
2421 | if (r) | |
72d3f592 | 2422 | goto init_failed; |
7a3e0bb2 | 2423 | |
0a4f2520 RZ |
2424 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2425 | if (r) | |
72d3f592 | 2426 | goto init_failed; |
d38ceaf9 | 2427 | |
121a2bc6 AG |
2428 | /* |
2429 | * retired pages will be loaded from eeprom and reserved here, | |
2430 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2431 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2432 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2433 | * |
2434 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2435 | * failure from bad gpu situation and stop amdgpu init process | |
2436 | * accordingly. For other failed cases, it will still release all | |
2437 | * the resource and print error message, rather than returning one | |
2438 | * negative value to upper level. | |
121a2bc6 AG |
2439 | * |
2440 | * Note: theoretically, this should be called before all vram allocations | |
2441 | * to protect retired page from abusing | |
2442 | */ | |
b82e65a9 GC |
2443 | r = amdgpu_ras_recovery_init(adev); |
2444 | if (r) | |
2445 | goto init_failed; | |
121a2bc6 | 2446 | |
cfbb6b00 AG |
2447 | /** |
2448 | * In case of XGMI grab extra reference for reset domain for this device | |
2449 | */ | |
a4c63caf | 2450 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
cfbb6b00 | 2451 | if (amdgpu_xgmi_add_device(adev) == 0) { |
46c67660 | 2452 | if (!amdgpu_sriov_vf(adev)) { |
2efc30f0 VC |
2453 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
2454 | ||
dfd0287b LH |
2455 | if (WARN_ON(!hive)) { |
2456 | r = -ENOENT; | |
2457 | goto init_failed; | |
2458 | } | |
2459 | ||
46c67660 | 2460 | if (!hive->reset_domain || |
2461 | !amdgpu_reset_get_reset_domain(hive->reset_domain)) { | |
2462 | r = -ENOENT; | |
2463 | amdgpu_put_xgmi_hive(hive); | |
2464 | goto init_failed; | |
2465 | } | |
2466 | ||
2467 | /* Drop the early temporary reset domain we created for device */ | |
2468 | amdgpu_reset_put_reset_domain(adev->reset_domain); | |
2469 | adev->reset_domain = hive->reset_domain; | |
9dfa4860 | 2470 | amdgpu_put_xgmi_hive(hive); |
cfbb6b00 | 2471 | } |
a4c63caf AG |
2472 | } |
2473 | } | |
2474 | ||
5fd8518d AG |
2475 | r = amdgpu_device_init_schedulers(adev); |
2476 | if (r) | |
2477 | goto init_failed; | |
e3c1b071 | 2478 | |
2479 | /* Don't init kfd if whole hive need to be reset during init */ | |
84b4dd3f PY |
2480 | if (!adev->gmc.xgmi.pending_reset) { |
2481 | kgd2kfd_init_zone_device(adev); | |
e3c1b071 | 2482 | amdgpu_amdkfd_device_init(adev); |
84b4dd3f | 2483 | } |
c6332b97 | 2484 | |
bd607166 KR |
2485 | amdgpu_fru_get_product_info(adev); |
2486 | ||
72d3f592 | 2487 | init_failed: |
c6332b97 | 2488 | |
72d3f592 | 2489 | return r; |
d38ceaf9 AD |
2490 | } |
2491 | ||
e3ecdffa AD |
2492 | /** |
2493 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2494 | * | |
2495 | * @adev: amdgpu_device pointer | |
2496 | * | |
2497 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2498 | * this function before a GPU reset. If the value is retained after a | |
2499 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2500 | */ | |
06ec9070 | 2501 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2502 | { |
2503 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2504 | } | |
2505 | ||
e3ecdffa AD |
2506 | /** |
2507 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2508 | * | |
2509 | * @adev: amdgpu_device pointer | |
2510 | * | |
2511 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2512 | * The driver calls this after a GPU reset to see if the contents of | |
2513 | * VRAM is lost or now. | |
2514 | * returns true if vram is lost, false if not. | |
2515 | */ | |
06ec9070 | 2516 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2517 | { |
dadce777 EQ |
2518 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2519 | AMDGPU_RESET_MAGIC_NUM)) | |
2520 | return true; | |
2521 | ||
53b3f8f4 | 2522 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2523 | return false; |
2524 | ||
2525 | /* | |
2526 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2527 | * always assumed to be lost. | |
2528 | */ | |
2529 | switch (amdgpu_asic_reset_method(adev)) { | |
2530 | case AMD_RESET_METHOD_BACO: | |
2531 | case AMD_RESET_METHOD_MODE1: | |
2532 | return true; | |
2533 | default: | |
2534 | return false; | |
2535 | } | |
0c49e0b8 CZ |
2536 | } |
2537 | ||
e3ecdffa | 2538 | /** |
1112a46b | 2539 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2540 | * |
2541 | * @adev: amdgpu_device pointer | |
b8b72130 | 2542 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2543 | * |
e3ecdffa | 2544 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2545 | * set_clockgating_state callbacks are run. |
2546 | * Late initialization pass enabling clockgating for hardware IPs. | |
2547 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2548 | * Returns 0 on success, negative error code on failure. |
2549 | */ | |
fdd34271 | 2550 | |
5d89bb2d LL |
2551 | int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2552 | enum amd_clockgating_state state) | |
d38ceaf9 | 2553 | { |
1112a46b | 2554 | int i, j, r; |
d38ceaf9 | 2555 | |
4a2ba394 SL |
2556 | if (amdgpu_emu_mode == 1) |
2557 | return 0; | |
2558 | ||
1112a46b RZ |
2559 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2560 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2561 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2562 | continue; |
47198eb7 | 2563 | /* skip CG for GFX, SDMA on S0ix */ |
5d70a549 | 2564 | if (adev->in_s0ix && |
47198eb7 AD |
2565 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || |
2566 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) | |
5d70a549 | 2567 | continue; |
4a446d55 | 2568 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2569 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2570 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2571 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2572 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2573 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2574 | /* enable clockgating to save power */ |
a1255107 | 2575 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2576 | state); |
4a446d55 AD |
2577 | if (r) { |
2578 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2579 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2580 | return r; |
2581 | } | |
b0b00ff1 | 2582 | } |
d38ceaf9 | 2583 | } |
06b18f61 | 2584 | |
c9f96fd5 RZ |
2585 | return 0; |
2586 | } | |
2587 | ||
5d89bb2d LL |
2588 | int amdgpu_device_set_pg_state(struct amdgpu_device *adev, |
2589 | enum amd_powergating_state state) | |
c9f96fd5 | 2590 | { |
1112a46b | 2591 | int i, j, r; |
06b18f61 | 2592 | |
c9f96fd5 RZ |
2593 | if (amdgpu_emu_mode == 1) |
2594 | return 0; | |
2595 | ||
1112a46b RZ |
2596 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2597 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2598 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 | 2599 | continue; |
47198eb7 | 2600 | /* skip PG for GFX, SDMA on S0ix */ |
5d70a549 | 2601 | if (adev->in_s0ix && |
47198eb7 AD |
2602 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || |
2603 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) | |
5d70a549 | 2604 | continue; |
c9f96fd5 RZ |
2605 | /* skip CG for VCE/UVD, it's handled specially */ |
2606 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2607 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2608 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2609 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2610 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2611 | /* enable powergating to save power */ | |
2612 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2613 | state); |
c9f96fd5 RZ |
2614 | if (r) { |
2615 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2616 | adev->ip_blocks[i].version->funcs->name, r); | |
2617 | return r; | |
2618 | } | |
2619 | } | |
2620 | } | |
2dc80b00 S |
2621 | return 0; |
2622 | } | |
2623 | ||
beff74bc AD |
2624 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2625 | { | |
2626 | struct amdgpu_gpu_instance *gpu_ins; | |
2627 | struct amdgpu_device *adev; | |
2628 | int i, ret = 0; | |
2629 | ||
2630 | mutex_lock(&mgpu_info.mutex); | |
2631 | ||
2632 | /* | |
2633 | * MGPU fan boost feature should be enabled | |
2634 | * only when there are two or more dGPUs in | |
2635 | * the system | |
2636 | */ | |
2637 | if (mgpu_info.num_dgpu < 2) | |
2638 | goto out; | |
2639 | ||
2640 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2641 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2642 | adev = gpu_ins->adev; | |
2643 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2644 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2645 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2646 | if (ret) | |
2647 | break; | |
2648 | ||
2649 | gpu_ins->mgpu_fan_enabled = 1; | |
2650 | } | |
2651 | } | |
2652 | ||
2653 | out: | |
2654 | mutex_unlock(&mgpu_info.mutex); | |
2655 | ||
2656 | return ret; | |
2657 | } | |
2658 | ||
e3ecdffa AD |
2659 | /** |
2660 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2661 | * | |
2662 | * @adev: amdgpu_device pointer | |
2663 | * | |
2664 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2665 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2666 | * late_init covers any special initialization that an IP requires | |
2667 | * after all of the have been initialized or something that needs to happen | |
2668 | * late in the init process. | |
2669 | * Returns 0 on success, negative error code on failure. | |
2670 | */ | |
06ec9070 | 2671 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2672 | { |
60599a03 | 2673 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2674 | int i = 0, r; |
2675 | ||
2676 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2677 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2678 | continue; |
2679 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2680 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2681 | if (r) { | |
2682 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2683 | adev->ip_blocks[i].version->funcs->name, r); | |
2684 | return r; | |
2685 | } | |
2dc80b00 | 2686 | } |
73f847db | 2687 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2688 | } |
2689 | ||
867e24ca | 2690 | r = amdgpu_ras_late_init(adev); |
2691 | if (r) { | |
2692 | DRM_ERROR("amdgpu_ras_late_init failed %d", r); | |
2693 | return r; | |
2694 | } | |
2695 | ||
a891d239 DL |
2696 | amdgpu_ras_set_error_query_ready(adev, true); |
2697 | ||
1112a46b RZ |
2698 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2699 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2700 | |
06ec9070 | 2701 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2702 | |
beff74bc AD |
2703 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2704 | if (r) | |
2705 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2706 | ||
4da8b639 | 2707 | /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */ |
47fc644f SS |
2708 | if (amdgpu_passthrough(adev) && |
2709 | ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) || | |
2710 | adev->asic_type == CHIP_ALDEBARAN)) | |
bc143d8b | 2711 | amdgpu_dpm_handle_passthrough_sbr(adev, true); |
60599a03 EQ |
2712 | |
2713 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2714 | mutex_lock(&mgpu_info.mutex); | |
2715 | ||
2716 | /* | |
2717 | * Reset device p-state to low as this was booted with high. | |
2718 | * | |
2719 | * This should be performed only after all devices from the same | |
2720 | * hive get initialized. | |
2721 | * | |
2722 | * However, it's unknown how many device in the hive in advance. | |
2723 | * As this is counted one by one during devices initializations. | |
2724 | * | |
2725 | * So, we wait for all XGMI interlinked devices initialized. | |
2726 | * This may bring some delays as those devices may come from | |
2727 | * different hives. But that should be OK. | |
2728 | */ | |
2729 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2730 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2731 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2732 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2733 | continue; | |
2734 | ||
d84a430d JK |
2735 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2736 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2737 | if (r) { |
2738 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2739 | break; | |
2740 | } | |
2741 | } | |
2742 | } | |
2743 | ||
2744 | mutex_unlock(&mgpu_info.mutex); | |
2745 | } | |
2746 | ||
d38ceaf9 AD |
2747 | return 0; |
2748 | } | |
2749 | ||
613aa3ea LY |
2750 | /** |
2751 | * amdgpu_device_smu_fini_early - smu hw_fini wrapper | |
2752 | * | |
2753 | * @adev: amdgpu_device pointer | |
2754 | * | |
2755 | * For ASICs need to disable SMC first | |
2756 | */ | |
2757 | static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev) | |
2758 | { | |
2759 | int i, r; | |
2760 | ||
2761 | if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)) | |
2762 | return; | |
2763 | ||
2764 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2765 | if (!adev->ip_blocks[i].status.hw) | |
2766 | continue; | |
2767 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2768 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); | |
2769 | /* XXX handle errors */ | |
2770 | if (r) { | |
2771 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
2772 | adev->ip_blocks[i].version->funcs->name, r); | |
2773 | } | |
2774 | adev->ip_blocks[i].status.hw = false; | |
2775 | break; | |
2776 | } | |
2777 | } | |
2778 | } | |
2779 | ||
e9669fb7 | 2780 | static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) |
d38ceaf9 AD |
2781 | { |
2782 | int i, r; | |
2783 | ||
e9669fb7 AG |
2784 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2785 | if (!adev->ip_blocks[i].version->funcs->early_fini) | |
2786 | continue; | |
5278a159 | 2787 | |
e9669fb7 AG |
2788 | r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); |
2789 | if (r) { | |
2790 | DRM_DEBUG("early_fini of IP block <%s> failed %d\n", | |
2791 | adev->ip_blocks[i].version->funcs->name, r); | |
2792 | } | |
2793 | } | |
c030f2e4 | 2794 | |
05df1f01 | 2795 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
2796 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2797 | ||
7270e895 TY |
2798 | amdgpu_amdkfd_suspend(adev, false); |
2799 | ||
613aa3ea LY |
2800 | /* Workaroud for ASICs need to disable SMC first */ |
2801 | amdgpu_device_smu_fini_early(adev); | |
3e96dbfd | 2802 | |
d38ceaf9 | 2803 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2804 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2805 | continue; |
8201a67a | 2806 | |
a1255107 | 2807 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2808 | /* XXX handle errors */ |
2c1a2784 | 2809 | if (r) { |
a1255107 AD |
2810 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2811 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2812 | } |
8201a67a | 2813 | |
a1255107 | 2814 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2815 | } |
2816 | ||
6effad8a GC |
2817 | if (amdgpu_sriov_vf(adev)) { |
2818 | if (amdgpu_virt_release_full_gpu(adev, false)) | |
2819 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2820 | } | |
2821 | ||
e9669fb7 AG |
2822 | return 0; |
2823 | } | |
2824 | ||
2825 | /** | |
2826 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2827 | * | |
2828 | * @adev: amdgpu_device pointer | |
2829 | * | |
2830 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2831 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2832 | * are run. hw_fini tears down the hardware associated with each IP | |
2833 | * and sw_fini tears down any software state associated with each IP. | |
2834 | * Returns 0 on success, negative error code on failure. | |
2835 | */ | |
2836 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |
2837 | { | |
2838 | int i, r; | |
2839 | ||
2840 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) | |
2841 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2842 | ||
e9669fb7 AG |
2843 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2844 | amdgpu_xgmi_remove_device(adev); | |
2845 | ||
c004d44e | 2846 | amdgpu_amdkfd_device_fini_sw(adev); |
9950cda2 | 2847 | |
d38ceaf9 | 2848 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2849 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2850 | continue; |
c12aba3a ML |
2851 | |
2852 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2853 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2854 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a | 2855 | amdgpu_device_wb_fini(adev); |
7ccfd79f | 2856 | amdgpu_device_mem_scratch_fini(adev); |
533aed27 | 2857 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2858 | } |
2859 | ||
a1255107 | 2860 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2861 | /* XXX handle errors */ |
2c1a2784 | 2862 | if (r) { |
a1255107 AD |
2863 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2864 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2865 | } |
a1255107 AD |
2866 | adev->ip_blocks[i].status.sw = false; |
2867 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2868 | } |
2869 | ||
a6dcfd9c | 2870 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2871 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2872 | continue; |
a1255107 AD |
2873 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2874 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2875 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2876 | } |
2877 | ||
c030f2e4 | 2878 | amdgpu_ras_fini(adev); |
2879 | ||
d38ceaf9 AD |
2880 | return 0; |
2881 | } | |
2882 | ||
e3ecdffa | 2883 | /** |
beff74bc | 2884 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2885 | * |
1112a46b | 2886 | * @work: work_struct. |
e3ecdffa | 2887 | */ |
beff74bc | 2888 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2889 | { |
2890 | struct amdgpu_device *adev = | |
beff74bc | 2891 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2892 | int r; |
2893 | ||
2894 | r = amdgpu_ib_ring_tests(adev); | |
2895 | if (r) | |
2896 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2897 | } |
2898 | ||
1e317b99 RZ |
2899 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2900 | { | |
2901 | struct amdgpu_device *adev = | |
2902 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2903 | ||
90a92662 MD |
2904 | WARN_ON_ONCE(adev->gfx.gfx_off_state); |
2905 | WARN_ON_ONCE(adev->gfx.gfx_off_req_count); | |
2906 | ||
2907 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2908 | adev->gfx.gfx_off_state = true; | |
1e317b99 RZ |
2909 | } |
2910 | ||
e3ecdffa | 2911 | /** |
e7854a03 | 2912 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2913 | * |
2914 | * @adev: amdgpu_device pointer | |
2915 | * | |
2916 | * Main suspend function for hardware IPs. The list of all the hardware | |
2917 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2918 | * suspend callbacks are run. suspend puts the hardware and software state | |
2919 | * in each IP into a state suitable for suspend. | |
2920 | * Returns 0 on success, negative error code on failure. | |
2921 | */ | |
e7854a03 AD |
2922 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2923 | { | |
2924 | int i, r; | |
2925 | ||
50ec83f0 AD |
2926 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2927 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2928 | |
b31d6ada EQ |
2929 | /* |
2930 | * Per PMFW team's suggestion, driver needs to handle gfxoff | |
2931 | * and df cstate features disablement for gpu reset(e.g. Mode1Reset) | |
2932 | * scenario. Add the missing df cstate disablement here. | |
2933 | */ | |
2934 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
2935 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
2936 | ||
e7854a03 AD |
2937 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2938 | if (!adev->ip_blocks[i].status.valid) | |
2939 | continue; | |
2b9f7848 | 2940 | |
e7854a03 | 2941 | /* displays are handled separately */ |
2b9f7848 ND |
2942 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2943 | continue; | |
2944 | ||
2945 | /* XXX handle errors */ | |
2946 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2947 | /* XXX handle errors */ | |
2948 | if (r) { | |
2949 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2950 | adev->ip_blocks[i].version->funcs->name, r); | |
2951 | return r; | |
e7854a03 | 2952 | } |
2b9f7848 ND |
2953 | |
2954 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2955 | } |
2956 | ||
e7854a03 AD |
2957 | return 0; |
2958 | } | |
2959 | ||
2960 | /** | |
2961 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2962 | * | |
2963 | * @adev: amdgpu_device pointer | |
2964 | * | |
2965 | * Main suspend function for hardware IPs. The list of all the hardware | |
2966 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2967 | * suspend callbacks are run. suspend puts the hardware and software state | |
2968 | * in each IP into a state suitable for suspend. | |
2969 | * Returns 0 on success, negative error code on failure. | |
2970 | */ | |
2971 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2972 | { |
2973 | int i, r; | |
2974 | ||
557f42a2 | 2975 | if (adev->in_s0ix) |
bc143d8b | 2976 | amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry); |
34416931 | 2977 | |
d38ceaf9 | 2978 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2979 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2980 | continue; |
e7854a03 AD |
2981 | /* displays are handled in phase1 */ |
2982 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2983 | continue; | |
bff77e86 LM |
2984 | /* PSP lost connection when err_event_athub occurs */ |
2985 | if (amdgpu_ras_intr_triggered() && | |
2986 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2987 | adev->ip_blocks[i].status.hw = false; | |
2988 | continue; | |
2989 | } | |
e3c1b071 | 2990 | |
2991 | /* skip unnecessary suspend if we do not initialize them yet */ | |
2992 | if (adev->gmc.xgmi.pending_reset && | |
2993 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2994 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
2995 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2996 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
2997 | adev->ip_blocks[i].status.hw = false; | |
2998 | continue; | |
2999 | } | |
557f42a2 | 3000 | |
afa6646b | 3001 | /* skip suspend of gfx/mes and psp for S0ix |
32ff160d AD |
3002 | * gfx is in gfxoff state, so on resume it will exit gfxoff just |
3003 | * like at runtime. PSP is also part of the always on hardware | |
3004 | * so no need to suspend it. | |
3005 | */ | |
557f42a2 | 3006 | if (adev->in_s0ix && |
32ff160d | 3007 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || |
afa6646b AD |
3008 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || |
3009 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES)) | |
557f42a2 AD |
3010 | continue; |
3011 | ||
2a7798ea AD |
3012 | /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */ |
3013 | if (adev->in_s0ix && | |
3014 | (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) && | |
3015 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) | |
3016 | continue; | |
3017 | ||
e11c7750 TH |
3018 | /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot. |
3019 | * These are in TMR, hence are expected to be reused by PSP-TOS to reload | |
3020 | * from this location and RLC Autoload automatically also gets loaded | |
3021 | * from here based on PMFW -> PSP message during re-init sequence. | |
3022 | * Therefore, the psp suspend & resume should be skipped to avoid destroy | |
3023 | * the TMR and reload FWs again for IMU enabled APU ASICs. | |
3024 | */ | |
3025 | if (amdgpu_in_reset(adev) && | |
3026 | (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs && | |
3027 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
3028 | continue; | |
3029 | ||
d38ceaf9 | 3030 | /* XXX handle errors */ |
a1255107 | 3031 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 3032 | /* XXX handle errors */ |
2c1a2784 | 3033 | if (r) { |
a1255107 AD |
3034 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
3035 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 3036 | } |
876923fb | 3037 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 3038 | /* handle putting the SMC in the appropriate state */ |
47fc644f | 3039 | if (!amdgpu_sriov_vf(adev)) { |
86b93fd6 JZ |
3040 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3041 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
3042 | if (r) { | |
3043 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
3044 | adev->mp1_state, r); | |
3045 | return r; | |
3046 | } | |
a3a09142 AD |
3047 | } |
3048 | } | |
d38ceaf9 AD |
3049 | } |
3050 | ||
3051 | return 0; | |
3052 | } | |
3053 | ||
e7854a03 AD |
3054 | /** |
3055 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
3056 | * | |
3057 | * @adev: amdgpu_device pointer | |
3058 | * | |
3059 | * Main suspend function for hardware IPs. The list of all the hardware | |
3060 | * IPs that make up the asic is walked, clockgating is disabled and the | |
3061 | * suspend callbacks are run. suspend puts the hardware and software state | |
3062 | * in each IP into a state suitable for suspend. | |
3063 | * Returns 0 on success, negative error code on failure. | |
3064 | */ | |
3065 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
3066 | { | |
3067 | int r; | |
3068 | ||
3c73683c JC |
3069 | if (amdgpu_sriov_vf(adev)) { |
3070 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 3071 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 3072 | } |
e7819644 | 3073 | |
e7854a03 AD |
3074 | r = amdgpu_device_ip_suspend_phase1(adev); |
3075 | if (r) | |
3076 | return r; | |
3077 | r = amdgpu_device_ip_suspend_phase2(adev); | |
3078 | ||
e7819644 YT |
3079 | if (amdgpu_sriov_vf(adev)) |
3080 | amdgpu_virt_release_full_gpu(adev, false); | |
3081 | ||
e7854a03 AD |
3082 | return r; |
3083 | } | |
3084 | ||
06ec9070 | 3085 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3086 | { |
3087 | int i, r; | |
3088 | ||
2cb681b6 | 3089 | static enum amd_ip_block_type ip_order[] = { |
2cb681b6 | 3090 | AMD_IP_BLOCK_TYPE_COMMON, |
c1c39032 | 3091 | AMD_IP_BLOCK_TYPE_GMC, |
39186aef | 3092 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
3093 | AMD_IP_BLOCK_TYPE_IH, |
3094 | }; | |
a90ad3c2 | 3095 | |
95ea3dbc | 3096 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2cb681b6 ML |
3097 | int j; |
3098 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3099 | |
4cd2a96d J |
3100 | block = &adev->ip_blocks[i]; |
3101 | block->status.hw = false; | |
2cb681b6 | 3102 | |
4cd2a96d | 3103 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 3104 | |
4cd2a96d | 3105 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
3106 | !block->status.valid) |
3107 | continue; | |
3108 | ||
3109 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 3110 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3111 | if (r) |
3112 | return r; | |
482f0e53 | 3113 | block->status.hw = true; |
a90ad3c2 ML |
3114 | } |
3115 | } | |
3116 | ||
3117 | return 0; | |
3118 | } | |
3119 | ||
06ec9070 | 3120 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3121 | { |
3122 | int i, r; | |
3123 | ||
2cb681b6 ML |
3124 | static enum amd_ip_block_type ip_order[] = { |
3125 | AMD_IP_BLOCK_TYPE_SMC, | |
3126 | AMD_IP_BLOCK_TYPE_DCE, | |
3127 | AMD_IP_BLOCK_TYPE_GFX, | |
3128 | AMD_IP_BLOCK_TYPE_SDMA, | |
ec64350d | 3129 | AMD_IP_BLOCK_TYPE_MES, |
257deb8c | 3130 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 | 3131 | AMD_IP_BLOCK_TYPE_VCE, |
d2cdc014 YZ |
3132 | AMD_IP_BLOCK_TYPE_VCN, |
3133 | AMD_IP_BLOCK_TYPE_JPEG | |
2cb681b6 | 3134 | }; |
a90ad3c2 | 3135 | |
2cb681b6 ML |
3136 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
3137 | int j; | |
3138 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3139 | |
2cb681b6 ML |
3140 | for (j = 0; j < adev->num_ip_blocks; j++) { |
3141 | block = &adev->ip_blocks[j]; | |
3142 | ||
3143 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
3144 | !block->status.valid || |
3145 | block->status.hw) | |
2cb681b6 ML |
3146 | continue; |
3147 | ||
895bd048 JZ |
3148 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
3149 | r = block->version->funcs->resume(adev); | |
3150 | else | |
3151 | r = block->version->funcs->hw_init(adev); | |
3152 | ||
0aaeefcc | 3153 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3154 | if (r) |
3155 | return r; | |
482f0e53 | 3156 | block->status.hw = true; |
a90ad3c2 ML |
3157 | } |
3158 | } | |
3159 | ||
3160 | return 0; | |
3161 | } | |
3162 | ||
e3ecdffa AD |
3163 | /** |
3164 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
3165 | * | |
3166 | * @adev: amdgpu_device pointer | |
3167 | * | |
3168 | * First resume function for hardware IPs. The list of all the hardware | |
3169 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3170 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
3171 | * after a suspend and updates the software state as necessary. This | |
3172 | * function is also used for restoring the GPU after a GPU reset. | |
3173 | * Returns 0 on success, negative error code on failure. | |
3174 | */ | |
06ec9070 | 3175 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
3176 | { |
3177 | int i, r; | |
3178 | ||
a90ad3c2 | 3179 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 3180 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 3181 | continue; |
a90ad3c2 | 3182 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3183 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
d7274ec7 BZ |
3184 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3185 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) { | |
482f0e53 | 3186 | |
fcf0649f CZ |
3187 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
3188 | if (r) { | |
3189 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
3190 | adev->ip_blocks[i].version->funcs->name, r); | |
3191 | return r; | |
3192 | } | |
482f0e53 | 3193 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
3194 | } |
3195 | } | |
3196 | ||
3197 | return 0; | |
3198 | } | |
3199 | ||
e3ecdffa AD |
3200 | /** |
3201 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
3202 | * | |
3203 | * @adev: amdgpu_device pointer | |
3204 | * | |
3205 | * First resume function for hardware IPs. The list of all the hardware | |
3206 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3207 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
3208 | * functional state after a suspend and updates the software state as | |
3209 | * necessary. This function is also used for restoring the GPU after a GPU | |
3210 | * reset. | |
3211 | * Returns 0 on success, negative error code on failure. | |
3212 | */ | |
06ec9070 | 3213 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
3214 | { |
3215 | int i, r; | |
3216 | ||
3217 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 3218 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 3219 | continue; |
fcf0649f | 3220 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3221 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
3222 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3223 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 3224 | continue; |
a1255107 | 3225 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 3226 | if (r) { |
a1255107 AD |
3227 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
3228 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 3229 | return r; |
2c1a2784 | 3230 | } |
482f0e53 | 3231 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
3232 | } |
3233 | ||
3234 | return 0; | |
3235 | } | |
3236 | ||
e3ecdffa AD |
3237 | /** |
3238 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
3239 | * | |
3240 | * @adev: amdgpu_device pointer | |
3241 | * | |
3242 | * Main resume function for hardware IPs. The hardware IPs | |
3243 | * are split into two resume functions because they are | |
b8920e1e | 3244 | * also used in recovering from a GPU reset and some additional |
e3ecdffa AD |
3245 | * steps need to be take between them. In this case (S3/S4) they are |
3246 | * run sequentially. | |
3247 | * Returns 0 on success, negative error code on failure. | |
3248 | */ | |
06ec9070 | 3249 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
3250 | { |
3251 | int r; | |
3252 | ||
06ec9070 | 3253 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
3254 | if (r) |
3255 | return r; | |
7a3e0bb2 RZ |
3256 | |
3257 | r = amdgpu_device_fw_loading(adev); | |
3258 | if (r) | |
3259 | return r; | |
3260 | ||
06ec9070 | 3261 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
3262 | |
3263 | return r; | |
3264 | } | |
3265 | ||
e3ecdffa AD |
3266 | /** |
3267 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
3268 | * | |
3269 | * @adev: amdgpu_device pointer | |
3270 | * | |
3271 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
3272 | */ | |
4e99a44e | 3273 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 3274 | { |
6867e1b5 ML |
3275 | if (amdgpu_sriov_vf(adev)) { |
3276 | if (adev->is_atom_fw) { | |
58ff791a | 3277 | if (amdgpu_atomfirmware_gpu_virtualization_supported(adev)) |
6867e1b5 ML |
3278 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; |
3279 | } else { | |
3280 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3281 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3282 | } | |
3283 | ||
3284 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3285 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3286 | } |
048765ad AR |
3287 | } |
3288 | ||
e3ecdffa AD |
3289 | /** |
3290 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3291 | * | |
3292 | * @asic_type: AMD asic type | |
3293 | * | |
3294 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3295 | * returns true if DC has support, false if not. | |
3296 | */ | |
4562236b HW |
3297 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3298 | { | |
3299 | switch (asic_type) { | |
0637d417 AD |
3300 | #ifdef CONFIG_DRM_AMDGPU_SI |
3301 | case CHIP_HAINAN: | |
3302 | #endif | |
3303 | case CHIP_TOPAZ: | |
3304 | /* chips with no display hardware */ | |
3305 | return false; | |
4562236b | 3306 | #if defined(CONFIG_DRM_AMD_DC) |
64200c46 MR |
3307 | case CHIP_TAHITI: |
3308 | case CHIP_PITCAIRN: | |
3309 | case CHIP_VERDE: | |
3310 | case CHIP_OLAND: | |
2d32ffd6 AD |
3311 | /* |
3312 | * We have systems in the wild with these ASICs that require | |
3313 | * LVDS and VGA support which is not supported with DC. | |
3314 | * | |
3315 | * Fallback to the non-DC driver here by default so as not to | |
3316 | * cause regressions. | |
3317 | */ | |
3318 | #if defined(CONFIG_DRM_AMD_DC_SI) | |
3319 | return amdgpu_dc > 0; | |
3320 | #else | |
3321 | return false; | |
64200c46 | 3322 | #endif |
4562236b | 3323 | case CHIP_BONAIRE: |
0d6fbccb | 3324 | case CHIP_KAVERI: |
367e6687 AD |
3325 | case CHIP_KABINI: |
3326 | case CHIP_MULLINS: | |
d9fda248 HW |
3327 | /* |
3328 | * We have systems in the wild with these ASICs that require | |
b5a0168e | 3329 | * VGA support which is not supported with DC. |
d9fda248 HW |
3330 | * |
3331 | * Fallback to the non-DC driver here by default so as not to | |
3332 | * cause regressions. | |
3333 | */ | |
3334 | return amdgpu_dc > 0; | |
f7f12b25 | 3335 | default: |
fd187853 | 3336 | return amdgpu_dc != 0; |
f7f12b25 | 3337 | #else |
4562236b | 3338 | default: |
93b09a9a | 3339 | if (amdgpu_dc > 0) |
b8920e1e | 3340 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n"); |
4562236b | 3341 | return false; |
f7f12b25 | 3342 | #endif |
4562236b HW |
3343 | } |
3344 | } | |
3345 | ||
3346 | /** | |
3347 | * amdgpu_device_has_dc_support - check if dc is supported | |
3348 | * | |
982a820b | 3349 | * @adev: amdgpu_device pointer |
4562236b HW |
3350 | * |
3351 | * Returns true for supported, false for not supported | |
3352 | */ | |
3353 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3354 | { | |
25263da3 | 3355 | if (adev->enable_virtual_display || |
abaf210c | 3356 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) |
2555039d XY |
3357 | return false; |
3358 | ||
4562236b HW |
3359 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3360 | } | |
3361 | ||
d4535e2c AG |
3362 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) |
3363 | { | |
3364 | struct amdgpu_device *adev = | |
3365 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3366 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3367 | |
c6a6e2db AG |
3368 | /* It's a bug to not have a hive within this function */ |
3369 | if (WARN_ON(!hive)) | |
3370 | return; | |
3371 | ||
3372 | /* | |
3373 | * Use task barrier to synchronize all xgmi reset works across the | |
3374 | * hive. task_barrier_enter and task_barrier_exit will block | |
3375 | * until all the threads running the xgmi reset works reach | |
3376 | * those points. task_barrier_full will do both blocks. | |
3377 | */ | |
3378 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3379 | ||
3380 | task_barrier_enter(&hive->tb); | |
4a580877 | 3381 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3382 | |
3383 | if (adev->asic_reset_res) | |
3384 | goto fail; | |
3385 | ||
3386 | task_barrier_exit(&hive->tb); | |
4a580877 | 3387 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3388 | |
3389 | if (adev->asic_reset_res) | |
3390 | goto fail; | |
43c4d576 | 3391 | |
5e67bba3 | 3392 | if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && |
3393 | adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) | |
3394 | adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); | |
c6a6e2db AG |
3395 | } else { |
3396 | ||
3397 | task_barrier_full(&hive->tb); | |
3398 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3399 | } | |
ce316fa5 | 3400 | |
c6a6e2db | 3401 | fail: |
d4535e2c | 3402 | if (adev->asic_reset_res) |
fed184e9 | 3403 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3404 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3405 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3406 | } |
3407 | ||
71f98027 AD |
3408 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3409 | { | |
3410 | char *input = amdgpu_lockup_timeout; | |
3411 | char *timeout_setting = NULL; | |
3412 | int index = 0; | |
3413 | long timeout; | |
3414 | int ret = 0; | |
3415 | ||
3416 | /* | |
67387dfe AD |
3417 | * By default timeout for non compute jobs is 10000 |
3418 | * and 60000 for compute jobs. | |
71f98027 | 3419 | * In SR-IOV or passthrough mode, timeout for compute |
b7b2a316 | 3420 | * jobs are 60000 by default. |
71f98027 AD |
3421 | */ |
3422 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3423 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3424 | if (amdgpu_sriov_vf(adev)) |
3425 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3426 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
71f98027 | 3427 | else |
67387dfe | 3428 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 | 3429 | |
f440ff44 | 3430 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3431 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3432 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3433 | ret = kstrtol(timeout_setting, 0, &timeout); |
3434 | if (ret) | |
3435 | return ret; | |
3436 | ||
3437 | if (timeout == 0) { | |
3438 | index++; | |
3439 | continue; | |
3440 | } else if (timeout < 0) { | |
3441 | timeout = MAX_SCHEDULE_TIMEOUT; | |
127aedf9 CK |
3442 | dev_warn(adev->dev, "lockup timeout disabled"); |
3443 | add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK); | |
71f98027 AD |
3444 | } else { |
3445 | timeout = msecs_to_jiffies(timeout); | |
3446 | } | |
3447 | ||
3448 | switch (index++) { | |
3449 | case 0: | |
3450 | adev->gfx_timeout = timeout; | |
3451 | break; | |
3452 | case 1: | |
3453 | adev->compute_timeout = timeout; | |
3454 | break; | |
3455 | case 2: | |
3456 | adev->sdma_timeout = timeout; | |
3457 | break; | |
3458 | case 3: | |
3459 | adev->video_timeout = timeout; | |
3460 | break; | |
3461 | default: | |
3462 | break; | |
3463 | } | |
3464 | } | |
3465 | /* | |
3466 | * There is only one value specified and | |
3467 | * it should apply to all non-compute jobs. | |
3468 | */ | |
bcccee89 | 3469 | if (index == 1) { |
71f98027 | 3470 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3471 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3472 | adev->compute_timeout = adev->gfx_timeout; | |
3473 | } | |
71f98027 AD |
3474 | } |
3475 | ||
3476 | return ret; | |
3477 | } | |
d4535e2c | 3478 | |
4a74c38c PY |
3479 | /** |
3480 | * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU | |
3481 | * | |
3482 | * @adev: amdgpu_device pointer | |
3483 | * | |
3484 | * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode | |
3485 | */ | |
3486 | static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev) | |
3487 | { | |
3488 | struct iommu_domain *domain; | |
3489 | ||
3490 | domain = iommu_get_domain_for_dev(adev->dev); | |
3491 | if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY) | |
3492 | adev->ram_is_direct_mapped = true; | |
3493 | } | |
3494 | ||
77f3a5cd | 3495 | static const struct attribute *amdgpu_dev_attributes[] = { |
77f3a5cd ND |
3496 | &dev_attr_pcie_replay_count.attr, |
3497 | NULL | |
3498 | }; | |
3499 | ||
02ff519e AD |
3500 | static void amdgpu_device_set_mcbp(struct amdgpu_device *adev) |
3501 | { | |
3502 | if (amdgpu_mcbp == 1) | |
3503 | adev->gfx.mcbp = true; | |
1e9e15dc JZ |
3504 | else if (amdgpu_mcbp == 0) |
3505 | adev->gfx.mcbp = false; | |
3506 | else if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) && | |
3507 | (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) && | |
3508 | adev->gfx.num_gfx_rings) | |
50a7c876 AD |
3509 | adev->gfx.mcbp = true; |
3510 | ||
02ff519e AD |
3511 | if (amdgpu_sriov_vf(adev)) |
3512 | adev->gfx.mcbp = true; | |
3513 | ||
3514 | if (adev->gfx.mcbp) | |
3515 | DRM_INFO("MCBP is enabled\n"); | |
3516 | } | |
3517 | ||
d38ceaf9 AD |
3518 | /** |
3519 | * amdgpu_device_init - initialize the driver | |
3520 | * | |
3521 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3522 | * @flags: driver flags |
3523 | * | |
3524 | * Initializes the driver info and hw (all asics). | |
3525 | * Returns 0 for success or an error on failure. | |
3526 | * Called at driver startup. | |
3527 | */ | |
3528 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3529 | uint32_t flags) |
3530 | { | |
8aba21b7 LT |
3531 | struct drm_device *ddev = adev_to_drm(adev); |
3532 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3533 | int r, i; |
b98c6299 | 3534 | bool px = false; |
95844d20 | 3535 | u32 max_MBps; |
59e9fff1 | 3536 | int tmp; |
d38ceaf9 AD |
3537 | |
3538 | adev->shutdown = false; | |
d38ceaf9 | 3539 | adev->flags = flags; |
4e66d7d2 YZ |
3540 | |
3541 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3542 | adev->asic_type = amdgpu_force_asic_type; | |
3543 | else | |
3544 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3545 | ||
d38ceaf9 | 3546 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3547 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3548 | adev->usec_timeout *= 10; |
770d13b1 | 3549 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3550 | adev->accel_working = false; |
3551 | adev->num_rings = 0; | |
68ce8b24 | 3552 | RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub()); |
d38ceaf9 AD |
3553 | adev->mman.buffer_funcs = NULL; |
3554 | adev->mman.buffer_funcs_ring = NULL; | |
3555 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3556 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3557 | adev->gmc.gmc_funcs = NULL; |
7bd939d0 | 3558 | adev->harvest_ip_mask = 0x0; |
f54d1867 | 3559 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3560 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3561 | |
3562 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3563 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3564 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3565 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
0c552ed3 LM |
3566 | adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; |
3567 | adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext; | |
36b9a952 HR |
3568 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3569 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3570 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3571 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3572 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3573 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3574 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3575 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3576 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3577 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3578 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3579 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3580 | ||
3e39ab90 AD |
3581 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3582 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3583 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3584 | |
3585 | /* mutex initialization are all done here so we | |
b8920e1e SS |
3586 | * can recall function without having locking issues |
3587 | */ | |
0e5ca0d1 | 3588 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3589 | mutex_init(&adev->pm.mutex); |
3590 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3591 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3592 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3593 | mutex_init(&adev->gfx.gfx_off_mutex); |
98a54e88 | 3594 | mutex_init(&adev->gfx.partition_mutex); |
d38ceaf9 | 3595 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3596 | mutex_init(&adev->mn_lock); |
e23b74aa | 3597 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3598 | hash_init(adev->mn_hash); |
32eaeae0 | 3599 | mutex_init(&adev->psp.mutex); |
bd052211 | 3600 | mutex_init(&adev->notifier_lock); |
8cda7a4f | 3601 | mutex_init(&adev->pm.stable_pstate_ctx_lock); |
f113cc32 | 3602 | mutex_init(&adev->benchmark_mutex); |
d38ceaf9 | 3603 | |
ab3b9de6 | 3604 | amdgpu_device_init_apu_flags(adev); |
9f6a7857 | 3605 | |
912dfc84 EQ |
3606 | r = amdgpu_device_check_arguments(adev); |
3607 | if (r) | |
3608 | return r; | |
d38ceaf9 | 3609 | |
d38ceaf9 AD |
3610 | spin_lock_init(&adev->mmio_idx_lock); |
3611 | spin_lock_init(&adev->smc_idx_lock); | |
3612 | spin_lock_init(&adev->pcie_idx_lock); | |
3613 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3614 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3615 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3616 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3617 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3618 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3619 | |
0c4e7fa5 CZ |
3620 | INIT_LIST_HEAD(&adev->shadow_list); |
3621 | mutex_init(&adev->shadow_list_lock); | |
3622 | ||
655ce9cb | 3623 | INIT_LIST_HEAD(&adev->reset_list); |
3624 | ||
6492e1b0 | 3625 | INIT_LIST_HEAD(&adev->ras_list); |
3626 | ||
beff74bc AD |
3627 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3628 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3629 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3630 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3631 | |
d4535e2c AG |
3632 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3633 | ||
d23ee13f | 3634 | adev->gfx.gfx_off_req_count = 1; |
0ad7347a AA |
3635 | adev->gfx.gfx_off_residency = 0; |
3636 | adev->gfx.gfx_off_entrycount = 0; | |
b6e79d9a | 3637 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3638 | |
b265bdbd EQ |
3639 | atomic_set(&adev->throttling_logging_enabled, 1); |
3640 | /* | |
3641 | * If throttling continues, logging will be performed every minute | |
3642 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3643 | * throttling interrupt comes every second. Thus, the total logging | |
3644 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3645 | * for throttling interrupt) = 60 seconds. | |
3646 | */ | |
3647 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3648 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3649 | ||
0fa49558 AX |
3650 | /* Registers mapping */ |
3651 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3652 | if (adev->asic_type >= CHIP_BONAIRE) { |
3653 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3654 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3655 | } else { | |
3656 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3657 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3658 | } | |
d38ceaf9 | 3659 | |
6c08e0ef EQ |
3660 | for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++) |
3661 | atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); | |
3662 | ||
d38ceaf9 | 3663 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
b8920e1e | 3664 | if (!adev->rmmio) |
d38ceaf9 | 3665 | return -ENOMEM; |
b8920e1e | 3666 | |
d38ceaf9 | 3667 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); |
b8920e1e | 3668 | DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size); |
d38ceaf9 | 3669 | |
436afdfa PY |
3670 | /* |
3671 | * Reset domain needs to be present early, before XGMI hive discovered | |
3672 | * (if any) and intitialized to use reset sem and in_gpu reset flag | |
3673 | * early on during init and before calling to RREG32. | |
3674 | */ | |
3675 | adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev"); | |
3676 | if (!adev->reset_domain) | |
3677 | return -ENOMEM; | |
3678 | ||
3aa0115d ML |
3679 | /* detect hw virtualization here */ |
3680 | amdgpu_detect_virtualization(adev); | |
3681 | ||
04e85958 TL |
3682 | amdgpu_device_get_pcie_info(adev); |
3683 | ||
dffa11b4 ML |
3684 | r = amdgpu_device_get_job_timeout_settings(adev); |
3685 | if (r) { | |
3686 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
4ef87d8f | 3687 | return r; |
a190d1c7 XY |
3688 | } |
3689 | ||
d38ceaf9 | 3690 | /* early init functions */ |
06ec9070 | 3691 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 3692 | if (r) |
4ef87d8f | 3693 | return r; |
d38ceaf9 | 3694 | |
02ff519e AD |
3695 | amdgpu_device_set_mcbp(adev); |
3696 | ||
b7cdb41e ML |
3697 | /* Get rid of things like offb */ |
3698 | r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver); | |
3699 | if (r) | |
3700 | return r; | |
3701 | ||
4d33e704 SK |
3702 | /* Enable TMZ based on IP_VERSION */ |
3703 | amdgpu_gmc_tmz_set(adev); | |
3704 | ||
957b0787 | 3705 | amdgpu_gmc_noretry_set(adev); |
4a0165f0 VS |
3706 | /* Need to get xgmi info early to decide the reset behavior*/ |
3707 | if (adev->gmc.xgmi.supported) { | |
3708 | r = adev->gfxhub.funcs->get_xgmi_info(adev); | |
3709 | if (r) | |
3710 | return r; | |
3711 | } | |
3712 | ||
8e6d0b69 | 3713 | /* enable PCIE atomic ops */ |
b4520bfd GW |
3714 | if (amdgpu_sriov_vf(adev)) { |
3715 | if (adev->virt.fw_reserve.p_pf2vf) | |
3716 | adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *) | |
3717 | adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags == | |
3718 | (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
0e768043 YZ |
3719 | /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a |
3720 | * internal path natively support atomics, set have_atomics_support to true. | |
3721 | */ | |
b4520bfd GW |
3722 | } else if ((adev->flags & AMD_IS_APU) && |
3723 | (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))) { | |
0e768043 | 3724 | adev->have_atomics_support = true; |
b4520bfd | 3725 | } else { |
8e6d0b69 | 3726 | adev->have_atomics_support = |
3727 | !pci_enable_atomic_ops_to_root(adev->pdev, | |
3728 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3729 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
b4520bfd GW |
3730 | } |
3731 | ||
8e6d0b69 | 3732 | if (!adev->have_atomics_support) |
3733 | dev_info(adev->dev, "PCIE atomic ops is not supported\n"); | |
3734 | ||
6585661d | 3735 | /* doorbell bar mapping and doorbell index init*/ |
43c064db | 3736 | amdgpu_doorbell_init(adev); |
6585661d | 3737 | |
9475a943 SL |
3738 | if (amdgpu_emu_mode == 1) { |
3739 | /* post the asic on emulation mode */ | |
3740 | emu_soc_asic_init(adev); | |
bfca0289 | 3741 | goto fence_driver_init; |
9475a943 | 3742 | } |
bfca0289 | 3743 | |
04442bf7 LL |
3744 | amdgpu_reset_init(adev); |
3745 | ||
4e99a44e | 3746 | /* detect if we are with an SRIOV vbios */ |
b4520bfd GW |
3747 | if (adev->bios) |
3748 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3749 | |
95e8e59e AD |
3750 | /* check if we need to reset the asic |
3751 | * E.g., driver was not cleanly unloaded previously, etc. | |
3752 | */ | |
f14899fd | 3753 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 3754 | if (adev->gmc.xgmi.num_physical_nodes) { |
3755 | dev_info(adev->dev, "Pending hive reset.\n"); | |
3756 | adev->gmc.xgmi.pending_reset = true; | |
3757 | /* Only need to init necessary block for SMU to handle the reset */ | |
3758 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3759 | if (!adev->ip_blocks[i].status.valid) | |
3760 | continue; | |
3761 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3762 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3763 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
3764 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 3765 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 3766 | adev->ip_blocks[i].version->funcs->name); |
3767 | adev->ip_blocks[i].status.hw = true; | |
3768 | } | |
3769 | } | |
3770 | } else { | |
59e9fff1 | 3771 | tmp = amdgpu_reset_method; |
3772 | /* It should do a default reset when loading or reloading the driver, | |
3773 | * regardless of the module parameter reset_method. | |
3774 | */ | |
3775 | amdgpu_reset_method = AMD_RESET_METHOD_NONE; | |
e3c1b071 | 3776 | r = amdgpu_asic_reset(adev); |
59e9fff1 | 3777 | amdgpu_reset_method = tmp; |
e3c1b071 | 3778 | if (r) { |
3779 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3780 | goto failed; | |
3781 | } | |
95e8e59e AD |
3782 | } |
3783 | } | |
3784 | ||
d38ceaf9 | 3785 | /* Post card if necessary */ |
39c640c0 | 3786 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3787 | if (!adev->bios) { |
bec86378 | 3788 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3789 | r = -EINVAL; |
3790 | goto failed; | |
d38ceaf9 | 3791 | } |
bec86378 | 3792 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3793 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3794 | if (r) { |
3795 | dev_err(adev->dev, "gpu post error!\n"); | |
3796 | goto failed; | |
3797 | } | |
d38ceaf9 AD |
3798 | } |
3799 | ||
9535a86a SZ |
3800 | if (adev->bios) { |
3801 | if (adev->is_atom_fw) { | |
3802 | /* Initialize clocks */ | |
3803 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3804 | if (r) { | |
3805 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
3806 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); | |
3807 | goto failed; | |
3808 | } | |
3809 | } else { | |
3810 | /* Initialize clocks */ | |
3811 | r = amdgpu_atombios_get_clock_info(adev); | |
3812 | if (r) { | |
3813 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
3814 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); | |
3815 | goto failed; | |
3816 | } | |
3817 | /* init i2c buses */ | |
3818 | if (!amdgpu_device_has_dc_support(adev)) | |
3819 | amdgpu_atombios_i2c_init(adev); | |
a5bde2f9 | 3820 | } |
2c1a2784 | 3821 | } |
d38ceaf9 | 3822 | |
bfca0289 | 3823 | fence_driver_init: |
d38ceaf9 | 3824 | /* Fence driver */ |
067f44c8 | 3825 | r = amdgpu_fence_driver_sw_init(adev); |
2c1a2784 | 3826 | if (r) { |
067f44c8 | 3827 | dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n"); |
e23b74aa | 3828 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3829 | goto failed; |
2c1a2784 | 3830 | } |
d38ceaf9 AD |
3831 | |
3832 | /* init the mode config */ | |
4a580877 | 3833 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3834 | |
06ec9070 | 3835 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3836 | if (r) { |
06ec9070 | 3837 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3838 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 3839 | goto release_ras_con; |
d38ceaf9 AD |
3840 | } |
3841 | ||
8d35a259 LG |
3842 | amdgpu_fence_driver_hw_init(adev); |
3843 | ||
d69b8971 YZ |
3844 | dev_info(adev->dev, |
3845 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3846 | adev->gfx.config.max_shader_engines, |
3847 | adev->gfx.config.max_sh_per_se, | |
3848 | adev->gfx.config.max_cu_per_sh, | |
3849 | adev->gfx.cu_info.number); | |
3850 | ||
d38ceaf9 AD |
3851 | adev->accel_working = true; |
3852 | ||
e59c0205 AX |
3853 | amdgpu_vm_check_compute_bug(adev); |
3854 | ||
95844d20 MO |
3855 | /* Initialize the buffer migration limit. */ |
3856 | if (amdgpu_moverate >= 0) | |
3857 | max_MBps = amdgpu_moverate; | |
3858 | else | |
3859 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3860 | /* Get a log2 for easy divisions. */ | |
3861 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3862 | ||
184d8384 LL |
3863 | r = amdgpu_atombios_sysfs_init(adev); |
3864 | if (r) | |
3865 | drm_err(&adev->ddev, | |
3866 | "registering atombios sysfs failed (%d).\n", r); | |
3867 | ||
d2f52ac8 | 3868 | r = amdgpu_pm_sysfs_init(adev); |
53e9d836 GC |
3869 | if (r) |
3870 | DRM_ERROR("registering pm sysfs failed (%d).\n", r); | |
d2f52ac8 | 3871 | |
5bb23532 | 3872 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3873 | if (r) { |
3874 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3875 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3876 | } else |
3877 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3878 | |
b0adca4d EQ |
3879 | /* |
3880 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3881 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3882 | * gpu instance is counted less. | |
3883 | */ | |
3884 | amdgpu_register_gpu_instance(adev); | |
3885 | ||
d38ceaf9 AD |
3886 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3887 | * explicit gating rather than handling it automatically. | |
3888 | */ | |
e3c1b071 | 3889 | if (!adev->gmc.xgmi.pending_reset) { |
3890 | r = amdgpu_device_ip_late_init(adev); | |
3891 | if (r) { | |
3892 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
3893 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 3894 | goto release_ras_con; |
e3c1b071 | 3895 | } |
3896 | /* must succeed. */ | |
3897 | amdgpu_ras_resume(adev); | |
3898 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
3899 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 3900 | } |
d38ceaf9 | 3901 | |
38eecbe0 CL |
3902 | if (amdgpu_sriov_vf(adev)) { |
3903 | amdgpu_virt_release_full_gpu(adev, true); | |
2c738637 | 3904 | flush_delayed_work(&adev->delayed_init_work); |
38eecbe0 | 3905 | } |
2c738637 | 3906 | |
77f3a5cd | 3907 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 3908 | if (r) |
77f3a5cd | 3909 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 3910 | |
7957ec80 LL |
3911 | amdgpu_fru_sysfs_init(adev); |
3912 | ||
d155bef0 AB |
3913 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3914 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3915 | if (r) |
3916 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3917 | ||
c1dd4aa6 AG |
3918 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
3919 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
3920 | pci_restore_state(pdev); | |
3921 | ||
8c3dd61c KHF |
3922 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3923 | /* this will fail for cards that aren't VGA class devices, just | |
b8920e1e SS |
3924 | * ignore it |
3925 | */ | |
8c3dd61c | 3926 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
bf44e8ce | 3927 | vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); |
8c3dd61c | 3928 | |
d37a3929 OC |
3929 | px = amdgpu_device_supports_px(ddev); |
3930 | ||
3931 | if (px || (!pci_is_thunderbolt_attached(adev->pdev) && | |
3932 | apple_gmux_detect(NULL, NULL))) | |
8c3dd61c KHF |
3933 | vga_switcheroo_register_client(adev->pdev, |
3934 | &amdgpu_switcheroo_ops, px); | |
d37a3929 OC |
3935 | |
3936 | if (px) | |
8c3dd61c | 3937 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); |
8c3dd61c | 3938 | |
e3c1b071 | 3939 | if (adev->gmc.xgmi.pending_reset) |
3940 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
3941 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3942 | ||
4a74c38c PY |
3943 | amdgpu_device_check_iommu_direct_map(adev); |
3944 | ||
d38ceaf9 | 3945 | return 0; |
83ba126a | 3946 | |
970fd197 | 3947 | release_ras_con: |
38eecbe0 CL |
3948 | if (amdgpu_sriov_vf(adev)) |
3949 | amdgpu_virt_release_full_gpu(adev, true); | |
3950 | ||
3951 | /* failed in exclusive mode due to timeout */ | |
3952 | if (amdgpu_sriov_vf(adev) && | |
3953 | !amdgpu_sriov_runtime(adev) && | |
3954 | amdgpu_virt_mmio_blocked(adev) && | |
3955 | !amdgpu_virt_wait_reset(adev)) { | |
3956 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
3957 | /* Don't send request since VF is inactive. */ | |
3958 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3959 | adev->virt.ops = NULL; | |
3960 | r = -EAGAIN; | |
3961 | } | |
970fd197 SY |
3962 | amdgpu_release_ras_context(adev); |
3963 | ||
83ba126a | 3964 | failed: |
89041940 | 3965 | amdgpu_vf_error_trans_all(adev); |
8840a387 | 3966 | |
83ba126a | 3967 | return r; |
d38ceaf9 AD |
3968 | } |
3969 | ||
07775fc1 AG |
3970 | static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) |
3971 | { | |
62d5f9f7 | 3972 | |
07775fc1 AG |
3973 | /* Clear all CPU mappings pointing to this device */ |
3974 | unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); | |
3975 | ||
3976 | /* Unmap all mapped bars - Doorbell, registers and VRAM */ | |
43c064db | 3977 | amdgpu_doorbell_fini(adev); |
07775fc1 AG |
3978 | |
3979 | iounmap(adev->rmmio); | |
3980 | adev->rmmio = NULL; | |
3981 | if (adev->mman.aper_base_kaddr) | |
3982 | iounmap(adev->mman.aper_base_kaddr); | |
3983 | adev->mman.aper_base_kaddr = NULL; | |
3984 | ||
3985 | /* Memory manager related */ | |
a0ba1279 | 3986 | if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { |
07775fc1 AG |
3987 | arch_phys_wc_del(adev->gmc.vram_mtrr); |
3988 | arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); | |
3989 | } | |
3990 | } | |
3991 | ||
d38ceaf9 | 3992 | /** |
bbe04dec | 3993 | * amdgpu_device_fini_hw - tear down the driver |
d38ceaf9 AD |
3994 | * |
3995 | * @adev: amdgpu_device pointer | |
3996 | * | |
3997 | * Tear down the driver info (all asics). | |
3998 | * Called at driver shutdown. | |
3999 | */ | |
72c8c97b | 4000 | void amdgpu_device_fini_hw(struct amdgpu_device *adev) |
d38ceaf9 | 4001 | { |
aac89168 | 4002 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 4003 | flush_delayed_work(&adev->delayed_init_work); |
d0d13fe8 | 4004 | adev->shutdown = true; |
9f875167 | 4005 | |
752c683d ML |
4006 | /* make sure IB test finished before entering exclusive mode |
4007 | * to avoid preemption on IB test | |
b8920e1e | 4008 | */ |
519b8b76 | 4009 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 4010 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
4011 | amdgpu_virt_fini_data_exchange(adev); |
4012 | } | |
752c683d | 4013 | |
e5b03032 ML |
4014 | /* disable all interrupts */ |
4015 | amdgpu_irq_disable_all(adev); | |
47fc644f | 4016 | if (adev->mode_info.mode_config_initialized) { |
1053b9c9 | 4017 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) |
4a580877 | 4018 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 4019 | else |
4a580877 | 4020 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 4021 | } |
8d35a259 | 4022 | amdgpu_fence_driver_hw_fini(adev); |
72c8c97b | 4023 | |
cd3a8a59 | 4024 | if (adev->mman.initialized) |
9bff18d1 | 4025 | drain_workqueue(adev->mman.bdev.wq); |
98f56188 | 4026 | |
53e9d836 | 4027 | if (adev->pm.sysfs_initialized) |
7c868b59 | 4028 | amdgpu_pm_sysfs_fini(adev); |
72c8c97b AG |
4029 | if (adev->ucode_sysfs_en) |
4030 | amdgpu_ucode_sysfs_fini(adev); | |
4031 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
7957ec80 | 4032 | amdgpu_fru_sysfs_fini(adev); |
72c8c97b | 4033 | |
232d1d43 SY |
4034 | /* disable ras feature must before hw fini */ |
4035 | amdgpu_ras_pre_fini(adev); | |
4036 | ||
e9669fb7 | 4037 | amdgpu_device_ip_fini_early(adev); |
d10d0daa | 4038 | |
a3848df6 YW |
4039 | amdgpu_irq_fini_hw(adev); |
4040 | ||
b6fd6e0f SK |
4041 | if (adev->mman.initialized) |
4042 | ttm_device_clear_dma_mappings(&adev->mman.bdev); | |
894c6890 | 4043 | |
d10d0daa | 4044 | amdgpu_gart_dummy_page_fini(adev); |
07775fc1 | 4045 | |
39934d3e VP |
4046 | if (drm_dev_is_unplugged(adev_to_drm(adev))) |
4047 | amdgpu_device_unmap_mmio(adev); | |
87172e89 | 4048 | |
72c8c97b AG |
4049 | } |
4050 | ||
4051 | void amdgpu_device_fini_sw(struct amdgpu_device *adev) | |
4052 | { | |
62d5f9f7 | 4053 | int idx; |
d37a3929 | 4054 | bool px; |
62d5f9f7 | 4055 | |
8d35a259 | 4056 | amdgpu_fence_driver_sw_fini(adev); |
a5c5d8d5 | 4057 | amdgpu_device_ip_fini(adev); |
b31d3063 | 4058 | amdgpu_ucode_release(&adev->firmware.gpu_info_fw); |
d38ceaf9 | 4059 | adev->accel_working = false; |
68ce8b24 | 4060 | dma_fence_put(rcu_dereference_protected(adev->gang_submit, true)); |
04442bf7 LL |
4061 | |
4062 | amdgpu_reset_fini(adev); | |
4063 | ||
d38ceaf9 | 4064 | /* free i2c buses */ |
4562236b HW |
4065 | if (!amdgpu_device_has_dc_support(adev)) |
4066 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
4067 | |
4068 | if (amdgpu_emu_mode != 1) | |
4069 | amdgpu_atombios_fini(adev); | |
4070 | ||
d38ceaf9 AD |
4071 | kfree(adev->bios); |
4072 | adev->bios = NULL; | |
d37a3929 OC |
4073 | |
4074 | px = amdgpu_device_supports_px(adev_to_drm(adev)); | |
4075 | ||
4076 | if (px || (!pci_is_thunderbolt_attached(adev->pdev) && | |
4077 | apple_gmux_detect(NULL, NULL))) | |
84c8b22e | 4078 | vga_switcheroo_unregister_client(adev->pdev); |
d37a3929 OC |
4079 | |
4080 | if (px) | |
83ba126a | 4081 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
d37a3929 | 4082 | |
38d6be81 | 4083 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
b8779475 | 4084 | vga_client_unregister(adev->pdev); |
e9bc1bf7 | 4085 | |
62d5f9f7 LS |
4086 | if (drm_dev_enter(adev_to_drm(adev), &idx)) { |
4087 | ||
4088 | iounmap(adev->rmmio); | |
4089 | adev->rmmio = NULL; | |
43c064db | 4090 | amdgpu_doorbell_fini(adev); |
62d5f9f7 LS |
4091 | drm_dev_exit(idx); |
4092 | } | |
4093 | ||
d155bef0 AB |
4094 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
4095 | amdgpu_pmu_fini(adev); | |
72de33f8 | 4096 | if (adev->mman.discovery_bin) |
a190d1c7 | 4097 | amdgpu_discovery_fini(adev); |
72c8c97b | 4098 | |
cfbb6b00 AG |
4099 | amdgpu_reset_put_reset_domain(adev->reset_domain); |
4100 | adev->reset_domain = NULL; | |
4101 | ||
72c8c97b AG |
4102 | kfree(adev->pci_state); |
4103 | ||
d38ceaf9 AD |
4104 | } |
4105 | ||
58144d28 ND |
4106 | /** |
4107 | * amdgpu_device_evict_resources - evict device resources | |
4108 | * @adev: amdgpu device object | |
4109 | * | |
4110 | * Evicts all ttm device resources(vram BOs, gart table) from the lru list | |
4111 | * of the vram memory type. Mainly used for evicting device resources | |
4112 | * at suspend time. | |
4113 | * | |
4114 | */ | |
7863c155 | 4115 | static int amdgpu_device_evict_resources(struct amdgpu_device *adev) |
58144d28 | 4116 | { |
7863c155 ML |
4117 | int ret; |
4118 | ||
e53d9665 ML |
4119 | /* No need to evict vram on APUs for suspend to ram or s2idle */ |
4120 | if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU)) | |
7863c155 | 4121 | return 0; |
58144d28 | 4122 | |
7863c155 ML |
4123 | ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM); |
4124 | if (ret) | |
58144d28 | 4125 | DRM_WARN("evicting device resources failed\n"); |
7863c155 | 4126 | return ret; |
58144d28 | 4127 | } |
d38ceaf9 AD |
4128 | |
4129 | /* | |
4130 | * Suspend & resume. | |
4131 | */ | |
4132 | /** | |
810ddc3a | 4133 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 4134 | * |
87e3f136 | 4135 | * @dev: drm dev pointer |
87e3f136 | 4136 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
4137 | * |
4138 | * Puts the hw in the suspend state (all asics). | |
4139 | * Returns 0 for success or an error on failure. | |
4140 | * Called at driver suspend. | |
4141 | */ | |
de185019 | 4142 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 4143 | { |
a2e15b0e | 4144 | struct amdgpu_device *adev = drm_to_adev(dev); |
d7274ec7 | 4145 | int r = 0; |
d38ceaf9 | 4146 | |
d38ceaf9 AD |
4147 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
4148 | return 0; | |
4149 | ||
44779b43 | 4150 | adev->in_suspend = true; |
3fa8f89d | 4151 | |
47ea2076 SF |
4152 | /* Evict the majority of BOs before grabbing the full access */ |
4153 | r = amdgpu_device_evict_resources(adev); | |
4154 | if (r) | |
4155 | return r; | |
4156 | ||
d7274ec7 BZ |
4157 | if (amdgpu_sriov_vf(adev)) { |
4158 | amdgpu_virt_fini_data_exchange(adev); | |
4159 | r = amdgpu_virt_request_full_gpu(adev, false); | |
4160 | if (r) | |
4161 | return r; | |
4162 | } | |
4163 | ||
3fa8f89d S |
4164 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3)) |
4165 | DRM_WARN("smart shift update failed\n"); | |
4166 | ||
5f818173 | 4167 | if (fbcon) |
087451f3 | 4168 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); |
5f818173 | 4169 | |
beff74bc | 4170 | cancel_delayed_work_sync(&adev->delayed_init_work); |
0dee7263 | 4171 | flush_delayed_work(&adev->gfx.gfx_off_delay_work); |
a5459475 | 4172 | |
5e6932fe | 4173 | amdgpu_ras_suspend(adev); |
4174 | ||
2196927b | 4175 | amdgpu_device_ip_suspend_phase1(adev); |
fe1053b7 | 4176 | |
c004d44e | 4177 | if (!adev->in_s0ix) |
5d3a2d95 | 4178 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); |
94fa5660 | 4179 | |
7863c155 ML |
4180 | r = amdgpu_device_evict_resources(adev); |
4181 | if (r) | |
4182 | return r; | |
d38ceaf9 | 4183 | |
8d35a259 | 4184 | amdgpu_fence_driver_hw_fini(adev); |
d38ceaf9 | 4185 | |
2196927b | 4186 | amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 4187 | |
d7274ec7 BZ |
4188 | if (amdgpu_sriov_vf(adev)) |
4189 | amdgpu_virt_release_full_gpu(adev, false); | |
4190 | ||
d38ceaf9 AD |
4191 | return 0; |
4192 | } | |
4193 | ||
4194 | /** | |
810ddc3a | 4195 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 4196 | * |
87e3f136 | 4197 | * @dev: drm dev pointer |
87e3f136 | 4198 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
4199 | * |
4200 | * Bring the hw back to operating state (all asics). | |
4201 | * Returns 0 for success or an error on failure. | |
4202 | * Called at driver resume. | |
4203 | */ | |
de185019 | 4204 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 4205 | { |
1348969a | 4206 | struct amdgpu_device *adev = drm_to_adev(dev); |
03161a6e | 4207 | int r = 0; |
d38ceaf9 | 4208 | |
d7274ec7 BZ |
4209 | if (amdgpu_sriov_vf(adev)) { |
4210 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4211 | if (r) | |
4212 | return r; | |
4213 | } | |
4214 | ||
d38ceaf9 AD |
4215 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
4216 | return 0; | |
4217 | ||
62498733 | 4218 | if (adev->in_s0ix) |
bc143d8b | 4219 | amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry); |
628c36d7 | 4220 | |
d38ceaf9 | 4221 | /* post card */ |
39c640c0 | 4222 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 4223 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 4224 | if (r) |
aac89168 | 4225 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 4226 | } |
d38ceaf9 | 4227 | |
06ec9070 | 4228 | r = amdgpu_device_ip_resume(adev); |
d7274ec7 | 4229 | |
e6707218 | 4230 | if (r) { |
aac89168 | 4231 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
3c22c1ea | 4232 | goto exit; |
e6707218 | 4233 | } |
8d35a259 | 4234 | amdgpu_fence_driver_hw_init(adev); |
5ceb54c6 | 4235 | |
06ec9070 | 4236 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 4237 | if (r) |
3c22c1ea | 4238 | goto exit; |
d38ceaf9 | 4239 | |
beff74bc AD |
4240 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
4241 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
4242 | ||
c004d44e | 4243 | if (!adev->in_s0ix) { |
5d3a2d95 AD |
4244 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); |
4245 | if (r) | |
3c22c1ea | 4246 | goto exit; |
5d3a2d95 | 4247 | } |
756e6880 | 4248 | |
3c22c1ea SF |
4249 | exit: |
4250 | if (amdgpu_sriov_vf(adev)) { | |
4251 | amdgpu_virt_init_data_exchange(adev); | |
4252 | amdgpu_virt_release_full_gpu(adev, true); | |
4253 | } | |
4254 | ||
4255 | if (r) | |
4256 | return r; | |
4257 | ||
96a5d8d4 | 4258 | /* Make sure IB tests flushed */ |
beff74bc | 4259 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 4260 | |
a2e15b0e | 4261 | if (fbcon) |
087451f3 | 4262 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false); |
d38ceaf9 | 4263 | |
5e6932fe | 4264 | amdgpu_ras_resume(adev); |
4265 | ||
d09ef243 AD |
4266 | if (adev->mode_info.num_crtc) { |
4267 | /* | |
4268 | * Most of the connector probing functions try to acquire runtime pm | |
4269 | * refs to ensure that the GPU is powered on when connector polling is | |
4270 | * performed. Since we're calling this from a runtime PM callback, | |
4271 | * trying to acquire rpm refs will cause us to deadlock. | |
4272 | * | |
4273 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
4274 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
4275 | */ | |
23a1a9e5 | 4276 | #ifdef CONFIG_PM |
d09ef243 | 4277 | dev->dev->power.disable_depth++; |
23a1a9e5 | 4278 | #endif |
d09ef243 AD |
4279 | if (!adev->dc_enabled) |
4280 | drm_helper_hpd_irq_event(dev); | |
4281 | else | |
4282 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 | 4283 | #ifdef CONFIG_PM |
d09ef243 | 4284 | dev->dev->power.disable_depth--; |
23a1a9e5 | 4285 | #endif |
d09ef243 | 4286 | } |
44779b43 RZ |
4287 | adev->in_suspend = false; |
4288 | ||
dc907c9d JX |
4289 | if (adev->enable_mes) |
4290 | amdgpu_mes_self_test(adev); | |
4291 | ||
3fa8f89d S |
4292 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0)) |
4293 | DRM_WARN("smart shift update failed\n"); | |
4294 | ||
4d3b9ae5 | 4295 | return 0; |
d38ceaf9 AD |
4296 | } |
4297 | ||
e3ecdffa AD |
4298 | /** |
4299 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
4300 | * | |
4301 | * @adev: amdgpu_device pointer | |
4302 | * | |
4303 | * The list of all the hardware IPs that make up the asic is walked and | |
4304 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
4305 | * if the asic is still hung or not. | |
4306 | * Returns true if any of the IPs are still in a hung state, false if not. | |
4307 | */ | |
06ec9070 | 4308 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
4309 | { |
4310 | int i; | |
4311 | bool asic_hang = false; | |
4312 | ||
f993d628 ML |
4313 | if (amdgpu_sriov_vf(adev)) |
4314 | return true; | |
4315 | ||
8bc04c29 AD |
4316 | if (amdgpu_asic_need_full_reset(adev)) |
4317 | return true; | |
4318 | ||
63fbf42f | 4319 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4320 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 4321 | continue; |
a1255107 AD |
4322 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
4323 | adev->ip_blocks[i].status.hang = | |
4324 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
4325 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 4326 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
4327 | asic_hang = true; |
4328 | } | |
4329 | } | |
4330 | return asic_hang; | |
4331 | } | |
4332 | ||
e3ecdffa AD |
4333 | /** |
4334 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
4335 | * | |
4336 | * @adev: amdgpu_device pointer | |
4337 | * | |
4338 | * The list of all the hardware IPs that make up the asic is walked and the | |
4339 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
4340 | * handles any IP specific hardware or software state changes that are | |
4341 | * necessary for a soft reset to succeed. | |
4342 | * Returns 0 on success, negative error code on failure. | |
4343 | */ | |
06ec9070 | 4344 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
4345 | { |
4346 | int i, r = 0; | |
4347 | ||
4348 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4349 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 4350 | continue; |
a1255107 AD |
4351 | if (adev->ip_blocks[i].status.hang && |
4352 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
4353 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
4354 | if (r) |
4355 | return r; | |
4356 | } | |
4357 | } | |
4358 | ||
4359 | return 0; | |
4360 | } | |
4361 | ||
e3ecdffa AD |
4362 | /** |
4363 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
4364 | * | |
4365 | * @adev: amdgpu_device pointer | |
4366 | * | |
4367 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
4368 | * reset is necessary to recover. | |
4369 | * Returns true if a full asic reset is required, false if not. | |
4370 | */ | |
06ec9070 | 4371 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 4372 | { |
da146d3b AD |
4373 | int i; |
4374 | ||
8bc04c29 AD |
4375 | if (amdgpu_asic_need_full_reset(adev)) |
4376 | return true; | |
4377 | ||
da146d3b | 4378 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4379 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 4380 | continue; |
a1255107 AD |
4381 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
4382 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
4383 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
4384 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
4385 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 4386 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 4387 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
4388 | return true; |
4389 | } | |
4390 | } | |
35d782fe CZ |
4391 | } |
4392 | return false; | |
4393 | } | |
4394 | ||
e3ecdffa AD |
4395 | /** |
4396 | * amdgpu_device_ip_soft_reset - do a soft reset | |
4397 | * | |
4398 | * @adev: amdgpu_device pointer | |
4399 | * | |
4400 | * The list of all the hardware IPs that make up the asic is walked and the | |
4401 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
4402 | * IP specific hardware or software state changes that are necessary to soft | |
4403 | * reset the IP. | |
4404 | * Returns 0 on success, negative error code on failure. | |
4405 | */ | |
06ec9070 | 4406 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4407 | { |
4408 | int i, r = 0; | |
4409 | ||
4410 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4411 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4412 | continue; |
a1255107 AD |
4413 | if (adev->ip_blocks[i].status.hang && |
4414 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
4415 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
4416 | if (r) |
4417 | return r; | |
4418 | } | |
4419 | } | |
4420 | ||
4421 | return 0; | |
4422 | } | |
4423 | ||
e3ecdffa AD |
4424 | /** |
4425 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
4426 | * | |
4427 | * @adev: amdgpu_device pointer | |
4428 | * | |
4429 | * The list of all the hardware IPs that make up the asic is walked and the | |
4430 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
4431 | * handles any IP specific hardware or software state changes that are | |
4432 | * necessary after the IP has been soft reset. | |
4433 | * Returns 0 on success, negative error code on failure. | |
4434 | */ | |
06ec9070 | 4435 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4436 | { |
4437 | int i, r = 0; | |
4438 | ||
4439 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4440 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4441 | continue; |
a1255107 AD |
4442 | if (adev->ip_blocks[i].status.hang && |
4443 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
4444 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
4445 | if (r) |
4446 | return r; | |
4447 | } | |
4448 | ||
4449 | return 0; | |
4450 | } | |
4451 | ||
e3ecdffa | 4452 | /** |
c33adbc7 | 4453 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4454 | * |
4455 | * @adev: amdgpu_device pointer | |
4456 | * | |
4457 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4458 | * restore things like GPUVM page tables after a GPU reset where | |
4459 | * the contents of VRAM might be lost. | |
403009bf CK |
4460 | * |
4461 | * Returns: | |
4462 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4463 | */ |
c33adbc7 | 4464 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4465 | { |
c41d1cf6 | 4466 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf | 4467 | struct amdgpu_bo *shadow; |
e18aaea7 | 4468 | struct amdgpu_bo_vm *vmbo; |
403009bf | 4469 | long r = 1, tmo; |
c41d1cf6 ML |
4470 | |
4471 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4472 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4473 | else |
4474 | tmo = msecs_to_jiffies(100); | |
4475 | ||
aac89168 | 4476 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4477 | mutex_lock(&adev->shadow_list_lock); |
e18aaea7 | 4478 | list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { |
4994d1f0 LC |
4479 | /* If vm is compute context or adev is APU, shadow will be NULL */ |
4480 | if (!vmbo->shadow) | |
4481 | continue; | |
4482 | shadow = vmbo->shadow; | |
4483 | ||
403009bf | 4484 | /* No need to recover an evicted BO */ |
d3116756 CK |
4485 | if (shadow->tbo.resource->mem_type != TTM_PL_TT || |
4486 | shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || | |
4487 | shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) | |
403009bf CK |
4488 | continue; |
4489 | ||
4490 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4491 | if (r) | |
4492 | break; | |
4493 | ||
c41d1cf6 | 4494 | if (fence) { |
1712fb1a | 4495 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4496 | dma_fence_put(fence); |
4497 | fence = next; | |
1712fb1a | 4498 | if (tmo == 0) { |
4499 | r = -ETIMEDOUT; | |
c41d1cf6 | 4500 | break; |
1712fb1a | 4501 | } else if (tmo < 0) { |
4502 | r = tmo; | |
4503 | break; | |
4504 | } | |
403009bf CK |
4505 | } else { |
4506 | fence = next; | |
c41d1cf6 | 4507 | } |
c41d1cf6 ML |
4508 | } |
4509 | mutex_unlock(&adev->shadow_list_lock); | |
4510 | ||
403009bf CK |
4511 | if (fence) |
4512 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4513 | dma_fence_put(fence); |
4514 | ||
1712fb1a | 4515 | if (r < 0 || tmo <= 0) { |
aac89168 | 4516 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4517 | return -EIO; |
4518 | } | |
c41d1cf6 | 4519 | |
aac89168 | 4520 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4521 | return 0; |
c41d1cf6 ML |
4522 | } |
4523 | ||
a90ad3c2 | 4524 | |
e3ecdffa | 4525 | /** |
06ec9070 | 4526 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4527 | * |
982a820b | 4528 | * @adev: amdgpu_device pointer |
87e3f136 | 4529 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4530 | * |
4531 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4532 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4533 | */ |
4534 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4535 | bool from_hypervisor) | |
5740682e ML |
4536 | { |
4537 | int r; | |
a5f67c93 | 4538 | struct amdgpu_hive_info *hive = NULL; |
7258fa31 | 4539 | int retry_limit = 0; |
5740682e | 4540 | |
7258fa31 | 4541 | retry: |
c004d44e | 4542 | amdgpu_amdkfd_pre_reset(adev); |
428890a3 | 4543 | |
5740682e ML |
4544 | if (from_hypervisor) |
4545 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4546 | else | |
4547 | r = amdgpu_virt_reset_gpu(adev); | |
4548 | if (r) | |
4549 | return r; | |
f734b213 | 4550 | amdgpu_irq_gpu_reset_resume_helper(adev); |
a90ad3c2 | 4551 | |
83f24a8f HC |
4552 | /* some sw clean up VF needs to do before recover */ |
4553 | amdgpu_virt_post_reset(adev); | |
4554 | ||
a90ad3c2 | 4555 | /* Resume IP prior to SMC */ |
06ec9070 | 4556 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4557 | if (r) |
4558 | goto error; | |
a90ad3c2 | 4559 | |
c9ffa427 | 4560 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4561 | |
7a3e0bb2 RZ |
4562 | r = amdgpu_device_fw_loading(adev); |
4563 | if (r) | |
4564 | return r; | |
4565 | ||
a90ad3c2 | 4566 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4567 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4568 | if (r) |
4569 | goto error; | |
a90ad3c2 | 4570 | |
a5f67c93 ZL |
4571 | hive = amdgpu_get_xgmi_hive(adev); |
4572 | /* Update PSP FW topology after reset */ | |
4573 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) | |
4574 | r = amdgpu_xgmi_update_topology(hive, adev); | |
4575 | ||
4576 | if (hive) | |
4577 | amdgpu_put_xgmi_hive(hive); | |
4578 | ||
4579 | if (!r) { | |
a5f67c93 | 4580 | r = amdgpu_ib_ring_tests(adev); |
9c12f5cd | 4581 | |
c004d44e | 4582 | amdgpu_amdkfd_post_reset(adev); |
a5f67c93 | 4583 | } |
a90ad3c2 | 4584 | |
abc34253 | 4585 | error: |
c41d1cf6 | 4586 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 4587 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 4588 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 | 4589 | } |
437f3e0b | 4590 | amdgpu_virt_release_full_gpu(adev, true); |
a90ad3c2 | 4591 | |
7258fa31 SK |
4592 | if (AMDGPU_RETRY_SRIOV_RESET(r)) { |
4593 | if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) { | |
4594 | retry_limit++; | |
4595 | goto retry; | |
4596 | } else | |
4597 | DRM_ERROR("GPU reset retry is beyond the retry limit\n"); | |
4598 | } | |
4599 | ||
a90ad3c2 ML |
4600 | return r; |
4601 | } | |
4602 | ||
9a1cddd6 | 4603 | /** |
4604 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
4605 | * | |
982a820b | 4606 | * @adev: amdgpu_device pointer |
9a1cddd6 | 4607 | * |
4608 | * check if there is any job in mirror list | |
4609 | */ | |
4610 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
4611 | { | |
4612 | int i; | |
4613 | struct drm_sched_job *job; | |
4614 | ||
4615 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4616 | struct amdgpu_ring *ring = adev->rings[i]; | |
4617 | ||
4618 | if (!ring || !ring->sched.thread) | |
4619 | continue; | |
4620 | ||
4621 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
4622 | job = list_first_entry_or_null(&ring->sched.pending_list, |
4623 | struct drm_sched_job, list); | |
9a1cddd6 | 4624 | spin_unlock(&ring->sched.job_list_lock); |
4625 | if (job) | |
4626 | return true; | |
4627 | } | |
4628 | return false; | |
4629 | } | |
4630 | ||
12938fad CK |
4631 | /** |
4632 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
4633 | * | |
982a820b | 4634 | * @adev: amdgpu_device pointer |
12938fad CK |
4635 | * |
4636 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
4637 | * a hung GPU. | |
4638 | */ | |
4639 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
4640 | { | |
12938fad | 4641 | |
3ba7b418 AG |
4642 | if (amdgpu_gpu_recovery == 0) |
4643 | goto disabled; | |
4644 | ||
1a11a65d YC |
4645 | /* Skip soft reset check in fatal error mode */ |
4646 | if (!amdgpu_ras_is_poison_mode_supported(adev)) | |
4647 | return true; | |
4648 | ||
3ba7b418 AG |
4649 | if (amdgpu_sriov_vf(adev)) |
4650 | return true; | |
4651 | ||
4652 | if (amdgpu_gpu_recovery == -1) { | |
4653 | switch (adev->asic_type) { | |
b3523c45 AD |
4654 | #ifdef CONFIG_DRM_AMDGPU_SI |
4655 | case CHIP_VERDE: | |
4656 | case CHIP_TAHITI: | |
4657 | case CHIP_PITCAIRN: | |
4658 | case CHIP_OLAND: | |
4659 | case CHIP_HAINAN: | |
4660 | #endif | |
4661 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
4662 | case CHIP_KAVERI: | |
4663 | case CHIP_KABINI: | |
4664 | case CHIP_MULLINS: | |
4665 | #endif | |
4666 | case CHIP_CARRIZO: | |
4667 | case CHIP_STONEY: | |
4668 | case CHIP_CYAN_SKILLFISH: | |
3ba7b418 | 4669 | goto disabled; |
b3523c45 AD |
4670 | default: |
4671 | break; | |
3ba7b418 | 4672 | } |
12938fad CK |
4673 | } |
4674 | ||
4675 | return true; | |
3ba7b418 AG |
4676 | |
4677 | disabled: | |
aac89168 | 4678 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4679 | return false; |
12938fad CK |
4680 | } |
4681 | ||
5c03e584 FX |
4682 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
4683 | { | |
47fc644f SS |
4684 | u32 i; |
4685 | int ret = 0; | |
5c03e584 | 4686 | |
47fc644f | 4687 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); |
5c03e584 | 4688 | |
47fc644f | 4689 | dev_info(adev->dev, "GPU mode1 reset\n"); |
5c03e584 | 4690 | |
47fc644f SS |
4691 | /* disable BM */ |
4692 | pci_clear_master(adev->pdev); | |
5c03e584 | 4693 | |
47fc644f | 4694 | amdgpu_device_cache_pci_state(adev->pdev); |
5c03e584 | 4695 | |
47fc644f SS |
4696 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { |
4697 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
4698 | ret = amdgpu_dpm_mode1_reset(adev); | |
4699 | } else { | |
4700 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
4701 | ret = psp_gpu_reset(adev); | |
4702 | } | |
5c03e584 | 4703 | |
47fc644f | 4704 | if (ret) |
2c0f880a | 4705 | goto mode1_reset_failed; |
5c03e584 | 4706 | |
47fc644f | 4707 | amdgpu_device_load_pci_state(adev->pdev); |
15c5c5f5 LL |
4708 | ret = amdgpu_psp_wait_for_bootloader(adev); |
4709 | if (ret) | |
2c0f880a | 4710 | goto mode1_reset_failed; |
5c03e584 | 4711 | |
47fc644f SS |
4712 | /* wait for asic to come out of reset */ |
4713 | for (i = 0; i < adev->usec_timeout; i++) { | |
4714 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
5c03e584 | 4715 | |
47fc644f SS |
4716 | if (memsize != 0xffffffff) |
4717 | break; | |
4718 | udelay(1); | |
4719 | } | |
5c03e584 | 4720 | |
2c0f880a HZ |
4721 | if (i >= adev->usec_timeout) { |
4722 | ret = -ETIMEDOUT; | |
4723 | goto mode1_reset_failed; | |
4724 | } | |
4725 | ||
47fc644f | 4726 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); |
15c5c5f5 | 4727 | |
2c0f880a HZ |
4728 | return 0; |
4729 | ||
4730 | mode1_reset_failed: | |
4731 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
47fc644f | 4732 | return ret; |
5c03e584 | 4733 | } |
5c6dd71e | 4734 | |
e3c1b071 | 4735 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
04442bf7 | 4736 | struct amdgpu_reset_context *reset_context) |
26bc5340 | 4737 | { |
5c1e6fa4 | 4738 | int i, r = 0; |
04442bf7 LL |
4739 | struct amdgpu_job *job = NULL; |
4740 | bool need_full_reset = | |
4741 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4742 | ||
4743 | if (reset_context->reset_req_dev == adev) | |
4744 | job = reset_context->job; | |
71182665 | 4745 | |
b602ca5f TZ |
4746 | if (amdgpu_sriov_vf(adev)) { |
4747 | /* stop the data exchange thread */ | |
4748 | amdgpu_virt_fini_data_exchange(adev); | |
4749 | } | |
4750 | ||
9e225fb9 AG |
4751 | amdgpu_fence_driver_isr_toggle(adev, true); |
4752 | ||
71182665 | 4753 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4754 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4755 | struct amdgpu_ring *ring = adev->rings[i]; | |
4756 | ||
51687759 | 4757 | if (!ring || !ring->sched.thread) |
0875dc9e | 4758 | continue; |
5740682e | 4759 | |
b8920e1e SS |
4760 | /* Clear job fence from fence drv to avoid force_completion |
4761 | * leave NULL and vm flush fence in fence drv | |
4762 | */ | |
5c1e6fa4 | 4763 | amdgpu_fence_driver_clear_job_fences(ring); |
c530b02f | 4764 | |
2f9d4084 ML |
4765 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4766 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4767 | } |
d38ceaf9 | 4768 | |
9e225fb9 AG |
4769 | amdgpu_fence_driver_isr_toggle(adev, false); |
4770 | ||
ff99849b | 4771 | if (job && job->vm) |
222b5f04 AG |
4772 | drm_sched_increase_karma(&job->base); |
4773 | ||
04442bf7 | 4774 | r = amdgpu_reset_prepare_hwcontext(adev, reset_context); |
404b277b | 4775 | /* If reset handler not implemented, continue; otherwise return */ |
b8920e1e | 4776 | if (r == -EOPNOTSUPP) |
404b277b LL |
4777 | r = 0; |
4778 | else | |
04442bf7 LL |
4779 | return r; |
4780 | ||
1d721ed6 | 4781 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4782 | if (!amdgpu_sriov_vf(adev)) { |
4783 | ||
4784 | if (!need_full_reset) | |
4785 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4786 | ||
360cd081 LG |
4787 | if (!need_full_reset && amdgpu_gpu_recovery && |
4788 | amdgpu_device_ip_check_soft_reset(adev)) { | |
26bc5340 AG |
4789 | amdgpu_device_ip_pre_soft_reset(adev); |
4790 | r = amdgpu_device_ip_soft_reset(adev); | |
4791 | amdgpu_device_ip_post_soft_reset(adev); | |
4792 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4793 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4794 | need_full_reset = true; |
4795 | } | |
4796 | } | |
4797 | ||
4798 | if (need_full_reset) | |
4799 | r = amdgpu_device_ip_suspend(adev); | |
04442bf7 LL |
4800 | if (need_full_reset) |
4801 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4802 | else | |
4803 | clear_bit(AMDGPU_NEED_FULL_RESET, | |
4804 | &reset_context->flags); | |
26bc5340 AG |
4805 | } |
4806 | ||
4807 | return r; | |
4808 | } | |
4809 | ||
15fd09a0 SA |
4810 | static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev) |
4811 | { | |
15fd09a0 SA |
4812 | int i; |
4813 | ||
38a15ad9 | 4814 | lockdep_assert_held(&adev->reset_domain->sem); |
15fd09a0 SA |
4815 | |
4816 | for (i = 0; i < adev->num_regs; i++) { | |
651d7ee6 SA |
4817 | adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]); |
4818 | trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], | |
4819 | adev->reset_dump_reg_value[i]); | |
15fd09a0 SA |
4820 | } |
4821 | ||
4822 | return 0; | |
4823 | } | |
4824 | ||
3d8785f6 SA |
4825 | #ifdef CONFIG_DEV_COREDUMP |
4826 | static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset, | |
4827 | size_t count, void *data, size_t datalen) | |
4828 | { | |
4829 | struct drm_printer p; | |
4830 | struct amdgpu_device *adev = data; | |
4831 | struct drm_print_iterator iter; | |
4832 | int i; | |
4833 | ||
4834 | iter.data = buffer; | |
4835 | iter.offset = 0; | |
4836 | iter.start = offset; | |
4837 | iter.remain = count; | |
4838 | ||
4839 | p = drm_coredump_printer(&iter); | |
4840 | ||
4841 | drm_printf(&p, "**** AMDGPU Device Coredump ****\n"); | |
4842 | drm_printf(&p, "kernel: " UTS_RELEASE "\n"); | |
4843 | drm_printf(&p, "module: " KBUILD_MODNAME "\n"); | |
4844 | drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec); | |
4845 | if (adev->reset_task_info.pid) | |
4846 | drm_printf(&p, "process_name: %s PID: %d\n", | |
4847 | adev->reset_task_info.process_name, | |
4848 | adev->reset_task_info.pid); | |
4849 | ||
4850 | if (adev->reset_vram_lost) | |
4851 | drm_printf(&p, "VRAM is lost due to GPU reset!\n"); | |
4852 | if (adev->num_regs) { | |
4853 | drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n"); | |
4854 | ||
4855 | for (i = 0; i < adev->num_regs; i++) | |
4856 | drm_printf(&p, "0x%08x: 0x%08x\n", | |
4857 | adev->reset_dump_reg_list[i], | |
4858 | adev->reset_dump_reg_value[i]); | |
4859 | } | |
4860 | ||
4861 | return count - iter.remain; | |
4862 | } | |
4863 | ||
4864 | static void amdgpu_devcoredump_free(void *data) | |
4865 | { | |
4866 | } | |
4867 | ||
4868 | static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev) | |
4869 | { | |
4870 | struct drm_device *dev = adev_to_drm(adev); | |
4871 | ||
4872 | ktime_get_ts64(&adev->reset_time); | |
d68ccdb2 | 4873 | dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_NOWAIT, |
3d8785f6 SA |
4874 | amdgpu_devcoredump_read, amdgpu_devcoredump_free); |
4875 | } | |
4876 | #endif | |
4877 | ||
04442bf7 LL |
4878 | int amdgpu_do_asic_reset(struct list_head *device_list_handle, |
4879 | struct amdgpu_reset_context *reset_context) | |
26bc5340 AG |
4880 | { |
4881 | struct amdgpu_device *tmp_adev = NULL; | |
04442bf7 | 4882 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
26bc5340 | 4883 | int r = 0; |
f5c7e779 | 4884 | bool gpu_reset_for_dev_remove = 0; |
26bc5340 | 4885 | |
04442bf7 LL |
4886 | /* Try reset handler method first */ |
4887 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
4888 | reset_list); | |
15fd09a0 | 4889 | amdgpu_reset_reg_dumps(tmp_adev); |
0a83bb35 LL |
4890 | |
4891 | reset_context->reset_device_list = device_list_handle; | |
04442bf7 | 4892 | r = amdgpu_reset_perform_reset(tmp_adev, reset_context); |
404b277b | 4893 | /* If reset handler not implemented, continue; otherwise return */ |
b8920e1e | 4894 | if (r == -EOPNOTSUPP) |
404b277b LL |
4895 | r = 0; |
4896 | else | |
04442bf7 LL |
4897 | return r; |
4898 | ||
4899 | /* Reset handler not implemented, use the default method */ | |
4900 | need_full_reset = | |
4901 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4902 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); | |
4903 | ||
f5c7e779 YC |
4904 | gpu_reset_for_dev_remove = |
4905 | test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) && | |
4906 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4907 | ||
26bc5340 | 4908 | /* |
655ce9cb | 4909 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
4910 | * to allow proper links negotiation in FW (within 1 sec) |
4911 | */ | |
7ac71382 | 4912 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 4913 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 4914 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4915 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 4916 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 4917 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4918 | r = -EALREADY; |
4919 | } else | |
4920 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4921 | |
041a62bc | 4922 | if (r) { |
aac89168 | 4923 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4924 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4925 | break; |
ce316fa5 LM |
4926 | } |
4927 | } | |
4928 | ||
041a62bc AG |
4929 | /* For XGMI wait for all resets to complete before proceed */ |
4930 | if (!r) { | |
655ce9cb | 4931 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
4932 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
4933 | flush_work(&tmp_adev->xgmi_reset_work); | |
4934 | r = tmp_adev->asic_reset_res; | |
4935 | if (r) | |
4936 | break; | |
ce316fa5 LM |
4937 | } |
4938 | } | |
4939 | } | |
ce316fa5 | 4940 | } |
26bc5340 | 4941 | |
43c4d576 | 4942 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 4943 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
5e67bba3 | 4944 | if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops && |
4945 | tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) | |
4946 | tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev); | |
43c4d576 JC |
4947 | } |
4948 | ||
00eaa571 | 4949 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4950 | } |
00eaa571 | 4951 | |
f5c7e779 YC |
4952 | /* Since the mode1 reset affects base ip blocks, the |
4953 | * phase1 ip blocks need to be resumed. Otherwise there | |
4954 | * will be a BIOS signature error and the psp bootloader | |
4955 | * can't load kdb on the next amdgpu install. | |
4956 | */ | |
4957 | if (gpu_reset_for_dev_remove) { | |
4958 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) | |
4959 | amdgpu_device_ip_resume_phase1(tmp_adev); | |
4960 | ||
4961 | goto end; | |
4962 | } | |
4963 | ||
655ce9cb | 4964 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
4965 | if (need_full_reset) { |
4966 | /* post card */ | |
e3c1b071 | 4967 | r = amdgpu_device_asic_init(tmp_adev); |
4968 | if (r) { | |
aac89168 | 4969 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 4970 | } else { |
26bc5340 | 4971 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
9cec53c1 | 4972 | |
26bc5340 AG |
4973 | r = amdgpu_device_ip_resume_phase1(tmp_adev); |
4974 | if (r) | |
4975 | goto out; | |
4976 | ||
4977 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
3d8785f6 SA |
4978 | #ifdef CONFIG_DEV_COREDUMP |
4979 | tmp_adev->reset_vram_lost = vram_lost; | |
4980 | memset(&tmp_adev->reset_task_info, 0, | |
4981 | sizeof(tmp_adev->reset_task_info)); | |
4982 | if (reset_context->job && reset_context->job->vm) | |
4983 | tmp_adev->reset_task_info = | |
4984 | reset_context->job->vm->task_info; | |
4985 | amdgpu_reset_capture_coredumpm(tmp_adev); | |
4986 | #endif | |
26bc5340 | 4987 | if (vram_lost) { |
77e7f829 | 4988 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4989 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4990 | } |
4991 | ||
26bc5340 AG |
4992 | r = amdgpu_device_fw_loading(tmp_adev); |
4993 | if (r) | |
4994 | return r; | |
4995 | ||
4996 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4997 | if (r) | |
4998 | goto out; | |
4999 | ||
5000 | if (vram_lost) | |
5001 | amdgpu_device_fill_reset_magic(tmp_adev); | |
5002 | ||
fdafb359 EQ |
5003 | /* |
5004 | * Add this ASIC as tracked as reset was already | |
5005 | * complete successfully. | |
5006 | */ | |
5007 | amdgpu_register_gpu_instance(tmp_adev); | |
5008 | ||
04442bf7 LL |
5009 | if (!reset_context->hive && |
5010 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
e3c1b071 | 5011 | amdgpu_xgmi_add_device(tmp_adev); |
5012 | ||
7c04ca50 | 5013 | r = amdgpu_device_ip_late_init(tmp_adev); |
5014 | if (r) | |
5015 | goto out; | |
5016 | ||
087451f3 | 5017 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false); |
565d1941 | 5018 | |
e8fbaf03 GC |
5019 | /* |
5020 | * The GPU enters bad state once faulty pages | |
5021 | * by ECC has reached the threshold, and ras | |
5022 | * recovery is scheduled next. So add one check | |
5023 | * here to break recovery if it indeed exceeds | |
5024 | * bad page threshold, and remind user to | |
5025 | * retire this GPU or setting one bigger | |
5026 | * bad_page_threshold value to fix this once | |
5027 | * probing driver again. | |
5028 | */ | |
11003c68 | 5029 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
5030 | /* must succeed. */ |
5031 | amdgpu_ras_resume(tmp_adev); | |
5032 | } else { | |
5033 | r = -EINVAL; | |
5034 | goto out; | |
5035 | } | |
e79a04d5 | 5036 | |
26bc5340 | 5037 | /* Update PSP FW topology after reset */ |
04442bf7 LL |
5038 | if (reset_context->hive && |
5039 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
5040 | r = amdgpu_xgmi_update_topology( | |
5041 | reset_context->hive, tmp_adev); | |
26bc5340 AG |
5042 | } |
5043 | } | |
5044 | ||
26bc5340 AG |
5045 | out: |
5046 | if (!r) { | |
5047 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
5048 | r = amdgpu_ib_ring_tests(tmp_adev); | |
5049 | if (r) { | |
5050 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
26bc5340 AG |
5051 | need_full_reset = true; |
5052 | r = -EAGAIN; | |
5053 | goto end; | |
5054 | } | |
5055 | } | |
5056 | ||
5057 | if (!r) | |
5058 | r = amdgpu_device_recover_vram(tmp_adev); | |
5059 | else | |
5060 | tmp_adev->asic_reset_res = r; | |
5061 | } | |
5062 | ||
5063 | end: | |
04442bf7 LL |
5064 | if (need_full_reset) |
5065 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
5066 | else | |
5067 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 AG |
5068 | return r; |
5069 | } | |
5070 | ||
e923be99 | 5071 | static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev) |
26bc5340 | 5072 | { |
5740682e | 5073 | |
a3a09142 AD |
5074 | switch (amdgpu_asic_reset_method(adev)) { |
5075 | case AMD_RESET_METHOD_MODE1: | |
5076 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
5077 | break; | |
5078 | case AMD_RESET_METHOD_MODE2: | |
5079 | adev->mp1_state = PP_MP1_STATE_RESET; | |
5080 | break; | |
5081 | default: | |
5082 | adev->mp1_state = PP_MP1_STATE_NONE; | |
5083 | break; | |
5084 | } | |
26bc5340 | 5085 | } |
d38ceaf9 | 5086 | |
e923be99 | 5087 | static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev) |
26bc5340 | 5088 | { |
89041940 | 5089 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 5090 | adev->mp1_state = PP_MP1_STATE_NONE; |
91fb309d HC |
5091 | } |
5092 | ||
3f12acc8 EQ |
5093 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
5094 | { | |
5095 | struct pci_dev *p = NULL; | |
5096 | ||
5097 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
5098 | adev->pdev->bus->number, 1); | |
5099 | if (p) { | |
5100 | pm_runtime_enable(&(p->dev)); | |
5101 | pm_runtime_resume(&(p->dev)); | |
5102 | } | |
b85e285e YY |
5103 | |
5104 | pci_dev_put(p); | |
3f12acc8 EQ |
5105 | } |
5106 | ||
5107 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
5108 | { | |
5109 | enum amd_reset_method reset_method; | |
5110 | struct pci_dev *p = NULL; | |
5111 | u64 expires; | |
5112 | ||
5113 | /* | |
5114 | * For now, only BACO and mode1 reset are confirmed | |
5115 | * to suffer the audio issue without proper suspended. | |
5116 | */ | |
5117 | reset_method = amdgpu_asic_reset_method(adev); | |
5118 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
5119 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
5120 | return -EINVAL; | |
5121 | ||
5122 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
5123 | adev->pdev->bus->number, 1); | |
5124 | if (!p) | |
5125 | return -ENODEV; | |
5126 | ||
5127 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
5128 | if (!expires) | |
5129 | /* | |
5130 | * If we cannot get the audio device autosuspend delay, | |
5131 | * a fixed 4S interval will be used. Considering 3S is | |
5132 | * the audio controller default autosuspend delay setting. | |
5133 | * 4S used here is guaranteed to cover that. | |
5134 | */ | |
54b7feb9 | 5135 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
5136 | |
5137 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
5138 | if (!pm_runtime_suspend(&(p->dev))) | |
5139 | break; | |
5140 | ||
5141 | if (expires < ktime_get_mono_fast_ns()) { | |
5142 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
b85e285e | 5143 | pci_dev_put(p); |
3f12acc8 EQ |
5144 | /* TODO: abort the succeeding gpu reset? */ |
5145 | return -ETIMEDOUT; | |
5146 | } | |
5147 | } | |
5148 | ||
5149 | pm_runtime_disable(&(p->dev)); | |
5150 | ||
b85e285e | 5151 | pci_dev_put(p); |
3f12acc8 EQ |
5152 | return 0; |
5153 | } | |
5154 | ||
d193b12b | 5155 | static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) |
247c7b0d AG |
5156 | { |
5157 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
5158 | ||
5159 | #if defined(CONFIG_DEBUG_FS) | |
5160 | if (!amdgpu_sriov_vf(adev)) | |
5161 | cancel_work(&adev->reset_work); | |
5162 | #endif | |
5163 | ||
5164 | if (adev->kfd.dev) | |
5165 | cancel_work(&adev->kfd.reset_work); | |
5166 | ||
5167 | if (amdgpu_sriov_vf(adev)) | |
5168 | cancel_work(&adev->virt.flr_work); | |
5169 | ||
5170 | if (con && adev->ras_enabled) | |
5171 | cancel_work(&con->recovery_work); | |
5172 | ||
5173 | } | |
5174 | ||
26bc5340 | 5175 | /** |
6e9c65f7 | 5176 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler |
26bc5340 | 5177 | * |
982a820b | 5178 | * @adev: amdgpu_device pointer |
26bc5340 | 5179 | * @job: which job trigger hang |
80bd2de1 | 5180 | * @reset_context: amdgpu reset context pointer |
26bc5340 AG |
5181 | * |
5182 | * Attempt to reset the GPU if it has hung (all asics). | |
5183 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
5184 | * Returns 0 for success or an error on failure. | |
5185 | */ | |
5186 | ||
cf727044 | 5187 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
f1549c09 LG |
5188 | struct amdgpu_job *job, |
5189 | struct amdgpu_reset_context *reset_context) | |
26bc5340 | 5190 | { |
1d721ed6 | 5191 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 | 5192 | bool job_signaled = false; |
26bc5340 | 5193 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 5194 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 5195 | int i, r = 0; |
bb5c7235 | 5196 | bool need_emergency_restart = false; |
3f12acc8 | 5197 | bool audio_suspended = false; |
f5c7e779 YC |
5198 | bool gpu_reset_for_dev_remove = false; |
5199 | ||
5200 | gpu_reset_for_dev_remove = | |
5201 | test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) && | |
5202 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 | 5203 | |
6e3cd2a9 | 5204 | /* |
bb5c7235 WS |
5205 | * Special case: RAS triggered and full reset isn't supported |
5206 | */ | |
5207 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
5208 | ||
d5ea093e AG |
5209 | /* |
5210 | * Flush RAM to disk so that after reboot | |
5211 | * the user can read log and see why the system rebooted. | |
5212 | */ | |
bb5c7235 | 5213 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
5214 | DRM_WARN("Emergency reboot."); |
5215 | ||
5216 | ksys_sync_helper(); | |
5217 | emergency_restart(); | |
5218 | } | |
5219 | ||
b823821f | 5220 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 5221 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 | 5222 | |
175ac6ec ZL |
5223 | if (!amdgpu_sriov_vf(adev)) |
5224 | hive = amdgpu_get_xgmi_hive(adev); | |
681260df | 5225 | if (hive) |
53b3f8f4 | 5226 | mutex_lock(&hive->hive_lock); |
26bc5340 | 5227 | |
f1549c09 LG |
5228 | reset_context->job = job; |
5229 | reset_context->hive = hive; | |
9e94d22c EQ |
5230 | /* |
5231 | * Build list of devices to reset. | |
5232 | * In case we are in XGMI hive mode, resort the device list | |
5233 | * to put adev in the 1st position. | |
5234 | */ | |
5235 | INIT_LIST_HEAD(&device_list); | |
175ac6ec | 5236 | if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) { |
83d29a5f | 5237 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { |
655ce9cb | 5238 | list_add_tail(&tmp_adev->reset_list, &device_list); |
83d29a5f YC |
5239 | if (gpu_reset_for_dev_remove && adev->shutdown) |
5240 | tmp_adev->shutdown = true; | |
5241 | } | |
655ce9cb | 5242 | if (!list_is_first(&adev->reset_list, &device_list)) |
5243 | list_rotate_to_front(&adev->reset_list, &device_list); | |
5244 | device_list_handle = &device_list; | |
26bc5340 | 5245 | } else { |
655ce9cb | 5246 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
5247 | device_list_handle = &device_list; |
5248 | } | |
5249 | ||
e923be99 AG |
5250 | /* We need to lock reset domain only once both for XGMI and single device */ |
5251 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
5252 | reset_list); | |
3675c2f2 | 5253 | amdgpu_device_lock_reset_domain(tmp_adev->reset_domain); |
e923be99 | 5254 | |
1d721ed6 | 5255 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 5256 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
f287a3c5 | 5257 | |
e923be99 | 5258 | amdgpu_device_set_mp1_state(tmp_adev); |
f287a3c5 | 5259 | |
3f12acc8 EQ |
5260 | /* |
5261 | * Try to put the audio codec into suspend state | |
5262 | * before gpu reset started. | |
5263 | * | |
5264 | * Due to the power domain of the graphics device | |
5265 | * is shared with AZ power domain. Without this, | |
5266 | * we may change the audio hardware from behind | |
5267 | * the audio driver's back. That will trigger | |
5268 | * some audio codec errors. | |
5269 | */ | |
5270 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
5271 | audio_suspended = true; | |
5272 | ||
9e94d22c EQ |
5273 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
5274 | ||
52fb44cf EQ |
5275 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
5276 | ||
c004d44e | 5277 | if (!amdgpu_sriov_vf(tmp_adev)) |
428890a3 | 5278 | amdgpu_amdkfd_pre_reset(tmp_adev); |
9e94d22c | 5279 | |
12ffa55d AG |
5280 | /* |
5281 | * Mark these ASICs to be reseted as untracked first | |
5282 | * And add them back after reset completed | |
5283 | */ | |
5284 | amdgpu_unregister_gpu_instance(tmp_adev); | |
5285 | ||
163d4cd2 | 5286 | drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true); |
565d1941 | 5287 | |
f1c1314b | 5288 | /* disable ras on ALL IPs */ |
bb5c7235 | 5289 | if (!need_emergency_restart && |
b823821f | 5290 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 5291 | amdgpu_ras_suspend(tmp_adev); |
5292 | ||
1d721ed6 AG |
5293 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5294 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5295 | ||
5296 | if (!ring || !ring->sched.thread) | |
5297 | continue; | |
5298 | ||
0b2d2c2e | 5299 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 5300 | |
bb5c7235 | 5301 | if (need_emergency_restart) |
7c6e68c7 | 5302 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 5303 | } |
8f8c80f4 | 5304 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
5305 | } |
5306 | ||
bb5c7235 | 5307 | if (need_emergency_restart) |
7c6e68c7 AG |
5308 | goto skip_sched_resume; |
5309 | ||
1d721ed6 AG |
5310 | /* |
5311 | * Must check guilty signal here since after this point all old | |
5312 | * HW fences are force signaled. | |
5313 | * | |
5314 | * job->base holds a reference to parent fence | |
5315 | */ | |
f6a3f660 | 5316 | if (job && dma_fence_is_signaled(&job->hw_fence)) { |
1d721ed6 | 5317 | job_signaled = true; |
1d721ed6 AG |
5318 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
5319 | goto skip_hw_reset; | |
5320 | } | |
5321 | ||
26bc5340 | 5322 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 5323 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
f5c7e779 YC |
5324 | if (gpu_reset_for_dev_remove) { |
5325 | /* Workaroud for ASICs need to disable SMC first */ | |
5326 | amdgpu_device_smu_fini_early(tmp_adev); | |
5327 | } | |
f1549c09 | 5328 | r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); |
26bc5340 AG |
5329 | /*TODO Should we stop ?*/ |
5330 | if (r) { | |
aac89168 | 5331 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 5332 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
5333 | tmp_adev->asic_reset_res = r; |
5334 | } | |
247c7b0d AG |
5335 | |
5336 | /* | |
5337 | * Drop all pending non scheduler resets. Scheduler resets | |
5338 | * were already dropped during drm_sched_stop | |
5339 | */ | |
d193b12b | 5340 | amdgpu_device_stop_pending_resets(tmp_adev); |
26bc5340 AG |
5341 | } |
5342 | ||
5343 | /* Actual ASIC resets if needed.*/ | |
4f30d920 | 5344 | /* Host driver will handle XGMI hive reset for SRIOV */ |
26bc5340 AG |
5345 | if (amdgpu_sriov_vf(adev)) { |
5346 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
5347 | if (r) | |
5348 | adev->asic_reset_res = r; | |
950d6425 | 5349 | |
28606c4e YC |
5350 | /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */ |
5351 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || | |
5352 | adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) | |
950d6425 | 5353 | amdgpu_ras_resume(adev); |
26bc5340 | 5354 | } else { |
f1549c09 | 5355 | r = amdgpu_do_asic_reset(device_list_handle, reset_context); |
b98a1648 | 5356 | if (r && r == -EAGAIN) |
26bc5340 | 5357 | goto retry; |
f5c7e779 YC |
5358 | |
5359 | if (!r && gpu_reset_for_dev_remove) | |
5360 | goto recover_end; | |
26bc5340 AG |
5361 | } |
5362 | ||
1d721ed6 AG |
5363 | skip_hw_reset: |
5364 | ||
26bc5340 | 5365 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 5366 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 5367 | |
1d721ed6 AG |
5368 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5369 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5370 | ||
5371 | if (!ring || !ring->sched.thread) | |
5372 | continue; | |
5373 | ||
6868a2c4 | 5374 | drm_sched_start(&ring->sched, true); |
1d721ed6 AG |
5375 | } |
5376 | ||
693073a0 | 5377 | if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)) |
ed67f729 JX |
5378 | amdgpu_mes_self_test(tmp_adev); |
5379 | ||
b8920e1e | 5380 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) |
4a580877 | 5381 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 | 5382 | |
7258fa31 SK |
5383 | if (tmp_adev->asic_reset_res) |
5384 | r = tmp_adev->asic_reset_res; | |
5385 | ||
1d721ed6 | 5386 | tmp_adev->asic_reset_res = 0; |
26bc5340 AG |
5387 | |
5388 | if (r) { | |
5389 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 5390 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
5391 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
5392 | } else { | |
12ffa55d | 5393 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
3fa8f89d S |
5394 | if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0)) |
5395 | DRM_WARN("smart shift update failed\n"); | |
26bc5340 | 5396 | } |
7c6e68c7 | 5397 | } |
26bc5340 | 5398 | |
7c6e68c7 | 5399 | skip_sched_resume: |
655ce9cb | 5400 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
428890a3 | 5401 | /* unlock kfd: SRIOV would do it separately */ |
c004d44e | 5402 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
428890a3 | 5403 | amdgpu_amdkfd_post_reset(tmp_adev); |
8e2712e7 | 5404 | |
5405 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
5406 | * need to bring up kfd here if it's not be initialized before | |
5407 | */ | |
5408 | if (!adev->kfd.init_complete) | |
5409 | amdgpu_amdkfd_device_init(adev); | |
5410 | ||
3f12acc8 EQ |
5411 | if (audio_suspended) |
5412 | amdgpu_device_resume_display_audio(tmp_adev); | |
e923be99 AG |
5413 | |
5414 | amdgpu_device_unset_mp1_state(tmp_adev); | |
d293470e YC |
5415 | |
5416 | amdgpu_ras_set_error_query_ready(tmp_adev, true); | |
26bc5340 AG |
5417 | } |
5418 | ||
f5c7e779 | 5419 | recover_end: |
e923be99 AG |
5420 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, |
5421 | reset_list); | |
5422 | amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain); | |
5423 | ||
9e94d22c | 5424 | if (hive) { |
9e94d22c | 5425 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 5426 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 5427 | } |
26bc5340 | 5428 | |
f287a3c5 | 5429 | if (r) |
26bc5340 | 5430 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
ab9a0b1f AG |
5431 | |
5432 | atomic_set(&adev->reset_domain->reset_res, r); | |
d38ceaf9 AD |
5433 | return r; |
5434 | } | |
5435 | ||
e3ecdffa AD |
5436 | /** |
5437 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
5438 | * | |
5439 | * @adev: amdgpu_device pointer | |
5440 | * | |
5441 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
5442 | * and lanes) of the slot the device is in. Handles APUs and | |
5443 | * virtualized environments where PCIE config space may not be available. | |
5444 | */ | |
5494d864 | 5445 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 5446 | { |
5d9a6330 | 5447 | struct pci_dev *pdev; |
c5313457 HK |
5448 | enum pci_bus_speed speed_cap, platform_speed_cap; |
5449 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 5450 | |
cd474ba0 AD |
5451 | if (amdgpu_pcie_gen_cap) |
5452 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 5453 | |
cd474ba0 AD |
5454 | if (amdgpu_pcie_lane_cap) |
5455 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 5456 | |
cd474ba0 | 5457 | /* covers APUs as well */ |
04e85958 | 5458 | if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) { |
cd474ba0 AD |
5459 | if (adev->pm.pcie_gen_mask == 0) |
5460 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
5461 | if (adev->pm.pcie_mlw_mask == 0) | |
5462 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 5463 | return; |
cd474ba0 | 5464 | } |
d0dd7f0c | 5465 | |
c5313457 HK |
5466 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
5467 | return; | |
5468 | ||
dbaa922b AD |
5469 | pcie_bandwidth_available(adev->pdev, NULL, |
5470 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 5471 | |
cd474ba0 | 5472 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
5473 | /* asic caps */ |
5474 | pdev = adev->pdev; | |
5475 | speed_cap = pcie_get_speed_cap(pdev); | |
5476 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
5477 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
5478 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
5479 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 5480 | } else { |
2b3a1f51 FX |
5481 | if (speed_cap == PCIE_SPEED_32_0GT) |
5482 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5483 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5484 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5485 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5486 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5487 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5488 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5489 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5490 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5491 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
5492 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
5493 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5494 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5495 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
5496 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
5497 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5498 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5499 | else | |
5500 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5501 | } | |
5502 | /* platform caps */ | |
c5313457 | 5503 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
5504 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5505 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5506 | } else { | |
2b3a1f51 FX |
5507 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
5508 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5509 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5510 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5511 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5512 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5513 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5514 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5515 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5516 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5517 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 5518 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
5519 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5520 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5521 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 5522 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
5523 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5524 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5525 | else | |
5526 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5527 | ||
cd474ba0 AD |
5528 | } |
5529 | } | |
5530 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 5531 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
5532 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
5533 | } else { | |
c5313457 | 5534 | switch (platform_link_width) { |
5d9a6330 | 5535 | case PCIE_LNK_X32: |
cd474ba0 AD |
5536 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
5537 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
5538 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5539 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5540 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5541 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5542 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5543 | break; | |
5d9a6330 | 5544 | case PCIE_LNK_X16: |
cd474ba0 AD |
5545 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5546 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5547 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5548 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5549 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5550 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5551 | break; | |
5d9a6330 | 5552 | case PCIE_LNK_X12: |
cd474ba0 AD |
5553 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5554 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5555 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5556 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5557 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5558 | break; | |
5d9a6330 | 5559 | case PCIE_LNK_X8: |
cd474ba0 AD |
5560 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5561 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5562 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5563 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5564 | break; | |
5d9a6330 | 5565 | case PCIE_LNK_X4: |
cd474ba0 AD |
5566 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5567 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5568 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5569 | break; | |
5d9a6330 | 5570 | case PCIE_LNK_X2: |
cd474ba0 AD |
5571 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5572 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5573 | break; | |
5d9a6330 | 5574 | case PCIE_LNK_X1: |
cd474ba0 AD |
5575 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5576 | break; | |
5577 | default: | |
5578 | break; | |
5579 | } | |
d0dd7f0c AD |
5580 | } |
5581 | } | |
5582 | } | |
d38ceaf9 | 5583 | |
08a2fd23 RE |
5584 | /** |
5585 | * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR | |
5586 | * | |
5587 | * @adev: amdgpu_device pointer | |
5588 | * @peer_adev: amdgpu_device pointer for peer device trying to access @adev | |
5589 | * | |
5590 | * Return true if @peer_adev can access (DMA) @adev through the PCIe | |
5591 | * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of | |
5592 | * @peer_adev. | |
5593 | */ | |
5594 | bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, | |
5595 | struct amdgpu_device *peer_adev) | |
5596 | { | |
5597 | #ifdef CONFIG_HSA_AMD_P2P | |
5598 | uint64_t address_mask = peer_adev->dev->dma_mask ? | |
5599 | ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1); | |
5600 | resource_size_t aper_limit = | |
5601 | adev->gmc.aper_base + adev->gmc.aper_size - 1; | |
bb66ecbf LL |
5602 | bool p2p_access = |
5603 | !adev->gmc.xgmi.connected_to_cpu && | |
5604 | !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); | |
08a2fd23 RE |
5605 | |
5606 | return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && | |
5607 | adev->gmc.real_vram_size == adev->gmc.visible_vram_size && | |
5608 | !(adev->gmc.aper_base & address_mask || | |
5609 | aper_limit & address_mask)); | |
5610 | #else | |
5611 | return false; | |
5612 | #endif | |
5613 | } | |
5614 | ||
361dbd01 AD |
5615 | int amdgpu_device_baco_enter(struct drm_device *dev) |
5616 | { | |
1348969a | 5617 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5618 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 5619 | |
6ab68650 | 5620 | if (!amdgpu_device_supports_baco(dev)) |
361dbd01 AD |
5621 | return -ENOTSUPP; |
5622 | ||
8ab0d6f0 | 5623 | if (ras && adev->ras_enabled && |
acdae216 | 5624 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5625 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
5626 | ||
9530273e | 5627 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
5628 | } |
5629 | ||
5630 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
5631 | { | |
1348969a | 5632 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5633 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 5634 | int ret = 0; |
361dbd01 | 5635 | |
6ab68650 | 5636 | if (!amdgpu_device_supports_baco(dev)) |
361dbd01 AD |
5637 | return -ENOTSUPP; |
5638 | ||
9530273e EQ |
5639 | ret = amdgpu_dpm_baco_exit(adev); |
5640 | if (ret) | |
5641 | return ret; | |
7a22677b | 5642 | |
8ab0d6f0 | 5643 | if (ras && adev->ras_enabled && |
acdae216 | 5644 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5645 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
5646 | ||
1bece222 CL |
5647 | if (amdgpu_passthrough(adev) && |
5648 | adev->nbio.funcs->clear_doorbell_interrupt) | |
5649 | adev->nbio.funcs->clear_doorbell_interrupt(adev); | |
5650 | ||
7a22677b | 5651 | return 0; |
361dbd01 | 5652 | } |
c9a6b82f AG |
5653 | |
5654 | /** | |
5655 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
5656 | * @pdev: PCI device struct | |
5657 | * @state: PCI channel state | |
5658 | * | |
5659 | * Description: Called when a PCI error is detected. | |
5660 | * | |
5661 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
5662 | */ | |
5663 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5664 | { | |
5665 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5666 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5667 | int i; |
c9a6b82f AG |
5668 | |
5669 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
5670 | ||
6894305c AG |
5671 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
5672 | DRM_WARN("No support for XGMI hive yet..."); | |
5673 | return PCI_ERS_RESULT_DISCONNECT; | |
5674 | } | |
5675 | ||
e17e27f9 GC |
5676 | adev->pci_channel_state = state; |
5677 | ||
c9a6b82f AG |
5678 | switch (state) { |
5679 | case pci_channel_io_normal: | |
5680 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 5681 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
5682 | case pci_channel_io_frozen: |
5683 | /* | |
d0fb18b5 | 5684 | * Locking adev->reset_domain->sem will prevent any external access |
acd89fca AG |
5685 | * to GPU during PCI error recovery |
5686 | */ | |
3675c2f2 | 5687 | amdgpu_device_lock_reset_domain(adev->reset_domain); |
e923be99 | 5688 | amdgpu_device_set_mp1_state(adev); |
acd89fca AG |
5689 | |
5690 | /* | |
5691 | * Block any work scheduling as we do for regular GPU reset | |
5692 | * for the duration of the recovery | |
5693 | */ | |
5694 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5695 | struct amdgpu_ring *ring = adev->rings[i]; | |
5696 | ||
5697 | if (!ring || !ring->sched.thread) | |
5698 | continue; | |
5699 | ||
5700 | drm_sched_stop(&ring->sched, NULL); | |
5701 | } | |
8f8c80f4 | 5702 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
5703 | return PCI_ERS_RESULT_NEED_RESET; |
5704 | case pci_channel_io_perm_failure: | |
5705 | /* Permanent error, prepare for device removal */ | |
5706 | return PCI_ERS_RESULT_DISCONNECT; | |
5707 | } | |
5708 | ||
5709 | return PCI_ERS_RESULT_NEED_RESET; | |
5710 | } | |
5711 | ||
5712 | /** | |
5713 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
5714 | * @pdev: pointer to PCI device | |
5715 | */ | |
5716 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
5717 | { | |
5718 | ||
5719 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
5720 | ||
5721 | /* TODO - dump whatever for debugging purposes */ | |
5722 | ||
5723 | /* This called only if amdgpu_pci_error_detected returns | |
5724 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
5725 | * works, no need to reset slot. | |
5726 | */ | |
5727 | ||
5728 | return PCI_ERS_RESULT_RECOVERED; | |
5729 | } | |
5730 | ||
5731 | /** | |
5732 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
5733 | * @pdev: PCI device struct | |
5734 | * | |
5735 | * Description: This routine is called by the pci error recovery | |
5736 | * code after the PCI slot has been reset, just before we | |
5737 | * should resume normal operations. | |
5738 | */ | |
5739 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
5740 | { | |
5741 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5742 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 5743 | int r, i; |
04442bf7 | 5744 | struct amdgpu_reset_context reset_context; |
362c7b91 | 5745 | u32 memsize; |
7ac71382 | 5746 | struct list_head device_list; |
c9a6b82f AG |
5747 | |
5748 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
5749 | ||
04442bf7 LL |
5750 | memset(&reset_context, 0, sizeof(reset_context)); |
5751 | ||
7ac71382 | 5752 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 5753 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 5754 | |
362c7b91 AG |
5755 | /* wait for asic to come out of reset */ |
5756 | msleep(500); | |
5757 | ||
7ac71382 | 5758 | /* Restore PCI confspace */ |
c1dd4aa6 | 5759 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 5760 | |
362c7b91 AG |
5761 | /* confirm ASIC came out of reset */ |
5762 | for (i = 0; i < adev->usec_timeout; i++) { | |
5763 | memsize = amdgpu_asic_get_config_memsize(adev); | |
5764 | ||
5765 | if (memsize != 0xffffffff) | |
5766 | break; | |
5767 | udelay(1); | |
5768 | } | |
5769 | if (memsize == 0xffffffff) { | |
5770 | r = -ETIME; | |
5771 | goto out; | |
5772 | } | |
5773 | ||
04442bf7 LL |
5774 | reset_context.method = AMD_RESET_METHOD_NONE; |
5775 | reset_context.reset_req_dev = adev; | |
5776 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5777 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); | |
5778 | ||
7afefb81 | 5779 | adev->no_hw_access = true; |
04442bf7 | 5780 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
7afefb81 | 5781 | adev->no_hw_access = false; |
c9a6b82f AG |
5782 | if (r) |
5783 | goto out; | |
5784 | ||
04442bf7 | 5785 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
c9a6b82f AG |
5786 | |
5787 | out: | |
c9a6b82f | 5788 | if (!r) { |
c1dd4aa6 AG |
5789 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
5790 | pci_restore_state(adev->pdev); | |
5791 | ||
c9a6b82f AG |
5792 | DRM_INFO("PCIe error recovery succeeded\n"); |
5793 | } else { | |
5794 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
e923be99 AG |
5795 | amdgpu_device_unset_mp1_state(adev); |
5796 | amdgpu_device_unlock_reset_domain(adev->reset_domain); | |
c9a6b82f AG |
5797 | } |
5798 | ||
5799 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
5800 | } | |
5801 | ||
5802 | /** | |
5803 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
5804 | * @pdev: pointer to PCI device | |
5805 | * | |
5806 | * Called when the error recovery driver tells us that its | |
505199a3 | 5807 | * OK to resume normal operation. |
c9a6b82f AG |
5808 | */ |
5809 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
5810 | { | |
5811 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5812 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5813 | int i; |
c9a6b82f | 5814 | |
c9a6b82f AG |
5815 | |
5816 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca | 5817 | |
e17e27f9 GC |
5818 | /* Only continue execution for the case of pci_channel_io_frozen */ |
5819 | if (adev->pci_channel_state != pci_channel_io_frozen) | |
5820 | return; | |
5821 | ||
acd89fca AG |
5822 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5823 | struct amdgpu_ring *ring = adev->rings[i]; | |
5824 | ||
5825 | if (!ring || !ring->sched.thread) | |
5826 | continue; | |
5827 | ||
acd89fca AG |
5828 | drm_sched_start(&ring->sched, true); |
5829 | } | |
5830 | ||
e923be99 AG |
5831 | amdgpu_device_unset_mp1_state(adev); |
5832 | amdgpu_device_unlock_reset_domain(adev->reset_domain); | |
c9a6b82f | 5833 | } |
c1dd4aa6 AG |
5834 | |
5835 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
5836 | { | |
5837 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5838 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5839 | int r; | |
5840 | ||
5841 | r = pci_save_state(pdev); | |
5842 | if (!r) { | |
5843 | kfree(adev->pci_state); | |
5844 | ||
5845 | adev->pci_state = pci_store_saved_state(pdev); | |
5846 | ||
5847 | if (!adev->pci_state) { | |
5848 | DRM_ERROR("Failed to store PCI saved state"); | |
5849 | return false; | |
5850 | } | |
5851 | } else { | |
5852 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
5853 | return false; | |
5854 | } | |
5855 | ||
5856 | return true; | |
5857 | } | |
5858 | ||
5859 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
5860 | { | |
5861 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5862 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5863 | int r; | |
5864 | ||
5865 | if (!adev->pci_state) | |
5866 | return false; | |
5867 | ||
5868 | r = pci_load_saved_state(pdev, adev->pci_state); | |
5869 | ||
5870 | if (!r) { | |
5871 | pci_restore_state(pdev); | |
5872 | } else { | |
5873 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
5874 | return false; | |
5875 | } | |
5876 | ||
5877 | return true; | |
5878 | } | |
5879 | ||
810085dd EH |
5880 | void amdgpu_device_flush_hdp(struct amdgpu_device *adev, |
5881 | struct amdgpu_ring *ring) | |
5882 | { | |
5883 | #ifdef CONFIG_X86_64 | |
b818a5d3 | 5884 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
5885 | return; |
5886 | #endif | |
5887 | if (adev->gmc.xgmi.connected_to_cpu) | |
5888 | return; | |
5889 | ||
5890 | if (ring && ring->funcs->emit_hdp_flush) | |
5891 | amdgpu_ring_emit_hdp_flush(ring); | |
5892 | else | |
5893 | amdgpu_asic_flush_hdp(adev, ring); | |
5894 | } | |
c1dd4aa6 | 5895 | |
810085dd EH |
5896 | void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, |
5897 | struct amdgpu_ring *ring) | |
5898 | { | |
5899 | #ifdef CONFIG_X86_64 | |
b818a5d3 | 5900 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
5901 | return; |
5902 | #endif | |
5903 | if (adev->gmc.xgmi.connected_to_cpu) | |
5904 | return; | |
c1dd4aa6 | 5905 | |
810085dd EH |
5906 | amdgpu_asic_invalidate_hdp(adev, ring); |
5907 | } | |
34f3a4a9 | 5908 | |
89a7a870 AG |
5909 | int amdgpu_in_reset(struct amdgpu_device *adev) |
5910 | { | |
5911 | return atomic_read(&adev->reset_domain->in_gpu_reset); | |
53a17b6b TZ |
5912 | } |
5913 | ||
34f3a4a9 LY |
5914 | /** |
5915 | * amdgpu_device_halt() - bring hardware to some kind of halt state | |
5916 | * | |
5917 | * @adev: amdgpu_device pointer | |
5918 | * | |
5919 | * Bring hardware to some kind of halt state so that no one can touch it | |
5920 | * any more. It will help to maintain error context when error occurred. | |
5921 | * Compare to a simple hang, the system will keep stable at least for SSH | |
5922 | * access. Then it should be trivial to inspect the hardware state and | |
5923 | * see what's going on. Implemented as following: | |
5924 | * | |
5925 | * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc), | |
5926 | * clears all CPU mappings to device, disallows remappings through page faults | |
5927 | * 2. amdgpu_irq_disable_all() disables all interrupts | |
5928 | * 3. amdgpu_fence_driver_hw_fini() signals all HW fences | |
5929 | * 4. set adev->no_hw_access to avoid potential crashes after setp 5 | |
5930 | * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings | |
5931 | * 6. pci_disable_device() and pci_wait_for_pending_transaction() | |
5932 | * flush any in flight DMA operations | |
5933 | */ | |
5934 | void amdgpu_device_halt(struct amdgpu_device *adev) | |
5935 | { | |
5936 | struct pci_dev *pdev = adev->pdev; | |
e0f943b4 | 5937 | struct drm_device *ddev = adev_to_drm(adev); |
34f3a4a9 | 5938 | |
2c1c7ba4 | 5939 | amdgpu_xcp_dev_unplug(adev); |
34f3a4a9 LY |
5940 | drm_dev_unplug(ddev); |
5941 | ||
5942 | amdgpu_irq_disable_all(adev); | |
5943 | ||
5944 | amdgpu_fence_driver_hw_fini(adev); | |
5945 | ||
5946 | adev->no_hw_access = true; | |
5947 | ||
5948 | amdgpu_device_unmap_mmio(adev); | |
5949 | ||
5950 | pci_disable_device(pdev); | |
5951 | pci_wait_for_pending_transaction(pdev); | |
5952 | } | |
86700a40 XD |
5953 | |
5954 | u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, | |
5955 | u32 reg) | |
5956 | { | |
5957 | unsigned long flags, address, data; | |
5958 | u32 r; | |
5959 | ||
5960 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
5961 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
5962 | ||
5963 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
5964 | WREG32(address, reg * 4); | |
5965 | (void)RREG32(address); | |
5966 | r = RREG32(data); | |
5967 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
5968 | return r; | |
5969 | } | |
5970 | ||
5971 | void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, | |
5972 | u32 reg, u32 v) | |
5973 | { | |
5974 | unsigned long flags, address, data; | |
5975 | ||
5976 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
5977 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
5978 | ||
5979 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
5980 | WREG32(address, reg * 4); | |
5981 | (void)RREG32(address); | |
5982 | WREG32(data, v); | |
5983 | (void)RREG32(data); | |
5984 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
5985 | } | |
68ce8b24 CK |
5986 | |
5987 | /** | |
5988 | * amdgpu_device_switch_gang - switch to a new gang | |
5989 | * @adev: amdgpu_device pointer | |
5990 | * @gang: the gang to switch to | |
5991 | * | |
5992 | * Try to switch to a new gang. | |
5993 | * Returns: NULL if we switched to the new gang or a reference to the current | |
5994 | * gang leader. | |
5995 | */ | |
5996 | struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, | |
5997 | struct dma_fence *gang) | |
5998 | { | |
5999 | struct dma_fence *old = NULL; | |
6000 | ||
6001 | do { | |
6002 | dma_fence_put(old); | |
6003 | rcu_read_lock(); | |
6004 | old = dma_fence_get_rcu_safe(&adev->gang_submit); | |
6005 | rcu_read_unlock(); | |
6006 | ||
6007 | if (old == gang) | |
6008 | break; | |
6009 | ||
6010 | if (!dma_fence_is_signaled(old)) | |
6011 | return old; | |
6012 | ||
6013 | } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit, | |
6014 | old, gang) != old); | |
6015 | ||
6016 | dma_fence_put(old); | |
6017 | return NULL; | |
6018 | } | |
220c8cc8 AD |
6019 | |
6020 | bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev) | |
6021 | { | |
6022 | switch (adev->asic_type) { | |
6023 | #ifdef CONFIG_DRM_AMDGPU_SI | |
6024 | case CHIP_HAINAN: | |
6025 | #endif | |
6026 | case CHIP_TOPAZ: | |
6027 | /* chips with no display hardware */ | |
6028 | return false; | |
6029 | #ifdef CONFIG_DRM_AMDGPU_SI | |
6030 | case CHIP_TAHITI: | |
6031 | case CHIP_PITCAIRN: | |
6032 | case CHIP_VERDE: | |
6033 | case CHIP_OLAND: | |
6034 | #endif | |
6035 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
6036 | case CHIP_BONAIRE: | |
6037 | case CHIP_HAWAII: | |
6038 | case CHIP_KAVERI: | |
6039 | case CHIP_KABINI: | |
6040 | case CHIP_MULLINS: | |
6041 | #endif | |
6042 | case CHIP_TONGA: | |
6043 | case CHIP_FIJI: | |
6044 | case CHIP_POLARIS10: | |
6045 | case CHIP_POLARIS11: | |
6046 | case CHIP_POLARIS12: | |
6047 | case CHIP_VEGAM: | |
6048 | case CHIP_CARRIZO: | |
6049 | case CHIP_STONEY: | |
6050 | /* chips with display hardware */ | |
6051 | return true; | |
6052 | default: | |
6053 | /* IP discovery */ | |
6054 | if (!adev->ip_versions[DCE_HWIP][0] || | |
6055 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) | |
6056 | return false; | |
6057 | return true; | |
6058 | } | |
6059 | } | |
81283fee JZ |
6060 | |
6061 | uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, | |
6062 | uint32_t inst, uint32_t reg_addr, char reg_name[], | |
6063 | uint32_t expected_value, uint32_t mask) | |
6064 | { | |
6065 | uint32_t ret = 0; | |
6066 | uint32_t old_ = 0; | |
6067 | uint32_t tmp_ = RREG32(reg_addr); | |
6068 | uint32_t loop = adev->usec_timeout; | |
6069 | ||
6070 | while ((tmp_ & (mask)) != (expected_value)) { | |
6071 | if (old_ != tmp_) { | |
6072 | loop = adev->usec_timeout; | |
6073 | old_ = tmp_; | |
6074 | } else | |
6075 | udelay(1); | |
6076 | tmp_ = RREG32(reg_addr); | |
6077 | loop--; | |
6078 | if (!loop) { | |
6079 | DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn", | |
6080 | inst, reg_name, (uint32_t)expected_value, | |
6081 | (uint32_t)(tmp_ & (mask))); | |
6082 | ret = -ETIMEDOUT; | |
6083 | break; | |
6084 | } | |
6085 | } | |
6086 | return ret; | |
6087 | } |