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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
d38ceaf9 AD |
30 | #include <linux/console.h> |
31 | #include <linux/slab.h> | |
d38ceaf9 AD |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
d38ceaf9 AD |
35 | #include <drm/amdgpu_drm.h> |
36 | #include <linux/vgaarb.h> | |
37 | #include <linux/vga_switcheroo.h> | |
38 | #include <linux/efi.h> | |
39 | #include "amdgpu.h" | |
f4b373f4 | 40 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
41 | #include "amdgpu_i2c.h" |
42 | #include "atom.h" | |
43 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 44 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 45 | #include "amd_pcie.h" |
33f34802 KW |
46 | #ifdef CONFIG_DRM_AMDGPU_SI |
47 | #include "si.h" | |
48 | #endif | |
a2e73f56 AD |
49 | #ifdef CONFIG_DRM_AMDGPU_CIK |
50 | #include "cik.h" | |
51 | #endif | |
aaa36a97 | 52 | #include "vi.h" |
460826e6 | 53 | #include "soc15.h" |
d38ceaf9 | 54 | #include "bif/bif_4_1_d.h" |
9accf2fd | 55 | #include <linux/pci.h> |
bec86378 | 56 | #include <linux/firmware.h> |
89041940 | 57 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 58 | |
ba997709 | 59 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 60 | #include "amdgpu_pm.h" |
d38ceaf9 | 61 | |
e2a75f88 | 62 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 63 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 64 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
e2a75f88 | 65 | |
2dc80b00 S |
66 | #define AMDGPU_RESUME_MS 2000 |
67 | ||
d38ceaf9 | 68 | static const char *amdgpu_asic_name[] = { |
da69c161 KW |
69 | "TAHITI", |
70 | "PITCAIRN", | |
71 | "VERDE", | |
72 | "OLAND", | |
73 | "HAINAN", | |
d38ceaf9 AD |
74 | "BONAIRE", |
75 | "KAVERI", | |
76 | "KABINI", | |
77 | "HAWAII", | |
78 | "MULLINS", | |
79 | "TOPAZ", | |
80 | "TONGA", | |
48299f95 | 81 | "FIJI", |
d38ceaf9 | 82 | "CARRIZO", |
139f4917 | 83 | "STONEY", |
2cc0c0b5 FC |
84 | "POLARIS10", |
85 | "POLARIS11", | |
c4642a47 | 86 | "POLARIS12", |
48ff108d | 87 | "VEGAM", |
d4196f01 | 88 | "VEGA10", |
8fab806a | 89 | "VEGA12", |
956fcddc | 90 | "VEGA20", |
2ca8a5d2 | 91 | "RAVEN", |
d38ceaf9 AD |
92 | "LAST", |
93 | }; | |
94 | ||
5494d864 AD |
95 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
96 | ||
e3ecdffa AD |
97 | /** |
98 | * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control | |
99 | * | |
100 | * @dev: drm_device pointer | |
101 | * | |
102 | * Returns true if the device is a dGPU with HG/PX power control, | |
103 | * otherwise return false. | |
104 | */ | |
d38ceaf9 AD |
105 | bool amdgpu_device_is_px(struct drm_device *dev) |
106 | { | |
107 | struct amdgpu_device *adev = dev->dev_private; | |
108 | ||
2f7d10b3 | 109 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
110 | return true; |
111 | return false; | |
112 | } | |
113 | ||
114 | /* | |
115 | * MMIO register access helper functions. | |
116 | */ | |
e3ecdffa AD |
117 | /** |
118 | * amdgpu_mm_rreg - read a memory mapped IO register | |
119 | * | |
120 | * @adev: amdgpu_device pointer | |
121 | * @reg: dword aligned register offset | |
122 | * @acc_flags: access flags which require special behavior | |
123 | * | |
124 | * Returns the 32 bit value from the offset specified. | |
125 | */ | |
d38ceaf9 | 126 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
15d72fd7 | 127 | uint32_t acc_flags) |
d38ceaf9 | 128 | { |
f4b373f4 TSD |
129 | uint32_t ret; |
130 | ||
43ca8efa | 131 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 132 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 133 | |
15d72fd7 | 134 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 135 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
136 | else { |
137 | unsigned long flags; | |
d38ceaf9 AD |
138 | |
139 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
140 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
141 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
142 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 143 | } |
f4b373f4 TSD |
144 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
145 | return ret; | |
d38ceaf9 AD |
146 | } |
147 | ||
421a2a30 ML |
148 | /* |
149 | * MMIO register read with bytes helper functions | |
150 | * @offset:bytes offset from MMIO start | |
151 | * | |
152 | */ | |
153 | ||
e3ecdffa AD |
154 | /** |
155 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
156 | * | |
157 | * @adev: amdgpu_device pointer | |
158 | * @offset: byte aligned register offset | |
159 | * | |
160 | * Returns the 8 bit value from the offset specified. | |
161 | */ | |
421a2a30 ML |
162 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
163 | if (offset < adev->rmmio_size) | |
164 | return (readb(adev->rmmio + offset)); | |
165 | BUG(); | |
166 | } | |
167 | ||
168 | /* | |
169 | * MMIO register write with bytes helper functions | |
170 | * @offset:bytes offset from MMIO start | |
171 | * @value: the value want to be written to the register | |
172 | * | |
173 | */ | |
e3ecdffa AD |
174 | /** |
175 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
176 | * | |
177 | * @adev: amdgpu_device pointer | |
178 | * @offset: byte aligned register offset | |
179 | * @value: 8 bit value to write | |
180 | * | |
181 | * Writes the value specified to the offset specified. | |
182 | */ | |
421a2a30 ML |
183 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
184 | if (offset < adev->rmmio_size) | |
185 | writeb(value, adev->rmmio + offset); | |
186 | else | |
187 | BUG(); | |
188 | } | |
189 | ||
e3ecdffa AD |
190 | /** |
191 | * amdgpu_mm_wreg - write to a memory mapped IO register | |
192 | * | |
193 | * @adev: amdgpu_device pointer | |
194 | * @reg: dword aligned register offset | |
195 | * @v: 32 bit value to write to the register | |
196 | * @acc_flags: access flags which require special behavior | |
197 | * | |
198 | * Writes the value specified to the offset specified. | |
199 | */ | |
d38ceaf9 | 200 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 201 | uint32_t acc_flags) |
d38ceaf9 | 202 | { |
f4b373f4 | 203 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 204 | |
47ed4e1c KW |
205 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
206 | adev->last_mm_index = v; | |
207 | } | |
208 | ||
43ca8efa | 209 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 210 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 211 | |
15d72fd7 | 212 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
213 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
214 | else { | |
215 | unsigned long flags; | |
216 | ||
217 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
218 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
219 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
220 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
221 | } | |
47ed4e1c KW |
222 | |
223 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
224 | udelay(500); | |
225 | } | |
d38ceaf9 AD |
226 | } |
227 | ||
e3ecdffa AD |
228 | /** |
229 | * amdgpu_io_rreg - read an IO register | |
230 | * | |
231 | * @adev: amdgpu_device pointer | |
232 | * @reg: dword aligned register offset | |
233 | * | |
234 | * Returns the 32 bit value from the offset specified. | |
235 | */ | |
d38ceaf9 AD |
236 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
237 | { | |
238 | if ((reg * 4) < adev->rio_mem_size) | |
239 | return ioread32(adev->rio_mem + (reg * 4)); | |
240 | else { | |
241 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
242 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
243 | } | |
244 | } | |
245 | ||
e3ecdffa AD |
246 | /** |
247 | * amdgpu_io_wreg - write to an IO register | |
248 | * | |
249 | * @adev: amdgpu_device pointer | |
250 | * @reg: dword aligned register offset | |
251 | * @v: 32 bit value to write to the register | |
252 | * | |
253 | * Writes the value specified to the offset specified. | |
254 | */ | |
d38ceaf9 AD |
255 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
256 | { | |
47ed4e1c KW |
257 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
258 | adev->last_mm_index = v; | |
259 | } | |
d38ceaf9 AD |
260 | |
261 | if ((reg * 4) < adev->rio_mem_size) | |
262 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
263 | else { | |
264 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
265 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
266 | } | |
47ed4e1c KW |
267 | |
268 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
269 | udelay(500); | |
270 | } | |
d38ceaf9 AD |
271 | } |
272 | ||
273 | /** | |
274 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
275 | * | |
276 | * @adev: amdgpu_device pointer | |
277 | * @index: doorbell index | |
278 | * | |
279 | * Returns the value in the doorbell aperture at the | |
280 | * requested doorbell index (CIK). | |
281 | */ | |
282 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
283 | { | |
284 | if (index < adev->doorbell.num_doorbells) { | |
285 | return readl(adev->doorbell.ptr + index); | |
286 | } else { | |
287 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
288 | return 0; | |
289 | } | |
290 | } | |
291 | ||
292 | /** | |
293 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
294 | * | |
295 | * @adev: amdgpu_device pointer | |
296 | * @index: doorbell index | |
297 | * @v: value to write | |
298 | * | |
299 | * Writes @v to the doorbell aperture at the | |
300 | * requested doorbell index (CIK). | |
301 | */ | |
302 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
303 | { | |
304 | if (index < adev->doorbell.num_doorbells) { | |
305 | writel(v, adev->doorbell.ptr + index); | |
306 | } else { | |
307 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
308 | } | |
309 | } | |
310 | ||
832be404 KW |
311 | /** |
312 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
313 | * | |
314 | * @adev: amdgpu_device pointer | |
315 | * @index: doorbell index | |
316 | * | |
317 | * Returns the value in the doorbell aperture at the | |
318 | * requested doorbell index (VEGA10+). | |
319 | */ | |
320 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
321 | { | |
322 | if (index < adev->doorbell.num_doorbells) { | |
323 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
324 | } else { | |
325 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
326 | return 0; | |
327 | } | |
328 | } | |
329 | ||
330 | /** | |
331 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
332 | * | |
333 | * @adev: amdgpu_device pointer | |
334 | * @index: doorbell index | |
335 | * @v: value to write | |
336 | * | |
337 | * Writes @v to the doorbell aperture at the | |
338 | * requested doorbell index (VEGA10+). | |
339 | */ | |
340 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
341 | { | |
342 | if (index < adev->doorbell.num_doorbells) { | |
343 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
344 | } else { | |
345 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
346 | } | |
347 | } | |
348 | ||
d38ceaf9 AD |
349 | /** |
350 | * amdgpu_invalid_rreg - dummy reg read function | |
351 | * | |
352 | * @adev: amdgpu device pointer | |
353 | * @reg: offset of register | |
354 | * | |
355 | * Dummy register read function. Used for register blocks | |
356 | * that certain asics don't have (all asics). | |
357 | * Returns the value in the register. | |
358 | */ | |
359 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
360 | { | |
361 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
362 | BUG(); | |
363 | return 0; | |
364 | } | |
365 | ||
366 | /** | |
367 | * amdgpu_invalid_wreg - dummy reg write function | |
368 | * | |
369 | * @adev: amdgpu device pointer | |
370 | * @reg: offset of register | |
371 | * @v: value to write to the register | |
372 | * | |
373 | * Dummy register read function. Used for register blocks | |
374 | * that certain asics don't have (all asics). | |
375 | */ | |
376 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
377 | { | |
378 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
379 | reg, v); | |
380 | BUG(); | |
381 | } | |
382 | ||
383 | /** | |
384 | * amdgpu_block_invalid_rreg - dummy reg read function | |
385 | * | |
386 | * @adev: amdgpu device pointer | |
387 | * @block: offset of instance | |
388 | * @reg: offset of register | |
389 | * | |
390 | * Dummy register read function. Used for register blocks | |
391 | * that certain asics don't have (all asics). | |
392 | * Returns the value in the register. | |
393 | */ | |
394 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
395 | uint32_t block, uint32_t reg) | |
396 | { | |
397 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
398 | reg, block); | |
399 | BUG(); | |
400 | return 0; | |
401 | } | |
402 | ||
403 | /** | |
404 | * amdgpu_block_invalid_wreg - dummy reg write function | |
405 | * | |
406 | * @adev: amdgpu device pointer | |
407 | * @block: offset of instance | |
408 | * @reg: offset of register | |
409 | * @v: value to write to the register | |
410 | * | |
411 | * Dummy register read function. Used for register blocks | |
412 | * that certain asics don't have (all asics). | |
413 | */ | |
414 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
415 | uint32_t block, | |
416 | uint32_t reg, uint32_t v) | |
417 | { | |
418 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
419 | reg, block, v); | |
420 | BUG(); | |
421 | } | |
422 | ||
e3ecdffa AD |
423 | /** |
424 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
425 | * | |
426 | * @adev: amdgpu device pointer | |
427 | * | |
428 | * Allocates a scratch page of VRAM for use by various things in the | |
429 | * driver. | |
430 | */ | |
06ec9070 | 431 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 432 | { |
a4a02777 CK |
433 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
434 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
435 | &adev->vram_scratch.robj, | |
436 | &adev->vram_scratch.gpu_addr, | |
437 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
438 | } |
439 | ||
e3ecdffa AD |
440 | /** |
441 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
442 | * | |
443 | * @adev: amdgpu device pointer | |
444 | * | |
445 | * Frees the VRAM scratch page. | |
446 | */ | |
06ec9070 | 447 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 448 | { |
078af1a3 | 449 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
450 | } |
451 | ||
452 | /** | |
9c3f2b54 | 453 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
454 | * |
455 | * @adev: amdgpu_device pointer | |
456 | * @registers: pointer to the register array | |
457 | * @array_size: size of the register array | |
458 | * | |
459 | * Programs an array or registers with and and or masks. | |
460 | * This is a helper for setting golden registers. | |
461 | */ | |
9c3f2b54 AD |
462 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
463 | const u32 *registers, | |
464 | const u32 array_size) | |
d38ceaf9 AD |
465 | { |
466 | u32 tmp, reg, and_mask, or_mask; | |
467 | int i; | |
468 | ||
469 | if (array_size % 3) | |
470 | return; | |
471 | ||
472 | for (i = 0; i < array_size; i +=3) { | |
473 | reg = registers[i + 0]; | |
474 | and_mask = registers[i + 1]; | |
475 | or_mask = registers[i + 2]; | |
476 | ||
477 | if (and_mask == 0xffffffff) { | |
478 | tmp = or_mask; | |
479 | } else { | |
480 | tmp = RREG32(reg); | |
481 | tmp &= ~and_mask; | |
482 | tmp |= or_mask; | |
483 | } | |
484 | WREG32(reg, tmp); | |
485 | } | |
486 | } | |
487 | ||
e3ecdffa AD |
488 | /** |
489 | * amdgpu_device_pci_config_reset - reset the GPU | |
490 | * | |
491 | * @adev: amdgpu_device pointer | |
492 | * | |
493 | * Resets the GPU using the pci config reset sequence. | |
494 | * Only applicable to asics prior to vega10. | |
495 | */ | |
8111c387 | 496 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
497 | { |
498 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
499 | } | |
500 | ||
501 | /* | |
502 | * GPU doorbell aperture helpers function. | |
503 | */ | |
504 | /** | |
06ec9070 | 505 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
506 | * |
507 | * @adev: amdgpu_device pointer | |
508 | * | |
509 | * Init doorbell driver information (CIK) | |
510 | * Returns 0 on success, error on failure. | |
511 | */ | |
06ec9070 | 512 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 513 | { |
705e519e CK |
514 | /* No doorbell on SI hardware generation */ |
515 | if (adev->asic_type < CHIP_BONAIRE) { | |
516 | adev->doorbell.base = 0; | |
517 | adev->doorbell.size = 0; | |
518 | adev->doorbell.num_doorbells = 0; | |
519 | adev->doorbell.ptr = NULL; | |
520 | return 0; | |
521 | } | |
522 | ||
d6895ad3 CK |
523 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
524 | return -EINVAL; | |
525 | ||
d38ceaf9 AD |
526 | /* doorbell bar mapping */ |
527 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
528 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
529 | ||
edf600da | 530 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
531 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
532 | if (adev->doorbell.num_doorbells == 0) | |
533 | return -EINVAL; | |
534 | ||
8972e5d2 CK |
535 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
536 | adev->doorbell.num_doorbells * | |
537 | sizeof(u32)); | |
538 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 539 | return -ENOMEM; |
d38ceaf9 AD |
540 | |
541 | return 0; | |
542 | } | |
543 | ||
544 | /** | |
06ec9070 | 545 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
546 | * |
547 | * @adev: amdgpu_device pointer | |
548 | * | |
549 | * Tear down doorbell driver information (CIK) | |
550 | */ | |
06ec9070 | 551 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
552 | { |
553 | iounmap(adev->doorbell.ptr); | |
554 | adev->doorbell.ptr = NULL; | |
555 | } | |
556 | ||
22cb0164 | 557 | |
d38ceaf9 AD |
558 | |
559 | /* | |
06ec9070 | 560 | * amdgpu_device_wb_*() |
455a7bc2 | 561 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 562 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
563 | */ |
564 | ||
565 | /** | |
06ec9070 | 566 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
567 | * |
568 | * @adev: amdgpu_device pointer | |
569 | * | |
570 | * Disables Writeback and frees the Writeback memory (all asics). | |
571 | * Used at driver shutdown. | |
572 | */ | |
06ec9070 | 573 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
574 | { |
575 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
576 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
577 | &adev->wb.gpu_addr, | |
578 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
579 | adev->wb.wb_obj = NULL; |
580 | } | |
581 | } | |
582 | ||
583 | /** | |
06ec9070 | 584 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
585 | * |
586 | * @adev: amdgpu_device pointer | |
587 | * | |
455a7bc2 | 588 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
589 | * Used at driver startup. |
590 | * Returns 0 on success or an -error on failure. | |
591 | */ | |
06ec9070 | 592 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
593 | { |
594 | int r; | |
595 | ||
596 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
597 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
598 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
599 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
600 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
601 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
602 | if (r) { |
603 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
604 | return r; | |
605 | } | |
d38ceaf9 AD |
606 | |
607 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
608 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
609 | ||
610 | /* clear wb memory */ | |
73469585 | 611 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
612 | } |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | /** | |
131b4b36 | 618 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
619 | * |
620 | * @adev: amdgpu_device pointer | |
621 | * @wb: wb index | |
622 | * | |
623 | * Allocate a wb slot for use by the driver (all asics). | |
624 | * Returns 0 on success or -EINVAL on failure. | |
625 | */ | |
131b4b36 | 626 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
627 | { |
628 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 629 | |
97407b63 | 630 | if (offset < adev->wb.num_wb) { |
7014285a | 631 | __set_bit(offset, adev->wb.used); |
63ae07ca | 632 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
633 | return 0; |
634 | } else { | |
635 | return -EINVAL; | |
636 | } | |
637 | } | |
638 | ||
d38ceaf9 | 639 | /** |
131b4b36 | 640 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
641 | * |
642 | * @adev: amdgpu_device pointer | |
643 | * @wb: wb index | |
644 | * | |
645 | * Free a wb slot allocated for use by the driver (all asics) | |
646 | */ | |
131b4b36 | 647 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 648 | { |
73469585 | 649 | wb >>= 3; |
d38ceaf9 | 650 | if (wb < adev->wb.num_wb) |
73469585 | 651 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
652 | } |
653 | ||
654 | /** | |
2543e28a | 655 | * amdgpu_device_vram_location - try to find VRAM location |
e3ecdffa | 656 | * |
d38ceaf9 AD |
657 | * @adev: amdgpu device structure holding all necessary informations |
658 | * @mc: memory controller structure holding memory informations | |
659 | * @base: base address at which to put VRAM | |
660 | * | |
455a7bc2 | 661 | * Function will try to place VRAM at base address provided |
3d647c8f | 662 | * as parameter. |
d38ceaf9 | 663 | */ |
2543e28a | 664 | void amdgpu_device_vram_location(struct amdgpu_device *adev, |
770d13b1 | 665 | struct amdgpu_gmc *mc, u64 base) |
d38ceaf9 AD |
666 | { |
667 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
668 | ||
669 | mc->vram_start = base; | |
d38ceaf9 AD |
670 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
671 | if (limit && limit < mc->real_vram_size) | |
672 | mc->real_vram_size = limit; | |
673 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
674 | mc->mc_vram_size >> 20, mc->vram_start, | |
675 | mc->vram_end, mc->real_vram_size >> 20); | |
676 | } | |
677 | ||
678 | /** | |
761f58e0 | 679 | * amdgpu_device_gart_location - try to find GART location |
e3ecdffa | 680 | * |
d38ceaf9 AD |
681 | * @adev: amdgpu device structure holding all necessary informations |
682 | * @mc: memory controller structure holding memory informations | |
683 | * | |
761f58e0 | 684 | * Function will place try to place GART before or after VRAM. |
d38ceaf9 | 685 | * |
761f58e0 | 686 | * If GART size is bigger than space left then we ajust GART size. |
d38ceaf9 | 687 | * Thus function will never fails. |
d38ceaf9 | 688 | */ |
2543e28a | 689 | void amdgpu_device_gart_location(struct amdgpu_device *adev, |
770d13b1 | 690 | struct amdgpu_gmc *mc) |
d38ceaf9 AD |
691 | { |
692 | u64 size_af, size_bf; | |
693 | ||
7951e376 RZ |
694 | mc->gart_size += adev->pm.smu_prv_buffer_size; |
695 | ||
770d13b1 | 696 | size_af = adev->gmc.mc_mask - mc->vram_end; |
ed21c047 | 697 | size_bf = mc->vram_start; |
d38ceaf9 | 698 | if (size_bf > size_af) { |
6f02a696 | 699 | if (mc->gart_size > size_bf) { |
761f58e0 | 700 | dev_warn(adev->dev, "limiting GART\n"); |
6f02a696 | 701 | mc->gart_size = size_bf; |
d38ceaf9 | 702 | } |
6f02a696 | 703 | mc->gart_start = 0; |
d38ceaf9 | 704 | } else { |
6f02a696 | 705 | if (mc->gart_size > size_af) { |
761f58e0 | 706 | dev_warn(adev->dev, "limiting GART\n"); |
6f02a696 | 707 | mc->gart_size = size_af; |
d38ceaf9 | 708 | } |
b98f1b9e CK |
709 | /* VCE doesn't like it when BOs cross a 4GB segment, so align |
710 | * the GART base on a 4GB boundary as well. | |
711 | */ | |
712 | mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL); | |
d38ceaf9 | 713 | } |
6f02a696 | 714 | mc->gart_end = mc->gart_start + mc->gart_size - 1; |
761f58e0 | 715 | dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", |
6f02a696 | 716 | mc->gart_size >> 20, mc->gart_start, mc->gart_end); |
d38ceaf9 AD |
717 | } |
718 | ||
d6895ad3 CK |
719 | /** |
720 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
721 | * | |
722 | * @adev: amdgpu_device pointer | |
723 | * | |
724 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
725 | * to fail, but if any of the BARs is not accessible after the size we abort | |
726 | * driver loading by returning -ENODEV. | |
727 | */ | |
728 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
729 | { | |
770d13b1 | 730 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 731 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
732 | struct pci_bus *root; |
733 | struct resource *res; | |
734 | unsigned i; | |
d6895ad3 CK |
735 | u16 cmd; |
736 | int r; | |
737 | ||
0c03b912 | 738 | /* Bypass for VF */ |
739 | if (amdgpu_sriov_vf(adev)) | |
740 | return 0; | |
741 | ||
31b8adab CK |
742 | /* Check if the root BUS has 64bit memory resources */ |
743 | root = adev->pdev->bus; | |
744 | while (root->parent) | |
745 | root = root->parent; | |
746 | ||
747 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 748 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
749 | res->start > 0x100000000ull) |
750 | break; | |
751 | } | |
752 | ||
753 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
754 | if (!res) | |
755 | return 0; | |
756 | ||
d6895ad3 CK |
757 | /* Disable memory decoding while we change the BAR addresses and size */ |
758 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
759 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
760 | cmd & ~PCI_COMMAND_MEMORY); | |
761 | ||
762 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 763 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
764 | if (adev->asic_type >= CHIP_BONAIRE) |
765 | pci_release_resource(adev->pdev, 2); | |
766 | ||
767 | pci_release_resource(adev->pdev, 0); | |
768 | ||
769 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
770 | if (r == -ENOSPC) | |
771 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
772 | else if (r && r != -ENOTSUPP) | |
773 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
774 | ||
775 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
776 | ||
777 | /* When the doorbell or fb BAR isn't available we have no chance of | |
778 | * using the device. | |
779 | */ | |
06ec9070 | 780 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
781 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
782 | return -ENODEV; | |
783 | ||
784 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
785 | ||
786 | return 0; | |
787 | } | |
a05502e5 | 788 | |
d38ceaf9 AD |
789 | /* |
790 | * GPU helpers function. | |
791 | */ | |
792 | /** | |
39c640c0 | 793 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
794 | * |
795 | * @adev: amdgpu_device pointer | |
796 | * | |
c836fec5 JQ |
797 | * Check if the asic has been initialized (all asics) at driver startup |
798 | * or post is needed if hw reset is performed. | |
799 | * Returns true if need or false if not. | |
d38ceaf9 | 800 | */ |
39c640c0 | 801 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
802 | { |
803 | uint32_t reg; | |
804 | ||
bec86378 ML |
805 | if (amdgpu_sriov_vf(adev)) |
806 | return false; | |
807 | ||
808 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
809 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
810 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
811 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
812 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
813 | */ |
814 | if (adev->asic_type == CHIP_FIJI) { | |
815 | int err; | |
816 | uint32_t fw_ver; | |
817 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
818 | /* force vPost if error occured */ | |
819 | if (err) | |
820 | return true; | |
821 | ||
822 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
823 | if (fw_ver < 0x00160e00) |
824 | return true; | |
bec86378 | 825 | } |
bec86378 | 826 | } |
91fe77eb | 827 | |
828 | if (adev->has_hw_reset) { | |
829 | adev->has_hw_reset = false; | |
830 | return true; | |
831 | } | |
832 | ||
833 | /* bios scratch used on CIK+ */ | |
834 | if (adev->asic_type >= CHIP_BONAIRE) | |
835 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
836 | ||
837 | /* check MEM_SIZE for older asics */ | |
838 | reg = amdgpu_asic_get_config_memsize(adev); | |
839 | ||
840 | if ((reg != 0) && (reg != 0xffffffff)) | |
841 | return false; | |
842 | ||
843 | return true; | |
bec86378 ML |
844 | } |
845 | ||
d38ceaf9 AD |
846 | /* if we get transitioned to only one device, take VGA back */ |
847 | /** | |
06ec9070 | 848 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
849 | * |
850 | * @cookie: amdgpu_device pointer | |
851 | * @state: enable/disable vga decode | |
852 | * | |
853 | * Enable/disable vga decode (all asics). | |
854 | * Returns VGA resource flags. | |
855 | */ | |
06ec9070 | 856 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
857 | { |
858 | struct amdgpu_device *adev = cookie; | |
859 | amdgpu_asic_set_vga_state(adev, state); | |
860 | if (state) | |
861 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
862 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
863 | else | |
864 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
865 | } | |
866 | ||
e3ecdffa AD |
867 | /** |
868 | * amdgpu_device_check_block_size - validate the vm block size | |
869 | * | |
870 | * @adev: amdgpu_device pointer | |
871 | * | |
872 | * Validates the vm block size specified via module parameter. | |
873 | * The vm block size defines number of bits in page table versus page directory, | |
874 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
875 | * page table and the remaining bits are in the page directory. | |
876 | */ | |
06ec9070 | 877 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
878 | { |
879 | /* defines number of bits in page table versus page directory, | |
880 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
881 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
882 | if (amdgpu_vm_block_size == -1) |
883 | return; | |
a1adf8be | 884 | |
bab4fee7 | 885 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
886 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
887 | amdgpu_vm_block_size); | |
97489129 | 888 | amdgpu_vm_block_size = -1; |
a1adf8be | 889 | } |
a1adf8be CZ |
890 | } |
891 | ||
e3ecdffa AD |
892 | /** |
893 | * amdgpu_device_check_vm_size - validate the vm size | |
894 | * | |
895 | * @adev: amdgpu_device pointer | |
896 | * | |
897 | * Validates the vm size in GB specified via module parameter. | |
898 | * The VM size is the size of the GPU virtual memory space in GB. | |
899 | */ | |
06ec9070 | 900 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 901 | { |
64dab074 AD |
902 | /* no need to check the default value */ |
903 | if (amdgpu_vm_size == -1) | |
904 | return; | |
905 | ||
83ca145d ZJ |
906 | if (amdgpu_vm_size < 1) { |
907 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
908 | amdgpu_vm_size); | |
f3368128 | 909 | amdgpu_vm_size = -1; |
83ca145d | 910 | } |
83ca145d ZJ |
911 | } |
912 | ||
7951e376 RZ |
913 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
914 | { | |
915 | struct sysinfo si; | |
916 | bool is_os_64 = (sizeof(void *) == 8) ? true : false; | |
917 | uint64_t total_memory; | |
918 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
919 | uint64_t dram_size_three_GB = 0xB8000000; | |
920 | ||
921 | if (amdgpu_smu_memory_pool_size == 0) | |
922 | return; | |
923 | ||
924 | if (!is_os_64) { | |
925 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
926 | goto def_value; | |
927 | } | |
928 | si_meminfo(&si); | |
929 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
930 | ||
931 | if ((amdgpu_smu_memory_pool_size == 1) || | |
932 | (amdgpu_smu_memory_pool_size == 2)) { | |
933 | if (total_memory < dram_size_three_GB) | |
934 | goto def_value1; | |
935 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
936 | (amdgpu_smu_memory_pool_size == 8)) { | |
937 | if (total_memory < dram_size_seven_GB) | |
938 | goto def_value1; | |
939 | } else { | |
940 | DRM_WARN("Smu memory pool size not supported\n"); | |
941 | goto def_value; | |
942 | } | |
943 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
944 | ||
945 | return; | |
946 | ||
947 | def_value1: | |
948 | DRM_WARN("No enough system memory\n"); | |
949 | def_value: | |
950 | adev->pm.smu_prv_buffer_size = 0; | |
951 | } | |
952 | ||
d38ceaf9 | 953 | /** |
06ec9070 | 954 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
955 | * |
956 | * @adev: amdgpu_device pointer | |
957 | * | |
958 | * Validates certain module parameters and updates | |
959 | * the associated values used by the driver (all asics). | |
960 | */ | |
06ec9070 | 961 | static void amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 962 | { |
5b011235 CZ |
963 | if (amdgpu_sched_jobs < 4) { |
964 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
965 | amdgpu_sched_jobs); | |
966 | amdgpu_sched_jobs = 4; | |
76117507 | 967 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
968 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
969 | amdgpu_sched_jobs); | |
970 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
971 | } | |
d38ceaf9 | 972 | |
83e74db6 | 973 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
974 | /* gart size must be greater or equal to 32M */ |
975 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
976 | amdgpu_gart_size); | |
83e74db6 | 977 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
978 | } |
979 | ||
36d38372 | 980 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 981 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
982 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
983 | amdgpu_gtt_size); | |
984 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
985 | } |
986 | ||
d07f14be RH |
987 | /* valid range is between 4 and 9 inclusive */ |
988 | if (amdgpu_vm_fragment_size != -1 && | |
989 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
990 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
991 | amdgpu_vm_fragment_size = -1; | |
992 | } | |
993 | ||
7951e376 RZ |
994 | amdgpu_device_check_smu_prv_buffer_size(adev); |
995 | ||
06ec9070 | 996 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 997 | |
06ec9070 | 998 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 999 | |
526bae37 | 1000 | if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || |
76117507 | 1001 | !is_power_of_2(amdgpu_vram_page_split))) { |
6a7f76e7 CK |
1002 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", |
1003 | amdgpu_vram_page_split); | |
1004 | amdgpu_vram_page_split = 1024; | |
1005 | } | |
8854695a AG |
1006 | |
1007 | if (amdgpu_lockup_timeout == 0) { | |
1008 | dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n"); | |
1009 | amdgpu_lockup_timeout = 10000; | |
1010 | } | |
19aede77 AD |
1011 | |
1012 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); | |
d38ceaf9 AD |
1013 | } |
1014 | ||
1015 | /** | |
1016 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1017 | * | |
1018 | * @pdev: pci dev pointer | |
1694467b | 1019 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1020 | * |
1021 | * Callback for the switcheroo driver. Suspends or resumes the | |
1022 | * the asics before or after it is powered up using ACPI methods. | |
1023 | */ | |
1024 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1025 | { | |
1026 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1027 | ||
1028 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1029 | return; | |
1030 | ||
1031 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1032 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1033 | /* don't suspend or resume card normally */ |
1034 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1035 | ||
810ddc3a | 1036 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1037 | |
d38ceaf9 AD |
1038 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1039 | drm_kms_helper_poll_enable(dev); | |
1040 | } else { | |
7ca85295 | 1041 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1042 | drm_kms_helper_poll_disable(dev); |
1043 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1044 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1045 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1046 | } | |
1047 | } | |
1048 | ||
1049 | /** | |
1050 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1051 | * | |
1052 | * @pdev: pci dev pointer | |
1053 | * | |
1054 | * Callback for the switcheroo driver. Check of the switcheroo | |
1055 | * state can be changed. | |
1056 | * Returns true if the state can be changed, false if not. | |
1057 | */ | |
1058 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1059 | { | |
1060 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1061 | ||
1062 | /* | |
1063 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1064 | * locking inversion with the driver load path. And the access here is | |
1065 | * completely racy anyway. So don't bother with locking for now. | |
1066 | */ | |
1067 | return dev->open_count == 0; | |
1068 | } | |
1069 | ||
1070 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1071 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1072 | .reprobe = NULL, | |
1073 | .can_switch = amdgpu_switcheroo_can_switch, | |
1074 | }; | |
1075 | ||
e3ecdffa AD |
1076 | /** |
1077 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1078 | * | |
87e3f136 | 1079 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1080 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1081 | * @state: clockgating state (gate or ungate) | |
1082 | * | |
1083 | * Sets the requested clockgating state for all instances of | |
1084 | * the hardware IP specified. | |
1085 | * Returns the error code from the last instance. | |
1086 | */ | |
43fa561f | 1087 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1088 | enum amd_ip_block_type block_type, |
1089 | enum amd_clockgating_state state) | |
d38ceaf9 | 1090 | { |
43fa561f | 1091 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1092 | int i, r = 0; |
1093 | ||
1094 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1095 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1096 | continue; |
c722865a RZ |
1097 | if (adev->ip_blocks[i].version->type != block_type) |
1098 | continue; | |
1099 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1100 | continue; | |
1101 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1102 | (void *)adev, state); | |
1103 | if (r) | |
1104 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1105 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1106 | } |
1107 | return r; | |
1108 | } | |
1109 | ||
e3ecdffa AD |
1110 | /** |
1111 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1112 | * | |
87e3f136 | 1113 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1114 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1115 | * @state: powergating state (gate or ungate) | |
1116 | * | |
1117 | * Sets the requested powergating state for all instances of | |
1118 | * the hardware IP specified. | |
1119 | * Returns the error code from the last instance. | |
1120 | */ | |
43fa561f | 1121 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1122 | enum amd_ip_block_type block_type, |
1123 | enum amd_powergating_state state) | |
d38ceaf9 | 1124 | { |
43fa561f | 1125 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1126 | int i, r = 0; |
1127 | ||
1128 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1129 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1130 | continue; |
c722865a RZ |
1131 | if (adev->ip_blocks[i].version->type != block_type) |
1132 | continue; | |
1133 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1134 | continue; | |
1135 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1136 | (void *)adev, state); | |
1137 | if (r) | |
1138 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1139 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1140 | } |
1141 | return r; | |
1142 | } | |
1143 | ||
e3ecdffa AD |
1144 | /** |
1145 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1146 | * | |
1147 | * @adev: amdgpu_device pointer | |
1148 | * @flags: clockgating feature flags | |
1149 | * | |
1150 | * Walks the list of IPs on the device and updates the clockgating | |
1151 | * flags for each IP. | |
1152 | * Updates @flags with the feature flags for each hardware IP where | |
1153 | * clockgating is enabled. | |
1154 | */ | |
2990a1fc AD |
1155 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1156 | u32 *flags) | |
6cb2d4e4 HR |
1157 | { |
1158 | int i; | |
1159 | ||
1160 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1161 | if (!adev->ip_blocks[i].status.valid) | |
1162 | continue; | |
1163 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1164 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1165 | } | |
1166 | } | |
1167 | ||
e3ecdffa AD |
1168 | /** |
1169 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1170 | * | |
1171 | * @adev: amdgpu_device pointer | |
1172 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1173 | * | |
1174 | * Waits for the request hardware IP to be idle. | |
1175 | * Returns 0 for success or a negative error code on failure. | |
1176 | */ | |
2990a1fc AD |
1177 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1178 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1179 | { |
1180 | int i, r; | |
1181 | ||
1182 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1183 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1184 | continue; |
a1255107 AD |
1185 | if (adev->ip_blocks[i].version->type == block_type) { |
1186 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1187 | if (r) |
1188 | return r; | |
1189 | break; | |
1190 | } | |
1191 | } | |
1192 | return 0; | |
1193 | ||
1194 | } | |
1195 | ||
e3ecdffa AD |
1196 | /** |
1197 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1198 | * | |
1199 | * @adev: amdgpu_device pointer | |
1200 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1201 | * | |
1202 | * Check if the hardware IP is idle or not. | |
1203 | * Returns true if it the IP is idle, false if not. | |
1204 | */ | |
2990a1fc AD |
1205 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1206 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1207 | { |
1208 | int i; | |
1209 | ||
1210 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1211 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1212 | continue; |
a1255107 AD |
1213 | if (adev->ip_blocks[i].version->type == block_type) |
1214 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1215 | } |
1216 | return true; | |
1217 | ||
1218 | } | |
1219 | ||
e3ecdffa AD |
1220 | /** |
1221 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1222 | * | |
1223 | * @adev: amdgpu_device pointer | |
87e3f136 | 1224 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1225 | * |
1226 | * Returns a pointer to the hardware IP block structure | |
1227 | * if it exists for the asic, otherwise NULL. | |
1228 | */ | |
2990a1fc AD |
1229 | struct amdgpu_ip_block * |
1230 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1231 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1232 | { |
1233 | int i; | |
1234 | ||
1235 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1236 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1237 | return &adev->ip_blocks[i]; |
1238 | ||
1239 | return NULL; | |
1240 | } | |
1241 | ||
1242 | /** | |
2990a1fc | 1243 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1244 | * |
1245 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1246 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1247 | * @major: major version |
1248 | * @minor: minor version | |
1249 | * | |
1250 | * return 0 if equal or greater | |
1251 | * return 1 if smaller or the ip_block doesn't exist | |
1252 | */ | |
2990a1fc AD |
1253 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1254 | enum amd_ip_block_type type, | |
1255 | u32 major, u32 minor) | |
d38ceaf9 | 1256 | { |
2990a1fc | 1257 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1258 | |
a1255107 AD |
1259 | if (ip_block && ((ip_block->version->major > major) || |
1260 | ((ip_block->version->major == major) && | |
1261 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1262 | return 0; |
1263 | ||
1264 | return 1; | |
1265 | } | |
1266 | ||
a1255107 | 1267 | /** |
2990a1fc | 1268 | * amdgpu_device_ip_block_add |
a1255107 AD |
1269 | * |
1270 | * @adev: amdgpu_device pointer | |
1271 | * @ip_block_version: pointer to the IP to add | |
1272 | * | |
1273 | * Adds the IP block driver information to the collection of IPs | |
1274 | * on the asic. | |
1275 | */ | |
2990a1fc AD |
1276 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1277 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1278 | { |
1279 | if (!ip_block_version) | |
1280 | return -EINVAL; | |
1281 | ||
e966a725 | 1282 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1283 | ip_block_version->funcs->name); |
1284 | ||
a1255107 AD |
1285 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
e3ecdffa AD |
1290 | /** |
1291 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1292 | * | |
1293 | * @adev: amdgpu_device pointer | |
1294 | * | |
1295 | * Enabled the virtual display feature if the user has enabled it via | |
1296 | * the module parameter virtual_display. This feature provides a virtual | |
1297 | * display hardware on headless boards or in virtualized environments. | |
1298 | * This function parses and validates the configuration string specified by | |
1299 | * the user and configues the virtual display configuration (number of | |
1300 | * virtual connectors, crtcs, etc.) specified. | |
1301 | */ | |
483ef985 | 1302 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1303 | { |
1304 | adev->enable_virtual_display = false; | |
1305 | ||
1306 | if (amdgpu_virtual_display) { | |
1307 | struct drm_device *ddev = adev->ddev; | |
1308 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1309 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1310 | |
1311 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1312 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1313 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1314 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1315 | if (!strcmp("all", pciaddname) |
1316 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1317 | long num_crtc; |
1318 | int res = -1; | |
1319 | ||
9accf2fd | 1320 | adev->enable_virtual_display = true; |
0f66356d ED |
1321 | |
1322 | if (pciaddname_tmp) | |
1323 | res = kstrtol(pciaddname_tmp, 10, | |
1324 | &num_crtc); | |
1325 | ||
1326 | if (!res) { | |
1327 | if (num_crtc < 1) | |
1328 | num_crtc = 1; | |
1329 | if (num_crtc > 6) | |
1330 | num_crtc = 6; | |
1331 | adev->mode_info.num_crtc = num_crtc; | |
1332 | } else { | |
1333 | adev->mode_info.num_crtc = 1; | |
1334 | } | |
9accf2fd ED |
1335 | break; |
1336 | } | |
1337 | } | |
1338 | ||
0f66356d ED |
1339 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1340 | amdgpu_virtual_display, pci_address_name, | |
1341 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1342 | |
1343 | kfree(pciaddstr); | |
1344 | } | |
1345 | } | |
1346 | ||
e3ecdffa AD |
1347 | /** |
1348 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1349 | * | |
1350 | * @adev: amdgpu_device pointer | |
1351 | * | |
1352 | * Parses the asic configuration parameters specified in the gpu info | |
1353 | * firmware and makes them availale to the driver for use in configuring | |
1354 | * the asic. | |
1355 | * Returns 0 on success, -EINVAL on failure. | |
1356 | */ | |
e2a75f88 AD |
1357 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1358 | { | |
e2a75f88 AD |
1359 | const char *chip_name; |
1360 | char fw_name[30]; | |
1361 | int err; | |
1362 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1363 | ||
ab4fe3e1 HR |
1364 | adev->firmware.gpu_info_fw = NULL; |
1365 | ||
e2a75f88 AD |
1366 | switch (adev->asic_type) { |
1367 | case CHIP_TOPAZ: | |
1368 | case CHIP_TONGA: | |
1369 | case CHIP_FIJI: | |
e2a75f88 | 1370 | case CHIP_POLARIS10: |
cc07f18d | 1371 | case CHIP_POLARIS11: |
e2a75f88 | 1372 | case CHIP_POLARIS12: |
cc07f18d | 1373 | case CHIP_VEGAM: |
e2a75f88 AD |
1374 | case CHIP_CARRIZO: |
1375 | case CHIP_STONEY: | |
1376 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1377 | case CHIP_VERDE: | |
1378 | case CHIP_TAHITI: | |
1379 | case CHIP_PITCAIRN: | |
1380 | case CHIP_OLAND: | |
1381 | case CHIP_HAINAN: | |
1382 | #endif | |
1383 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1384 | case CHIP_BONAIRE: | |
1385 | case CHIP_HAWAII: | |
1386 | case CHIP_KAVERI: | |
1387 | case CHIP_KABINI: | |
1388 | case CHIP_MULLINS: | |
1389 | #endif | |
27c0bc71 | 1390 | case CHIP_VEGA20: |
e2a75f88 AD |
1391 | default: |
1392 | return 0; | |
1393 | case CHIP_VEGA10: | |
1394 | chip_name = "vega10"; | |
1395 | break; | |
3f76dced AD |
1396 | case CHIP_VEGA12: |
1397 | chip_name = "vega12"; | |
1398 | break; | |
2d2e5e7e AD |
1399 | case CHIP_RAVEN: |
1400 | chip_name = "raven"; | |
1401 | break; | |
e2a75f88 AD |
1402 | } |
1403 | ||
1404 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1405 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1406 | if (err) { |
1407 | dev_err(adev->dev, | |
1408 | "Failed to load gpu_info firmware \"%s\"\n", | |
1409 | fw_name); | |
1410 | goto out; | |
1411 | } | |
ab4fe3e1 | 1412 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1413 | if (err) { |
1414 | dev_err(adev->dev, | |
1415 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1416 | fw_name); | |
1417 | goto out; | |
1418 | } | |
1419 | ||
ab4fe3e1 | 1420 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1421 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1422 | ||
1423 | switch (hdr->version_major) { | |
1424 | case 1: | |
1425 | { | |
1426 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1427 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1428 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1429 | ||
b5ab16bf AD |
1430 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1431 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1432 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1433 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1434 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1435 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1436 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1437 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1438 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1439 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1440 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1441 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1442 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1443 | adev->gfx.cu_info.max_waves_per_simd = |
1444 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1445 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1446 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1447 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1448 | break; |
1449 | } | |
1450 | default: | |
1451 | dev_err(adev->dev, | |
1452 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1453 | err = -EINVAL; | |
1454 | goto out; | |
1455 | } | |
1456 | out: | |
e2a75f88 AD |
1457 | return err; |
1458 | } | |
1459 | ||
e3ecdffa AD |
1460 | /** |
1461 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1462 | * | |
1463 | * @adev: amdgpu_device pointer | |
1464 | * | |
1465 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1466 | * up each asic are discovered each IP's early_init callback is run. This | |
1467 | * is the first stage in initializing the asic. | |
1468 | * Returns 0 on success, negative error code on failure. | |
1469 | */ | |
06ec9070 | 1470 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1471 | { |
aaa36a97 | 1472 | int i, r; |
d38ceaf9 | 1473 | |
483ef985 | 1474 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1475 | |
d38ceaf9 | 1476 | switch (adev->asic_type) { |
aaa36a97 AD |
1477 | case CHIP_TOPAZ: |
1478 | case CHIP_TONGA: | |
48299f95 | 1479 | case CHIP_FIJI: |
2cc0c0b5 | 1480 | case CHIP_POLARIS10: |
32cc7e53 | 1481 | case CHIP_POLARIS11: |
c4642a47 | 1482 | case CHIP_POLARIS12: |
32cc7e53 | 1483 | case CHIP_VEGAM: |
aaa36a97 | 1484 | case CHIP_CARRIZO: |
39bb0c92 SL |
1485 | case CHIP_STONEY: |
1486 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1487 | adev->family = AMDGPU_FAMILY_CZ; |
1488 | else | |
1489 | adev->family = AMDGPU_FAMILY_VI; | |
1490 | ||
1491 | r = vi_set_ip_blocks(adev); | |
1492 | if (r) | |
1493 | return r; | |
1494 | break; | |
33f34802 KW |
1495 | #ifdef CONFIG_DRM_AMDGPU_SI |
1496 | case CHIP_VERDE: | |
1497 | case CHIP_TAHITI: | |
1498 | case CHIP_PITCAIRN: | |
1499 | case CHIP_OLAND: | |
1500 | case CHIP_HAINAN: | |
295d0daf | 1501 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1502 | r = si_set_ip_blocks(adev); |
1503 | if (r) | |
1504 | return r; | |
1505 | break; | |
1506 | #endif | |
a2e73f56 AD |
1507 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1508 | case CHIP_BONAIRE: | |
1509 | case CHIP_HAWAII: | |
1510 | case CHIP_KAVERI: | |
1511 | case CHIP_KABINI: | |
1512 | case CHIP_MULLINS: | |
1513 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1514 | adev->family = AMDGPU_FAMILY_CI; | |
1515 | else | |
1516 | adev->family = AMDGPU_FAMILY_KV; | |
1517 | ||
1518 | r = cik_set_ip_blocks(adev); | |
1519 | if (r) | |
1520 | return r; | |
1521 | break; | |
1522 | #endif | |
e48a3cd9 AD |
1523 | case CHIP_VEGA10: |
1524 | case CHIP_VEGA12: | |
e4bd8170 | 1525 | case CHIP_VEGA20: |
e48a3cd9 | 1526 | case CHIP_RAVEN: |
2ca8a5d2 CZ |
1527 | if (adev->asic_type == CHIP_RAVEN) |
1528 | adev->family = AMDGPU_FAMILY_RV; | |
1529 | else | |
1530 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1531 | |
1532 | r = soc15_set_ip_blocks(adev); | |
1533 | if (r) | |
1534 | return r; | |
1535 | break; | |
d38ceaf9 AD |
1536 | default: |
1537 | /* FIXME: not supported yet */ | |
1538 | return -EINVAL; | |
1539 | } | |
1540 | ||
e2a75f88 AD |
1541 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1542 | if (r) | |
1543 | return r; | |
1544 | ||
1884734a | 1545 | amdgpu_amdkfd_device_probe(adev); |
1546 | ||
3149d9da XY |
1547 | if (amdgpu_sriov_vf(adev)) { |
1548 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1549 | if (r) | |
5ffa61c1 | 1550 | return -EAGAIN; |
3149d9da XY |
1551 | } |
1552 | ||
00f54b97 HR |
1553 | adev->powerplay.pp_feature = amdgpu_pp_feature_mask; |
1554 | ||
d38ceaf9 AD |
1555 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1556 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1557 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1558 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1559 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1560 | } else { |
a1255107 AD |
1561 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1562 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1563 | if (r == -ENOENT) { |
a1255107 | 1564 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1565 | } else if (r) { |
a1255107 AD |
1566 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1567 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1568 | return r; |
2c1a2784 | 1569 | } else { |
a1255107 | 1570 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1571 | } |
974e6b64 | 1572 | } else { |
a1255107 | 1573 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1574 | } |
d38ceaf9 AD |
1575 | } |
1576 | } | |
1577 | ||
395d1fb9 NH |
1578 | adev->cg_flags &= amdgpu_cg_mask; |
1579 | adev->pg_flags &= amdgpu_pg_mask; | |
1580 | ||
d38ceaf9 AD |
1581 | return 0; |
1582 | } | |
1583 | ||
e3ecdffa AD |
1584 | /** |
1585 | * amdgpu_device_ip_init - run init for hardware IPs | |
1586 | * | |
1587 | * @adev: amdgpu_device pointer | |
1588 | * | |
1589 | * Main initialization pass for hardware IPs. The list of all the hardware | |
1590 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
1591 | * are run. sw_init initializes the software state associated with each IP | |
1592 | * and hw_init initializes the hardware associated with each IP. | |
1593 | * Returns 0 on success, negative error code on failure. | |
1594 | */ | |
06ec9070 | 1595 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1596 | { |
1597 | int i, r; | |
1598 | ||
1599 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1600 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1601 | continue; |
a1255107 | 1602 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1603 | if (r) { |
a1255107 AD |
1604 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1605 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1606 | return r; |
2c1a2784 | 1607 | } |
a1255107 | 1608 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 1609 | |
d38ceaf9 | 1610 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1611 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 1612 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
1613 | if (r) { |
1614 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1615 | return r; |
2c1a2784 | 1616 | } |
a1255107 | 1617 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1618 | if (r) { |
1619 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1620 | return r; |
2c1a2784 | 1621 | } |
06ec9070 | 1622 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 1623 | if (r) { |
06ec9070 | 1624 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
d38ceaf9 | 1625 | return r; |
2c1a2784 | 1626 | } |
a1255107 | 1627 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1628 | |
1629 | /* right after GMC hw init, we create CSA */ | |
1630 | if (amdgpu_sriov_vf(adev)) { | |
1631 | r = amdgpu_allocate_static_csa(adev); | |
1632 | if (r) { | |
1633 | DRM_ERROR("allocate CSA failed %d\n", r); | |
1634 | return r; | |
1635 | } | |
1636 | } | |
d38ceaf9 AD |
1637 | } |
1638 | } | |
1639 | ||
1640 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1641 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1642 | continue; |
bfca0289 | 1643 | if (adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1644 | continue; |
a1255107 | 1645 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1646 | if (r) { |
a1255107 AD |
1647 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1648 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1649 | return r; |
2c1a2784 | 1650 | } |
a1255107 | 1651 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1652 | } |
1653 | ||
1884734a | 1654 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1655 | |
1656 | if (amdgpu_sriov_vf(adev)) | |
1657 | amdgpu_virt_release_full_gpu(adev, true); | |
1658 | ||
d38ceaf9 AD |
1659 | return 0; |
1660 | } | |
1661 | ||
e3ecdffa AD |
1662 | /** |
1663 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
1664 | * | |
1665 | * @adev: amdgpu_device pointer | |
1666 | * | |
1667 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
1668 | * this function before a GPU reset. If the value is retained after a | |
1669 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
1670 | */ | |
06ec9070 | 1671 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1672 | { |
1673 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1674 | } | |
1675 | ||
e3ecdffa AD |
1676 | /** |
1677 | * amdgpu_device_check_vram_lost - check if vram is valid | |
1678 | * | |
1679 | * @adev: amdgpu_device pointer | |
1680 | * | |
1681 | * Checks the reset magic value written to the gart pointer in VRAM. | |
1682 | * The driver calls this after a GPU reset to see if the contents of | |
1683 | * VRAM is lost or now. | |
1684 | * returns true if vram is lost, false if not. | |
1685 | */ | |
06ec9070 | 1686 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1687 | { |
1688 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1689 | AMDGPU_RESET_MAGIC_NUM); | |
1690 | } | |
1691 | ||
e3ecdffa | 1692 | /** |
1112a46b | 1693 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
1694 | * |
1695 | * @adev: amdgpu_device pointer | |
1696 | * | |
e3ecdffa | 1697 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
1698 | * set_clockgating_state callbacks are run. |
1699 | * Late initialization pass enabling clockgating for hardware IPs. | |
1700 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
1701 | * Returns 0 on success, negative error code on failure. |
1702 | */ | |
1112a46b RZ |
1703 | static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
1704 | enum amd_clockgating_state state) | |
d38ceaf9 | 1705 | { |
1112a46b | 1706 | int i, j, r; |
d38ceaf9 | 1707 | |
4a2ba394 SL |
1708 | if (amdgpu_emu_mode == 1) |
1709 | return 0; | |
1710 | ||
1112a46b RZ |
1711 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1712 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a1255107 | 1713 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1714 | continue; |
4a446d55 | 1715 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 1716 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 1717 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 1718 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
57716327 | 1719 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 1720 | /* enable clockgating to save power */ |
a1255107 | 1721 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 1722 | state); |
4a446d55 AD |
1723 | if (r) { |
1724 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1725 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1726 | return r; |
1727 | } | |
b0b00ff1 | 1728 | } |
d38ceaf9 | 1729 | } |
06b18f61 | 1730 | |
c9f96fd5 RZ |
1731 | return 0; |
1732 | } | |
1733 | ||
1112a46b | 1734 | static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state) |
c9f96fd5 | 1735 | { |
1112a46b | 1736 | int i, j, r; |
06b18f61 | 1737 | |
c9f96fd5 RZ |
1738 | if (amdgpu_emu_mode == 1) |
1739 | return 0; | |
1740 | ||
1112a46b RZ |
1741 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1742 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
c9f96fd5 RZ |
1743 | if (!adev->ip_blocks[i].status.valid) |
1744 | continue; | |
1745 | /* skip CG for VCE/UVD, it's handled specially */ | |
1746 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1747 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
1748 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
1749 | adev->ip_blocks[i].version->funcs->set_powergating_state) { | |
1750 | /* enable powergating to save power */ | |
1751 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 1752 | state); |
c9f96fd5 RZ |
1753 | if (r) { |
1754 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
1755 | adev->ip_blocks[i].version->funcs->name, r); | |
1756 | return r; | |
1757 | } | |
1758 | } | |
1759 | } | |
2dc80b00 S |
1760 | return 0; |
1761 | } | |
1762 | ||
e3ecdffa AD |
1763 | /** |
1764 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
1765 | * | |
1766 | * @adev: amdgpu_device pointer | |
1767 | * | |
1768 | * Late initialization pass for hardware IPs. The list of all the hardware | |
1769 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
1770 | * late_init covers any special initialization that an IP requires | |
1771 | * after all of the have been initialized or something that needs to happen | |
1772 | * late in the init process. | |
1773 | * Returns 0 on success, negative error code on failure. | |
1774 | */ | |
06ec9070 | 1775 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 S |
1776 | { |
1777 | int i = 0, r; | |
1778 | ||
1779 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1780 | if (!adev->ip_blocks[i].status.valid) | |
1781 | continue; | |
1782 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1783 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1784 | if (r) { | |
1785 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1786 | adev->ip_blocks[i].version->funcs->name, r); | |
1787 | return r; | |
1788 | } | |
1789 | adev->ip_blocks[i].status.late_initialized = true; | |
1790 | } | |
1791 | } | |
1792 | ||
1112a46b RZ |
1793 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
1794 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 1795 | |
2c773de2 S |
1796 | queue_delayed_work(system_wq, &adev->late_init_work, |
1797 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
d38ceaf9 | 1798 | |
06ec9070 | 1799 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 AD |
1800 | |
1801 | return 0; | |
1802 | } | |
1803 | ||
e3ecdffa AD |
1804 | /** |
1805 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
1806 | * | |
1807 | * @adev: amdgpu_device pointer | |
1808 | * | |
1809 | * Main teardown pass for hardware IPs. The list of all the hardware | |
1810 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
1811 | * are run. hw_fini tears down the hardware associated with each IP | |
1812 | * and sw_fini tears down any software state associated with each IP. | |
1813 | * Returns 0 on success, negative error code on failure. | |
1814 | */ | |
06ec9070 | 1815 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1816 | { |
1817 | int i, r; | |
1818 | ||
1884734a | 1819 | amdgpu_amdkfd_device_fini(adev); |
3e96dbfd AD |
1820 | /* need to disable SMC first */ |
1821 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1822 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1823 | continue; |
57716327 RZ |
1824 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC && |
1825 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { | |
3e96dbfd | 1826 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1827 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1828 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1829 | if (r) { |
1830 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1831 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1832 | return r; |
1833 | } | |
408acede | 1834 | amdgpu_gfx_off_ctrl(adev, false); |
6c1fd99b | 1835 | cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); |
a1255107 | 1836 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1837 | /* XXX handle errors */ |
1838 | if (r) { | |
1839 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1840 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1841 | } |
a1255107 | 1842 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1843 | break; |
1844 | } | |
1845 | } | |
1846 | ||
d38ceaf9 | 1847 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1848 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1849 | continue; |
8201a67a RZ |
1850 | |
1851 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
81ce8bea | 1852 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 1853 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
81ce8bea | 1854 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
8201a67a RZ |
1855 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
1856 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1857 | AMD_CG_STATE_UNGATE); | |
1858 | if (r) { | |
1859 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1860 | adev->ip_blocks[i].version->funcs->name, r); | |
1861 | return r; | |
1862 | } | |
2c1a2784 | 1863 | } |
8201a67a | 1864 | |
a1255107 | 1865 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1866 | /* XXX handle errors */ |
2c1a2784 | 1867 | if (r) { |
a1255107 AD |
1868 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1869 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1870 | } |
8201a67a | 1871 | |
a1255107 | 1872 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1873 | } |
1874 | ||
9950cda2 | 1875 | |
d38ceaf9 | 1876 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1877 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1878 | continue; |
c12aba3a ML |
1879 | |
1880 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
1881 | amdgpu_free_static_csa(adev); | |
1882 | amdgpu_device_wb_fini(adev); | |
1883 | amdgpu_device_vram_scratch_fini(adev); | |
1884 | } | |
1885 | ||
a1255107 | 1886 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1887 | /* XXX handle errors */ |
2c1a2784 | 1888 | if (r) { |
a1255107 AD |
1889 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1890 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1891 | } |
a1255107 AD |
1892 | adev->ip_blocks[i].status.sw = false; |
1893 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1894 | } |
1895 | ||
a6dcfd9c | 1896 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1897 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1898 | continue; |
a1255107 AD |
1899 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1900 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1901 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1902 | } |
1903 | ||
030308fc | 1904 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
1905 | if (amdgpu_virt_release_full_gpu(adev, false)) |
1906 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 1907 | |
d38ceaf9 AD |
1908 | return 0; |
1909 | } | |
1910 | ||
e3ecdffa | 1911 | /** |
1112a46b | 1912 | * amdgpu_device_ip_late_init_func_handler - work handler for ib test |
e3ecdffa | 1913 | * |
1112a46b | 1914 | * @work: work_struct. |
e3ecdffa | 1915 | */ |
06ec9070 | 1916 | static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) |
2dc80b00 S |
1917 | { |
1918 | struct amdgpu_device *adev = | |
1919 | container_of(work, struct amdgpu_device, late_init_work.work); | |
916ac57f RZ |
1920 | int r; |
1921 | ||
1922 | r = amdgpu_ib_ring_tests(adev); | |
1923 | if (r) | |
1924 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
1925 | } |
1926 | ||
1e317b99 RZ |
1927 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
1928 | { | |
1929 | struct amdgpu_device *adev = | |
1930 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
1931 | ||
1932 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
1933 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
1934 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
1935 | adev->gfx.gfx_off_state = true; | |
1936 | } | |
1937 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
1938 | } | |
1939 | ||
e3ecdffa | 1940 | /** |
e7854a03 | 1941 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
1942 | * |
1943 | * @adev: amdgpu_device pointer | |
1944 | * | |
1945 | * Main suspend function for hardware IPs. The list of all the hardware | |
1946 | * IPs that make up the asic is walked, clockgating is disabled and the | |
1947 | * suspend callbacks are run. suspend puts the hardware and software state | |
1948 | * in each IP into a state suitable for suspend. | |
1949 | * Returns 0 on success, negative error code on failure. | |
1950 | */ | |
e7854a03 AD |
1951 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
1952 | { | |
1953 | int i, r; | |
1954 | ||
1955 | if (amdgpu_sriov_vf(adev)) | |
1956 | amdgpu_virt_request_full_gpu(adev, false); | |
1957 | ||
1958 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
1959 | if (!adev->ip_blocks[i].status.valid) | |
1960 | continue; | |
1961 | /* displays are handled separately */ | |
1962 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { | |
1963 | /* ungate blocks so that suspend can properly shut them down */ | |
1964 | if (adev->ip_blocks[i].version->funcs->set_clockgating_state) { | |
1965 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1966 | AMD_CG_STATE_UNGATE); | |
1967 | if (r) { | |
1968 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
1969 | adev->ip_blocks[i].version->funcs->name, r); | |
1970 | } | |
1971 | } | |
1972 | /* XXX handle errors */ | |
1973 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
1974 | /* XXX handle errors */ | |
1975 | if (r) { | |
1976 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
1977 | adev->ip_blocks[i].version->funcs->name, r); | |
1978 | } | |
1979 | } | |
1980 | } | |
1981 | ||
1982 | if (amdgpu_sriov_vf(adev)) | |
1983 | amdgpu_virt_release_full_gpu(adev, false); | |
1984 | ||
1985 | return 0; | |
1986 | } | |
1987 | ||
1988 | /** | |
1989 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
1990 | * | |
1991 | * @adev: amdgpu_device pointer | |
1992 | * | |
1993 | * Main suspend function for hardware IPs. The list of all the hardware | |
1994 | * IPs that make up the asic is walked, clockgating is disabled and the | |
1995 | * suspend callbacks are run. suspend puts the hardware and software state | |
1996 | * in each IP into a state suitable for suspend. | |
1997 | * Returns 0 on success, negative error code on failure. | |
1998 | */ | |
1999 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2000 | { |
2001 | int i, r; | |
2002 | ||
e941ea99 XY |
2003 | if (amdgpu_sriov_vf(adev)) |
2004 | amdgpu_virt_request_full_gpu(adev, false); | |
2005 | ||
c5a93a28 | 2006 | /* ungate SMC block first */ |
2990a1fc AD |
2007 | r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, |
2008 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 2009 | if (r) { |
2990a1fc | 2010 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r); |
c5a93a28 FC |
2011 | } |
2012 | ||
9134c6d7 | 2013 | /* call smu to disable gfx off feature first when suspend */ |
408acede | 2014 | amdgpu_gfx_off_ctrl(adev, false); |
6c1fd99b | 2015 | cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); |
9134c6d7 | 2016 | |
d38ceaf9 | 2017 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2018 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2019 | continue; |
e7854a03 AD |
2020 | /* displays are handled in phase1 */ |
2021 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2022 | continue; | |
d38ceaf9 | 2023 | /* ungate blocks so that suspend can properly shut them down */ |
5b2a3d2c | 2024 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_SMC && |
57716327 | 2025 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
a1255107 AD |
2026 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
2027 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 2028 | if (r) { |
a1255107 AD |
2029 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
2030 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 2031 | } |
2c1a2784 | 2032 | } |
d38ceaf9 | 2033 | /* XXX handle errors */ |
a1255107 | 2034 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2035 | /* XXX handle errors */ |
2c1a2784 | 2036 | if (r) { |
a1255107 AD |
2037 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2038 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2039 | } |
d38ceaf9 AD |
2040 | } |
2041 | ||
e941ea99 XY |
2042 | if (amdgpu_sriov_vf(adev)) |
2043 | amdgpu_virt_release_full_gpu(adev, false); | |
2044 | ||
d38ceaf9 AD |
2045 | return 0; |
2046 | } | |
2047 | ||
e7854a03 AD |
2048 | /** |
2049 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2050 | * | |
2051 | * @adev: amdgpu_device pointer | |
2052 | * | |
2053 | * Main suspend function for hardware IPs. The list of all the hardware | |
2054 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2055 | * suspend callbacks are run. suspend puts the hardware and software state | |
2056 | * in each IP into a state suitable for suspend. | |
2057 | * Returns 0 on success, negative error code on failure. | |
2058 | */ | |
2059 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2060 | { | |
2061 | int r; | |
2062 | ||
2063 | r = amdgpu_device_ip_suspend_phase1(adev); | |
2064 | if (r) | |
2065 | return r; | |
2066 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2067 | ||
2068 | return r; | |
2069 | } | |
2070 | ||
06ec9070 | 2071 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2072 | { |
2073 | int i, r; | |
2074 | ||
2cb681b6 ML |
2075 | static enum amd_ip_block_type ip_order[] = { |
2076 | AMD_IP_BLOCK_TYPE_GMC, | |
2077 | AMD_IP_BLOCK_TYPE_COMMON, | |
2cb681b6 ML |
2078 | AMD_IP_BLOCK_TYPE_IH, |
2079 | }; | |
a90ad3c2 | 2080 | |
2cb681b6 ML |
2081 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2082 | int j; | |
2083 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2084 | |
2cb681b6 ML |
2085 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2086 | block = &adev->ip_blocks[j]; | |
2087 | ||
2088 | if (block->version->type != ip_order[i] || | |
2089 | !block->status.valid) | |
2090 | continue; | |
2091 | ||
2092 | r = block->version->funcs->hw_init(adev); | |
3f48c681 | 2093 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2094 | if (r) |
2095 | return r; | |
a90ad3c2 ML |
2096 | } |
2097 | } | |
2098 | ||
2099 | return 0; | |
2100 | } | |
2101 | ||
06ec9070 | 2102 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2103 | { |
2104 | int i, r; | |
2105 | ||
2cb681b6 ML |
2106 | static enum amd_ip_block_type ip_order[] = { |
2107 | AMD_IP_BLOCK_TYPE_SMC, | |
ef4c166d | 2108 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2109 | AMD_IP_BLOCK_TYPE_DCE, |
2110 | AMD_IP_BLOCK_TYPE_GFX, | |
2111 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
2112 | AMD_IP_BLOCK_TYPE_UVD, |
2113 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 2114 | }; |
a90ad3c2 | 2115 | |
2cb681b6 ML |
2116 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2117 | int j; | |
2118 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2119 | |
2cb681b6 ML |
2120 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2121 | block = &adev->ip_blocks[j]; | |
2122 | ||
2123 | if (block->version->type != ip_order[i] || | |
2124 | !block->status.valid) | |
2125 | continue; | |
2126 | ||
2127 | r = block->version->funcs->hw_init(adev); | |
3f48c681 | 2128 | DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2129 | if (r) |
2130 | return r; | |
a90ad3c2 ML |
2131 | } |
2132 | } | |
2133 | ||
2134 | return 0; | |
2135 | } | |
2136 | ||
e3ecdffa AD |
2137 | /** |
2138 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2139 | * | |
2140 | * @adev: amdgpu_device pointer | |
2141 | * | |
2142 | * First resume function for hardware IPs. The list of all the hardware | |
2143 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2144 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2145 | * after a suspend and updates the software state as necessary. This | |
2146 | * function is also used for restoring the GPU after a GPU reset. | |
2147 | * Returns 0 on success, negative error code on failure. | |
2148 | */ | |
06ec9070 | 2149 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2150 | { |
2151 | int i, r; | |
2152 | ||
a90ad3c2 ML |
2153 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2154 | if (!adev->ip_blocks[i].status.valid) | |
2155 | continue; | |
a90ad3c2 | 2156 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2157 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2158 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
fcf0649f CZ |
2159 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2160 | if (r) { | |
2161 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2162 | adev->ip_blocks[i].version->funcs->name, r); | |
2163 | return r; | |
2164 | } | |
a90ad3c2 ML |
2165 | } |
2166 | } | |
2167 | ||
2168 | return 0; | |
2169 | } | |
2170 | ||
e3ecdffa AD |
2171 | /** |
2172 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2173 | * | |
2174 | * @adev: amdgpu_device pointer | |
2175 | * | |
2176 | * First resume function for hardware IPs. The list of all the hardware | |
2177 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2178 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2179 | * functional state after a suspend and updates the software state as | |
2180 | * necessary. This function is also used for restoring the GPU after a GPU | |
2181 | * reset. | |
2182 | * Returns 0 on success, negative error code on failure. | |
2183 | */ | |
06ec9070 | 2184 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2185 | { |
2186 | int i, r; | |
2187 | ||
2188 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2189 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2190 | continue; |
fcf0649f | 2191 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2192 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2193 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) | |
fcf0649f | 2194 | continue; |
a1255107 | 2195 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2196 | if (r) { |
a1255107 AD |
2197 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2198 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2199 | return r; |
2c1a2784 | 2200 | } |
d38ceaf9 AD |
2201 | } |
2202 | ||
2203 | return 0; | |
2204 | } | |
2205 | ||
e3ecdffa AD |
2206 | /** |
2207 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2208 | * | |
2209 | * @adev: amdgpu_device pointer | |
2210 | * | |
2211 | * Main resume function for hardware IPs. The hardware IPs | |
2212 | * are split into two resume functions because they are | |
2213 | * are also used in in recovering from a GPU reset and some additional | |
2214 | * steps need to be take between them. In this case (S3/S4) they are | |
2215 | * run sequentially. | |
2216 | * Returns 0 on success, negative error code on failure. | |
2217 | */ | |
06ec9070 | 2218 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2219 | { |
2220 | int r; | |
2221 | ||
06ec9070 | 2222 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2223 | if (r) |
2224 | return r; | |
06ec9070 | 2225 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2226 | |
2227 | return r; | |
2228 | } | |
2229 | ||
e3ecdffa AD |
2230 | /** |
2231 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2232 | * | |
2233 | * @adev: amdgpu_device pointer | |
2234 | * | |
2235 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2236 | */ | |
4e99a44e | 2237 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2238 | { |
6867e1b5 ML |
2239 | if (amdgpu_sriov_vf(adev)) { |
2240 | if (adev->is_atom_fw) { | |
2241 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2242 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2243 | } else { | |
2244 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2245 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2246 | } | |
2247 | ||
2248 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2249 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2250 | } |
048765ad AR |
2251 | } |
2252 | ||
e3ecdffa AD |
2253 | /** |
2254 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2255 | * | |
2256 | * @asic_type: AMD asic type | |
2257 | * | |
2258 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2259 | * returns true if DC has support, false if not. | |
2260 | */ | |
4562236b HW |
2261 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2262 | { | |
2263 | switch (asic_type) { | |
2264 | #if defined(CONFIG_DRM_AMD_DC) | |
2265 | case CHIP_BONAIRE: | |
0d6fbccb | 2266 | case CHIP_KAVERI: |
367e6687 AD |
2267 | case CHIP_KABINI: |
2268 | case CHIP_MULLINS: | |
d9fda248 HW |
2269 | /* |
2270 | * We have systems in the wild with these ASICs that require | |
2271 | * LVDS and VGA support which is not supported with DC. | |
2272 | * | |
2273 | * Fallback to the non-DC driver here by default so as not to | |
2274 | * cause regressions. | |
2275 | */ | |
2276 | return amdgpu_dc > 0; | |
2277 | case CHIP_HAWAII: | |
4562236b HW |
2278 | case CHIP_CARRIZO: |
2279 | case CHIP_STONEY: | |
4562236b | 2280 | case CHIP_POLARIS10: |
675fd32b | 2281 | case CHIP_POLARIS11: |
2c8ad2d5 | 2282 | case CHIP_POLARIS12: |
675fd32b | 2283 | case CHIP_VEGAM: |
4562236b HW |
2284 | case CHIP_TONGA: |
2285 | case CHIP_FIJI: | |
42f8ffa1 | 2286 | case CHIP_VEGA10: |
dca7b401 | 2287 | case CHIP_VEGA12: |
c6034aa2 | 2288 | case CHIP_VEGA20: |
dc37a9a0 | 2289 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
fd187853 | 2290 | case CHIP_RAVEN: |
42f8ffa1 | 2291 | #endif |
fd187853 | 2292 | return amdgpu_dc != 0; |
4562236b HW |
2293 | #endif |
2294 | default: | |
2295 | return false; | |
2296 | } | |
2297 | } | |
2298 | ||
2299 | /** | |
2300 | * amdgpu_device_has_dc_support - check if dc is supported | |
2301 | * | |
2302 | * @adev: amdgpu_device_pointer | |
2303 | * | |
2304 | * Returns true for supported, false for not supported | |
2305 | */ | |
2306 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2307 | { | |
2555039d XY |
2308 | if (amdgpu_sriov_vf(adev)) |
2309 | return false; | |
2310 | ||
4562236b HW |
2311 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2312 | } | |
2313 | ||
d38ceaf9 AD |
2314 | /** |
2315 | * amdgpu_device_init - initialize the driver | |
2316 | * | |
2317 | * @adev: amdgpu_device pointer | |
87e3f136 | 2318 | * @ddev: drm dev pointer |
d38ceaf9 AD |
2319 | * @pdev: pci dev pointer |
2320 | * @flags: driver flags | |
2321 | * | |
2322 | * Initializes the driver info and hw (all asics). | |
2323 | * Returns 0 for success or an error on failure. | |
2324 | * Called at driver startup. | |
2325 | */ | |
2326 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2327 | struct drm_device *ddev, | |
2328 | struct pci_dev *pdev, | |
2329 | uint32_t flags) | |
2330 | { | |
2331 | int r, i; | |
2332 | bool runtime = false; | |
95844d20 | 2333 | u32 max_MBps; |
d38ceaf9 AD |
2334 | |
2335 | adev->shutdown = false; | |
2336 | adev->dev = &pdev->dev; | |
2337 | adev->ddev = ddev; | |
2338 | adev->pdev = pdev; | |
2339 | adev->flags = flags; | |
2f7d10b3 | 2340 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2341 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 SL |
2342 | if (amdgpu_emu_mode == 1) |
2343 | adev->usec_timeout *= 2; | |
770d13b1 | 2344 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2345 | adev->accel_working = false; |
2346 | adev->num_rings = 0; | |
2347 | adev->mman.buffer_funcs = NULL; | |
2348 | adev->mman.buffer_funcs_ring = NULL; | |
2349 | adev->vm_manager.vm_pte_funcs = NULL; | |
3798e9a6 | 2350 | adev->vm_manager.vm_pte_num_rqs = 0; |
132f34e4 | 2351 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 2352 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2353 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2354 | |
2355 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2356 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2357 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2358 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2359 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2360 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2361 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2362 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2363 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2364 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2365 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2366 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2367 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2368 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2369 | ||
3e39ab90 AD |
2370 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2371 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2372 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2373 | |
2374 | /* mutex initialization are all done here so we | |
2375 | * can recall function without having locking issues */ | |
d38ceaf9 | 2376 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2377 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2378 | mutex_init(&adev->pm.mutex); |
2379 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2380 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2381 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 2382 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 2383 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2384 | mutex_init(&adev->mn_lock); |
e23b74aa | 2385 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 2386 | hash_init(adev->mn_hash); |
13a752e3 | 2387 | mutex_init(&adev->lock_reset); |
d38ceaf9 | 2388 | |
06ec9070 | 2389 | amdgpu_device_check_arguments(adev); |
d38ceaf9 | 2390 | |
d38ceaf9 AD |
2391 | spin_lock_init(&adev->mmio_idx_lock); |
2392 | spin_lock_init(&adev->smc_idx_lock); | |
2393 | spin_lock_init(&adev->pcie_idx_lock); | |
2394 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2395 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2396 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2397 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2398 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2399 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2400 | |
0c4e7fa5 CZ |
2401 | INIT_LIST_HEAD(&adev->shadow_list); |
2402 | mutex_init(&adev->shadow_list_lock); | |
2403 | ||
795f2813 AR |
2404 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2405 | spin_lock_init(&adev->ring_lru_list_lock); | |
2406 | ||
06ec9070 AD |
2407 | INIT_DELAYED_WORK(&adev->late_init_work, |
2408 | amdgpu_device_ip_late_init_func_handler); | |
1e317b99 RZ |
2409 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
2410 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 2411 | |
d23ee13f | 2412 | adev->gfx.gfx_off_req_count = 1; |
b1ddf548 RZ |
2413 | adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false; |
2414 | ||
0fa49558 AX |
2415 | /* Registers mapping */ |
2416 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2417 | if (adev->asic_type >= CHIP_BONAIRE) { |
2418 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2419 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2420 | } else { | |
2421 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2422 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2423 | } | |
d38ceaf9 | 2424 | |
d38ceaf9 AD |
2425 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2426 | if (adev->rmmio == NULL) { | |
2427 | return -ENOMEM; | |
2428 | } | |
2429 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2430 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2431 | ||
705e519e | 2432 | /* doorbell bar mapping */ |
06ec9070 | 2433 | amdgpu_device_doorbell_init(adev); |
d38ceaf9 AD |
2434 | |
2435 | /* io port mapping */ | |
2436 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2437 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2438 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2439 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2440 | break; | |
2441 | } | |
2442 | } | |
2443 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2444 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 2445 | |
5494d864 AD |
2446 | amdgpu_device_get_pcie_info(adev); |
2447 | ||
d38ceaf9 | 2448 | /* early init functions */ |
06ec9070 | 2449 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
2450 | if (r) |
2451 | return r; | |
2452 | ||
2453 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
2454 | /* this will fail for cards that aren't VGA class devices, just | |
2455 | * ignore it */ | |
06ec9070 | 2456 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 2457 | |
e9bef455 | 2458 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2459 | runtime = true; |
84c8b22e LW |
2460 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2461 | vga_switcheroo_register_client(adev->pdev, | |
2462 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2463 | if (runtime) |
2464 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2465 | ||
9475a943 SL |
2466 | if (amdgpu_emu_mode == 1) { |
2467 | /* post the asic on emulation mode */ | |
2468 | emu_soc_asic_init(adev); | |
bfca0289 | 2469 | goto fence_driver_init; |
9475a943 | 2470 | } |
bfca0289 | 2471 | |
d38ceaf9 | 2472 | /* Read BIOS */ |
83ba126a AD |
2473 | if (!amdgpu_get_bios(adev)) { |
2474 | r = -EINVAL; | |
2475 | goto failed; | |
2476 | } | |
f7e9e9fe | 2477 | |
d38ceaf9 | 2478 | r = amdgpu_atombios_init(adev); |
2c1a2784 AD |
2479 | if (r) { |
2480 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
e23b74aa | 2481 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); |
83ba126a | 2482 | goto failed; |
2c1a2784 | 2483 | } |
d38ceaf9 | 2484 | |
4e99a44e ML |
2485 | /* detect if we are with an SRIOV vbios */ |
2486 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2487 | |
d38ceaf9 | 2488 | /* Post card if necessary */ |
39c640c0 | 2489 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 2490 | if (!adev->bios) { |
bec86378 | 2491 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2492 | r = -EINVAL; |
2493 | goto failed; | |
d38ceaf9 | 2494 | } |
bec86378 | 2495 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2496 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2497 | if (r) { | |
2498 | dev_err(adev->dev, "gpu post error!\n"); | |
2499 | goto failed; | |
2500 | } | |
d38ceaf9 AD |
2501 | } |
2502 | ||
88b64e95 AD |
2503 | if (adev->is_atom_fw) { |
2504 | /* Initialize clocks */ | |
2505 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2506 | if (r) { | |
2507 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2508 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2509 | goto failed; |
2510 | } | |
2511 | } else { | |
a5bde2f9 AD |
2512 | /* Initialize clocks */ |
2513 | r = amdgpu_atombios_get_clock_info(adev); | |
2514 | if (r) { | |
2515 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2516 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2517 | goto failed; |
a5bde2f9 AD |
2518 | } |
2519 | /* init i2c buses */ | |
4562236b HW |
2520 | if (!amdgpu_device_has_dc_support(adev)) |
2521 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2522 | } |
d38ceaf9 | 2523 | |
bfca0289 | 2524 | fence_driver_init: |
d38ceaf9 AD |
2525 | /* Fence driver */ |
2526 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2527 | if (r) { |
2528 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2529 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2530 | goto failed; |
2c1a2784 | 2531 | } |
d38ceaf9 AD |
2532 | |
2533 | /* init the mode config */ | |
2534 | drm_mode_config_init(adev->ddev); | |
2535 | ||
06ec9070 | 2536 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 2537 | if (r) { |
8840a387 | 2538 | /* failed in exclusive mode due to timeout */ |
2539 | if (amdgpu_sriov_vf(adev) && | |
2540 | !amdgpu_sriov_runtime(adev) && | |
2541 | amdgpu_virt_mmio_blocked(adev) && | |
2542 | !amdgpu_virt_wait_reset(adev)) { | |
2543 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
2544 | /* Don't send request since VF is inactive. */ |
2545 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
2546 | adev->virt.ops = NULL; | |
8840a387 | 2547 | r = -EAGAIN; |
2548 | goto failed; | |
2549 | } | |
06ec9070 | 2550 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 2551 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
83ba126a | 2552 | goto failed; |
d38ceaf9 AD |
2553 | } |
2554 | ||
2555 | adev->accel_working = true; | |
2556 | ||
e59c0205 AX |
2557 | amdgpu_vm_check_compute_bug(adev); |
2558 | ||
95844d20 MO |
2559 | /* Initialize the buffer migration limit. */ |
2560 | if (amdgpu_moverate >= 0) | |
2561 | max_MBps = amdgpu_moverate; | |
2562 | else | |
2563 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2564 | /* Get a log2 for easy divisions. */ | |
2565 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2566 | ||
d38ceaf9 AD |
2567 | r = amdgpu_ib_pool_init(adev); |
2568 | if (r) { | |
2569 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
e23b74aa | 2570 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); |
83ba126a | 2571 | goto failed; |
d38ceaf9 AD |
2572 | } |
2573 | ||
2dc8f81e HC |
2574 | if (amdgpu_sriov_vf(adev)) |
2575 | amdgpu_virt_init_data_exchange(adev); | |
2576 | ||
9bc92b9c ML |
2577 | amdgpu_fbdev_init(adev); |
2578 | ||
d2f52ac8 RZ |
2579 | r = amdgpu_pm_sysfs_init(adev); |
2580 | if (r) | |
2581 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2582 | ||
75758255 | 2583 | r = amdgpu_debugfs_gem_init(adev); |
3f14e623 | 2584 | if (r) |
d38ceaf9 | 2585 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2586 | |
2587 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2588 | if (r) |
d38ceaf9 | 2589 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2590 | |
50ab2533 | 2591 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2592 | if (r) |
50ab2533 | 2593 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2594 | |
763efb6c | 2595 | r = amdgpu_debugfs_init(adev); |
db95e218 | 2596 | if (r) |
763efb6c | 2597 | DRM_ERROR("Creating debugfs files failed (%d).\n", r); |
db95e218 | 2598 | |
d38ceaf9 AD |
2599 | if ((amdgpu_testing & 1)) { |
2600 | if (adev->accel_working) | |
2601 | amdgpu_test_moves(adev); | |
2602 | else | |
2603 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2604 | } | |
d38ceaf9 AD |
2605 | if (amdgpu_benchmarking) { |
2606 | if (adev->accel_working) | |
2607 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2608 | else | |
2609 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2610 | } | |
2611 | ||
2612 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2613 | * explicit gating rather than handling it automatically. | |
2614 | */ | |
06ec9070 | 2615 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 2616 | if (r) { |
06ec9070 | 2617 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 2618 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2619 | goto failed; |
2c1a2784 | 2620 | } |
d38ceaf9 AD |
2621 | |
2622 | return 0; | |
83ba126a AD |
2623 | |
2624 | failed: | |
89041940 | 2625 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2626 | if (runtime) |
2627 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 2628 | |
83ba126a | 2629 | return r; |
d38ceaf9 AD |
2630 | } |
2631 | ||
d38ceaf9 AD |
2632 | /** |
2633 | * amdgpu_device_fini - tear down the driver | |
2634 | * | |
2635 | * @adev: amdgpu_device pointer | |
2636 | * | |
2637 | * Tear down the driver info (all asics). | |
2638 | * Called at driver shutdown. | |
2639 | */ | |
2640 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2641 | { | |
2642 | int r; | |
2643 | ||
2644 | DRM_INFO("amdgpu: finishing device.\n"); | |
2645 | adev->shutdown = true; | |
e5b03032 ML |
2646 | /* disable all interrupts */ |
2647 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
2648 | if (adev->mode_info.mode_config_initialized){ |
2649 | if (!amdgpu_device_has_dc_support(adev)) | |
2650 | drm_crtc_force_disable_all(adev->ddev); | |
2651 | else | |
2652 | drm_atomic_helper_shutdown(adev->ddev); | |
2653 | } | |
d38ceaf9 AD |
2654 | amdgpu_ib_pool_fini(adev); |
2655 | amdgpu_fence_driver_fini(adev); | |
58e955d9 | 2656 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2657 | amdgpu_fbdev_fini(adev); |
06ec9070 | 2658 | r = amdgpu_device_ip_fini(adev); |
ab4fe3e1 HR |
2659 | if (adev->firmware.gpu_info_fw) { |
2660 | release_firmware(adev->firmware.gpu_info_fw); | |
2661 | adev->firmware.gpu_info_fw = NULL; | |
2662 | } | |
d38ceaf9 | 2663 | adev->accel_working = false; |
2dc80b00 | 2664 | cancel_delayed_work_sync(&adev->late_init_work); |
d38ceaf9 | 2665 | /* free i2c buses */ |
4562236b HW |
2666 | if (!amdgpu_device_has_dc_support(adev)) |
2667 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
2668 | |
2669 | if (amdgpu_emu_mode != 1) | |
2670 | amdgpu_atombios_fini(adev); | |
2671 | ||
d38ceaf9 AD |
2672 | kfree(adev->bios); |
2673 | adev->bios = NULL; | |
84c8b22e LW |
2674 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2675 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2676 | if (adev->flags & AMD_IS_PX) |
2677 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2678 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2679 | if (adev->rio_mem) | |
2680 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2681 | adev->rio_mem = NULL; | |
2682 | iounmap(adev->rmmio); | |
2683 | adev->rmmio = NULL; | |
06ec9070 | 2684 | amdgpu_device_doorbell_fini(adev); |
d38ceaf9 | 2685 | amdgpu_debugfs_regs_cleanup(adev); |
d38ceaf9 AD |
2686 | } |
2687 | ||
2688 | ||
2689 | /* | |
2690 | * Suspend & resume. | |
2691 | */ | |
2692 | /** | |
810ddc3a | 2693 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 2694 | * |
87e3f136 DP |
2695 | * @dev: drm dev pointer |
2696 | * @suspend: suspend state | |
2697 | * @fbcon : notify the fbdev of suspend | |
d38ceaf9 AD |
2698 | * |
2699 | * Puts the hw in the suspend state (all asics). | |
2700 | * Returns 0 for success or an error on failure. | |
2701 | * Called at driver suspend. | |
2702 | */ | |
810ddc3a | 2703 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2704 | { |
2705 | struct amdgpu_device *adev; | |
2706 | struct drm_crtc *crtc; | |
2707 | struct drm_connector *connector; | |
5ceb54c6 | 2708 | int r; |
d38ceaf9 AD |
2709 | |
2710 | if (dev == NULL || dev->dev_private == NULL) { | |
2711 | return -ENODEV; | |
2712 | } | |
2713 | ||
2714 | adev = dev->dev_private; | |
2715 | ||
2716 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2717 | return 0; | |
2718 | ||
2719 | drm_kms_helper_poll_disable(dev); | |
2720 | ||
5f818173 S |
2721 | if (fbcon) |
2722 | amdgpu_fbdev_set_suspend(adev, 1); | |
2723 | ||
a5459475 RZ |
2724 | cancel_delayed_work_sync(&adev->late_init_work); |
2725 | ||
4562236b HW |
2726 | if (!amdgpu_device_has_dc_support(adev)) { |
2727 | /* turn off display hw */ | |
2728 | drm_modeset_lock_all(dev); | |
2729 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2730 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2731 | } | |
2732 | drm_modeset_unlock_all(dev); | |
fe1053b7 AD |
2733 | /* unpin the front buffers and cursors */ |
2734 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2735 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2736 | struct drm_framebuffer *fb = crtc->primary->fb; | |
2737 | struct amdgpu_bo *robj; | |
2738 | ||
2739 | if (amdgpu_crtc->cursor_bo) { | |
2740 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2741 | r = amdgpu_bo_reserve(aobj, true); | |
2742 | if (r == 0) { | |
2743 | amdgpu_bo_unpin(aobj); | |
2744 | amdgpu_bo_unreserve(aobj); | |
2745 | } | |
756e6880 | 2746 | } |
756e6880 | 2747 | |
fe1053b7 AD |
2748 | if (fb == NULL || fb->obj[0] == NULL) { |
2749 | continue; | |
2750 | } | |
2751 | robj = gem_to_amdgpu_bo(fb->obj[0]); | |
2752 | /* don't unpin kernel fb objects */ | |
2753 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
2754 | r = amdgpu_bo_reserve(robj, true); | |
2755 | if (r == 0) { | |
2756 | amdgpu_bo_unpin(robj); | |
2757 | amdgpu_bo_unreserve(robj); | |
2758 | } | |
d38ceaf9 AD |
2759 | } |
2760 | } | |
2761 | } | |
fe1053b7 AD |
2762 | |
2763 | amdgpu_amdkfd_suspend(adev); | |
2764 | ||
2765 | r = amdgpu_device_ip_suspend_phase1(adev); | |
2766 | ||
d38ceaf9 AD |
2767 | /* evict vram memory */ |
2768 | amdgpu_bo_evict_vram(adev); | |
2769 | ||
5ceb54c6 | 2770 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 2771 | |
fe1053b7 | 2772 | r = amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 2773 | |
a0a71e49 AD |
2774 | /* evict remaining vram memory |
2775 | * This second call to evict vram is to evict the gart page table | |
2776 | * using the CPU. | |
2777 | */ | |
d38ceaf9 AD |
2778 | amdgpu_bo_evict_vram(adev); |
2779 | ||
2780 | pci_save_state(dev->pdev); | |
2781 | if (suspend) { | |
2782 | /* Shut down the device */ | |
2783 | pci_disable_device(dev->pdev); | |
2784 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2785 | } else { |
2786 | r = amdgpu_asic_reset(adev); | |
2787 | if (r) | |
2788 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2789 | } |
2790 | ||
d38ceaf9 AD |
2791 | return 0; |
2792 | } | |
2793 | ||
2794 | /** | |
810ddc3a | 2795 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 2796 | * |
87e3f136 DP |
2797 | * @dev: drm dev pointer |
2798 | * @resume: resume state | |
2799 | * @fbcon : notify the fbdev of resume | |
d38ceaf9 AD |
2800 | * |
2801 | * Bring the hw back to operating state (all asics). | |
2802 | * Returns 0 for success or an error on failure. | |
2803 | * Called at driver resume. | |
2804 | */ | |
810ddc3a | 2805 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2806 | { |
2807 | struct drm_connector *connector; | |
2808 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2809 | struct drm_crtc *crtc; |
03161a6e | 2810 | int r = 0; |
d38ceaf9 AD |
2811 | |
2812 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2813 | return 0; | |
2814 | ||
d38ceaf9 AD |
2815 | if (resume) { |
2816 | pci_set_power_state(dev->pdev, PCI_D0); | |
2817 | pci_restore_state(dev->pdev); | |
74b0b157 | 2818 | r = pci_enable_device(dev->pdev); |
03161a6e | 2819 | if (r) |
4d3b9ae5 | 2820 | return r; |
d38ceaf9 AD |
2821 | } |
2822 | ||
2823 | /* post card */ | |
39c640c0 | 2824 | if (amdgpu_device_need_post(adev)) { |
74b0b157 | 2825 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2826 | if (r) | |
2827 | DRM_ERROR("amdgpu asic init failed\n"); | |
2828 | } | |
d38ceaf9 | 2829 | |
06ec9070 | 2830 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 2831 | if (r) { |
06ec9070 | 2832 | DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 2833 | return r; |
e6707218 | 2834 | } |
5ceb54c6 AD |
2835 | amdgpu_fence_driver_resume(adev); |
2836 | ||
d38ceaf9 | 2837 | |
06ec9070 | 2838 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 2839 | if (r) |
4d3b9ae5 | 2840 | return r; |
d38ceaf9 | 2841 | |
fe1053b7 AD |
2842 | if (!amdgpu_device_has_dc_support(adev)) { |
2843 | /* pin cursors */ | |
2844 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2845 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2846 | ||
2847 | if (amdgpu_crtc->cursor_bo) { | |
2848 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2849 | r = amdgpu_bo_reserve(aobj, true); | |
2850 | if (r == 0) { | |
2851 | r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); | |
2852 | if (r != 0) | |
2853 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2854 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); | |
2855 | amdgpu_bo_unreserve(aobj); | |
2856 | } | |
756e6880 AD |
2857 | } |
2858 | } | |
2859 | } | |
ba997709 YZ |
2860 | r = amdgpu_amdkfd_resume(adev); |
2861 | if (r) | |
2862 | return r; | |
756e6880 | 2863 | |
96a5d8d4 LL |
2864 | /* Make sure IB tests flushed */ |
2865 | flush_delayed_work(&adev->late_init_work); | |
2866 | ||
d38ceaf9 AD |
2867 | /* blat the mode back in */ |
2868 | if (fbcon) { | |
4562236b HW |
2869 | if (!amdgpu_device_has_dc_support(adev)) { |
2870 | /* pre DCE11 */ | |
2871 | drm_helper_resume_force_mode(dev); | |
2872 | ||
2873 | /* turn on display hw */ | |
2874 | drm_modeset_lock_all(dev); | |
2875 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2876 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2877 | } | |
2878 | drm_modeset_unlock_all(dev); | |
d38ceaf9 | 2879 | } |
4d3b9ae5 | 2880 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
2881 | } |
2882 | ||
2883 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2884 | |
2885 | /* | |
2886 | * Most of the connector probing functions try to acquire runtime pm | |
2887 | * refs to ensure that the GPU is powered on when connector polling is | |
2888 | * performed. Since we're calling this from a runtime PM callback, | |
2889 | * trying to acquire rpm refs will cause us to deadlock. | |
2890 | * | |
2891 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2892 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2893 | */ | |
2894 | #ifdef CONFIG_PM | |
2895 | dev->dev->power.disable_depth++; | |
2896 | #endif | |
4562236b HW |
2897 | if (!amdgpu_device_has_dc_support(adev)) |
2898 | drm_helper_hpd_irq_event(dev); | |
2899 | else | |
2900 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
2901 | #ifdef CONFIG_PM |
2902 | dev->dev->power.disable_depth--; | |
2903 | #endif | |
4d3b9ae5 | 2904 | return 0; |
d38ceaf9 AD |
2905 | } |
2906 | ||
e3ecdffa AD |
2907 | /** |
2908 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
2909 | * | |
2910 | * @adev: amdgpu_device pointer | |
2911 | * | |
2912 | * The list of all the hardware IPs that make up the asic is walked and | |
2913 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
2914 | * if the asic is still hung or not. | |
2915 | * Returns true if any of the IPs are still in a hung state, false if not. | |
2916 | */ | |
06ec9070 | 2917 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
2918 | { |
2919 | int i; | |
2920 | bool asic_hang = false; | |
2921 | ||
f993d628 ML |
2922 | if (amdgpu_sriov_vf(adev)) |
2923 | return true; | |
2924 | ||
8bc04c29 AD |
2925 | if (amdgpu_asic_need_full_reset(adev)) |
2926 | return true; | |
2927 | ||
63fbf42f | 2928 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2929 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2930 | continue; |
a1255107 AD |
2931 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2932 | adev->ip_blocks[i].status.hang = | |
2933 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2934 | if (adev->ip_blocks[i].status.hang) { | |
2935 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2936 | asic_hang = true; |
2937 | } | |
2938 | } | |
2939 | return asic_hang; | |
2940 | } | |
2941 | ||
e3ecdffa AD |
2942 | /** |
2943 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
2944 | * | |
2945 | * @adev: amdgpu_device pointer | |
2946 | * | |
2947 | * The list of all the hardware IPs that make up the asic is walked and the | |
2948 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
2949 | * handles any IP specific hardware or software state changes that are | |
2950 | * necessary for a soft reset to succeed. | |
2951 | * Returns 0 on success, negative error code on failure. | |
2952 | */ | |
06ec9070 | 2953 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2954 | { |
2955 | int i, r = 0; | |
2956 | ||
2957 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2958 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2959 | continue; |
a1255107 AD |
2960 | if (adev->ip_blocks[i].status.hang && |
2961 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2962 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2963 | if (r) |
2964 | return r; | |
2965 | } | |
2966 | } | |
2967 | ||
2968 | return 0; | |
2969 | } | |
2970 | ||
e3ecdffa AD |
2971 | /** |
2972 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
2973 | * | |
2974 | * @adev: amdgpu_device pointer | |
2975 | * | |
2976 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
2977 | * reset is necessary to recover. | |
2978 | * Returns true if a full asic reset is required, false if not. | |
2979 | */ | |
06ec9070 | 2980 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 2981 | { |
da146d3b AD |
2982 | int i; |
2983 | ||
8bc04c29 AD |
2984 | if (amdgpu_asic_need_full_reset(adev)) |
2985 | return true; | |
2986 | ||
da146d3b | 2987 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2988 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2989 | continue; |
a1255107 AD |
2990 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2991 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2992 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
2993 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
2994 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 2995 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
2996 | DRM_INFO("Some block need full reset!\n"); |
2997 | return true; | |
2998 | } | |
2999 | } | |
35d782fe CZ |
3000 | } |
3001 | return false; | |
3002 | } | |
3003 | ||
e3ecdffa AD |
3004 | /** |
3005 | * amdgpu_device_ip_soft_reset - do a soft reset | |
3006 | * | |
3007 | * @adev: amdgpu_device pointer | |
3008 | * | |
3009 | * The list of all the hardware IPs that make up the asic is walked and the | |
3010 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
3011 | * IP specific hardware or software state changes that are necessary to soft | |
3012 | * reset the IP. | |
3013 | * Returns 0 on success, negative error code on failure. | |
3014 | */ | |
06ec9070 | 3015 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3016 | { |
3017 | int i, r = 0; | |
3018 | ||
3019 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3020 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3021 | continue; |
a1255107 AD |
3022 | if (adev->ip_blocks[i].status.hang && |
3023 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
3024 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
3025 | if (r) |
3026 | return r; | |
3027 | } | |
3028 | } | |
3029 | ||
3030 | return 0; | |
3031 | } | |
3032 | ||
e3ecdffa AD |
3033 | /** |
3034 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
3035 | * | |
3036 | * @adev: amdgpu_device pointer | |
3037 | * | |
3038 | * The list of all the hardware IPs that make up the asic is walked and the | |
3039 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
3040 | * handles any IP specific hardware or software state changes that are | |
3041 | * necessary after the IP has been soft reset. | |
3042 | * Returns 0 on success, negative error code on failure. | |
3043 | */ | |
06ec9070 | 3044 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3045 | { |
3046 | int i, r = 0; | |
3047 | ||
3048 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3049 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3050 | continue; |
a1255107 AD |
3051 | if (adev->ip_blocks[i].status.hang && |
3052 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
3053 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
3054 | if (r) |
3055 | return r; | |
3056 | } | |
3057 | ||
3058 | return 0; | |
3059 | } | |
3060 | ||
e3ecdffa AD |
3061 | /** |
3062 | * amdgpu_device_recover_vram_from_shadow - restore shadowed VRAM buffers | |
3063 | * | |
3064 | * @adev: amdgpu_device pointer | |
3065 | * @ring: amdgpu_ring for the engine handling the buffer operations | |
3066 | * @bo: amdgpu_bo buffer whose shadow is being restored | |
3067 | * @fence: dma_fence associated with the operation | |
3068 | * | |
3069 | * Restores the VRAM buffer contents from the shadow in GTT. Used to | |
3070 | * restore things like GPUVM page tables after a GPU reset where | |
3071 | * the contents of VRAM might be lost. | |
3072 | * Returns 0 on success, negative error code on failure. | |
3073 | */ | |
06ec9070 AD |
3074 | static int amdgpu_device_recover_vram_from_shadow(struct amdgpu_device *adev, |
3075 | struct amdgpu_ring *ring, | |
3076 | struct amdgpu_bo *bo, | |
3077 | struct dma_fence **fence) | |
53cdccd5 CZ |
3078 | { |
3079 | uint32_t domain; | |
3080 | int r; | |
3081 | ||
23d2e504 RH |
3082 | if (!bo->shadow) |
3083 | return 0; | |
3084 | ||
1d284797 | 3085 | r = amdgpu_bo_reserve(bo, true); |
23d2e504 RH |
3086 | if (r) |
3087 | return r; | |
3088 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
3089 | /* if bo has been evicted, then no need to recover */ | |
3090 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
82521316 RH |
3091 | r = amdgpu_bo_validate(bo->shadow); |
3092 | if (r) { | |
3093 | DRM_ERROR("bo validate failed!\n"); | |
3094 | goto err; | |
3095 | } | |
3096 | ||
23d2e504 | 3097 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, |
53cdccd5 | 3098 | NULL, fence, true); |
23d2e504 RH |
3099 | if (r) { |
3100 | DRM_ERROR("recover page table failed!\n"); | |
3101 | goto err; | |
3102 | } | |
3103 | } | |
53cdccd5 | 3104 | err: |
23d2e504 RH |
3105 | amdgpu_bo_unreserve(bo); |
3106 | return r; | |
53cdccd5 CZ |
3107 | } |
3108 | ||
e3ecdffa AD |
3109 | /** |
3110 | * amdgpu_device_handle_vram_lost - Handle the loss of VRAM contents | |
3111 | * | |
3112 | * @adev: amdgpu_device pointer | |
3113 | * | |
3114 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
3115 | * restore things like GPUVM page tables after a GPU reset where | |
3116 | * the contents of VRAM might be lost. | |
3117 | * Returns 0 on success, 1 on failure. | |
3118 | */ | |
c41d1cf6 ML |
3119 | static int amdgpu_device_handle_vram_lost(struct amdgpu_device *adev) |
3120 | { | |
3121 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
3122 | struct amdgpu_bo *bo, *tmp; | |
3123 | struct dma_fence *fence = NULL, *next = NULL; | |
3124 | long r = 1; | |
3125 | int i = 0; | |
3126 | long tmo; | |
3127 | ||
3128 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 3129 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
3130 | else |
3131 | tmo = msecs_to_jiffies(100); | |
3132 | ||
3133 | DRM_INFO("recover vram bo from shadow start\n"); | |
3134 | mutex_lock(&adev->shadow_list_lock); | |
3135 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
3136 | next = NULL; | |
3137 | amdgpu_device_recover_vram_from_shadow(adev, ring, bo, &next); | |
3138 | if (fence) { | |
3139 | r = dma_fence_wait_timeout(fence, false, tmo); | |
3140 | if (r == 0) | |
3141 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
3142 | else if (r < 0) | |
3143 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
3144 | if (r < 1) { | |
3145 | dma_fence_put(fence); | |
3146 | fence = next; | |
3147 | break; | |
3148 | } | |
3149 | i++; | |
3150 | } | |
3151 | ||
3152 | dma_fence_put(fence); | |
3153 | fence = next; | |
3154 | } | |
3155 | mutex_unlock(&adev->shadow_list_lock); | |
3156 | ||
3157 | if (fence) { | |
3158 | r = dma_fence_wait_timeout(fence, false, tmo); | |
3159 | if (r == 0) | |
3160 | pr_err("wait fence %p[%d] timeout\n", fence, i); | |
3161 | else if (r < 0) | |
3162 | pr_err("wait fence %p[%d] interrupted\n", fence, i); | |
3163 | ||
3164 | } | |
3165 | dma_fence_put(fence); | |
3166 | ||
3167 | if (r > 0) | |
3168 | DRM_INFO("recover vram bo from shadow done\n"); | |
3169 | else | |
3170 | DRM_ERROR("recover vram bo from shadow failed\n"); | |
3171 | ||
e3ecdffa | 3172 | return (r > 0) ? 0 : 1; |
c41d1cf6 ML |
3173 | } |
3174 | ||
e3ecdffa | 3175 | /** |
06ec9070 | 3176 | * amdgpu_device_reset - reset ASIC/GPU for bare-metal or passthrough |
a90ad3c2 ML |
3177 | * |
3178 | * @adev: amdgpu device pointer | |
a90ad3c2 | 3179 | * |
5740682e | 3180 | * attempt to do soft-reset or full-reset and reinitialize Asic |
3f48c681 | 3181 | * return 0 means succeeded otherwise failed |
e3ecdffa | 3182 | */ |
c41d1cf6 | 3183 | static int amdgpu_device_reset(struct amdgpu_device *adev) |
a90ad3c2 | 3184 | { |
5740682e ML |
3185 | bool need_full_reset, vram_lost = 0; |
3186 | int r; | |
a90ad3c2 | 3187 | |
06ec9070 | 3188 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); |
a90ad3c2 | 3189 | |
5740682e | 3190 | if (!need_full_reset) { |
06ec9070 AD |
3191 | amdgpu_device_ip_pre_soft_reset(adev); |
3192 | r = amdgpu_device_ip_soft_reset(adev); | |
3193 | amdgpu_device_ip_post_soft_reset(adev); | |
3194 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
5740682e ML |
3195 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); |
3196 | need_full_reset = true; | |
3197 | } | |
5740682e | 3198 | } |
a90ad3c2 | 3199 | |
5740682e | 3200 | if (need_full_reset) { |
cdd61df6 | 3201 | r = amdgpu_device_ip_suspend(adev); |
a90ad3c2 | 3202 | |
5740682e | 3203 | retry: |
5740682e | 3204 | r = amdgpu_asic_reset(adev); |
5740682e ML |
3205 | /* post card */ |
3206 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
65781c78 | 3207 | |
5740682e ML |
3208 | if (!r) { |
3209 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
06ec9070 | 3210 | r = amdgpu_device_ip_resume_phase1(adev); |
5740682e ML |
3211 | if (r) |
3212 | goto out; | |
65781c78 | 3213 | |
06ec9070 | 3214 | vram_lost = amdgpu_device_check_vram_lost(adev); |
5740682e ML |
3215 | if (vram_lost) { |
3216 | DRM_ERROR("VRAM is lost!\n"); | |
3217 | atomic_inc(&adev->vram_lost_counter); | |
3218 | } | |
3219 | ||
c1c7ce8f CK |
3220 | r = amdgpu_gtt_mgr_recover( |
3221 | &adev->mman.bdev.man[TTM_PL_TT]); | |
5740682e ML |
3222 | if (r) |
3223 | goto out; | |
3224 | ||
06ec9070 | 3225 | r = amdgpu_device_ip_resume_phase2(adev); |
5740682e ML |
3226 | if (r) |
3227 | goto out; | |
3228 | ||
3229 | if (vram_lost) | |
06ec9070 | 3230 | amdgpu_device_fill_reset_magic(adev); |
65781c78 | 3231 | } |
5740682e | 3232 | } |
65781c78 | 3233 | |
5740682e ML |
3234 | out: |
3235 | if (!r) { | |
3236 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
3237 | r = amdgpu_ib_ring_tests(adev); | |
3238 | if (r) { | |
3239 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
cdd61df6 | 3240 | r = amdgpu_device_ip_suspend(adev); |
5740682e ML |
3241 | need_full_reset = true; |
3242 | goto retry; | |
3243 | } | |
3244 | } | |
65781c78 | 3245 | |
c41d1cf6 ML |
3246 | if (!r && ((need_full_reset && !(adev->flags & AMD_IS_APU)) || vram_lost)) |
3247 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 | 3248 | |
5740682e ML |
3249 | return r; |
3250 | } | |
a90ad3c2 | 3251 | |
e3ecdffa | 3252 | /** |
06ec9070 | 3253 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3254 | * |
3255 | * @adev: amdgpu device pointer | |
87e3f136 | 3256 | * @from_hypervisor: request from hypervisor |
5740682e ML |
3257 | * |
3258 | * do VF FLR and reinitialize Asic | |
3f48c681 | 3259 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
3260 | */ |
3261 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3262 | bool from_hypervisor) | |
5740682e ML |
3263 | { |
3264 | int r; | |
3265 | ||
3266 | if (from_hypervisor) | |
3267 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3268 | else | |
3269 | r = amdgpu_virt_reset_gpu(adev); | |
3270 | if (r) | |
3271 | return r; | |
a90ad3c2 ML |
3272 | |
3273 | /* Resume IP prior to SMC */ | |
06ec9070 | 3274 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3275 | if (r) |
3276 | goto error; | |
a90ad3c2 ML |
3277 | |
3278 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 3279 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 ML |
3280 | |
3281 | /* now we are okay to resume SMC/CP/SDMA */ | |
06ec9070 | 3282 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
3283 | if (r) |
3284 | goto error; | |
a90ad3c2 ML |
3285 | |
3286 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3287 | r = amdgpu_ib_ring_tests(adev); |
a90ad3c2 | 3288 | |
abc34253 ED |
3289 | error: |
3290 | amdgpu_virt_release_full_gpu(adev, true); | |
c41d1cf6 ML |
3291 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
3292 | atomic_inc(&adev->vram_lost_counter); | |
3293 | r = amdgpu_device_handle_vram_lost(adev); | |
a90ad3c2 ML |
3294 | } |
3295 | ||
3296 | return r; | |
3297 | } | |
3298 | ||
d38ceaf9 | 3299 | /** |
5f152b5e | 3300 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler |
d38ceaf9 AD |
3301 | * |
3302 | * @adev: amdgpu device pointer | |
5740682e | 3303 | * @job: which job trigger hang |
87e3f136 | 3304 | * @force: forces reset regardless of amdgpu_gpu_recovery |
d38ceaf9 | 3305 | * |
5740682e | 3306 | * Attempt to reset the GPU if it has hung (all asics). |
d38ceaf9 AD |
3307 | * Returns 0 for success or an error on failure. |
3308 | */ | |
5f152b5e AD |
3309 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
3310 | struct amdgpu_job *job, bool force) | |
d38ceaf9 | 3311 | { |
5740682e | 3312 | int i, r, resched; |
fb140b29 | 3313 | |
54bc1398 | 3314 | if (!force && !amdgpu_device_ip_check_soft_reset(adev)) { |
63fbf42f CZ |
3315 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); |
3316 | return 0; | |
3317 | } | |
d38ceaf9 | 3318 | |
dcebf026 AG |
3319 | if (!force && (amdgpu_gpu_recovery == 0 || |
3320 | (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))) { | |
3321 | DRM_INFO("GPU recovery disabled.\n"); | |
3322 | return 0; | |
3323 | } | |
3324 | ||
5740682e ML |
3325 | dev_info(adev->dev, "GPU reset begin!\n"); |
3326 | ||
13a752e3 | 3327 | mutex_lock(&adev->lock_reset); |
d94aed5a | 3328 | atomic_inc(&adev->gpu_reset_counter); |
13a752e3 | 3329 | adev->in_gpu_reset = 1; |
d38ceaf9 | 3330 | |
5c6dd71e SL |
3331 | /* Block kfd */ |
3332 | amdgpu_amdkfd_pre_reset(adev); | |
3333 | ||
a3c47d6b CZ |
3334 | /* block TTM */ |
3335 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
71182665 | 3336 | |
71182665 | 3337 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
3338 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3339 | struct amdgpu_ring *ring = adev->rings[i]; | |
3340 | ||
51687759 | 3341 | if (!ring || !ring->sched.thread) |
0875dc9e | 3342 | continue; |
5740682e | 3343 | |
71182665 ML |
3344 | kthread_park(ring->sched.thread); |
3345 | ||
3320b8d2 | 3346 | if (job && job->base.sched == &ring->sched) |
5740682e ML |
3347 | continue; |
3348 | ||
67ccea60 | 3349 | drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL); |
5740682e | 3350 | |
2f9d4084 ML |
3351 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
3352 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 3353 | } |
d38ceaf9 | 3354 | |
5740682e | 3355 | if (amdgpu_sriov_vf(adev)) |
c41d1cf6 | 3356 | r = amdgpu_device_reset_sriov(adev, job ? false : true); |
5740682e | 3357 | else |
c41d1cf6 | 3358 | r = amdgpu_device_reset(adev); |
5740682e | 3359 | |
71182665 ML |
3360 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3361 | struct amdgpu_ring *ring = adev->rings[i]; | |
53cdccd5 | 3362 | |
71182665 ML |
3363 | if (!ring || !ring->sched.thread) |
3364 | continue; | |
5740682e | 3365 | |
71182665 ML |
3366 | /* only need recovery sched of the given job's ring |
3367 | * or all rings (in the case @job is NULL) | |
3368 | * after above amdgpu_reset accomplished | |
3369 | */ | |
3320b8d2 | 3370 | if ((!job || job->base.sched == &ring->sched) && !r) |
1b1f42d8 | 3371 | drm_sched_job_recovery(&ring->sched); |
5740682e | 3372 | |
71182665 | 3373 | kthread_unpark(ring->sched.thread); |
d38ceaf9 AD |
3374 | } |
3375 | ||
bf830604 | 3376 | if (!amdgpu_device_has_dc_support(adev)) { |
4562236b | 3377 | drm_helper_resume_force_mode(adev->ddev); |
5740682e | 3378 | } |
d38ceaf9 AD |
3379 | |
3380 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
5740682e | 3381 | |
89041940 | 3382 | if (r) { |
d38ceaf9 | 3383 | /* bad news, how to tell it to userspace ? */ |
5740682e ML |
3384 | dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); |
3385 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); | |
3386 | } else { | |
3f48c681 | 3387 | dev_info(adev->dev, "GPU reset(%d) succeeded!\n",atomic_read(&adev->gpu_reset_counter)); |
89041940 | 3388 | } |
d38ceaf9 | 3389 | |
5c6dd71e SL |
3390 | /*unlock kfd */ |
3391 | amdgpu_amdkfd_post_reset(adev); | |
89041940 | 3392 | amdgpu_vf_error_trans_all(adev); |
13a752e3 ML |
3393 | adev->in_gpu_reset = 0; |
3394 | mutex_unlock(&adev->lock_reset); | |
d38ceaf9 AD |
3395 | return r; |
3396 | } | |
3397 | ||
e3ecdffa AD |
3398 | /** |
3399 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
3400 | * | |
3401 | * @adev: amdgpu_device pointer | |
3402 | * | |
3403 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
3404 | * and lanes) of the slot the device is in. Handles APUs and | |
3405 | * virtualized environments where PCIE config space may not be available. | |
3406 | */ | |
5494d864 | 3407 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 3408 | { |
5d9a6330 AD |
3409 | struct pci_dev *pdev; |
3410 | enum pci_bus_speed speed_cap; | |
3411 | enum pcie_link_width link_width; | |
d0dd7f0c | 3412 | |
cd474ba0 AD |
3413 | if (amdgpu_pcie_gen_cap) |
3414 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3415 | |
cd474ba0 AD |
3416 | if (amdgpu_pcie_lane_cap) |
3417 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3418 | |
cd474ba0 AD |
3419 | /* covers APUs as well */ |
3420 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3421 | if (adev->pm.pcie_gen_mask == 0) | |
3422 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3423 | if (adev->pm.pcie_mlw_mask == 0) | |
3424 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3425 | return; |
cd474ba0 | 3426 | } |
d0dd7f0c | 3427 | |
cd474ba0 | 3428 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
3429 | /* asic caps */ |
3430 | pdev = adev->pdev; | |
3431 | speed_cap = pcie_get_speed_cap(pdev); | |
3432 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
3433 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
3434 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
3435 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 3436 | } else { |
5d9a6330 AD |
3437 | if (speed_cap == PCIE_SPEED_16_0GT) |
3438 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3439 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3440 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
3441 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
3442 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
3443 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3444 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3445 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3446 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
3447 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3448 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3449 | else | |
3450 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3451 | } | |
3452 | /* platform caps */ | |
3453 | pdev = adev->ddev->pdev->bus->self; | |
3454 | speed_cap = pcie_get_speed_cap(pdev); | |
3455 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
3456 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3457 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3458 | } else { | |
3459 | if (speed_cap == PCIE_SPEED_16_0GT) | |
3460 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3461 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3462 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
3463 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
3464 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
3465 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3466 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3467 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3468 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
3469 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3470 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3471 | else | |
3472 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3473 | ||
cd474ba0 AD |
3474 | } |
3475 | } | |
3476 | if (adev->pm.pcie_mlw_mask == 0) { | |
5d9a6330 AD |
3477 | pdev = adev->ddev->pdev->bus->self; |
3478 | link_width = pcie_get_width_cap(pdev); | |
3479 | if (link_width == PCIE_LNK_WIDTH_UNKNOWN) { | |
3480 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
3481 | } else { | |
3482 | switch (link_width) { | |
3483 | case PCIE_LNK_X32: | |
cd474ba0 AD |
3484 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
3485 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3486 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3487 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3488 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3489 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3490 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3491 | break; | |
5d9a6330 | 3492 | case PCIE_LNK_X16: |
cd474ba0 AD |
3493 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
3494 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3495 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3496 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3497 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3498 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3499 | break; | |
5d9a6330 | 3500 | case PCIE_LNK_X12: |
cd474ba0 AD |
3501 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
3502 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3503 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3504 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3505 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3506 | break; | |
5d9a6330 | 3507 | case PCIE_LNK_X8: |
cd474ba0 AD |
3508 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
3509 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3510 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3511 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3512 | break; | |
5d9a6330 | 3513 | case PCIE_LNK_X4: |
cd474ba0 AD |
3514 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
3515 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3516 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3517 | break; | |
5d9a6330 | 3518 | case PCIE_LNK_X2: |
cd474ba0 AD |
3519 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
3520 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3521 | break; | |
5d9a6330 | 3522 | case PCIE_LNK_X1: |
cd474ba0 AD |
3523 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
3524 | break; | |
3525 | default: | |
3526 | break; | |
3527 | } | |
d0dd7f0c AD |
3528 | } |
3529 | } | |
3530 | } | |
d38ceaf9 | 3531 |