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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
fdf2f6c5 | 33 | |
4562236b | 34 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 35 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
36 | #include <drm/amdgpu_drm.h> |
37 | #include <linux/vgaarb.h> | |
38 | #include <linux/vga_switcheroo.h> | |
39 | #include <linux/efi.h> | |
40 | #include "amdgpu.h" | |
f4b373f4 | 41 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
42 | #include "amdgpu_i2c.h" |
43 | #include "atom.h" | |
44 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 45 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 46 | #include "amd_pcie.h" |
33f34802 KW |
47 | #ifdef CONFIG_DRM_AMDGPU_SI |
48 | #include "si.h" | |
49 | #endif | |
a2e73f56 AD |
50 | #ifdef CONFIG_DRM_AMDGPU_CIK |
51 | #include "cik.h" | |
52 | #endif | |
aaa36a97 | 53 | #include "vi.h" |
460826e6 | 54 | #include "soc15.h" |
0a5b8c7b | 55 | #include "nv.h" |
d38ceaf9 | 56 | #include "bif/bif_4_1_d.h" |
9accf2fd | 57 | #include <linux/pci.h> |
bec86378 | 58 | #include <linux/firmware.h> |
89041940 | 59 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 60 | |
ba997709 | 61 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 62 | #include "amdgpu_pm.h" |
d38ceaf9 | 63 | |
5183411b | 64 | #include "amdgpu_xgmi.h" |
c030f2e4 | 65 | #include "amdgpu_ras.h" |
9c7c85f7 | 66 | #include "amdgpu_pmu.h" |
bd607166 | 67 | #include "amdgpu_fru_eeprom.h" |
04442bf7 | 68 | #include "amdgpu_reset.h" |
5183411b | 69 | |
d5ea093e | 70 | #include <linux/suspend.h> |
c6a6e2db | 71 | #include <drm/task_barrier.h> |
3f12acc8 | 72 | #include <linux/pm_runtime.h> |
d5ea093e | 73 | |
e2a75f88 | 74 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 75 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 76 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 77 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 78 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 79 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 80 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 81 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 82 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 83 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
4e52a9f8 | 84 | MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin"); |
e2a75f88 | 85 | |
2dc80b00 S |
86 | #define AMDGPU_RESUME_MS 2000 |
87 | ||
050091ab | 88 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
89 | "TAHITI", |
90 | "PITCAIRN", | |
91 | "VERDE", | |
92 | "OLAND", | |
93 | "HAINAN", | |
d38ceaf9 AD |
94 | "BONAIRE", |
95 | "KAVERI", | |
96 | "KABINI", | |
97 | "HAWAII", | |
98 | "MULLINS", | |
99 | "TOPAZ", | |
100 | "TONGA", | |
48299f95 | 101 | "FIJI", |
d38ceaf9 | 102 | "CARRIZO", |
139f4917 | 103 | "STONEY", |
2cc0c0b5 FC |
104 | "POLARIS10", |
105 | "POLARIS11", | |
c4642a47 | 106 | "POLARIS12", |
48ff108d | 107 | "VEGAM", |
d4196f01 | 108 | "VEGA10", |
8fab806a | 109 | "VEGA12", |
956fcddc | 110 | "VEGA20", |
2ca8a5d2 | 111 | "RAVEN", |
d6c3b24e | 112 | "ARCTURUS", |
1eee4228 | 113 | "RENOIR", |
d46b417a | 114 | "ALDEBARAN", |
852a6626 | 115 | "NAVI10", |
87dbad02 | 116 | "NAVI14", |
9802f5d7 | 117 | "NAVI12", |
ccaf72d3 | 118 | "SIENNA_CICHLID", |
ddd8fbe7 | 119 | "NAVY_FLOUNDER", |
4f1e9a76 | 120 | "VANGOGH", |
a2468e04 | 121 | "DIMGREY_CAVEFISH", |
d38ceaf9 AD |
122 | "LAST", |
123 | }; | |
124 | ||
dcea6e65 KR |
125 | /** |
126 | * DOC: pcie_replay_count | |
127 | * | |
128 | * The amdgpu driver provides a sysfs API for reporting the total number | |
129 | * of PCIe replays (NAKs) | |
130 | * The file pcie_replay_count is used for this and returns the total | |
131 | * number of replays as a sum of the NAKs generated and NAKs received | |
132 | */ | |
133 | ||
134 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
135 | struct device_attribute *attr, char *buf) | |
136 | { | |
137 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 138 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
139 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
140 | ||
36000c7a | 141 | return sysfs_emit(buf, "%llu\n", cnt); |
dcea6e65 KR |
142 | } |
143 | ||
144 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
145 | amdgpu_device_get_pcie_replay_count, NULL); | |
146 | ||
5494d864 AD |
147 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
148 | ||
bd607166 KR |
149 | /** |
150 | * DOC: product_name | |
151 | * | |
152 | * The amdgpu driver provides a sysfs API for reporting the product name | |
153 | * for the device | |
154 | * The file serial_number is used for this and returns the product name | |
155 | * as returned from the FRU. | |
156 | * NOTE: This is only available for certain server cards | |
157 | */ | |
158 | ||
159 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
160 | struct device_attribute *attr, char *buf) | |
161 | { | |
162 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 163 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 164 | |
36000c7a | 165 | return sysfs_emit(buf, "%s\n", adev->product_name); |
bd607166 KR |
166 | } |
167 | ||
168 | static DEVICE_ATTR(product_name, S_IRUGO, | |
169 | amdgpu_device_get_product_name, NULL); | |
170 | ||
171 | /** | |
172 | * DOC: product_number | |
173 | * | |
174 | * The amdgpu driver provides a sysfs API for reporting the part number | |
175 | * for the device | |
176 | * The file serial_number is used for this and returns the part number | |
177 | * as returned from the FRU. | |
178 | * NOTE: This is only available for certain server cards | |
179 | */ | |
180 | ||
181 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
182 | struct device_attribute *attr, char *buf) | |
183 | { | |
184 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 185 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 186 | |
36000c7a | 187 | return sysfs_emit(buf, "%s\n", adev->product_number); |
bd607166 KR |
188 | } |
189 | ||
190 | static DEVICE_ATTR(product_number, S_IRUGO, | |
191 | amdgpu_device_get_product_number, NULL); | |
192 | ||
193 | /** | |
194 | * DOC: serial_number | |
195 | * | |
196 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
197 | * for the device | |
198 | * The file serial_number is used for this and returns the serial number | |
199 | * as returned from the FRU. | |
200 | * NOTE: This is only available for certain server cards | |
201 | */ | |
202 | ||
203 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
204 | struct device_attribute *attr, char *buf) | |
205 | { | |
206 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 207 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 208 | |
36000c7a | 209 | return sysfs_emit(buf, "%s\n", adev->serial); |
bd607166 KR |
210 | } |
211 | ||
212 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
213 | amdgpu_device_get_serial_number, NULL); | |
214 | ||
fd496ca8 | 215 | /** |
b98c6299 | 216 | * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control |
fd496ca8 AD |
217 | * |
218 | * @dev: drm_device pointer | |
219 | * | |
b98c6299 | 220 | * Returns true if the device is a dGPU with ATPX power control, |
fd496ca8 AD |
221 | * otherwise return false. |
222 | */ | |
b98c6299 | 223 | bool amdgpu_device_supports_px(struct drm_device *dev) |
fd496ca8 AD |
224 | { |
225 | struct amdgpu_device *adev = drm_to_adev(dev); | |
226 | ||
b98c6299 | 227 | if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid()) |
fd496ca8 AD |
228 | return true; |
229 | return false; | |
230 | } | |
231 | ||
e3ecdffa | 232 | /** |
0330b848 | 233 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
234 | * |
235 | * @dev: drm_device pointer | |
236 | * | |
b98c6299 | 237 | * Returns true if the device is a dGPU with ACPI power control, |
e3ecdffa AD |
238 | * otherwise return false. |
239 | */ | |
31af062a | 240 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 241 | { |
1348969a | 242 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 243 | |
b98c6299 AD |
244 | if (adev->has_pr3 || |
245 | ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid())) | |
d38ceaf9 AD |
246 | return true; |
247 | return false; | |
248 | } | |
249 | ||
a69cba42 AD |
250 | /** |
251 | * amdgpu_device_supports_baco - Does the device support BACO | |
252 | * | |
253 | * @dev: drm_device pointer | |
254 | * | |
255 | * Returns true if the device supporte BACO, | |
256 | * otherwise return false. | |
257 | */ | |
258 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
259 | { | |
1348969a | 260 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
261 | |
262 | return amdgpu_asic_supports_baco(adev); | |
263 | } | |
264 | ||
6e3cd2a9 MCC |
265 | /* |
266 | * VRAM access helper functions | |
267 | */ | |
268 | ||
e35e2b11 | 269 | /** |
e35e2b11 TY |
270 | * amdgpu_device_vram_access - read/write a buffer in vram |
271 | * | |
272 | * @adev: amdgpu_device pointer | |
273 | * @pos: offset of the buffer in vram | |
274 | * @buf: virtual address of the buffer in system memory | |
275 | * @size: read/write size, sizeof(@buf) must > @size | |
276 | * @write: true - write to vram, otherwise - read from vram | |
277 | */ | |
278 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
279 | uint32_t *buf, size_t size, bool write) | |
280 | { | |
e35e2b11 | 281 | unsigned long flags; |
ce05ac56 CK |
282 | uint32_t hi = ~0; |
283 | uint64_t last; | |
284 | ||
9d11eb0d CK |
285 | |
286 | #ifdef CONFIG_64BIT | |
287 | last = min(pos + size, adev->gmc.visible_vram_size); | |
288 | if (last > pos) { | |
289 | void __iomem *addr = adev->mman.aper_base_kaddr + pos; | |
290 | size_t count = last - pos; | |
291 | ||
292 | if (write) { | |
293 | memcpy_toio(addr, buf, count); | |
294 | mb(); | |
295 | amdgpu_asic_flush_hdp(adev, NULL); | |
296 | } else { | |
297 | amdgpu_asic_invalidate_hdp(adev, NULL); | |
298 | mb(); | |
299 | memcpy_fromio(buf, addr, count); | |
300 | } | |
301 | ||
302 | if (count == size) | |
303 | return; | |
304 | ||
305 | pos += count; | |
306 | buf += count / 4; | |
307 | size -= count; | |
308 | } | |
309 | #endif | |
310 | ||
ce05ac56 CK |
311 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); |
312 | for (last = pos + size; pos < last; pos += 4) { | |
313 | uint32_t tmp = pos >> 31; | |
e35e2b11 | 314 | |
e35e2b11 | 315 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); |
ce05ac56 CK |
316 | if (tmp != hi) { |
317 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
318 | hi = tmp; | |
319 | } | |
e35e2b11 TY |
320 | if (write) |
321 | WREG32_NO_KIQ(mmMM_DATA, *buf++); | |
322 | else | |
323 | *buf++ = RREG32_NO_KIQ(mmMM_DATA); | |
e35e2b11 | 324 | } |
ce05ac56 | 325 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); |
e35e2b11 TY |
326 | } |
327 | ||
d38ceaf9 | 328 | /* |
f7ee1874 | 329 | * register access helper functions. |
d38ceaf9 | 330 | */ |
56b53c0b DL |
331 | |
332 | /* Check if hw access should be skipped because of hotplug or device error */ | |
333 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
334 | { | |
335 | if (adev->in_pci_err_recovery) | |
336 | return true; | |
337 | ||
338 | #ifdef CONFIG_LOCKDEP | |
339 | /* | |
340 | * This is a bit complicated to understand, so worth a comment. What we assert | |
341 | * here is that the GPU reset is not running on another thread in parallel. | |
342 | * | |
343 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
344 | * we know that the reset is not running in paralell. | |
345 | * | |
346 | * If the trylock fails we assert that we are either already holding the read | |
347 | * side of the lock or are the reset thread itself and hold the write side of | |
348 | * the lock. | |
349 | */ | |
350 | if (in_task()) { | |
351 | if (down_read_trylock(&adev->reset_sem)) | |
352 | up_read(&adev->reset_sem); | |
353 | else | |
354 | lockdep_assert_held(&adev->reset_sem); | |
355 | } | |
356 | #endif | |
357 | return false; | |
358 | } | |
359 | ||
e3ecdffa | 360 | /** |
f7ee1874 | 361 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
362 | * |
363 | * @adev: amdgpu_device pointer | |
364 | * @reg: dword aligned register offset | |
365 | * @acc_flags: access flags which require special behavior | |
366 | * | |
367 | * Returns the 32 bit value from the offset specified. | |
368 | */ | |
f7ee1874 HZ |
369 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
370 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 371 | { |
f4b373f4 TSD |
372 | uint32_t ret; |
373 | ||
56b53c0b | 374 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
375 | return 0; |
376 | ||
f7ee1874 HZ |
377 | if ((reg * 4) < adev->rmmio_size) { |
378 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
379 | amdgpu_sriov_runtime(adev) && | |
380 | down_read_trylock(&adev->reset_sem)) { | |
381 | ret = amdgpu_kiq_rreg(adev, reg); | |
382 | up_read(&adev->reset_sem); | |
383 | } else { | |
384 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
385 | } | |
386 | } else { | |
387 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 388 | } |
bc992ba5 | 389 | |
f7ee1874 | 390 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 391 | |
f4b373f4 | 392 | return ret; |
d38ceaf9 AD |
393 | } |
394 | ||
421a2a30 ML |
395 | /* |
396 | * MMIO register read with bytes helper functions | |
397 | * @offset:bytes offset from MMIO start | |
398 | * | |
399 | */ | |
400 | ||
e3ecdffa AD |
401 | /** |
402 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
403 | * | |
404 | * @adev: amdgpu_device pointer | |
405 | * @offset: byte aligned register offset | |
406 | * | |
407 | * Returns the 8 bit value from the offset specified. | |
408 | */ | |
7cbbc745 AG |
409 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
410 | { | |
56b53c0b | 411 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
412 | return 0; |
413 | ||
421a2a30 ML |
414 | if (offset < adev->rmmio_size) |
415 | return (readb(adev->rmmio + offset)); | |
416 | BUG(); | |
417 | } | |
418 | ||
419 | /* | |
420 | * MMIO register write with bytes helper functions | |
421 | * @offset:bytes offset from MMIO start | |
422 | * @value: the value want to be written to the register | |
423 | * | |
424 | */ | |
e3ecdffa AD |
425 | /** |
426 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
427 | * | |
428 | * @adev: amdgpu_device pointer | |
429 | * @offset: byte aligned register offset | |
430 | * @value: 8 bit value to write | |
431 | * | |
432 | * Writes the value specified to the offset specified. | |
433 | */ | |
7cbbc745 AG |
434 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
435 | { | |
56b53c0b | 436 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
437 | return; |
438 | ||
421a2a30 ML |
439 | if (offset < adev->rmmio_size) |
440 | writeb(value, adev->rmmio + offset); | |
441 | else | |
442 | BUG(); | |
443 | } | |
444 | ||
e3ecdffa | 445 | /** |
f7ee1874 | 446 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
447 | * |
448 | * @adev: amdgpu_device pointer | |
449 | * @reg: dword aligned register offset | |
450 | * @v: 32 bit value to write to the register | |
451 | * @acc_flags: access flags which require special behavior | |
452 | * | |
453 | * Writes the value specified to the offset specified. | |
454 | */ | |
f7ee1874 HZ |
455 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
456 | uint32_t reg, uint32_t v, | |
457 | uint32_t acc_flags) | |
d38ceaf9 | 458 | { |
56b53c0b | 459 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
460 | return; |
461 | ||
f7ee1874 HZ |
462 | if ((reg * 4) < adev->rmmio_size) { |
463 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
464 | amdgpu_sriov_runtime(adev) && | |
465 | down_read_trylock(&adev->reset_sem)) { | |
466 | amdgpu_kiq_wreg(adev, reg, v); | |
467 | up_read(&adev->reset_sem); | |
468 | } else { | |
469 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
470 | } | |
471 | } else { | |
472 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 473 | } |
bc992ba5 | 474 | |
f7ee1874 | 475 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 476 | } |
d38ceaf9 | 477 | |
2e0cc4d4 ML |
478 | /* |
479 | * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range | |
480 | * | |
481 | * this function is invoked only the debugfs register access | |
482 | * */ | |
f7ee1874 HZ |
483 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
484 | uint32_t reg, uint32_t v) | |
2e0cc4d4 | 485 | { |
56b53c0b | 486 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
487 | return; |
488 | ||
2e0cc4d4 | 489 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
490 | adev->gfx.rlc.funcs && |
491 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 | 492 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
5e025531 | 493 | return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0); |
f7ee1874 HZ |
494 | } else { |
495 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 496 | } |
d38ceaf9 AD |
497 | } |
498 | ||
d38ceaf9 AD |
499 | /** |
500 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
501 | * | |
502 | * @adev: amdgpu_device pointer | |
503 | * @index: doorbell index | |
504 | * | |
505 | * Returns the value in the doorbell aperture at the | |
506 | * requested doorbell index (CIK). | |
507 | */ | |
508 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
509 | { | |
56b53c0b | 510 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
511 | return 0; |
512 | ||
d38ceaf9 AD |
513 | if (index < adev->doorbell.num_doorbells) { |
514 | return readl(adev->doorbell.ptr + index); | |
515 | } else { | |
516 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
517 | return 0; | |
518 | } | |
519 | } | |
520 | ||
521 | /** | |
522 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
523 | * | |
524 | * @adev: amdgpu_device pointer | |
525 | * @index: doorbell index | |
526 | * @v: value to write | |
527 | * | |
528 | * Writes @v to the doorbell aperture at the | |
529 | * requested doorbell index (CIK). | |
530 | */ | |
531 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
532 | { | |
56b53c0b | 533 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
534 | return; |
535 | ||
d38ceaf9 AD |
536 | if (index < adev->doorbell.num_doorbells) { |
537 | writel(v, adev->doorbell.ptr + index); | |
538 | } else { | |
539 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
540 | } | |
541 | } | |
542 | ||
832be404 KW |
543 | /** |
544 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
545 | * | |
546 | * @adev: amdgpu_device pointer | |
547 | * @index: doorbell index | |
548 | * | |
549 | * Returns the value in the doorbell aperture at the | |
550 | * requested doorbell index (VEGA10+). | |
551 | */ | |
552 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
553 | { | |
56b53c0b | 554 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
555 | return 0; |
556 | ||
832be404 KW |
557 | if (index < adev->doorbell.num_doorbells) { |
558 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
559 | } else { | |
560 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
561 | return 0; | |
562 | } | |
563 | } | |
564 | ||
565 | /** | |
566 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
567 | * | |
568 | * @adev: amdgpu_device pointer | |
569 | * @index: doorbell index | |
570 | * @v: value to write | |
571 | * | |
572 | * Writes @v to the doorbell aperture at the | |
573 | * requested doorbell index (VEGA10+). | |
574 | */ | |
575 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
576 | { | |
56b53c0b | 577 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
578 | return; |
579 | ||
832be404 KW |
580 | if (index < adev->doorbell.num_doorbells) { |
581 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
582 | } else { | |
583 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
584 | } | |
585 | } | |
586 | ||
1bba3683 HZ |
587 | /** |
588 | * amdgpu_device_indirect_rreg - read an indirect register | |
589 | * | |
590 | * @adev: amdgpu_device pointer | |
591 | * @pcie_index: mmio register offset | |
592 | * @pcie_data: mmio register offset | |
22f453fb | 593 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
594 | * |
595 | * Returns the value of indirect register @reg_addr | |
596 | */ | |
597 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
598 | u32 pcie_index, u32 pcie_data, | |
599 | u32 reg_addr) | |
600 | { | |
601 | unsigned long flags; | |
602 | u32 r; | |
603 | void __iomem *pcie_index_offset; | |
604 | void __iomem *pcie_data_offset; | |
605 | ||
606 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
607 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
608 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
609 | ||
610 | writel(reg_addr, pcie_index_offset); | |
611 | readl(pcie_index_offset); | |
612 | r = readl(pcie_data_offset); | |
613 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
614 | ||
615 | return r; | |
616 | } | |
617 | ||
618 | /** | |
619 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
620 | * | |
621 | * @adev: amdgpu_device pointer | |
622 | * @pcie_index: mmio register offset | |
623 | * @pcie_data: mmio register offset | |
22f453fb | 624 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
625 | * |
626 | * Returns the value of indirect register @reg_addr | |
627 | */ | |
628 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
629 | u32 pcie_index, u32 pcie_data, | |
630 | u32 reg_addr) | |
631 | { | |
632 | unsigned long flags; | |
633 | u64 r; | |
634 | void __iomem *pcie_index_offset; | |
635 | void __iomem *pcie_data_offset; | |
636 | ||
637 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
638 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
639 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
640 | ||
641 | /* read low 32 bits */ | |
642 | writel(reg_addr, pcie_index_offset); | |
643 | readl(pcie_index_offset); | |
644 | r = readl(pcie_data_offset); | |
645 | /* read high 32 bits */ | |
646 | writel(reg_addr + 4, pcie_index_offset); | |
647 | readl(pcie_index_offset); | |
648 | r |= ((u64)readl(pcie_data_offset) << 32); | |
649 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
650 | ||
651 | return r; | |
652 | } | |
653 | ||
654 | /** | |
655 | * amdgpu_device_indirect_wreg - write an indirect register address | |
656 | * | |
657 | * @adev: amdgpu_device pointer | |
658 | * @pcie_index: mmio register offset | |
659 | * @pcie_data: mmio register offset | |
660 | * @reg_addr: indirect register offset | |
661 | * @reg_data: indirect register data | |
662 | * | |
663 | */ | |
664 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
665 | u32 pcie_index, u32 pcie_data, | |
666 | u32 reg_addr, u32 reg_data) | |
667 | { | |
668 | unsigned long flags; | |
669 | void __iomem *pcie_index_offset; | |
670 | void __iomem *pcie_data_offset; | |
671 | ||
672 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
673 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
674 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
675 | ||
676 | writel(reg_addr, pcie_index_offset); | |
677 | readl(pcie_index_offset); | |
678 | writel(reg_data, pcie_data_offset); | |
679 | readl(pcie_data_offset); | |
680 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
681 | } | |
682 | ||
683 | /** | |
684 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
685 | * | |
686 | * @adev: amdgpu_device pointer | |
687 | * @pcie_index: mmio register offset | |
688 | * @pcie_data: mmio register offset | |
689 | * @reg_addr: indirect register offset | |
690 | * @reg_data: indirect register data | |
691 | * | |
692 | */ | |
693 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
694 | u32 pcie_index, u32 pcie_data, | |
695 | u32 reg_addr, u64 reg_data) | |
696 | { | |
697 | unsigned long flags; | |
698 | void __iomem *pcie_index_offset; | |
699 | void __iomem *pcie_data_offset; | |
700 | ||
701 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
702 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
703 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
704 | ||
705 | /* write low 32 bits */ | |
706 | writel(reg_addr, pcie_index_offset); | |
707 | readl(pcie_index_offset); | |
708 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
709 | readl(pcie_data_offset); | |
710 | /* write high 32 bits */ | |
711 | writel(reg_addr + 4, pcie_index_offset); | |
712 | readl(pcie_index_offset); | |
713 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
714 | readl(pcie_data_offset); | |
715 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
716 | } | |
717 | ||
d38ceaf9 AD |
718 | /** |
719 | * amdgpu_invalid_rreg - dummy reg read function | |
720 | * | |
982a820b | 721 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
722 | * @reg: offset of register |
723 | * | |
724 | * Dummy register read function. Used for register blocks | |
725 | * that certain asics don't have (all asics). | |
726 | * Returns the value in the register. | |
727 | */ | |
728 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
729 | { | |
730 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
731 | BUG(); | |
732 | return 0; | |
733 | } | |
734 | ||
735 | /** | |
736 | * amdgpu_invalid_wreg - dummy reg write function | |
737 | * | |
982a820b | 738 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
739 | * @reg: offset of register |
740 | * @v: value to write to the register | |
741 | * | |
742 | * Dummy register read function. Used for register blocks | |
743 | * that certain asics don't have (all asics). | |
744 | */ | |
745 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
746 | { | |
747 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
748 | reg, v); | |
749 | BUG(); | |
750 | } | |
751 | ||
4fa1c6a6 TZ |
752 | /** |
753 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
754 | * | |
982a820b | 755 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
756 | * @reg: offset of register |
757 | * | |
758 | * Dummy register read function. Used for register blocks | |
759 | * that certain asics don't have (all asics). | |
760 | * Returns the value in the register. | |
761 | */ | |
762 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
763 | { | |
764 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
765 | BUG(); | |
766 | return 0; | |
767 | } | |
768 | ||
769 | /** | |
770 | * amdgpu_invalid_wreg64 - dummy reg write function | |
771 | * | |
982a820b | 772 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
773 | * @reg: offset of register |
774 | * @v: value to write to the register | |
775 | * | |
776 | * Dummy register read function. Used for register blocks | |
777 | * that certain asics don't have (all asics). | |
778 | */ | |
779 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
780 | { | |
781 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
782 | reg, v); | |
783 | BUG(); | |
784 | } | |
785 | ||
d38ceaf9 AD |
786 | /** |
787 | * amdgpu_block_invalid_rreg - dummy reg read function | |
788 | * | |
982a820b | 789 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
790 | * @block: offset of instance |
791 | * @reg: offset of register | |
792 | * | |
793 | * Dummy register read function. Used for register blocks | |
794 | * that certain asics don't have (all asics). | |
795 | * Returns the value in the register. | |
796 | */ | |
797 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
798 | uint32_t block, uint32_t reg) | |
799 | { | |
800 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
801 | reg, block); | |
802 | BUG(); | |
803 | return 0; | |
804 | } | |
805 | ||
806 | /** | |
807 | * amdgpu_block_invalid_wreg - dummy reg write function | |
808 | * | |
982a820b | 809 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
810 | * @block: offset of instance |
811 | * @reg: offset of register | |
812 | * @v: value to write to the register | |
813 | * | |
814 | * Dummy register read function. Used for register blocks | |
815 | * that certain asics don't have (all asics). | |
816 | */ | |
817 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
818 | uint32_t block, | |
819 | uint32_t reg, uint32_t v) | |
820 | { | |
821 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
822 | reg, block, v); | |
823 | BUG(); | |
824 | } | |
825 | ||
4d2997ab AD |
826 | /** |
827 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
828 | * | |
982a820b | 829 | * @adev: amdgpu_device pointer |
4d2997ab AD |
830 | * |
831 | * Does any asic specific work and then calls atom asic init. | |
832 | */ | |
833 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
834 | { | |
835 | amdgpu_asic_pre_asic_init(adev); | |
836 | ||
837 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
838 | } | |
839 | ||
e3ecdffa AD |
840 | /** |
841 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
842 | * | |
982a820b | 843 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
844 | * |
845 | * Allocates a scratch page of VRAM for use by various things in the | |
846 | * driver. | |
847 | */ | |
06ec9070 | 848 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 849 | { |
a4a02777 CK |
850 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
851 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
852 | &adev->vram_scratch.robj, | |
853 | &adev->vram_scratch.gpu_addr, | |
854 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
855 | } |
856 | ||
e3ecdffa AD |
857 | /** |
858 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
859 | * | |
982a820b | 860 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
861 | * |
862 | * Frees the VRAM scratch page. | |
863 | */ | |
06ec9070 | 864 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 865 | { |
078af1a3 | 866 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
867 | } |
868 | ||
869 | /** | |
9c3f2b54 | 870 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
871 | * |
872 | * @adev: amdgpu_device pointer | |
873 | * @registers: pointer to the register array | |
874 | * @array_size: size of the register array | |
875 | * | |
876 | * Programs an array or registers with and and or masks. | |
877 | * This is a helper for setting golden registers. | |
878 | */ | |
9c3f2b54 AD |
879 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
880 | const u32 *registers, | |
881 | const u32 array_size) | |
d38ceaf9 AD |
882 | { |
883 | u32 tmp, reg, and_mask, or_mask; | |
884 | int i; | |
885 | ||
886 | if (array_size % 3) | |
887 | return; | |
888 | ||
889 | for (i = 0; i < array_size; i +=3) { | |
890 | reg = registers[i + 0]; | |
891 | and_mask = registers[i + 1]; | |
892 | or_mask = registers[i + 2]; | |
893 | ||
894 | if (and_mask == 0xffffffff) { | |
895 | tmp = or_mask; | |
896 | } else { | |
897 | tmp = RREG32(reg); | |
898 | tmp &= ~and_mask; | |
e0d07657 HZ |
899 | if (adev->family >= AMDGPU_FAMILY_AI) |
900 | tmp |= (or_mask & and_mask); | |
901 | else | |
902 | tmp |= or_mask; | |
d38ceaf9 AD |
903 | } |
904 | WREG32(reg, tmp); | |
905 | } | |
906 | } | |
907 | ||
e3ecdffa AD |
908 | /** |
909 | * amdgpu_device_pci_config_reset - reset the GPU | |
910 | * | |
911 | * @adev: amdgpu_device pointer | |
912 | * | |
913 | * Resets the GPU using the pci config reset sequence. | |
914 | * Only applicable to asics prior to vega10. | |
915 | */ | |
8111c387 | 916 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
917 | { |
918 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
919 | } | |
920 | ||
af484df8 AD |
921 | /** |
922 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
923 | * | |
924 | * @adev: amdgpu_device pointer | |
925 | * | |
926 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
927 | */ | |
928 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
929 | { | |
930 | return pci_reset_function(adev->pdev); | |
931 | } | |
932 | ||
d38ceaf9 AD |
933 | /* |
934 | * GPU doorbell aperture helpers function. | |
935 | */ | |
936 | /** | |
06ec9070 | 937 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
938 | * |
939 | * @adev: amdgpu_device pointer | |
940 | * | |
941 | * Init doorbell driver information (CIK) | |
942 | * Returns 0 on success, error on failure. | |
943 | */ | |
06ec9070 | 944 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 945 | { |
6585661d | 946 | |
705e519e CK |
947 | /* No doorbell on SI hardware generation */ |
948 | if (adev->asic_type < CHIP_BONAIRE) { | |
949 | adev->doorbell.base = 0; | |
950 | adev->doorbell.size = 0; | |
951 | adev->doorbell.num_doorbells = 0; | |
952 | adev->doorbell.ptr = NULL; | |
953 | return 0; | |
954 | } | |
955 | ||
d6895ad3 CK |
956 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
957 | return -EINVAL; | |
958 | ||
22357775 AD |
959 | amdgpu_asic_init_doorbell_index(adev); |
960 | ||
d38ceaf9 AD |
961 | /* doorbell bar mapping */ |
962 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
963 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
964 | ||
edf600da | 965 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 966 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
967 | if (adev->doorbell.num_doorbells == 0) |
968 | return -EINVAL; | |
969 | ||
ec3db8a6 | 970 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
971 | * paging queue doorbell use the second page. The |
972 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
973 | * doorbells are in the first page. So with paging queue enabled, | |
974 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
975 | */ |
976 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 977 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 978 | |
8972e5d2 CK |
979 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
980 | adev->doorbell.num_doorbells * | |
981 | sizeof(u32)); | |
982 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 983 | return -ENOMEM; |
d38ceaf9 AD |
984 | |
985 | return 0; | |
986 | } | |
987 | ||
988 | /** | |
06ec9070 | 989 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
990 | * |
991 | * @adev: amdgpu_device pointer | |
992 | * | |
993 | * Tear down doorbell driver information (CIK) | |
994 | */ | |
06ec9070 | 995 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
996 | { |
997 | iounmap(adev->doorbell.ptr); | |
998 | adev->doorbell.ptr = NULL; | |
999 | } | |
1000 | ||
22cb0164 | 1001 | |
d38ceaf9 AD |
1002 | |
1003 | /* | |
06ec9070 | 1004 | * amdgpu_device_wb_*() |
455a7bc2 | 1005 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1006 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1007 | */ |
1008 | ||
1009 | /** | |
06ec9070 | 1010 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1011 | * |
1012 | * @adev: amdgpu_device pointer | |
1013 | * | |
1014 | * Disables Writeback and frees the Writeback memory (all asics). | |
1015 | * Used at driver shutdown. | |
1016 | */ | |
06ec9070 | 1017 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1018 | { |
1019 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1020 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1021 | &adev->wb.gpu_addr, | |
1022 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1023 | adev->wb.wb_obj = NULL; |
1024 | } | |
1025 | } | |
1026 | ||
1027 | /** | |
06ec9070 | 1028 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1029 | * |
1030 | * @adev: amdgpu_device pointer | |
1031 | * | |
455a7bc2 | 1032 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1033 | * Used at driver startup. |
1034 | * Returns 0 on success or an -error on failure. | |
1035 | */ | |
06ec9070 | 1036 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1037 | { |
1038 | int r; | |
1039 | ||
1040 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1041 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1042 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1043 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1044 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1045 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1046 | if (r) { |
1047 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1048 | return r; | |
1049 | } | |
d38ceaf9 AD |
1050 | |
1051 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1052 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1053 | ||
1054 | /* clear wb memory */ | |
73469585 | 1055 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1056 | } |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | /** | |
131b4b36 | 1062 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1063 | * |
1064 | * @adev: amdgpu_device pointer | |
1065 | * @wb: wb index | |
1066 | * | |
1067 | * Allocate a wb slot for use by the driver (all asics). | |
1068 | * Returns 0 on success or -EINVAL on failure. | |
1069 | */ | |
131b4b36 | 1070 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1071 | { |
1072 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1073 | |
97407b63 | 1074 | if (offset < adev->wb.num_wb) { |
7014285a | 1075 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1076 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1077 | return 0; |
1078 | } else { | |
1079 | return -EINVAL; | |
1080 | } | |
1081 | } | |
1082 | ||
d38ceaf9 | 1083 | /** |
131b4b36 | 1084 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1085 | * |
1086 | * @adev: amdgpu_device pointer | |
1087 | * @wb: wb index | |
1088 | * | |
1089 | * Free a wb slot allocated for use by the driver (all asics) | |
1090 | */ | |
131b4b36 | 1091 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1092 | { |
73469585 | 1093 | wb >>= 3; |
d38ceaf9 | 1094 | if (wb < adev->wb.num_wb) |
73469585 | 1095 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1096 | } |
1097 | ||
d6895ad3 CK |
1098 | /** |
1099 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1100 | * | |
1101 | * @adev: amdgpu_device pointer | |
1102 | * | |
1103 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1104 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1105 | * driver loading by returning -ENODEV. | |
1106 | */ | |
1107 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1108 | { | |
453f617a | 1109 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1110 | struct pci_bus *root; |
1111 | struct resource *res; | |
1112 | unsigned i; | |
d6895ad3 CK |
1113 | u16 cmd; |
1114 | int r; | |
1115 | ||
0c03b912 | 1116 | /* Bypass for VF */ |
1117 | if (amdgpu_sriov_vf(adev)) | |
1118 | return 0; | |
1119 | ||
b7221f2b AD |
1120 | /* skip if the bios has already enabled large BAR */ |
1121 | if (adev->gmc.real_vram_size && | |
1122 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1123 | return 0; | |
1124 | ||
31b8adab CK |
1125 | /* Check if the root BUS has 64bit memory resources */ |
1126 | root = adev->pdev->bus; | |
1127 | while (root->parent) | |
1128 | root = root->parent; | |
1129 | ||
1130 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1131 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1132 | res->start > 0x100000000ull) |
1133 | break; | |
1134 | } | |
1135 | ||
1136 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1137 | if (!res) | |
1138 | return 0; | |
1139 | ||
453f617a ND |
1140 | /* Limit the BAR size to what is available */ |
1141 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1142 | rbar_size); | |
1143 | ||
d6895ad3 CK |
1144 | /* Disable memory decoding while we change the BAR addresses and size */ |
1145 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1146 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1147 | cmd & ~PCI_COMMAND_MEMORY); | |
1148 | ||
1149 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 1150 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
1151 | if (adev->asic_type >= CHIP_BONAIRE) |
1152 | pci_release_resource(adev->pdev, 2); | |
1153 | ||
1154 | pci_release_resource(adev->pdev, 0); | |
1155 | ||
1156 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1157 | if (r == -ENOSPC) | |
1158 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1159 | else if (r && r != -ENOTSUPP) | |
1160 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1161 | ||
1162 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1163 | ||
1164 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1165 | * using the device. | |
1166 | */ | |
06ec9070 | 1167 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
1168 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1169 | return -ENODEV; | |
1170 | ||
1171 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1172 | ||
1173 | return 0; | |
1174 | } | |
a05502e5 | 1175 | |
d38ceaf9 AD |
1176 | /* |
1177 | * GPU helpers function. | |
1178 | */ | |
1179 | /** | |
39c640c0 | 1180 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1181 | * |
1182 | * @adev: amdgpu_device pointer | |
1183 | * | |
c836fec5 JQ |
1184 | * Check if the asic has been initialized (all asics) at driver startup |
1185 | * or post is needed if hw reset is performed. | |
1186 | * Returns true if need or false if not. | |
d38ceaf9 | 1187 | */ |
39c640c0 | 1188 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1189 | { |
1190 | uint32_t reg; | |
1191 | ||
bec86378 ML |
1192 | if (amdgpu_sriov_vf(adev)) |
1193 | return false; | |
1194 | ||
1195 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1196 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1197 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1198 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1199 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1200 | */ |
1201 | if (adev->asic_type == CHIP_FIJI) { | |
1202 | int err; | |
1203 | uint32_t fw_ver; | |
1204 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1205 | /* force vPost if error occured */ | |
1206 | if (err) | |
1207 | return true; | |
1208 | ||
1209 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1210 | if (fw_ver < 0x00160e00) |
1211 | return true; | |
bec86378 | 1212 | } |
bec86378 | 1213 | } |
91fe77eb | 1214 | |
e3c1b071 | 1215 | /* Don't post if we need to reset whole hive on init */ |
1216 | if (adev->gmc.xgmi.pending_reset) | |
1217 | return false; | |
1218 | ||
91fe77eb | 1219 | if (adev->has_hw_reset) { |
1220 | adev->has_hw_reset = false; | |
1221 | return true; | |
1222 | } | |
1223 | ||
1224 | /* bios scratch used on CIK+ */ | |
1225 | if (adev->asic_type >= CHIP_BONAIRE) | |
1226 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1227 | ||
1228 | /* check MEM_SIZE for older asics */ | |
1229 | reg = amdgpu_asic_get_config_memsize(adev); | |
1230 | ||
1231 | if ((reg != 0) && (reg != 0xffffffff)) | |
1232 | return false; | |
1233 | ||
1234 | return true; | |
bec86378 ML |
1235 | } |
1236 | ||
d38ceaf9 AD |
1237 | /* if we get transitioned to only one device, take VGA back */ |
1238 | /** | |
06ec9070 | 1239 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
1240 | * |
1241 | * @cookie: amdgpu_device pointer | |
1242 | * @state: enable/disable vga decode | |
1243 | * | |
1244 | * Enable/disable vga decode (all asics). | |
1245 | * Returns VGA resource flags. | |
1246 | */ | |
06ec9070 | 1247 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
1248 | { |
1249 | struct amdgpu_device *adev = cookie; | |
1250 | amdgpu_asic_set_vga_state(adev, state); | |
1251 | if (state) | |
1252 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1253 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1254 | else | |
1255 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1256 | } | |
1257 | ||
e3ecdffa AD |
1258 | /** |
1259 | * amdgpu_device_check_block_size - validate the vm block size | |
1260 | * | |
1261 | * @adev: amdgpu_device pointer | |
1262 | * | |
1263 | * Validates the vm block size specified via module parameter. | |
1264 | * The vm block size defines number of bits in page table versus page directory, | |
1265 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1266 | * page table and the remaining bits are in the page directory. | |
1267 | */ | |
06ec9070 | 1268 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1269 | { |
1270 | /* defines number of bits in page table versus page directory, | |
1271 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1272 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1273 | if (amdgpu_vm_block_size == -1) |
1274 | return; | |
a1adf8be | 1275 | |
bab4fee7 | 1276 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1277 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1278 | amdgpu_vm_block_size); | |
97489129 | 1279 | amdgpu_vm_block_size = -1; |
a1adf8be | 1280 | } |
a1adf8be CZ |
1281 | } |
1282 | ||
e3ecdffa AD |
1283 | /** |
1284 | * amdgpu_device_check_vm_size - validate the vm size | |
1285 | * | |
1286 | * @adev: amdgpu_device pointer | |
1287 | * | |
1288 | * Validates the vm size in GB specified via module parameter. | |
1289 | * The VM size is the size of the GPU virtual memory space in GB. | |
1290 | */ | |
06ec9070 | 1291 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1292 | { |
64dab074 AD |
1293 | /* no need to check the default value */ |
1294 | if (amdgpu_vm_size == -1) | |
1295 | return; | |
1296 | ||
83ca145d ZJ |
1297 | if (amdgpu_vm_size < 1) { |
1298 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1299 | amdgpu_vm_size); | |
f3368128 | 1300 | amdgpu_vm_size = -1; |
83ca145d | 1301 | } |
83ca145d ZJ |
1302 | } |
1303 | ||
7951e376 RZ |
1304 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1305 | { | |
1306 | struct sysinfo si; | |
a9d4fe2f | 1307 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1308 | uint64_t total_memory; |
1309 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1310 | uint64_t dram_size_three_GB = 0xB8000000; | |
1311 | ||
1312 | if (amdgpu_smu_memory_pool_size == 0) | |
1313 | return; | |
1314 | ||
1315 | if (!is_os_64) { | |
1316 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1317 | goto def_value; | |
1318 | } | |
1319 | si_meminfo(&si); | |
1320 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1321 | ||
1322 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1323 | (amdgpu_smu_memory_pool_size == 2)) { | |
1324 | if (total_memory < dram_size_three_GB) | |
1325 | goto def_value1; | |
1326 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1327 | (amdgpu_smu_memory_pool_size == 8)) { | |
1328 | if (total_memory < dram_size_seven_GB) | |
1329 | goto def_value1; | |
1330 | } else { | |
1331 | DRM_WARN("Smu memory pool size not supported\n"); | |
1332 | goto def_value; | |
1333 | } | |
1334 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1335 | ||
1336 | return; | |
1337 | ||
1338 | def_value1: | |
1339 | DRM_WARN("No enough system memory\n"); | |
1340 | def_value: | |
1341 | adev->pm.smu_prv_buffer_size = 0; | |
1342 | } | |
1343 | ||
d38ceaf9 | 1344 | /** |
06ec9070 | 1345 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1346 | * |
1347 | * @adev: amdgpu_device pointer | |
1348 | * | |
1349 | * Validates certain module parameters and updates | |
1350 | * the associated values used by the driver (all asics). | |
1351 | */ | |
912dfc84 | 1352 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1353 | { |
5b011235 CZ |
1354 | if (amdgpu_sched_jobs < 4) { |
1355 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1356 | amdgpu_sched_jobs); | |
1357 | amdgpu_sched_jobs = 4; | |
76117507 | 1358 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1359 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1360 | amdgpu_sched_jobs); | |
1361 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1362 | } | |
d38ceaf9 | 1363 | |
83e74db6 | 1364 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1365 | /* gart size must be greater or equal to 32M */ |
1366 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1367 | amdgpu_gart_size); | |
83e74db6 | 1368 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1369 | } |
1370 | ||
36d38372 | 1371 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1372 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1373 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1374 | amdgpu_gtt_size); | |
1375 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1376 | } |
1377 | ||
d07f14be RH |
1378 | /* valid range is between 4 and 9 inclusive */ |
1379 | if (amdgpu_vm_fragment_size != -1 && | |
1380 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1381 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1382 | amdgpu_vm_fragment_size = -1; | |
1383 | } | |
1384 | ||
5d5bd5e3 KW |
1385 | if (amdgpu_sched_hw_submission < 2) { |
1386 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1387 | amdgpu_sched_hw_submission); | |
1388 | amdgpu_sched_hw_submission = 2; | |
1389 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1390 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1391 | amdgpu_sched_hw_submission); | |
1392 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1393 | } | |
1394 | ||
7951e376 RZ |
1395 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1396 | ||
06ec9070 | 1397 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1398 | |
06ec9070 | 1399 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1400 | |
19aede77 | 1401 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1402 | |
c6252390 | 1403 | amdgpu_gmc_tmz_set(adev); |
01a8dcec | 1404 | |
9b498efa AD |
1405 | amdgpu_gmc_noretry_set(adev); |
1406 | ||
e3c00faa | 1407 | return 0; |
d38ceaf9 AD |
1408 | } |
1409 | ||
1410 | /** | |
1411 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1412 | * | |
1413 | * @pdev: pci dev pointer | |
1694467b | 1414 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1415 | * |
1416 | * Callback for the switcheroo driver. Suspends or resumes the | |
1417 | * the asics before or after it is powered up using ACPI methods. | |
1418 | */ | |
8aba21b7 LT |
1419 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1420 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1421 | { |
1422 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1423 | int r; |
d38ceaf9 | 1424 | |
b98c6299 | 1425 | if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1426 | return; |
1427 | ||
1428 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1429 | pr_info("switched on\n"); |
d38ceaf9 AD |
1430 | /* don't suspend or resume card normally */ |
1431 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1432 | ||
8f66090b TZ |
1433 | pci_set_power_state(pdev, PCI_D0); |
1434 | amdgpu_device_load_pci_state(pdev); | |
1435 | r = pci_enable_device(pdev); | |
de185019 AD |
1436 | if (r) |
1437 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1438 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1439 | |
d38ceaf9 | 1440 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1441 | } else { |
dd4fa6c1 | 1442 | pr_info("switched off\n"); |
d38ceaf9 | 1443 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
de185019 | 1444 | amdgpu_device_suspend(dev, true); |
8f66090b | 1445 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1446 | /* Shut down the device */ |
8f66090b TZ |
1447 | pci_disable_device(pdev); |
1448 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1449 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1450 | } | |
1451 | } | |
1452 | ||
1453 | /** | |
1454 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1455 | * | |
1456 | * @pdev: pci dev pointer | |
1457 | * | |
1458 | * Callback for the switcheroo driver. Check of the switcheroo | |
1459 | * state can be changed. | |
1460 | * Returns true if the state can be changed, false if not. | |
1461 | */ | |
1462 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1463 | { | |
1464 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1465 | ||
1466 | /* | |
1467 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1468 | * locking inversion with the driver load path. And the access here is | |
1469 | * completely racy anyway. So don't bother with locking for now. | |
1470 | */ | |
7e13ad89 | 1471 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1472 | } |
1473 | ||
1474 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1475 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1476 | .reprobe = NULL, | |
1477 | .can_switch = amdgpu_switcheroo_can_switch, | |
1478 | }; | |
1479 | ||
e3ecdffa AD |
1480 | /** |
1481 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1482 | * | |
87e3f136 | 1483 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1484 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1485 | * @state: clockgating state (gate or ungate) | |
1486 | * | |
1487 | * Sets the requested clockgating state for all instances of | |
1488 | * the hardware IP specified. | |
1489 | * Returns the error code from the last instance. | |
1490 | */ | |
43fa561f | 1491 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1492 | enum amd_ip_block_type block_type, |
1493 | enum amd_clockgating_state state) | |
d38ceaf9 | 1494 | { |
43fa561f | 1495 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1496 | int i, r = 0; |
1497 | ||
1498 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1499 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1500 | continue; |
c722865a RZ |
1501 | if (adev->ip_blocks[i].version->type != block_type) |
1502 | continue; | |
1503 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1504 | continue; | |
1505 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1506 | (void *)adev, state); | |
1507 | if (r) | |
1508 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1509 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1510 | } |
1511 | return r; | |
1512 | } | |
1513 | ||
e3ecdffa AD |
1514 | /** |
1515 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1516 | * | |
87e3f136 | 1517 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1518 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1519 | * @state: powergating state (gate or ungate) | |
1520 | * | |
1521 | * Sets the requested powergating state for all instances of | |
1522 | * the hardware IP specified. | |
1523 | * Returns the error code from the last instance. | |
1524 | */ | |
43fa561f | 1525 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1526 | enum amd_ip_block_type block_type, |
1527 | enum amd_powergating_state state) | |
d38ceaf9 | 1528 | { |
43fa561f | 1529 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1530 | int i, r = 0; |
1531 | ||
1532 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1533 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1534 | continue; |
c722865a RZ |
1535 | if (adev->ip_blocks[i].version->type != block_type) |
1536 | continue; | |
1537 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1538 | continue; | |
1539 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1540 | (void *)adev, state); | |
1541 | if (r) | |
1542 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1543 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1544 | } |
1545 | return r; | |
1546 | } | |
1547 | ||
e3ecdffa AD |
1548 | /** |
1549 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1550 | * | |
1551 | * @adev: amdgpu_device pointer | |
1552 | * @flags: clockgating feature flags | |
1553 | * | |
1554 | * Walks the list of IPs on the device and updates the clockgating | |
1555 | * flags for each IP. | |
1556 | * Updates @flags with the feature flags for each hardware IP where | |
1557 | * clockgating is enabled. | |
1558 | */ | |
2990a1fc AD |
1559 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1560 | u32 *flags) | |
6cb2d4e4 HR |
1561 | { |
1562 | int i; | |
1563 | ||
1564 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1565 | if (!adev->ip_blocks[i].status.valid) | |
1566 | continue; | |
1567 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1568 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1569 | } | |
1570 | } | |
1571 | ||
e3ecdffa AD |
1572 | /** |
1573 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1574 | * | |
1575 | * @adev: amdgpu_device pointer | |
1576 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1577 | * | |
1578 | * Waits for the request hardware IP to be idle. | |
1579 | * Returns 0 for success or a negative error code on failure. | |
1580 | */ | |
2990a1fc AD |
1581 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1582 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1583 | { |
1584 | int i, r; | |
1585 | ||
1586 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1587 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1588 | continue; |
a1255107 AD |
1589 | if (adev->ip_blocks[i].version->type == block_type) { |
1590 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1591 | if (r) |
1592 | return r; | |
1593 | break; | |
1594 | } | |
1595 | } | |
1596 | return 0; | |
1597 | ||
1598 | } | |
1599 | ||
e3ecdffa AD |
1600 | /** |
1601 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1602 | * | |
1603 | * @adev: amdgpu_device pointer | |
1604 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1605 | * | |
1606 | * Check if the hardware IP is idle or not. | |
1607 | * Returns true if it the IP is idle, false if not. | |
1608 | */ | |
2990a1fc AD |
1609 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1610 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1611 | { |
1612 | int i; | |
1613 | ||
1614 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1615 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1616 | continue; |
a1255107 AD |
1617 | if (adev->ip_blocks[i].version->type == block_type) |
1618 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1619 | } |
1620 | return true; | |
1621 | ||
1622 | } | |
1623 | ||
e3ecdffa AD |
1624 | /** |
1625 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1626 | * | |
1627 | * @adev: amdgpu_device pointer | |
87e3f136 | 1628 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1629 | * |
1630 | * Returns a pointer to the hardware IP block structure | |
1631 | * if it exists for the asic, otherwise NULL. | |
1632 | */ | |
2990a1fc AD |
1633 | struct amdgpu_ip_block * |
1634 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1635 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1636 | { |
1637 | int i; | |
1638 | ||
1639 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1640 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1641 | return &adev->ip_blocks[i]; |
1642 | ||
1643 | return NULL; | |
1644 | } | |
1645 | ||
1646 | /** | |
2990a1fc | 1647 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1648 | * |
1649 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1650 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1651 | * @major: major version |
1652 | * @minor: minor version | |
1653 | * | |
1654 | * return 0 if equal or greater | |
1655 | * return 1 if smaller or the ip_block doesn't exist | |
1656 | */ | |
2990a1fc AD |
1657 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1658 | enum amd_ip_block_type type, | |
1659 | u32 major, u32 minor) | |
d38ceaf9 | 1660 | { |
2990a1fc | 1661 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1662 | |
a1255107 AD |
1663 | if (ip_block && ((ip_block->version->major > major) || |
1664 | ((ip_block->version->major == major) && | |
1665 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1666 | return 0; |
1667 | ||
1668 | return 1; | |
1669 | } | |
1670 | ||
a1255107 | 1671 | /** |
2990a1fc | 1672 | * amdgpu_device_ip_block_add |
a1255107 AD |
1673 | * |
1674 | * @adev: amdgpu_device pointer | |
1675 | * @ip_block_version: pointer to the IP to add | |
1676 | * | |
1677 | * Adds the IP block driver information to the collection of IPs | |
1678 | * on the asic. | |
1679 | */ | |
2990a1fc AD |
1680 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1681 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1682 | { |
1683 | if (!ip_block_version) | |
1684 | return -EINVAL; | |
1685 | ||
e966a725 | 1686 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1687 | ip_block_version->funcs->name); |
1688 | ||
a1255107 AD |
1689 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
e3ecdffa AD |
1694 | /** |
1695 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1696 | * | |
1697 | * @adev: amdgpu_device pointer | |
1698 | * | |
1699 | * Enabled the virtual display feature if the user has enabled it via | |
1700 | * the module parameter virtual_display. This feature provides a virtual | |
1701 | * display hardware on headless boards or in virtualized environments. | |
1702 | * This function parses and validates the configuration string specified by | |
1703 | * the user and configues the virtual display configuration (number of | |
1704 | * virtual connectors, crtcs, etc.) specified. | |
1705 | */ | |
483ef985 | 1706 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1707 | { |
1708 | adev->enable_virtual_display = false; | |
1709 | ||
1710 | if (amdgpu_virtual_display) { | |
8f66090b | 1711 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 1712 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1713 | |
1714 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1715 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1716 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1717 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1718 | if (!strcmp("all", pciaddname) |
1719 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1720 | long num_crtc; |
1721 | int res = -1; | |
1722 | ||
9accf2fd | 1723 | adev->enable_virtual_display = true; |
0f66356d ED |
1724 | |
1725 | if (pciaddname_tmp) | |
1726 | res = kstrtol(pciaddname_tmp, 10, | |
1727 | &num_crtc); | |
1728 | ||
1729 | if (!res) { | |
1730 | if (num_crtc < 1) | |
1731 | num_crtc = 1; | |
1732 | if (num_crtc > 6) | |
1733 | num_crtc = 6; | |
1734 | adev->mode_info.num_crtc = num_crtc; | |
1735 | } else { | |
1736 | adev->mode_info.num_crtc = 1; | |
1737 | } | |
9accf2fd ED |
1738 | break; |
1739 | } | |
1740 | } | |
1741 | ||
0f66356d ED |
1742 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1743 | amdgpu_virtual_display, pci_address_name, | |
1744 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1745 | |
1746 | kfree(pciaddstr); | |
1747 | } | |
1748 | } | |
1749 | ||
e3ecdffa AD |
1750 | /** |
1751 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1752 | * | |
1753 | * @adev: amdgpu_device pointer | |
1754 | * | |
1755 | * Parses the asic configuration parameters specified in the gpu info | |
1756 | * firmware and makes them availale to the driver for use in configuring | |
1757 | * the asic. | |
1758 | * Returns 0 on success, -EINVAL on failure. | |
1759 | */ | |
e2a75f88 AD |
1760 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1761 | { | |
e2a75f88 | 1762 | const char *chip_name; |
c0a43457 | 1763 | char fw_name[40]; |
e2a75f88 AD |
1764 | int err; |
1765 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1766 | ||
ab4fe3e1 HR |
1767 | adev->firmware.gpu_info_fw = NULL; |
1768 | ||
72de33f8 | 1769 | if (adev->mman.discovery_bin) { |
258620d0 | 1770 | amdgpu_discovery_get_gfx_info(adev); |
cc375d8c TY |
1771 | |
1772 | /* | |
1773 | * FIXME: The bounding box is still needed by Navi12, so | |
1774 | * temporarily read it from gpu_info firmware. Should be droped | |
1775 | * when DAL no longer needs it. | |
1776 | */ | |
1777 | if (adev->asic_type != CHIP_NAVI12) | |
1778 | return 0; | |
258620d0 AD |
1779 | } |
1780 | ||
e2a75f88 | 1781 | switch (adev->asic_type) { |
e2a75f88 AD |
1782 | #ifdef CONFIG_DRM_AMDGPU_SI |
1783 | case CHIP_VERDE: | |
1784 | case CHIP_TAHITI: | |
1785 | case CHIP_PITCAIRN: | |
1786 | case CHIP_OLAND: | |
1787 | case CHIP_HAINAN: | |
1788 | #endif | |
1789 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1790 | case CHIP_BONAIRE: | |
1791 | case CHIP_HAWAII: | |
1792 | case CHIP_KAVERI: | |
1793 | case CHIP_KABINI: | |
1794 | case CHIP_MULLINS: | |
1795 | #endif | |
da87c30b AD |
1796 | case CHIP_TOPAZ: |
1797 | case CHIP_TONGA: | |
1798 | case CHIP_FIJI: | |
1799 | case CHIP_POLARIS10: | |
1800 | case CHIP_POLARIS11: | |
1801 | case CHIP_POLARIS12: | |
1802 | case CHIP_VEGAM: | |
1803 | case CHIP_CARRIZO: | |
1804 | case CHIP_STONEY: | |
27c0bc71 | 1805 | case CHIP_VEGA20: |
44b3253a | 1806 | case CHIP_ALDEBARAN: |
84d244a3 JC |
1807 | case CHIP_SIENNA_CICHLID: |
1808 | case CHIP_NAVY_FLOUNDER: | |
eac88a5f | 1809 | case CHIP_DIMGREY_CAVEFISH: |
e2a75f88 AD |
1810 | default: |
1811 | return 0; | |
1812 | case CHIP_VEGA10: | |
1813 | chip_name = "vega10"; | |
1814 | break; | |
3f76dced AD |
1815 | case CHIP_VEGA12: |
1816 | chip_name = "vega12"; | |
1817 | break; | |
2d2e5e7e | 1818 | case CHIP_RAVEN: |
54f78a76 | 1819 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1820 | chip_name = "raven2"; |
54f78a76 | 1821 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1822 | chip_name = "picasso"; |
54c4d17e FX |
1823 | else |
1824 | chip_name = "raven"; | |
2d2e5e7e | 1825 | break; |
65e60f6e LM |
1826 | case CHIP_ARCTURUS: |
1827 | chip_name = "arcturus"; | |
1828 | break; | |
b51a26a0 | 1829 | case CHIP_RENOIR: |
2e62f0b5 PL |
1830 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
1831 | chip_name = "renoir"; | |
1832 | else | |
1833 | chip_name = "green_sardine"; | |
b51a26a0 | 1834 | break; |
23c6268e HR |
1835 | case CHIP_NAVI10: |
1836 | chip_name = "navi10"; | |
1837 | break; | |
ed42cfe1 XY |
1838 | case CHIP_NAVI14: |
1839 | chip_name = "navi14"; | |
1840 | break; | |
42b325e5 XY |
1841 | case CHIP_NAVI12: |
1842 | chip_name = "navi12"; | |
1843 | break; | |
4e52a9f8 HR |
1844 | case CHIP_VANGOGH: |
1845 | chip_name = "vangogh"; | |
1846 | break; | |
e2a75f88 AD |
1847 | } |
1848 | ||
1849 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1850 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1851 | if (err) { |
1852 | dev_err(adev->dev, | |
1853 | "Failed to load gpu_info firmware \"%s\"\n", | |
1854 | fw_name); | |
1855 | goto out; | |
1856 | } | |
ab4fe3e1 | 1857 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1858 | if (err) { |
1859 | dev_err(adev->dev, | |
1860 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1861 | fw_name); | |
1862 | goto out; | |
1863 | } | |
1864 | ||
ab4fe3e1 | 1865 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1866 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1867 | ||
1868 | switch (hdr->version_major) { | |
1869 | case 1: | |
1870 | { | |
1871 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1872 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1873 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1874 | ||
cc375d8c TY |
1875 | /* |
1876 | * Should be droped when DAL no longer needs it. | |
1877 | */ | |
1878 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
1879 | goto parse_soc_bounding_box; |
1880 | ||
b5ab16bf AD |
1881 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1882 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1883 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1884 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1885 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1886 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1887 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1888 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1889 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1890 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1891 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1892 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1893 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1894 | adev->gfx.cu_info.max_waves_per_simd = |
1895 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1896 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1897 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1898 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 1899 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
1900 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
1901 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
1902 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1903 | adev->gfx.config.num_sc_per_sh = | |
1904 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
1905 | adev->gfx.config.num_packer_per_sc = | |
1906 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
1907 | } | |
ec51d3fa XY |
1908 | |
1909 | parse_soc_bounding_box: | |
ec51d3fa XY |
1910 | /* |
1911 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 1912 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 1913 | */ |
48321c3d HW |
1914 | if (hdr->version_minor == 2) { |
1915 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
1916 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
1917 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
1918 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
1919 | } | |
e2a75f88 AD |
1920 | break; |
1921 | } | |
1922 | default: | |
1923 | dev_err(adev->dev, | |
1924 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1925 | err = -EINVAL; | |
1926 | goto out; | |
1927 | } | |
1928 | out: | |
e2a75f88 AD |
1929 | return err; |
1930 | } | |
1931 | ||
e3ecdffa AD |
1932 | /** |
1933 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1934 | * | |
1935 | * @adev: amdgpu_device pointer | |
1936 | * | |
1937 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1938 | * up each asic are discovered each IP's early_init callback is run. This | |
1939 | * is the first stage in initializing the asic. | |
1940 | * Returns 0 on success, negative error code on failure. | |
1941 | */ | |
06ec9070 | 1942 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1943 | { |
aaa36a97 | 1944 | int i, r; |
d38ceaf9 | 1945 | |
483ef985 | 1946 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1947 | |
00a979f3 | 1948 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 1949 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
1950 | if (r) |
1951 | return r; | |
00a979f3 WS |
1952 | } |
1953 | ||
d38ceaf9 | 1954 | switch (adev->asic_type) { |
33f34802 KW |
1955 | #ifdef CONFIG_DRM_AMDGPU_SI |
1956 | case CHIP_VERDE: | |
1957 | case CHIP_TAHITI: | |
1958 | case CHIP_PITCAIRN: | |
1959 | case CHIP_OLAND: | |
1960 | case CHIP_HAINAN: | |
295d0daf | 1961 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1962 | r = si_set_ip_blocks(adev); |
1963 | if (r) | |
1964 | return r; | |
1965 | break; | |
1966 | #endif | |
a2e73f56 AD |
1967 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1968 | case CHIP_BONAIRE: | |
1969 | case CHIP_HAWAII: | |
1970 | case CHIP_KAVERI: | |
1971 | case CHIP_KABINI: | |
1972 | case CHIP_MULLINS: | |
e1ad2d53 | 1973 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 1974 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
1975 | else |
1976 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
1977 | |
1978 | r = cik_set_ip_blocks(adev); | |
1979 | if (r) | |
1980 | return r; | |
1981 | break; | |
1982 | #endif | |
da87c30b AD |
1983 | case CHIP_TOPAZ: |
1984 | case CHIP_TONGA: | |
1985 | case CHIP_FIJI: | |
1986 | case CHIP_POLARIS10: | |
1987 | case CHIP_POLARIS11: | |
1988 | case CHIP_POLARIS12: | |
1989 | case CHIP_VEGAM: | |
1990 | case CHIP_CARRIZO: | |
1991 | case CHIP_STONEY: | |
1992 | if (adev->flags & AMD_IS_APU) | |
1993 | adev->family = AMDGPU_FAMILY_CZ; | |
1994 | else | |
1995 | adev->family = AMDGPU_FAMILY_VI; | |
1996 | ||
1997 | r = vi_set_ip_blocks(adev); | |
1998 | if (r) | |
1999 | return r; | |
2000 | break; | |
e48a3cd9 AD |
2001 | case CHIP_VEGA10: |
2002 | case CHIP_VEGA12: | |
e4bd8170 | 2003 | case CHIP_VEGA20: |
e48a3cd9 | 2004 | case CHIP_RAVEN: |
61cf44c1 | 2005 | case CHIP_ARCTURUS: |
b51a26a0 | 2006 | case CHIP_RENOIR: |
c00a18ec | 2007 | case CHIP_ALDEBARAN: |
70534d1e | 2008 | if (adev->flags & AMD_IS_APU) |
2ca8a5d2 CZ |
2009 | adev->family = AMDGPU_FAMILY_RV; |
2010 | else | |
2011 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
2012 | |
2013 | r = soc15_set_ip_blocks(adev); | |
2014 | if (r) | |
2015 | return r; | |
2016 | break; | |
0a5b8c7b | 2017 | case CHIP_NAVI10: |
7ecb5cd4 | 2018 | case CHIP_NAVI14: |
4808cf9c | 2019 | case CHIP_NAVI12: |
11e8aef5 | 2020 | case CHIP_SIENNA_CICHLID: |
41f446bf | 2021 | case CHIP_NAVY_FLOUNDER: |
144722fa | 2022 | case CHIP_DIMGREY_CAVEFISH: |
4e52a9f8 HR |
2023 | case CHIP_VANGOGH: |
2024 | if (adev->asic_type == CHIP_VANGOGH) | |
2025 | adev->family = AMDGPU_FAMILY_VGH; | |
2026 | else | |
2027 | adev->family = AMDGPU_FAMILY_NV; | |
0a5b8c7b HR |
2028 | |
2029 | r = nv_set_ip_blocks(adev); | |
2030 | if (r) | |
2031 | return r; | |
2032 | break; | |
d38ceaf9 AD |
2033 | default: |
2034 | /* FIXME: not supported yet */ | |
2035 | return -EINVAL; | |
2036 | } | |
2037 | ||
1884734a | 2038 | amdgpu_amdkfd_device_probe(adev); |
2039 | ||
3b94fb10 | 2040 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2041 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2042 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2043 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2044 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
00f54b97 | 2045 | |
d38ceaf9 AD |
2046 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2047 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
2048 | DRM_ERROR("disabled ip block: %d <%s>\n", |
2049 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 2050 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2051 | } else { |
a1255107 AD |
2052 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2053 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2054 | if (r == -ENOENT) { |
a1255107 | 2055 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2056 | } else if (r) { |
a1255107 AD |
2057 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2058 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2059 | return r; |
2c1a2784 | 2060 | } else { |
a1255107 | 2061 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2062 | } |
974e6b64 | 2063 | } else { |
a1255107 | 2064 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2065 | } |
d38ceaf9 | 2066 | } |
21a249ca AD |
2067 | /* get the vbios after the asic_funcs are set up */ |
2068 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2069 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2070 | if (r) | |
2071 | return r; | |
2072 | ||
21a249ca AD |
2073 | /* Read BIOS */ |
2074 | if (!amdgpu_get_bios(adev)) | |
2075 | return -EINVAL; | |
2076 | ||
2077 | r = amdgpu_atombios_init(adev); | |
2078 | if (r) { | |
2079 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2080 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2081 | return r; | |
2082 | } | |
77eabc6f PJZ |
2083 | |
2084 | /*get pf2vf msg info at it's earliest time*/ | |
2085 | if (amdgpu_sriov_vf(adev)) | |
2086 | amdgpu_virt_init_data_exchange(adev); | |
2087 | ||
21a249ca | 2088 | } |
d38ceaf9 AD |
2089 | } |
2090 | ||
395d1fb9 NH |
2091 | adev->cg_flags &= amdgpu_cg_mask; |
2092 | adev->pg_flags &= amdgpu_pg_mask; | |
2093 | ||
d38ceaf9 AD |
2094 | return 0; |
2095 | } | |
2096 | ||
0a4f2520 RZ |
2097 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2098 | { | |
2099 | int i, r; | |
2100 | ||
2101 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2102 | if (!adev->ip_blocks[i].status.sw) | |
2103 | continue; | |
2104 | if (adev->ip_blocks[i].status.hw) | |
2105 | continue; | |
2106 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2107 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2108 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2109 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2110 | if (r) { | |
2111 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2112 | adev->ip_blocks[i].version->funcs->name, r); | |
2113 | return r; | |
2114 | } | |
2115 | adev->ip_blocks[i].status.hw = true; | |
2116 | } | |
2117 | } | |
2118 | ||
2119 | return 0; | |
2120 | } | |
2121 | ||
2122 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2123 | { | |
2124 | int i, r; | |
2125 | ||
2126 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2127 | if (!adev->ip_blocks[i].status.sw) | |
2128 | continue; | |
2129 | if (adev->ip_blocks[i].status.hw) | |
2130 | continue; | |
2131 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2132 | if (r) { | |
2133 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2134 | adev->ip_blocks[i].version->funcs->name, r); | |
2135 | return r; | |
2136 | } | |
2137 | adev->ip_blocks[i].status.hw = true; | |
2138 | } | |
2139 | ||
2140 | return 0; | |
2141 | } | |
2142 | ||
7a3e0bb2 RZ |
2143 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2144 | { | |
2145 | int r = 0; | |
2146 | int i; | |
80f41f84 | 2147 | uint32_t smu_version; |
7a3e0bb2 RZ |
2148 | |
2149 | if (adev->asic_type >= CHIP_VEGA10) { | |
2150 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2151 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2152 | continue; | |
2153 | ||
e3c1b071 | 2154 | if (!adev->ip_blocks[i].status.sw) |
2155 | continue; | |
2156 | ||
482f0e53 ML |
2157 | /* no need to do the fw loading again if already done*/ |
2158 | if (adev->ip_blocks[i].status.hw == true) | |
2159 | break; | |
2160 | ||
53b3f8f4 | 2161 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2162 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2163 | if (r) { | |
2164 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2165 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2166 | return r; |
2167 | } | |
2168 | } else { | |
2169 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2170 | if (r) { | |
2171 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2172 | adev->ip_blocks[i].version->funcs->name, r); | |
2173 | return r; | |
7a3e0bb2 | 2174 | } |
7a3e0bb2 | 2175 | } |
482f0e53 ML |
2176 | |
2177 | adev->ip_blocks[i].status.hw = true; | |
2178 | break; | |
7a3e0bb2 RZ |
2179 | } |
2180 | } | |
482f0e53 | 2181 | |
8973d9ec ED |
2182 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2183 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2184 | |
80f41f84 | 2185 | return r; |
7a3e0bb2 RZ |
2186 | } |
2187 | ||
e3ecdffa AD |
2188 | /** |
2189 | * amdgpu_device_ip_init - run init for hardware IPs | |
2190 | * | |
2191 | * @adev: amdgpu_device pointer | |
2192 | * | |
2193 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2194 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2195 | * are run. sw_init initializes the software state associated with each IP | |
2196 | * and hw_init initializes the hardware associated with each IP. | |
2197 | * Returns 0 on success, negative error code on failure. | |
2198 | */ | |
06ec9070 | 2199 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2200 | { |
2201 | int i, r; | |
2202 | ||
c030f2e4 | 2203 | r = amdgpu_ras_init(adev); |
2204 | if (r) | |
2205 | return r; | |
2206 | ||
d38ceaf9 | 2207 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2208 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2209 | continue; |
a1255107 | 2210 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2211 | if (r) { |
a1255107 AD |
2212 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2213 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2214 | goto init_failed; |
2c1a2784 | 2215 | } |
a1255107 | 2216 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2217 | |
d38ceaf9 | 2218 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2219 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 2220 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2221 | if (r) { |
2222 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2223 | goto init_failed; |
2c1a2784 | 2224 | } |
a1255107 | 2225 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2226 | if (r) { |
2227 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2228 | goto init_failed; |
2c1a2784 | 2229 | } |
06ec9070 | 2230 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2231 | if (r) { |
06ec9070 | 2232 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2233 | goto init_failed; |
2c1a2784 | 2234 | } |
a1255107 | 2235 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2236 | |
2237 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2238 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2239 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2240 | AMDGPU_GEM_DOMAIN_VRAM, | |
2241 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2242 | if (r) { |
2243 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2244 | goto init_failed; |
2493664f ML |
2245 | } |
2246 | } | |
d38ceaf9 AD |
2247 | } |
2248 | } | |
2249 | ||
c9ffa427 YT |
2250 | if (amdgpu_sriov_vf(adev)) |
2251 | amdgpu_virt_init_data_exchange(adev); | |
2252 | ||
533aed27 AG |
2253 | r = amdgpu_ib_pool_init(adev); |
2254 | if (r) { | |
2255 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2256 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2257 | goto init_failed; | |
2258 | } | |
2259 | ||
c8963ea4 RZ |
2260 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2261 | if (r) | |
72d3f592 | 2262 | goto init_failed; |
0a4f2520 RZ |
2263 | |
2264 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
2265 | if (r) | |
72d3f592 | 2266 | goto init_failed; |
0a4f2520 | 2267 | |
7a3e0bb2 RZ |
2268 | r = amdgpu_device_fw_loading(adev); |
2269 | if (r) | |
72d3f592 | 2270 | goto init_failed; |
7a3e0bb2 | 2271 | |
0a4f2520 RZ |
2272 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2273 | if (r) | |
72d3f592 | 2274 | goto init_failed; |
d38ceaf9 | 2275 | |
121a2bc6 AG |
2276 | /* |
2277 | * retired pages will be loaded from eeprom and reserved here, | |
2278 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2279 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2280 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2281 | * |
2282 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2283 | * failure from bad gpu situation and stop amdgpu init process | |
2284 | * accordingly. For other failed cases, it will still release all | |
2285 | * the resource and print error message, rather than returning one | |
2286 | * negative value to upper level. | |
121a2bc6 AG |
2287 | * |
2288 | * Note: theoretically, this should be called before all vram allocations | |
2289 | * to protect retired page from abusing | |
2290 | */ | |
b82e65a9 GC |
2291 | r = amdgpu_ras_recovery_init(adev); |
2292 | if (r) | |
2293 | goto init_failed; | |
121a2bc6 | 2294 | |
3e2e2ab5 HZ |
2295 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2296 | amdgpu_xgmi_add_device(adev); | |
e3c1b071 | 2297 | |
2298 | /* Don't init kfd if whole hive need to be reset during init */ | |
2299 | if (!adev->gmc.xgmi.pending_reset) | |
2300 | amdgpu_amdkfd_device_init(adev); | |
c6332b97 | 2301 | |
bd607166 KR |
2302 | amdgpu_fru_get_product_info(adev); |
2303 | ||
72d3f592 | 2304 | init_failed: |
c9ffa427 | 2305 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2306 | amdgpu_virt_release_full_gpu(adev, true); |
2307 | ||
72d3f592 | 2308 | return r; |
d38ceaf9 AD |
2309 | } |
2310 | ||
e3ecdffa AD |
2311 | /** |
2312 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2313 | * | |
2314 | * @adev: amdgpu_device pointer | |
2315 | * | |
2316 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2317 | * this function before a GPU reset. If the value is retained after a | |
2318 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2319 | */ | |
06ec9070 | 2320 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2321 | { |
2322 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2323 | } | |
2324 | ||
e3ecdffa AD |
2325 | /** |
2326 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2327 | * | |
2328 | * @adev: amdgpu_device pointer | |
2329 | * | |
2330 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2331 | * The driver calls this after a GPU reset to see if the contents of | |
2332 | * VRAM is lost or now. | |
2333 | * returns true if vram is lost, false if not. | |
2334 | */ | |
06ec9070 | 2335 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2336 | { |
dadce777 EQ |
2337 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2338 | AMDGPU_RESET_MAGIC_NUM)) | |
2339 | return true; | |
2340 | ||
53b3f8f4 | 2341 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2342 | return false; |
2343 | ||
2344 | /* | |
2345 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2346 | * always assumed to be lost. | |
2347 | */ | |
2348 | switch (amdgpu_asic_reset_method(adev)) { | |
2349 | case AMD_RESET_METHOD_BACO: | |
2350 | case AMD_RESET_METHOD_MODE1: | |
2351 | return true; | |
2352 | default: | |
2353 | return false; | |
2354 | } | |
0c49e0b8 CZ |
2355 | } |
2356 | ||
e3ecdffa | 2357 | /** |
1112a46b | 2358 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2359 | * |
2360 | * @adev: amdgpu_device pointer | |
b8b72130 | 2361 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2362 | * |
e3ecdffa | 2363 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2364 | * set_clockgating_state callbacks are run. |
2365 | * Late initialization pass enabling clockgating for hardware IPs. | |
2366 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2367 | * Returns 0 on success, negative error code on failure. |
2368 | */ | |
fdd34271 | 2369 | |
5d89bb2d LL |
2370 | int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2371 | enum amd_clockgating_state state) | |
d38ceaf9 | 2372 | { |
1112a46b | 2373 | int i, j, r; |
d38ceaf9 | 2374 | |
4a2ba394 SL |
2375 | if (amdgpu_emu_mode == 1) |
2376 | return 0; | |
2377 | ||
1112a46b RZ |
2378 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2379 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2380 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2381 | continue; |
5d70a549 PV |
2382 | /* skip CG for GFX on S0ix */ |
2383 | if (adev->in_s0ix && | |
2384 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2385 | continue; | |
4a446d55 | 2386 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2387 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2388 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2389 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2390 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2391 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2392 | /* enable clockgating to save power */ |
a1255107 | 2393 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2394 | state); |
4a446d55 AD |
2395 | if (r) { |
2396 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2397 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2398 | return r; |
2399 | } | |
b0b00ff1 | 2400 | } |
d38ceaf9 | 2401 | } |
06b18f61 | 2402 | |
c9f96fd5 RZ |
2403 | return 0; |
2404 | } | |
2405 | ||
5d89bb2d LL |
2406 | int amdgpu_device_set_pg_state(struct amdgpu_device *adev, |
2407 | enum amd_powergating_state state) | |
c9f96fd5 | 2408 | { |
1112a46b | 2409 | int i, j, r; |
06b18f61 | 2410 | |
c9f96fd5 RZ |
2411 | if (amdgpu_emu_mode == 1) |
2412 | return 0; | |
2413 | ||
1112a46b RZ |
2414 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2415 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2416 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 | 2417 | continue; |
5d70a549 PV |
2418 | /* skip PG for GFX on S0ix */ |
2419 | if (adev->in_s0ix && | |
2420 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2421 | continue; | |
c9f96fd5 RZ |
2422 | /* skip CG for VCE/UVD, it's handled specially */ |
2423 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2424 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2425 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2426 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2427 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2428 | /* enable powergating to save power */ | |
2429 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2430 | state); |
c9f96fd5 RZ |
2431 | if (r) { |
2432 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2433 | adev->ip_blocks[i].version->funcs->name, r); | |
2434 | return r; | |
2435 | } | |
2436 | } | |
2437 | } | |
2dc80b00 S |
2438 | return 0; |
2439 | } | |
2440 | ||
beff74bc AD |
2441 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2442 | { | |
2443 | struct amdgpu_gpu_instance *gpu_ins; | |
2444 | struct amdgpu_device *adev; | |
2445 | int i, ret = 0; | |
2446 | ||
2447 | mutex_lock(&mgpu_info.mutex); | |
2448 | ||
2449 | /* | |
2450 | * MGPU fan boost feature should be enabled | |
2451 | * only when there are two or more dGPUs in | |
2452 | * the system | |
2453 | */ | |
2454 | if (mgpu_info.num_dgpu < 2) | |
2455 | goto out; | |
2456 | ||
2457 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2458 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2459 | adev = gpu_ins->adev; | |
2460 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2461 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2462 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2463 | if (ret) | |
2464 | break; | |
2465 | ||
2466 | gpu_ins->mgpu_fan_enabled = 1; | |
2467 | } | |
2468 | } | |
2469 | ||
2470 | out: | |
2471 | mutex_unlock(&mgpu_info.mutex); | |
2472 | ||
2473 | return ret; | |
2474 | } | |
2475 | ||
e3ecdffa AD |
2476 | /** |
2477 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2478 | * | |
2479 | * @adev: amdgpu_device pointer | |
2480 | * | |
2481 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2482 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2483 | * late_init covers any special initialization that an IP requires | |
2484 | * after all of the have been initialized or something that needs to happen | |
2485 | * late in the init process. | |
2486 | * Returns 0 on success, negative error code on failure. | |
2487 | */ | |
06ec9070 | 2488 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2489 | { |
60599a03 | 2490 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2491 | int i = 0, r; |
2492 | ||
2493 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2494 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2495 | continue; |
2496 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2497 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2498 | if (r) { | |
2499 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2500 | adev->ip_blocks[i].version->funcs->name, r); | |
2501 | return r; | |
2502 | } | |
2dc80b00 | 2503 | } |
73f847db | 2504 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2505 | } |
2506 | ||
a891d239 DL |
2507 | amdgpu_ras_set_error_query_ready(adev, true); |
2508 | ||
1112a46b RZ |
2509 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2510 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2511 | |
06ec9070 | 2512 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2513 | |
beff74bc AD |
2514 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2515 | if (r) | |
2516 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2517 | ||
2d02893f | 2518 | /* For XGMI + passthrough configuration on arcturus, enable light SBR */ |
2519 | if (adev->asic_type == CHIP_ARCTURUS && | |
2520 | amdgpu_passthrough(adev) && | |
2521 | adev->gmc.xgmi.num_physical_nodes > 1) | |
2522 | smu_set_light_sbr(&adev->smu, true); | |
60599a03 EQ |
2523 | |
2524 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2525 | mutex_lock(&mgpu_info.mutex); | |
2526 | ||
2527 | /* | |
2528 | * Reset device p-state to low as this was booted with high. | |
2529 | * | |
2530 | * This should be performed only after all devices from the same | |
2531 | * hive get initialized. | |
2532 | * | |
2533 | * However, it's unknown how many device in the hive in advance. | |
2534 | * As this is counted one by one during devices initializations. | |
2535 | * | |
2536 | * So, we wait for all XGMI interlinked devices initialized. | |
2537 | * This may bring some delays as those devices may come from | |
2538 | * different hives. But that should be OK. | |
2539 | */ | |
2540 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2541 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2542 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2543 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2544 | continue; | |
2545 | ||
d84a430d JK |
2546 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2547 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2548 | if (r) { |
2549 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2550 | break; | |
2551 | } | |
2552 | } | |
2553 | } | |
2554 | ||
2555 | mutex_unlock(&mgpu_info.mutex); | |
2556 | } | |
2557 | ||
d38ceaf9 AD |
2558 | return 0; |
2559 | } | |
2560 | ||
e3ecdffa AD |
2561 | /** |
2562 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2563 | * | |
2564 | * @adev: amdgpu_device pointer | |
2565 | * | |
2566 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2567 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2568 | * are run. hw_fini tears down the hardware associated with each IP | |
2569 | * and sw_fini tears down any software state associated with each IP. | |
2570 | * Returns 0 on success, negative error code on failure. | |
2571 | */ | |
06ec9070 | 2572 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
2573 | { |
2574 | int i, r; | |
2575 | ||
5278a159 SY |
2576 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) |
2577 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2578 | ||
c030f2e4 | 2579 | amdgpu_ras_pre_fini(adev); |
2580 | ||
a82400b5 AG |
2581 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2582 | amdgpu_xgmi_remove_device(adev); | |
2583 | ||
05df1f01 | 2584 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
2585 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2586 | ||
26eb6b51 DL |
2587 | amdgpu_amdkfd_device_fini(adev); |
2588 | ||
3e96dbfd AD |
2589 | /* need to disable SMC first */ |
2590 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2591 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 2592 | continue; |
fdd34271 | 2593 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 2594 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
2595 | /* XXX handle errors */ |
2596 | if (r) { | |
2597 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 2598 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 2599 | } |
a1255107 | 2600 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
2601 | break; |
2602 | } | |
2603 | } | |
2604 | ||
d38ceaf9 | 2605 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2606 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2607 | continue; |
8201a67a | 2608 | |
a1255107 | 2609 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2610 | /* XXX handle errors */ |
2c1a2784 | 2611 | if (r) { |
a1255107 AD |
2612 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2613 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2614 | } |
8201a67a | 2615 | |
a1255107 | 2616 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2617 | } |
2618 | ||
9950cda2 | 2619 | |
d38ceaf9 | 2620 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2621 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2622 | continue; |
c12aba3a ML |
2623 | |
2624 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2625 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2626 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2627 | amdgpu_device_wb_fini(adev); |
2628 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2629 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2630 | } |
2631 | ||
a1255107 | 2632 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2633 | /* XXX handle errors */ |
2c1a2784 | 2634 | if (r) { |
a1255107 AD |
2635 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2636 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2637 | } |
a1255107 AD |
2638 | adev->ip_blocks[i].status.sw = false; |
2639 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2640 | } |
2641 | ||
a6dcfd9c | 2642 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2643 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2644 | continue; |
a1255107 AD |
2645 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2646 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2647 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2648 | } |
2649 | ||
c030f2e4 | 2650 | amdgpu_ras_fini(adev); |
2651 | ||
030308fc | 2652 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
2653 | if (amdgpu_virt_release_full_gpu(adev, false)) |
2654 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 2655 | |
d38ceaf9 AD |
2656 | return 0; |
2657 | } | |
2658 | ||
e3ecdffa | 2659 | /** |
beff74bc | 2660 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2661 | * |
1112a46b | 2662 | * @work: work_struct. |
e3ecdffa | 2663 | */ |
beff74bc | 2664 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2665 | { |
2666 | struct amdgpu_device *adev = | |
beff74bc | 2667 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2668 | int r; |
2669 | ||
2670 | r = amdgpu_ib_ring_tests(adev); | |
2671 | if (r) | |
2672 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2673 | } |
2674 | ||
1e317b99 RZ |
2675 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2676 | { | |
2677 | struct amdgpu_device *adev = | |
2678 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2679 | ||
2680 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
2681 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
2682 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2683 | adev->gfx.gfx_off_state = true; | |
2684 | } | |
2685 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
2686 | } | |
2687 | ||
e3ecdffa | 2688 | /** |
e7854a03 | 2689 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2690 | * |
2691 | * @adev: amdgpu_device pointer | |
2692 | * | |
2693 | * Main suspend function for hardware IPs. The list of all the hardware | |
2694 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2695 | * suspend callbacks are run. suspend puts the hardware and software state | |
2696 | * in each IP into a state suitable for suspend. | |
2697 | * Returns 0 on success, negative error code on failure. | |
2698 | */ | |
e7854a03 AD |
2699 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2700 | { | |
2701 | int i, r; | |
2702 | ||
50ec83f0 AD |
2703 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2704 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2705 | |
e7854a03 AD |
2706 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2707 | if (!adev->ip_blocks[i].status.valid) | |
2708 | continue; | |
2b9f7848 | 2709 | |
e7854a03 | 2710 | /* displays are handled separately */ |
2b9f7848 ND |
2711 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2712 | continue; | |
2713 | ||
2714 | /* XXX handle errors */ | |
2715 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2716 | /* XXX handle errors */ | |
2717 | if (r) { | |
2718 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2719 | adev->ip_blocks[i].version->funcs->name, r); | |
2720 | return r; | |
e7854a03 | 2721 | } |
2b9f7848 ND |
2722 | |
2723 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2724 | } |
2725 | ||
e7854a03 AD |
2726 | return 0; |
2727 | } | |
2728 | ||
2729 | /** | |
2730 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2731 | * | |
2732 | * @adev: amdgpu_device pointer | |
2733 | * | |
2734 | * Main suspend function for hardware IPs. The list of all the hardware | |
2735 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2736 | * suspend callbacks are run. suspend puts the hardware and software state | |
2737 | * in each IP into a state suitable for suspend. | |
2738 | * Returns 0 on success, negative error code on failure. | |
2739 | */ | |
2740 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2741 | { |
2742 | int i, r; | |
2743 | ||
557f42a2 | 2744 | if (adev->in_s0ix) |
34416931 | 2745 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); |
34416931 | 2746 | |
d38ceaf9 | 2747 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2748 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2749 | continue; |
e7854a03 AD |
2750 | /* displays are handled in phase1 */ |
2751 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2752 | continue; | |
bff77e86 LM |
2753 | /* PSP lost connection when err_event_athub occurs */ |
2754 | if (amdgpu_ras_intr_triggered() && | |
2755 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2756 | adev->ip_blocks[i].status.hw = false; | |
2757 | continue; | |
2758 | } | |
e3c1b071 | 2759 | |
2760 | /* skip unnecessary suspend if we do not initialize them yet */ | |
2761 | if (adev->gmc.xgmi.pending_reset && | |
2762 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2763 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
2764 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2765 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
2766 | adev->ip_blocks[i].status.hw = false; | |
2767 | continue; | |
2768 | } | |
557f42a2 | 2769 | |
32ff160d AD |
2770 | /* skip suspend of gfx and psp for S0ix |
2771 | * gfx is in gfxoff state, so on resume it will exit gfxoff just | |
2772 | * like at runtime. PSP is also part of the always on hardware | |
2773 | * so no need to suspend it. | |
2774 | */ | |
557f42a2 | 2775 | if (adev->in_s0ix && |
32ff160d AD |
2776 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || |
2777 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)) | |
557f42a2 AD |
2778 | continue; |
2779 | ||
d38ceaf9 | 2780 | /* XXX handle errors */ |
a1255107 | 2781 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2782 | /* XXX handle errors */ |
2c1a2784 | 2783 | if (r) { |
a1255107 AD |
2784 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2785 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2786 | } |
876923fb | 2787 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 2788 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
2789 | if(!amdgpu_sriov_vf(adev)){ |
2790 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2791 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
2792 | if (r) { | |
2793 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2794 | adev->mp1_state, r); | |
2795 | return r; | |
2796 | } | |
a3a09142 AD |
2797 | } |
2798 | } | |
d38ceaf9 AD |
2799 | } |
2800 | ||
2801 | return 0; | |
2802 | } | |
2803 | ||
e7854a03 AD |
2804 | /** |
2805 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2806 | * | |
2807 | * @adev: amdgpu_device pointer | |
2808 | * | |
2809 | * Main suspend function for hardware IPs. The list of all the hardware | |
2810 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2811 | * suspend callbacks are run. suspend puts the hardware and software state | |
2812 | * in each IP into a state suitable for suspend. | |
2813 | * Returns 0 on success, negative error code on failure. | |
2814 | */ | |
2815 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2816 | { | |
2817 | int r; | |
2818 | ||
3c73683c JC |
2819 | if (amdgpu_sriov_vf(adev)) { |
2820 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 2821 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 2822 | } |
e7819644 | 2823 | |
e7854a03 AD |
2824 | r = amdgpu_device_ip_suspend_phase1(adev); |
2825 | if (r) | |
2826 | return r; | |
2827 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2828 | ||
e7819644 YT |
2829 | if (amdgpu_sriov_vf(adev)) |
2830 | amdgpu_virt_release_full_gpu(adev, false); | |
2831 | ||
e7854a03 AD |
2832 | return r; |
2833 | } | |
2834 | ||
06ec9070 | 2835 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2836 | { |
2837 | int i, r; | |
2838 | ||
2cb681b6 ML |
2839 | static enum amd_ip_block_type ip_order[] = { |
2840 | AMD_IP_BLOCK_TYPE_GMC, | |
2841 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2842 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2843 | AMD_IP_BLOCK_TYPE_IH, |
2844 | }; | |
a90ad3c2 | 2845 | |
2cb681b6 ML |
2846 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2847 | int j; | |
2848 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2849 | |
4cd2a96d J |
2850 | block = &adev->ip_blocks[i]; |
2851 | block->status.hw = false; | |
2cb681b6 | 2852 | |
4cd2a96d | 2853 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 2854 | |
4cd2a96d | 2855 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
2856 | !block->status.valid) |
2857 | continue; | |
2858 | ||
2859 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2860 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2861 | if (r) |
2862 | return r; | |
482f0e53 | 2863 | block->status.hw = true; |
a90ad3c2 ML |
2864 | } |
2865 | } | |
2866 | ||
2867 | return 0; | |
2868 | } | |
2869 | ||
06ec9070 | 2870 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2871 | { |
2872 | int i, r; | |
2873 | ||
2cb681b6 ML |
2874 | static enum amd_ip_block_type ip_order[] = { |
2875 | AMD_IP_BLOCK_TYPE_SMC, | |
2876 | AMD_IP_BLOCK_TYPE_DCE, | |
2877 | AMD_IP_BLOCK_TYPE_GFX, | |
2878 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 2879 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
2880 | AMD_IP_BLOCK_TYPE_VCE, |
2881 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 2882 | }; |
a90ad3c2 | 2883 | |
2cb681b6 ML |
2884 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2885 | int j; | |
2886 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2887 | |
2cb681b6 ML |
2888 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2889 | block = &adev->ip_blocks[j]; | |
2890 | ||
2891 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
2892 | !block->status.valid || |
2893 | block->status.hw) | |
2cb681b6 ML |
2894 | continue; |
2895 | ||
895bd048 JZ |
2896 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
2897 | r = block->version->funcs->resume(adev); | |
2898 | else | |
2899 | r = block->version->funcs->hw_init(adev); | |
2900 | ||
0aaeefcc | 2901 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2902 | if (r) |
2903 | return r; | |
482f0e53 | 2904 | block->status.hw = true; |
a90ad3c2 ML |
2905 | } |
2906 | } | |
2907 | ||
2908 | return 0; | |
2909 | } | |
2910 | ||
e3ecdffa AD |
2911 | /** |
2912 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2913 | * | |
2914 | * @adev: amdgpu_device pointer | |
2915 | * | |
2916 | * First resume function for hardware IPs. The list of all the hardware | |
2917 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2918 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2919 | * after a suspend and updates the software state as necessary. This | |
2920 | * function is also used for restoring the GPU after a GPU reset. | |
2921 | * Returns 0 on success, negative error code on failure. | |
2922 | */ | |
06ec9070 | 2923 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2924 | { |
2925 | int i, r; | |
2926 | ||
a90ad3c2 | 2927 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 2928 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 2929 | continue; |
a90ad3c2 | 2930 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2931 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2932 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 2933 | |
fcf0649f CZ |
2934 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2935 | if (r) { | |
2936 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2937 | adev->ip_blocks[i].version->funcs->name, r); | |
2938 | return r; | |
2939 | } | |
482f0e53 | 2940 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
2941 | } |
2942 | } | |
2943 | ||
2944 | return 0; | |
2945 | } | |
2946 | ||
e3ecdffa AD |
2947 | /** |
2948 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2949 | * | |
2950 | * @adev: amdgpu_device pointer | |
2951 | * | |
2952 | * First resume function for hardware IPs. The list of all the hardware | |
2953 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2954 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2955 | * functional state after a suspend and updates the software state as | |
2956 | * necessary. This function is also used for restoring the GPU after a GPU | |
2957 | * reset. | |
2958 | * Returns 0 on success, negative error code on failure. | |
2959 | */ | |
06ec9070 | 2960 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2961 | { |
2962 | int i, r; | |
2963 | ||
2964 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 2965 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2966 | continue; |
fcf0649f | 2967 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 2968 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
2969 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
2970 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 2971 | continue; |
a1255107 | 2972 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2973 | if (r) { |
a1255107 AD |
2974 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2975 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2976 | return r; |
2c1a2784 | 2977 | } |
482f0e53 | 2978 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
2979 | } |
2980 | ||
2981 | return 0; | |
2982 | } | |
2983 | ||
e3ecdffa AD |
2984 | /** |
2985 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2986 | * | |
2987 | * @adev: amdgpu_device pointer | |
2988 | * | |
2989 | * Main resume function for hardware IPs. The hardware IPs | |
2990 | * are split into two resume functions because they are | |
2991 | * are also used in in recovering from a GPU reset and some additional | |
2992 | * steps need to be take between them. In this case (S3/S4) they are | |
2993 | * run sequentially. | |
2994 | * Returns 0 on success, negative error code on failure. | |
2995 | */ | |
06ec9070 | 2996 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2997 | { |
2998 | int r; | |
2999 | ||
06ec9070 | 3000 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
3001 | if (r) |
3002 | return r; | |
7a3e0bb2 RZ |
3003 | |
3004 | r = amdgpu_device_fw_loading(adev); | |
3005 | if (r) | |
3006 | return r; | |
3007 | ||
06ec9070 | 3008 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
3009 | |
3010 | return r; | |
3011 | } | |
3012 | ||
e3ecdffa AD |
3013 | /** |
3014 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
3015 | * | |
3016 | * @adev: amdgpu_device pointer | |
3017 | * | |
3018 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
3019 | */ | |
4e99a44e | 3020 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 3021 | { |
6867e1b5 ML |
3022 | if (amdgpu_sriov_vf(adev)) { |
3023 | if (adev->is_atom_fw) { | |
3024 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
3025 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3026 | } else { | |
3027 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3028 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3029 | } | |
3030 | ||
3031 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3032 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3033 | } |
048765ad AR |
3034 | } |
3035 | ||
e3ecdffa AD |
3036 | /** |
3037 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3038 | * | |
3039 | * @asic_type: AMD asic type | |
3040 | * | |
3041 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3042 | * returns true if DC has support, false if not. | |
3043 | */ | |
4562236b HW |
3044 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3045 | { | |
3046 | switch (asic_type) { | |
3047 | #if defined(CONFIG_DRM_AMD_DC) | |
64200c46 MR |
3048 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3049 | case CHIP_TAHITI: | |
3050 | case CHIP_PITCAIRN: | |
3051 | case CHIP_VERDE: | |
3052 | case CHIP_OLAND: | |
3053 | #endif | |
4562236b | 3054 | case CHIP_BONAIRE: |
0d6fbccb | 3055 | case CHIP_KAVERI: |
367e6687 AD |
3056 | case CHIP_KABINI: |
3057 | case CHIP_MULLINS: | |
d9fda248 HW |
3058 | /* |
3059 | * We have systems in the wild with these ASICs that require | |
3060 | * LVDS and VGA support which is not supported with DC. | |
3061 | * | |
3062 | * Fallback to the non-DC driver here by default so as not to | |
3063 | * cause regressions. | |
3064 | */ | |
3065 | return amdgpu_dc > 0; | |
3066 | case CHIP_HAWAII: | |
4562236b HW |
3067 | case CHIP_CARRIZO: |
3068 | case CHIP_STONEY: | |
4562236b | 3069 | case CHIP_POLARIS10: |
675fd32b | 3070 | case CHIP_POLARIS11: |
2c8ad2d5 | 3071 | case CHIP_POLARIS12: |
675fd32b | 3072 | case CHIP_VEGAM: |
4562236b HW |
3073 | case CHIP_TONGA: |
3074 | case CHIP_FIJI: | |
42f8ffa1 | 3075 | case CHIP_VEGA10: |
dca7b401 | 3076 | case CHIP_VEGA12: |
c6034aa2 | 3077 | case CHIP_VEGA20: |
b86a1aa3 | 3078 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
fd187853 | 3079 | case CHIP_RAVEN: |
b4f199c7 | 3080 | case CHIP_NAVI10: |
8fceceb6 | 3081 | case CHIP_NAVI14: |
078655d9 | 3082 | case CHIP_NAVI12: |
e1c14c43 | 3083 | case CHIP_RENOIR: |
81d9bfb8 | 3084 | case CHIP_SIENNA_CICHLID: |
a6c5308f | 3085 | case CHIP_NAVY_FLOUNDER: |
7cc656e2 | 3086 | case CHIP_DIMGREY_CAVEFISH: |
84b934bc | 3087 | case CHIP_VANGOGH: |
42f8ffa1 | 3088 | #endif |
fd187853 | 3089 | return amdgpu_dc != 0; |
4562236b HW |
3090 | #endif |
3091 | default: | |
93b09a9a | 3092 | if (amdgpu_dc > 0) |
044a48f4 | 3093 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter " |
93b09a9a | 3094 | "but isn't supported by ASIC, ignoring\n"); |
4562236b HW |
3095 | return false; |
3096 | } | |
3097 | } | |
3098 | ||
3099 | /** | |
3100 | * amdgpu_device_has_dc_support - check if dc is supported | |
3101 | * | |
982a820b | 3102 | * @adev: amdgpu_device pointer |
4562236b HW |
3103 | * |
3104 | * Returns true for supported, false for not supported | |
3105 | */ | |
3106 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3107 | { | |
c997e8e2 | 3108 | if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display) |
2555039d XY |
3109 | return false; |
3110 | ||
4562236b HW |
3111 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3112 | } | |
3113 | ||
d4535e2c AG |
3114 | |
3115 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) | |
3116 | { | |
3117 | struct amdgpu_device *adev = | |
3118 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3119 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3120 | |
c6a6e2db AG |
3121 | /* It's a bug to not have a hive within this function */ |
3122 | if (WARN_ON(!hive)) | |
3123 | return; | |
3124 | ||
3125 | /* | |
3126 | * Use task barrier to synchronize all xgmi reset works across the | |
3127 | * hive. task_barrier_enter and task_barrier_exit will block | |
3128 | * until all the threads running the xgmi reset works reach | |
3129 | * those points. task_barrier_full will do both blocks. | |
3130 | */ | |
3131 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3132 | ||
3133 | task_barrier_enter(&hive->tb); | |
4a580877 | 3134 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3135 | |
3136 | if (adev->asic_reset_res) | |
3137 | goto fail; | |
3138 | ||
3139 | task_barrier_exit(&hive->tb); | |
4a580877 | 3140 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3141 | |
3142 | if (adev->asic_reset_res) | |
3143 | goto fail; | |
43c4d576 | 3144 | |
8bc7b360 HZ |
3145 | if (adev->mmhub.ras_funcs && |
3146 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
3147 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
c6a6e2db AG |
3148 | } else { |
3149 | ||
3150 | task_barrier_full(&hive->tb); | |
3151 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3152 | } | |
ce316fa5 | 3153 | |
c6a6e2db | 3154 | fail: |
d4535e2c | 3155 | if (adev->asic_reset_res) |
fed184e9 | 3156 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3157 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3158 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3159 | } |
3160 | ||
71f98027 AD |
3161 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3162 | { | |
3163 | char *input = amdgpu_lockup_timeout; | |
3164 | char *timeout_setting = NULL; | |
3165 | int index = 0; | |
3166 | long timeout; | |
3167 | int ret = 0; | |
3168 | ||
3169 | /* | |
3170 | * By default timeout for non compute jobs is 10000. | |
3171 | * And there is no timeout enforced on compute jobs. | |
3172 | * In SR-IOV or passthrough mode, timeout for compute | |
b7b2a316 | 3173 | * jobs are 60000 by default. |
71f98027 AD |
3174 | */ |
3175 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3176 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3177 | if (amdgpu_sriov_vf(adev)) |
3178 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3179 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
3180 | else if (amdgpu_passthrough(adev)) | |
b7b2a316 | 3181 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 AD |
3182 | else |
3183 | adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; | |
3184 | ||
f440ff44 | 3185 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3186 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3187 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3188 | ret = kstrtol(timeout_setting, 0, &timeout); |
3189 | if (ret) | |
3190 | return ret; | |
3191 | ||
3192 | if (timeout == 0) { | |
3193 | index++; | |
3194 | continue; | |
3195 | } else if (timeout < 0) { | |
3196 | timeout = MAX_SCHEDULE_TIMEOUT; | |
3197 | } else { | |
3198 | timeout = msecs_to_jiffies(timeout); | |
3199 | } | |
3200 | ||
3201 | switch (index++) { | |
3202 | case 0: | |
3203 | adev->gfx_timeout = timeout; | |
3204 | break; | |
3205 | case 1: | |
3206 | adev->compute_timeout = timeout; | |
3207 | break; | |
3208 | case 2: | |
3209 | adev->sdma_timeout = timeout; | |
3210 | break; | |
3211 | case 3: | |
3212 | adev->video_timeout = timeout; | |
3213 | break; | |
3214 | default: | |
3215 | break; | |
3216 | } | |
3217 | } | |
3218 | /* | |
3219 | * There is only one value specified and | |
3220 | * it should apply to all non-compute jobs. | |
3221 | */ | |
bcccee89 | 3222 | if (index == 1) { |
71f98027 | 3223 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3224 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3225 | adev->compute_timeout = adev->gfx_timeout; | |
3226 | } | |
71f98027 AD |
3227 | } |
3228 | ||
3229 | return ret; | |
3230 | } | |
d4535e2c | 3231 | |
77f3a5cd ND |
3232 | static const struct attribute *amdgpu_dev_attributes[] = { |
3233 | &dev_attr_product_name.attr, | |
3234 | &dev_attr_product_number.attr, | |
3235 | &dev_attr_serial_number.attr, | |
3236 | &dev_attr_pcie_replay_count.attr, | |
3237 | NULL | |
3238 | }; | |
3239 | ||
c9a6b82f | 3240 | |
d38ceaf9 AD |
3241 | /** |
3242 | * amdgpu_device_init - initialize the driver | |
3243 | * | |
3244 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3245 | * @flags: driver flags |
3246 | * | |
3247 | * Initializes the driver info and hw (all asics). | |
3248 | * Returns 0 for success or an error on failure. | |
3249 | * Called at driver startup. | |
3250 | */ | |
3251 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3252 | uint32_t flags) |
3253 | { | |
8aba21b7 LT |
3254 | struct drm_device *ddev = adev_to_drm(adev); |
3255 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3256 | int r, i; |
b98c6299 | 3257 | bool px = false; |
95844d20 | 3258 | u32 max_MBps; |
d38ceaf9 AD |
3259 | |
3260 | adev->shutdown = false; | |
d38ceaf9 | 3261 | adev->flags = flags; |
4e66d7d2 YZ |
3262 | |
3263 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3264 | adev->asic_type = amdgpu_force_asic_type; | |
3265 | else | |
3266 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3267 | ||
d38ceaf9 | 3268 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3269 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3270 | adev->usec_timeout *= 10; |
770d13b1 | 3271 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3272 | adev->accel_working = false; |
3273 | adev->num_rings = 0; | |
3274 | adev->mman.buffer_funcs = NULL; | |
3275 | adev->mman.buffer_funcs_ring = NULL; | |
3276 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3277 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3278 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 3279 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3280 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3281 | |
3282 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3283 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3284 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3285 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3286 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3287 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3288 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3289 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3290 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3291 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3292 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3293 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3294 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3295 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3296 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3297 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3298 | ||
3e39ab90 AD |
3299 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3300 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3301 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3302 | |
3303 | /* mutex initialization are all done here so we | |
3304 | * can recall function without having locking issues */ | |
0e5ca0d1 | 3305 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3306 | mutex_init(&adev->pm.mutex); |
3307 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3308 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3309 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3310 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3311 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3312 | mutex_init(&adev->mn_lock); |
e23b74aa | 3313 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3314 | hash_init(adev->mn_hash); |
53b3f8f4 | 3315 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 3316 | init_rwsem(&adev->reset_sem); |
32eaeae0 | 3317 | mutex_init(&adev->psp.mutex); |
bd052211 | 3318 | mutex_init(&adev->notifier_lock); |
d38ceaf9 | 3319 | |
912dfc84 EQ |
3320 | r = amdgpu_device_check_arguments(adev); |
3321 | if (r) | |
3322 | return r; | |
d38ceaf9 | 3323 | |
d38ceaf9 AD |
3324 | spin_lock_init(&adev->mmio_idx_lock); |
3325 | spin_lock_init(&adev->smc_idx_lock); | |
3326 | spin_lock_init(&adev->pcie_idx_lock); | |
3327 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3328 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3329 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3330 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3331 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3332 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3333 | |
0c4e7fa5 CZ |
3334 | INIT_LIST_HEAD(&adev->shadow_list); |
3335 | mutex_init(&adev->shadow_list_lock); | |
3336 | ||
655ce9cb | 3337 | INIT_LIST_HEAD(&adev->reset_list); |
3338 | ||
beff74bc AD |
3339 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3340 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3341 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3342 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3343 | |
d4535e2c AG |
3344 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3345 | ||
d23ee13f | 3346 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3347 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3348 | |
b265bdbd EQ |
3349 | atomic_set(&adev->throttling_logging_enabled, 1); |
3350 | /* | |
3351 | * If throttling continues, logging will be performed every minute | |
3352 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3353 | * throttling interrupt comes every second. Thus, the total logging | |
3354 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3355 | * for throttling interrupt) = 60 seconds. | |
3356 | */ | |
3357 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3358 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3359 | ||
0fa49558 AX |
3360 | /* Registers mapping */ |
3361 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3362 | if (adev->asic_type >= CHIP_BONAIRE) { |
3363 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3364 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3365 | } else { | |
3366 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3367 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3368 | } | |
d38ceaf9 | 3369 | |
d38ceaf9 AD |
3370 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3371 | if (adev->rmmio == NULL) { | |
3372 | return -ENOMEM; | |
3373 | } | |
3374 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3375 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3376 | ||
b2109d8e JX |
3377 | /* enable PCIE atomic ops */ |
3378 | r = pci_enable_atomic_ops_to_root(adev->pdev, | |
3379 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3380 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3381 | if (r) { | |
3382 | adev->have_atomics_support = false; | |
3383 | DRM_INFO("PCIE atomic ops is not supported\n"); | |
3384 | } else { | |
3385 | adev->have_atomics_support = true; | |
3386 | } | |
3387 | ||
5494d864 AD |
3388 | amdgpu_device_get_pcie_info(adev); |
3389 | ||
b239c017 JX |
3390 | if (amdgpu_mcbp) |
3391 | DRM_INFO("MCBP is enabled\n"); | |
3392 | ||
5f84cc63 JX |
3393 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
3394 | adev->enable_mes = true; | |
3395 | ||
3aa0115d ML |
3396 | /* detect hw virtualization here */ |
3397 | amdgpu_detect_virtualization(adev); | |
3398 | ||
dffa11b4 ML |
3399 | r = amdgpu_device_get_job_timeout_settings(adev); |
3400 | if (r) { | |
3401 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
4192f7b5 | 3402 | goto failed_unmap; |
a190d1c7 XY |
3403 | } |
3404 | ||
d38ceaf9 | 3405 | /* early init functions */ |
06ec9070 | 3406 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 3407 | if (r) |
4192f7b5 | 3408 | goto failed_unmap; |
d38ceaf9 | 3409 | |
6585661d OZ |
3410 | /* doorbell bar mapping and doorbell index init*/ |
3411 | amdgpu_device_doorbell_init(adev); | |
3412 | ||
9475a943 SL |
3413 | if (amdgpu_emu_mode == 1) { |
3414 | /* post the asic on emulation mode */ | |
3415 | emu_soc_asic_init(adev); | |
bfca0289 | 3416 | goto fence_driver_init; |
9475a943 | 3417 | } |
bfca0289 | 3418 | |
04442bf7 LL |
3419 | amdgpu_reset_init(adev); |
3420 | ||
4e99a44e ML |
3421 | /* detect if we are with an SRIOV vbios */ |
3422 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3423 | |
95e8e59e AD |
3424 | /* check if we need to reset the asic |
3425 | * E.g., driver was not cleanly unloaded previously, etc. | |
3426 | */ | |
f14899fd | 3427 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 3428 | if (adev->gmc.xgmi.num_physical_nodes) { |
3429 | dev_info(adev->dev, "Pending hive reset.\n"); | |
3430 | adev->gmc.xgmi.pending_reset = true; | |
3431 | /* Only need to init necessary block for SMU to handle the reset */ | |
3432 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3433 | if (!adev->ip_blocks[i].status.valid) | |
3434 | continue; | |
3435 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3436 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3437 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
3438 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 3439 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 3440 | adev->ip_blocks[i].version->funcs->name); |
3441 | adev->ip_blocks[i].status.hw = true; | |
3442 | } | |
3443 | } | |
3444 | } else { | |
3445 | r = amdgpu_asic_reset(adev); | |
3446 | if (r) { | |
3447 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3448 | goto failed; | |
3449 | } | |
95e8e59e AD |
3450 | } |
3451 | } | |
3452 | ||
8f66090b | 3453 | pci_enable_pcie_error_reporting(adev->pdev); |
c9a6b82f | 3454 | |
d38ceaf9 | 3455 | /* Post card if necessary */ |
39c640c0 | 3456 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3457 | if (!adev->bios) { |
bec86378 | 3458 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3459 | r = -EINVAL; |
3460 | goto failed; | |
d38ceaf9 | 3461 | } |
bec86378 | 3462 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3463 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3464 | if (r) { |
3465 | dev_err(adev->dev, "gpu post error!\n"); | |
3466 | goto failed; | |
3467 | } | |
d38ceaf9 AD |
3468 | } |
3469 | ||
88b64e95 AD |
3470 | if (adev->is_atom_fw) { |
3471 | /* Initialize clocks */ | |
3472 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3473 | if (r) { | |
3474 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3475 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3476 | goto failed; |
3477 | } | |
3478 | } else { | |
a5bde2f9 AD |
3479 | /* Initialize clocks */ |
3480 | r = amdgpu_atombios_get_clock_info(adev); | |
3481 | if (r) { | |
3482 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3483 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3484 | goto failed; |
a5bde2f9 AD |
3485 | } |
3486 | /* init i2c buses */ | |
4562236b HW |
3487 | if (!amdgpu_device_has_dc_support(adev)) |
3488 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3489 | } |
d38ceaf9 | 3490 | |
bfca0289 | 3491 | fence_driver_init: |
d38ceaf9 AD |
3492 | /* Fence driver */ |
3493 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
3494 | if (r) { |
3495 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 3496 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3497 | goto failed; |
2c1a2784 | 3498 | } |
d38ceaf9 AD |
3499 | |
3500 | /* init the mode config */ | |
4a580877 | 3501 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3502 | |
06ec9070 | 3503 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3504 | if (r) { |
8840a387 | 3505 | /* failed in exclusive mode due to timeout */ |
3506 | if (amdgpu_sriov_vf(adev) && | |
3507 | !amdgpu_sriov_runtime(adev) && | |
3508 | amdgpu_virt_mmio_blocked(adev) && | |
3509 | !amdgpu_virt_wait_reset(adev)) { | |
3510 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3511 | /* Don't send request since VF is inactive. */ |
3512 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3513 | adev->virt.ops = NULL; | |
8840a387 | 3514 | r = -EAGAIN; |
970fd197 | 3515 | goto release_ras_con; |
8840a387 | 3516 | } |
06ec9070 | 3517 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3518 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 3519 | goto release_ras_con; |
d38ceaf9 AD |
3520 | } |
3521 | ||
d69b8971 YZ |
3522 | dev_info(adev->dev, |
3523 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3524 | adev->gfx.config.max_shader_engines, |
3525 | adev->gfx.config.max_sh_per_se, | |
3526 | adev->gfx.config.max_cu_per_sh, | |
3527 | adev->gfx.cu_info.number); | |
3528 | ||
d38ceaf9 AD |
3529 | adev->accel_working = true; |
3530 | ||
e59c0205 AX |
3531 | amdgpu_vm_check_compute_bug(adev); |
3532 | ||
95844d20 MO |
3533 | /* Initialize the buffer migration limit. */ |
3534 | if (amdgpu_moverate >= 0) | |
3535 | max_MBps = amdgpu_moverate; | |
3536 | else | |
3537 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3538 | /* Get a log2 for easy divisions. */ | |
3539 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3540 | ||
9bc92b9c ML |
3541 | amdgpu_fbdev_init(adev); |
3542 | ||
d2f52ac8 | 3543 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3544 | if (r) { |
3545 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3546 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3547 | } else |
3548 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3549 | |
5bb23532 | 3550 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3551 | if (r) { |
3552 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3553 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3554 | } else |
3555 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3556 | |
d38ceaf9 AD |
3557 | if ((amdgpu_testing & 1)) { |
3558 | if (adev->accel_working) | |
3559 | amdgpu_test_moves(adev); | |
3560 | else | |
3561 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
3562 | } | |
d38ceaf9 AD |
3563 | if (amdgpu_benchmarking) { |
3564 | if (adev->accel_working) | |
3565 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
3566 | else | |
3567 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
3568 | } | |
3569 | ||
b0adca4d EQ |
3570 | /* |
3571 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3572 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3573 | * gpu instance is counted less. | |
3574 | */ | |
3575 | amdgpu_register_gpu_instance(adev); | |
3576 | ||
d38ceaf9 AD |
3577 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3578 | * explicit gating rather than handling it automatically. | |
3579 | */ | |
e3c1b071 | 3580 | if (!adev->gmc.xgmi.pending_reset) { |
3581 | r = amdgpu_device_ip_late_init(adev); | |
3582 | if (r) { | |
3583 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
3584 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 3585 | goto release_ras_con; |
e3c1b071 | 3586 | } |
3587 | /* must succeed. */ | |
3588 | amdgpu_ras_resume(adev); | |
3589 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
3590 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 3591 | } |
d38ceaf9 | 3592 | |
2c738637 ML |
3593 | if (amdgpu_sriov_vf(adev)) |
3594 | flush_delayed_work(&adev->delayed_init_work); | |
3595 | ||
77f3a5cd | 3596 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 3597 | if (r) |
77f3a5cd | 3598 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 3599 | |
d155bef0 AB |
3600 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3601 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3602 | if (r) |
3603 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3604 | ||
c1dd4aa6 AG |
3605 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
3606 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
3607 | pci_restore_state(pdev); | |
3608 | ||
8c3dd61c KHF |
3609 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3610 | /* this will fail for cards that aren't VGA class devices, just | |
3611 | * ignore it */ | |
3612 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) | |
3613 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); | |
3614 | ||
3615 | if (amdgpu_device_supports_px(ddev)) { | |
3616 | px = true; | |
3617 | vga_switcheroo_register_client(adev->pdev, | |
3618 | &amdgpu_switcheroo_ops, px); | |
3619 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
3620 | } | |
3621 | ||
e3c1b071 | 3622 | if (adev->gmc.xgmi.pending_reset) |
3623 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
3624 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3625 | ||
d38ceaf9 | 3626 | return 0; |
83ba126a | 3627 | |
970fd197 SY |
3628 | release_ras_con: |
3629 | amdgpu_release_ras_context(adev); | |
3630 | ||
83ba126a | 3631 | failed: |
89041940 | 3632 | amdgpu_vf_error_trans_all(adev); |
8840a387 | 3633 | |
4192f7b5 AD |
3634 | failed_unmap: |
3635 | iounmap(adev->rmmio); | |
3636 | adev->rmmio = NULL; | |
3637 | ||
83ba126a | 3638 | return r; |
d38ceaf9 AD |
3639 | } |
3640 | ||
d38ceaf9 AD |
3641 | /** |
3642 | * amdgpu_device_fini - tear down the driver | |
3643 | * | |
3644 | * @adev: amdgpu_device pointer | |
3645 | * | |
3646 | * Tear down the driver info (all asics). | |
3647 | * Called at driver shutdown. | |
3648 | */ | |
3649 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
3650 | { | |
aac89168 | 3651 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3652 | flush_delayed_work(&adev->delayed_init_work); |
bb0cd09b | 3653 | ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); |
d0d13fe8 | 3654 | adev->shutdown = true; |
9f875167 | 3655 | |
c1dd4aa6 AG |
3656 | kfree(adev->pci_state); |
3657 | ||
752c683d ML |
3658 | /* make sure IB test finished before entering exclusive mode |
3659 | * to avoid preemption on IB test | |
3660 | * */ | |
519b8b76 | 3661 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 3662 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
3663 | amdgpu_virt_fini_data_exchange(adev); |
3664 | } | |
752c683d | 3665 | |
e5b03032 ML |
3666 | /* disable all interrupts */ |
3667 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
3668 | if (adev->mode_info.mode_config_initialized){ |
3669 | if (!amdgpu_device_has_dc_support(adev)) | |
4a580877 | 3670 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3671 | else |
4a580877 | 3672 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3673 | } |
d38ceaf9 | 3674 | amdgpu_fence_driver_fini(adev); |
7c868b59 YT |
3675 | if (adev->pm_sysfs_en) |
3676 | amdgpu_pm_sysfs_fini(adev); | |
d38ceaf9 | 3677 | amdgpu_fbdev_fini(adev); |
e230ac11 | 3678 | amdgpu_device_ip_fini(adev); |
75e1658e ND |
3679 | release_firmware(adev->firmware.gpu_info_fw); |
3680 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 | 3681 | adev->accel_working = false; |
04442bf7 LL |
3682 | |
3683 | amdgpu_reset_fini(adev); | |
3684 | ||
d38ceaf9 | 3685 | /* free i2c buses */ |
4562236b HW |
3686 | if (!amdgpu_device_has_dc_support(adev)) |
3687 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3688 | |
3689 | if (amdgpu_emu_mode != 1) | |
3690 | amdgpu_atombios_fini(adev); | |
3691 | ||
d38ceaf9 AD |
3692 | kfree(adev->bios); |
3693 | adev->bios = NULL; | |
b98c6299 | 3694 | if (amdgpu_device_supports_px(adev_to_drm(adev))) { |
84c8b22e | 3695 | vga_switcheroo_unregister_client(adev->pdev); |
83ba126a | 3696 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
b98c6299 | 3697 | } |
38d6be81 AD |
3698 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
3699 | vga_client_register(adev->pdev, NULL, NULL, NULL); | |
d38ceaf9 AD |
3700 | iounmap(adev->rmmio); |
3701 | adev->rmmio = NULL; | |
06ec9070 | 3702 | amdgpu_device_doorbell_fini(adev); |
e9bc1bf7 | 3703 | |
7c868b59 YT |
3704 | if (adev->ucode_sysfs_en) |
3705 | amdgpu_ucode_sysfs_fini(adev); | |
77f3a5cd ND |
3706 | |
3707 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
d155bef0 AB |
3708 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3709 | amdgpu_pmu_fini(adev); | |
72de33f8 | 3710 | if (adev->mman.discovery_bin) |
a190d1c7 | 3711 | amdgpu_discovery_fini(adev); |
d38ceaf9 AD |
3712 | } |
3713 | ||
3714 | ||
3715 | /* | |
3716 | * Suspend & resume. | |
3717 | */ | |
3718 | /** | |
810ddc3a | 3719 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3720 | * |
87e3f136 | 3721 | * @dev: drm dev pointer |
87e3f136 | 3722 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
3723 | * |
3724 | * Puts the hw in the suspend state (all asics). | |
3725 | * Returns 0 for success or an error on failure. | |
3726 | * Called at driver suspend. | |
3727 | */ | |
de185019 | 3728 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 3729 | { |
a2e15b0e | 3730 | struct amdgpu_device *adev = drm_to_adev(dev); |
5ceb54c6 | 3731 | int r; |
d38ceaf9 | 3732 | |
d38ceaf9 AD |
3733 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
3734 | return 0; | |
3735 | ||
44779b43 | 3736 | adev->in_suspend = true; |
d38ceaf9 AD |
3737 | drm_kms_helper_poll_disable(dev); |
3738 | ||
5f818173 S |
3739 | if (fbcon) |
3740 | amdgpu_fbdev_set_suspend(adev, 1); | |
3741 | ||
beff74bc | 3742 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3743 | |
5e6932fe | 3744 | amdgpu_ras_suspend(adev); |
3745 | ||
fe1053b7 AD |
3746 | r = amdgpu_device_ip_suspend_phase1(adev); |
3747 | ||
5d3a2d95 AD |
3748 | if (!adev->in_s0ix) |
3749 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); | |
94fa5660 | 3750 | |
d38ceaf9 AD |
3751 | /* evict vram memory */ |
3752 | amdgpu_bo_evict_vram(adev); | |
3753 | ||
5ceb54c6 | 3754 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 3755 | |
34416931 | 3756 | r = amdgpu_device_ip_suspend_phase2(adev); |
a0a71e49 AD |
3757 | /* evict remaining vram memory |
3758 | * This second call to evict vram is to evict the gart page table | |
3759 | * using the CPU. | |
3760 | */ | |
d38ceaf9 AD |
3761 | amdgpu_bo_evict_vram(adev); |
3762 | ||
d38ceaf9 AD |
3763 | return 0; |
3764 | } | |
3765 | ||
3766 | /** | |
810ddc3a | 3767 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 3768 | * |
87e3f136 | 3769 | * @dev: drm dev pointer |
87e3f136 | 3770 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
3771 | * |
3772 | * Bring the hw back to operating state (all asics). | |
3773 | * Returns 0 for success or an error on failure. | |
3774 | * Called at driver resume. | |
3775 | */ | |
de185019 | 3776 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 3777 | { |
1348969a | 3778 | struct amdgpu_device *adev = drm_to_adev(dev); |
03161a6e | 3779 | int r = 0; |
d38ceaf9 AD |
3780 | |
3781 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
3782 | return 0; | |
3783 | ||
62498733 | 3784 | if (adev->in_s0ix) |
628c36d7 PL |
3785 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry); |
3786 | ||
d38ceaf9 | 3787 | /* post card */ |
39c640c0 | 3788 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 3789 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 3790 | if (r) |
aac89168 | 3791 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 3792 | } |
d38ceaf9 | 3793 | |
06ec9070 | 3794 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 3795 | if (r) { |
aac89168 | 3796 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 3797 | return r; |
e6707218 | 3798 | } |
5ceb54c6 AD |
3799 | amdgpu_fence_driver_resume(adev); |
3800 | ||
d38ceaf9 | 3801 | |
06ec9070 | 3802 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 3803 | if (r) |
4d3b9ae5 | 3804 | return r; |
d38ceaf9 | 3805 | |
beff74bc AD |
3806 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
3807 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3808 | ||
5d3a2d95 AD |
3809 | if (!adev->in_s0ix) { |
3810 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); | |
3811 | if (r) | |
3812 | return r; | |
3813 | } | |
756e6880 | 3814 | |
96a5d8d4 | 3815 | /* Make sure IB tests flushed */ |
beff74bc | 3816 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 3817 | |
a2e15b0e | 3818 | if (fbcon) |
4d3b9ae5 | 3819 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
3820 | |
3821 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 3822 | |
5e6932fe | 3823 | amdgpu_ras_resume(adev); |
3824 | ||
23a1a9e5 L |
3825 | /* |
3826 | * Most of the connector probing functions try to acquire runtime pm | |
3827 | * refs to ensure that the GPU is powered on when connector polling is | |
3828 | * performed. Since we're calling this from a runtime PM callback, | |
3829 | * trying to acquire rpm refs will cause us to deadlock. | |
3830 | * | |
3831 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
3832 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
3833 | */ | |
3834 | #ifdef CONFIG_PM | |
3835 | dev->dev->power.disable_depth++; | |
3836 | #endif | |
4562236b HW |
3837 | if (!amdgpu_device_has_dc_support(adev)) |
3838 | drm_helper_hpd_irq_event(dev); | |
3839 | else | |
3840 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
3841 | #ifdef CONFIG_PM |
3842 | dev->dev->power.disable_depth--; | |
3843 | #endif | |
44779b43 RZ |
3844 | adev->in_suspend = false; |
3845 | ||
4d3b9ae5 | 3846 | return 0; |
d38ceaf9 AD |
3847 | } |
3848 | ||
e3ecdffa AD |
3849 | /** |
3850 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
3851 | * | |
3852 | * @adev: amdgpu_device pointer | |
3853 | * | |
3854 | * The list of all the hardware IPs that make up the asic is walked and | |
3855 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
3856 | * if the asic is still hung or not. | |
3857 | * Returns true if any of the IPs are still in a hung state, false if not. | |
3858 | */ | |
06ec9070 | 3859 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
3860 | { |
3861 | int i; | |
3862 | bool asic_hang = false; | |
3863 | ||
f993d628 ML |
3864 | if (amdgpu_sriov_vf(adev)) |
3865 | return true; | |
3866 | ||
8bc04c29 AD |
3867 | if (amdgpu_asic_need_full_reset(adev)) |
3868 | return true; | |
3869 | ||
63fbf42f | 3870 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3871 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 3872 | continue; |
a1255107 AD |
3873 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
3874 | adev->ip_blocks[i].status.hang = | |
3875 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
3876 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 3877 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
3878 | asic_hang = true; |
3879 | } | |
3880 | } | |
3881 | return asic_hang; | |
3882 | } | |
3883 | ||
e3ecdffa AD |
3884 | /** |
3885 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
3886 | * | |
3887 | * @adev: amdgpu_device pointer | |
3888 | * | |
3889 | * The list of all the hardware IPs that make up the asic is walked and the | |
3890 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
3891 | * handles any IP specific hardware or software state changes that are | |
3892 | * necessary for a soft reset to succeed. | |
3893 | * Returns 0 on success, negative error code on failure. | |
3894 | */ | |
06ec9070 | 3895 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
3896 | { |
3897 | int i, r = 0; | |
3898 | ||
3899 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3900 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 3901 | continue; |
a1255107 AD |
3902 | if (adev->ip_blocks[i].status.hang && |
3903 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
3904 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
3905 | if (r) |
3906 | return r; | |
3907 | } | |
3908 | } | |
3909 | ||
3910 | return 0; | |
3911 | } | |
3912 | ||
e3ecdffa AD |
3913 | /** |
3914 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
3915 | * | |
3916 | * @adev: amdgpu_device pointer | |
3917 | * | |
3918 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
3919 | * reset is necessary to recover. | |
3920 | * Returns true if a full asic reset is required, false if not. | |
3921 | */ | |
06ec9070 | 3922 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 3923 | { |
da146d3b AD |
3924 | int i; |
3925 | ||
8bc04c29 AD |
3926 | if (amdgpu_asic_need_full_reset(adev)) |
3927 | return true; | |
3928 | ||
da146d3b | 3929 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3930 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 3931 | continue; |
a1255107 AD |
3932 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
3933 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
3934 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
3935 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
3936 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 3937 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 3938 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
3939 | return true; |
3940 | } | |
3941 | } | |
35d782fe CZ |
3942 | } |
3943 | return false; | |
3944 | } | |
3945 | ||
e3ecdffa AD |
3946 | /** |
3947 | * amdgpu_device_ip_soft_reset - do a soft reset | |
3948 | * | |
3949 | * @adev: amdgpu_device pointer | |
3950 | * | |
3951 | * The list of all the hardware IPs that make up the asic is walked and the | |
3952 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
3953 | * IP specific hardware or software state changes that are necessary to soft | |
3954 | * reset the IP. | |
3955 | * Returns 0 on success, negative error code on failure. | |
3956 | */ | |
06ec9070 | 3957 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3958 | { |
3959 | int i, r = 0; | |
3960 | ||
3961 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3962 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3963 | continue; |
a1255107 AD |
3964 | if (adev->ip_blocks[i].status.hang && |
3965 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
3966 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
3967 | if (r) |
3968 | return r; | |
3969 | } | |
3970 | } | |
3971 | ||
3972 | return 0; | |
3973 | } | |
3974 | ||
e3ecdffa AD |
3975 | /** |
3976 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
3977 | * | |
3978 | * @adev: amdgpu_device pointer | |
3979 | * | |
3980 | * The list of all the hardware IPs that make up the asic is walked and the | |
3981 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
3982 | * handles any IP specific hardware or software state changes that are | |
3983 | * necessary after the IP has been soft reset. | |
3984 | * Returns 0 on success, negative error code on failure. | |
3985 | */ | |
06ec9070 | 3986 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3987 | { |
3988 | int i, r = 0; | |
3989 | ||
3990 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3991 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3992 | continue; |
a1255107 AD |
3993 | if (adev->ip_blocks[i].status.hang && |
3994 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
3995 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
3996 | if (r) |
3997 | return r; | |
3998 | } | |
3999 | ||
4000 | return 0; | |
4001 | } | |
4002 | ||
e3ecdffa | 4003 | /** |
c33adbc7 | 4004 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4005 | * |
4006 | * @adev: amdgpu_device pointer | |
4007 | * | |
4008 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4009 | * restore things like GPUVM page tables after a GPU reset where | |
4010 | * the contents of VRAM might be lost. | |
403009bf CK |
4011 | * |
4012 | * Returns: | |
4013 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4014 | */ |
c33adbc7 | 4015 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4016 | { |
c41d1cf6 | 4017 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf CK |
4018 | struct amdgpu_bo *shadow; |
4019 | long r = 1, tmo; | |
c41d1cf6 ML |
4020 | |
4021 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4022 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4023 | else |
4024 | tmo = msecs_to_jiffies(100); | |
4025 | ||
aac89168 | 4026 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4027 | mutex_lock(&adev->shadow_list_lock); |
403009bf CK |
4028 | list_for_each_entry(shadow, &adev->shadow_list, shadow_list) { |
4029 | ||
4030 | /* No need to recover an evicted BO */ | |
4031 | if (shadow->tbo.mem.mem_type != TTM_PL_TT || | |
b575f10d | 4032 | shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET || |
403009bf CK |
4033 | shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM) |
4034 | continue; | |
4035 | ||
4036 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4037 | if (r) | |
4038 | break; | |
4039 | ||
c41d1cf6 | 4040 | if (fence) { |
1712fb1a | 4041 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4042 | dma_fence_put(fence); |
4043 | fence = next; | |
1712fb1a | 4044 | if (tmo == 0) { |
4045 | r = -ETIMEDOUT; | |
c41d1cf6 | 4046 | break; |
1712fb1a | 4047 | } else if (tmo < 0) { |
4048 | r = tmo; | |
4049 | break; | |
4050 | } | |
403009bf CK |
4051 | } else { |
4052 | fence = next; | |
c41d1cf6 | 4053 | } |
c41d1cf6 ML |
4054 | } |
4055 | mutex_unlock(&adev->shadow_list_lock); | |
4056 | ||
403009bf CK |
4057 | if (fence) |
4058 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4059 | dma_fence_put(fence); |
4060 | ||
1712fb1a | 4061 | if (r < 0 || tmo <= 0) { |
aac89168 | 4062 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4063 | return -EIO; |
4064 | } | |
c41d1cf6 | 4065 | |
aac89168 | 4066 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4067 | return 0; |
c41d1cf6 ML |
4068 | } |
4069 | ||
a90ad3c2 | 4070 | |
e3ecdffa | 4071 | /** |
06ec9070 | 4072 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4073 | * |
982a820b | 4074 | * @adev: amdgpu_device pointer |
87e3f136 | 4075 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4076 | * |
4077 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4078 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4079 | */ |
4080 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4081 | bool from_hypervisor) | |
5740682e ML |
4082 | { |
4083 | int r; | |
4084 | ||
4085 | if (from_hypervisor) | |
4086 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4087 | else | |
4088 | r = amdgpu_virt_reset_gpu(adev); | |
4089 | if (r) | |
4090 | return r; | |
a90ad3c2 | 4091 | |
b639c22c JZ |
4092 | amdgpu_amdkfd_pre_reset(adev); |
4093 | ||
a90ad3c2 | 4094 | /* Resume IP prior to SMC */ |
06ec9070 | 4095 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4096 | if (r) |
4097 | goto error; | |
a90ad3c2 | 4098 | |
c9ffa427 | 4099 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4100 | /* we need recover gart prior to run SMC/CP/SDMA resume */ |
6c28aed6 | 4101 | amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); |
a90ad3c2 | 4102 | |
7a3e0bb2 RZ |
4103 | r = amdgpu_device_fw_loading(adev); |
4104 | if (r) | |
4105 | return r; | |
4106 | ||
a90ad3c2 | 4107 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4108 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4109 | if (r) |
4110 | goto error; | |
a90ad3c2 ML |
4111 | |
4112 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 4113 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 4114 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 4115 | |
abc34253 | 4116 | error: |
c41d1cf6 | 4117 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 4118 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 4119 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 | 4120 | } |
437f3e0b | 4121 | amdgpu_virt_release_full_gpu(adev, true); |
a90ad3c2 ML |
4122 | |
4123 | return r; | |
4124 | } | |
4125 | ||
9a1cddd6 | 4126 | /** |
4127 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
4128 | * | |
982a820b | 4129 | * @adev: amdgpu_device pointer |
9a1cddd6 | 4130 | * |
4131 | * check if there is any job in mirror list | |
4132 | */ | |
4133 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
4134 | { | |
4135 | int i; | |
4136 | struct drm_sched_job *job; | |
4137 | ||
4138 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4139 | struct amdgpu_ring *ring = adev->rings[i]; | |
4140 | ||
4141 | if (!ring || !ring->sched.thread) | |
4142 | continue; | |
4143 | ||
4144 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
4145 | job = list_first_entry_or_null(&ring->sched.pending_list, |
4146 | struct drm_sched_job, list); | |
9a1cddd6 | 4147 | spin_unlock(&ring->sched.job_list_lock); |
4148 | if (job) | |
4149 | return true; | |
4150 | } | |
4151 | return false; | |
4152 | } | |
4153 | ||
12938fad CK |
4154 | /** |
4155 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
4156 | * | |
982a820b | 4157 | * @adev: amdgpu_device pointer |
12938fad CK |
4158 | * |
4159 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
4160 | * a hung GPU. | |
4161 | */ | |
4162 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
4163 | { | |
4164 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4165 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
4166 | return false; |
4167 | } | |
4168 | ||
3ba7b418 AG |
4169 | if (amdgpu_gpu_recovery == 0) |
4170 | goto disabled; | |
4171 | ||
4172 | if (amdgpu_sriov_vf(adev)) | |
4173 | return true; | |
4174 | ||
4175 | if (amdgpu_gpu_recovery == -1) { | |
4176 | switch (adev->asic_type) { | |
fc42d47c AG |
4177 | case CHIP_BONAIRE: |
4178 | case CHIP_HAWAII: | |
3ba7b418 AG |
4179 | case CHIP_TOPAZ: |
4180 | case CHIP_TONGA: | |
4181 | case CHIP_FIJI: | |
4182 | case CHIP_POLARIS10: | |
4183 | case CHIP_POLARIS11: | |
4184 | case CHIP_POLARIS12: | |
4185 | case CHIP_VEGAM: | |
4186 | case CHIP_VEGA20: | |
4187 | case CHIP_VEGA10: | |
4188 | case CHIP_VEGA12: | |
c43b849f | 4189 | case CHIP_RAVEN: |
e9d4cf91 | 4190 | case CHIP_ARCTURUS: |
2cb44fb0 | 4191 | case CHIP_RENOIR: |
658c6639 AD |
4192 | case CHIP_NAVI10: |
4193 | case CHIP_NAVI14: | |
4194 | case CHIP_NAVI12: | |
131a3c74 | 4195 | case CHIP_SIENNA_CICHLID: |
665fe4dc | 4196 | case CHIP_NAVY_FLOUNDER: |
27859ee3 | 4197 | case CHIP_DIMGREY_CAVEFISH: |
fe68ceef | 4198 | case CHIP_VANGOGH: |
ea4e96a7 | 4199 | case CHIP_ALDEBARAN: |
3ba7b418 AG |
4200 | break; |
4201 | default: | |
4202 | goto disabled; | |
4203 | } | |
12938fad CK |
4204 | } |
4205 | ||
4206 | return true; | |
3ba7b418 AG |
4207 | |
4208 | disabled: | |
aac89168 | 4209 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4210 | return false; |
12938fad CK |
4211 | } |
4212 | ||
5c03e584 FX |
4213 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
4214 | { | |
4215 | u32 i; | |
4216 | int ret = 0; | |
4217 | ||
4218 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
4219 | ||
4220 | dev_info(adev->dev, "GPU mode1 reset\n"); | |
4221 | ||
4222 | /* disable BM */ | |
4223 | pci_clear_master(adev->pdev); | |
4224 | ||
4225 | amdgpu_device_cache_pci_state(adev->pdev); | |
4226 | ||
4227 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
4228 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
4229 | ret = amdgpu_dpm_mode1_reset(adev); | |
4230 | } else { | |
4231 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
4232 | ret = psp_gpu_reset(adev); | |
4233 | } | |
4234 | ||
4235 | if (ret) | |
4236 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
4237 | ||
4238 | amdgpu_device_load_pci_state(adev->pdev); | |
4239 | ||
4240 | /* wait for asic to come out of reset */ | |
4241 | for (i = 0; i < adev->usec_timeout; i++) { | |
4242 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
4243 | ||
4244 | if (memsize != 0xffffffff) | |
4245 | break; | |
4246 | udelay(1); | |
4247 | } | |
4248 | ||
4249 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
4250 | return ret; | |
4251 | } | |
5c6dd71e | 4252 | |
e3c1b071 | 4253 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
04442bf7 | 4254 | struct amdgpu_reset_context *reset_context) |
26bc5340 AG |
4255 | { |
4256 | int i, r = 0; | |
04442bf7 LL |
4257 | struct amdgpu_job *job = NULL; |
4258 | bool need_full_reset = | |
4259 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4260 | ||
4261 | if (reset_context->reset_req_dev == adev) | |
4262 | job = reset_context->job; | |
71182665 | 4263 | |
e3c1b071 | 4264 | /* no need to dump if device is not in good state during probe period */ |
4265 | if (!adev->gmc.xgmi.pending_reset) | |
4266 | amdgpu_debugfs_wait_dump(adev); | |
728e7e0c | 4267 | |
b602ca5f TZ |
4268 | if (amdgpu_sriov_vf(adev)) { |
4269 | /* stop the data exchange thread */ | |
4270 | amdgpu_virt_fini_data_exchange(adev); | |
4271 | } | |
4272 | ||
71182665 | 4273 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4274 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4275 | struct amdgpu_ring *ring = adev->rings[i]; | |
4276 | ||
51687759 | 4277 | if (!ring || !ring->sched.thread) |
0875dc9e | 4278 | continue; |
5740682e | 4279 | |
2f9d4084 ML |
4280 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4281 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4282 | } |
d38ceaf9 | 4283 | |
222b5f04 AG |
4284 | if(job) |
4285 | drm_sched_increase_karma(&job->base); | |
4286 | ||
04442bf7 | 4287 | r = amdgpu_reset_prepare_hwcontext(adev, reset_context); |
404b277b LL |
4288 | /* If reset handler not implemented, continue; otherwise return */ |
4289 | if (r == -ENOSYS) | |
4290 | r = 0; | |
4291 | else | |
04442bf7 LL |
4292 | return r; |
4293 | ||
1d721ed6 | 4294 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4295 | if (!amdgpu_sriov_vf(adev)) { |
4296 | ||
4297 | if (!need_full_reset) | |
4298 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4299 | ||
4300 | if (!need_full_reset) { | |
4301 | amdgpu_device_ip_pre_soft_reset(adev); | |
4302 | r = amdgpu_device_ip_soft_reset(adev); | |
4303 | amdgpu_device_ip_post_soft_reset(adev); | |
4304 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4305 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4306 | need_full_reset = true; |
4307 | } | |
4308 | } | |
4309 | ||
4310 | if (need_full_reset) | |
4311 | r = amdgpu_device_ip_suspend(adev); | |
04442bf7 LL |
4312 | if (need_full_reset) |
4313 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4314 | else | |
4315 | clear_bit(AMDGPU_NEED_FULL_RESET, | |
4316 | &reset_context->flags); | |
26bc5340 AG |
4317 | } |
4318 | ||
4319 | return r; | |
4320 | } | |
4321 | ||
04442bf7 LL |
4322 | int amdgpu_do_asic_reset(struct list_head *device_list_handle, |
4323 | struct amdgpu_reset_context *reset_context) | |
26bc5340 AG |
4324 | { |
4325 | struct amdgpu_device *tmp_adev = NULL; | |
04442bf7 | 4326 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
26bc5340 AG |
4327 | int r = 0; |
4328 | ||
04442bf7 LL |
4329 | /* Try reset handler method first */ |
4330 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
4331 | reset_list); | |
4332 | r = amdgpu_reset_perform_reset(tmp_adev, reset_context); | |
404b277b LL |
4333 | /* If reset handler not implemented, continue; otherwise return */ |
4334 | if (r == -ENOSYS) | |
4335 | r = 0; | |
4336 | else | |
04442bf7 LL |
4337 | return r; |
4338 | ||
4339 | /* Reset handler not implemented, use the default method */ | |
4340 | need_full_reset = | |
4341 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4342 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); | |
4343 | ||
26bc5340 | 4344 | /* |
655ce9cb | 4345 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
4346 | * to allow proper links negotiation in FW (within 1 sec) |
4347 | */ | |
7ac71382 | 4348 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 4349 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 4350 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4351 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 4352 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 4353 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4354 | r = -EALREADY; |
4355 | } else | |
4356 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4357 | |
041a62bc | 4358 | if (r) { |
aac89168 | 4359 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4360 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4361 | break; |
ce316fa5 LM |
4362 | } |
4363 | } | |
4364 | ||
041a62bc AG |
4365 | /* For XGMI wait for all resets to complete before proceed */ |
4366 | if (!r) { | |
655ce9cb | 4367 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
4368 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
4369 | flush_work(&tmp_adev->xgmi_reset_work); | |
4370 | r = tmp_adev->asic_reset_res; | |
4371 | if (r) | |
4372 | break; | |
ce316fa5 LM |
4373 | } |
4374 | } | |
4375 | } | |
ce316fa5 | 4376 | } |
26bc5340 | 4377 | |
43c4d576 | 4378 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 4379 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8bc7b360 HZ |
4380 | if (tmp_adev->mmhub.ras_funcs && |
4381 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count) | |
4382 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count(tmp_adev); | |
43c4d576 JC |
4383 | } |
4384 | ||
00eaa571 | 4385 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4386 | } |
00eaa571 | 4387 | |
655ce9cb | 4388 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
4389 | if (need_full_reset) { |
4390 | /* post card */ | |
e3c1b071 | 4391 | r = amdgpu_device_asic_init(tmp_adev); |
4392 | if (r) { | |
aac89168 | 4393 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 4394 | } else { |
26bc5340 AG |
4395 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
4396 | r = amdgpu_device_ip_resume_phase1(tmp_adev); | |
4397 | if (r) | |
4398 | goto out; | |
4399 | ||
4400 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
4401 | if (vram_lost) { | |
77e7f829 | 4402 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4403 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4404 | } |
4405 | ||
6c28aed6 | 4406 | r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT)); |
26bc5340 AG |
4407 | if (r) |
4408 | goto out; | |
4409 | ||
4410 | r = amdgpu_device_fw_loading(tmp_adev); | |
4411 | if (r) | |
4412 | return r; | |
4413 | ||
4414 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4415 | if (r) | |
4416 | goto out; | |
4417 | ||
4418 | if (vram_lost) | |
4419 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4420 | ||
fdafb359 EQ |
4421 | /* |
4422 | * Add this ASIC as tracked as reset was already | |
4423 | * complete successfully. | |
4424 | */ | |
4425 | amdgpu_register_gpu_instance(tmp_adev); | |
4426 | ||
04442bf7 LL |
4427 | if (!reset_context->hive && |
4428 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
e3c1b071 | 4429 | amdgpu_xgmi_add_device(tmp_adev); |
4430 | ||
7c04ca50 | 4431 | r = amdgpu_device_ip_late_init(tmp_adev); |
4432 | if (r) | |
4433 | goto out; | |
4434 | ||
565d1941 EQ |
4435 | amdgpu_fbdev_set_suspend(tmp_adev, 0); |
4436 | ||
e8fbaf03 GC |
4437 | /* |
4438 | * The GPU enters bad state once faulty pages | |
4439 | * by ECC has reached the threshold, and ras | |
4440 | * recovery is scheduled next. So add one check | |
4441 | * here to break recovery if it indeed exceeds | |
4442 | * bad page threshold, and remind user to | |
4443 | * retire this GPU or setting one bigger | |
4444 | * bad_page_threshold value to fix this once | |
4445 | * probing driver again. | |
4446 | */ | |
11003c68 | 4447 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
4448 | /* must succeed. */ |
4449 | amdgpu_ras_resume(tmp_adev); | |
4450 | } else { | |
4451 | r = -EINVAL; | |
4452 | goto out; | |
4453 | } | |
e79a04d5 | 4454 | |
26bc5340 | 4455 | /* Update PSP FW topology after reset */ |
04442bf7 LL |
4456 | if (reset_context->hive && |
4457 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4458 | r = amdgpu_xgmi_update_topology( | |
4459 | reset_context->hive, tmp_adev); | |
26bc5340 AG |
4460 | } |
4461 | } | |
4462 | ||
26bc5340 AG |
4463 | out: |
4464 | if (!r) { | |
4465 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4466 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4467 | if (r) { | |
4468 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
4469 | r = amdgpu_device_ip_suspend(tmp_adev); | |
4470 | need_full_reset = true; | |
4471 | r = -EAGAIN; | |
4472 | goto end; | |
4473 | } | |
4474 | } | |
4475 | ||
4476 | if (!r) | |
4477 | r = amdgpu_device_recover_vram(tmp_adev); | |
4478 | else | |
4479 | tmp_adev->asic_reset_res = r; | |
4480 | } | |
4481 | ||
4482 | end: | |
04442bf7 LL |
4483 | if (need_full_reset) |
4484 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4485 | else | |
4486 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 AG |
4487 | return r; |
4488 | } | |
4489 | ||
08ebb485 DL |
4490 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, |
4491 | struct amdgpu_hive_info *hive) | |
26bc5340 | 4492 | { |
53b3f8f4 DL |
4493 | if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0) |
4494 | return false; | |
4495 | ||
08ebb485 DL |
4496 | if (hive) { |
4497 | down_write_nest_lock(&adev->reset_sem, &hive->hive_lock); | |
4498 | } else { | |
4499 | down_write(&adev->reset_sem); | |
4500 | } | |
5740682e | 4501 | |
a3a09142 AD |
4502 | switch (amdgpu_asic_reset_method(adev)) { |
4503 | case AMD_RESET_METHOD_MODE1: | |
4504 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4505 | break; | |
4506 | case AMD_RESET_METHOD_MODE2: | |
4507 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4508 | break; | |
4509 | default: | |
4510 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4511 | break; | |
4512 | } | |
1d721ed6 AG |
4513 | |
4514 | return true; | |
26bc5340 | 4515 | } |
d38ceaf9 | 4516 | |
26bc5340 AG |
4517 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
4518 | { | |
89041940 | 4519 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4520 | adev->mp1_state = PP_MP1_STATE_NONE; |
53b3f8f4 | 4521 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 4522 | up_write(&adev->reset_sem); |
26bc5340 AG |
4523 | } |
4524 | ||
91fb309d HC |
4525 | /* |
4526 | * to lockup a list of amdgpu devices in a hive safely, if not a hive | |
4527 | * with multiple nodes, it will be similar as amdgpu_device_lock_adev. | |
4528 | * | |
4529 | * unlock won't require roll back. | |
4530 | */ | |
4531 | static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive) | |
4532 | { | |
4533 | struct amdgpu_device *tmp_adev = NULL; | |
4534 | ||
4535 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
4536 | if (!hive) { | |
4537 | dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes"); | |
4538 | return -ENODEV; | |
4539 | } | |
4540 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4541 | if (!amdgpu_device_lock_adev(tmp_adev, hive)) | |
4542 | goto roll_back; | |
4543 | } | |
4544 | } else if (!amdgpu_device_lock_adev(adev, hive)) | |
4545 | return -EAGAIN; | |
4546 | ||
4547 | return 0; | |
4548 | roll_back: | |
4549 | if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) { | |
4550 | /* | |
4551 | * if the lockup iteration break in the middle of a hive, | |
4552 | * it may means there may has a race issue, | |
4553 | * or a hive device locked up independently. | |
4554 | * we may be in trouble and may not, so will try to roll back | |
4555 | * the lock and give out a warnning. | |
4556 | */ | |
4557 | dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock"); | |
4558 | list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4559 | amdgpu_device_unlock_adev(tmp_adev); | |
4560 | } | |
4561 | } | |
4562 | return -EAGAIN; | |
4563 | } | |
4564 | ||
3f12acc8 EQ |
4565 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4566 | { | |
4567 | struct pci_dev *p = NULL; | |
4568 | ||
4569 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4570 | adev->pdev->bus->number, 1); | |
4571 | if (p) { | |
4572 | pm_runtime_enable(&(p->dev)); | |
4573 | pm_runtime_resume(&(p->dev)); | |
4574 | } | |
4575 | } | |
4576 | ||
4577 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4578 | { | |
4579 | enum amd_reset_method reset_method; | |
4580 | struct pci_dev *p = NULL; | |
4581 | u64 expires; | |
4582 | ||
4583 | /* | |
4584 | * For now, only BACO and mode1 reset are confirmed | |
4585 | * to suffer the audio issue without proper suspended. | |
4586 | */ | |
4587 | reset_method = amdgpu_asic_reset_method(adev); | |
4588 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4589 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4590 | return -EINVAL; | |
4591 | ||
4592 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4593 | adev->pdev->bus->number, 1); | |
4594 | if (!p) | |
4595 | return -ENODEV; | |
4596 | ||
4597 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4598 | if (!expires) | |
4599 | /* | |
4600 | * If we cannot get the audio device autosuspend delay, | |
4601 | * a fixed 4S interval will be used. Considering 3S is | |
4602 | * the audio controller default autosuspend delay setting. | |
4603 | * 4S used here is guaranteed to cover that. | |
4604 | */ | |
54b7feb9 | 4605 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4606 | |
4607 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4608 | if (!pm_runtime_suspend(&(p->dev))) | |
4609 | break; | |
4610 | ||
4611 | if (expires < ktime_get_mono_fast_ns()) { | |
4612 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4613 | /* TODO: abort the succeeding gpu reset? */ | |
4614 | return -ETIMEDOUT; | |
4615 | } | |
4616 | } | |
4617 | ||
4618 | pm_runtime_disable(&(p->dev)); | |
4619 | ||
4620 | return 0; | |
4621 | } | |
4622 | ||
04442bf7 LL |
4623 | void amdgpu_device_recheck_guilty_jobs( |
4624 | struct amdgpu_device *adev, struct list_head *device_list_handle, | |
4625 | struct amdgpu_reset_context *reset_context) | |
e6c6338f JZ |
4626 | { |
4627 | int i, r = 0; | |
4628 | ||
4629 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4630 | struct amdgpu_ring *ring = adev->rings[i]; | |
4631 | int ret = 0; | |
4632 | struct drm_sched_job *s_job; | |
4633 | ||
4634 | if (!ring || !ring->sched.thread) | |
4635 | continue; | |
4636 | ||
4637 | s_job = list_first_entry_or_null(&ring->sched.pending_list, | |
4638 | struct drm_sched_job, list); | |
4639 | if (s_job == NULL) | |
4640 | continue; | |
4641 | ||
4642 | /* clear job's guilty and depend the folowing step to decide the real one */ | |
4643 | drm_sched_reset_karma(s_job); | |
4644 | drm_sched_resubmit_jobs_ext(&ring->sched, 1); | |
4645 | ||
4646 | ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout); | |
4647 | if (ret == 0) { /* timeout */ | |
4648 | DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n", | |
4649 | ring->sched.name, s_job->id); | |
4650 | ||
4651 | /* set guilty */ | |
4652 | drm_sched_increase_karma(s_job); | |
4653 | retry: | |
4654 | /* do hw reset */ | |
4655 | if (amdgpu_sriov_vf(adev)) { | |
4656 | amdgpu_virt_fini_data_exchange(adev); | |
4657 | r = amdgpu_device_reset_sriov(adev, false); | |
4658 | if (r) | |
4659 | adev->asic_reset_res = r; | |
4660 | } else { | |
04442bf7 LL |
4661 | clear_bit(AMDGPU_SKIP_HW_RESET, |
4662 | &reset_context->flags); | |
4663 | r = amdgpu_do_asic_reset(device_list_handle, | |
4664 | reset_context); | |
e6c6338f JZ |
4665 | if (r && r == -EAGAIN) |
4666 | goto retry; | |
4667 | } | |
4668 | ||
4669 | /* | |
4670 | * add reset counter so that the following | |
4671 | * resubmitted job could flush vmid | |
4672 | */ | |
4673 | atomic_inc(&adev->gpu_reset_counter); | |
4674 | continue; | |
4675 | } | |
4676 | ||
4677 | /* got the hw fence, signal finished fence */ | |
4678 | atomic_dec(ring->sched.score); | |
4679 | dma_fence_get(&s_job->s_fence->finished); | |
4680 | dma_fence_signal(&s_job->s_fence->finished); | |
4681 | dma_fence_put(&s_job->s_fence->finished); | |
4682 | ||
4683 | /* remove node from list and free the job */ | |
4684 | spin_lock(&ring->sched.job_list_lock); | |
4685 | list_del_init(&s_job->list); | |
4686 | spin_unlock(&ring->sched.job_list_lock); | |
4687 | ring->sched.ops->free_job(s_job); | |
4688 | } | |
4689 | } | |
4690 | ||
26bc5340 AG |
4691 | /** |
4692 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
4693 | * | |
982a820b | 4694 | * @adev: amdgpu_device pointer |
26bc5340 AG |
4695 | * @job: which job trigger hang |
4696 | * | |
4697 | * Attempt to reset the GPU if it has hung (all asics). | |
4698 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
4699 | * Returns 0 for success or an error on failure. | |
4700 | */ | |
4701 | ||
4702 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
4703 | struct amdgpu_job *job) | |
4704 | { | |
1d721ed6 | 4705 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 | 4706 | bool job_signaled = false; |
26bc5340 | 4707 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 4708 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 4709 | int i, r = 0; |
bb5c7235 | 4710 | bool need_emergency_restart = false; |
3f12acc8 | 4711 | bool audio_suspended = false; |
e6c6338f | 4712 | int tmp_vram_lost_counter; |
04442bf7 LL |
4713 | struct amdgpu_reset_context reset_context; |
4714 | ||
4715 | memset(&reset_context, 0, sizeof(reset_context)); | |
26bc5340 | 4716 | |
6e3cd2a9 | 4717 | /* |
bb5c7235 WS |
4718 | * Special case: RAS triggered and full reset isn't supported |
4719 | */ | |
4720 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
4721 | ||
d5ea093e AG |
4722 | /* |
4723 | * Flush RAM to disk so that after reboot | |
4724 | * the user can read log and see why the system rebooted. | |
4725 | */ | |
bb5c7235 | 4726 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
4727 | DRM_WARN("Emergency reboot."); |
4728 | ||
4729 | ksys_sync_helper(); | |
4730 | emergency_restart(); | |
4731 | } | |
4732 | ||
b823821f | 4733 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 4734 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 AG |
4735 | |
4736 | /* | |
1d721ed6 AG |
4737 | * Here we trylock to avoid chain of resets executing from |
4738 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
4739 | * different schedulers for same device while this TO handler is running. | |
4740 | * We always reset all schedulers for device and all devices for XGMI | |
4741 | * hive so that should take care of them too. | |
26bc5340 | 4742 | */ |
d95e8e97 | 4743 | hive = amdgpu_get_xgmi_hive(adev); |
53b3f8f4 DL |
4744 | if (hive) { |
4745 | if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) { | |
4746 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
4747 | job ? job->base.id : -1, hive->hive_id); | |
d95e8e97 | 4748 | amdgpu_put_xgmi_hive(hive); |
91fb309d HC |
4749 | if (job) |
4750 | drm_sched_increase_karma(&job->base); | |
53b3f8f4 DL |
4751 | return 0; |
4752 | } | |
4753 | mutex_lock(&hive->hive_lock); | |
1d721ed6 | 4754 | } |
26bc5340 | 4755 | |
04442bf7 LL |
4756 | reset_context.method = AMD_RESET_METHOD_NONE; |
4757 | reset_context.reset_req_dev = adev; | |
4758 | reset_context.job = job; | |
4759 | reset_context.hive = hive; | |
4760 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
4761 | ||
91fb309d HC |
4762 | /* |
4763 | * lock the device before we try to operate the linked list | |
4764 | * if didn't get the device lock, don't touch the linked list since | |
4765 | * others may iterating it. | |
4766 | */ | |
4767 | r = amdgpu_device_lock_hive_adev(adev, hive); | |
4768 | if (r) { | |
4769 | dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress", | |
4770 | job ? job->base.id : -1); | |
4771 | ||
4772 | /* even we skipped this reset, still need to set the job to guilty */ | |
4773 | if (job) | |
4774 | drm_sched_increase_karma(&job->base); | |
4775 | goto skip_recovery; | |
4776 | } | |
4777 | ||
9e94d22c EQ |
4778 | /* |
4779 | * Build list of devices to reset. | |
4780 | * In case we are in XGMI hive mode, resort the device list | |
4781 | * to put adev in the 1st position. | |
4782 | */ | |
4783 | INIT_LIST_HEAD(&device_list); | |
4784 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
655ce9cb | 4785 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) |
4786 | list_add_tail(&tmp_adev->reset_list, &device_list); | |
4787 | if (!list_is_first(&adev->reset_list, &device_list)) | |
4788 | list_rotate_to_front(&adev->reset_list, &device_list); | |
4789 | device_list_handle = &device_list; | |
26bc5340 | 4790 | } else { |
655ce9cb | 4791 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
4792 | device_list_handle = &device_list; |
4793 | } | |
4794 | ||
1d721ed6 | 4795 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 4796 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
3f12acc8 EQ |
4797 | /* |
4798 | * Try to put the audio codec into suspend state | |
4799 | * before gpu reset started. | |
4800 | * | |
4801 | * Due to the power domain of the graphics device | |
4802 | * is shared with AZ power domain. Without this, | |
4803 | * we may change the audio hardware from behind | |
4804 | * the audio driver's back. That will trigger | |
4805 | * some audio codec errors. | |
4806 | */ | |
4807 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
4808 | audio_suspended = true; | |
4809 | ||
9e94d22c EQ |
4810 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
4811 | ||
52fb44cf EQ |
4812 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
4813 | ||
9e94d22c EQ |
4814 | if (!amdgpu_sriov_vf(tmp_adev)) |
4815 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
4816 | ||
12ffa55d AG |
4817 | /* |
4818 | * Mark these ASICs to be reseted as untracked first | |
4819 | * And add them back after reset completed | |
4820 | */ | |
4821 | amdgpu_unregister_gpu_instance(tmp_adev); | |
4822 | ||
a2f63ee8 | 4823 | amdgpu_fbdev_set_suspend(tmp_adev, 1); |
565d1941 | 4824 | |
f1c1314b | 4825 | /* disable ras on ALL IPs */ |
bb5c7235 | 4826 | if (!need_emergency_restart && |
b823821f | 4827 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 4828 | amdgpu_ras_suspend(tmp_adev); |
4829 | ||
1d721ed6 AG |
4830 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4831 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4832 | ||
4833 | if (!ring || !ring->sched.thread) | |
4834 | continue; | |
4835 | ||
0b2d2c2e | 4836 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 4837 | |
bb5c7235 | 4838 | if (need_emergency_restart) |
7c6e68c7 | 4839 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 4840 | } |
8f8c80f4 | 4841 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
4842 | } |
4843 | ||
bb5c7235 | 4844 | if (need_emergency_restart) |
7c6e68c7 AG |
4845 | goto skip_sched_resume; |
4846 | ||
1d721ed6 AG |
4847 | /* |
4848 | * Must check guilty signal here since after this point all old | |
4849 | * HW fences are force signaled. | |
4850 | * | |
4851 | * job->base holds a reference to parent fence | |
4852 | */ | |
4853 | if (job && job->base.s_fence->parent && | |
7dd8c205 | 4854 | dma_fence_is_signaled(job->base.s_fence->parent)) { |
1d721ed6 | 4855 | job_signaled = true; |
1d721ed6 AG |
4856 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
4857 | goto skip_hw_reset; | |
4858 | } | |
4859 | ||
26bc5340 | 4860 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 4861 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
04442bf7 | 4862 | r = amdgpu_device_pre_asic_reset(tmp_adev, &reset_context); |
26bc5340 AG |
4863 | /*TODO Should we stop ?*/ |
4864 | if (r) { | |
aac89168 | 4865 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 4866 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
4867 | tmp_adev->asic_reset_res = r; |
4868 | } | |
4869 | } | |
4870 | ||
e6c6338f | 4871 | tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); |
26bc5340 AG |
4872 | /* Actual ASIC resets if needed.*/ |
4873 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
4874 | if (amdgpu_sriov_vf(adev)) { | |
4875 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
4876 | if (r) | |
4877 | adev->asic_reset_res = r; | |
4878 | } else { | |
04442bf7 | 4879 | r = amdgpu_do_asic_reset(device_list_handle, &reset_context); |
26bc5340 AG |
4880 | if (r && r == -EAGAIN) |
4881 | goto retry; | |
4882 | } | |
4883 | ||
1d721ed6 AG |
4884 | skip_hw_reset: |
4885 | ||
26bc5340 | 4886 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 4887 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 4888 | |
e6c6338f JZ |
4889 | /* |
4890 | * Sometimes a later bad compute job can block a good gfx job as gfx | |
4891 | * and compute ring share internal GC HW mutually. We add an additional | |
4892 | * guilty jobs recheck step to find the real guilty job, it synchronously | |
4893 | * submits and pends for the first job being signaled. If it gets timeout, | |
4894 | * we identify it as a real guilty job. | |
4895 | */ | |
4896 | if (amdgpu_gpu_recovery == 2 && | |
4897 | !(tmp_vram_lost_counter < atomic_read(&adev->vram_lost_counter))) | |
04442bf7 LL |
4898 | amdgpu_device_recheck_guilty_jobs( |
4899 | tmp_adev, device_list_handle, &reset_context); | |
e6c6338f | 4900 | |
1d721ed6 AG |
4901 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4902 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
4903 | ||
4904 | if (!ring || !ring->sched.thread) | |
4905 | continue; | |
4906 | ||
4907 | /* No point to resubmit jobs if we didn't HW reset*/ | |
4908 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
4909 | drm_sched_resubmit_jobs(&ring->sched); | |
4910 | ||
4911 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
4912 | } | |
4913 | ||
4914 | if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) { | |
4a580877 | 4915 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
4916 | } |
4917 | ||
4918 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
4919 | |
4920 | if (r) { | |
4921 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 4922 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
4923 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
4924 | } else { | |
12ffa55d | 4925 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 | 4926 | } |
7c6e68c7 | 4927 | } |
26bc5340 | 4928 | |
7c6e68c7 | 4929 | skip_sched_resume: |
655ce9cb | 4930 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8e2712e7 | 4931 | /* unlock kfd: SRIOV would do it separately */ |
bb5c7235 | 4932 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
7c6e68c7 | 4933 | amdgpu_amdkfd_post_reset(tmp_adev); |
8e2712e7 | 4934 | |
4935 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
4936 | * need to bring up kfd here if it's not be initialized before | |
4937 | */ | |
4938 | if (!adev->kfd.init_complete) | |
4939 | amdgpu_amdkfd_device_init(adev); | |
4940 | ||
3f12acc8 EQ |
4941 | if (audio_suspended) |
4942 | amdgpu_device_resume_display_audio(tmp_adev); | |
26bc5340 AG |
4943 | amdgpu_device_unlock_adev(tmp_adev); |
4944 | } | |
4945 | ||
cbfd17f7 | 4946 | skip_recovery: |
9e94d22c | 4947 | if (hive) { |
53b3f8f4 | 4948 | atomic_set(&hive->in_reset, 0); |
9e94d22c | 4949 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 4950 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 4951 | } |
26bc5340 | 4952 | |
91fb309d | 4953 | if (r && r != -EAGAIN) |
26bc5340 | 4954 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
d38ceaf9 AD |
4955 | return r; |
4956 | } | |
4957 | ||
e3ecdffa AD |
4958 | /** |
4959 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
4960 | * | |
4961 | * @adev: amdgpu_device pointer | |
4962 | * | |
4963 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
4964 | * and lanes) of the slot the device is in. Handles APUs and | |
4965 | * virtualized environments where PCIE config space may not be available. | |
4966 | */ | |
5494d864 | 4967 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 4968 | { |
5d9a6330 | 4969 | struct pci_dev *pdev; |
c5313457 HK |
4970 | enum pci_bus_speed speed_cap, platform_speed_cap; |
4971 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 4972 | |
cd474ba0 AD |
4973 | if (amdgpu_pcie_gen_cap) |
4974 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 4975 | |
cd474ba0 AD |
4976 | if (amdgpu_pcie_lane_cap) |
4977 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 4978 | |
cd474ba0 AD |
4979 | /* covers APUs as well */ |
4980 | if (pci_is_root_bus(adev->pdev->bus)) { | |
4981 | if (adev->pm.pcie_gen_mask == 0) | |
4982 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
4983 | if (adev->pm.pcie_mlw_mask == 0) | |
4984 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 4985 | return; |
cd474ba0 | 4986 | } |
d0dd7f0c | 4987 | |
c5313457 HK |
4988 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
4989 | return; | |
4990 | ||
dbaa922b AD |
4991 | pcie_bandwidth_available(adev->pdev, NULL, |
4992 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 4993 | |
cd474ba0 | 4994 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
4995 | /* asic caps */ |
4996 | pdev = adev->pdev; | |
4997 | speed_cap = pcie_get_speed_cap(pdev); | |
4998 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
4999 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
5000 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
5001 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 5002 | } else { |
2b3a1f51 FX |
5003 | if (speed_cap == PCIE_SPEED_32_0GT) |
5004 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5005 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5006 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5007 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5008 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5009 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5010 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5011 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5012 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5013 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
5014 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
5015 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5016 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5017 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
5018 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
5019 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5020 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5021 | else | |
5022 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5023 | } | |
5024 | /* platform caps */ | |
c5313457 | 5025 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
5026 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5027 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5028 | } else { | |
2b3a1f51 FX |
5029 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
5030 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5031 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5032 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5033 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5034 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5035 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5036 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5037 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5038 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5039 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 5040 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
5041 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5042 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5043 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 5044 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
5045 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5046 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5047 | else | |
5048 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5049 | ||
cd474ba0 AD |
5050 | } |
5051 | } | |
5052 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 5053 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
5054 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
5055 | } else { | |
c5313457 | 5056 | switch (platform_link_width) { |
5d9a6330 | 5057 | case PCIE_LNK_X32: |
cd474ba0 AD |
5058 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
5059 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
5060 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5061 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5062 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5063 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5064 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5065 | break; | |
5d9a6330 | 5066 | case PCIE_LNK_X16: |
cd474ba0 AD |
5067 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5068 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5069 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5070 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5071 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5072 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5073 | break; | |
5d9a6330 | 5074 | case PCIE_LNK_X12: |
cd474ba0 AD |
5075 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5076 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5077 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5078 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5079 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5080 | break; | |
5d9a6330 | 5081 | case PCIE_LNK_X8: |
cd474ba0 AD |
5082 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5083 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5084 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5085 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5086 | break; | |
5d9a6330 | 5087 | case PCIE_LNK_X4: |
cd474ba0 AD |
5088 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5089 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5090 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5091 | break; | |
5d9a6330 | 5092 | case PCIE_LNK_X2: |
cd474ba0 AD |
5093 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5094 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5095 | break; | |
5d9a6330 | 5096 | case PCIE_LNK_X1: |
cd474ba0 AD |
5097 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5098 | break; | |
5099 | default: | |
5100 | break; | |
5101 | } | |
d0dd7f0c AD |
5102 | } |
5103 | } | |
5104 | } | |
d38ceaf9 | 5105 | |
361dbd01 AD |
5106 | int amdgpu_device_baco_enter(struct drm_device *dev) |
5107 | { | |
1348969a | 5108 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5109 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 5110 | |
4a580877 | 5111 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5112 | return -ENOTSUPP; |
5113 | ||
6fb33209 | 5114 | if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5115 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
5116 | ||
9530273e | 5117 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
5118 | } |
5119 | ||
5120 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
5121 | { | |
1348969a | 5122 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5123 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 5124 | int ret = 0; |
361dbd01 | 5125 | |
4a580877 | 5126 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5127 | return -ENOTSUPP; |
5128 | ||
9530273e EQ |
5129 | ret = amdgpu_dpm_baco_exit(adev); |
5130 | if (ret) | |
5131 | return ret; | |
7a22677b | 5132 | |
6fb33209 | 5133 | if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5134 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
5135 | ||
5136 | return 0; | |
361dbd01 | 5137 | } |
c9a6b82f | 5138 | |
acd89fca AG |
5139 | static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev) |
5140 | { | |
5141 | int i; | |
5142 | ||
5143 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5144 | struct amdgpu_ring *ring = adev->rings[i]; | |
5145 | ||
5146 | if (!ring || !ring->sched.thread) | |
5147 | continue; | |
5148 | ||
5149 | cancel_delayed_work_sync(&ring->sched.work_tdr); | |
5150 | } | |
5151 | } | |
5152 | ||
c9a6b82f AG |
5153 | /** |
5154 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
5155 | * @pdev: PCI device struct | |
5156 | * @state: PCI channel state | |
5157 | * | |
5158 | * Description: Called when a PCI error is detected. | |
5159 | * | |
5160 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
5161 | */ | |
5162 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5163 | { | |
5164 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5165 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5166 | int i; |
c9a6b82f AG |
5167 | |
5168 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
5169 | ||
6894305c AG |
5170 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
5171 | DRM_WARN("No support for XGMI hive yet..."); | |
5172 | return PCI_ERS_RESULT_DISCONNECT; | |
5173 | } | |
5174 | ||
c9a6b82f AG |
5175 | switch (state) { |
5176 | case pci_channel_io_normal: | |
5177 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 5178 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
5179 | case pci_channel_io_frozen: |
5180 | /* | |
acd89fca AG |
5181 | * Cancel and wait for all TDRs in progress if failing to |
5182 | * set adev->in_gpu_reset in amdgpu_device_lock_adev | |
5183 | * | |
5184 | * Locking adev->reset_sem will prevent any external access | |
5185 | * to GPU during PCI error recovery | |
5186 | */ | |
5187 | while (!amdgpu_device_lock_adev(adev, NULL)) | |
5188 | amdgpu_cancel_all_tdr(adev); | |
5189 | ||
5190 | /* | |
5191 | * Block any work scheduling as we do for regular GPU reset | |
5192 | * for the duration of the recovery | |
5193 | */ | |
5194 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5195 | struct amdgpu_ring *ring = adev->rings[i]; | |
5196 | ||
5197 | if (!ring || !ring->sched.thread) | |
5198 | continue; | |
5199 | ||
5200 | drm_sched_stop(&ring->sched, NULL); | |
5201 | } | |
8f8c80f4 | 5202 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
5203 | return PCI_ERS_RESULT_NEED_RESET; |
5204 | case pci_channel_io_perm_failure: | |
5205 | /* Permanent error, prepare for device removal */ | |
5206 | return PCI_ERS_RESULT_DISCONNECT; | |
5207 | } | |
5208 | ||
5209 | return PCI_ERS_RESULT_NEED_RESET; | |
5210 | } | |
5211 | ||
5212 | /** | |
5213 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
5214 | * @pdev: pointer to PCI device | |
5215 | */ | |
5216 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
5217 | { | |
5218 | ||
5219 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
5220 | ||
5221 | /* TODO - dump whatever for debugging purposes */ | |
5222 | ||
5223 | /* This called only if amdgpu_pci_error_detected returns | |
5224 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
5225 | * works, no need to reset slot. | |
5226 | */ | |
5227 | ||
5228 | return PCI_ERS_RESULT_RECOVERED; | |
5229 | } | |
5230 | ||
5231 | /** | |
5232 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
5233 | * @pdev: PCI device struct | |
5234 | * | |
5235 | * Description: This routine is called by the pci error recovery | |
5236 | * code after the PCI slot has been reset, just before we | |
5237 | * should resume normal operations. | |
5238 | */ | |
5239 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
5240 | { | |
5241 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5242 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 5243 | int r, i; |
04442bf7 | 5244 | struct amdgpu_reset_context reset_context; |
362c7b91 | 5245 | u32 memsize; |
7ac71382 | 5246 | struct list_head device_list; |
c9a6b82f AG |
5247 | |
5248 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
5249 | ||
04442bf7 LL |
5250 | memset(&reset_context, 0, sizeof(reset_context)); |
5251 | ||
7ac71382 | 5252 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 5253 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 5254 | |
362c7b91 AG |
5255 | /* wait for asic to come out of reset */ |
5256 | msleep(500); | |
5257 | ||
7ac71382 | 5258 | /* Restore PCI confspace */ |
c1dd4aa6 | 5259 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 5260 | |
362c7b91 AG |
5261 | /* confirm ASIC came out of reset */ |
5262 | for (i = 0; i < adev->usec_timeout; i++) { | |
5263 | memsize = amdgpu_asic_get_config_memsize(adev); | |
5264 | ||
5265 | if (memsize != 0xffffffff) | |
5266 | break; | |
5267 | udelay(1); | |
5268 | } | |
5269 | if (memsize == 0xffffffff) { | |
5270 | r = -ETIME; | |
5271 | goto out; | |
5272 | } | |
5273 | ||
04442bf7 LL |
5274 | reset_context.method = AMD_RESET_METHOD_NONE; |
5275 | reset_context.reset_req_dev = adev; | |
5276 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5277 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); | |
5278 | ||
8a11d283 | 5279 | adev->in_pci_err_recovery = true; |
04442bf7 | 5280 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
bf36b52e | 5281 | adev->in_pci_err_recovery = false; |
c9a6b82f AG |
5282 | if (r) |
5283 | goto out; | |
5284 | ||
04442bf7 | 5285 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
c9a6b82f AG |
5286 | |
5287 | out: | |
c9a6b82f | 5288 | if (!r) { |
c1dd4aa6 AG |
5289 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
5290 | pci_restore_state(adev->pdev); | |
5291 | ||
c9a6b82f AG |
5292 | DRM_INFO("PCIe error recovery succeeded\n"); |
5293 | } else { | |
5294 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
5295 | amdgpu_device_unlock_adev(adev); | |
5296 | } | |
5297 | ||
5298 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
5299 | } | |
5300 | ||
5301 | /** | |
5302 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
5303 | * @pdev: pointer to PCI device | |
5304 | * | |
5305 | * Called when the error recovery driver tells us that its | |
505199a3 | 5306 | * OK to resume normal operation. |
c9a6b82f AG |
5307 | */ |
5308 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
5309 | { | |
5310 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5311 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5312 | int i; |
c9a6b82f | 5313 | |
c9a6b82f AG |
5314 | |
5315 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca AG |
5316 | |
5317 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5318 | struct amdgpu_ring *ring = adev->rings[i]; | |
5319 | ||
5320 | if (!ring || !ring->sched.thread) | |
5321 | continue; | |
5322 | ||
5323 | ||
5324 | drm_sched_resubmit_jobs(&ring->sched); | |
5325 | drm_sched_start(&ring->sched, true); | |
5326 | } | |
5327 | ||
5328 | amdgpu_device_unlock_adev(adev); | |
c9a6b82f | 5329 | } |
c1dd4aa6 AG |
5330 | |
5331 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
5332 | { | |
5333 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5334 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5335 | int r; | |
5336 | ||
5337 | r = pci_save_state(pdev); | |
5338 | if (!r) { | |
5339 | kfree(adev->pci_state); | |
5340 | ||
5341 | adev->pci_state = pci_store_saved_state(pdev); | |
5342 | ||
5343 | if (!adev->pci_state) { | |
5344 | DRM_ERROR("Failed to store PCI saved state"); | |
5345 | return false; | |
5346 | } | |
5347 | } else { | |
5348 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
5349 | return false; | |
5350 | } | |
5351 | ||
5352 | return true; | |
5353 | } | |
5354 | ||
5355 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
5356 | { | |
5357 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5358 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5359 | int r; | |
5360 | ||
5361 | if (!adev->pci_state) | |
5362 | return false; | |
5363 | ||
5364 | r = pci_load_saved_state(pdev, adev->pci_state); | |
5365 | ||
5366 | if (!r) { | |
5367 | pci_restore_state(pdev); | |
5368 | } else { | |
5369 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
5370 | return false; | |
5371 | } | |
5372 | ||
5373 | return true; | |
5374 | } | |
5375 | ||
5376 |