[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ctx.h

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef __AMDGPU_CTX_H__
#define __AMDGPU_CTX_H__

#include "amdgpu_ring.h"

struct drm_device;
struct drm_file;
struct amdgpu_fpriv;

#define AMDGPU_MAX_ENTITY_NUM 4
#define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total))

struct amdgpu_ctx_entity {
	uint64_t		sequence;
	struct drm_sched_entity	entity;
	struct dma_fence	*fences[];
};

struct amdgpu_ctx {
	struct kref			refcount;
	struct amdgpu_device		*adev;
	unsigned			reset_counter;
	unsigned			reset_counter_query;
	uint32_t			vram_lost_counter;
	spinlock_t			ring_lock;
	struct amdgpu_ctx_entity	*entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
	bool				preamble_presented;
	int32_t				init_priority;
	int32_t				override_priority;
	struct mutex			lock;
	atomic_t			guilty;
	unsigned long			ras_counter_ce;
	unsigned long			ras_counter_ue;
	uint32_t			stable_pstate;
};

struct amdgpu_ctx_mgr {
	struct amdgpu_device	*adev;
	struct mutex		lock;
	/* protected by lock */
	struct idr		ctx_handles;
};

extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
int amdgpu_ctx_put(struct amdgpu_ctx *ctx);

int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
			  u32 ring, struct drm_sched_entity **entity);
void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
			  struct drm_sched_entity *entity,
			  struct dma_fence *fence, uint64_t *seq);
struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
				       struct drm_sched_entity *entity,
				       uint64_t seq);
bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, int32_t ctx_prio);

int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *filp);

int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
			       struct drm_sched_entity *entity);

void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
		uint32_t idx, uint64_t *elapsed);
#endif
Commit	Line	Data
8290268f CK	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef __AMDGPU_CTX_H__
	24	#define __AMDGPU_CTX_H__
	25
	26	#include "amdgpu_ring.h"
	27
	28	struct drm_device;
	29	struct drm_file;
	30	struct amdgpu_fpriv;
	31
977f7e10	32	#define AMDGPU_MAX_ENTITY_NUM 4
5c439c38	33	#define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total))
977f7e10	34
1b1f2fec	35	struct amdgpu_ctx_entity {
8290268f	36	uint64_t sequence;
8290268f	37	struct drm_sched_entity entity;
977f7e10	38	struct dma_fence *fences[];
8290268f CK	39	};
	40
	41	struct amdgpu_ctx {
1b1f2fec CK	42	struct kref refcount;
	43	struct amdgpu_device *adev;
	44	unsigned reset_counter;
	45	unsigned reset_counter_query;
	46	uint32_t vram_lost_counter;
	47	spinlock_t ring_lock;
977f7e10	48	struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
1b1f2fec	49	bool preamble_presented;
84d588c3 ND	50	int32_t init_priority;
84d588c3 ND	51	int32_t override_priority;
94f4c496	52	struct mutex lock;
1b1f2fec	53	atomic_t guilty;
64cc5414 GC	54	unsigned long ras_counter_ce;
64cc5414 GC	55	unsigned long ras_counter_ue;
8cda7a4f	56	uint32_t stable_pstate;
8290268f CK	57	};
	58
	59	struct amdgpu_ctx_mgr {
	60	struct amdgpu_device *adev;
	61	struct mutex lock;
	62	/* protected by lock */
	63	struct idr ctx_handles;
	64	};
	65
1b1f2fec CK	66	extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
1b1f2fec CK	67
8290268f CK	68	struct amdgpu_ctx amdgpu_ctx_get(struct amdgpu_fpriv fpriv, uint32_t id);
	69	int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
	70
0d346a14 CK	71	int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
0d346a14 CK	72	u32 ring, struct drm_sched_entity **entity);
85eff200 CK	73	void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
	74	struct drm_sched_entity *entity,
	75	struct dma_fence fence, uint64_t seq);
8290268f	76	struct dma_fence amdgpu_ctx_get_fence(struct amdgpu_ctx ctx,
0d346a14 CK	77	struct drm_sched_entity *entity,
0d346a14 CK	78	uint64_t seq);
84d588c3 ND	79	bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
84d588c3 ND	80	void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, int32_t ctx_prio);
8290268f CK	81
	82	int amdgpu_ctx_ioctl(struct drm_device dev, void data,
	83	struct drm_file *filp);
	84
0d346a14 CK	85	int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
0d346a14 CK	86	struct drm_sched_entity *entity);
8290268f CK	87
	88	void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
	89	void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
56753e73	90	long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
8290268f	91	void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
87444254 RS	92	ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
87444254 RS	93	uint32_t idx, uint64_t *elapsed);
8290268f	94	#endif