[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ctx.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: monk liu <monk.liu@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"

static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
{
	unsigned i, j;
	int r;

	memset(ctx, 0, sizeof(*ctx));
	ctx->adev = adev;
	kref_init(&ctx->refcount);
	spin_lock_init(&ctx->ring_lock);
	ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS,
			      sizeof(struct fence*), GFP_KERNEL);
	if (!ctx->fences)
		return -ENOMEM;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		ctx->rings[i].sequence = 1;
		ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
	}

	ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);

	/* create context entity for each ring */
	for (i = 0; i < adev->num_rings; i++) {
		struct amdgpu_ring *ring = adev->rings[i];
		struct amd_sched_rq *rq;

		rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
		r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
					  rq, amdgpu_sched_jobs);
		if (r)
			break;
	}

	if (i < adev->num_rings) {
		for (j = 0; j < i; j++)
			amd_sched_entity_fini(&adev->rings[j]->sched,
					      &ctx->rings[j].entity);
		kfree(ctx->fences);
		ctx->fences = NULL;
		return r;
	}
	return 0;
}

static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
{
	struct amdgpu_device *adev = ctx->adev;
	unsigned i, j;

	if (!adev)
		return;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		for (j = 0; j < amdgpu_sched_jobs; ++j)
			fence_put(ctx->rings[i].fences[j]);
	kfree(ctx->fences);
	ctx->fences = NULL;

	for (i = 0; i < adev->num_rings; i++)
		amd_sched_entity_fini(&adev->rings[i]->sched,
				      &ctx->rings[i].entity);
}

static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv,
			    uint32_t *id)
{
	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	struct amdgpu_ctx *ctx;
	int r;

	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return -ENOMEM;

	mutex_lock(&mgr->lock);
	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	if (r < 0) {
		mutex_unlock(&mgr->lock);
		kfree(ctx);
		return r;
	}
	*id = (uint32_t)r;
	r = amdgpu_ctx_init(adev, ctx);
	if (r) {
		idr_remove(&mgr->ctx_handles, *id);
		*id = 0;
		kfree(ctx);
	}
	mutex_unlock(&mgr->lock);
	return r;
}

static void amdgpu_ctx_do_release(struct kref *ref)
{
	struct amdgpu_ctx *ctx;

	ctx = container_of(ref, struct amdgpu_ctx, refcount);

	amdgpu_ctx_fini(ctx);

	kfree(ctx);
}

static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	struct amdgpu_ctx *ctx;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx) {
		idr_remove(&mgr->ctx_handles, id);
		kref_put(&ctx->refcount, amdgpu_ctx_do_release);
		mutex_unlock(&mgr->lock);
		return 0;
	}
	mutex_unlock(&mgr->lock);
	return -EINVAL;
}

static int amdgpu_ctx_query(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv, uint32_t id,
			    union drm_amdgpu_ctx_out *out)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;
	unsigned reset_counter;

	if (!fpriv)
		return -EINVAL;

	mgr = &fpriv->ctx_mgr;
	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (!ctx) {
		mutex_unlock(&mgr->lock);
		return -EINVAL;
	}

	/* TODO: these two are always zero */
	out->state.flags = 0x0;
	out->state.hangs = 0x0;

	/* determine if a GPU reset has occured since the last call */
	reset_counter = atomic_read(&adev->gpu_reset_counter);
	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	if (ctx->reset_counter == reset_counter)
		out->state.reset_status = AMDGPU_CTX_NO_RESET;
	else
		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	ctx->reset_counter = reset_counter;

	mutex_unlock(&mgr->lock);
	return 0;
}

int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *filp)
{
	int r;
	uint32_t id;

	union drm_amdgpu_ctx *args = data;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	r = 0;
	id = args->in.ctx_id;

	switch (args->in.op) {
	case AMDGPU_CTX_OP_ALLOC_CTX:
		r = amdgpu_ctx_alloc(adev, fpriv, &id);
		args->out.alloc.ctx_id = id;
		break;
	case AMDGPU_CTX_OP_FREE_CTX:
		r = amdgpu_ctx_free(fpriv, id);
		break;
	case AMDGPU_CTX_OP_QUERY_STATE:
		r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
		break;
	default:
		return -EINVAL;
	}

	return r;
}

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;

	if (!fpriv)
		return NULL;

	mgr = &fpriv->ctx_mgr;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx)
		kref_get(&ctx->refcount);
	mutex_unlock(&mgr->lock);
	return ctx;
}

int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
{
	if (ctx == NULL)
		return -EINVAL;

	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
	return 0;
}

uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
			      struct fence *fence)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	uint64_t seq = cring->sequence;
	unsigned idx = 0;
	struct fence *other = NULL;

	idx = seq & (amdgpu_sched_jobs - 1);
	other = cring->fences[idx];
	if (other) {
		signed long r;
		r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
		if (r < 0)
			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	}

	fence_get(fence);

	spin_lock(&ctx->ring_lock);
	cring->fences[idx] = fence;
	cring->sequence++;
	spin_unlock(&ctx->ring_lock);

	fence_put(other);

	return seq;
}

struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
				   struct amdgpu_ring *ring, uint64_t seq)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	struct fence *fence;

	spin_lock(&ctx->ring_lock);

	if (seq >= cring->sequence) {
		spin_unlock(&ctx->ring_lock);
		return ERR_PTR(-EINVAL);
	}


	if (seq + amdgpu_sched_jobs < cring->sequence) {
		spin_unlock(&ctx->ring_lock);
		return NULL;
	}

	fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
	spin_unlock(&ctx->ring_lock);

	return fence;
}

void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
{
	mutex_init(&mgr->lock);
	idr_init(&mgr->ctx_handles);
}

void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
{
	struct amdgpu_ctx *ctx;
	struct idr *idp;
	uint32_t id;

	idp = &mgr->ctx_handles;

	idr_for_each_entry(idp, ctx, id) {
		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
			DRM_ERROR("ctx %p is still alive\n", ctx);
	}

	idr_destroy(&mgr->ctx_handles);
	mutex_destroy(&mgr->lock);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: monk liu <monk.liu@amd.com>
	23	*/
	24
	25	#include <drm/drmP.h>
	26	#include "amdgpu.h"
	27
20874179	28	static int amdgpu_ctx_init(struct amdgpu_device adev, struct amdgpu_ctx ctx)
d38ceaf9	29	{
21c16bf6	30	unsigned i, j;
47f38501	31	int r;
d38ceaf9	32
23ca0e4e CZ	33	memset(ctx, 0, sizeof(*ctx));
	34	ctx->adev = adev;
	35	kref_init(&ctx->refcount);
	36	spin_lock_init(&ctx->ring_lock);
a750b47e CK	37	ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS,
a750b47e CK	38	sizeof(struct fence*), GFP_KERNEL);
37cd0ca2 CZ	39	if (!ctx->fences)
37cd0ca2 CZ	40	return -ENOMEM;
d38ceaf9	41
37cd0ca2 CZ	42	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
37cd0ca2 CZ	43	ctx->rings[i].sequence = 1;
a750b47e	44	ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
37cd0ca2	45	}
ce199ad6 NH	46
	47	ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
	48
cadf97b1 CZ	49	/* create context entity for each ring */
cadf97b1 CZ	50	for (i = 0; i < adev->num_rings; i++) {
20874179	51	struct amdgpu_ring *ring = adev->rings[i];
cadf97b1	52	struct amd_sched_rq *rq;
20874179 CK	53
	54	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
	55	r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
cadf97b1 CZ	56	rq, amdgpu_sched_jobs);
	57	if (r)
	58	break;
	59	}
	60
	61	if (i < adev->num_rings) {
	62	for (j = 0; j < i; j++)
	63	amd_sched_entity_fini(&adev->rings[j]->sched,
	64	&ctx->rings[j].entity);
	65	kfree(ctx->fences);
54ddf3a6	66	ctx->fences = NULL;
cadf97b1	67	return r;
9cb7e5a9	68	}
d38ceaf9 AD	69	return 0;
	70	}
	71
20874179	72	static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
d38ceaf9	73	{
47f38501 CK	74	struct amdgpu_device *adev = ctx->adev;
	75	unsigned i, j;
	76
fe295b27 DA	77	if (!adev)
	78	return;
	79
47f38501	80	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
37cd0ca2	81	for (j = 0; j < amdgpu_sched_jobs; ++j)
47f38501	82	fence_put(ctx->rings[i].fences[j]);
37cd0ca2	83	kfree(ctx->fences);
54ddf3a6	84	ctx->fences = NULL;
47f38501	85
cadf97b1 CZ	86	for (i = 0; i < adev->num_rings; i++)
	87	amd_sched_entity_fini(&adev->rings[i]->sched,
	88	&ctx->rings[i].entity);
47f38501 CK	89	}
	90
	91	static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
	92	struct amdgpu_fpriv *fpriv,
	93	uint32_t *id)
	94	{
	95	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
d38ceaf9	96	struct amdgpu_ctx *ctx;
47f38501	97	int r;
d38ceaf9	98
47f38501 CK	99	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	100	if (!ctx)
	101	return -ENOMEM;
	102
	103	mutex_lock(&mgr->lock);
	104	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	105	if (r < 0) {
0147ee0f	106	mutex_unlock(&mgr->lock);
47f38501 CK	107	kfree(ctx);
	108	return r;
	109	}
	110	*id = (uint32_t)r;
20874179	111	r = amdgpu_ctx_init(adev, ctx);
c648ed7c CZ	112	if (r) {
	113	idr_remove(&mgr->ctx_handles, *id);
	114	*id = 0;
	115	kfree(ctx);
	116	}
47f38501	117	mutex_unlock(&mgr->lock);
47f38501 CK	118	return r;
	119	}
	120
	121	static void amdgpu_ctx_do_release(struct kref *ref)
	122	{
	123	struct amdgpu_ctx *ctx;
	124
	125	ctx = container_of(ref, struct amdgpu_ctx, refcount);
	126
	127	amdgpu_ctx_fini(ctx);
	128
	129	kfree(ctx);
	130	}
	131
	132	static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
	133	{
	134	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	135	struct amdgpu_ctx *ctx;
	136
	137	mutex_lock(&mgr->lock);
	138	ctx = idr_find(&mgr->ctx_handles, id);
	139	if (ctx) {
	140	idr_remove(&mgr->ctx_handles, id);
23ca0e4e	141	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
47f38501	142	mutex_unlock(&mgr->lock);
f11358da	143	return 0;
d38ceaf9	144	}
47f38501	145	mutex_unlock(&mgr->lock);
d38ceaf9 AD	146	return -EINVAL;
	147	}
	148
d94aed5a MO	149	static int amdgpu_ctx_query(struct amdgpu_device *adev,
	150	struct amdgpu_fpriv *fpriv, uint32_t id,
	151	union drm_amdgpu_ctx_out *out)
d38ceaf9 AD	152	{
d38ceaf9 AD	153	struct amdgpu_ctx *ctx;
23ca0e4e	154	struct amdgpu_ctx_mgr *mgr;
d94aed5a	155	unsigned reset_counter;
d38ceaf9	156
23ca0e4e CZ	157	if (!fpriv)
	158	return -EINVAL;
	159
	160	mgr = &fpriv->ctx_mgr;
0147ee0f	161	mutex_lock(&mgr->lock);
d38ceaf9	162	ctx = idr_find(&mgr->ctx_handles, id);
d94aed5a	163	if (!ctx) {
0147ee0f	164	mutex_unlock(&mgr->lock);
d94aed5a	165	return -EINVAL;
d38ceaf9	166	}
d94aed5a MO	167
d94aed5a MO	168	/* TODO: these two are always zero */
0b492a4c AD	169	out->state.flags = 0x0;
0b492a4c AD	170	out->state.hangs = 0x0;
d94aed5a MO	171
	172	/* determine if a GPU reset has occured since the last call */
	173	reset_counter = atomic_read(&adev->gpu_reset_counter);
	174	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	175	if (ctx->reset_counter == reset_counter)
	176	out->state.reset_status = AMDGPU_CTX_NO_RESET;
	177	else
	178	out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	179	ctx->reset_counter = reset_counter;
	180
0147ee0f	181	mutex_unlock(&mgr->lock);
d94aed5a	182	return 0;
d38ceaf9 AD	183	}
d38ceaf9 AD	184
d38ceaf9	185	int amdgpu_ctx_ioctl(struct drm_device dev, void data,
d94aed5a	186	struct drm_file *filp)
d38ceaf9 AD	187	{
	188	int r;
	189	uint32_t id;
d38ceaf9 AD	190
	191	union drm_amdgpu_ctx *args = data;
	192	struct amdgpu_device *adev = dev->dev_private;
	193	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	194
	195	r = 0;
	196	id = args->in.ctx_id;
d38ceaf9 AD	197
d38ceaf9 AD	198	switch (args->in.op) {
a750b47e CK	199	case AMDGPU_CTX_OP_ALLOC_CTX:
	200	r = amdgpu_ctx_alloc(adev, fpriv, &id);
	201	args->out.alloc.ctx_id = id;
	202	break;
	203	case AMDGPU_CTX_OP_FREE_CTX:
	204	r = amdgpu_ctx_free(fpriv, id);
	205	break;
	206	case AMDGPU_CTX_OP_QUERY_STATE:
	207	r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
	208	break;
	209	default:
	210	return -EINVAL;
d38ceaf9 AD	211	}
	212
	213	return r;
	214	}
66b3cf2a JZ	215
	216	struct amdgpu_ctx amdgpu_ctx_get(struct amdgpu_fpriv fpriv, uint32_t id)
	217	{
	218	struct amdgpu_ctx *ctx;
23ca0e4e CZ	219	struct amdgpu_ctx_mgr *mgr;
	220
	221	if (!fpriv)
	222	return NULL;
	223
	224	mgr = &fpriv->ctx_mgr;
66b3cf2a JZ	225
	226	mutex_lock(&mgr->lock);
	227	ctx = idr_find(&mgr->ctx_handles, id);
	228	if (ctx)
	229	kref_get(&ctx->refcount);
	230	mutex_unlock(&mgr->lock);
	231	return ctx;
	232	}
	233
	234	int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
	235	{
66b3cf2a JZ	236	if (ctx == NULL)
	237	return -EINVAL;
	238
66b3cf2a	239	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
66b3cf2a JZ	240	return 0;
66b3cf2a JZ	241	}
21c16bf6 CK	242
21c16bf6 CK	243	uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx ctx, struct amdgpu_ring ring,
ce882e6d	244	struct fence *fence)
21c16bf6 CK	245	{
21c16bf6 CK	246	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
ce882e6d	247	uint64_t seq = cring->sequence;
b43a9a7e CZ	248	unsigned idx = 0;
b43a9a7e CZ	249	struct fence *other = NULL;
21c16bf6	250
5b011235	251	idx = seq & (amdgpu_sched_jobs - 1);
b43a9a7e	252	other = cring->fences[idx];
21c16bf6 CK	253	if (other) {
	254	signed long r;
	255	r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
	256	if (r < 0)
	257	DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	258	}
	259
	260	fence_get(fence);
	261
	262	spin_lock(&ctx->ring_lock);
	263	cring->fences[idx] = fence;
ce882e6d	264	cring->sequence++;
21c16bf6 CK	265	spin_unlock(&ctx->ring_lock);
	266
	267	fence_put(other);
	268
	269	return seq;
	270	}
	271
	272	struct fence amdgpu_ctx_get_fence(struct amdgpu_ctx ctx,
	273	struct amdgpu_ring *ring, uint64_t seq)
	274	{
	275	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	276	struct fence *fence;
	277
	278	spin_lock(&ctx->ring_lock);
b43a9a7e	279
ce882e6d	280	if (seq >= cring->sequence) {
21c16bf6 CK	281	spin_unlock(&ctx->ring_lock);
	282	return ERR_PTR(-EINVAL);
	283	}
	284
b43a9a7e	285
37cd0ca2	286	if (seq + amdgpu_sched_jobs < cring->sequence) {
21c16bf6 CK	287	spin_unlock(&ctx->ring_lock);
	288	return NULL;
	289	}
	290
5b011235	291	fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
21c16bf6 CK	292	spin_unlock(&ctx->ring_lock);
	293
	294	return fence;
	295	}
efd4ccb5 CK	296
	297	void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
	298	{
	299	mutex_init(&mgr->lock);
	300	idr_init(&mgr->ctx_handles);
	301	}
	302
	303	void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
	304	{
	305	struct amdgpu_ctx *ctx;
	306	struct idr *idp;
	307	uint32_t id;
	308
	309	idp = &mgr->ctx_handles;
	310
	311	idr_for_each_entry(idp, ctx, id) {
	312	if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
	313	DRM_ERROR("ctx %p is still alive\n", ctx);
	314	}
	315
	316	idr_destroy(&mgr->ctx_handles);
	317	mutex_destroy(&mgr->lock);
	318	}