Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
568d7c76 | 27 | #include <linux/pagemap.h> |
d38ceaf9 AD |
28 | #include <drm/drmP.h> |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
d38ceaf9 AD |
33 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, |
34 | u32 ip_instance, u32 ring, | |
35 | struct amdgpu_ring **out_ring) | |
36 | { | |
37 | /* Right now all IPs have only one instance - multiple rings. */ | |
38 | if (ip_instance != 0) { | |
39 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
40 | return -EINVAL; | |
41 | } | |
42 | ||
43 | switch (ip_type) { | |
44 | default: | |
45 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
46 | return -EINVAL; | |
47 | case AMDGPU_HW_IP_GFX: | |
48 | if (ring < adev->gfx.num_gfx_rings) { | |
49 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
50 | } else { | |
51 | DRM_ERROR("only %d gfx rings are supported now\n", | |
52 | adev->gfx.num_gfx_rings); | |
53 | return -EINVAL; | |
54 | } | |
55 | break; | |
56 | case AMDGPU_HW_IP_COMPUTE: | |
57 | if (ring < adev->gfx.num_compute_rings) { | |
58 | *out_ring = &adev->gfx.compute_ring[ring]; | |
59 | } else { | |
60 | DRM_ERROR("only %d compute rings are supported now\n", | |
61 | adev->gfx.num_compute_rings); | |
62 | return -EINVAL; | |
63 | } | |
64 | break; | |
65 | case AMDGPU_HW_IP_DMA: | |
c113ea1c AD |
66 | if (ring < adev->sdma.num_instances) { |
67 | *out_ring = &adev->sdma.instance[ring].ring; | |
d38ceaf9 | 68 | } else { |
c113ea1c AD |
69 | DRM_ERROR("only %d SDMA rings are supported\n", |
70 | adev->sdma.num_instances); | |
d38ceaf9 AD |
71 | return -EINVAL; |
72 | } | |
73 | break; | |
74 | case AMDGPU_HW_IP_UVD: | |
75 | *out_ring = &adev->uvd.ring; | |
76 | break; | |
77 | case AMDGPU_HW_IP_VCE: | |
78 | if (ring < 2){ | |
79 | *out_ring = &adev->vce.ring[ring]; | |
80 | } else { | |
81 | DRM_ERROR("only two VCE rings are supported\n"); | |
82 | return -EINVAL; | |
83 | } | |
84 | break; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
91acbeb6 | 89 | static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, |
758ac17f CK |
90 | struct drm_amdgpu_cs_chunk_fence *data, |
91 | uint32_t *offset) | |
91acbeb6 CK |
92 | { |
93 | struct drm_gem_object *gobj; | |
91acbeb6 | 94 | |
a8ad0bd8 | 95 | gobj = drm_gem_object_lookup(p->filp, data->handle); |
91acbeb6 CK |
96 | if (gobj == NULL) |
97 | return -EINVAL; | |
98 | ||
758ac17f | 99 | p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); |
91acbeb6 CK |
100 | p->uf_entry.priority = 0; |
101 | p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; | |
102 | p->uf_entry.tv.shared = true; | |
2f568dbd | 103 | p->uf_entry.user_pages = NULL; |
758ac17f | 104 | *offset = data->offset; |
91acbeb6 CK |
105 | |
106 | drm_gem_object_unreference_unlocked(gobj); | |
758ac17f CK |
107 | |
108 | if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { | |
109 | amdgpu_bo_unref(&p->uf_entry.robj); | |
110 | return -EINVAL; | |
111 | } | |
112 | ||
91acbeb6 CK |
113 | return 0; |
114 | } | |
115 | ||
d38ceaf9 AD |
116 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
117 | { | |
4c0b242c | 118 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
c5637837 | 119 | struct amdgpu_vm *vm = &fpriv->vm; |
d38ceaf9 AD |
120 | union drm_amdgpu_cs *cs = data; |
121 | uint64_t *chunk_array_user; | |
1d263474 | 122 | uint64_t *chunk_array; |
50838c8c | 123 | unsigned size, num_ibs = 0; |
758ac17f | 124 | uint32_t uf_offset = 0; |
54313503 | 125 | int i; |
1d263474 | 126 | int ret; |
d38ceaf9 | 127 | |
1d263474 DC |
128 | if (cs->in.num_chunks == 0) |
129 | return 0; | |
130 | ||
131 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
132 | if (!chunk_array) | |
133 | return -ENOMEM; | |
d38ceaf9 | 134 | |
3cb485f3 CK |
135 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
136 | if (!p->ctx) { | |
1d263474 DC |
137 | ret = -EINVAL; |
138 | goto free_chunk; | |
3cb485f3 | 139 | } |
1d263474 | 140 | |
d38ceaf9 | 141 | /* get chunks */ |
028423b0 | 142 | chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); |
d38ceaf9 AD |
143 | if (copy_from_user(chunk_array, chunk_array_user, |
144 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
1d263474 | 145 | ret = -EFAULT; |
2a7d9bda | 146 | goto put_ctx; |
d38ceaf9 AD |
147 | } |
148 | ||
149 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 150 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 | 151 | GFP_KERNEL); |
1d263474 DC |
152 | if (!p->chunks) { |
153 | ret = -ENOMEM; | |
2a7d9bda | 154 | goto put_ctx; |
d38ceaf9 AD |
155 | } |
156 | ||
157 | for (i = 0; i < p->nchunks; i++) { | |
158 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
159 | struct drm_amdgpu_cs_chunk user_chunk; | |
160 | uint32_t __user *cdata; | |
161 | ||
028423b0 | 162 | chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; |
d38ceaf9 AD |
163 | if (copy_from_user(&user_chunk, chunk_ptr, |
164 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
1d263474 DC |
165 | ret = -EFAULT; |
166 | i--; | |
167 | goto free_partial_kdata; | |
d38ceaf9 AD |
168 | } |
169 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
170 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
171 | |
172 | size = p->chunks[i].length_dw; | |
028423b0 | 173 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
d38ceaf9 AD |
174 | |
175 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
176 | if (p->chunks[i].kdata == NULL) { | |
1d263474 DC |
177 | ret = -ENOMEM; |
178 | i--; | |
179 | goto free_partial_kdata; | |
d38ceaf9 AD |
180 | } |
181 | size *= sizeof(uint32_t); | |
182 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
1d263474 DC |
183 | ret = -EFAULT; |
184 | goto free_partial_kdata; | |
d38ceaf9 AD |
185 | } |
186 | ||
9a5e8fb1 CK |
187 | switch (p->chunks[i].chunk_id) { |
188 | case AMDGPU_CHUNK_ID_IB: | |
50838c8c | 189 | ++num_ibs; |
9a5e8fb1 CK |
190 | break; |
191 | ||
192 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 | 193 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
91acbeb6 | 194 | if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { |
1d263474 DC |
195 | ret = -EINVAL; |
196 | goto free_partial_kdata; | |
d38ceaf9 | 197 | } |
91acbeb6 | 198 | |
758ac17f CK |
199 | ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata, |
200 | &uf_offset); | |
91acbeb6 CK |
201 | if (ret) |
202 | goto free_partial_kdata; | |
203 | ||
9a5e8fb1 CK |
204 | break; |
205 | ||
2b48d323 CK |
206 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
207 | break; | |
208 | ||
9a5e8fb1 | 209 | default: |
1d263474 DC |
210 | ret = -EINVAL; |
211 | goto free_partial_kdata; | |
d38ceaf9 AD |
212 | } |
213 | } | |
214 | ||
c5637837 | 215 | ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm); |
50838c8c | 216 | if (ret) |
4acabfe3 | 217 | goto free_all_kdata; |
d38ceaf9 | 218 | |
b5f5acbc CK |
219 | if (p->uf_entry.robj) |
220 | p->job->uf_addr = uf_offset; | |
d38ceaf9 | 221 | kfree(chunk_array); |
1d263474 DC |
222 | return 0; |
223 | ||
224 | free_all_kdata: | |
225 | i = p->nchunks - 1; | |
226 | free_partial_kdata: | |
227 | for (; i >= 0; i--) | |
228 | drm_free_large(p->chunks[i].kdata); | |
229 | kfree(p->chunks); | |
2a7d9bda | 230 | put_ctx: |
1d263474 DC |
231 | amdgpu_ctx_put(p->ctx); |
232 | free_chunk: | |
233 | kfree(chunk_array); | |
234 | ||
235 | return ret; | |
d38ceaf9 AD |
236 | } |
237 | ||
95844d20 MO |
238 | /* Convert microseconds to bytes. */ |
239 | static u64 us_to_bytes(struct amdgpu_device *adev, s64 us) | |
240 | { | |
241 | if (us <= 0 || !adev->mm_stats.log2_max_MBps) | |
242 | return 0; | |
243 | ||
244 | /* Since accum_us is incremented by a million per second, just | |
245 | * multiply it by the number of MB/s to get the number of bytes. | |
246 | */ | |
247 | return us << adev->mm_stats.log2_max_MBps; | |
248 | } | |
249 | ||
250 | static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes) | |
251 | { | |
252 | if (!adev->mm_stats.log2_max_MBps) | |
253 | return 0; | |
254 | ||
255 | return bytes >> adev->mm_stats.log2_max_MBps; | |
256 | } | |
257 | ||
258 | /* Returns how many bytes TTM can move right now. If no bytes can be moved, | |
259 | * it returns 0. If it returns non-zero, it's OK to move at least one buffer, | |
260 | * which means it can go over the threshold once. If that happens, the driver | |
261 | * will be in debt and no other buffer migrations can be done until that debt | |
262 | * is repaid. | |
263 | * | |
264 | * This approach allows moving a buffer of any size (it's important to allow | |
265 | * that). | |
266 | * | |
267 | * The currency is simply time in microseconds and it increases as the clock | |
268 | * ticks. The accumulated microseconds (us) are converted to bytes and | |
269 | * returned. | |
d38ceaf9 AD |
270 | */ |
271 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
272 | { | |
95844d20 MO |
273 | s64 time_us, increment_us; |
274 | u64 max_bytes; | |
275 | u64 free_vram, total_vram, used_vram; | |
d38ceaf9 | 276 | |
95844d20 MO |
277 | /* Allow a maximum of 200 accumulated ms. This is basically per-IB |
278 | * throttling. | |
d38ceaf9 | 279 | * |
95844d20 MO |
280 | * It means that in order to get full max MBps, at least 5 IBs per |
281 | * second must be submitted and not more than 200ms apart from each | |
282 | * other. | |
283 | */ | |
284 | const s64 us_upper_bound = 200000; | |
d38ceaf9 | 285 | |
95844d20 MO |
286 | if (!adev->mm_stats.log2_max_MBps) |
287 | return 0; | |
288 | ||
289 | total_vram = adev->mc.real_vram_size - adev->vram_pin_size; | |
290 | used_vram = atomic64_read(&adev->vram_usage); | |
291 | free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; | |
292 | ||
293 | spin_lock(&adev->mm_stats.lock); | |
294 | ||
295 | /* Increase the amount of accumulated us. */ | |
296 | time_us = ktime_to_us(ktime_get()); | |
297 | increment_us = time_us - adev->mm_stats.last_update_us; | |
298 | adev->mm_stats.last_update_us = time_us; | |
299 | adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us, | |
300 | us_upper_bound); | |
301 | ||
302 | /* This prevents the short period of low performance when the VRAM | |
303 | * usage is low and the driver is in debt or doesn't have enough | |
304 | * accumulated us to fill VRAM quickly. | |
d38ceaf9 | 305 | * |
95844d20 MO |
306 | * The situation can occur in these cases: |
307 | * - a lot of VRAM is freed by userspace | |
308 | * - the presence of a big buffer causes a lot of evictions | |
309 | * (solution: split buffers into smaller ones) | |
d38ceaf9 | 310 | * |
95844d20 MO |
311 | * If 128 MB or 1/8th of VRAM is free, start filling it now by setting |
312 | * accum_us to a positive number. | |
d38ceaf9 | 313 | */ |
95844d20 MO |
314 | if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) { |
315 | s64 min_us; | |
316 | ||
317 | /* Be more aggresive on dGPUs. Try to fill a portion of free | |
318 | * VRAM now. | |
319 | */ | |
320 | if (!(adev->flags & AMD_IS_APU)) | |
321 | min_us = bytes_to_us(adev, free_vram / 4); | |
322 | else | |
323 | min_us = 0; /* Reset accum_us on APUs. */ | |
324 | ||
325 | adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us); | |
326 | } | |
d38ceaf9 | 327 | |
95844d20 MO |
328 | /* This returns 0 if the driver is in debt to disallow (optional) |
329 | * buffer moves. | |
330 | */ | |
331 | max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us); | |
332 | ||
333 | spin_unlock(&adev->mm_stats.lock); | |
334 | return max_bytes; | |
335 | } | |
336 | ||
337 | /* Report how many bytes have really been moved for the last command | |
338 | * submission. This can result in a debt that can stop buffer migrations | |
339 | * temporarily. | |
340 | */ | |
341 | static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, | |
342 | u64 num_bytes) | |
343 | { | |
344 | spin_lock(&adev->mm_stats.lock); | |
345 | adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes); | |
346 | spin_unlock(&adev->mm_stats.lock); | |
d38ceaf9 AD |
347 | } |
348 | ||
14fd833e CZ |
349 | static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, |
350 | struct amdgpu_bo *bo) | |
351 | { | |
352 | u64 initial_bytes_moved; | |
353 | uint32_t domain; | |
354 | int r; | |
355 | ||
356 | if (bo->pin_count) | |
357 | return 0; | |
358 | ||
95844d20 MO |
359 | /* Don't move this buffer if we have depleted our allowance |
360 | * to move it. Don't move anything if the threshold is zero. | |
14fd833e | 361 | */ |
95844d20 | 362 | if (p->bytes_moved < p->bytes_moved_threshold) |
14fd833e CZ |
363 | domain = bo->prefered_domains; |
364 | else | |
365 | domain = bo->allowed_domains; | |
366 | ||
367 | retry: | |
368 | amdgpu_ttm_placement_from_domain(bo, domain); | |
369 | initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); | |
370 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
371 | p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - | |
372 | initial_bytes_moved; | |
373 | ||
1abdc3d7 CK |
374 | if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { |
375 | domain = bo->allowed_domains; | |
376 | goto retry; | |
14fd833e CZ |
377 | } |
378 | ||
379 | return r; | |
380 | } | |
381 | ||
662bfa61 CK |
382 | /* Last resort, try to evict something from the current working set */ |
383 | static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, | |
384 | struct amdgpu_bo_list_entry *lobj) | |
385 | { | |
386 | uint32_t domain = lobj->robj->allowed_domains; | |
387 | int r; | |
388 | ||
389 | if (!p->evictable) | |
390 | return false; | |
391 | ||
392 | for (;&p->evictable->tv.head != &p->validated; | |
393 | p->evictable = list_prev_entry(p->evictable, tv.head)) { | |
394 | ||
395 | struct amdgpu_bo_list_entry *candidate = p->evictable; | |
396 | struct amdgpu_bo *bo = candidate->robj; | |
397 | u64 initial_bytes_moved; | |
398 | uint32_t other; | |
399 | ||
400 | /* If we reached our current BO we can forget it */ | |
401 | if (candidate == lobj) | |
402 | break; | |
403 | ||
404 | other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
405 | ||
406 | /* Check if this BO is in one of the domains we need space for */ | |
407 | if (!(other & domain)) | |
408 | continue; | |
409 | ||
410 | /* Check if we can move this BO somewhere else */ | |
411 | other = bo->allowed_domains & ~domain; | |
412 | if (!other) | |
413 | continue; | |
414 | ||
415 | /* Good we can try to move this BO somewhere else */ | |
416 | amdgpu_ttm_placement_from_domain(bo, other); | |
417 | initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); | |
418 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
419 | p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - | |
420 | initial_bytes_moved; | |
421 | ||
422 | if (unlikely(r)) | |
423 | break; | |
424 | ||
425 | p->evictable = list_prev_entry(p->evictable, tv.head); | |
426 | list_move(&candidate->tv.head, &p->validated); | |
427 | ||
428 | return true; | |
429 | } | |
430 | ||
431 | return false; | |
432 | } | |
433 | ||
761c2e82 | 434 | static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, |
a5b75058 | 435 | struct list_head *validated) |
d38ceaf9 | 436 | { |
d38ceaf9 | 437 | struct amdgpu_bo_list_entry *lobj; |
d38ceaf9 AD |
438 | int r; |
439 | ||
a5b75058 | 440 | list_for_each_entry(lobj, validated, tv.head) { |
36409d12 | 441 | struct amdgpu_bo *bo = lobj->robj; |
2f568dbd | 442 | bool binding_userptr = false; |
cc325d19 | 443 | struct mm_struct *usermm; |
d38ceaf9 | 444 | |
cc325d19 CK |
445 | usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); |
446 | if (usermm && usermm != current->mm) | |
447 | return -EPERM; | |
448 | ||
2f568dbd CK |
449 | /* Check if we have user pages and nobody bound the BO already */ |
450 | if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) { | |
451 | size_t size = sizeof(struct page *); | |
452 | ||
453 | size *= bo->tbo.ttm->num_pages; | |
454 | memcpy(bo->tbo.ttm->pages, lobj->user_pages, size); | |
455 | binding_userptr = true; | |
456 | } | |
457 | ||
662bfa61 CK |
458 | if (p->evictable == lobj) |
459 | p->evictable = NULL; | |
460 | ||
461 | do { | |
462 | r = amdgpu_cs_bo_validate(p, bo); | |
463 | } while (r == -ENOMEM && amdgpu_cs_try_evict(p, lobj)); | |
14fd833e | 464 | if (r) |
36409d12 | 465 | return r; |
662bfa61 | 466 | |
14fd833e CZ |
467 | if (bo->shadow) { |
468 | r = amdgpu_cs_bo_validate(p, bo); | |
469 | if (r) | |
470 | return r; | |
d38ceaf9 | 471 | } |
2f568dbd CK |
472 | |
473 | if (binding_userptr) { | |
474 | drm_free_large(lobj->user_pages); | |
475 | lobj->user_pages = NULL; | |
476 | } | |
d38ceaf9 AD |
477 | } |
478 | return 0; | |
479 | } | |
480 | ||
2a7d9bda CK |
481 | static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, |
482 | union drm_amdgpu_cs *cs) | |
d38ceaf9 AD |
483 | { |
484 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
2f568dbd | 485 | struct amdgpu_bo_list_entry *e; |
a5b75058 | 486 | struct list_head duplicates; |
840d5144 | 487 | bool need_mmap_lock = false; |
2f568dbd | 488 | unsigned i, tries = 10; |
636ce25c | 489 | int r; |
d38ceaf9 | 490 | |
2a7d9bda CK |
491 | INIT_LIST_HEAD(&p->validated); |
492 | ||
493 | p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); | |
840d5144 | 494 | if (p->bo_list) { |
211dff55 CK |
495 | need_mmap_lock = p->bo_list->first_userptr != |
496 | p->bo_list->num_entries; | |
636ce25c | 497 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); |
840d5144 | 498 | } |
d38ceaf9 | 499 | |
3c0eea6c | 500 | INIT_LIST_HEAD(&duplicates); |
56467ebf | 501 | amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); |
d38ceaf9 | 502 | |
758ac17f | 503 | if (p->uf_entry.robj) |
91acbeb6 CK |
504 | list_add(&p->uf_entry.tv.head, &p->validated); |
505 | ||
d38ceaf9 AD |
506 | if (need_mmap_lock) |
507 | down_read(¤t->mm->mmap_sem); | |
508 | ||
2f568dbd CK |
509 | while (1) { |
510 | struct list_head need_pages; | |
511 | unsigned i; | |
512 | ||
513 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, | |
514 | &duplicates); | |
f1037950 MO |
515 | if (unlikely(r != 0)) { |
516 | DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); | |
2f568dbd | 517 | goto error_free_pages; |
f1037950 | 518 | } |
2f568dbd CK |
519 | |
520 | /* Without a BO list we don't have userptr BOs */ | |
521 | if (!p->bo_list) | |
522 | break; | |
523 | ||
524 | INIT_LIST_HEAD(&need_pages); | |
525 | for (i = p->bo_list->first_userptr; | |
526 | i < p->bo_list->num_entries; ++i) { | |
527 | ||
528 | e = &p->bo_list->array[i]; | |
529 | ||
530 | if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm, | |
531 | &e->user_invalidated) && e->user_pages) { | |
532 | ||
533 | /* We acquired a page array, but somebody | |
534 | * invalidated it. Free it an try again | |
535 | */ | |
536 | release_pages(e->user_pages, | |
537 | e->robj->tbo.ttm->num_pages, | |
538 | false); | |
539 | drm_free_large(e->user_pages); | |
540 | e->user_pages = NULL; | |
541 | } | |
542 | ||
543 | if (e->robj->tbo.ttm->state != tt_bound && | |
544 | !e->user_pages) { | |
545 | list_del(&e->tv.head); | |
546 | list_add(&e->tv.head, &need_pages); | |
547 | ||
548 | amdgpu_bo_unreserve(e->robj); | |
549 | } | |
550 | } | |
551 | ||
552 | if (list_empty(&need_pages)) | |
553 | break; | |
554 | ||
555 | /* Unreserve everything again. */ | |
556 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
557 | ||
f1037950 | 558 | /* We tried too many times, just abort */ |
2f568dbd CK |
559 | if (!--tries) { |
560 | r = -EDEADLK; | |
f1037950 | 561 | DRM_ERROR("deadlock in %s\n", __func__); |
2f568dbd CK |
562 | goto error_free_pages; |
563 | } | |
564 | ||
565 | /* Fill the page arrays for all useptrs. */ | |
566 | list_for_each_entry(e, &need_pages, tv.head) { | |
567 | struct ttm_tt *ttm = e->robj->tbo.ttm; | |
568 | ||
569 | e->user_pages = drm_calloc_large(ttm->num_pages, | |
570 | sizeof(struct page*)); | |
571 | if (!e->user_pages) { | |
572 | r = -ENOMEM; | |
f1037950 | 573 | DRM_ERROR("calloc failure in %s\n", __func__); |
2f568dbd CK |
574 | goto error_free_pages; |
575 | } | |
576 | ||
577 | r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages); | |
578 | if (r) { | |
f1037950 | 579 | DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); |
2f568dbd CK |
580 | drm_free_large(e->user_pages); |
581 | e->user_pages = NULL; | |
582 | goto error_free_pages; | |
583 | } | |
584 | } | |
585 | ||
586 | /* And try again. */ | |
587 | list_splice(&need_pages, &p->validated); | |
588 | } | |
a5b75058 | 589 | |
5a712a87 | 590 | amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates); |
56467ebf | 591 | |
f69f90a1 CK |
592 | p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); |
593 | p->bytes_moved = 0; | |
662bfa61 CK |
594 | p->evictable = list_last_entry(&p->validated, |
595 | struct amdgpu_bo_list_entry, | |
596 | tv.head); | |
f69f90a1 CK |
597 | |
598 | r = amdgpu_cs_list_validate(p, &duplicates); | |
f1037950 MO |
599 | if (r) { |
600 | DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n"); | |
a5b75058 | 601 | goto error_validate; |
f1037950 | 602 | } |
a5b75058 | 603 | |
f69f90a1 | 604 | r = amdgpu_cs_list_validate(p, &p->validated); |
f1037950 MO |
605 | if (r) { |
606 | DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n"); | |
a8480309 | 607 | goto error_validate; |
f1037950 | 608 | } |
a8480309 | 609 | |
95844d20 MO |
610 | amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved); |
611 | ||
5a712a87 CK |
612 | fpriv->vm.last_eviction_counter = |
613 | atomic64_read(&p->adev->num_evictions); | |
614 | ||
a8480309 | 615 | if (p->bo_list) { |
d88bf583 CK |
616 | struct amdgpu_bo *gds = p->bo_list->gds_obj; |
617 | struct amdgpu_bo *gws = p->bo_list->gws_obj; | |
618 | struct amdgpu_bo *oa = p->bo_list->oa_obj; | |
a8480309 CK |
619 | struct amdgpu_vm *vm = &fpriv->vm; |
620 | unsigned i; | |
621 | ||
622 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
623 | struct amdgpu_bo *bo = p->bo_list->array[i].robj; | |
624 | ||
625 | p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); | |
626 | } | |
d88bf583 CK |
627 | |
628 | if (gds) { | |
629 | p->job->gds_base = amdgpu_bo_gpu_offset(gds); | |
630 | p->job->gds_size = amdgpu_bo_size(gds); | |
631 | } | |
632 | if (gws) { | |
633 | p->job->gws_base = amdgpu_bo_gpu_offset(gws); | |
634 | p->job->gws_size = amdgpu_bo_size(gws); | |
635 | } | |
636 | if (oa) { | |
637 | p->job->oa_base = amdgpu_bo_gpu_offset(oa); | |
638 | p->job->oa_size = amdgpu_bo_size(oa); | |
639 | } | |
a8480309 | 640 | } |
a5b75058 | 641 | |
c855e250 CK |
642 | if (!r && p->uf_entry.robj) { |
643 | struct amdgpu_bo *uf = p->uf_entry.robj; | |
644 | ||
645 | r = amdgpu_ttm_bind(uf->tbo.ttm, &uf->tbo.mem); | |
646 | p->job->uf_addr += amdgpu_bo_gpu_offset(uf); | |
647 | } | |
b5f5acbc | 648 | |
a5b75058 | 649 | error_validate: |
eceb8a15 CK |
650 | if (r) { |
651 | amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); | |
a5b75058 | 652 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); |
eceb8a15 | 653 | } |
d38ceaf9 | 654 | |
2f568dbd CK |
655 | error_free_pages: |
656 | ||
d38ceaf9 AD |
657 | if (need_mmap_lock) |
658 | up_read(¤t->mm->mmap_sem); | |
659 | ||
2f568dbd CK |
660 | if (p->bo_list) { |
661 | for (i = p->bo_list->first_userptr; | |
662 | i < p->bo_list->num_entries; ++i) { | |
663 | e = &p->bo_list->array[i]; | |
664 | ||
665 | if (!e->user_pages) | |
666 | continue; | |
667 | ||
668 | release_pages(e->user_pages, | |
669 | e->robj->tbo.ttm->num_pages, | |
670 | false); | |
671 | drm_free_large(e->user_pages); | |
672 | } | |
673 | } | |
674 | ||
d38ceaf9 AD |
675 | return r; |
676 | } | |
677 | ||
678 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
679 | { | |
680 | struct amdgpu_bo_list_entry *e; | |
681 | int r; | |
682 | ||
683 | list_for_each_entry(e, &p->validated, tv.head) { | |
684 | struct reservation_object *resv = e->robj->tbo.resv; | |
e86f9cee | 685 | r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp); |
d38ceaf9 AD |
686 | |
687 | if (r) | |
688 | return r; | |
689 | } | |
690 | return 0; | |
691 | } | |
692 | ||
984810fc CK |
693 | /** |
694 | * cs_parser_fini() - clean parser states | |
695 | * @parser: parser structure holding parsing context. | |
696 | * @error: error number | |
697 | * | |
698 | * If error is set than unvalidate buffer, otherwise just free memory | |
699 | * used by parsing context. | |
700 | **/ | |
701 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
049fc527 | 702 | { |
eceb8a15 | 703 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; |
984810fc CK |
704 | unsigned i; |
705 | ||
d38ceaf9 | 706 | if (!error) { |
28b8d66e NH |
707 | amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); |
708 | ||
d38ceaf9 | 709 | ttm_eu_fence_buffer_objects(&parser->ticket, |
984810fc CK |
710 | &parser->validated, |
711 | parser->fence); | |
d38ceaf9 AD |
712 | } else if (backoff) { |
713 | ttm_eu_backoff_reservation(&parser->ticket, | |
714 | &parser->validated); | |
715 | } | |
984810fc | 716 | fence_put(parser->fence); |
7e52a81c | 717 | |
3cb485f3 CK |
718 | if (parser->ctx) |
719 | amdgpu_ctx_put(parser->ctx); | |
a3348bb8 CZ |
720 | if (parser->bo_list) |
721 | amdgpu_bo_list_put(parser->bo_list); | |
722 | ||
d38ceaf9 AD |
723 | for (i = 0; i < parser->nchunks; i++) |
724 | drm_free_large(parser->chunks[i].kdata); | |
725 | kfree(parser->chunks); | |
50838c8c CK |
726 | if (parser->job) |
727 | amdgpu_job_free(parser->job); | |
91acbeb6 | 728 | amdgpu_bo_unref(&parser->uf_entry.robj); |
d38ceaf9 AD |
729 | } |
730 | ||
731 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, | |
732 | struct amdgpu_vm *vm) | |
733 | { | |
734 | struct amdgpu_device *adev = p->adev; | |
735 | struct amdgpu_bo_va *bo_va; | |
736 | struct amdgpu_bo *bo; | |
737 | int i, r; | |
738 | ||
739 | r = amdgpu_vm_update_page_directory(adev, vm); | |
740 | if (r) | |
741 | return r; | |
742 | ||
e86f9cee | 743 | r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence); |
05906dec BN |
744 | if (r) |
745 | return r; | |
746 | ||
d38ceaf9 AD |
747 | r = amdgpu_vm_clear_freed(adev, vm); |
748 | if (r) | |
749 | return r; | |
750 | ||
751 | if (p->bo_list) { | |
752 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
753 | struct fence *f; |
754 | ||
d38ceaf9 AD |
755 | /* ignore duplicates */ |
756 | bo = p->bo_list->array[i].robj; | |
757 | if (!bo) | |
758 | continue; | |
759 | ||
760 | bo_va = p->bo_list->array[i].bo_va; | |
761 | if (bo_va == NULL) | |
762 | continue; | |
763 | ||
99e124f4 | 764 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
d38ceaf9 AD |
765 | if (r) |
766 | return r; | |
767 | ||
bb1e38a4 | 768 | f = bo_va->last_pt_update; |
e86f9cee | 769 | r = amdgpu_sync_fence(adev, &p->job->sync, f); |
91e1a520 CK |
770 | if (r) |
771 | return r; | |
d38ceaf9 | 772 | } |
b495bd3a CK |
773 | |
774 | } | |
775 | ||
e86f9cee | 776 | r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync); |
b495bd3a CK |
777 | |
778 | if (amdgpu_vm_debug && p->bo_list) { | |
779 | /* Invalidate all BOs to test for userspace bugs */ | |
780 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
781 | /* ignore duplicates */ | |
782 | bo = p->bo_list->array[i].robj; | |
783 | if (!bo) | |
784 | continue; | |
785 | ||
786 | amdgpu_vm_bo_invalidate(adev, bo); | |
787 | } | |
d38ceaf9 AD |
788 | } |
789 | ||
b495bd3a | 790 | return r; |
d38ceaf9 AD |
791 | } |
792 | ||
793 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
b07c60c0 | 794 | struct amdgpu_cs_parser *p) |
d38ceaf9 | 795 | { |
b07c60c0 | 796 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
d38ceaf9 | 797 | struct amdgpu_vm *vm = &fpriv->vm; |
b07c60c0 | 798 | struct amdgpu_ring *ring = p->job->ring; |
d38ceaf9 AD |
799 | int i, r; |
800 | ||
d38ceaf9 | 801 | /* Only for UVD/VCE VM emulation */ |
b07c60c0 | 802 | if (ring->funcs->parse_cs) { |
9a79588c | 803 | p->job->vm = NULL; |
b07c60c0 CK |
804 | for (i = 0; i < p->job->num_ibs; i++) { |
805 | r = amdgpu_ring_parse_cs(ring, p, i); | |
d38ceaf9 AD |
806 | if (r) |
807 | return r; | |
808 | } | |
9a79588c CK |
809 | } else { |
810 | p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); | |
281d144d | 811 | |
9a79588c CK |
812 | r = amdgpu_bo_vm_update_pte(p, vm); |
813 | if (r) | |
814 | return r; | |
815 | } | |
d38ceaf9 | 816 | |
9a79588c | 817 | return amdgpu_cs_sync_rings(p); |
d38ceaf9 AD |
818 | } |
819 | ||
820 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
821 | { | |
822 | if (r == -EDEADLK) { | |
823 | r = amdgpu_gpu_reset(adev); | |
824 | if (!r) | |
825 | r = -EAGAIN; | |
826 | } | |
827 | return r; | |
828 | } | |
829 | ||
830 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
831 | struct amdgpu_cs_parser *parser) | |
832 | { | |
833 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
834 | struct amdgpu_vm *vm = &fpriv->vm; | |
835 | int i, j; | |
836 | int r; | |
837 | ||
50838c8c | 838 | for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { |
d38ceaf9 AD |
839 | struct amdgpu_cs_chunk *chunk; |
840 | struct amdgpu_ib *ib; | |
841 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 842 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
843 | |
844 | chunk = &parser->chunks[i]; | |
50838c8c | 845 | ib = &parser->job->ibs[j]; |
d38ceaf9 AD |
846 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; |
847 | ||
848 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
849 | continue; | |
850 | ||
d38ceaf9 AD |
851 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
852 | chunk_ib->ip_instance, chunk_ib->ring, | |
853 | &ring); | |
3ccec53c | 854 | if (r) |
d38ceaf9 | 855 | return r; |
d38ceaf9 | 856 | |
753ad49c ML |
857 | if (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) { |
858 | parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT; | |
859 | if (!parser->ctx->preamble_presented) { | |
860 | parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; | |
861 | parser->ctx->preamble_presented = true; | |
862 | } | |
863 | } | |
864 | ||
b07c60c0 CK |
865 | if (parser->job->ring && parser->job->ring != ring) |
866 | return -EINVAL; | |
867 | ||
868 | parser->job->ring = ring; | |
869 | ||
d38ceaf9 | 870 | if (ring->funcs->parse_cs) { |
4802ce11 | 871 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 872 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
873 | uint64_t offset; |
874 | uint8_t *kptr; | |
3ccec53c | 875 | |
4802ce11 CK |
876 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
877 | &aobj); | |
3ccec53c MO |
878 | if (!aobj) { |
879 | DRM_ERROR("IB va_start is invalid\n"); | |
880 | return -EINVAL; | |
d38ceaf9 AD |
881 | } |
882 | ||
4802ce11 CK |
883 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
884 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
885 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
886 | return -EINVAL; | |
887 | } | |
888 | ||
3ccec53c | 889 | /* the IB should be reserved at this point */ |
4802ce11 | 890 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 891 | if (r) { |
d38ceaf9 AD |
892 | return r; |
893 | } | |
894 | ||
4802ce11 CK |
895 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
896 | kptr += chunk_ib->va_start - offset; | |
897 | ||
b07c60c0 | 898 | r = amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib); |
d38ceaf9 AD |
899 | if (r) { |
900 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
901 | return r; |
902 | } | |
903 | ||
904 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
905 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 | 906 | } else { |
b07c60c0 | 907 | r = amdgpu_ib_get(adev, vm, 0, ib); |
d38ceaf9 AD |
908 | if (r) { |
909 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
910 | return r; |
911 | } | |
912 | ||
913 | ib->gpu_addr = chunk_ib->va_start; | |
914 | } | |
d38ceaf9 | 915 | |
3ccec53c | 916 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 917 | ib->flags = chunk_ib->flags; |
d38ceaf9 AD |
918 | j++; |
919 | } | |
920 | ||
758ac17f | 921 | /* UVD & VCE fw doesn't support user fences */ |
b5f5acbc | 922 | if (parser->job->uf_addr && ( |
758ac17f CK |
923 | parser->job->ring->type == AMDGPU_RING_TYPE_UVD || |
924 | parser->job->ring->type == AMDGPU_RING_TYPE_VCE)) | |
925 | return -EINVAL; | |
d38ceaf9 AD |
926 | |
927 | return 0; | |
928 | } | |
929 | ||
2b48d323 CK |
930 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
931 | struct amdgpu_cs_parser *p) | |
932 | { | |
76a1ea61 | 933 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
934 | int i, j, r; |
935 | ||
2b48d323 CK |
936 | for (i = 0; i < p->nchunks; ++i) { |
937 | struct drm_amdgpu_cs_chunk_dep *deps; | |
938 | struct amdgpu_cs_chunk *chunk; | |
939 | unsigned num_deps; | |
940 | ||
941 | chunk = &p->chunks[i]; | |
942 | ||
943 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
944 | continue; | |
945 | ||
946 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
947 | num_deps = chunk->length_dw * 4 / | |
948 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
949 | ||
950 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 951 | struct amdgpu_ring *ring; |
76a1ea61 | 952 | struct amdgpu_ctx *ctx; |
21c16bf6 | 953 | struct fence *fence; |
2b48d323 CK |
954 | |
955 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
956 | deps[j].ip_instance, | |
957 | deps[j].ring, &ring); | |
958 | if (r) | |
959 | return r; | |
960 | ||
76a1ea61 CK |
961 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
962 | if (ctx == NULL) | |
963 | return -EINVAL; | |
964 | ||
21c16bf6 CK |
965 | fence = amdgpu_ctx_get_fence(ctx, ring, |
966 | deps[j].handle); | |
967 | if (IS_ERR(fence)) { | |
968 | r = PTR_ERR(fence); | |
76a1ea61 | 969 | amdgpu_ctx_put(ctx); |
2b48d323 | 970 | return r; |
91e1a520 | 971 | |
21c16bf6 | 972 | } else if (fence) { |
e86f9cee CK |
973 | r = amdgpu_sync_fence(adev, &p->job->sync, |
974 | fence); | |
21c16bf6 CK |
975 | fence_put(fence); |
976 | amdgpu_ctx_put(ctx); | |
977 | if (r) | |
978 | return r; | |
979 | } | |
2b48d323 CK |
980 | } |
981 | } | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
cd75dc68 CK |
986 | static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, |
987 | union drm_amdgpu_cs *cs) | |
988 | { | |
b07c60c0 | 989 | struct amdgpu_ring *ring = p->job->ring; |
92f25098 | 990 | struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; |
cd75dc68 | 991 | struct amdgpu_job *job; |
e686941a | 992 | int r; |
cd75dc68 | 993 | |
50838c8c CK |
994 | job = p->job; |
995 | p->job = NULL; | |
cd75dc68 | 996 | |
595a9cd6 | 997 | r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp); |
e686941a | 998 | if (r) { |
d71518b5 | 999 | amdgpu_job_free(job); |
e686941a | 1000 | return r; |
cd75dc68 CK |
1001 | } |
1002 | ||
e686941a | 1003 | job->owner = p->filp; |
3aecd24c | 1004 | job->fence_ctx = entity->fence_context; |
595a9cd6 CK |
1005 | p->fence = fence_get(&job->base.s_fence->finished); |
1006 | cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence); | |
758ac17f | 1007 | job->uf_sequence = cs->out.handle; |
a5fb4ec2 | 1008 | amdgpu_job_free_resources(job); |
cd75dc68 CK |
1009 | |
1010 | trace_amdgpu_cs_ioctl(job); | |
1011 | amd_sched_entity_push_job(&job->base); | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
049fc527 CZ |
1016 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
1017 | { | |
1018 | struct amdgpu_device *adev = dev->dev_private; | |
1019 | union drm_amdgpu_cs *cs = data; | |
7e52a81c | 1020 | struct amdgpu_cs_parser parser = {}; |
26a6980c CK |
1021 | bool reserved_buffers = false; |
1022 | int i, r; | |
049fc527 | 1023 | |
0c418f10 | 1024 | if (!adev->accel_working) |
049fc527 | 1025 | return -EBUSY; |
2b48d323 | 1026 | |
7e52a81c CK |
1027 | parser.adev = adev; |
1028 | parser.filp = filp; | |
1029 | ||
1030 | r = amdgpu_cs_parser_init(&parser, data); | |
d38ceaf9 | 1031 | if (r) { |
049fc527 | 1032 | DRM_ERROR("Failed to initialize parser !\n"); |
7e52a81c | 1033 | amdgpu_cs_parser_fini(&parser, r, false); |
d38ceaf9 AD |
1034 | r = amdgpu_cs_handle_lockup(adev, r); |
1035 | return r; | |
1036 | } | |
2a7d9bda | 1037 | r = amdgpu_cs_parser_bos(&parser, data); |
26a6980c CK |
1038 | if (r == -ENOMEM) |
1039 | DRM_ERROR("Not enough memory for command submission!\n"); | |
1040 | else if (r && r != -ERESTARTSYS) | |
1041 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
1042 | else if (!r) { | |
1043 | reserved_buffers = true; | |
7e52a81c | 1044 | r = amdgpu_cs_ib_fill(adev, &parser); |
26a6980c CK |
1045 | } |
1046 | ||
1047 | if (!r) { | |
7e52a81c | 1048 | r = amdgpu_cs_dependencies(adev, &parser); |
26a6980c CK |
1049 | if (r) |
1050 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
1051 | } | |
1052 | ||
1053 | if (r) | |
1054 | goto out; | |
1055 | ||
50838c8c | 1056 | for (i = 0; i < parser.job->num_ibs; i++) |
7e52a81c | 1057 | trace_amdgpu_cs(&parser, i); |
26a6980c | 1058 | |
7e52a81c | 1059 | r = amdgpu_cs_ib_vm_chunk(adev, &parser); |
4fe63117 CZ |
1060 | if (r) |
1061 | goto out; | |
1062 | ||
4acabfe3 | 1063 | r = amdgpu_cs_submit(&parser, cs); |
d38ceaf9 | 1064 | |
d38ceaf9 | 1065 | out: |
7e52a81c | 1066 | amdgpu_cs_parser_fini(&parser, r, reserved_buffers); |
d38ceaf9 AD |
1067 | r = amdgpu_cs_handle_lockup(adev, r); |
1068 | return r; | |
1069 | } | |
1070 | ||
1071 | /** | |
1072 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
1073 | * | |
1074 | * @dev: drm device | |
1075 | * @data: data from userspace | |
1076 | * @filp: file private | |
1077 | * | |
1078 | * Wait for the command submission identified by handle to finish. | |
1079 | */ | |
1080 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
1081 | struct drm_file *filp) | |
1082 | { | |
1083 | union drm_amdgpu_wait_cs *wait = data; | |
1084 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 1085 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 1086 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 1087 | struct amdgpu_ctx *ctx; |
21c16bf6 | 1088 | struct fence *fence; |
d38ceaf9 AD |
1089 | long r; |
1090 | ||
21c16bf6 CK |
1091 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
1092 | wait->in.ring, &ring); | |
1093 | if (r) | |
1094 | return r; | |
1095 | ||
66b3cf2a JZ |
1096 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
1097 | if (ctx == NULL) | |
1098 | return -EINVAL; | |
d38ceaf9 | 1099 | |
4b559c90 CZ |
1100 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
1101 | if (IS_ERR(fence)) | |
1102 | r = PTR_ERR(fence); | |
1103 | else if (fence) { | |
1104 | r = fence_wait_timeout(fence, true, timeout); | |
1105 | fence_put(fence); | |
1106 | } else | |
1107 | r = 1; | |
049fc527 | 1108 | |
66b3cf2a | 1109 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
1110 | if (r < 0) |
1111 | return r; | |
1112 | ||
1113 | memset(wait, 0, sizeof(*wait)); | |
1114 | wait->out.status = (r == 0); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | /** | |
1120 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
1121 | * | |
1122 | * @parser: command submission parser context | |
1123 | * @addr: VM address | |
1124 | * @bo: resulting BO of the mapping found | |
1125 | * | |
1126 | * Search the buffer objects in the command submission context for a certain | |
1127 | * virtual memory address. Returns allocation structure when found, NULL | |
1128 | * otherwise. | |
1129 | */ | |
1130 | struct amdgpu_bo_va_mapping * | |
1131 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
1132 | uint64_t addr, struct amdgpu_bo **bo) | |
1133 | { | |
d38ceaf9 | 1134 | struct amdgpu_bo_va_mapping *mapping; |
15486fd2 CK |
1135 | unsigned i; |
1136 | ||
1137 | if (!parser->bo_list) | |
1138 | return NULL; | |
d38ceaf9 AD |
1139 | |
1140 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
1141 | ||
15486fd2 CK |
1142 | for (i = 0; i < parser->bo_list->num_entries; i++) { |
1143 | struct amdgpu_bo_list_entry *lobj; | |
1144 | ||
1145 | lobj = &parser->bo_list->array[i]; | |
1146 | if (!lobj->bo_va) | |
d38ceaf9 AD |
1147 | continue; |
1148 | ||
15486fd2 | 1149 | list_for_each_entry(mapping, &lobj->bo_va->valids, list) { |
7fc11959 CK |
1150 | if (mapping->it.start > addr || |
1151 | addr > mapping->it.last) | |
1152 | continue; | |
1153 | ||
15486fd2 | 1154 | *bo = lobj->bo_va->bo; |
7fc11959 CK |
1155 | return mapping; |
1156 | } | |
1157 | ||
15486fd2 | 1158 | list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { |
d38ceaf9 AD |
1159 | if (mapping->it.start > addr || |
1160 | addr > mapping->it.last) | |
1161 | continue; | |
1162 | ||
15486fd2 | 1163 | *bo = lobj->bo_va->bo; |
d38ceaf9 AD |
1164 | return mapping; |
1165 | } | |
1166 | } | |
1167 | ||
1168 | return NULL; | |
1169 | } | |
c855e250 CK |
1170 | |
1171 | /** | |
1172 | * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM | |
1173 | * | |
1174 | * @parser: command submission parser context | |
1175 | * | |
1176 | * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM. | |
1177 | */ | |
1178 | int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser) | |
1179 | { | |
1180 | unsigned i; | |
1181 | int r; | |
1182 | ||
1183 | if (!parser->bo_list) | |
1184 | return 0; | |
1185 | ||
1186 | for (i = 0; i < parser->bo_list->num_entries; i++) { | |
1187 | struct amdgpu_bo *bo = parser->bo_list->array[i].robj; | |
1188 | ||
1189 | r = amdgpu_ttm_bind(bo->tbo.ttm, &bo->tbo.mem); | |
1190 | if (unlikely(r)) | |
1191 | return r; | |
1192 | } | |
1193 | ||
1194 | return 0; | |
1195 | } |