Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
27 | #include <linux/list_sort.h> | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
d38ceaf9 AD |
33 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, |
34 | u32 ip_instance, u32 ring, | |
35 | struct amdgpu_ring **out_ring) | |
36 | { | |
37 | /* Right now all IPs have only one instance - multiple rings. */ | |
38 | if (ip_instance != 0) { | |
39 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
40 | return -EINVAL; | |
41 | } | |
42 | ||
43 | switch (ip_type) { | |
44 | default: | |
45 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
46 | return -EINVAL; | |
47 | case AMDGPU_HW_IP_GFX: | |
48 | if (ring < adev->gfx.num_gfx_rings) { | |
49 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
50 | } else { | |
51 | DRM_ERROR("only %d gfx rings are supported now\n", | |
52 | adev->gfx.num_gfx_rings); | |
53 | return -EINVAL; | |
54 | } | |
55 | break; | |
56 | case AMDGPU_HW_IP_COMPUTE: | |
57 | if (ring < adev->gfx.num_compute_rings) { | |
58 | *out_ring = &adev->gfx.compute_ring[ring]; | |
59 | } else { | |
60 | DRM_ERROR("only %d compute rings are supported now\n", | |
61 | adev->gfx.num_compute_rings); | |
62 | return -EINVAL; | |
63 | } | |
64 | break; | |
65 | case AMDGPU_HW_IP_DMA: | |
c113ea1c AD |
66 | if (ring < adev->sdma.num_instances) { |
67 | *out_ring = &adev->sdma.instance[ring].ring; | |
d38ceaf9 | 68 | } else { |
c113ea1c AD |
69 | DRM_ERROR("only %d SDMA rings are supported\n", |
70 | adev->sdma.num_instances); | |
d38ceaf9 AD |
71 | return -EINVAL; |
72 | } | |
73 | break; | |
74 | case AMDGPU_HW_IP_UVD: | |
75 | *out_ring = &adev->uvd.ring; | |
76 | break; | |
77 | case AMDGPU_HW_IP_VCE: | |
78 | if (ring < 2){ | |
79 | *out_ring = &adev->vce.ring[ring]; | |
80 | } else { | |
81 | DRM_ERROR("only two VCE rings are supported\n"); | |
82 | return -EINVAL; | |
83 | } | |
84 | break; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
91acbeb6 CK |
89 | static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, |
90 | struct drm_amdgpu_cs_chunk_fence *fence_data) | |
91 | { | |
92 | struct drm_gem_object *gobj; | |
93 | uint32_t handle; | |
94 | ||
95 | handle = fence_data->handle; | |
96 | gobj = drm_gem_object_lookup(p->adev->ddev, p->filp, | |
97 | fence_data->handle); | |
98 | if (gobj == NULL) | |
99 | return -EINVAL; | |
100 | ||
101 | p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); | |
102 | p->uf.offset = fence_data->offset; | |
103 | ||
104 | if (amdgpu_ttm_tt_has_userptr(p->uf.bo->tbo.ttm)) { | |
105 | drm_gem_object_unreference_unlocked(gobj); | |
106 | return -EINVAL; | |
107 | } | |
108 | ||
109 | p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo); | |
91acbeb6 CK |
110 | p->uf_entry.priority = 0; |
111 | p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; | |
112 | p->uf_entry.tv.shared = true; | |
113 | ||
114 | drm_gem_object_unreference_unlocked(gobj); | |
115 | return 0; | |
116 | } | |
117 | ||
d38ceaf9 AD |
118 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
119 | { | |
120 | union drm_amdgpu_cs *cs = data; | |
121 | uint64_t *chunk_array_user; | |
1d263474 | 122 | uint64_t *chunk_array; |
d38ceaf9 | 123 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
54313503 DC |
124 | unsigned size; |
125 | int i; | |
1d263474 | 126 | int ret; |
d38ceaf9 | 127 | |
1d263474 DC |
128 | if (cs->in.num_chunks == 0) |
129 | return 0; | |
130 | ||
131 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
132 | if (!chunk_array) | |
133 | return -ENOMEM; | |
d38ceaf9 | 134 | |
3cb485f3 CK |
135 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
136 | if (!p->ctx) { | |
1d263474 DC |
137 | ret = -EINVAL; |
138 | goto free_chunk; | |
3cb485f3 | 139 | } |
1d263474 | 140 | |
d38ceaf9 | 141 | /* get chunks */ |
028423b0 | 142 | chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); |
d38ceaf9 AD |
143 | if (copy_from_user(chunk_array, chunk_array_user, |
144 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
1d263474 | 145 | ret = -EFAULT; |
2a7d9bda | 146 | goto put_ctx; |
d38ceaf9 AD |
147 | } |
148 | ||
149 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 150 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 | 151 | GFP_KERNEL); |
1d263474 DC |
152 | if (!p->chunks) { |
153 | ret = -ENOMEM; | |
2a7d9bda | 154 | goto put_ctx; |
d38ceaf9 AD |
155 | } |
156 | ||
157 | for (i = 0; i < p->nchunks; i++) { | |
158 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
159 | struct drm_amdgpu_cs_chunk user_chunk; | |
160 | uint32_t __user *cdata; | |
161 | ||
028423b0 | 162 | chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; |
d38ceaf9 AD |
163 | if (copy_from_user(&user_chunk, chunk_ptr, |
164 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
1d263474 DC |
165 | ret = -EFAULT; |
166 | i--; | |
167 | goto free_partial_kdata; | |
d38ceaf9 AD |
168 | } |
169 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
170 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
171 | |
172 | size = p->chunks[i].length_dw; | |
028423b0 | 173 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
d38ceaf9 AD |
174 | |
175 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
176 | if (p->chunks[i].kdata == NULL) { | |
1d263474 DC |
177 | ret = -ENOMEM; |
178 | i--; | |
179 | goto free_partial_kdata; | |
d38ceaf9 AD |
180 | } |
181 | size *= sizeof(uint32_t); | |
182 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
1d263474 DC |
183 | ret = -EFAULT; |
184 | goto free_partial_kdata; | |
d38ceaf9 AD |
185 | } |
186 | ||
9a5e8fb1 CK |
187 | switch (p->chunks[i].chunk_id) { |
188 | case AMDGPU_CHUNK_ID_IB: | |
189 | p->num_ibs++; | |
190 | break; | |
191 | ||
192 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 | 193 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
91acbeb6 | 194 | if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { |
1d263474 DC |
195 | ret = -EINVAL; |
196 | goto free_partial_kdata; | |
d38ceaf9 | 197 | } |
91acbeb6 CK |
198 | |
199 | ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata); | |
200 | if (ret) | |
201 | goto free_partial_kdata; | |
202 | ||
9a5e8fb1 CK |
203 | break; |
204 | ||
2b48d323 CK |
205 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
206 | break; | |
207 | ||
9a5e8fb1 | 208 | default: |
1d263474 DC |
209 | ret = -EINVAL; |
210 | goto free_partial_kdata; | |
d38ceaf9 AD |
211 | } |
212 | } | |
213 | ||
e60b344f | 214 | |
b203dd95 | 215 | p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); |
1d263474 DC |
216 | if (!p->ibs) { |
217 | ret = -ENOMEM; | |
218 | goto free_all_kdata; | |
219 | } | |
d38ceaf9 | 220 | |
d38ceaf9 | 221 | kfree(chunk_array); |
1d263474 DC |
222 | return 0; |
223 | ||
224 | free_all_kdata: | |
225 | i = p->nchunks - 1; | |
226 | free_partial_kdata: | |
227 | for (; i >= 0; i--) | |
228 | drm_free_large(p->chunks[i].kdata); | |
229 | kfree(p->chunks); | |
2a7d9bda | 230 | put_ctx: |
1d263474 DC |
231 | amdgpu_ctx_put(p->ctx); |
232 | free_chunk: | |
233 | kfree(chunk_array); | |
234 | ||
235 | return ret; | |
d38ceaf9 AD |
236 | } |
237 | ||
238 | /* Returns how many bytes TTM can move per IB. | |
239 | */ | |
240 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
241 | { | |
242 | u64 real_vram_size = adev->mc.real_vram_size; | |
243 | u64 vram_usage = atomic64_read(&adev->vram_usage); | |
244 | ||
245 | /* This function is based on the current VRAM usage. | |
246 | * | |
247 | * - If all of VRAM is free, allow relocating the number of bytes that | |
248 | * is equal to 1/4 of the size of VRAM for this IB. | |
249 | ||
250 | * - If more than one half of VRAM is occupied, only allow relocating | |
251 | * 1 MB of data for this IB. | |
252 | * | |
253 | * - From 0 to one half of used VRAM, the threshold decreases | |
254 | * linearly. | |
255 | * __________________ | |
256 | * 1/4 of -|\ | | |
257 | * VRAM | \ | | |
258 | * | \ | | |
259 | * | \ | | |
260 | * | \ | | |
261 | * | \ | | |
262 | * | \ | | |
263 | * | \________|1 MB | |
264 | * |----------------| | |
265 | * VRAM 0 % 100 % | |
266 | * used used | |
267 | * | |
268 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
269 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
270 | * can be moved as long as the threshold isn't crossed before | |
271 | * the relocation takes place. We don't want to disable buffer | |
272 | * relocations completely. | |
273 | * | |
274 | * The idea is that buffers should be placed in VRAM at creation time | |
275 | * and TTM should only do a minimum number of relocations during | |
276 | * command submission. In practice, you need to submit at least | |
277 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
278 | * | |
279 | * Also, things can get pretty crazy under memory pressure and actual | |
280 | * VRAM usage can change a lot, so playing safe even at 50% does | |
281 | * consistently increase performance. | |
282 | */ | |
283 | ||
284 | u64 half_vram = real_vram_size >> 1; | |
285 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
286 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
287 | return max(bytes_moved_threshold, 1024*1024ull); | |
288 | } | |
289 | ||
f69f90a1 | 290 | int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, |
a5b75058 | 291 | struct list_head *validated) |
d38ceaf9 | 292 | { |
f69f90a1 CK |
293 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
294 | struct amdgpu_vm *vm = &fpriv->vm; | |
d38ceaf9 | 295 | struct amdgpu_bo_list_entry *lobj; |
f69f90a1 | 296 | u64 initial_bytes_moved; |
d38ceaf9 AD |
297 | int r; |
298 | ||
a5b75058 | 299 | list_for_each_entry(lobj, validated, tv.head) { |
36409d12 CK |
300 | struct amdgpu_bo *bo = lobj->robj; |
301 | uint32_t domain; | |
d38ceaf9 | 302 | |
36409d12 CK |
303 | lobj->bo_va = amdgpu_vm_bo_find(vm, bo); |
304 | if (bo->pin_count) | |
305 | continue; | |
306 | ||
307 | /* Avoid moving this one if we have moved too many buffers | |
308 | * for this IB already. | |
309 | * | |
310 | * Note that this allows moving at least one buffer of | |
311 | * any size, because it doesn't take the current "bo" | |
312 | * into account. We don't want to disallow buffer moves | |
313 | * completely. | |
314 | */ | |
315 | if (p->bytes_moved <= p->bytes_moved_threshold) | |
1ea863fd | 316 | domain = bo->prefered_domains; |
36409d12 | 317 | else |
1ea863fd | 318 | domain = bo->allowed_domains; |
36409d12 CK |
319 | |
320 | retry: | |
321 | amdgpu_ttm_placement_from_domain(bo, domain); | |
322 | initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); | |
323 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
324 | p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - | |
325 | initial_bytes_moved; | |
326 | ||
327 | if (unlikely(r)) { | |
1ea863fd CK |
328 | if (r != -ERESTARTSYS && domain != bo->allowed_domains) { |
329 | domain = bo->allowed_domains; | |
36409d12 | 330 | goto retry; |
d38ceaf9 | 331 | } |
36409d12 | 332 | return r; |
d38ceaf9 | 333 | } |
d38ceaf9 AD |
334 | } |
335 | return 0; | |
336 | } | |
337 | ||
2a7d9bda CK |
338 | static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, |
339 | union drm_amdgpu_cs *cs) | |
d38ceaf9 AD |
340 | { |
341 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
a5b75058 | 342 | struct list_head duplicates; |
840d5144 | 343 | bool need_mmap_lock = false; |
636ce25c | 344 | int r; |
d38ceaf9 | 345 | |
2a7d9bda CK |
346 | INIT_LIST_HEAD(&p->validated); |
347 | ||
348 | p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); | |
840d5144 | 349 | if (p->bo_list) { |
350 | need_mmap_lock = p->bo_list->has_userptr; | |
636ce25c | 351 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); |
840d5144 | 352 | } |
d38ceaf9 | 353 | |
3c0eea6c | 354 | INIT_LIST_HEAD(&duplicates); |
56467ebf | 355 | amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); |
d38ceaf9 | 356 | |
91acbeb6 CK |
357 | if (p->uf.bo) |
358 | list_add(&p->uf_entry.tv.head, &p->validated); | |
359 | ||
d38ceaf9 AD |
360 | if (need_mmap_lock) |
361 | down_read(¤t->mm->mmap_sem); | |
362 | ||
a5b75058 CK |
363 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); |
364 | if (unlikely(r != 0)) | |
365 | goto error_reserve; | |
366 | ||
ee1782c3 | 367 | amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates); |
56467ebf | 368 | |
f69f90a1 CK |
369 | p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); |
370 | p->bytes_moved = 0; | |
371 | ||
372 | r = amdgpu_cs_list_validate(p, &duplicates); | |
a5b75058 CK |
373 | if (r) |
374 | goto error_validate; | |
375 | ||
f69f90a1 | 376 | r = amdgpu_cs_list_validate(p, &p->validated); |
a5b75058 CK |
377 | |
378 | error_validate: | |
eceb8a15 CK |
379 | if (r) { |
380 | amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); | |
a5b75058 | 381 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); |
eceb8a15 | 382 | } |
d38ceaf9 | 383 | |
a5b75058 | 384 | error_reserve: |
d38ceaf9 AD |
385 | if (need_mmap_lock) |
386 | up_read(¤t->mm->mmap_sem); | |
387 | ||
388 | return r; | |
389 | } | |
390 | ||
391 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
392 | { | |
393 | struct amdgpu_bo_list_entry *e; | |
394 | int r; | |
395 | ||
396 | list_for_each_entry(e, &p->validated, tv.head) { | |
397 | struct reservation_object *resv = e->robj->tbo.resv; | |
398 | r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); | |
399 | ||
400 | if (r) | |
401 | return r; | |
402 | } | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static int cmp_size_smaller_first(void *priv, struct list_head *a, | |
407 | struct list_head *b) | |
408 | { | |
409 | struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); | |
410 | struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); | |
411 | ||
412 | /* Sort A before B if A is smaller. */ | |
413 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; | |
414 | } | |
415 | ||
984810fc CK |
416 | /** |
417 | * cs_parser_fini() - clean parser states | |
418 | * @parser: parser structure holding parsing context. | |
419 | * @error: error number | |
420 | * | |
421 | * If error is set than unvalidate buffer, otherwise just free memory | |
422 | * used by parsing context. | |
423 | **/ | |
424 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
049fc527 | 425 | { |
eceb8a15 | 426 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; |
984810fc CK |
427 | unsigned i; |
428 | ||
d38ceaf9 | 429 | if (!error) { |
28b8d66e NH |
430 | amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); |
431 | ||
d38ceaf9 AD |
432 | /* Sort the buffer list from the smallest to largest buffer, |
433 | * which affects the order of buffers in the LRU list. | |
434 | * This assures that the smallest buffers are added first | |
435 | * to the LRU list, so they are likely to be later evicted | |
436 | * first, instead of large buffers whose eviction is more | |
437 | * expensive. | |
438 | * | |
439 | * This slightly lowers the number of bytes moved by TTM | |
440 | * per frame under memory pressure. | |
441 | */ | |
442 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); | |
443 | ||
444 | ttm_eu_fence_buffer_objects(&parser->ticket, | |
984810fc CK |
445 | &parser->validated, |
446 | parser->fence); | |
d38ceaf9 AD |
447 | } else if (backoff) { |
448 | ttm_eu_backoff_reservation(&parser->ticket, | |
449 | &parser->validated); | |
450 | } | |
984810fc | 451 | fence_put(parser->fence); |
7e52a81c | 452 | |
3cb485f3 CK |
453 | if (parser->ctx) |
454 | amdgpu_ctx_put(parser->ctx); | |
a3348bb8 CZ |
455 | if (parser->bo_list) |
456 | amdgpu_bo_list_put(parser->bo_list); | |
457 | ||
d38ceaf9 AD |
458 | for (i = 0; i < parser->nchunks; i++) |
459 | drm_free_large(parser->chunks[i].kdata); | |
460 | kfree(parser->chunks); | |
e4a58a28 CK |
461 | if (parser->ibs) |
462 | for (i = 0; i < parser->num_ibs; i++) | |
463 | amdgpu_ib_free(parser->adev, &parser->ibs[i]); | |
464 | kfree(parser->ibs); | |
91acbeb6 CK |
465 | amdgpu_bo_unref(&parser->uf.bo); |
466 | amdgpu_bo_unref(&parser->uf_entry.robj); | |
d38ceaf9 AD |
467 | } |
468 | ||
469 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, | |
470 | struct amdgpu_vm *vm) | |
471 | { | |
472 | struct amdgpu_device *adev = p->adev; | |
473 | struct amdgpu_bo_va *bo_va; | |
474 | struct amdgpu_bo *bo; | |
475 | int i, r; | |
476 | ||
477 | r = amdgpu_vm_update_page_directory(adev, vm); | |
478 | if (r) | |
479 | return r; | |
480 | ||
05906dec BN |
481 | r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence); |
482 | if (r) | |
483 | return r; | |
484 | ||
d38ceaf9 AD |
485 | r = amdgpu_vm_clear_freed(adev, vm); |
486 | if (r) | |
487 | return r; | |
488 | ||
489 | if (p->bo_list) { | |
490 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
491 | struct fence *f; |
492 | ||
d38ceaf9 AD |
493 | /* ignore duplicates */ |
494 | bo = p->bo_list->array[i].robj; | |
495 | if (!bo) | |
496 | continue; | |
497 | ||
498 | bo_va = p->bo_list->array[i].bo_va; | |
499 | if (bo_va == NULL) | |
500 | continue; | |
501 | ||
502 | r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); | |
503 | if (r) | |
504 | return r; | |
505 | ||
bb1e38a4 | 506 | f = bo_va->last_pt_update; |
91e1a520 CK |
507 | r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f); |
508 | if (r) | |
509 | return r; | |
d38ceaf9 | 510 | } |
b495bd3a CK |
511 | |
512 | } | |
513 | ||
514 | r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); | |
515 | ||
516 | if (amdgpu_vm_debug && p->bo_list) { | |
517 | /* Invalidate all BOs to test for userspace bugs */ | |
518 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
519 | /* ignore duplicates */ | |
520 | bo = p->bo_list->array[i].robj; | |
521 | if (!bo) | |
522 | continue; | |
523 | ||
524 | amdgpu_vm_bo_invalidate(adev, bo); | |
525 | } | |
d38ceaf9 AD |
526 | } |
527 | ||
b495bd3a | 528 | return r; |
d38ceaf9 AD |
529 | } |
530 | ||
531 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
532 | struct amdgpu_cs_parser *parser) | |
533 | { | |
534 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
535 | struct amdgpu_vm *vm = &fpriv->vm; | |
536 | struct amdgpu_ring *ring; | |
537 | int i, r; | |
538 | ||
539 | if (parser->num_ibs == 0) | |
540 | return 0; | |
541 | ||
542 | /* Only for UVD/VCE VM emulation */ | |
543 | for (i = 0; i < parser->num_ibs; i++) { | |
544 | ring = parser->ibs[i].ring; | |
545 | if (ring->funcs->parse_cs) { | |
546 | r = amdgpu_ring_parse_cs(ring, parser, i); | |
547 | if (r) | |
548 | return r; | |
549 | } | |
550 | } | |
551 | ||
d38ceaf9 | 552 | r = amdgpu_bo_vm_update_pte(parser, vm); |
984810fc CK |
553 | if (!r) |
554 | amdgpu_cs_sync_rings(parser); | |
d38ceaf9 | 555 | |
d38ceaf9 AD |
556 | return r; |
557 | } | |
558 | ||
559 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
560 | { | |
561 | if (r == -EDEADLK) { | |
562 | r = amdgpu_gpu_reset(adev); | |
563 | if (!r) | |
564 | r = -EAGAIN; | |
565 | } | |
566 | return r; | |
567 | } | |
568 | ||
569 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
570 | struct amdgpu_cs_parser *parser) | |
571 | { | |
572 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
573 | struct amdgpu_vm *vm = &fpriv->vm; | |
574 | int i, j; | |
575 | int r; | |
576 | ||
577 | for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { | |
578 | struct amdgpu_cs_chunk *chunk; | |
579 | struct amdgpu_ib *ib; | |
580 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 581 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
582 | |
583 | chunk = &parser->chunks[i]; | |
584 | ib = &parser->ibs[j]; | |
585 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; | |
586 | ||
587 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
588 | continue; | |
589 | ||
d38ceaf9 AD |
590 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
591 | chunk_ib->ip_instance, chunk_ib->ring, | |
592 | &ring); | |
3ccec53c | 593 | if (r) |
d38ceaf9 | 594 | return r; |
d38ceaf9 AD |
595 | |
596 | if (ring->funcs->parse_cs) { | |
4802ce11 | 597 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 598 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
599 | uint64_t offset; |
600 | uint8_t *kptr; | |
3ccec53c | 601 | |
4802ce11 CK |
602 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
603 | &aobj); | |
3ccec53c MO |
604 | if (!aobj) { |
605 | DRM_ERROR("IB va_start is invalid\n"); | |
606 | return -EINVAL; | |
d38ceaf9 AD |
607 | } |
608 | ||
4802ce11 CK |
609 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
610 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
611 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
612 | return -EINVAL; | |
613 | } | |
614 | ||
3ccec53c | 615 | /* the IB should be reserved at this point */ |
4802ce11 | 616 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 617 | if (r) { |
d38ceaf9 AD |
618 | return r; |
619 | } | |
620 | ||
4802ce11 CK |
621 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
622 | kptr += chunk_ib->va_start - offset; | |
623 | ||
d38ceaf9 AD |
624 | r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); |
625 | if (r) { | |
626 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
627 | return r; |
628 | } | |
629 | ||
630 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
631 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 AD |
632 | } else { |
633 | r = amdgpu_ib_get(ring, vm, 0, ib); | |
634 | if (r) { | |
635 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
636 | return r; |
637 | } | |
638 | ||
639 | ib->gpu_addr = chunk_ib->va_start; | |
640 | } | |
d38ceaf9 | 641 | |
3ccec53c | 642 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 643 | ib->flags = chunk_ib->flags; |
3cb485f3 | 644 | ib->ctx = parser->ctx; |
d38ceaf9 AD |
645 | j++; |
646 | } | |
647 | ||
648 | if (!parser->num_ibs) | |
649 | return 0; | |
650 | ||
651 | /* add GDS resources to first IB */ | |
652 | if (parser->bo_list) { | |
653 | struct amdgpu_bo *gds = parser->bo_list->gds_obj; | |
654 | struct amdgpu_bo *gws = parser->bo_list->gws_obj; | |
655 | struct amdgpu_bo *oa = parser->bo_list->oa_obj; | |
656 | struct amdgpu_ib *ib = &parser->ibs[0]; | |
657 | ||
658 | if (gds) { | |
659 | ib->gds_base = amdgpu_bo_gpu_offset(gds); | |
660 | ib->gds_size = amdgpu_bo_size(gds); | |
661 | } | |
662 | if (gws) { | |
663 | ib->gws_base = amdgpu_bo_gpu_offset(gws); | |
664 | ib->gws_size = amdgpu_bo_size(gws); | |
665 | } | |
666 | if (oa) { | |
667 | ib->oa_base = amdgpu_bo_gpu_offset(oa); | |
668 | ib->oa_size = amdgpu_bo_size(oa); | |
669 | } | |
670 | } | |
d38ceaf9 AD |
671 | /* wrap the last IB with user fence */ |
672 | if (parser->uf.bo) { | |
673 | struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; | |
674 | ||
675 | /* UVD & VCE fw doesn't support user fences */ | |
676 | if (ib->ring->type == AMDGPU_RING_TYPE_UVD || | |
677 | ib->ring->type == AMDGPU_RING_TYPE_VCE) | |
678 | return -EINVAL; | |
679 | ||
680 | ib->user = &parser->uf; | |
681 | } | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
2b48d323 CK |
686 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
687 | struct amdgpu_cs_parser *p) | |
688 | { | |
76a1ea61 | 689 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
690 | struct amdgpu_ib *ib; |
691 | int i, j, r; | |
692 | ||
693 | if (!p->num_ibs) | |
694 | return 0; | |
695 | ||
696 | /* Add dependencies to first IB */ | |
697 | ib = &p->ibs[0]; | |
698 | for (i = 0; i < p->nchunks; ++i) { | |
699 | struct drm_amdgpu_cs_chunk_dep *deps; | |
700 | struct amdgpu_cs_chunk *chunk; | |
701 | unsigned num_deps; | |
702 | ||
703 | chunk = &p->chunks[i]; | |
704 | ||
705 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
706 | continue; | |
707 | ||
708 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
709 | num_deps = chunk->length_dw * 4 / | |
710 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
711 | ||
712 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 713 | struct amdgpu_ring *ring; |
76a1ea61 | 714 | struct amdgpu_ctx *ctx; |
21c16bf6 | 715 | struct fence *fence; |
2b48d323 CK |
716 | |
717 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
718 | deps[j].ip_instance, | |
719 | deps[j].ring, &ring); | |
720 | if (r) | |
721 | return r; | |
722 | ||
76a1ea61 CK |
723 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
724 | if (ctx == NULL) | |
725 | return -EINVAL; | |
726 | ||
21c16bf6 CK |
727 | fence = amdgpu_ctx_get_fence(ctx, ring, |
728 | deps[j].handle); | |
729 | if (IS_ERR(fence)) { | |
730 | r = PTR_ERR(fence); | |
76a1ea61 | 731 | amdgpu_ctx_put(ctx); |
2b48d323 | 732 | return r; |
91e1a520 | 733 | |
21c16bf6 CK |
734 | } else if (fence) { |
735 | r = amdgpu_sync_fence(adev, &ib->sync, fence); | |
736 | fence_put(fence); | |
737 | amdgpu_ctx_put(ctx); | |
738 | if (r) | |
739 | return r; | |
740 | } | |
2b48d323 CK |
741 | } |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
4c7eb91c | 747 | static int amdgpu_cs_free_job(struct amdgpu_job *job) |
bb977d37 CZ |
748 | { |
749 | int i; | |
4c7eb91c JZ |
750 | if (job->ibs) |
751 | for (i = 0; i < job->num_ibs; i++) | |
752 | amdgpu_ib_free(job->adev, &job->ibs[i]); | |
753 | kfree(job->ibs); | |
754 | if (job->uf.bo) | |
f3f17692 | 755 | amdgpu_bo_unref(&job->uf.bo); |
bb977d37 CZ |
756 | return 0; |
757 | } | |
758 | ||
049fc527 CZ |
759 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
760 | { | |
761 | struct amdgpu_device *adev = dev->dev_private; | |
762 | union drm_amdgpu_cs *cs = data; | |
7e52a81c | 763 | struct amdgpu_cs_parser parser = {}; |
26a6980c CK |
764 | bool reserved_buffers = false; |
765 | int i, r; | |
049fc527 | 766 | |
0c418f10 | 767 | if (!adev->accel_working) |
049fc527 | 768 | return -EBUSY; |
2b48d323 | 769 | |
7e52a81c CK |
770 | parser.adev = adev; |
771 | parser.filp = filp; | |
772 | ||
773 | r = amdgpu_cs_parser_init(&parser, data); | |
d38ceaf9 | 774 | if (r) { |
049fc527 | 775 | DRM_ERROR("Failed to initialize parser !\n"); |
7e52a81c | 776 | amdgpu_cs_parser_fini(&parser, r, false); |
d38ceaf9 AD |
777 | r = amdgpu_cs_handle_lockup(adev, r); |
778 | return r; | |
779 | } | |
2a7d9bda | 780 | r = amdgpu_cs_parser_bos(&parser, data); |
26a6980c CK |
781 | if (r == -ENOMEM) |
782 | DRM_ERROR("Not enough memory for command submission!\n"); | |
783 | else if (r && r != -ERESTARTSYS) | |
784 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
785 | else if (!r) { | |
786 | reserved_buffers = true; | |
7e52a81c | 787 | r = amdgpu_cs_ib_fill(adev, &parser); |
26a6980c CK |
788 | } |
789 | ||
790 | if (!r) { | |
7e52a81c | 791 | r = amdgpu_cs_dependencies(adev, &parser); |
26a6980c CK |
792 | if (r) |
793 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
794 | } | |
795 | ||
796 | if (r) | |
797 | goto out; | |
798 | ||
7e52a81c CK |
799 | for (i = 0; i < parser.num_ibs; i++) |
800 | trace_amdgpu_cs(&parser, i); | |
26a6980c | 801 | |
7e52a81c | 802 | r = amdgpu_cs_ib_vm_chunk(adev, &parser); |
4fe63117 CZ |
803 | if (r) |
804 | goto out; | |
805 | ||
7e52a81c | 806 | if (amdgpu_enable_scheduler && parser.num_ibs) { |
7e52a81c | 807 | struct amdgpu_ring * ring = parser.ibs->ring; |
e2840221 CK |
808 | struct amd_sched_fence *fence; |
809 | struct amdgpu_job *job; | |
7e52a81c | 810 | |
bb977d37 | 811 | job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); |
4cfdcd9c DC |
812 | if (!job) { |
813 | r = -ENOMEM; | |
814 | goto out; | |
815 | } | |
7e52a81c | 816 | |
4f839a24 | 817 | job->base.sched = &ring->sched; |
7e52a81c CK |
818 | job->base.s_entity = &parser.ctx->rings[ring->idx].entity; |
819 | job->adev = parser.adev; | |
e2840221 CK |
820 | job->owner = parser.filp; |
821 | job->free_job = amdgpu_cs_free_job; | |
822 | ||
5d82730a CK |
823 | job->ibs = parser.ibs; |
824 | job->num_ibs = parser.num_ibs; | |
825 | parser.ibs = NULL; | |
826 | parser.num_ibs = 0; | |
827 | ||
bb977d37 | 828 | if (job->ibs[job->num_ibs - 1].user) { |
7e52a81c | 829 | job->uf = parser.uf; |
bb977d37 | 830 | job->ibs[job->num_ibs - 1].user = &job->uf; |
7e52a81c | 831 | parser.uf.bo = NULL; |
bb977d37 CZ |
832 | } |
833 | ||
e2840221 CK |
834 | fence = amd_sched_fence_create(job->base.s_entity, |
835 | parser.filp); | |
836 | if (!fence) { | |
837 | r = -ENOMEM; | |
bb977d37 CZ |
838 | amdgpu_cs_free_job(job); |
839 | kfree(job); | |
f556cb0c CZ |
840 | goto out; |
841 | } | |
e2840221 | 842 | job->base.s_fence = fence; |
984810fc | 843 | parser.fence = fence_get(&fence->base); |
e2840221 CK |
844 | |
845 | cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring, | |
846 | &fence->base); | |
e4a58a28 | 847 | job->ibs[job->num_ibs - 1].sequence = cs->out.handle; |
eb98d1c5 | 848 | |
7034decf | 849 | trace_amdgpu_cs_ioctl(job); |
e2840221 CK |
850 | amd_sched_entity_push_job(&job->base); |
851 | ||
984810fc CK |
852 | } else { |
853 | struct amdgpu_fence *fence; | |
e2840221 | 854 | |
984810fc CK |
855 | r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs, |
856 | parser.filp); | |
857 | fence = parser.ibs[parser.num_ibs - 1].fence; | |
858 | parser.fence = fence_get(&fence->base); | |
859 | cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence; | |
d38ceaf9 AD |
860 | } |
861 | ||
d38ceaf9 | 862 | out: |
7e52a81c | 863 | amdgpu_cs_parser_fini(&parser, r, reserved_buffers); |
d38ceaf9 AD |
864 | r = amdgpu_cs_handle_lockup(adev, r); |
865 | return r; | |
866 | } | |
867 | ||
868 | /** | |
869 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
870 | * | |
871 | * @dev: drm device | |
872 | * @data: data from userspace | |
873 | * @filp: file private | |
874 | * | |
875 | * Wait for the command submission identified by handle to finish. | |
876 | */ | |
877 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
878 | struct drm_file *filp) | |
879 | { | |
880 | union drm_amdgpu_wait_cs *wait = data; | |
881 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 882 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 883 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 884 | struct amdgpu_ctx *ctx; |
21c16bf6 | 885 | struct fence *fence; |
d38ceaf9 AD |
886 | long r; |
887 | ||
21c16bf6 CK |
888 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
889 | wait->in.ring, &ring); | |
890 | if (r) | |
891 | return r; | |
892 | ||
66b3cf2a JZ |
893 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
894 | if (ctx == NULL) | |
895 | return -EINVAL; | |
d38ceaf9 | 896 | |
4b559c90 CZ |
897 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
898 | if (IS_ERR(fence)) | |
899 | r = PTR_ERR(fence); | |
900 | else if (fence) { | |
901 | r = fence_wait_timeout(fence, true, timeout); | |
902 | fence_put(fence); | |
903 | } else | |
904 | r = 1; | |
049fc527 | 905 | |
66b3cf2a | 906 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
907 | if (r < 0) |
908 | return r; | |
909 | ||
910 | memset(wait, 0, sizeof(*wait)); | |
911 | wait->out.status = (r == 0); | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
916 | /** | |
917 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
918 | * | |
919 | * @parser: command submission parser context | |
920 | * @addr: VM address | |
921 | * @bo: resulting BO of the mapping found | |
922 | * | |
923 | * Search the buffer objects in the command submission context for a certain | |
924 | * virtual memory address. Returns allocation structure when found, NULL | |
925 | * otherwise. | |
926 | */ | |
927 | struct amdgpu_bo_va_mapping * | |
928 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
929 | uint64_t addr, struct amdgpu_bo **bo) | |
930 | { | |
931 | struct amdgpu_bo_list_entry *reloc; | |
932 | struct amdgpu_bo_va_mapping *mapping; | |
933 | ||
934 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
935 | ||
936 | list_for_each_entry(reloc, &parser->validated, tv.head) { | |
937 | if (!reloc->bo_va) | |
938 | continue; | |
939 | ||
7fc11959 CK |
940 | list_for_each_entry(mapping, &reloc->bo_va->valids, list) { |
941 | if (mapping->it.start > addr || | |
942 | addr > mapping->it.last) | |
943 | continue; | |
944 | ||
945 | *bo = reloc->bo_va->bo; | |
946 | return mapping; | |
947 | } | |
948 | ||
949 | list_for_each_entry(mapping, &reloc->bo_va->invalids, list) { | |
d38ceaf9 AD |
950 | if (mapping->it.start > addr || |
951 | addr > mapping->it.last) | |
952 | continue; | |
953 | ||
954 | *bo = reloc->bo_va->bo; | |
955 | return mapping; | |
956 | } | |
957 | } | |
958 | ||
959 | return NULL; | |
960 | } |