Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
27 | #include <linux/list_sort.h> | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | #define AMDGPU_CS_MAX_PRIORITY 32u | |
34 | #define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1) | |
35 | ||
36 | /* This is based on the bucket sort with O(n) time complexity. | |
37 | * An item with priority "i" is added to bucket[i]. The lists are then | |
38 | * concatenated in descending order. | |
39 | */ | |
40 | struct amdgpu_cs_buckets { | |
41 | struct list_head bucket[AMDGPU_CS_NUM_BUCKETS]; | |
42 | }; | |
43 | ||
44 | static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b) | |
45 | { | |
46 | unsigned i; | |
47 | ||
48 | for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) | |
49 | INIT_LIST_HEAD(&b->bucket[i]); | |
50 | } | |
51 | ||
52 | static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b, | |
53 | struct list_head *item, unsigned priority) | |
54 | { | |
55 | /* Since buffers which appear sooner in the relocation list are | |
56 | * likely to be used more often than buffers which appear later | |
57 | * in the list, the sort mustn't change the ordering of buffers | |
58 | * with the same priority, i.e. it must be stable. | |
59 | */ | |
60 | list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]); | |
61 | } | |
62 | ||
63 | static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b, | |
64 | struct list_head *out_list) | |
65 | { | |
66 | unsigned i; | |
67 | ||
68 | /* Connect the sorted buckets in the output list. */ | |
69 | for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) { | |
70 | list_splice(&b->bucket[i], out_list); | |
71 | } | |
72 | } | |
73 | ||
74 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, | |
75 | u32 ip_instance, u32 ring, | |
76 | struct amdgpu_ring **out_ring) | |
77 | { | |
78 | /* Right now all IPs have only one instance - multiple rings. */ | |
79 | if (ip_instance != 0) { | |
80 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | switch (ip_type) { | |
85 | default: | |
86 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
87 | return -EINVAL; | |
88 | case AMDGPU_HW_IP_GFX: | |
89 | if (ring < adev->gfx.num_gfx_rings) { | |
90 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
91 | } else { | |
92 | DRM_ERROR("only %d gfx rings are supported now\n", | |
93 | adev->gfx.num_gfx_rings); | |
94 | return -EINVAL; | |
95 | } | |
96 | break; | |
97 | case AMDGPU_HW_IP_COMPUTE: | |
98 | if (ring < adev->gfx.num_compute_rings) { | |
99 | *out_ring = &adev->gfx.compute_ring[ring]; | |
100 | } else { | |
101 | DRM_ERROR("only %d compute rings are supported now\n", | |
102 | adev->gfx.num_compute_rings); | |
103 | return -EINVAL; | |
104 | } | |
105 | break; | |
106 | case AMDGPU_HW_IP_DMA: | |
107 | if (ring < 2) { | |
108 | *out_ring = &adev->sdma[ring].ring; | |
109 | } else { | |
110 | DRM_ERROR("only two SDMA rings are supported\n"); | |
111 | return -EINVAL; | |
112 | } | |
113 | break; | |
114 | case AMDGPU_HW_IP_UVD: | |
115 | *out_ring = &adev->uvd.ring; | |
116 | break; | |
117 | case AMDGPU_HW_IP_VCE: | |
118 | if (ring < 2){ | |
119 | *out_ring = &adev->vce.ring[ring]; | |
120 | } else { | |
121 | DRM_ERROR("only two VCE rings are supported\n"); | |
122 | return -EINVAL; | |
123 | } | |
124 | break; | |
125 | } | |
126 | return 0; | |
127 | } | |
128 | ||
049fc527 CZ |
129 | static void amdgpu_job_work_func(struct work_struct *work) |
130 | { | |
131 | struct amdgpu_cs_parser *sched_job = | |
132 | container_of(work, struct amdgpu_cs_parser, | |
133 | job_work); | |
134 | mutex_lock(&sched_job->job_lock); | |
afe10081 CZ |
135 | if (sched_job->free_job) |
136 | sched_job->free_job(sched_job); | |
049fc527 CZ |
137 | mutex_unlock(&sched_job->job_lock); |
138 | /* after processing job, free memory */ | |
281b4223 | 139 | fence_put(&sched_job->s_fence->base); |
049fc527 CZ |
140 | kfree(sched_job); |
141 | } | |
142 | struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, | |
143 | struct drm_file *filp, | |
144 | struct amdgpu_ctx *ctx, | |
145 | struct amdgpu_ib *ibs, | |
146 | uint32_t num_ibs) | |
147 | { | |
148 | struct amdgpu_cs_parser *parser; | |
149 | int i; | |
150 | ||
151 | parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL); | |
152 | if (!parser) | |
153 | return NULL; | |
154 | ||
155 | parser->adev = adev; | |
156 | parser->filp = filp; | |
157 | parser->ctx = ctx; | |
158 | parser->ibs = ibs; | |
159 | parser->num_ibs = num_ibs; | |
160 | if (amdgpu_enable_scheduler) { | |
161 | mutex_init(&parser->job_lock); | |
162 | INIT_WORK(&parser->job_work, amdgpu_job_work_func); | |
163 | } | |
164 | for (i = 0; i < num_ibs; i++) | |
165 | ibs[i].ctx = ctx; | |
166 | ||
167 | return parser; | |
168 | } | |
169 | ||
d38ceaf9 AD |
170 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
171 | { | |
172 | union drm_amdgpu_cs *cs = data; | |
173 | uint64_t *chunk_array_user; | |
174 | uint64_t *chunk_array = NULL; | |
175 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
049fc527 | 176 | struct amdgpu_bo_list *bo_list = NULL; |
d38ceaf9 AD |
177 | unsigned size, i; |
178 | int r = 0; | |
179 | ||
180 | if (!cs->in.num_chunks) | |
181 | goto out; | |
182 | ||
3cb485f3 CK |
183 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
184 | if (!p->ctx) { | |
185 | r = -EINVAL; | |
186 | goto out; | |
187 | } | |
049fc527 | 188 | bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); |
1939e3e2 | 189 | if (!amdgpu_enable_scheduler) |
049fc527 | 190 | p->bo_list = bo_list; |
1939e3e2 | 191 | else { |
192 | if (bo_list && !bo_list->has_userptr) { | |
193 | p->bo_list = amdgpu_bo_list_clone(bo_list); | |
194 | amdgpu_bo_list_put(bo_list); | |
195 | if (!p->bo_list) | |
196 | return -ENOMEM; | |
197 | } else if (bo_list && bo_list->has_userptr) | |
198 | p->bo_list = bo_list; | |
199 | else | |
200 | p->bo_list = NULL; | |
201 | } | |
d38ceaf9 AD |
202 | |
203 | /* get chunks */ | |
204 | INIT_LIST_HEAD(&p->validated); | |
e60b344f | 205 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); |
d38ceaf9 AD |
206 | if (chunk_array == NULL) { |
207 | r = -ENOMEM; | |
208 | goto out; | |
209 | } | |
210 | ||
e60b344f | 211 | chunk_array_user = (uint64_t __user *)(cs->in.chunks); |
d38ceaf9 AD |
212 | if (copy_from_user(chunk_array, chunk_array_user, |
213 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
214 | r = -EFAULT; | |
215 | goto out; | |
216 | } | |
217 | ||
218 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 219 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 AD |
220 | GFP_KERNEL); |
221 | if (p->chunks == NULL) { | |
222 | r = -ENOMEM; | |
223 | goto out; | |
224 | } | |
225 | ||
226 | for (i = 0; i < p->nchunks; i++) { | |
227 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
228 | struct drm_amdgpu_cs_chunk user_chunk; | |
229 | uint32_t __user *cdata; | |
230 | ||
e60b344f | 231 | chunk_ptr = (void __user *)chunk_array[i]; |
d38ceaf9 AD |
232 | if (copy_from_user(&user_chunk, chunk_ptr, |
233 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
234 | r = -EFAULT; | |
235 | goto out; | |
236 | } | |
237 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
238 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
239 | |
240 | size = p->chunks[i].length_dw; | |
e60b344f | 241 | cdata = (void __user *)user_chunk.chunk_data; |
d38ceaf9 AD |
242 | p->chunks[i].user_ptr = cdata; |
243 | ||
244 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
245 | if (p->chunks[i].kdata == NULL) { | |
246 | r = -ENOMEM; | |
247 | goto out; | |
248 | } | |
249 | size *= sizeof(uint32_t); | |
250 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
251 | r = -EFAULT; | |
252 | goto out; | |
253 | } | |
254 | ||
9a5e8fb1 CK |
255 | switch (p->chunks[i].chunk_id) { |
256 | case AMDGPU_CHUNK_ID_IB: | |
257 | p->num_ibs++; | |
258 | break; | |
259 | ||
260 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 AD |
261 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
262 | if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) { | |
263 | uint32_t handle; | |
264 | struct drm_gem_object *gobj; | |
265 | struct drm_amdgpu_cs_chunk_fence *fence_data; | |
266 | ||
267 | fence_data = (void *)p->chunks[i].kdata; | |
268 | handle = fence_data->handle; | |
269 | gobj = drm_gem_object_lookup(p->adev->ddev, | |
270 | p->filp, handle); | |
271 | if (gobj == NULL) { | |
272 | r = -EINVAL; | |
273 | goto out; | |
274 | } | |
275 | ||
276 | p->uf.bo = gem_to_amdgpu_bo(gobj); | |
277 | p->uf.offset = fence_data->offset; | |
278 | } else { | |
279 | r = -EINVAL; | |
280 | goto out; | |
281 | } | |
9a5e8fb1 CK |
282 | break; |
283 | ||
2b48d323 CK |
284 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
285 | break; | |
286 | ||
9a5e8fb1 CK |
287 | default: |
288 | r = -EINVAL; | |
289 | goto out; | |
d38ceaf9 AD |
290 | } |
291 | } | |
292 | ||
e60b344f | 293 | |
294 | p->ibs = kmalloc_array(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); | |
295 | if (!p->ibs) | |
d38ceaf9 | 296 | r = -ENOMEM; |
d38ceaf9 | 297 | |
d38ceaf9 AD |
298 | out: |
299 | kfree(chunk_array); | |
300 | return r; | |
301 | } | |
302 | ||
303 | /* Returns how many bytes TTM can move per IB. | |
304 | */ | |
305 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
306 | { | |
307 | u64 real_vram_size = adev->mc.real_vram_size; | |
308 | u64 vram_usage = atomic64_read(&adev->vram_usage); | |
309 | ||
310 | /* This function is based on the current VRAM usage. | |
311 | * | |
312 | * - If all of VRAM is free, allow relocating the number of bytes that | |
313 | * is equal to 1/4 of the size of VRAM for this IB. | |
314 | ||
315 | * - If more than one half of VRAM is occupied, only allow relocating | |
316 | * 1 MB of data for this IB. | |
317 | * | |
318 | * - From 0 to one half of used VRAM, the threshold decreases | |
319 | * linearly. | |
320 | * __________________ | |
321 | * 1/4 of -|\ | | |
322 | * VRAM | \ | | |
323 | * | \ | | |
324 | * | \ | | |
325 | * | \ | | |
326 | * | \ | | |
327 | * | \ | | |
328 | * | \________|1 MB | |
329 | * |----------------| | |
330 | * VRAM 0 % 100 % | |
331 | * used used | |
332 | * | |
333 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
334 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
335 | * can be moved as long as the threshold isn't crossed before | |
336 | * the relocation takes place. We don't want to disable buffer | |
337 | * relocations completely. | |
338 | * | |
339 | * The idea is that buffers should be placed in VRAM at creation time | |
340 | * and TTM should only do a minimum number of relocations during | |
341 | * command submission. In practice, you need to submit at least | |
342 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
343 | * | |
344 | * Also, things can get pretty crazy under memory pressure and actual | |
345 | * VRAM usage can change a lot, so playing safe even at 50% does | |
346 | * consistently increase performance. | |
347 | */ | |
348 | ||
349 | u64 half_vram = real_vram_size >> 1; | |
350 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
351 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
352 | return max(bytes_moved_threshold, 1024*1024ull); | |
353 | } | |
354 | ||
355 | int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p) | |
356 | { | |
357 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
358 | struct amdgpu_vm *vm = &fpriv->vm; | |
359 | struct amdgpu_device *adev = p->adev; | |
360 | struct amdgpu_bo_list_entry *lobj; | |
361 | struct list_head duplicates; | |
362 | struct amdgpu_bo *bo; | |
363 | u64 bytes_moved = 0, initial_bytes_moved; | |
364 | u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev); | |
365 | int r; | |
366 | ||
367 | INIT_LIST_HEAD(&duplicates); | |
368 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); | |
369 | if (unlikely(r != 0)) { | |
370 | return r; | |
371 | } | |
372 | ||
373 | list_for_each_entry(lobj, &p->validated, tv.head) { | |
374 | bo = lobj->robj; | |
375 | if (!bo->pin_count) { | |
376 | u32 domain = lobj->prefered_domains; | |
377 | u32 current_domain = | |
378 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
379 | ||
380 | /* Check if this buffer will be moved and don't move it | |
381 | * if we have moved too many buffers for this IB already. | |
382 | * | |
383 | * Note that this allows moving at least one buffer of | |
384 | * any size, because it doesn't take the current "bo" | |
385 | * into account. We don't want to disallow buffer moves | |
386 | * completely. | |
387 | */ | |
388 | if (current_domain != AMDGPU_GEM_DOMAIN_CPU && | |
389 | (domain & current_domain) == 0 && /* will be moved */ | |
390 | bytes_moved > bytes_moved_threshold) { | |
391 | /* don't move it */ | |
392 | domain = current_domain; | |
393 | } | |
394 | ||
395 | retry: | |
396 | amdgpu_ttm_placement_from_domain(bo, domain); | |
397 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); | |
398 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
399 | bytes_moved += atomic64_read(&adev->num_bytes_moved) - | |
400 | initial_bytes_moved; | |
401 | ||
402 | if (unlikely(r)) { | |
403 | if (r != -ERESTARTSYS && domain != lobj->allowed_domains) { | |
404 | domain = lobj->allowed_domains; | |
405 | goto retry; | |
406 | } | |
407 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
408 | return r; | |
409 | } | |
410 | } | |
411 | lobj->bo_va = amdgpu_vm_bo_find(vm, bo); | |
412 | } | |
413 | return 0; | |
414 | } | |
415 | ||
416 | static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) | |
417 | { | |
418 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
419 | struct amdgpu_cs_buckets buckets; | |
840d5144 | 420 | bool need_mmap_lock = false; |
d38ceaf9 AD |
421 | int i, r; |
422 | ||
840d5144 | 423 | if (p->bo_list) { |
424 | need_mmap_lock = p->bo_list->has_userptr; | |
425 | amdgpu_cs_buckets_init(&buckets); | |
426 | for (i = 0; i < p->bo_list->num_entries; i++) | |
427 | amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, | |
428 | p->bo_list->array[i].priority); | |
d38ceaf9 | 429 | |
840d5144 | 430 | amdgpu_cs_buckets_get_list(&buckets, &p->validated); |
431 | } | |
d38ceaf9 | 432 | |
d38ceaf9 AD |
433 | p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm, |
434 | &p->validated); | |
435 | ||
d38ceaf9 AD |
436 | if (need_mmap_lock) |
437 | down_read(¤t->mm->mmap_sem); | |
438 | ||
439 | r = amdgpu_cs_list_validate(p); | |
440 | ||
441 | if (need_mmap_lock) | |
442 | up_read(¤t->mm->mmap_sem); | |
443 | ||
444 | return r; | |
445 | } | |
446 | ||
447 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
448 | { | |
449 | struct amdgpu_bo_list_entry *e; | |
450 | int r; | |
451 | ||
452 | list_for_each_entry(e, &p->validated, tv.head) { | |
453 | struct reservation_object *resv = e->robj->tbo.resv; | |
454 | r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); | |
455 | ||
456 | if (r) | |
457 | return r; | |
458 | } | |
459 | return 0; | |
460 | } | |
461 | ||
462 | static int cmp_size_smaller_first(void *priv, struct list_head *a, | |
463 | struct list_head *b) | |
464 | { | |
465 | struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); | |
466 | struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); | |
467 | ||
468 | /* Sort A before B if A is smaller. */ | |
469 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; | |
470 | } | |
471 | ||
049fc527 CZ |
472 | static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff) |
473 | { | |
d38ceaf9 AD |
474 | if (!error) { |
475 | /* Sort the buffer list from the smallest to largest buffer, | |
476 | * which affects the order of buffers in the LRU list. | |
477 | * This assures that the smallest buffers are added first | |
478 | * to the LRU list, so they are likely to be later evicted | |
479 | * first, instead of large buffers whose eviction is more | |
480 | * expensive. | |
481 | * | |
482 | * This slightly lowers the number of bytes moved by TTM | |
483 | * per frame under memory pressure. | |
484 | */ | |
485 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); | |
486 | ||
487 | ttm_eu_fence_buffer_objects(&parser->ticket, | |
488 | &parser->validated, | |
489 | &parser->ibs[parser->num_ibs-1].fence->base); | |
490 | } else if (backoff) { | |
491 | ttm_eu_backoff_reservation(&parser->ticket, | |
492 | &parser->validated); | |
493 | } | |
049fc527 | 494 | } |
d38ceaf9 | 495 | |
049fc527 CZ |
496 | static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser) |
497 | { | |
498 | unsigned i; | |
3cb485f3 CK |
499 | if (parser->ctx) |
500 | amdgpu_ctx_put(parser->ctx); | |
049fc527 | 501 | if (parser->bo_list) { |
1939e3e2 | 502 | if (amdgpu_enable_scheduler && !parser->bo_list->has_userptr) |
049fc527 CZ |
503 | amdgpu_bo_list_free(parser->bo_list); |
504 | else | |
505 | amdgpu_bo_list_put(parser->bo_list); | |
506 | } | |
d38ceaf9 AD |
507 | drm_free_large(parser->vm_bos); |
508 | for (i = 0; i < parser->nchunks; i++) | |
509 | drm_free_large(parser->chunks[i].kdata); | |
510 | kfree(parser->chunks); | |
b8682ac2 CK |
511 | if (parser->ibs) |
512 | for (i = 0; i < parser->num_ibs; i++) | |
513 | amdgpu_ib_free(parser->adev, &parser->ibs[i]); | |
d38ceaf9 | 514 | kfree(parser->ibs); |
d38ceaf9 AD |
515 | if (parser->uf.bo) |
516 | drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); | |
049fc527 CZ |
517 | |
518 | if (!amdgpu_enable_scheduler) | |
519 | kfree(parser); | |
d38ceaf9 AD |
520 | } |
521 | ||
351dba73 CK |
522 | /** |
523 | * cs_parser_fini() - clean parser states | |
524 | * @parser: parser structure holding parsing context. | |
525 | * @error: error number | |
526 | * | |
527 | * If error is set than unvalidate buffer, otherwise just free memory | |
528 | * used by parsing context. | |
529 | **/ | |
530 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
531 | { | |
532 | amdgpu_cs_parser_fini_early(parser, error, backoff); | |
533 | amdgpu_cs_parser_fini_late(parser); | |
534 | } | |
535 | ||
4cd7f42c | 536 | static int amdgpu_cs_parser_run_job(struct amdgpu_cs_parser *sched_job) |
351dba73 CK |
537 | { |
538 | amdgpu_cs_parser_fini_early(sched_job, 0, true); | |
539 | return 0; | |
540 | } | |
541 | ||
4cd7f42c | 542 | static int amdgpu_cs_parser_free_job(struct amdgpu_cs_parser *sched_job) |
351dba73 CK |
543 | { |
544 | amdgpu_cs_parser_fini_late(sched_job); | |
545 | return 0; | |
546 | } | |
547 | ||
d38ceaf9 AD |
548 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, |
549 | struct amdgpu_vm *vm) | |
550 | { | |
551 | struct amdgpu_device *adev = p->adev; | |
552 | struct amdgpu_bo_va *bo_va; | |
553 | struct amdgpu_bo *bo; | |
554 | int i, r; | |
555 | ||
556 | r = amdgpu_vm_update_page_directory(adev, vm); | |
557 | if (r) | |
558 | return r; | |
559 | ||
560 | r = amdgpu_vm_clear_freed(adev, vm); | |
561 | if (r) | |
562 | return r; | |
563 | ||
564 | if (p->bo_list) { | |
565 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
566 | struct fence *f; |
567 | ||
d38ceaf9 AD |
568 | /* ignore duplicates */ |
569 | bo = p->bo_list->array[i].robj; | |
570 | if (!bo) | |
571 | continue; | |
572 | ||
573 | bo_va = p->bo_list->array[i].bo_va; | |
574 | if (bo_va == NULL) | |
575 | continue; | |
576 | ||
577 | r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); | |
578 | if (r) | |
579 | return r; | |
580 | ||
bb1e38a4 | 581 | f = bo_va->last_pt_update; |
91e1a520 CK |
582 | r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f); |
583 | if (r) | |
584 | return r; | |
d38ceaf9 AD |
585 | } |
586 | } | |
587 | ||
cfe2c978 | 588 | return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); |
d38ceaf9 AD |
589 | } |
590 | ||
591 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
592 | struct amdgpu_cs_parser *parser) | |
593 | { | |
594 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
595 | struct amdgpu_vm *vm = &fpriv->vm; | |
596 | struct amdgpu_ring *ring; | |
597 | int i, r; | |
598 | ||
599 | if (parser->num_ibs == 0) | |
600 | return 0; | |
601 | ||
602 | /* Only for UVD/VCE VM emulation */ | |
603 | for (i = 0; i < parser->num_ibs; i++) { | |
604 | ring = parser->ibs[i].ring; | |
605 | if (ring->funcs->parse_cs) { | |
606 | r = amdgpu_ring_parse_cs(ring, parser, i); | |
607 | if (r) | |
608 | return r; | |
609 | } | |
610 | } | |
611 | ||
612 | mutex_lock(&vm->mutex); | |
613 | r = amdgpu_bo_vm_update_pte(parser, vm); | |
614 | if (r) { | |
615 | goto out; | |
616 | } | |
617 | amdgpu_cs_sync_rings(parser); | |
049fc527 CZ |
618 | if (!amdgpu_enable_scheduler) |
619 | r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs, | |
620 | parser->filp); | |
d38ceaf9 AD |
621 | |
622 | out: | |
623 | mutex_unlock(&vm->mutex); | |
624 | return r; | |
625 | } | |
626 | ||
627 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
628 | { | |
629 | if (r == -EDEADLK) { | |
630 | r = amdgpu_gpu_reset(adev); | |
631 | if (!r) | |
632 | r = -EAGAIN; | |
633 | } | |
634 | return r; | |
635 | } | |
636 | ||
637 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
638 | struct amdgpu_cs_parser *parser) | |
639 | { | |
640 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
641 | struct amdgpu_vm *vm = &fpriv->vm; | |
642 | int i, j; | |
643 | int r; | |
644 | ||
645 | for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { | |
646 | struct amdgpu_cs_chunk *chunk; | |
647 | struct amdgpu_ib *ib; | |
648 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 649 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
650 | |
651 | chunk = &parser->chunks[i]; | |
652 | ib = &parser->ibs[j]; | |
653 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; | |
654 | ||
655 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
656 | continue; | |
657 | ||
d38ceaf9 AD |
658 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
659 | chunk_ib->ip_instance, chunk_ib->ring, | |
660 | &ring); | |
3ccec53c | 661 | if (r) |
d38ceaf9 | 662 | return r; |
d38ceaf9 AD |
663 | |
664 | if (ring->funcs->parse_cs) { | |
4802ce11 | 665 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 666 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
667 | uint64_t offset; |
668 | uint8_t *kptr; | |
3ccec53c | 669 | |
4802ce11 CK |
670 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
671 | &aobj); | |
3ccec53c MO |
672 | if (!aobj) { |
673 | DRM_ERROR("IB va_start is invalid\n"); | |
674 | return -EINVAL; | |
d38ceaf9 AD |
675 | } |
676 | ||
4802ce11 CK |
677 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
678 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
679 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
3ccec53c | 683 | /* the IB should be reserved at this point */ |
4802ce11 | 684 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 685 | if (r) { |
d38ceaf9 AD |
686 | return r; |
687 | } | |
688 | ||
4802ce11 CK |
689 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
690 | kptr += chunk_ib->va_start - offset; | |
691 | ||
d38ceaf9 AD |
692 | r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); |
693 | if (r) { | |
694 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
695 | return r; |
696 | } | |
697 | ||
698 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
699 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 AD |
700 | } else { |
701 | r = amdgpu_ib_get(ring, vm, 0, ib); | |
702 | if (r) { | |
703 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
704 | return r; |
705 | } | |
706 | ||
707 | ib->gpu_addr = chunk_ib->va_start; | |
708 | } | |
d38ceaf9 | 709 | |
3ccec53c | 710 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 711 | ib->flags = chunk_ib->flags; |
3cb485f3 | 712 | ib->ctx = parser->ctx; |
d38ceaf9 AD |
713 | j++; |
714 | } | |
715 | ||
716 | if (!parser->num_ibs) | |
717 | return 0; | |
718 | ||
719 | /* add GDS resources to first IB */ | |
720 | if (parser->bo_list) { | |
721 | struct amdgpu_bo *gds = parser->bo_list->gds_obj; | |
722 | struct amdgpu_bo *gws = parser->bo_list->gws_obj; | |
723 | struct amdgpu_bo *oa = parser->bo_list->oa_obj; | |
724 | struct amdgpu_ib *ib = &parser->ibs[0]; | |
725 | ||
726 | if (gds) { | |
727 | ib->gds_base = amdgpu_bo_gpu_offset(gds); | |
728 | ib->gds_size = amdgpu_bo_size(gds); | |
729 | } | |
730 | if (gws) { | |
731 | ib->gws_base = amdgpu_bo_gpu_offset(gws); | |
732 | ib->gws_size = amdgpu_bo_size(gws); | |
733 | } | |
734 | if (oa) { | |
735 | ib->oa_base = amdgpu_bo_gpu_offset(oa); | |
736 | ib->oa_size = amdgpu_bo_size(oa); | |
737 | } | |
738 | } | |
d38ceaf9 AD |
739 | /* wrap the last IB with user fence */ |
740 | if (parser->uf.bo) { | |
741 | struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; | |
742 | ||
743 | /* UVD & VCE fw doesn't support user fences */ | |
744 | if (ib->ring->type == AMDGPU_RING_TYPE_UVD || | |
745 | ib->ring->type == AMDGPU_RING_TYPE_VCE) | |
746 | return -EINVAL; | |
747 | ||
748 | ib->user = &parser->uf; | |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
2b48d323 CK |
754 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
755 | struct amdgpu_cs_parser *p) | |
756 | { | |
76a1ea61 | 757 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
758 | struct amdgpu_ib *ib; |
759 | int i, j, r; | |
760 | ||
761 | if (!p->num_ibs) | |
762 | return 0; | |
763 | ||
764 | /* Add dependencies to first IB */ | |
765 | ib = &p->ibs[0]; | |
766 | for (i = 0; i < p->nchunks; ++i) { | |
767 | struct drm_amdgpu_cs_chunk_dep *deps; | |
768 | struct amdgpu_cs_chunk *chunk; | |
769 | unsigned num_deps; | |
770 | ||
771 | chunk = &p->chunks[i]; | |
772 | ||
773 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
774 | continue; | |
775 | ||
776 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
777 | num_deps = chunk->length_dw * 4 / | |
778 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
779 | ||
780 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 781 | struct amdgpu_ring *ring; |
76a1ea61 | 782 | struct amdgpu_ctx *ctx; |
21c16bf6 | 783 | struct fence *fence; |
2b48d323 CK |
784 | |
785 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
786 | deps[j].ip_instance, | |
787 | deps[j].ring, &ring); | |
788 | if (r) | |
789 | return r; | |
790 | ||
76a1ea61 CK |
791 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
792 | if (ctx == NULL) | |
793 | return -EINVAL; | |
794 | ||
21c16bf6 CK |
795 | fence = amdgpu_ctx_get_fence(ctx, ring, |
796 | deps[j].handle); | |
797 | if (IS_ERR(fence)) { | |
798 | r = PTR_ERR(fence); | |
76a1ea61 | 799 | amdgpu_ctx_put(ctx); |
2b48d323 | 800 | return r; |
91e1a520 | 801 | |
21c16bf6 CK |
802 | } else if (fence) { |
803 | r = amdgpu_sync_fence(adev, &ib->sync, fence); | |
804 | fence_put(fence); | |
805 | amdgpu_ctx_put(ctx); | |
806 | if (r) | |
807 | return r; | |
808 | } | |
2b48d323 CK |
809 | } |
810 | } | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
049fc527 | 815 | static int amdgpu_cs_parser_prepare_job(struct amdgpu_cs_parser *sched_job) |
d38ceaf9 | 816 | { |
dd01d071 | 817 | int r, i; |
049fc527 CZ |
818 | struct amdgpu_cs_parser *parser = sched_job; |
819 | struct amdgpu_device *adev = sched_job->adev; | |
dd01d071 | 820 | bool reserved_buffers = false; |
049fc527 | 821 | |
dd01d071 JZ |
822 | r = amdgpu_cs_parser_relocs(parser); |
823 | if (r) { | |
824 | if (r != -ERESTARTSYS) { | |
3ccec53c MO |
825 | if (r == -ENOMEM) |
826 | DRM_ERROR("Not enough memory for command submission!\n"); | |
827 | else | |
828 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
829 | } | |
2b48d323 CK |
830 | } |
831 | ||
832 | if (!r) { | |
3ccec53c | 833 | reserved_buffers = true; |
049fc527 | 834 | r = amdgpu_cs_ib_fill(adev, parser); |
d38ceaf9 | 835 | } |
21c16bf6 | 836 | if (!r) { |
049fc527 | 837 | r = amdgpu_cs_dependencies(adev, parser); |
21c16bf6 CK |
838 | if (r) |
839 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
840 | } | |
dd01d071 JZ |
841 | if (r) { |
842 | amdgpu_cs_parser_fini(parser, r, reserved_buffers); | |
843 | return r; | |
844 | } | |
049fc527 | 845 | |
dd01d071 JZ |
846 | for (i = 0; i < parser->num_ibs; i++) |
847 | trace_amdgpu_cs(parser, i); | |
049fc527 | 848 | |
dd01d071 JZ |
849 | r = amdgpu_cs_ib_vm_chunk(adev, parser); |
850 | return r; | |
049fc527 CZ |
851 | } |
852 | ||
853 | static struct amdgpu_ring *amdgpu_cs_parser_get_ring( | |
854 | struct amdgpu_device *adev, | |
855 | struct amdgpu_cs_parser *parser) | |
856 | { | |
857 | int i, r; | |
858 | ||
859 | struct amdgpu_cs_chunk *chunk; | |
860 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
861 | struct amdgpu_ring *ring; | |
862 | for (i = 0; i < parser->nchunks; i++) { | |
863 | chunk = &parser->chunks[i]; | |
864 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; | |
865 | ||
866 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
867 | continue; | |
868 | ||
869 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, | |
870 | chunk_ib->ip_instance, chunk_ib->ring, | |
871 | &ring); | |
872 | if (r) | |
873 | return NULL; | |
874 | break; | |
875 | } | |
876 | return ring; | |
877 | } | |
878 | ||
879 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
880 | { | |
881 | struct amdgpu_device *adev = dev->dev_private; | |
882 | union drm_amdgpu_cs *cs = data; | |
883 | struct amdgpu_cs_parser *parser; | |
884 | int r; | |
885 | ||
886 | down_read(&adev->exclusive_lock); | |
887 | if (!adev->accel_working) { | |
888 | up_read(&adev->exclusive_lock); | |
889 | return -EBUSY; | |
890 | } | |
2b48d323 | 891 | |
049fc527 CZ |
892 | parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0); |
893 | if (!parser) | |
894 | return -ENOMEM; | |
895 | r = amdgpu_cs_parser_init(parser, data); | |
d38ceaf9 | 896 | if (r) { |
049fc527 CZ |
897 | DRM_ERROR("Failed to initialize parser !\n"); |
898 | amdgpu_cs_parser_fini(parser, r, false); | |
d38ceaf9 AD |
899 | up_read(&adev->exclusive_lock); |
900 | r = amdgpu_cs_handle_lockup(adev, r); | |
901 | return r; | |
902 | } | |
903 | ||
049fc527 CZ |
904 | if (amdgpu_enable_scheduler && parser->num_ibs) { |
905 | struct amdgpu_ring * ring = | |
906 | amdgpu_cs_parser_get_ring(adev, parser); | |
4274f5d4 | 907 | if (ring->is_pte_ring || (parser->bo_list && parser->bo_list->has_userptr)) { |
049fc527 CZ |
908 | r = amdgpu_cs_parser_prepare_job(parser); |
909 | if (r) | |
910 | goto out; | |
911 | } else | |
912 | parser->prepare_job = amdgpu_cs_parser_prepare_job; | |
4b559c90 | 913 | parser->ring = ring; |
049fc527 CZ |
914 | parser->run_job = amdgpu_cs_parser_run_job; |
915 | parser->free_job = amdgpu_cs_parser_free_job; | |
f556cb0c CZ |
916 | mutex_lock(&parser->job_lock); |
917 | r = amd_sched_push_job(ring->scheduler, | |
918 | &parser->ctx->rings[ring->idx].entity, | |
919 | parser, | |
920 | &parser->s_fence); | |
921 | if (r) { | |
922 | mutex_unlock(&parser->job_lock); | |
923 | goto out; | |
924 | } | |
925 | parser->ibs[parser->num_ibs - 1].sequence = | |
926 | amdgpu_ctx_add_fence(parser->ctx, ring, | |
927 | &parser->s_fence->base, | |
928 | parser->s_fence->v_seq); | |
929 | cs->out.handle = parser->s_fence->v_seq; | |
930 | mutex_unlock(&parser->job_lock); | |
049fc527 CZ |
931 | up_read(&adev->exclusive_lock); |
932 | return 0; | |
d38ceaf9 | 933 | } |
049fc527 CZ |
934 | r = amdgpu_cs_parser_prepare_job(parser); |
935 | if (r) | |
936 | goto out; | |
d38ceaf9 | 937 | |
049fc527 | 938 | cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; |
d38ceaf9 | 939 | out: |
049fc527 | 940 | amdgpu_cs_parser_fini(parser, r, true); |
d38ceaf9 AD |
941 | up_read(&adev->exclusive_lock); |
942 | r = amdgpu_cs_handle_lockup(adev, r); | |
943 | return r; | |
944 | } | |
945 | ||
946 | /** | |
947 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
948 | * | |
949 | * @dev: drm device | |
950 | * @data: data from userspace | |
951 | * @filp: file private | |
952 | * | |
953 | * Wait for the command submission identified by handle to finish. | |
954 | */ | |
955 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
956 | struct drm_file *filp) | |
957 | { | |
958 | union drm_amdgpu_wait_cs *wait = data; | |
959 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 960 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 961 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 962 | struct amdgpu_ctx *ctx; |
21c16bf6 | 963 | struct fence *fence; |
d38ceaf9 AD |
964 | long r; |
965 | ||
21c16bf6 CK |
966 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
967 | wait->in.ring, &ring); | |
968 | if (r) | |
969 | return r; | |
970 | ||
66b3cf2a JZ |
971 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
972 | if (ctx == NULL) | |
973 | return -EINVAL; | |
d38ceaf9 | 974 | |
4b559c90 CZ |
975 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
976 | if (IS_ERR(fence)) | |
977 | r = PTR_ERR(fence); | |
978 | else if (fence) { | |
979 | r = fence_wait_timeout(fence, true, timeout); | |
980 | fence_put(fence); | |
981 | } else | |
982 | r = 1; | |
049fc527 | 983 | |
66b3cf2a | 984 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
985 | if (r < 0) |
986 | return r; | |
987 | ||
988 | memset(wait, 0, sizeof(*wait)); | |
989 | wait->out.status = (r == 0); | |
990 | ||
991 | return 0; | |
992 | } | |
993 | ||
994 | /** | |
995 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
996 | * | |
997 | * @parser: command submission parser context | |
998 | * @addr: VM address | |
999 | * @bo: resulting BO of the mapping found | |
1000 | * | |
1001 | * Search the buffer objects in the command submission context for a certain | |
1002 | * virtual memory address. Returns allocation structure when found, NULL | |
1003 | * otherwise. | |
1004 | */ | |
1005 | struct amdgpu_bo_va_mapping * | |
1006 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
1007 | uint64_t addr, struct amdgpu_bo **bo) | |
1008 | { | |
1009 | struct amdgpu_bo_list_entry *reloc; | |
1010 | struct amdgpu_bo_va_mapping *mapping; | |
1011 | ||
1012 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
1013 | ||
1014 | list_for_each_entry(reloc, &parser->validated, tv.head) { | |
1015 | if (!reloc->bo_va) | |
1016 | continue; | |
1017 | ||
7fc11959 CK |
1018 | list_for_each_entry(mapping, &reloc->bo_va->valids, list) { |
1019 | if (mapping->it.start > addr || | |
1020 | addr > mapping->it.last) | |
1021 | continue; | |
1022 | ||
1023 | *bo = reloc->bo_va->bo; | |
1024 | return mapping; | |
1025 | } | |
1026 | ||
1027 | list_for_each_entry(mapping, &reloc->bo_va->invalids, list) { | |
d38ceaf9 AD |
1028 | if (mapping->it.start > addr || |
1029 | addr > mapping->it.last) | |
1030 | continue; | |
1031 | ||
1032 | *bo = reloc->bo_va->bo; | |
1033 | return mapping; | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | return NULL; | |
1038 | } |