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Merge remote-tracking branches 'asoc/topic/wm8753', 'asoc/topic/wm8770', 'asoc/topic...
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_connectors.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_edid.h>
28#include <drm/drm_crtc_helper.h>
29#include <drm/drm_fb_helper.h>
30#include <drm/amdgpu_drm.h>
31#include "amdgpu.h"
32#include "atom.h"
33#include "atombios_encoders.h"
34#include "atombios_dp.h"
35#include "amdgpu_connectors.h"
36#include "amdgpu_i2c.h"
37
38#include <linux/pm_runtime.h>
39
40void amdgpu_connector_hotplug(struct drm_connector *connector)
41{
42 struct drm_device *dev = connector->dev;
43 struct amdgpu_device *adev = dev->dev_private;
44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
45
46 /* bail if the connector does not have hpd pin, e.g.,
47 * VGA, TV, etc.
48 */
49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
50 return;
51
52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
53
54 /* if the connector is already off, don't turn it back on */
55 if (connector->dpms != DRM_MODE_DPMS_ON)
56 return;
57
58 /* just deal with DP (not eDP) here. */
59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
60 struct amdgpu_connector_atom_dig *dig_connector =
61 amdgpu_connector->con_priv;
62
63 /* if existing sink type was not DP no need to retrain */
64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
65 return;
66
67 /* first get sink type as it may be reset after (un)plug */
68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
69 /* don't do anything if sink is not display port, i.e.,
70 * passive dp->(dvi|hdmi) adaptor
71 */
7d617264
MD		 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
75 /* Don't start link training before we have the DPCD */
76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
77 return;
a887adad 78
7d617264
MD		 79 /* Turn the connector off and back on immediately, which
80 * will trigger link training
81 */
82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
d38ceaf9
AD		 84 }
85 }
86}
87
88static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
89{
90 struct drm_crtc *crtc = encoder->crtc;
91
92 if (crtc && crtc->enabled) {
93 drm_crtc_helper_set_mode(crtc, &crtc->mode,
94 crtc->x, crtc->y, crtc->primary->fb);
95 }
96}
97
98int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
99{
100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
101 struct amdgpu_connector_atom_dig *dig_connector;
102 int bpc = 8;
103 unsigned mode_clock, max_tmds_clock;
104
105 switch (connector->connector_type) {
106 case DRM_MODE_CONNECTOR_DVII:
107 case DRM_MODE_CONNECTOR_HDMIB:
108 if (amdgpu_connector->use_digital) {
109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
110 if (connector->display_info.bpc)
111 bpc = connector->display_info.bpc;
112 }
113 }
114 break;
115 case DRM_MODE_CONNECTOR_DVID:
116 case DRM_MODE_CONNECTOR_HDMIA:
117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
118 if (connector->display_info.bpc)
119 bpc = connector->display_info.bpc;
120 }
121 break;
122 case DRM_MODE_CONNECTOR_DisplayPort:
123 dig_connector = amdgpu_connector->con_priv;
124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
127 if (connector->display_info.bpc)
128 bpc = connector->display_info.bpc;
129 }
130 break;
131 case DRM_MODE_CONNECTOR_eDP:
132 case DRM_MODE_CONNECTOR_LVDS:
133 if (connector->display_info.bpc)
134 bpc = connector->display_info.bpc;
135 else {
17b10f94 136 const struct drm_connector_helper_funcs *connector_funcs =
d38ceaf9
AD		 137 connector->helper_private;
138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
141
142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
143 bpc = 6;
144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
145 bpc = 8;
146 }
147 break;
148 }
149
150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
151 /*
152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
154 * 12 bpc is always supported on hdmi deep color sinks, as this is
155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
156 */
157 if (bpc > 12) {
158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
159 connector->name, bpc);
160 bpc = 12;
161 }
162
163 /* Any defined maximum tmds clock limit we must not exceed? */
2a272ca9 164 if (connector->display_info.max_tmds_clock > 0) {
d38ceaf9
AD		 165 /* mode_clock is clock in kHz for mode to be modeset on this connector */
166 mode_clock = amdgpu_connector->pixelclock_for_modeset;
167
168 /* Maximum allowable input clock in kHz */
2a272ca9 169 max_tmds_clock = connector->display_info.max_tmds_clock;
d38ceaf9
AD		 170
171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
172 connector->name, mode_clock, max_tmds_clock);
173
174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
177 (mode_clock * 5/4 <= max_tmds_clock))
178 bpc = 10;
179 else
180 bpc = 8;
181
182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
183 connector->name, bpc);
184 }
185
186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
187 bpc = 8;
188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
189 connector->name, bpc);
d38ceaf9 190 }
9d746ab6
MK		 191 } else if (bpc > 8) {
192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
194 connector->name);
195 bpc = 8;
d38ceaf9
AD		 196 }
197 }
198
199 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
201 connector->name);
202 bpc = 8;
203 }
204
205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
206 connector->name, connector->display_info.bpc, bpc);
207
208 return bpc;
209}
210
211static void
212amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
213 enum drm_connector_status status)
214{
215 struct drm_encoder *best_encoder = NULL;
216 struct drm_encoder *encoder = NULL;
17b10f94 217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
d38ceaf9
AD		 218 bool connected;
219 int i;
220
221 best_encoder = connector_funcs->best_encoder(connector);
222
223 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
224 if (connector->encoder_ids[i] == 0)
225 break;
226
418da172 227 encoder = drm_encoder_find(connector->dev, NULL,
d38ceaf9
AD		 228 connector->encoder_ids[i]);
229 if (!encoder)
230 continue;
231
232 if ((encoder == best_encoder) && (status == connector_status_connected))
233 connected = true;
234 else
235 connected = false;
236
237 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
238
239 }
240}
241
242static struct drm_encoder *
243amdgpu_connector_find_encoder(struct drm_connector *connector,
244 int encoder_type)
245{
246 struct drm_encoder *encoder;
247 int i;
248
249 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
250 if (connector->encoder_ids[i] == 0)
251 break;
418da172 252 encoder = drm_encoder_find(connector->dev, NULL,
d38ceaf9
AD		 253 connector->encoder_ids[i]);
254 if (!encoder)
255 continue;
256
257 if (encoder->encoder_type == encoder_type)
258 return encoder;
259 }
260 return NULL;
261}
262
263struct edid *amdgpu_connector_edid(struct drm_connector *connector)
264{
265 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
266 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
267
268 if (amdgpu_connector->edid) {
269 return amdgpu_connector->edid;
270 } else if (edid_blob) {
271 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
272 if (edid)
273 amdgpu_connector->edid = edid;
274 }
275 return amdgpu_connector->edid;
276}
277
278static struct edid *
279amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
280{
281 struct edid *edid;
282
283 if (adev->mode_info.bios_hardcoded_edid) {
284 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
285 if (edid) {
286 memcpy((unsigned char *)edid,
287 (unsigned char *)adev->mode_info.bios_hardcoded_edid,
288 adev->mode_info.bios_hardcoded_edid_size);
289 return edid;
290 }
291 }
292 return NULL;
293}
294
295static void amdgpu_connector_get_edid(struct drm_connector *connector)
296{
297 struct drm_device *dev = connector->dev;
298 struct amdgpu_device *adev = dev->dev_private;
299 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
300
301 if (amdgpu_connector->edid)
302 return;
303
304 /* on hw with routers, select right port */
305 if (amdgpu_connector->router.ddc_valid)
306 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
307
308 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
309 ENCODER_OBJECT_ID_NONE) &&
310 amdgpu_connector->ddc_bus->has_aux) {
311 amdgpu_connector->edid = drm_get_edid(connector,
312 &amdgpu_connector->ddc_bus->aux.ddc);
313 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
314 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
315 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
316
317 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
318 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
319 amdgpu_connector->ddc_bus->has_aux)
320 amdgpu_connector->edid = drm_get_edid(connector,
321 &amdgpu_connector->ddc_bus->aux.ddc);
322 else if (amdgpu_connector->ddc_bus)
323 amdgpu_connector->edid = drm_get_edid(connector,
324 &amdgpu_connector->ddc_bus->adapter);
325 } else if (amdgpu_connector->ddc_bus) {
326 amdgpu_connector->edid = drm_get_edid(connector,
327 &amdgpu_connector->ddc_bus->adapter);
328 }
329
330 if (!amdgpu_connector->edid) {
331 /* some laptops provide a hardcoded edid in rom for LCDs */
332 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
333 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
334 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
335 }
336}
337
338static void amdgpu_connector_free_edid(struct drm_connector *connector)
339{
340 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
341
c5927537
HJ		 342 kfree(amdgpu_connector->edid);
343 amdgpu_connector->edid = NULL;
d38ceaf9
AD		 344}
345
346static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
347{
348 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
349 int ret;
350
351 if (amdgpu_connector->edid) {
352 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
353 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
d38ceaf9
AD		 354 return ret;
355 }
356 drm_mode_connector_update_edid_property(connector, NULL);
357 return 0;
358}
359
360static struct drm_encoder *
361amdgpu_connector_best_single_encoder(struct drm_connector *connector)
362{
363 int enc_id = connector->encoder_ids[0];
364
365 /* pick the encoder ids */
366 if (enc_id)
418da172 367 return drm_encoder_find(connector->dev, NULL, enc_id);
d38ceaf9
AD		 368 return NULL;
369}
370
371static void amdgpu_get_native_mode(struct drm_connector *connector)
372{
373 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
374 struct amdgpu_encoder *amdgpu_encoder;
375
376 if (encoder == NULL)
377 return;
378
379 amdgpu_encoder = to_amdgpu_encoder(encoder);
380
381 if (!list_empty(&connector->probed_modes)) {
382 struct drm_display_mode *preferred_mode =
383 list_first_entry(&connector->probed_modes,
384 struct drm_display_mode, head);
385
386 amdgpu_encoder->native_mode = *preferred_mode;
387 } else {
388 amdgpu_encoder->native_mode.clock = 0;
389 }
390}
391
392static struct drm_display_mode *
393amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
394{
395 struct drm_device *dev = encoder->dev;
396 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
397 struct drm_display_mode *mode = NULL;
398 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
399
400 if (native_mode->hdisplay != 0 &&
401 native_mode->vdisplay != 0 &&
402 native_mode->clock != 0) {
403 mode = drm_mode_duplicate(dev, native_mode);
404 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
405 drm_mode_set_name(mode);
406
407 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
408 } else if (native_mode->hdisplay != 0 &&
409 native_mode->vdisplay != 0) {
410 /* mac laptops without an edid */
411 /* Note that this is not necessarily the exact panel mode,
412 * but an approximation based on the cvt formula. For these
413 * systems we should ideally read the mode info out of the
414 * registers or add a mode table, but this works and is much
415 * simpler.
416 */
417 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
418 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
419 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
420 }
421 return mode;
422}
423
424static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
425 struct drm_connector *connector)
426{
427 struct drm_device *dev = encoder->dev;
428 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
429 struct drm_display_mode *mode = NULL;
430 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
431 int i;
aeba709a 432 static const struct mode_size {
d38ceaf9
AD		 433 int w;
434 int h;
435 } common_modes[17] = {
436 { 640, 480},
437 { 720, 480},
438 { 800, 600},
439 { 848, 480},
440 {1024, 768},
441 {1152, 768},
442 {1280, 720},
443 {1280, 800},
444 {1280, 854},
445 {1280, 960},
446 {1280, 1024},
447 {1440, 900},
448 {1400, 1050},
449 {1680, 1050},
450 {1600, 1200},
451 {1920, 1080},
452 {1920, 1200}
453 };
454
455 for (i = 0; i < 17; i++) {
456 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
457 if (common_modes[i].w > 1024 ||
458 common_modes[i].h > 768)
459 continue;
460 }
461 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
462 if (common_modes[i].w > native_mode->hdisplay ||
463 common_modes[i].h > native_mode->vdisplay ||
464 (common_modes[i].w == native_mode->hdisplay &&
465 common_modes[i].h == native_mode->vdisplay))
466 continue;
467 }
468 if (common_modes[i].w < 320 || common_modes[i].h < 200)
469 continue;
470
471 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
472 drm_mode_probed_add(connector, mode);
473 }
474}
475
476static int amdgpu_connector_set_property(struct drm_connector *connector,
477 struct drm_property *property,
478 uint64_t val)
479{
480 struct drm_device *dev = connector->dev;
481 struct amdgpu_device *adev = dev->dev_private;
482 struct drm_encoder *encoder;
483 struct amdgpu_encoder *amdgpu_encoder;
484
485 if (property == adev->mode_info.coherent_mode_property) {
486 struct amdgpu_encoder_atom_dig *dig;
487 bool new_coherent_mode;
488
489 /* need to find digital encoder on connector */
490 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
491 if (!encoder)
492 return 0;
493
494 amdgpu_encoder = to_amdgpu_encoder(encoder);
495
496 if (!amdgpu_encoder->enc_priv)
497 return 0;
498
499 dig = amdgpu_encoder->enc_priv;
500 new_coherent_mode = val ? true : false;
501 if (dig->coherent_mode != new_coherent_mode) {
502 dig->coherent_mode = new_coherent_mode;
503 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
504 }
505 }
506
507 if (property == adev->mode_info.audio_property) {
508 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
509 /* need to find digital encoder on connector */
510 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
511 if (!encoder)
512 return 0;
513
514 amdgpu_encoder = to_amdgpu_encoder(encoder);
515
516 if (amdgpu_connector->audio != val) {
517 amdgpu_connector->audio = val;
518 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
519 }
520 }
521
522 if (property == adev->mode_info.dither_property) {
523 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
524 /* need to find digital encoder on connector */
525 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
526 if (!encoder)
527 return 0;
528
529 amdgpu_encoder = to_amdgpu_encoder(encoder);
530
531 if (amdgpu_connector->dither != val) {
532 amdgpu_connector->dither = val;
533 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
534 }
535 }
536
537 if (property == adev->mode_info.underscan_property) {
538 /* need to find digital encoder on connector */
539 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
540 if (!encoder)
541 return 0;
542
543 amdgpu_encoder = to_amdgpu_encoder(encoder);
544
545 if (amdgpu_encoder->underscan_type != val) {
546 amdgpu_encoder->underscan_type = val;
547 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
548 }
549 }
550
551 if (property == adev->mode_info.underscan_hborder_property) {
552 /* need to find digital encoder on connector */
553 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
554 if (!encoder)
555 return 0;
556
557 amdgpu_encoder = to_amdgpu_encoder(encoder);
558
559 if (amdgpu_encoder->underscan_hborder != val) {
560 amdgpu_encoder->underscan_hborder = val;
561 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
562 }
563 }
564
565 if (property == adev->mode_info.underscan_vborder_property) {
566 /* need to find digital encoder on connector */
567 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
568 if (!encoder)
569 return 0;
570
571 amdgpu_encoder = to_amdgpu_encoder(encoder);
572
573 if (amdgpu_encoder->underscan_vborder != val) {
574 amdgpu_encoder->underscan_vborder = val;
575 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
576 }
577 }
578
579 if (property == adev->mode_info.load_detect_property) {
580 struct amdgpu_connector *amdgpu_connector =
581 to_amdgpu_connector(connector);
582
583 if (val == 0)
584 amdgpu_connector->dac_load_detect = false;
585 else
586 amdgpu_connector->dac_load_detect = true;
587 }
588
589 if (property == dev->mode_config.scaling_mode_property) {
590 enum amdgpu_rmx_type rmx_type;
591
592 if (connector->encoder) {
593 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
594 } else {
17b10f94 595 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
d38ceaf9
AD		 596 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
597 }
598
599 switch (val) {
600 default:
601 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
602 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
603 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
604 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
605 }
606 if (amdgpu_encoder->rmx_type == rmx_type)
607 return 0;
608
609 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
610 (amdgpu_encoder->native_mode.clock == 0))
611 return 0;
612
613 amdgpu_encoder->rmx_type = rmx_type;
614
615 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
616 }
617
618 return 0;
619}
620
621static void
622amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
623 struct drm_connector *connector)
624{
625 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
626 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
627 struct drm_display_mode *t, *mode;
628
629 /* If the EDID preferred mode doesn't match the native mode, use it */
630 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
631 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
632 if (mode->hdisplay != native_mode->hdisplay ||
633 mode->vdisplay != native_mode->vdisplay)
634 memcpy(native_mode, mode, sizeof(*mode));
635 }
636 }
637
638 /* Try to get native mode details from EDID if necessary */
639 if (!native_mode->clock) {
640 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
641 if (mode->hdisplay == native_mode->hdisplay &&
642 mode->vdisplay == native_mode->vdisplay) {
643 *native_mode = *mode;
644 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
645 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
646 break;
647 }
648 }
649 }
650
651 if (!native_mode->clock) {
652 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
653 amdgpu_encoder->rmx_type = RMX_OFF;
654 }
655}
656
657static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
658{
659 struct drm_encoder *encoder;
660 int ret = 0;
661 struct drm_display_mode *mode;
662
663 amdgpu_connector_get_edid(connector);
664 ret = amdgpu_connector_ddc_get_modes(connector);
665 if (ret > 0) {
666 encoder = amdgpu_connector_best_single_encoder(connector);
667 if (encoder) {
668 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
669 /* add scaled modes */
670 amdgpu_connector_add_common_modes(encoder, connector);
671 }
672 return ret;
673 }
674
675 encoder = amdgpu_connector_best_single_encoder(connector);
676 if (!encoder)
677 return 0;
678
679 /* we have no EDID modes */
680 mode = amdgpu_connector_lcd_native_mode(encoder);
681 if (mode) {
682 ret = 1;
683 drm_mode_probed_add(connector, mode);
684 /* add the width/height from vbios tables if available */
685 connector->display_info.width_mm = mode->width_mm;
686 connector->display_info.height_mm = mode->height_mm;
687 /* add scaled modes */
688 amdgpu_connector_add_common_modes(encoder, connector);
689 }
690
691 return ret;
692}
693
694static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
695 struct drm_display_mode *mode)
696{
697 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
698
699 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
700 return MODE_PANEL;
701
702 if (encoder) {
703 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
704 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
705
706 /* AVIVO hardware supports downscaling modes larger than the panel
707 * to the panel size, but I'm not sure this is desirable.
708 */
709 if ((mode->hdisplay > native_mode->hdisplay) ||
710 (mode->vdisplay > native_mode->vdisplay))
711 return MODE_PANEL;
712
713 /* if scaling is disabled, block non-native modes */
714 if (amdgpu_encoder->rmx_type == RMX_OFF) {
715 if ((mode->hdisplay != native_mode->hdisplay) ||
716 (mode->vdisplay != native_mode->vdisplay))
717 return MODE_PANEL;
718 }
719 }
720
721 return MODE_OK;
722}
723
724static enum drm_connector_status
725amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
726{
727 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
728 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
729 enum drm_connector_status ret = connector_status_disconnected;
730 int r;
731
aa0aad57
LW		 732 if (!drm_kms_helper_is_poll_worker()) {
733 r = pm_runtime_get_sync(connector->dev->dev);
734 if (r < 0)
735 return connector_status_disconnected;
736 }
d38ceaf9
AD		 737
738 if (encoder) {
739 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
740 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
741
742 /* check if panel is valid */
743 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
744 ret = connector_status_connected;
745
746 }
747
748 /* check for edid as well */
749 amdgpu_connector_get_edid(connector);
750 if (amdgpu_connector->edid)
751 ret = connector_status_connected;
752 /* check acpi lid status ??? */
753
754 amdgpu_connector_update_scratch_regs(connector, ret);
aa0aad57
LW		 755
756 if (!drm_kms_helper_is_poll_worker()) {
757 pm_runtime_mark_last_busy(connector->dev->dev);
758 pm_runtime_put_autosuspend(connector->dev->dev);
759 }
760
d38ceaf9
AD		 761 return ret;
762}
763
40492f60 764static void amdgpu_connector_unregister(struct drm_connector *connector)
d38ceaf9
AD		 765{
766 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
767
eef2b411 768 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
d38ceaf9 769 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
2f9ba199
GI		 770 amdgpu_connector->ddc_bus->has_aux = false;
771 }
40492f60
GI		 772}
773
774static void amdgpu_connector_destroy(struct drm_connector *connector)
775{
776 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
777
d38ceaf9
AD		 778 amdgpu_connector_free_edid(connector);
779 kfree(amdgpu_connector->con_priv);
780 drm_connector_unregister(connector);
781 drm_connector_cleanup(connector);
782 kfree(connector);
783}
784
785static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
786 struct drm_property *property,
787 uint64_t value)
788{
789 struct drm_device *dev = connector->dev;
790 struct amdgpu_encoder *amdgpu_encoder;
791 enum amdgpu_rmx_type rmx_type;
792
793 DRM_DEBUG_KMS("\n");
794 if (property != dev->mode_config.scaling_mode_property)
795 return 0;
796
797 if (connector->encoder)
798 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
799 else {
17b10f94 800 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
d38ceaf9
AD		 801 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
802 }
803
804 switch (value) {
805 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
806 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
807 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
808 default:
809 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
810 }
811 if (amdgpu_encoder->rmx_type == rmx_type)
812 return 0;
813
814 amdgpu_encoder->rmx_type = rmx_type;
815
816 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
817 return 0;
818}
819
820
821static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
822 .get_modes = amdgpu_connector_lvds_get_modes,
823 .mode_valid = amdgpu_connector_lvds_mode_valid,
824 .best_encoder = amdgpu_connector_best_single_encoder,
825};
826
827static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
828 .dpms = drm_helper_connector_dpms,
829 .detect = amdgpu_connector_lvds_detect,
830 .fill_modes = drm_helper_probe_single_connector_modes,
40492f60 831 .early_unregister = amdgpu_connector_unregister,
d38ceaf9
AD		 832 .destroy = amdgpu_connector_destroy,
833 .set_property = amdgpu_connector_set_lcd_property,
834};
835
836static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
837{
838 int ret;
839
840 amdgpu_connector_get_edid(connector);
841 ret = amdgpu_connector_ddc_get_modes(connector);
842
843 return ret;
844}
845
846static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
847 struct drm_display_mode *mode)
848{
849 struct drm_device *dev = connector->dev;
850 struct amdgpu_device *adev = dev->dev_private;
851
852 /* XXX check mode bandwidth */
853
854 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
855 return MODE_CLOCK_HIGH;
856
857 return MODE_OK;
858}
859
860static enum drm_connector_status
861amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
862{
863 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
864 struct drm_encoder *encoder;
17b10f94 865 const struct drm_encoder_helper_funcs *encoder_funcs;
d38ceaf9
AD		 866 bool dret = false;
867 enum drm_connector_status ret = connector_status_disconnected;
868 int r;
869
aa0aad57
LW		 870 if (!drm_kms_helper_is_poll_worker()) {
871 r = pm_runtime_get_sync(connector->dev->dev);
872 if (r < 0)
873 return connector_status_disconnected;
874 }
d38ceaf9
AD		 875
876 encoder = amdgpu_connector_best_single_encoder(connector);
877 if (!encoder)
878 ret = connector_status_disconnected;
879
880 if (amdgpu_connector->ddc_bus)
881 dret = amdgpu_ddc_probe(amdgpu_connector, false);
882 if (dret) {
883 amdgpu_connector->detected_by_load = false;
884 amdgpu_connector_free_edid(connector);
885 amdgpu_connector_get_edid(connector);
886
887 if (!amdgpu_connector->edid) {
888 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
889 connector->name);
890 ret = connector_status_connected;
891 } else {
892 amdgpu_connector->use_digital =
893 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
894
895 /* some oems have boards with separate digital and analog connectors
896 * with a shared ddc line (often vga + hdmi)
897 */
898 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
899 amdgpu_connector_free_edid(connector);
900 ret = connector_status_disconnected;
901 } else {
902 ret = connector_status_connected;
903 }
904 }
905 } else {
906
907 /* if we aren't forcing don't do destructive polling */
908 if (!force) {
909 /* only return the previous status if we last
910 * detected a monitor via load.
911 */
912 if (amdgpu_connector->detected_by_load)
913 ret = connector->status;
914 goto out;
915 }
916
917 if (amdgpu_connector->dac_load_detect && encoder) {
918 encoder_funcs = encoder->helper_private;
919 ret = encoder_funcs->detect(encoder, connector);
920 if (ret != connector_status_disconnected)
921 amdgpu_connector->detected_by_load = true;
922 }
923 }
924
925 amdgpu_connector_update_scratch_regs(connector, ret);
926
927out:
aa0aad57
LW		 928 if (!drm_kms_helper_is_poll_worker()) {
929 pm_runtime_mark_last_busy(connector->dev->dev);
930 pm_runtime_put_autosuspend(connector->dev->dev);
931 }
d38ceaf9
AD		 932
933 return ret;
934}
935
936static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
937 .get_modes = amdgpu_connector_vga_get_modes,
938 .mode_valid = amdgpu_connector_vga_mode_valid,
939 .best_encoder = amdgpu_connector_best_single_encoder,
940};
941
942static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
943 .dpms = drm_helper_connector_dpms,
944 .detect = amdgpu_connector_vga_detect,
945 .fill_modes = drm_helper_probe_single_connector_modes,
40492f60 946 .early_unregister = amdgpu_connector_unregister,
d38ceaf9
AD		 947 .destroy = amdgpu_connector_destroy,
948 .set_property = amdgpu_connector_set_property,
949};
950
951static bool
952amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
953{
954 struct drm_device *dev = connector->dev;
955 struct amdgpu_device *adev = dev->dev_private;
956 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
957 enum drm_connector_status status;
958
959 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
960 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
961 status = connector_status_connected;
962 else
963 status = connector_status_disconnected;
964 if (connector->status == status)
965 return true;
966 }
967
968 return false;
969}
970
971/*
972 * DVI is complicated
973 * Do a DDC probe, if DDC probe passes, get the full EDID so
974 * we can do analog/digital monitor detection at this point.
975 * If the monitor is an analog monitor or we got no DDC,
976 * we need to find the DAC encoder object for this connector.
977 * If we got no DDC, we do load detection on the DAC encoder object.
978 * If we got analog DDC or load detection passes on the DAC encoder
979 * we have to check if this analog encoder is shared with anyone else (TV)
980 * if its shared we have to set the other connector to disconnected.
981 */
982static enum drm_connector_status
983amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
984{
985 struct drm_device *dev = connector->dev;
986 struct amdgpu_device *adev = dev->dev_private;
987 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
988 struct drm_encoder *encoder = NULL;
17b10f94 989 const struct drm_encoder_helper_funcs *encoder_funcs;
d38ceaf9
AD		 990 int i, r;
991 enum drm_connector_status ret = connector_status_disconnected;
992 bool dret = false, broken_edid = false;
993
aa0aad57
LW		 994 if (!drm_kms_helper_is_poll_worker()) {
995 r = pm_runtime_get_sync(connector->dev->dev);
996 if (r < 0)
997 return connector_status_disconnected;
998 }
d38ceaf9
AD		 999
1000 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1001 ret = connector->status;
1002 goto exit;
1003 }
1004
1005 if (amdgpu_connector->ddc_bus)
1006 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1007 if (dret) {
1008 amdgpu_connector->detected_by_load = false;
1009 amdgpu_connector_free_edid(connector);
1010 amdgpu_connector_get_edid(connector);
1011
1012 if (!amdgpu_connector->edid) {
1013 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1014 connector->name);
1015 ret = connector_status_connected;
1016 broken_edid = true; /* defer use_digital to later */
1017 } else {
1018 amdgpu_connector->use_digital =
1019 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1020
1021 /* some oems have boards with separate digital and analog connectors
1022 * with a shared ddc line (often vga + hdmi)
1023 */
1024 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1025 amdgpu_connector_free_edid(connector);
1026 ret = connector_status_disconnected;
1027 } else {
1028 ret = connector_status_connected;
1029 }
1030
1031 /* This gets complicated. We have boards with VGA + HDMI with a
1032 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1033 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1034 * you don't really know what's connected to which port as both are digital.
1035 */
1036 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1037 struct drm_connector *list_connector;
1038 struct amdgpu_connector *list_amdgpu_connector;
1039 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1040 if (connector == list_connector)
1041 continue;
1042 list_amdgpu_connector = to_amdgpu_connector(list_connector);
1043 if (list_amdgpu_connector->shared_ddc &&
1044 (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1045 amdgpu_connector->ddc_bus->rec.i2c_id)) {
1046 /* cases where both connectors are digital */
1047 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1048 /* hpd is our only option in this case */
1049 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1050 amdgpu_connector_free_edid(connector);
1051 ret = connector_status_disconnected;
1052 }
1053 }
1054 }
1055 }
1056 }
1057 }
1058 }
1059
1060 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1061 goto out;
1062
1063 /* DVI-D and HDMI-A are digital only */
1064 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1065 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1066 goto out;
1067
1068 /* if we aren't forcing don't do destructive polling */
1069 if (!force) {
1070 /* only return the previous status if we last
1071 * detected a monitor via load.
1072 */
1073 if (amdgpu_connector->detected_by_load)
1074 ret = connector->status;
1075 goto out;
1076 }
1077
1078 /* find analog encoder */
1079 if (amdgpu_connector->dac_load_detect) {
1080 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1081 if (connector->encoder_ids[i] == 0)
1082 break;
1083
418da172 1084 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
d38ceaf9
AD		 1085 if (!encoder)
1086 continue;
1087
1088 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1089 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1090 continue;
1091
1092 encoder_funcs = encoder->helper_private;
1093 if (encoder_funcs->detect) {
1094 if (!broken_edid) {
1095 if (ret != connector_status_connected) {
1096 /* deal with analog monitors without DDC */
1097 ret = encoder_funcs->detect(encoder, connector);
1098 if (ret == connector_status_connected) {
1099 amdgpu_connector->use_digital = false;
1100 }
1101 if (ret != connector_status_disconnected)
1102 amdgpu_connector->detected_by_load = true;
1103 }
1104 } else {
1105 enum drm_connector_status lret;
1106 /* assume digital unless load detected otherwise */
1107 amdgpu_connector->use_digital = true;
1108 lret = encoder_funcs->detect(encoder, connector);
1109 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1110 if (lret == connector_status_connected)
1111 amdgpu_connector->use_digital = false;
1112 }
1113 break;
1114 }
1115 }
1116 }
1117
1118out:
1119 /* updated in get modes as well since we need to know if it's analog or digital */
1120 amdgpu_connector_update_scratch_regs(connector, ret);
1121
1122exit:
aa0aad57
LW		 1123 if (!drm_kms_helper_is_poll_worker()) {
1124 pm_runtime_mark_last_busy(connector->dev->dev);
1125 pm_runtime_put_autosuspend(connector->dev->dev);
1126 }
d38ceaf9
AD		 1127
1128 return ret;
1129}
1130
1131/* okay need to be smart in here about which encoder to pick */
1132static struct drm_encoder *
1133amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1134{
1135 int enc_id = connector->encoder_ids[0];
1136 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1137 struct drm_encoder *encoder;
1138 int i;
1139 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1140 if (connector->encoder_ids[i] == 0)
1141 break;
1142
418da172 1143 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
d38ceaf9
AD		 1144 if (!encoder)
1145 continue;
1146
1147 if (amdgpu_connector->use_digital == true) {
1148 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1149 return encoder;
1150 } else {
1151 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1152 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1153 return encoder;
1154 }
1155 }
1156
1157 /* see if we have a default encoder TODO */
1158
1159 /* then check use digitial */
1160 /* pick the first one */
1161 if (enc_id)
418da172 1162 return drm_encoder_find(connector->dev, NULL, enc_id);
d38ceaf9
AD		 1163 return NULL;
1164}
1165
1166static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1167{
1168 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1169 if (connector->force == DRM_FORCE_ON)
1170 amdgpu_connector->use_digital = false;
1171 if (connector->force == DRM_FORCE_ON_DIGITAL)
1172 amdgpu_connector->use_digital = true;
1173}
1174
1175static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1176 struct drm_display_mode *mode)
1177{
1178 struct drm_device *dev = connector->dev;
1179 struct amdgpu_device *adev = dev->dev_private;
1180 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1181
1182 /* XXX check mode bandwidth */
1183
1184 if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1185 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1186 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1187 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1188 return MODE_OK;
1189 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1190 /* HDMI 1.3+ supports max clock of 340 Mhz */
1191 if (mode->clock > 340000)
1192 return MODE_CLOCK_HIGH;
1193 else
1194 return MODE_OK;
1195 } else {
1196 return MODE_CLOCK_HIGH;
1197 }
1198 }
1199
1200 /* check against the max pixel clock */
1201 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1202 return MODE_CLOCK_HIGH;
1203
1204 return MODE_OK;
1205}
1206
1207static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1208 .get_modes = amdgpu_connector_vga_get_modes,
1209 .mode_valid = amdgpu_connector_dvi_mode_valid,
1210 .best_encoder = amdgpu_connector_dvi_encoder,
1211};
1212
1213static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1214 .dpms = drm_helper_connector_dpms,
1215 .detect = amdgpu_connector_dvi_detect,
1216 .fill_modes = drm_helper_probe_single_connector_modes,
1217 .set_property = amdgpu_connector_set_property,
40492f60 1218 .early_unregister = amdgpu_connector_unregister,
d38ceaf9
AD		 1219 .destroy = amdgpu_connector_destroy,
1220 .force = amdgpu_connector_dvi_force,
1221};
1222
1223static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1224{
1225 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1226 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1227 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1228 int ret;
1229
1230 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1231 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1232 struct drm_display_mode *mode;
1233
1234 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1235 if (!amdgpu_dig_connector->edp_on)
1236 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1237 ATOM_TRANSMITTER_ACTION_POWER_ON);
1238 amdgpu_connector_get_edid(connector);
1239 ret = amdgpu_connector_ddc_get_modes(connector);
1240 if (!amdgpu_dig_connector->edp_on)
1241 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1242 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1243 } else {
1244 /* need to setup ddc on the bridge */
1245 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1246 ENCODER_OBJECT_ID_NONE) {
1247 if (encoder)
1248 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1249 }
1250 amdgpu_connector_get_edid(connector);
1251 ret = amdgpu_connector_ddc_get_modes(connector);
1252 }
1253
1254 if (ret > 0) {
1255 if (encoder) {
1256 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1257 /* add scaled modes */
1258 amdgpu_connector_add_common_modes(encoder, connector);
1259 }
1260 return ret;
1261 }
1262
1263 if (!encoder)
1264 return 0;
1265
1266 /* we have no EDID modes */
1267 mode = amdgpu_connector_lcd_native_mode(encoder);
1268 if (mode) {
1269 ret = 1;
1270 drm_mode_probed_add(connector, mode);
1271 /* add the width/height from vbios tables if available */
1272 connector->display_info.width_mm = mode->width_mm;
1273 connector->display_info.height_mm = mode->height_mm;
1274 /* add scaled modes */
1275 amdgpu_connector_add_common_modes(encoder, connector);
1276 }
1277 } else {
1278 /* need to setup ddc on the bridge */
1279 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1280 ENCODER_OBJECT_ID_NONE) {
1281 if (encoder)
1282 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1283 }
1284 amdgpu_connector_get_edid(connector);
1285 ret = amdgpu_connector_ddc_get_modes(connector);
1286
1287 amdgpu_get_native_mode(connector);
1288 }
1289
1290 return ret;
1291}
1292
1293u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1294{
1295 struct drm_encoder *encoder;
1296 struct amdgpu_encoder *amdgpu_encoder;
1297 int i;
1298
1299 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1300 if (connector->encoder_ids[i] == 0)
1301 break;
1302
418da172 1303 encoder = drm_encoder_find(connector->dev, NULL,
d38ceaf9
AD		 1304 connector->encoder_ids[i]);
1305 if (!encoder)
1306 continue;
1307
1308 amdgpu_encoder = to_amdgpu_encoder(encoder);
1309
1310 switch (amdgpu_encoder->encoder_id) {
1311 case ENCODER_OBJECT_ID_TRAVIS:
1312 case ENCODER_OBJECT_ID_NUTMEG:
1313 return amdgpu_encoder->encoder_id;
1314 default:
1315 break;
1316 }
1317 }
1318
1319 return ENCODER_OBJECT_ID_NONE;
1320}
1321
1322static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1323{
1324 struct drm_encoder *encoder;
1325 struct amdgpu_encoder *amdgpu_encoder;
1326 int i;
1327 bool found = false;
1328
1329 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1330 if (connector->encoder_ids[i] == 0)
1331 break;
418da172 1332 encoder = drm_encoder_find(connector->dev, NULL,
d38ceaf9
AD		 1333 connector->encoder_ids[i]);
1334 if (!encoder)
1335 continue;
1336
1337 amdgpu_encoder = to_amdgpu_encoder(encoder);
1338 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1339 found = true;
1340 }
1341
1342 return found;
1343}
1344
1345bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1346{
1347 struct drm_device *dev = connector->dev;
1348 struct amdgpu_device *adev = dev->dev_private;
1349
1350 if ((adev->clock.default_dispclk >= 53900) &&
1351 amdgpu_connector_encoder_is_hbr2(connector)) {
1352 return true;
1353 }
1354
1355 return false;
1356}
1357
1358static enum drm_connector_status
1359amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1360{
1361 struct drm_device *dev = connector->dev;
1362 struct amdgpu_device *adev = dev->dev_private;
1363 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1364 enum drm_connector_status ret = connector_status_disconnected;
1365 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1366 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1367 int r;
1368
aa0aad57
LW		 1369 if (!drm_kms_helper_is_poll_worker()) {
1370 r = pm_runtime_get_sync(connector->dev->dev);
1371 if (r < 0)
1372 return connector_status_disconnected;
1373 }
d38ceaf9
AD		 1374
1375 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1376 ret = connector->status;
1377 goto out;
1378 }
1379
1380 amdgpu_connector_free_edid(connector);
1381
1382 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1383 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1384 if (encoder) {
1385 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1386 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1387
1388 /* check if panel is valid */
1389 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1390 ret = connector_status_connected;
1391 }
1392 /* eDP is always DP */
1393 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1394 if (!amdgpu_dig_connector->edp_on)
1395 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1396 ATOM_TRANSMITTER_ACTION_POWER_ON);
1397 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1398 ret = connector_status_connected;
1399 if (!amdgpu_dig_connector->edp_on)
1400 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1401 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1402 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1403 ENCODER_OBJECT_ID_NONE) {
1404 /* DP bridges are always DP */
1405 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1406 /* get the DPCD from the bridge */
1407 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1408
1409 if (encoder) {
1410 /* setup ddc on the bridge */
1411 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1412 /* bridge chips are always aux */
1413 if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1414 ret = connector_status_connected;
1415 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
17b10f94 1416 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d38ceaf9
AD		 1417 ret = encoder_funcs->detect(encoder, connector);
1418 }
1419 }
1420 } else {
1421 amdgpu_dig_connector->dp_sink_type =
1422 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1423 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1424 ret = connector_status_connected;
1425 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1426 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1427 } else {
1428 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1429 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1430 ret = connector_status_connected;
1431 } else {
1432 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1433 if (amdgpu_ddc_probe(amdgpu_connector, false))
1434 ret = connector_status_connected;
1435 }
1436 }
1437 }
1438
1439 amdgpu_connector_update_scratch_regs(connector, ret);
1440out:
aa0aad57
LW		 1441 if (!drm_kms_helper_is_poll_worker()) {
1442 pm_runtime_mark_last_busy(connector->dev->dev);
1443 pm_runtime_put_autosuspend(connector->dev->dev);
1444 }
d38ceaf9
AD		 1445
1446 return ret;
1447}
1448
1449static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1450 struct drm_display_mode *mode)
1451{
1452 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1453 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1454
1455 /* XXX check mode bandwidth */
1456
1457 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1458 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1459 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1460
1461 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1462 return MODE_PANEL;
1463
1464 if (encoder) {
1465 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1466 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1467
1468 /* AVIVO hardware supports downscaling modes larger than the panel
1469 * to the panel size, but I'm not sure this is desirable.
1470 */
1471 if ((mode->hdisplay > native_mode->hdisplay) ||
1472 (mode->vdisplay > native_mode->vdisplay))
1473 return MODE_PANEL;
1474
1475 /* if scaling is disabled, block non-native modes */
1476 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1477 if ((mode->hdisplay != native_mode->hdisplay) ||
1478 (mode->vdisplay != native_mode->vdisplay))
1479 return MODE_PANEL;
1480 }
1481 }
1482 return MODE_OK;
1483 } else {
1484 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1485 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1486 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1487 } else {
1488 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1489 /* HDMI 1.3+ supports max clock of 340 Mhz */
1490 if (mode->clock > 340000)
1491 return MODE_CLOCK_HIGH;
1492 } else {
1493 if (mode->clock > 165000)
1494 return MODE_CLOCK_HIGH;
1495 }
1496 }
1497 }
1498
1499 return MODE_OK;
1500}
1501
1502static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1503 .get_modes = amdgpu_connector_dp_get_modes,
1504 .mode_valid = amdgpu_connector_dp_mode_valid,
1505 .best_encoder = amdgpu_connector_dvi_encoder,
1506};
1507
1508static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1509 .dpms = drm_helper_connector_dpms,
1510 .detect = amdgpu_connector_dp_detect,
1511 .fill_modes = drm_helper_probe_single_connector_modes,
1512 .set_property = amdgpu_connector_set_property,
40492f60 1513 .early_unregister = amdgpu_connector_unregister,
d38ceaf9
AD		 1514 .destroy = amdgpu_connector_destroy,
1515 .force = amdgpu_connector_dvi_force,
1516};
1517
1518static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1519 .dpms = drm_helper_connector_dpms,
1520 .detect = amdgpu_connector_dp_detect,
1521 .fill_modes = drm_helper_probe_single_connector_modes,
1522 .set_property = amdgpu_connector_set_lcd_property,
40492f60 1523 .early_unregister = amdgpu_connector_unregister,
d38ceaf9
AD		 1524 .destroy = amdgpu_connector_destroy,
1525 .force = amdgpu_connector_dvi_force,
1526};
1527
1528void
1529amdgpu_connector_add(struct amdgpu_device *adev,
1530 uint32_t connector_id,
1531 uint32_t supported_device,
1532 int connector_type,
1533 struct amdgpu_i2c_bus_rec *i2c_bus,
1534 uint16_t connector_object_id,
1535 struct amdgpu_hpd *hpd,
1536 struct amdgpu_router *router)
1537{
1538 struct drm_device *dev = adev->ddev;
1539 struct drm_connector *connector;
1540 struct amdgpu_connector *amdgpu_connector;
1541 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1542 struct drm_encoder *encoder;
1543 struct amdgpu_encoder *amdgpu_encoder;
1544 uint32_t subpixel_order = SubPixelNone;
1545 bool shared_ddc = false;
1546 bool is_dp_bridge = false;
1547 bool has_aux = false;
1548
1549 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1550 return;
1551
1552 /* see if we already added it */
1553 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1554 amdgpu_connector = to_amdgpu_connector(connector);
1555 if (amdgpu_connector->connector_id == connector_id) {
1556 amdgpu_connector->devices |= supported_device;
1557 return;
1558 }
1559 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1560 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1561 amdgpu_connector->shared_ddc = true;
1562 shared_ddc = true;
1563 }
1564 if (amdgpu_connector->router_bus && router->ddc_valid &&
1565 (amdgpu_connector->router.router_id == router->router_id)) {
1566 amdgpu_connector->shared_ddc = false;
1567 shared_ddc = false;
1568 }
1569 }
1570 }
1571
1572 /* check if it's a dp bridge */
1573 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1574 amdgpu_encoder = to_amdgpu_encoder(encoder);
1575 if (amdgpu_encoder->devices & supported_device) {
1576 switch (amdgpu_encoder->encoder_id) {
1577 case ENCODER_OBJECT_ID_TRAVIS:
1578 case ENCODER_OBJECT_ID_NUTMEG:
1579 is_dp_bridge = true;
1580 break;
1581 default:
1582 break;
1583 }
1584 }
1585 }
1586
1587 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1588 if (!amdgpu_connector)
1589 return;
1590
1591 connector = &amdgpu_connector->base;
1592
1593 amdgpu_connector->connector_id = connector_id;
1594 amdgpu_connector->devices = supported_device;
1595 amdgpu_connector->shared_ddc = shared_ddc;
1596 amdgpu_connector->connector_object_id = connector_object_id;
1597 amdgpu_connector->hpd = *hpd;
1598
1599 amdgpu_connector->router = *router;
1600 if (router->ddc_valid || router->cd_valid) {
1601 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1602 if (!amdgpu_connector->router_bus)
1603 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1604 }
1605
1606 if (is_dp_bridge) {
1607 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1608 if (!amdgpu_dig_connector)
1609 goto failed;
1610 amdgpu_connector->con_priv = amdgpu_dig_connector;
1611 if (i2c_bus->valid) {
1612 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1613 if (amdgpu_connector->ddc_bus)
1614 has_aux = true;
1615 else
1616 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1617 }
1618 switch (connector_type) {
1619 case DRM_MODE_CONNECTOR_VGA:
1620 case DRM_MODE_CONNECTOR_DVIA:
1621 default:
1622 drm_connector_init(dev, &amdgpu_connector->base,
1623 &amdgpu_connector_dp_funcs, connector_type);
1624 drm_connector_helper_add(&amdgpu_connector->base,
1625 &amdgpu_connector_dp_helper_funcs);
1626 connector->interlace_allowed = true;
1627 connector->doublescan_allowed = true;
1628 amdgpu_connector->dac_load_detect = true;
1629 drm_object_attach_property(&amdgpu_connector->base.base,
1630 adev->mode_info.load_detect_property,
1631 1);
1632 drm_object_attach_property(&amdgpu_connector->base.base,
1633 dev->mode_config.scaling_mode_property,
1634 DRM_MODE_SCALE_NONE);
1635 break;
1636 case DRM_MODE_CONNECTOR_DVII:
1637 case DRM_MODE_CONNECTOR_DVID:
1638 case DRM_MODE_CONNECTOR_HDMIA:
1639 case DRM_MODE_CONNECTOR_HDMIB:
1640 case DRM_MODE_CONNECTOR_DisplayPort:
1641 drm_connector_init(dev, &amdgpu_connector->base,
1642 &amdgpu_connector_dp_funcs, connector_type);
1643 drm_connector_helper_add(&amdgpu_connector->base,
1644 &amdgpu_connector_dp_helper_funcs);
1645 drm_object_attach_property(&amdgpu_connector->base.base,
1646 adev->mode_info.underscan_property,
1647 UNDERSCAN_OFF);
1648 drm_object_attach_property(&amdgpu_connector->base.base,
1649 adev->mode_info.underscan_hborder_property,
1650 0);
1651 drm_object_attach_property(&amdgpu_connector->base.base,
1652 adev->mode_info.underscan_vborder_property,
1653 0);
1654
1655 drm_object_attach_property(&amdgpu_connector->base.base,
1656 dev->mode_config.scaling_mode_property,
1657 DRM_MODE_SCALE_NONE);
1658
1659 drm_object_attach_property(&amdgpu_connector->base.base,
1660 adev->mode_info.dither_property,
1661 AMDGPU_FMT_DITHER_DISABLE);
1662
1663 if (amdgpu_audio != 0)
1664 drm_object_attach_property(&amdgpu_connector->base.base,
1665 adev->mode_info.audio_property,
1666 AMDGPU_AUDIO_AUTO);
1667
1668 subpixel_order = SubPixelHorizontalRGB;
1669 connector->interlace_allowed = true;
1670 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1671 connector->doublescan_allowed = true;
1672 else
1673 connector->doublescan_allowed = false;
1674 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1675 amdgpu_connector->dac_load_detect = true;
1676 drm_object_attach_property(&amdgpu_connector->base.base,
1677 adev->mode_info.load_detect_property,
1678 1);
1679 }
1680 break;
1681 case DRM_MODE_CONNECTOR_LVDS:
1682 case DRM_MODE_CONNECTOR_eDP:
1683 drm_connector_init(dev, &amdgpu_connector->base,
1684 &amdgpu_connector_edp_funcs, connector_type);
1685 drm_connector_helper_add(&amdgpu_connector->base,
1686 &amdgpu_connector_dp_helper_funcs);
1687 drm_object_attach_property(&amdgpu_connector->base.base,
1688 dev->mode_config.scaling_mode_property,
1689 DRM_MODE_SCALE_FULLSCREEN);
1690 subpixel_order = SubPixelHorizontalRGB;
1691 connector->interlace_allowed = false;
1692 connector->doublescan_allowed = false;
1693 break;
1694 }
1695 } else {
1696 switch (connector_type) {
1697 case DRM_MODE_CONNECTOR_VGA:
1698 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1699 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1700 if (i2c_bus->valid) {
1701 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1702 if (!amdgpu_connector->ddc_bus)
1703 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1704 }
1705 amdgpu_connector->dac_load_detect = true;
1706 drm_object_attach_property(&amdgpu_connector->base.base,
1707 adev->mode_info.load_detect_property,
1708 1);
1709 drm_object_attach_property(&amdgpu_connector->base.base,
1710 dev->mode_config.scaling_mode_property,
1711 DRM_MODE_SCALE_NONE);
1712 /* no HPD on analog connectors */
1713 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
d38ceaf9
AD		 1714 connector->interlace_allowed = true;
1715 connector->doublescan_allowed = true;
1716 break;
1717 case DRM_MODE_CONNECTOR_DVIA:
1718 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1719 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1720 if (i2c_bus->valid) {
1721 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1722 if (!amdgpu_connector->ddc_bus)
1723 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1724 }
1725 amdgpu_connector->dac_load_detect = true;
1726 drm_object_attach_property(&amdgpu_connector->base.base,
1727 adev->mode_info.load_detect_property,
1728 1);
1729 drm_object_attach_property(&amdgpu_connector->base.base,
1730 dev->mode_config.scaling_mode_property,
1731 DRM_MODE_SCALE_NONE);
1732 /* no HPD on analog connectors */
1733 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1734 connector->interlace_allowed = true;
1735 connector->doublescan_allowed = true;
1736 break;
1737 case DRM_MODE_CONNECTOR_DVII:
1738 case DRM_MODE_CONNECTOR_DVID:
1739 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1740 if (!amdgpu_dig_connector)
1741 goto failed;
1742 amdgpu_connector->con_priv = amdgpu_dig_connector;
1743 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1744 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1745 if (i2c_bus->valid) {
1746 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1747 if (!amdgpu_connector->ddc_bus)
1748 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1749 }
1750 subpixel_order = SubPixelHorizontalRGB;
1751 drm_object_attach_property(&amdgpu_connector->base.base,
1752 adev->mode_info.coherent_mode_property,
1753 1);
1754 drm_object_attach_property(&amdgpu_connector->base.base,
1755 adev->mode_info.underscan_property,
1756 UNDERSCAN_OFF);
1757 drm_object_attach_property(&amdgpu_connector->base.base,
1758 adev->mode_info.underscan_hborder_property,
1759 0);
1760 drm_object_attach_property(&amdgpu_connector->base.base,
1761 adev->mode_info.underscan_vborder_property,
1762 0);
1763 drm_object_attach_property(&amdgpu_connector->base.base,
1764 dev->mode_config.scaling_mode_property,
1765 DRM_MODE_SCALE_NONE);
1766
1767 if (amdgpu_audio != 0) {
1768 drm_object_attach_property(&amdgpu_connector->base.base,
1769 adev->mode_info.audio_property,
1770 AMDGPU_AUDIO_AUTO);
1771 }
1772 drm_object_attach_property(&amdgpu_connector->base.base,
1773 adev->mode_info.dither_property,
1774 AMDGPU_FMT_DITHER_DISABLE);
1775 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1776 amdgpu_connector->dac_load_detect = true;
1777 drm_object_attach_property(&amdgpu_connector->base.base,
1778 adev->mode_info.load_detect_property,
1779 1);
1780 }
1781 connector->interlace_allowed = true;
1782 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1783 connector->doublescan_allowed = true;
1784 else
1785 connector->doublescan_allowed = false;
1786 break;
1787 case DRM_MODE_CONNECTOR_HDMIA:
1788 case DRM_MODE_CONNECTOR_HDMIB:
1789 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1790 if (!amdgpu_dig_connector)
1791 goto failed;
1792 amdgpu_connector->con_priv = amdgpu_dig_connector;
1793 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1794 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1795 if (i2c_bus->valid) {
1796 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1797 if (!amdgpu_connector->ddc_bus)
1798 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1799 }
1800 drm_object_attach_property(&amdgpu_connector->base.base,
1801 adev->mode_info.coherent_mode_property,
1802 1);
1803 drm_object_attach_property(&amdgpu_connector->base.base,
1804 adev->mode_info.underscan_property,
1805 UNDERSCAN_OFF);
1806 drm_object_attach_property(&amdgpu_connector->base.base,
1807 adev->mode_info.underscan_hborder_property,
1808 0);
1809 drm_object_attach_property(&amdgpu_connector->base.base,
1810 adev->mode_info.underscan_vborder_property,
1811 0);
1812 drm_object_attach_property(&amdgpu_connector->base.base,
1813 dev->mode_config.scaling_mode_property,
1814 DRM_MODE_SCALE_NONE);
1815 if (amdgpu_audio != 0) {
1816 drm_object_attach_property(&amdgpu_connector->base.base,
1817 adev->mode_info.audio_property,
1818 AMDGPU_AUDIO_AUTO);
1819 }
1820 drm_object_attach_property(&amdgpu_connector->base.base,
1821 adev->mode_info.dither_property,
1822 AMDGPU_FMT_DITHER_DISABLE);
1823 subpixel_order = SubPixelHorizontalRGB;
1824 connector->interlace_allowed = true;
1825 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1826 connector->doublescan_allowed = true;
1827 else
1828 connector->doublescan_allowed = false;
1829 break;
1830 case DRM_MODE_CONNECTOR_DisplayPort:
1831 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1832 if (!amdgpu_dig_connector)
1833 goto failed;
1834 amdgpu_connector->con_priv = amdgpu_dig_connector;
1835 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1836 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1837 if (i2c_bus->valid) {
1838 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1839 if (amdgpu_connector->ddc_bus)
1840 has_aux = true;
1841 else
1842 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1843 }
1844 subpixel_order = SubPixelHorizontalRGB;
1845 drm_object_attach_property(&amdgpu_connector->base.base,
1846 adev->mode_info.coherent_mode_property,
1847 1);
1848 drm_object_attach_property(&amdgpu_connector->base.base,
1849 adev->mode_info.underscan_property,
1850 UNDERSCAN_OFF);
1851 drm_object_attach_property(&amdgpu_connector->base.base,
1852 adev->mode_info.underscan_hborder_property,
1853 0);
1854 drm_object_attach_property(&amdgpu_connector->base.base,
1855 adev->mode_info.underscan_vborder_property,
1856 0);
1857 drm_object_attach_property(&amdgpu_connector->base.base,
1858 dev->mode_config.scaling_mode_property,
1859 DRM_MODE_SCALE_NONE);
1860 if (amdgpu_audio != 0) {
1861 drm_object_attach_property(&amdgpu_connector->base.base,
1862 adev->mode_info.audio_property,
1863 AMDGPU_AUDIO_AUTO);
1864 }
1865 drm_object_attach_property(&amdgpu_connector->base.base,
1866 adev->mode_info.dither_property,
1867 AMDGPU_FMT_DITHER_DISABLE);
1868 connector->interlace_allowed = true;
1869 /* in theory with a DP to VGA converter... */
1870 connector->doublescan_allowed = false;
1871 break;
1872 case DRM_MODE_CONNECTOR_eDP:
1873 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1874 if (!amdgpu_dig_connector)
1875 goto failed;
1876 amdgpu_connector->con_priv = amdgpu_dig_connector;
1877 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1878 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1879 if (i2c_bus->valid) {
1880 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1881 if (amdgpu_connector->ddc_bus)
1882 has_aux = true;
1883 else
1884 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1885 }
1886 drm_object_attach_property(&amdgpu_connector->base.base,
1887 dev->mode_config.scaling_mode_property,
1888 DRM_MODE_SCALE_FULLSCREEN);
1889 subpixel_order = SubPixelHorizontalRGB;
1890 connector->interlace_allowed = false;
1891 connector->doublescan_allowed = false;
1892 break;
1893 case DRM_MODE_CONNECTOR_LVDS:
1894 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1895 if (!amdgpu_dig_connector)
1896 goto failed;
1897 amdgpu_connector->con_priv = amdgpu_dig_connector;
1898 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1899 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1900 if (i2c_bus->valid) {
1901 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1902 if (!amdgpu_connector->ddc_bus)
1903 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1904 }
1905 drm_object_attach_property(&amdgpu_connector->base.base,
1906 dev->mode_config.scaling_mode_property,
1907 DRM_MODE_SCALE_FULLSCREEN);
1908 subpixel_order = SubPixelHorizontalRGB;
1909 connector->interlace_allowed = false;
1910 connector->doublescan_allowed = false;
1911 break;
1912 }
1913 }
1914
1915 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
b636a1b3
L		 1916 if (i2c_bus->valid) {
1917 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1918 DRM_CONNECTOR_POLL_DISCONNECT;
1919 }
d38ceaf9
AD		 1920 } else
1921 connector->polled = DRM_CONNECTOR_POLL_HPD;
1922
1923 connector->display_info.subpixel_order = subpixel_order;
1924 drm_connector_register(connector);
1925
1926 if (has_aux)
1927 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1928
1929 return;
1930
1931failed:
1932 drm_connector_cleanup(connector);
1933 kfree(connector);
1934}
Linux 6.x block layer and io_uring tree(s)