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Merge remote-tracking branches 'asoc/topic/fsl-spdif', 'asoc/topic/hdmi', 'asoc/topic...
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cgs.c
CommitLineData
d03846af
CZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
57ff96cf
CZ		 24#include <linux/list.h>
25#include <linux/slab.h>
97cb7f6e 26#include <linux/pci.h>
3f1d35a0 27#include <linux/acpi.h>
57ff96cf 28#include <drm/drmP.h>
bf3911b0 29#include <linux/firmware.h>
57ff96cf 30#include <drm/amdgpu_drm.h>
d03846af
CZ		 31#include "amdgpu.h"
32#include "cgs_linux.h"
25da4427 33#include "atom.h"
bf3911b0
JZ		 34#include "amdgpu_ucode.h"
35
d03846af
CZ		 36struct amdgpu_cgs_device {
37 struct cgs_device base;
38 struct amdgpu_device *adev;
39};
40
41#define CGS_FUNC_ADEV \
42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev
44
110e6f26 45static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
d03846af
CZ		 46 uint64_t *mc_start, uint64_t *mc_size,
47 uint64_t *mem_size)
48{
57ff96cf
CZ		 49 CGS_FUNC_ADEV;
50 switch(type) {
51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
52 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
53 *mc_start = 0;
54 *mc_size = adev->mc.visible_vram_size;
55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
56 break;
57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
59 *mc_start = adev->mc.visible_vram_size;
60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
61 *mem_size = *mc_size;
62 break;
63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
65 *mc_start = adev->mc.gtt_start;
66 *mc_size = adev->mc.gtt_size;
67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
68 break;
69 default:
70 return -EINVAL;
71 }
72
d03846af
CZ		 73 return 0;
74}
75
110e6f26 76static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
d03846af
CZ		 77 uint64_t size,
78 uint64_t min_offset, uint64_t max_offset,
79 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
80{
57ff96cf
CZ		 81 CGS_FUNC_ADEV;
82 int ret;
83 struct amdgpu_bo *bo;
84 struct page *kmem_page = vmalloc_to_page(kmem);
85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
86
87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
72d7668b 89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
57ff96cf
CZ		 90 if (ret)
91 return ret;
92 ret = amdgpu_bo_reserve(bo, false);
93 if (unlikely(ret != 0))
94 return ret;
95
96 /* pin buffer into GTT */
97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
98 min_offset, max_offset, mcaddr);
99 amdgpu_bo_unreserve(bo);
100
101 *kmem_handle = (cgs_handle_t)bo;
102 return ret;
d03846af
CZ		 103}
104
110e6f26 105static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
d03846af 106{
57ff96cf
CZ		 107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
108
109 if (obj) {
110 int r = amdgpu_bo_reserve(obj, false);
111 if (likely(r == 0)) {
112 amdgpu_bo_unpin(obj);
113 amdgpu_bo_unreserve(obj);
114 }
115 amdgpu_bo_unref(&obj);
116
117 }
d03846af
CZ		 118 return 0;
119}
120
110e6f26 121static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
d03846af
CZ		 122 enum cgs_gpu_mem_type type,
123 uint64_t size, uint64_t align,
124 uint64_t min_offset, uint64_t max_offset,
125 cgs_handle_t *handle)
126{
57ff96cf
CZ		 127 CGS_FUNC_ADEV;
128 uint16_t flags = 0;
129 int ret = 0;
130 uint32_t domain = 0;
131 struct amdgpu_bo *obj;
132 struct ttm_placement placement;
133 struct ttm_place place;
134
135 if (min_offset > max_offset) {
136 BUG_ON(1);
137 return -EINVAL;
138 }
139
140 /* fail if the alignment is not a power of 2 */
141 if (((align != 1) && (align & (align - 1)))
142 || size == 0 || align == 0)
143 return -EINVAL;
144
145
146 switch(type) {
147 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
148 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
149 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
150 domain = AMDGPU_GEM_DOMAIN_VRAM;
151 if (max_offset > adev->mc.real_vram_size)
152 return -EINVAL;
153 place.fpfn = min_offset >> PAGE_SHIFT;
154 place.lpfn = max_offset >> PAGE_SHIFT;
155 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
156 TTM_PL_FLAG_VRAM;
157 break;
158 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
159 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
160 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
161 domain = AMDGPU_GEM_DOMAIN_VRAM;
162 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
163 place.fpfn =
164 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
165 place.lpfn =
166 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
167 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
168 TTM_PL_FLAG_VRAM;
169 }
170
171 break;
172 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
173 domain = AMDGPU_GEM_DOMAIN_GTT;
174 place.fpfn = min_offset >> PAGE_SHIFT;
175 place.lpfn = max_offset >> PAGE_SHIFT;
176 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
177 break;
178 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
179 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
180 domain = AMDGPU_GEM_DOMAIN_GTT;
181 place.fpfn = min_offset >> PAGE_SHIFT;
182 place.lpfn = max_offset >> PAGE_SHIFT;
183 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
184 TTM_PL_FLAG_UNCACHED;
185 break;
186 default:
187 return -EINVAL;
188 }
189
190
191 *handle = 0;
192
193 placement.placement = &place;
194 placement.num_placement = 1;
195 placement.busy_placement = &place;
196 placement.num_busy_placement = 1;
197
198 ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
199 true, domain, flags,
72d7668b
CK		 200 NULL, &placement, NULL,
201 &obj);
57ff96cf
CZ		 202 if (ret) {
203 DRM_ERROR("(%d) bo create failed\n", ret);
204 return ret;
205 }
206 *handle = (cgs_handle_t)obj;
207
208 return ret;
d03846af
CZ		 209}
210
110e6f26 211static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
d03846af 212{
57ff96cf
CZ		 213 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
214
215 if (obj) {
216 int r = amdgpu_bo_reserve(obj, false);
217 if (likely(r == 0)) {
218 amdgpu_bo_kunmap(obj);
219 amdgpu_bo_unpin(obj);
220 amdgpu_bo_unreserve(obj);
221 }
222 amdgpu_bo_unref(&obj);
223
224 }
d03846af
CZ		 225 return 0;
226}
227
110e6f26 228static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
d03846af
CZ		 229 uint64_t *mcaddr)
230{
57ff96cf
CZ		 231 int r;
232 u64 min_offset, max_offset;
233 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
234
235 WARN_ON_ONCE(obj->placement.num_placement > 1);
236
237 min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
238 max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
239
240 r = amdgpu_bo_reserve(obj, false);
241 if (unlikely(r != 0))
242 return r;
243 r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT,
244 min_offset, max_offset, mcaddr);
245 amdgpu_bo_unreserve(obj);
246 return r;
d03846af
CZ		 247}
248
110e6f26 249static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
d03846af 250{
57ff96cf
CZ		 251 int r;
252 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
253 r = amdgpu_bo_reserve(obj, false);
254 if (unlikely(r != 0))
255 return r;
256 r = amdgpu_bo_unpin(obj);
257 amdgpu_bo_unreserve(obj);
258 return r;
d03846af
CZ		 259}
260
110e6f26 261static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
d03846af
CZ		 262 void **map)
263{
57ff96cf
CZ		 264 int r;
265 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
266 r = amdgpu_bo_reserve(obj, false);
267 if (unlikely(r != 0))
268 return r;
269 r = amdgpu_bo_kmap(obj, map);
270 amdgpu_bo_unreserve(obj);
271 return r;
d03846af
CZ		 272}
273
110e6f26 274static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
d03846af 275{
57ff96cf
CZ		 276 int r;
277 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
278 r = amdgpu_bo_reserve(obj, false);
279 if (unlikely(r != 0))
280 return r;
281 amdgpu_bo_kunmap(obj);
282 amdgpu_bo_unreserve(obj);
283 return r;
d03846af
CZ		 284}
285
110e6f26 286static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
d03846af 287{
aba684d8
CZ		 288 CGS_FUNC_ADEV;
289 return RREG32(offset);
d03846af
CZ		 290}
291
110e6f26 292static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
d03846af
CZ		 293 uint32_t value)
294{
aba684d8
CZ		 295 CGS_FUNC_ADEV;
296 WREG32(offset, value);
d03846af
CZ		 297}
298
110e6f26 299static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
d03846af
CZ		 300 enum cgs_ind_reg space,
301 unsigned index)
302{
aba684d8
CZ		 303 CGS_FUNC_ADEV;
304 switch (space) {
305 case CGS_IND_REG__MMIO:
306 return RREG32_IDX(index);
307 case CGS_IND_REG__PCIE:
308 return RREG32_PCIE(index);
309 case CGS_IND_REG__SMC:
310 return RREG32_SMC(index);
311 case CGS_IND_REG__UVD_CTX:
312 return RREG32_UVD_CTX(index);
313 case CGS_IND_REG__DIDT:
314 return RREG32_DIDT(index);
315 case CGS_IND_REG__AUDIO_ENDPT:
316 DRM_ERROR("audio endpt register access not implemented.\n");
317 return 0;
318 }
319 WARN(1, "Invalid indirect register space");
d03846af
CZ		 320 return 0;
321}
322
110e6f26 323static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
d03846af
CZ		 324 enum cgs_ind_reg space,
325 unsigned index, uint32_t value)
326{
aba684d8
CZ		 327 CGS_FUNC_ADEV;
328 switch (space) {
329 case CGS_IND_REG__MMIO:
330 return WREG32_IDX(index, value);
331 case CGS_IND_REG__PCIE:
332 return WREG32_PCIE(index, value);
333 case CGS_IND_REG__SMC:
334 return WREG32_SMC(index, value);
335 case CGS_IND_REG__UVD_CTX:
336 return WREG32_UVD_CTX(index, value);
337 case CGS_IND_REG__DIDT:
338 return WREG32_DIDT(index, value);
339 case CGS_IND_REG__AUDIO_ENDPT:
340 DRM_ERROR("audio endpt register access not implemented.\n");
341 return;
342 }
343 WARN(1, "Invalid indirect register space");
d03846af
CZ		 344}
345
110e6f26 346static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
d03846af 347{
97cb7f6e
CZ		 348 CGS_FUNC_ADEV;
349 uint8_t val;
350 int ret = pci_read_config_byte(adev->pdev, addr, &val);
351 if (WARN(ret, "pci_read_config_byte error"))
352 return 0;
353 return val;
d03846af
CZ		 354}
355
110e6f26 356static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
d03846af 357{
97cb7f6e
CZ		 358 CGS_FUNC_ADEV;
359 uint16_t val;
360 int ret = pci_read_config_word(adev->pdev, addr, &val);
361 if (WARN(ret, "pci_read_config_word error"))
362 return 0;
363 return val;
d03846af
CZ		 364}
365
110e6f26 366static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
d03846af
CZ		 367 unsigned addr)
368{
97cb7f6e
CZ		 369 CGS_FUNC_ADEV;
370 uint32_t val;
371 int ret = pci_read_config_dword(adev->pdev, addr, &val);
372 if (WARN(ret, "pci_read_config_dword error"))
373 return 0;
374 return val;
d03846af
CZ		 375}
376
110e6f26 377static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 378 uint8_t value)
379{
97cb7f6e
CZ		 380 CGS_FUNC_ADEV;
381 int ret = pci_write_config_byte(adev->pdev, addr, value);
382 WARN(ret, "pci_write_config_byte error");
d03846af
CZ		 383}
384
110e6f26 385static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 386 uint16_t value)
387{
97cb7f6e
CZ		 388 CGS_FUNC_ADEV;
389 int ret = pci_write_config_word(adev->pdev, addr, value);
390 WARN(ret, "pci_write_config_word error");
d03846af
CZ		 391}
392
110e6f26 393static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
d03846af
CZ		 394 uint32_t value)
395{
97cb7f6e
CZ		 396 CGS_FUNC_ADEV;
397 int ret = pci_write_config_dword(adev->pdev, addr, value);
398 WARN(ret, "pci_write_config_dword error");
d03846af
CZ		 399}
400
ba228ac8 401
110e6f26 402static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
ba228ac8
AD		 403 enum cgs_resource_type resource_type,
404 uint64_t size,
405 uint64_t offset,
406 uint64_t *resource_base)
407{
408 CGS_FUNC_ADEV;
409
410 if (resource_base == NULL)
411 return -EINVAL;
412
413 switch (resource_type) {
414 case CGS_RESOURCE_TYPE_MMIO:
415 if (adev->rmmio_size == 0)
416 return -ENOENT;
417 if ((offset + size) > adev->rmmio_size)
418 return -EINVAL;
419 *resource_base = adev->rmmio_base;
420 return 0;
421 case CGS_RESOURCE_TYPE_DOORBELL:
422 if (adev->doorbell.size == 0)
423 return -ENOENT;
424 if ((offset + size) > adev->doorbell.size)
425 return -EINVAL;
426 *resource_base = adev->doorbell.base;
427 return 0;
428 case CGS_RESOURCE_TYPE_FB:
429 case CGS_RESOURCE_TYPE_IO:
430 case CGS_RESOURCE_TYPE_ROM:
431 default:
432 return -EINVAL;
433 }
434}
435
110e6f26 436static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
d03846af
CZ		 437 unsigned table, uint16_t *size,
438 uint8_t *frev, uint8_t *crev)
439{
25da4427
CZ		 440 CGS_FUNC_ADEV;
441 uint16_t data_start;
442
443 if (amdgpu_atom_parse_data_header(
444 adev->mode_info.atom_context, table, size,
445 frev, crev, &data_start))
446 return (uint8_t*)adev->mode_info.atom_context->bios +
447 data_start;
448
d03846af
CZ		 449 return NULL;
450}
451
110e6f26 452static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
d03846af
CZ		 453 uint8_t *frev, uint8_t *crev)
454{
25da4427
CZ		 455 CGS_FUNC_ADEV;
456
457 if (amdgpu_atom_parse_cmd_header(
458 adev->mode_info.atom_context, table,
459 frev, crev))
460 return 0;
461
462 return -EINVAL;
d03846af
CZ		 463}
464
110e6f26 465static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
d03846af
CZ		 466 void *args)
467{
25da4427 468 CGS_FUNC_ADEV;
d03846af 469
25da4427
CZ		 470 return amdgpu_atom_execute_table(
471 adev->mode_info.atom_context, table, args);
472}
d03846af 473
110e6f26 474static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
d03846af
CZ		 475{
476 /* TODO */
477 return 0;
478}
479
110e6f26 480static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
d03846af
CZ		 481{
482 /* TODO */
483 return 0;
484}
485
110e6f26 486static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 487 int active)
488{
489 /* TODO */
490 return 0;
491}
492
110e6f26 493static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 494 enum cgs_clock clock, unsigned freq)
495{
496 /* TODO */
497 return 0;
498}
499
110e6f26 500static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
d03846af
CZ		 501 enum cgs_engine engine, int powered)
502{
503 /* TODO */
504 return 0;
505}
506
507
508
110e6f26 509static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
d03846af
CZ		 510 enum cgs_clock clock,
511 struct cgs_clock_limits *limits)
512{
513 /* TODO */
514 return 0;
515}
516
110e6f26 517static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
d03846af
CZ		 518 const uint32_t *voltages)
519{
520 DRM_ERROR("not implemented");
521 return -EPERM;
522}
523
0cf3be21
AD		 524struct cgs_irq_params {
525 unsigned src_id;
526 cgs_irq_source_set_func_t set;
527 cgs_irq_handler_func_t handler;
528 void *private_data;
529};
530
531static int cgs_set_irq_state(struct amdgpu_device *adev,
532 struct amdgpu_irq_src *src,
533 unsigned type,
534 enum amdgpu_interrupt_state state)
535{
536 struct cgs_irq_params *irq_params =
537 (struct cgs_irq_params *)src->data;
538 if (!irq_params)
539 return -EINVAL;
540 if (!irq_params->set)
541 return -EINVAL;
542 return irq_params->set(irq_params->private_data,
543 irq_params->src_id,
544 type,
545 (int)state);
546}
547
548static int cgs_process_irq(struct amdgpu_device *adev,
549 struct amdgpu_irq_src *source,
550 struct amdgpu_iv_entry *entry)
551{
552 struct cgs_irq_params *irq_params =
553 (struct cgs_irq_params *)source->data;
554 if (!irq_params)
555 return -EINVAL;
556 if (!irq_params->handler)
557 return -EINVAL;
558 return irq_params->handler(irq_params->private_data,
559 irq_params->src_id,
560 entry->iv_entry);
561}
562
563static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
564 .set = cgs_set_irq_state,
565 .process = cgs_process_irq,
566};
567
110e6f26 568static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id,
d03846af
CZ		 569 unsigned num_types,
570 cgs_irq_source_set_func_t set,
571 cgs_irq_handler_func_t handler,
572 void *private_data)
573{
0cf3be21
AD		 574 CGS_FUNC_ADEV;
575 int ret = 0;
576 struct cgs_irq_params *irq_params;
577 struct amdgpu_irq_src *source =
578 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
579 if (!source)
580 return -ENOMEM;
581 irq_params =
582 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
583 if (!irq_params) {
584 kfree(source);
585 return -ENOMEM;
586 }
587 source->num_types = num_types;
588 source->funcs = &cgs_irq_funcs;
589 irq_params->src_id = src_id;
590 irq_params->set = set;
591 irq_params->handler = handler;
592 irq_params->private_data = private_data;
593 source->data = (void *)irq_params;
594 ret = amdgpu_irq_add_id(adev, src_id, source);
595 if (ret) {
596 kfree(irq_params);
597 kfree(source);
598 }
599
600 return ret;
d03846af
CZ		 601}
602
110e6f26 603static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
d03846af 604{
0cf3be21
AD		 605 CGS_FUNC_ADEV;
606 return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
d03846af
CZ		 607}
608
110e6f26 609static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
d03846af 610{
0cf3be21
AD		 611 CGS_FUNC_ADEV;
612 return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
d03846af
CZ		 613}
614
110e6f26 615int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
404b2fa3 616 enum amd_ip_block_type block_type,
617 enum amd_clockgating_state state)
618{
619 CGS_FUNC_ADEV;
620 int i, r = -1;
621
622 for (i = 0; i < adev->num_ip_blocks; i++) {
623 if (!adev->ip_block_status[i].valid)
624 continue;
625
626 if (adev->ip_blocks[i].type == block_type) {
627 r = adev->ip_blocks[i].funcs->set_clockgating_state(
628 (void *)adev,
629 state);
630 break;
631 }
632 }
633 return r;
634}
635
110e6f26 636int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
404b2fa3 637 enum amd_ip_block_type block_type,
638 enum amd_powergating_state state)
639{
640 CGS_FUNC_ADEV;
641 int i, r = -1;
642
643 for (i = 0; i < adev->num_ip_blocks; i++) {
644 if (!adev->ip_block_status[i].valid)
645 continue;
646
647 if (adev->ip_blocks[i].type == block_type) {
648 r = adev->ip_blocks[i].funcs->set_powergating_state(
649 (void *)adev,
650 state);
651 break;
652 }
653 }
654 return r;
655}
656
657
110e6f26 658static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
bf3911b0
JZ		 659{
660 CGS_FUNC_ADEV;
661 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
662
663 switch (fw_type) {
664 case CGS_UCODE_ID_SDMA0:
665 result = AMDGPU_UCODE_ID_SDMA0;
666 break;
667 case CGS_UCODE_ID_SDMA1:
668 result = AMDGPU_UCODE_ID_SDMA1;
669 break;
670 case CGS_UCODE_ID_CP_CE:
671 result = AMDGPU_UCODE_ID_CP_CE;
672 break;
673 case CGS_UCODE_ID_CP_PFP:
674 result = AMDGPU_UCODE_ID_CP_PFP;
675 break;
676 case CGS_UCODE_ID_CP_ME:
677 result = AMDGPU_UCODE_ID_CP_ME;
678 break;
679 case CGS_UCODE_ID_CP_MEC:
680 case CGS_UCODE_ID_CP_MEC_JT1:
681 result = AMDGPU_UCODE_ID_CP_MEC1;
682 break;
683 case CGS_UCODE_ID_CP_MEC_JT2:
2cc0c0b5
FC		 684 if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11
685 || adev->asic_type == CHIP_POLARIS10)
bf3911b0 686 result = AMDGPU_UCODE_ID_CP_MEC2;
c8172625 687 else
bf3911b0
JZ		 688 result = AMDGPU_UCODE_ID_CP_MEC1;
689 break;
690 case CGS_UCODE_ID_RLC_G:
691 result = AMDGPU_UCODE_ID_RLC_G;
692 break;
693 default:
694 DRM_ERROR("Firmware type not supported\n");
695 }
696 return result;
697}
698
a392746a
ML		 699static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
700{
701 CGS_FUNC_ADEV;
702 if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
703 release_firmware(adev->pm.fw);
704 return 0;
705 }
706 /* cannot release other firmware because they are not created by cgs */
707 return -EINVAL;
708}
709
110e6f26 710static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
bf3911b0
JZ		 711 enum cgs_ucode_id type,
712 struct cgs_firmware_info *info)
713{
714 CGS_FUNC_ADEV;
715
735f002b 716 if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
bf3911b0
JZ		 717 uint64_t gpu_addr;
718 uint32_t data_size;
719 const struct gfx_firmware_header_v1_0 *header;
720 enum AMDGPU_UCODE_ID id;
721 struct amdgpu_firmware_info *ucode;
722
723 id = fw_type_convert(cgs_device, type);
724 ucode = &adev->firmware.ucode[id];
725 if (ucode->fw == NULL)
726 return -EINVAL;
727
728 gpu_addr = ucode->mc_addr;
729 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
730 data_size = le32_to_cpu(header->header.ucode_size_bytes);
731
732 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
733 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
734 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
735 data_size = le32_to_cpu(header->jt_size) << 2;
736 }
737 info->mc_addr = gpu_addr;
738 info->image_size = data_size;
739 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
740 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
741 } else {
742 char fw_name[30] = {0};
743 int err = 0;
744 uint32_t ucode_size;
745 uint32_t ucode_start_address;
746 const uint8_t *src;
747 const struct smc_firmware_header_v1_0 *hdr;
748
0b45541d
ML		 749 if (!adev->pm.fw) {
750 switch (adev->asic_type) {
751 case CHIP_TONGA:
752 strcpy(fw_name, "amdgpu/tonga_smc.bin");
753 break;
754 case CHIP_FIJI:
755 strcpy(fw_name, "amdgpu/fiji_smc.bin");
756 break;
757 case CHIP_POLARIS11:
758 if (type == CGS_UCODE_ID_SMU)
759 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
760 else if (type == CGS_UCODE_ID_SMU_SK)
761 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
762 break;
763 case CHIP_POLARIS10:
764 if (type == CGS_UCODE_ID_SMU)
765 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
766 else if (type == CGS_UCODE_ID_SMU_SK)
767 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
768 break;
769 default:
770 DRM_ERROR("SMC firmware not supported\n");
771 return -EINVAL;
772 }
773
774 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
775 if (err) {
776 DRM_ERROR("Failed to request firmware\n");
777 return err;
778 }
779
780 err = amdgpu_ucode_validate(adev->pm.fw);
781 if (err) {
782 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
783 release_firmware(adev->pm.fw);
784 adev->pm.fw = NULL;
785 return err;
786 }
bf3911b0
JZ		 787 }
788
789 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
790 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
791 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
792 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
793 src = (const uint8_t *)(adev->pm.fw->data +
794 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
795
796 info->version = adev->pm.fw_version;
797 info->image_size = ucode_size;
798 info->kptr = (void *)src;
799 }
800 return 0;
801}
802
110e6f26 803static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
5e618699
RZ		 804 struct cgs_system_info *sys_info)
805{
806 CGS_FUNC_ADEV;
807
808 if (NULL == sys_info)
809 return -ENODEV;
810
811 if (sizeof(struct cgs_system_info) != sys_info->size)
812 return -ENODEV;
813
814 switch (sys_info->info_id) {
815 case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
816 sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
817 break;
cfd316d5
AD		 818 case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
819 sys_info->value = adev->pm.pcie_gen_mask;
820 break;
821 case CGS_SYSTEM_INFO_PCIE_MLW:
822 sys_info->value = adev->pm.pcie_mlw_mask;
823 break;
08d33408
AD		 824 case CGS_SYSTEM_INFO_CG_FLAGS:
825 sys_info->value = adev->cg_flags;
826 break;
827 case CGS_SYSTEM_INFO_PG_FLAGS:
828 sys_info->value = adev->pg_flags;
829 break;
bacec898 830 case CGS_SYSTEM_INFO_GFX_CU_INFO:
7dae69a2 831 sys_info->value = adev->gfx.cu_info.number;
bacec898 832 break;
5e618699
RZ		 833 default:
834 return -ENODEV;
835 }
836
837 return 0;
838}
839
110e6f26 840static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
47bf18b5
RZ		 841 struct cgs_display_info *info)
842{
843 CGS_FUNC_ADEV;
844 struct amdgpu_crtc *amdgpu_crtc;
845 struct drm_device *ddev = adev->ddev;
846 struct drm_crtc *crtc;
847 uint32_t line_time_us, vblank_lines;
f9e9c08e 848 struct cgs_mode_info *mode_info;
47bf18b5
RZ		 849
850 if (info == NULL)
851 return -EINVAL;
852
f9e9c08e
RZ		 853 mode_info = info->mode_info;
854
47bf18b5
RZ		 855 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
856 list_for_each_entry(crtc,
857 &ddev->mode_config.crtc_list, head) {
858 amdgpu_crtc = to_amdgpu_crtc(crtc);
859 if (crtc->enabled) {
860 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
861 info->display_count++;
862 }
f9e9c08e 863 if (mode_info != NULL &&
47bf18b5
RZ		 864 crtc->enabled && amdgpu_crtc->enabled &&
865 amdgpu_crtc->hw_mode.clock) {
866 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
867 amdgpu_crtc->hw_mode.clock;
868 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
869 amdgpu_crtc->hw_mode.crtc_vdisplay +
870 (amdgpu_crtc->v_border * 2);
f9e9c08e
RZ		 871 mode_info->vblank_time_us = vblank_lines * line_time_us;
872 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
873 mode_info->ref_clock = adev->clock.spll.reference_freq;
874 mode_info = NULL;
47bf18b5
RZ		 875 }
876 }
877 }
878
879 return 0;
880}
881
4c90080b 882
110e6f26 883static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
4c90080b
RZ		 884{
885 CGS_FUNC_ADEV;
886
887 adev->pm.dpm_enabled = enabled;
888
889 return 0;
890}
891
3f1d35a0
RZ		 892/** \brief evaluate acpi namespace object, handle or pathname must be valid
893 * \param cgs_device
894 * \param info input/output arguments for the control method
895 * \return status
896 */
897
898#if defined(CONFIG_ACPI)
110e6f26 899static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
3f1d35a0
RZ		 900 struct cgs_acpi_method_info *info)
901{
902 CGS_FUNC_ADEV;
903 acpi_handle handle;
904 struct acpi_object_list input;
905 struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
906 union acpi_object *params = NULL;
907 union acpi_object *obj = NULL;
908 uint8_t name[5] = {'\0'};
909 struct cgs_acpi_method_argument *argument = NULL;
910 uint32_t i, count;
911 acpi_status status;
29b9c528 912 int result = 0;
3f1d35a0
RZ		 913 uint32_t func_no = 0xFFFFFFFF;
914
915 handle = ACPI_HANDLE(&adev->pdev->dev);
916 if (!handle)
917 return -ENODEV;
918
919 memset(&input, 0, sizeof(struct acpi_object_list));
920
921 /* validate input info */
922 if (info->size != sizeof(struct cgs_acpi_method_info))
923 return -EINVAL;
924
925 input.count = info->input_count;
926 if (info->input_count > 0) {
927 if (info->pinput_argument == NULL)
928 return -EINVAL;
b92c26d1
DC		 929 argument = info->pinput_argument;
930 func_no = argument->value;
931 for (i = 0; i < info->input_count; i++) {
932 if (((argument->type == ACPI_TYPE_STRING) ||
933 (argument->type == ACPI_TYPE_BUFFER)) &&
934 (argument->pointer == NULL))
935 return -EINVAL;
936 argument++;
937 }
3f1d35a0
RZ		 938 }
939
940 if (info->output_count > 0) {
941 if (info->poutput_argument == NULL)
942 return -EINVAL;
943 argument = info->poutput_argument;
944 for (i = 0; i < info->output_count; i++) {
945 if (((argument->type == ACPI_TYPE_STRING) ||
946 (argument->type == ACPI_TYPE_BUFFER))
947 && (argument->pointer == NULL))
948 return -EINVAL;
949 argument++;
950 }
951 }
952
953 /* The path name passed to acpi_evaluate_object should be null terminated */
954 if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
955 strncpy(name, (char *)&(info->name), sizeof(uint32_t));
956 name[4] = '\0';
957 }
958
959 /* parse input parameters */
960 if (input.count > 0) {
961 input.pointer = params =
962 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
963 if (params == NULL)
964 return -EINVAL;
965
966 argument = info->pinput_argument;
967
968 for (i = 0; i < input.count; i++) {
969 params->type = argument->type;
970 switch (params->type) {
971 case ACPI_TYPE_INTEGER:
972 params->integer.value = argument->value;
973 break;
974 case ACPI_TYPE_STRING:
975 params->string.length = argument->method_length;
976 params->string.pointer = argument->pointer;
977 break;
978 case ACPI_TYPE_BUFFER:
979 params->buffer.length = argument->method_length;
980 params->buffer.pointer = argument->pointer;
981 break;
982 default:
983 break;
984 }
985 params++;
986 argument++;
987 }
988 }
989
990 /* parse output info */
991 count = info->output_count;
992 argument = info->poutput_argument;
993
994 /* evaluate the acpi method */
995 status = acpi_evaluate_object(handle, name, &input, &output);
996
997 if (ACPI_FAILURE(status)) {
998 result = -EIO;
999 goto error;
1000 }
1001
1002 /* return the output info */
1003 obj = output.pointer;
1004
1005 if (count > 1) {
1006 if ((obj->type != ACPI_TYPE_PACKAGE) ||
1007 (obj->package.count != count)) {
1008 result = -EIO;
1009 goto error;
1010 }
1011 params = obj->package.elements;
1012 } else
1013 params = obj;
1014
1015 if (params == NULL) {
1016 result = -EIO;
1017 goto error;
1018 }
1019
1020 for (i = 0; i < count; i++) {
1021 if (argument->type != params->type) {
1022 result = -EIO;
1023 goto error;
1024 }
1025 switch (params->type) {
1026 case ACPI_TYPE_INTEGER:
1027 argument->value = params->integer.value;
1028 break;
1029 case ACPI_TYPE_STRING:
1030 if ((params->string.length != argument->data_length) ||
1031 (params->string.pointer == NULL)) {
1032 result = -EIO;
1033 goto error;
1034 }
1035 strncpy(argument->pointer,
1036 params->string.pointer,
1037 params->string.length);
1038 break;
1039 case ACPI_TYPE_BUFFER:
1040 if (params->buffer.pointer == NULL) {
1041 result = -EIO;
1042 goto error;
1043 }
1044 memcpy(argument->pointer,
1045 params->buffer.pointer,
1046 argument->data_length);
1047 break;
1048 default:
1049 break;
1050 }
1051 argument++;
1052 params++;
1053 }
1054
1055error:
1056 if (obj != NULL)
1057 kfree(obj);
1058 kfree((void *)input.pointer);
1059 return result;
1060}
1061#else
110e6f26 1062static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
3f1d35a0
RZ		 1063 struct cgs_acpi_method_info *info)
1064{
1065 return -EIO;
1066}
1067#endif
1068
110e6f26 1069int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
3f1d35a0
RZ		 1070 uint32_t acpi_method,
1071 uint32_t acpi_function,
1072 void *pinput, void *poutput,
1073 uint32_t output_count,
1074 uint32_t input_size,
1075 uint32_t output_size)
1076{
1077 struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
1078 struct cgs_acpi_method_argument acpi_output = {0};
1079 struct cgs_acpi_method_info info = {0};
1080
1081 acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
1082 acpi_input[0].method_length = sizeof(uint32_t);
1083 acpi_input[0].data_length = sizeof(uint32_t);
1084 acpi_input[0].value = acpi_function;
1085
1086 acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
1087 acpi_input[1].method_length = CGS_ACPI_MAX_BUFFER_SIZE;
1088 acpi_input[1].data_length = input_size;
1089 acpi_input[1].pointer = pinput;
1090
1091 acpi_output.type = CGS_ACPI_TYPE_BUFFER;
1092 acpi_output.method_length = CGS_ACPI_MAX_BUFFER_SIZE;
1093 acpi_output.data_length = output_size;
1094 acpi_output.pointer = poutput;
1095
1096 info.size = sizeof(struct cgs_acpi_method_info);
1097 info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
1098 info.input_count = 2;
1099 info.name = acpi_method;
1100 info.pinput_argument = acpi_input;
1101 info.output_count = output_count;
1102 info.poutput_argument = &acpi_output;
1103
1104 return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
1105}
1106
d03846af
CZ		 1107static const struct cgs_ops amdgpu_cgs_ops = {
1108 amdgpu_cgs_gpu_mem_info,
1109 amdgpu_cgs_gmap_kmem,
1110 amdgpu_cgs_gunmap_kmem,
1111 amdgpu_cgs_alloc_gpu_mem,
1112 amdgpu_cgs_free_gpu_mem,
1113 amdgpu_cgs_gmap_gpu_mem,
1114 amdgpu_cgs_gunmap_gpu_mem,
1115 amdgpu_cgs_kmap_gpu_mem,
1116 amdgpu_cgs_kunmap_gpu_mem,
1117 amdgpu_cgs_read_register,
1118 amdgpu_cgs_write_register,
1119 amdgpu_cgs_read_ind_register,
1120 amdgpu_cgs_write_ind_register,
1121 amdgpu_cgs_read_pci_config_byte,
1122 amdgpu_cgs_read_pci_config_word,
1123 amdgpu_cgs_read_pci_config_dword,
1124 amdgpu_cgs_write_pci_config_byte,
1125 amdgpu_cgs_write_pci_config_word,
1126 amdgpu_cgs_write_pci_config_dword,
ba228ac8 1127 amdgpu_cgs_get_pci_resource,
d03846af
CZ		 1128 amdgpu_cgs_atom_get_data_table,
1129 amdgpu_cgs_atom_get_cmd_table_revs,
1130 amdgpu_cgs_atom_exec_cmd_table,
1131 amdgpu_cgs_create_pm_request,
1132 amdgpu_cgs_destroy_pm_request,
1133 amdgpu_cgs_set_pm_request,
1134 amdgpu_cgs_pm_request_clock,
1135 amdgpu_cgs_pm_request_engine,
1136 amdgpu_cgs_pm_query_clock_limits,
bf3911b0 1137 amdgpu_cgs_set_camera_voltages,
404b2fa3 1138 amdgpu_cgs_get_firmware_info,
a392746a 1139 amdgpu_cgs_rel_firmware,
404b2fa3 1140 amdgpu_cgs_set_powergating_state,
3f1d35a0 1141 amdgpu_cgs_set_clockgating_state,
47bf18b5 1142 amdgpu_cgs_get_active_displays_info,
4c90080b 1143 amdgpu_cgs_notify_dpm_enabled,
3f1d35a0 1144 amdgpu_cgs_call_acpi_method,
5e618699 1145 amdgpu_cgs_query_system_info,
d03846af
CZ		 1146};
1147
1148static const struct cgs_os_ops amdgpu_cgs_os_ops = {
d03846af
CZ		 1149 amdgpu_cgs_add_irq_source,
1150 amdgpu_cgs_irq_get,
1151 amdgpu_cgs_irq_put
1152};
1153
110e6f26 1154struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
d03846af
CZ		 1155{
1156 struct amdgpu_cgs_device *cgs_device =
1157 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
1158
1159 if (!cgs_device) {
1160 DRM_ERROR("Couldn't allocate CGS device structure\n");
1161 return NULL;
1162 }
1163
1164 cgs_device->base.ops = &amdgpu_cgs_ops;
1165 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
1166 cgs_device->adev = adev;
1167
110e6f26 1168 return (struct cgs_device *)cgs_device;
d03846af
CZ		 1169}
1170
110e6f26 1171void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
d03846af
CZ		 1172{
1173 kfree(cgs_device);
1174}
Linux 6.x block layer and io_uring tree(s)