Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
fdf2f6c5 | 26 | |
d38ceaf9 AD |
27 | #include <drm/amdgpu_drm.h> |
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_atombios.h" | |
4e89df63 | 30 | #include "amdgpu_atomfirmware.h" |
d38ceaf9 | 31 | #include "amdgpu_i2c.h" |
5df58525 | 32 | #include "amdgpu_display.h" |
d38ceaf9 AD |
33 | |
34 | #include "atom.h" | |
35 | #include "atom-bits.h" | |
36 | #include "atombios_encoders.h" | |
37 | #include "bif/bif_4_1_d.h" | |
38 | ||
39 | static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev, | |
40 | ATOM_GPIO_I2C_ASSIGMENT *gpio, | |
41 | u8 index) | |
42 | { | |
43 | ||
44 | } | |
45 | ||
46 | static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) | |
47 | { | |
48 | struct amdgpu_i2c_bus_rec i2c; | |
49 | ||
50 | memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); | |
51 | ||
52 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); | |
53 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); | |
54 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); | |
55 | i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); | |
56 | i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); | |
57 | i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); | |
58 | i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); | |
59 | i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); | |
60 | i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); | |
61 | i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); | |
62 | i2c.en_clk_mask = (1 << gpio->ucClkEnShift); | |
63 | i2c.en_data_mask = (1 << gpio->ucDataEnShift); | |
64 | i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); | |
65 | i2c.y_data_mask = (1 << gpio->ucDataY_Shift); | |
66 | i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); | |
67 | i2c.a_data_mask = (1 << gpio->ucDataA_Shift); | |
68 | ||
69 | if (gpio->sucI2cId.sbfAccess.bfHW_Capable) | |
70 | i2c.hw_capable = true; | |
71 | else | |
72 | i2c.hw_capable = false; | |
73 | ||
74 | if (gpio->sucI2cId.ucAccess == 0xa0) | |
75 | i2c.mm_i2c = true; | |
76 | else | |
77 | i2c.mm_i2c = false; | |
78 | ||
79 | i2c.i2c_id = gpio->sucI2cId.ucAccess; | |
80 | ||
81 | if (i2c.mask_clk_reg) | |
82 | i2c.valid = true; | |
83 | else | |
84 | i2c.valid = false; | |
85 | ||
86 | return i2c; | |
87 | } | |
88 | ||
89 | struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, | |
90 | uint8_t id) | |
91 | { | |
92 | struct atom_context *ctx = adev->mode_info.atom_context; | |
93 | ATOM_GPIO_I2C_ASSIGMENT *gpio; | |
94 | struct amdgpu_i2c_bus_rec i2c; | |
95 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
96 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
97 | uint16_t data_offset, size; | |
98 | int i, num_indices; | |
99 | ||
100 | memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); | |
101 | i2c.valid = false; | |
102 | ||
103 | if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { | |
104 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); | |
105 | ||
106 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
107 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); | |
108 | ||
109 | gpio = &i2c_info->asGPIO_Info[0]; | |
110 | for (i = 0; i < num_indices; i++) { | |
111 | ||
112 | amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); | |
113 | ||
114 | if (gpio->sucI2cId.ucAccess == id) { | |
115 | i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); | |
116 | break; | |
117 | } | |
118 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) | |
119 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); | |
120 | } | |
121 | } | |
122 | ||
123 | return i2c; | |
124 | } | |
125 | ||
126 | void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) | |
127 | { | |
128 | struct atom_context *ctx = adev->mode_info.atom_context; | |
129 | ATOM_GPIO_I2C_ASSIGMENT *gpio; | |
130 | struct amdgpu_i2c_bus_rec i2c; | |
131 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
132 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
133 | uint16_t data_offset, size; | |
134 | int i, num_indices; | |
135 | char stmp[32]; | |
136 | ||
137 | if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { | |
138 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); | |
139 | ||
140 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
141 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); | |
142 | ||
143 | gpio = &i2c_info->asGPIO_Info[0]; | |
144 | for (i = 0; i < num_indices; i++) { | |
145 | amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); | |
146 | ||
147 | i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); | |
148 | ||
149 | if (i2c.valid) { | |
150 | sprintf(stmp, "0x%x", i2c.i2c_id); | |
151 | adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp); | |
152 | } | |
153 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) | |
154 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); | |
155 | } | |
156 | } | |
157 | } | |
158 | ||
159 | struct amdgpu_gpio_rec | |
160 | amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, | |
161 | u8 id) | |
162 | { | |
163 | struct atom_context *ctx = adev->mode_info.atom_context; | |
164 | struct amdgpu_gpio_rec gpio; | |
165 | int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); | |
166 | struct _ATOM_GPIO_PIN_LUT *gpio_info; | |
167 | ATOM_GPIO_PIN_ASSIGNMENT *pin; | |
168 | u16 data_offset, size; | |
169 | int i, num_indices; | |
170 | ||
171 | memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); | |
172 | gpio.valid = false; | |
173 | ||
174 | if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { | |
175 | gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); | |
176 | ||
177 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
178 | sizeof(ATOM_GPIO_PIN_ASSIGNMENT); | |
179 | ||
180 | pin = gpio_info->asGPIO_Pin; | |
181 | for (i = 0; i < num_indices; i++) { | |
182 | if (id == pin->ucGPIO_ID) { | |
183 | gpio.id = pin->ucGPIO_ID; | |
184 | gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); | |
185 | gpio.shift = pin->ucGpioPinBitShift; | |
186 | gpio.mask = (1 << pin->ucGpioPinBitShift); | |
187 | gpio.valid = true; | |
188 | break; | |
189 | } | |
190 | pin = (ATOM_GPIO_PIN_ASSIGNMENT *) | |
191 | ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); | |
192 | } | |
193 | } | |
194 | ||
195 | return gpio; | |
196 | } | |
197 | ||
198 | static struct amdgpu_hpd | |
199 | amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, | |
200 | struct amdgpu_gpio_rec *gpio) | |
201 | { | |
202 | struct amdgpu_hpd hpd; | |
203 | u32 reg; | |
204 | ||
205 | memset(&hpd, 0, sizeof(struct amdgpu_hpd)); | |
206 | ||
207 | reg = amdgpu_display_hpd_get_gpio_reg(adev); | |
208 | ||
209 | hpd.gpio = *gpio; | |
210 | if (gpio->reg == reg) { | |
211 | switch(gpio->mask) { | |
212 | case (1 << 0): | |
213 | hpd.hpd = AMDGPU_HPD_1; | |
214 | break; | |
215 | case (1 << 8): | |
216 | hpd.hpd = AMDGPU_HPD_2; | |
217 | break; | |
218 | case (1 << 16): | |
219 | hpd.hpd = AMDGPU_HPD_3; | |
220 | break; | |
221 | case (1 << 24): | |
222 | hpd.hpd = AMDGPU_HPD_4; | |
223 | break; | |
224 | case (1 << 26): | |
225 | hpd.hpd = AMDGPU_HPD_5; | |
226 | break; | |
227 | case (1 << 28): | |
228 | hpd.hpd = AMDGPU_HPD_6; | |
229 | break; | |
230 | default: | |
231 | hpd.hpd = AMDGPU_HPD_NONE; | |
232 | break; | |
233 | } | |
234 | } else | |
235 | hpd.hpd = AMDGPU_HPD_NONE; | |
236 | return hpd; | |
237 | } | |
238 | ||
d38ceaf9 AD |
239 | static const int object_connector_convert[] = { |
240 | DRM_MODE_CONNECTOR_Unknown, | |
241 | DRM_MODE_CONNECTOR_DVII, | |
242 | DRM_MODE_CONNECTOR_DVII, | |
243 | DRM_MODE_CONNECTOR_DVID, | |
244 | DRM_MODE_CONNECTOR_DVID, | |
245 | DRM_MODE_CONNECTOR_VGA, | |
246 | DRM_MODE_CONNECTOR_Composite, | |
247 | DRM_MODE_CONNECTOR_SVIDEO, | |
248 | DRM_MODE_CONNECTOR_Unknown, | |
249 | DRM_MODE_CONNECTOR_Unknown, | |
250 | DRM_MODE_CONNECTOR_9PinDIN, | |
251 | DRM_MODE_CONNECTOR_Unknown, | |
252 | DRM_MODE_CONNECTOR_HDMIA, | |
253 | DRM_MODE_CONNECTOR_HDMIB, | |
254 | DRM_MODE_CONNECTOR_LVDS, | |
255 | DRM_MODE_CONNECTOR_9PinDIN, | |
256 | DRM_MODE_CONNECTOR_Unknown, | |
257 | DRM_MODE_CONNECTOR_Unknown, | |
258 | DRM_MODE_CONNECTOR_Unknown, | |
259 | DRM_MODE_CONNECTOR_DisplayPort, | |
260 | DRM_MODE_CONNECTOR_eDP, | |
261 | DRM_MODE_CONNECTOR_Unknown | |
262 | }; | |
263 | ||
0bad1619 ED |
264 | bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev) |
265 | { | |
266 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
267 | struct atom_context *ctx = mode_info->atom_context; | |
268 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
269 | u16 size, data_offset; | |
270 | u8 frev, crev; | |
271 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; | |
272 | ATOM_OBJECT_HEADER *obj_header; | |
273 | ||
274 | if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) | |
275 | return false; | |
276 | ||
277 | if (crev < 2) | |
278 | return false; | |
279 | ||
280 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); | |
281 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) | |
282 | (ctx->bios + data_offset + | |
283 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); | |
284 | ||
285 | if (path_obj->ucNumOfDispPath) | |
286 | return true; | |
287 | else | |
288 | return false; | |
289 | } | |
290 | ||
d38ceaf9 AD |
291 | bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) |
292 | { | |
293 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
294 | struct atom_context *ctx = mode_info->atom_context; | |
295 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
296 | u16 size, data_offset; | |
297 | u8 frev, crev; | |
298 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; | |
299 | ATOM_ENCODER_OBJECT_TABLE *enc_obj; | |
300 | ATOM_OBJECT_TABLE *router_obj; | |
301 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; | |
302 | ATOM_OBJECT_HEADER *obj_header; | |
303 | int i, j, k, path_size, device_support; | |
304 | int connector_type; | |
305 | u16 conn_id, connector_object_id; | |
306 | struct amdgpu_i2c_bus_rec ddc_bus; | |
307 | struct amdgpu_router router; | |
308 | struct amdgpu_gpio_rec gpio; | |
309 | struct amdgpu_hpd hpd; | |
310 | ||
311 | if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) | |
312 | return false; | |
313 | ||
314 | if (crev < 2) | |
315 | return false; | |
316 | ||
317 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); | |
318 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) | |
319 | (ctx->bios + data_offset + | |
320 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); | |
321 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) | |
322 | (ctx->bios + data_offset + | |
323 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); | |
324 | enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) | |
325 | (ctx->bios + data_offset + | |
326 | le16_to_cpu(obj_header->usEncoderObjectTableOffset)); | |
327 | router_obj = (ATOM_OBJECT_TABLE *) | |
328 | (ctx->bios + data_offset + | |
329 | le16_to_cpu(obj_header->usRouterObjectTableOffset)); | |
330 | device_support = le16_to_cpu(obj_header->usDeviceSupport); | |
331 | ||
332 | path_size = 0; | |
333 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { | |
334 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; | |
335 | ATOM_DISPLAY_OBJECT_PATH *path; | |
336 | addr += path_size; | |
337 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; | |
338 | path_size += le16_to_cpu(path->usSize); | |
339 | ||
340 | if (device_support & le16_to_cpu(path->usDeviceTag)) { | |
341 | uint8_t con_obj_id, con_obj_num, con_obj_type; | |
342 | ||
343 | con_obj_id = | |
344 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) | |
345 | >> OBJECT_ID_SHIFT; | |
346 | con_obj_num = | |
347 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) | |
348 | >> ENUM_ID_SHIFT; | |
349 | con_obj_type = | |
350 | (le16_to_cpu(path->usConnObjectId) & | |
351 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
352 | ||
611a1507 AD |
353 | /* Skip TV/CV support */ |
354 | if ((le16_to_cpu(path->usDeviceTag) == | |
355 | ATOM_DEVICE_TV1_SUPPORT) || | |
356 | (le16_to_cpu(path->usDeviceTag) == | |
357 | ATOM_DEVICE_CV_SUPPORT)) | |
358 | continue; | |
359 | ||
e1718d97 AD |
360 | if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) { |
361 | DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n", | |
362 | con_obj_id, le16_to_cpu(path->usDeviceTag)); | |
363 | continue; | |
364 | } | |
365 | ||
d38ceaf9 AD |
366 | connector_type = |
367 | object_connector_convert[con_obj_id]; | |
368 | connector_object_id = con_obj_id; | |
369 | ||
370 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | |
371 | continue; | |
372 | ||
373 | router.ddc_valid = false; | |
374 | router.cd_valid = false; | |
375 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { | |
376 | uint8_t grph_obj_id, grph_obj_num, grph_obj_type; | |
377 | ||
378 | grph_obj_id = | |
379 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
380 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
381 | grph_obj_num = | |
382 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
383 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
384 | grph_obj_type = | |
385 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
386 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
387 | ||
388 | if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { | |
389 | for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { | |
390 | u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); | |
391 | if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { | |
392 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) | |
393 | (ctx->bios + data_offset + | |
394 | le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); | |
395 | ATOM_ENCODER_CAP_RECORD *cap_record; | |
396 | u16 caps = 0; | |
397 | ||
398 | while (record->ucRecordSize > 0 && | |
399 | record->ucRecordType > 0 && | |
400 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
401 | switch (record->ucRecordType) { | |
402 | case ATOM_ENCODER_CAP_RECORD_TYPE: | |
403 | cap_record =(ATOM_ENCODER_CAP_RECORD *) | |
404 | record; | |
405 | caps = le16_to_cpu(cap_record->usEncoderCap); | |
406 | break; | |
407 | } | |
408 | record = (ATOM_COMMON_RECORD_HEADER *) | |
409 | ((char *)record + record->ucRecordSize); | |
410 | } | |
411 | amdgpu_display_add_encoder(adev, encoder_obj, | |
412 | le16_to_cpu(path->usDeviceTag), | |
413 | caps); | |
414 | } | |
415 | } | |
416 | } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { | |
417 | for (k = 0; k < router_obj->ucNumberOfObjects; k++) { | |
418 | u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); | |
419 | if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { | |
420 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) | |
421 | (ctx->bios + data_offset + | |
422 | le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); | |
423 | ATOM_I2C_RECORD *i2c_record; | |
424 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; | |
425 | ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; | |
426 | ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; | |
427 | ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = | |
428 | (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) | |
429 | (ctx->bios + data_offset + | |
430 | le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); | |
431 | u8 *num_dst_objs = (u8 *) | |
432 | ((u8 *)router_src_dst_table + 1 + | |
433 | (router_src_dst_table->ucNumberOfSrc * 2)); | |
434 | u16 *dst_objs = (u16 *)(num_dst_objs + 1); | |
435 | int enum_id; | |
436 | ||
437 | router.router_id = router_obj_id; | |
438 | for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { | |
439 | if (le16_to_cpu(path->usConnObjectId) == | |
440 | le16_to_cpu(dst_objs[enum_id])) | |
441 | break; | |
442 | } | |
443 | ||
444 | while (record->ucRecordSize > 0 && | |
445 | record->ucRecordType > 0 && | |
446 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
447 | switch (record->ucRecordType) { | |
448 | case ATOM_I2C_RECORD_TYPE: | |
449 | i2c_record = | |
450 | (ATOM_I2C_RECORD *) | |
451 | record; | |
452 | i2c_config = | |
453 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
454 | &i2c_record->sucI2cId; | |
455 | router.i2c_info = | |
456 | amdgpu_atombios_lookup_i2c_gpio(adev, | |
457 | i2c_config-> | |
458 | ucAccess); | |
459 | router.i2c_addr = i2c_record->ucI2CAddr >> 1; | |
460 | break; | |
461 | case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: | |
462 | ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) | |
463 | record; | |
464 | router.ddc_valid = true; | |
465 | router.ddc_mux_type = ddc_path->ucMuxType; | |
466 | router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; | |
467 | router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; | |
468 | break; | |
469 | case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: | |
470 | cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) | |
471 | record; | |
472 | router.cd_valid = true; | |
473 | router.cd_mux_type = cd_path->ucMuxType; | |
474 | router.cd_mux_control_pin = cd_path->ucMuxControlPin; | |
475 | router.cd_mux_state = cd_path->ucMuxState[enum_id]; | |
476 | break; | |
477 | } | |
478 | record = (ATOM_COMMON_RECORD_HEADER *) | |
479 | ((char *)record + record->ucRecordSize); | |
480 | } | |
481 | } | |
482 | } | |
483 | } | |
484 | } | |
485 | ||
486 | /* look up gpio for ddc, hpd */ | |
487 | ddc_bus.valid = false; | |
488 | hpd.hpd = AMDGPU_HPD_NONE; | |
489 | if ((le16_to_cpu(path->usDeviceTag) & | |
490 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { | |
491 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { | |
492 | if (le16_to_cpu(path->usConnObjectId) == | |
493 | le16_to_cpu(con_obj->asObjects[j]. | |
494 | usObjectID)) { | |
495 | ATOM_COMMON_RECORD_HEADER | |
496 | *record = | |
497 | (ATOM_COMMON_RECORD_HEADER | |
498 | *) | |
499 | (ctx->bios + data_offset + | |
500 | le16_to_cpu(con_obj-> | |
501 | asObjects[j]. | |
502 | usRecordOffset)); | |
503 | ATOM_I2C_RECORD *i2c_record; | |
504 | ATOM_HPD_INT_RECORD *hpd_record; | |
505 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; | |
506 | ||
507 | while (record->ucRecordSize > 0 && | |
508 | record->ucRecordType > 0 && | |
509 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
510 | switch (record->ucRecordType) { | |
511 | case ATOM_I2C_RECORD_TYPE: | |
512 | i2c_record = | |
513 | (ATOM_I2C_RECORD *) | |
514 | record; | |
515 | i2c_config = | |
516 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
517 | &i2c_record->sucI2cId; | |
518 | ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, | |
519 | i2c_config-> | |
520 | ucAccess); | |
521 | break; | |
522 | case ATOM_HPD_INT_RECORD_TYPE: | |
523 | hpd_record = | |
524 | (ATOM_HPD_INT_RECORD *) | |
525 | record; | |
526 | gpio = amdgpu_atombios_lookup_gpio(adev, | |
527 | hpd_record->ucHPDIntGPIOID); | |
528 | hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); | |
529 | hpd.plugged_state = hpd_record->ucPlugged_PinState; | |
530 | break; | |
531 | } | |
532 | record = | |
533 | (ATOM_COMMON_RECORD_HEADER | |
534 | *) ((char *)record | |
535 | + | |
536 | record-> | |
537 | ucRecordSize); | |
538 | } | |
539 | break; | |
540 | } | |
541 | } | |
542 | } | |
543 | ||
544 | /* needed for aux chan transactions */ | |
545 | ddc_bus.hpd = hpd.hpd; | |
546 | ||
547 | conn_id = le16_to_cpu(path->usConnObjectId); | |
548 | ||
d38ceaf9 AD |
549 | amdgpu_display_add_connector(adev, |
550 | conn_id, | |
551 | le16_to_cpu(path->usDeviceTag), | |
552 | connector_type, &ddc_bus, | |
553 | connector_object_id, | |
554 | &hpd, | |
555 | &router); | |
556 | ||
557 | } | |
558 | } | |
559 | ||
560 | amdgpu_link_encoder_connector(adev->ddev); | |
561 | ||
562 | return true; | |
563 | } | |
564 | ||
565 | union firmware_info { | |
566 | ATOM_FIRMWARE_INFO info; | |
567 | ATOM_FIRMWARE_INFO_V1_2 info_12; | |
568 | ATOM_FIRMWARE_INFO_V1_3 info_13; | |
569 | ATOM_FIRMWARE_INFO_V1_4 info_14; | |
570 | ATOM_FIRMWARE_INFO_V2_1 info_21; | |
571 | ATOM_FIRMWARE_INFO_V2_2 info_22; | |
572 | }; | |
573 | ||
574 | int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) | |
575 | { | |
576 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
577 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
578 | uint8_t frev, crev; | |
579 | uint16_t data_offset; | |
580 | int ret = -EINVAL; | |
581 | ||
582 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, | |
583 | &frev, &crev, &data_offset)) { | |
584 | int i; | |
585 | struct amdgpu_pll *ppll = &adev->clock.ppll[0]; | |
586 | struct amdgpu_pll *spll = &adev->clock.spll; | |
587 | struct amdgpu_pll *mpll = &adev->clock.mpll; | |
588 | union firmware_info *firmware_info = | |
589 | (union firmware_info *)(mode_info->atom_context->bios + | |
590 | data_offset); | |
591 | /* pixel clocks */ | |
592 | ppll->reference_freq = | |
593 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
594 | ppll->reference_div = 0; | |
595 | ||
a8a04c99 AD |
596 | ppll->pll_out_min = |
597 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); | |
d38ceaf9 AD |
598 | ppll->pll_out_max = |
599 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); | |
600 | ||
a8a04c99 AD |
601 | ppll->lcd_pll_out_min = |
602 | le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; | |
603 | if (ppll->lcd_pll_out_min == 0) | |
d38ceaf9 | 604 | ppll->lcd_pll_out_min = ppll->pll_out_min; |
a8a04c99 AD |
605 | ppll->lcd_pll_out_max = |
606 | le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; | |
607 | if (ppll->lcd_pll_out_max == 0) | |
d38ceaf9 | 608 | ppll->lcd_pll_out_max = ppll->pll_out_max; |
d38ceaf9 AD |
609 | |
610 | if (ppll->pll_out_min == 0) | |
611 | ppll->pll_out_min = 64800; | |
612 | ||
613 | ppll->pll_in_min = | |
614 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); | |
615 | ppll->pll_in_max = | |
616 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); | |
617 | ||
618 | ppll->min_post_div = 2; | |
619 | ppll->max_post_div = 0x7f; | |
620 | ppll->min_frac_feedback_div = 0; | |
621 | ppll->max_frac_feedback_div = 9; | |
622 | ppll->min_ref_div = 2; | |
623 | ppll->max_ref_div = 0x3ff; | |
624 | ppll->min_feedback_div = 4; | |
625 | ppll->max_feedback_div = 0xfff; | |
626 | ppll->best_vco = 0; | |
627 | ||
628 | for (i = 1; i < AMDGPU_MAX_PPLL; i++) | |
629 | adev->clock.ppll[i] = *ppll; | |
630 | ||
631 | /* system clock */ | |
632 | spll->reference_freq = | |
633 | le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); | |
634 | spll->reference_div = 0; | |
635 | ||
636 | spll->pll_out_min = | |
637 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); | |
638 | spll->pll_out_max = | |
639 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); | |
640 | ||
641 | /* ??? */ | |
642 | if (spll->pll_out_min == 0) | |
643 | spll->pll_out_min = 64800; | |
644 | ||
645 | spll->pll_in_min = | |
646 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); | |
647 | spll->pll_in_max = | |
648 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); | |
649 | ||
650 | spll->min_post_div = 1; | |
651 | spll->max_post_div = 1; | |
652 | spll->min_ref_div = 2; | |
653 | spll->max_ref_div = 0xff; | |
654 | spll->min_feedback_div = 4; | |
655 | spll->max_feedback_div = 0xff; | |
656 | spll->best_vco = 0; | |
657 | ||
658 | /* memory clock */ | |
659 | mpll->reference_freq = | |
660 | le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); | |
661 | mpll->reference_div = 0; | |
662 | ||
663 | mpll->pll_out_min = | |
664 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); | |
665 | mpll->pll_out_max = | |
666 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); | |
667 | ||
668 | /* ??? */ | |
669 | if (mpll->pll_out_min == 0) | |
670 | mpll->pll_out_min = 64800; | |
671 | ||
672 | mpll->pll_in_min = | |
673 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); | |
674 | mpll->pll_in_max = | |
675 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); | |
676 | ||
677 | adev->clock.default_sclk = | |
678 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); | |
679 | adev->clock.default_mclk = | |
680 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); | |
681 | ||
682 | mpll->min_post_div = 1; | |
683 | mpll->max_post_div = 1; | |
684 | mpll->min_ref_div = 2; | |
685 | mpll->max_ref_div = 0xff; | |
686 | mpll->min_feedback_div = 4; | |
687 | mpll->max_feedback_div = 0xff; | |
688 | mpll->best_vco = 0; | |
689 | ||
690 | /* disp clock */ | |
691 | adev->clock.default_dispclk = | |
692 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); | |
80c083c5 AD |
693 | /* set a reasonable default for DP */ |
694 | if (adev->clock.default_dispclk < 53900) { | |
9953b72f | 695 | DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n", |
696 | adev->clock.default_dispclk / 100); | |
80c083c5 | 697 | adev->clock.default_dispclk = 60000; |
52b482b0 | 698 | } else if (adev->clock.default_dispclk <= 60000) { |
9953b72f | 699 | DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n", |
700 | adev->clock.default_dispclk / 100); | |
52b482b0 | 701 | adev->clock.default_dispclk = 62500; |
80c083c5 | 702 | } |
d38ceaf9 AD |
703 | adev->clock.dp_extclk = |
704 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); | |
705 | adev->clock.current_dispclk = adev->clock.default_dispclk; | |
706 | ||
707 | adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); | |
708 | if (adev->clock.max_pixel_clock == 0) | |
709 | adev->clock.max_pixel_clock = 40000; | |
710 | ||
711 | /* not technically a clock, but... */ | |
712 | adev->mode_info.firmware_flags = | |
713 | le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); | |
714 | ||
715 | ret = 0; | |
716 | } | |
717 | ||
718 | adev->pm.current_sclk = adev->clock.default_sclk; | |
719 | adev->pm.current_mclk = adev->clock.default_mclk; | |
720 | ||
721 | return ret; | |
722 | } | |
723 | ||
397a270e AD |
724 | union gfx_info { |
725 | ATOM_GFX_INFO_V2_1 info; | |
726 | }; | |
727 | ||
728 | int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev) | |
729 | { | |
730 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
731 | int index = GetIndexIntoMasterTable(DATA, GFX_Info); | |
732 | uint8_t frev, crev; | |
733 | uint16_t data_offset; | |
734 | int ret = -EINVAL; | |
735 | ||
736 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, | |
737 | &frev, &crev, &data_offset)) { | |
738 | union gfx_info *gfx_info = (union gfx_info *) | |
739 | (mode_info->atom_context->bios + data_offset); | |
740 | ||
741 | adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; | |
742 | adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; | |
743 | adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; | |
744 | adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; | |
745 | adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; | |
746 | adev->gfx.config.max_texture_channel_caches = | |
747 | gfx_info->info.max_texture_channel_caches; | |
748 | ||
749 | ret = 0; | |
750 | } | |
751 | return ret; | |
752 | } | |
753 | ||
d38ceaf9 AD |
754 | union igp_info { |
755 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
756 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; | |
757 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; | |
758 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; | |
759 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; | |
760 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; | |
761 | }; | |
762 | ||
1ce65f52 HW |
763 | /* |
764 | * Return vram width from integrated system info table, if available, | |
765 | * or 0 if not. | |
766 | */ | |
767 | int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev) | |
768 | { | |
769 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
770 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
771 | u16 data_offset, size; | |
772 | union igp_info *igp_info; | |
773 | u8 frev, crev; | |
774 | ||
775 | /* get any igp specific overrides */ | |
776 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, | |
777 | &frev, &crev, &data_offset)) { | |
778 | igp_info = (union igp_info *) | |
779 | (mode_info->atom_context->bios + data_offset); | |
780 | switch (crev) { | |
781 | case 8: | |
782 | case 9: | |
783 | return igp_info->info_8.ucUMAChannelNumber * 64; | |
784 | default: | |
785 | return 0; | |
786 | } | |
787 | } | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
d38ceaf9 AD |
792 | static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, |
793 | struct amdgpu_atom_ss *ss, | |
794 | int id) | |
795 | { | |
796 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
797 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
798 | u16 data_offset, size; | |
799 | union igp_info *igp_info; | |
800 | u8 frev, crev; | |
801 | u16 percentage = 0, rate = 0; | |
802 | ||
803 | /* get any igp specific overrides */ | |
804 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, | |
805 | &frev, &crev, &data_offset)) { | |
806 | igp_info = (union igp_info *) | |
807 | (mode_info->atom_context->bios + data_offset); | |
808 | switch (crev) { | |
809 | case 6: | |
810 | switch (id) { | |
811 | case ASIC_INTERNAL_SS_ON_TMDS: | |
812 | percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); | |
813 | rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); | |
814 | break; | |
815 | case ASIC_INTERNAL_SS_ON_HDMI: | |
816 | percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); | |
817 | rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); | |
818 | break; | |
819 | case ASIC_INTERNAL_SS_ON_LVDS: | |
820 | percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); | |
821 | rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); | |
822 | break; | |
823 | } | |
824 | break; | |
825 | case 7: | |
826 | switch (id) { | |
827 | case ASIC_INTERNAL_SS_ON_TMDS: | |
828 | percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); | |
829 | rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); | |
830 | break; | |
831 | case ASIC_INTERNAL_SS_ON_HDMI: | |
832 | percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); | |
833 | rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); | |
834 | break; | |
835 | case ASIC_INTERNAL_SS_ON_LVDS: | |
836 | percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); | |
837 | rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); | |
838 | break; | |
839 | } | |
840 | break; | |
841 | case 8: | |
842 | switch (id) { | |
843 | case ASIC_INTERNAL_SS_ON_TMDS: | |
844 | percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); | |
845 | rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); | |
846 | break; | |
847 | case ASIC_INTERNAL_SS_ON_HDMI: | |
848 | percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); | |
849 | rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); | |
850 | break; | |
851 | case ASIC_INTERNAL_SS_ON_LVDS: | |
852 | percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); | |
853 | rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); | |
854 | break; | |
855 | } | |
856 | break; | |
857 | case 9: | |
858 | switch (id) { | |
859 | case ASIC_INTERNAL_SS_ON_TMDS: | |
860 | percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); | |
861 | rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); | |
862 | break; | |
863 | case ASIC_INTERNAL_SS_ON_HDMI: | |
864 | percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); | |
865 | rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); | |
866 | break; | |
867 | case ASIC_INTERNAL_SS_ON_LVDS: | |
868 | percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); | |
869 | rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); | |
870 | break; | |
871 | } | |
872 | break; | |
873 | default: | |
874 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
875 | break; | |
876 | } | |
877 | if (percentage) | |
878 | ss->percentage = percentage; | |
879 | if (rate) | |
880 | ss->rate = rate; | |
881 | } | |
882 | } | |
883 | ||
884 | union asic_ss_info { | |
885 | struct _ATOM_ASIC_INTERNAL_SS_INFO info; | |
886 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; | |
887 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; | |
888 | }; | |
889 | ||
890 | union asic_ss_assignment { | |
891 | struct _ATOM_ASIC_SS_ASSIGNMENT v1; | |
892 | struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; | |
893 | struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; | |
894 | }; | |
895 | ||
896 | bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, | |
897 | struct amdgpu_atom_ss *ss, | |
898 | int id, u32 clock) | |
899 | { | |
900 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
901 | int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); | |
902 | uint16_t data_offset, size; | |
903 | union asic_ss_info *ss_info; | |
904 | union asic_ss_assignment *ss_assign; | |
905 | uint8_t frev, crev; | |
906 | int i, num_indices; | |
907 | ||
908 | if (id == ASIC_INTERNAL_MEMORY_SS) { | |
909 | if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) | |
910 | return false; | |
911 | } | |
912 | if (id == ASIC_INTERNAL_ENGINE_SS) { | |
913 | if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) | |
914 | return false; | |
915 | } | |
916 | ||
917 | memset(ss, 0, sizeof(struct amdgpu_atom_ss)); | |
918 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, | |
919 | &frev, &crev, &data_offset)) { | |
920 | ||
921 | ss_info = | |
922 | (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); | |
923 | ||
924 | switch (frev) { | |
925 | case 1: | |
926 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
927 | sizeof(ATOM_ASIC_SS_ASSIGNMENT); | |
928 | ||
929 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); | |
930 | for (i = 0; i < num_indices; i++) { | |
931 | if ((ss_assign->v1.ucClockIndication == id) && | |
932 | (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { | |
933 | ss->percentage = | |
934 | le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); | |
935 | ss->type = ss_assign->v1.ucSpreadSpectrumMode; | |
936 | ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); | |
937 | ss->percentage_divider = 100; | |
938 | return true; | |
939 | } | |
940 | ss_assign = (union asic_ss_assignment *) | |
941 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); | |
942 | } | |
943 | break; | |
944 | case 2: | |
945 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
946 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); | |
947 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); | |
948 | for (i = 0; i < num_indices; i++) { | |
949 | if ((ss_assign->v2.ucClockIndication == id) && | |
950 | (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { | |
951 | ss->percentage = | |
952 | le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); | |
953 | ss->type = ss_assign->v2.ucSpreadSpectrumMode; | |
954 | ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); | |
955 | ss->percentage_divider = 100; | |
956 | if ((crev == 2) && | |
957 | ((id == ASIC_INTERNAL_ENGINE_SS) || | |
958 | (id == ASIC_INTERNAL_MEMORY_SS))) | |
959 | ss->rate /= 100; | |
960 | return true; | |
961 | } | |
962 | ss_assign = (union asic_ss_assignment *) | |
963 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); | |
964 | } | |
965 | break; | |
966 | case 3: | |
967 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
968 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); | |
969 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); | |
970 | for (i = 0; i < num_indices; i++) { | |
971 | if ((ss_assign->v3.ucClockIndication == id) && | |
972 | (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { | |
973 | ss->percentage = | |
974 | le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); | |
975 | ss->type = ss_assign->v3.ucSpreadSpectrumMode; | |
976 | ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); | |
977 | if (ss_assign->v3.ucSpreadSpectrumMode & | |
978 | SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) | |
979 | ss->percentage_divider = 1000; | |
980 | else | |
981 | ss->percentage_divider = 100; | |
982 | if ((id == ASIC_INTERNAL_ENGINE_SS) || | |
983 | (id == ASIC_INTERNAL_MEMORY_SS)) | |
984 | ss->rate /= 100; | |
2f7d10b3 | 985 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 AD |
986 | amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); |
987 | return true; | |
988 | } | |
989 | ss_assign = (union asic_ss_assignment *) | |
990 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); | |
991 | } | |
992 | break; | |
993 | default: | |
994 | DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); | |
995 | break; | |
996 | } | |
997 | ||
998 | } | |
999 | return false; | |
1000 | } | |
1001 | ||
1002 | union get_clock_dividers { | |
1003 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; | |
1004 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; | |
1005 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; | |
1006 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; | |
1007 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; | |
1008 | struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; | |
1009 | struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; | |
1010 | }; | |
1011 | ||
1012 | int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, | |
1013 | u8 clock_type, | |
1014 | u32 clock, | |
1015 | bool strobe_mode, | |
1016 | struct atom_clock_dividers *dividers) | |
1017 | { | |
1018 | union get_clock_dividers args; | |
1019 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); | |
1020 | u8 frev, crev; | |
1021 | ||
1022 | memset(&args, 0, sizeof(args)); | |
1023 | memset(dividers, 0, sizeof(struct atom_clock_dividers)); | |
1024 | ||
1025 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
1026 | return -EINVAL; | |
1027 | ||
1028 | switch (crev) { | |
9139d731 MSB |
1029 | case 2: |
1030 | case 3: | |
1031 | case 5: | |
1032 | /* r6xx, r7xx, evergreen, ni, si. | |
1033 | * TODO: add support for asic_type <= CHIP_RV770*/ | |
1034 | if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { | |
1035 | args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); | |
1036 | ||
1037 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1038 | ||
1039 | dividers->post_div = args.v3.ucPostDiv; | |
1040 | dividers->enable_post_div = (args.v3.ucCntlFlag & | |
1041 | ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; | |
1042 | dividers->enable_dithen = (args.v3.ucCntlFlag & | |
1043 | ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; | |
1044 | dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); | |
1045 | dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); | |
1046 | dividers->ref_div = args.v3.ucRefDiv; | |
1047 | dividers->vco_mode = (args.v3.ucCntlFlag & | |
1048 | ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; | |
1049 | } else { | |
1050 | /* for SI we use ComputeMemoryClockParam for memory plls */ | |
1051 | if (adev->asic_type >= CHIP_TAHITI) | |
1052 | return -EINVAL; | |
1053 | args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); | |
1054 | if (strobe_mode) | |
1055 | args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; | |
1056 | ||
1057 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1058 | ||
1059 | dividers->post_div = args.v5.ucPostDiv; | |
1060 | dividers->enable_post_div = (args.v5.ucCntlFlag & | |
1061 | ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; | |
1062 | dividers->enable_dithen = (args.v5.ucCntlFlag & | |
1063 | ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; | |
1064 | dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); | |
1065 | dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); | |
1066 | dividers->ref_div = args.v5.ucRefDiv; | |
1067 | dividers->vco_mode = (args.v5.ucCntlFlag & | |
1068 | ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; | |
1069 | } | |
1070 | break; | |
d38ceaf9 AD |
1071 | case 4: |
1072 | /* fusion */ | |
1073 | args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
1074 | ||
1075 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1076 | ||
1077 | dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; | |
1078 | dividers->real_clock = le32_to_cpu(args.v4.ulClock); | |
1079 | break; | |
1080 | case 6: | |
1081 | /* CI */ | |
1082 | /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ | |
1083 | args.v6_in.ulClock.ulComputeClockFlag = clock_type; | |
1084 | args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ | |
1085 | ||
1086 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1087 | ||
1088 | dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); | |
1089 | dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); | |
1090 | dividers->ref_div = args.v6_out.ucPllRefDiv; | |
1091 | dividers->post_div = args.v6_out.ucPllPostDiv; | |
1092 | dividers->flags = args.v6_out.ucPllCntlFlag; | |
1093 | dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); | |
1094 | dividers->post_divider = args.v6_out.ulClock.ucPostDiv; | |
1095 | break; | |
1096 | default: | |
1097 | return -EINVAL; | |
1098 | } | |
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, | |
1103 | u32 clock, | |
1104 | bool strobe_mode, | |
1105 | struct atom_mpll_param *mpll_param) | |
1106 | { | |
1107 | COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; | |
1108 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); | |
1109 | u8 frev, crev; | |
1110 | ||
1111 | memset(&args, 0, sizeof(args)); | |
1112 | memset(mpll_param, 0, sizeof(struct atom_mpll_param)); | |
1113 | ||
1114 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
1115 | return -EINVAL; | |
1116 | ||
1117 | switch (frev) { | |
1118 | case 2: | |
1119 | switch (crev) { | |
1120 | case 1: | |
1121 | /* SI */ | |
1122 | args.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
1123 | args.ucInputFlag = 0; | |
1124 | if (strobe_mode) | |
1125 | args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; | |
1126 | ||
1127 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1128 | ||
1129 | mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); | |
1130 | mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); | |
1131 | mpll_param->post_div = args.ucPostDiv; | |
1132 | mpll_param->dll_speed = args.ucDllSpeed; | |
1133 | mpll_param->bwcntl = args.ucBWCntl; | |
1134 | mpll_param->vco_mode = | |
1135 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); | |
1136 | mpll_param->yclk_sel = | |
1137 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; | |
1138 | mpll_param->qdr = | |
1139 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; | |
1140 | mpll_param->half_rate = | |
1141 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; | |
1142 | break; | |
1143 | default: | |
1144 | return -EINVAL; | |
1145 | } | |
1146 | break; | |
1147 | default: | |
1148 | return -EINVAL; | |
1149 | } | |
1150 | return 0; | |
1151 | } | |
1152 | ||
d38ceaf9 AD |
1153 | void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, |
1154 | u32 eng_clock, u32 mem_clock) | |
1155 | { | |
1156 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | |
1157 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); | |
1158 | u32 tmp; | |
1159 | ||
1160 | memset(&args, 0, sizeof(args)); | |
1161 | ||
1162 | tmp = eng_clock & SET_CLOCK_FREQ_MASK; | |
1163 | tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); | |
1164 | ||
1165 | args.ulTargetEngineClock = cpu_to_le32(tmp); | |
1166 | if (mem_clock) | |
1167 | args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); | |
1168 | ||
1169 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1170 | } | |
1171 | ||
9139d731 MSB |
1172 | void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, |
1173 | u16 *vddc, u16 *vddci, u16 *mvdd) | |
1174 | { | |
1175 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
1176 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
1177 | u8 frev, crev; | |
1178 | u16 data_offset; | |
1179 | union firmware_info *firmware_info; | |
1180 | ||
1181 | *vddc = 0; | |
1182 | *vddci = 0; | |
1183 | *mvdd = 0; | |
1184 | ||
1185 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, | |
1186 | &frev, &crev, &data_offset)) { | |
1187 | firmware_info = | |
1188 | (union firmware_info *)(mode_info->atom_context->bios + | |
1189 | data_offset); | |
1190 | *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); | |
1191 | if ((frev == 2) && (crev >= 2)) { | |
1192 | *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); | |
1193 | *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); | |
1194 | } | |
1195 | } | |
1196 | } | |
1197 | ||
d38ceaf9 AD |
1198 | union set_voltage { |
1199 | struct _SET_VOLTAGE_PS_ALLOCATION alloc; | |
1200 | struct _SET_VOLTAGE_PARAMETERS v1; | |
1201 | struct _SET_VOLTAGE_PARAMETERS_V2 v2; | |
1202 | struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; | |
1203 | }; | |
1204 | ||
9139d731 MSB |
1205 | int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, |
1206 | u16 voltage_id, u16 *voltage) | |
1207 | { | |
1208 | union set_voltage args; | |
1209 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
1210 | u8 frev, crev; | |
1211 | ||
1212 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
1213 | return -EINVAL; | |
1214 | ||
1215 | switch (crev) { | |
1216 | case 1: | |
1217 | return -EINVAL; | |
1218 | case 2: | |
1219 | args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; | |
1220 | args.v2.ucVoltageMode = 0; | |
1221 | args.v2.usVoltageLevel = 0; | |
1222 | ||
1223 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1224 | ||
1225 | *voltage = le16_to_cpu(args.v2.usVoltageLevel); | |
1226 | break; | |
1227 | case 3: | |
1228 | args.v3.ucVoltageType = voltage_type; | |
1229 | args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; | |
1230 | args.v3.usVoltageLevel = cpu_to_le16(voltage_id); | |
1231 | ||
1232 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1233 | ||
1234 | *voltage = le16_to_cpu(args.v3.usVoltageLevel); | |
1235 | break; | |
1236 | default: | |
1237 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1238 | return -EINVAL; | |
1239 | } | |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev, | |
1245 | u16 *voltage, | |
1246 | u16 leakage_idx) | |
1247 | { | |
1248 | return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); | |
1249 | } | |
1250 | ||
d38ceaf9 AD |
1251 | int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, |
1252 | u16 *leakage_id) | |
1253 | { | |
1254 | union set_voltage args; | |
1255 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
1256 | u8 frev, crev; | |
1257 | ||
1258 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
1259 | return -EINVAL; | |
1260 | ||
1261 | switch (crev) { | |
1262 | case 3: | |
1263 | case 4: | |
1264 | args.v3.ucVoltageType = 0; | |
1265 | args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; | |
1266 | args.v3.usVoltageLevel = 0; | |
1267 | ||
1268 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1269 | ||
1270 | *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); | |
1271 | break; | |
1272 | default: | |
1273 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1274 | return -EINVAL; | |
1275 | } | |
1276 | ||
1277 | return 0; | |
1278 | } | |
1279 | ||
1280 | int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, | |
1281 | u16 *vddc, u16 *vddci, | |
1282 | u16 virtual_voltage_id, | |
1283 | u16 vbios_voltage_id) | |
1284 | { | |
1285 | int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); | |
1286 | u8 frev, crev; | |
1287 | u16 data_offset, size; | |
1288 | int i, j; | |
1289 | ATOM_ASIC_PROFILING_INFO_V2_1 *profile; | |
1290 | u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; | |
1291 | ||
1292 | *vddc = 0; | |
1293 | *vddci = 0; | |
1294 | ||
1295 | if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1296 | &frev, &crev, &data_offset)) | |
1297 | return -EINVAL; | |
1298 | ||
1299 | profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) | |
1300 | (adev->mode_info.atom_context->bios + data_offset); | |
1301 | ||
1302 | switch (frev) { | |
1303 | case 1: | |
1304 | return -EINVAL; | |
1305 | case 2: | |
1306 | switch (crev) { | |
1307 | case 1: | |
1308 | if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) | |
1309 | return -EINVAL; | |
1310 | leakage_bin = (u16 *) | |
1311 | (adev->mode_info.atom_context->bios + data_offset + | |
1312 | le16_to_cpu(profile->usLeakageBinArrayOffset)); | |
1313 | vddc_id_buf = (u16 *) | |
1314 | (adev->mode_info.atom_context->bios + data_offset + | |
1315 | le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); | |
1316 | vddc_buf = (u16 *) | |
1317 | (adev->mode_info.atom_context->bios + data_offset + | |
1318 | le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); | |
1319 | vddci_id_buf = (u16 *) | |
1320 | (adev->mode_info.atom_context->bios + data_offset + | |
1321 | le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); | |
1322 | vddci_buf = (u16 *) | |
1323 | (adev->mode_info.atom_context->bios + data_offset + | |
1324 | le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); | |
1325 | ||
1326 | if (profile->ucElbVDDC_Num > 0) { | |
1327 | for (i = 0; i < profile->ucElbVDDC_Num; i++) { | |
1328 | if (vddc_id_buf[i] == virtual_voltage_id) { | |
1329 | for (j = 0; j < profile->ucLeakageBinNum; j++) { | |
1330 | if (vbios_voltage_id <= leakage_bin[j]) { | |
1331 | *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; | |
1332 | break; | |
1333 | } | |
1334 | } | |
1335 | break; | |
1336 | } | |
1337 | } | |
1338 | } | |
1339 | if (profile->ucElbVDDCI_Num > 0) { | |
1340 | for (i = 0; i < profile->ucElbVDDCI_Num; i++) { | |
1341 | if (vddci_id_buf[i] == virtual_voltage_id) { | |
1342 | for (j = 0; j < profile->ucLeakageBinNum; j++) { | |
1343 | if (vbios_voltage_id <= leakage_bin[j]) { | |
1344 | *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; | |
1345 | break; | |
1346 | } | |
1347 | } | |
1348 | break; | |
1349 | } | |
1350 | } | |
1351 | } | |
1352 | break; | |
1353 | default: | |
1354 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1355 | return -EINVAL; | |
1356 | } | |
1357 | break; | |
1358 | default: | |
1359 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1360 | return -EINVAL; | |
1361 | } | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | union get_voltage_info { | |
1367 | struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; | |
1368 | struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; | |
1369 | }; | |
1370 | ||
1371 | int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, | |
1372 | u16 virtual_voltage_id, | |
1373 | u16 *voltage) | |
1374 | { | |
1375 | int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); | |
1376 | u32 entry_id; | |
1377 | u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; | |
1378 | union get_voltage_info args; | |
1379 | ||
1380 | for (entry_id = 0; entry_id < count; entry_id++) { | |
1381 | if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == | |
1382 | virtual_voltage_id) | |
1383 | break; | |
1384 | } | |
1385 | ||
1386 | if (entry_id >= count) | |
1387 | return -EINVAL; | |
1388 | ||
1389 | args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; | |
1390 | args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; | |
1391 | args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); | |
1392 | args.in.ulSCLKFreq = | |
1393 | cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); | |
1394 | ||
1395 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1396 | ||
1397 | *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); | |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | union voltage_object_info { | |
1403 | struct _ATOM_VOLTAGE_OBJECT_INFO v1; | |
1404 | struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; | |
1405 | struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; | |
1406 | }; | |
1407 | ||
1408 | union voltage_object { | |
1409 | struct _ATOM_VOLTAGE_OBJECT v1; | |
1410 | struct _ATOM_VOLTAGE_OBJECT_V2 v2; | |
1411 | union _ATOM_VOLTAGE_OBJECT_V3 v3; | |
1412 | }; | |
1413 | ||
1414 | ||
1415 | static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, | |
1416 | u8 voltage_type, u8 voltage_mode) | |
1417 | { | |
1418 | u32 size = le16_to_cpu(v3->sHeader.usStructureSize); | |
1419 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); | |
1420 | u8 *start = (u8*)v3; | |
1421 | ||
1422 | while (offset < size) { | |
1423 | ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); | |
1424 | if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && | |
1425 | (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) | |
1426 | return vo; | |
1427 | offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); | |
1428 | } | |
1429 | return NULL; | |
1430 | } | |
1431 | ||
9139d731 MSB |
1432 | int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, |
1433 | u8 voltage_type, | |
1434 | u8 *svd_gpio_id, u8 *svc_gpio_id) | |
1435 | { | |
1436 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
1437 | u8 frev, crev; | |
1438 | u16 data_offset, size; | |
1439 | union voltage_object_info *voltage_info; | |
1440 | union voltage_object *voltage_object = NULL; | |
1441 | ||
1442 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1443 | &frev, &crev, &data_offset)) { | |
1444 | voltage_info = (union voltage_object_info *) | |
1445 | (adev->mode_info.atom_context->bios + data_offset); | |
1446 | ||
1447 | switch (frev) { | |
1448 | case 3: | |
1449 | switch (crev) { | |
1450 | case 1: | |
1451 | voltage_object = (union voltage_object *) | |
1452 | amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, | |
1453 | voltage_type, | |
1454 | VOLTAGE_OBJ_SVID2); | |
1455 | if (voltage_object) { | |
1456 | *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; | |
1457 | *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; | |
1458 | } else { | |
1459 | return -EINVAL; | |
1460 | } | |
1461 | break; | |
1462 | default: | |
1463 | DRM_ERROR("unknown voltage object table\n"); | |
1464 | return -EINVAL; | |
1465 | } | |
1466 | break; | |
1467 | default: | |
1468 | DRM_ERROR("unknown voltage object table\n"); | |
1469 | return -EINVAL; | |
1470 | } | |
1471 | ||
1472 | } | |
1473 | return 0; | |
1474 | } | |
1475 | ||
d38ceaf9 AD |
1476 | bool |
1477 | amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, | |
1478 | u8 voltage_type, u8 voltage_mode) | |
1479 | { | |
1480 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
1481 | u8 frev, crev; | |
1482 | u16 data_offset, size; | |
1483 | union voltage_object_info *voltage_info; | |
1484 | ||
1485 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1486 | &frev, &crev, &data_offset)) { | |
1487 | voltage_info = (union voltage_object_info *) | |
1488 | (adev->mode_info.atom_context->bios + data_offset); | |
1489 | ||
1490 | switch (frev) { | |
1491 | case 3: | |
1492 | switch (crev) { | |
1493 | case 1: | |
1494 | if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, | |
1495 | voltage_type, voltage_mode)) | |
1496 | return true; | |
1497 | break; | |
1498 | default: | |
1499 | DRM_ERROR("unknown voltage object table\n"); | |
1500 | return false; | |
1501 | } | |
1502 | break; | |
1503 | default: | |
1504 | DRM_ERROR("unknown voltage object table\n"); | |
1505 | return false; | |
1506 | } | |
1507 | ||
1508 | } | |
1509 | return false; | |
1510 | } | |
1511 | ||
1512 | int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, | |
1513 | u8 voltage_type, u8 voltage_mode, | |
1514 | struct atom_voltage_table *voltage_table) | |
1515 | { | |
1516 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
1517 | u8 frev, crev; | |
1518 | u16 data_offset, size; | |
1519 | int i; | |
1520 | union voltage_object_info *voltage_info; | |
1521 | union voltage_object *voltage_object = NULL; | |
1522 | ||
1523 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1524 | &frev, &crev, &data_offset)) { | |
1525 | voltage_info = (union voltage_object_info *) | |
1526 | (adev->mode_info.atom_context->bios + data_offset); | |
1527 | ||
1528 | switch (frev) { | |
1529 | case 3: | |
1530 | switch (crev) { | |
1531 | case 1: | |
1532 | voltage_object = (union voltage_object *) | |
1533 | amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, | |
1534 | voltage_type, voltage_mode); | |
1535 | if (voltage_object) { | |
1536 | ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = | |
1537 | &voltage_object->v3.asGpioVoltageObj; | |
1538 | VOLTAGE_LUT_ENTRY_V2 *lut; | |
1539 | if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) | |
1540 | return -EINVAL; | |
1541 | lut = &gpio->asVolGpioLut[0]; | |
1542 | for (i = 0; i < gpio->ucGpioEntryNum; i++) { | |
1543 | voltage_table->entries[i].value = | |
1544 | le16_to_cpu(lut->usVoltageValue); | |
1545 | voltage_table->entries[i].smio_low = | |
1546 | le32_to_cpu(lut->ulVoltageId); | |
1547 | lut = (VOLTAGE_LUT_ENTRY_V2 *) | |
1548 | ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); | |
1549 | } | |
1550 | voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); | |
1551 | voltage_table->count = gpio->ucGpioEntryNum; | |
1552 | voltage_table->phase_delay = gpio->ucPhaseDelay; | |
1553 | return 0; | |
1554 | } | |
1555 | break; | |
1556 | default: | |
1557 | DRM_ERROR("unknown voltage object table\n"); | |
1558 | return -EINVAL; | |
1559 | } | |
1560 | break; | |
1561 | default: | |
1562 | DRM_ERROR("unknown voltage object table\n"); | |
1563 | return -EINVAL; | |
1564 | } | |
1565 | } | |
1566 | return -EINVAL; | |
1567 | } | |
1568 | ||
1569 | union vram_info { | |
1570 | struct _ATOM_VRAM_INFO_V3 v1_3; | |
1571 | struct _ATOM_VRAM_INFO_V4 v1_4; | |
1572 | struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; | |
1573 | }; | |
1574 | ||
1575 | #define MEM_ID_MASK 0xff000000 | |
1576 | #define MEM_ID_SHIFT 24 | |
1577 | #define CLOCK_RANGE_MASK 0x00ffffff | |
1578 | #define CLOCK_RANGE_SHIFT 0 | |
1579 | #define LOW_NIBBLE_MASK 0xf | |
1580 | #define DATA_EQU_PREV 0 | |
1581 | #define DATA_FROM_TABLE 4 | |
1582 | ||
1583 | int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, | |
1584 | u8 module_index, | |
1585 | struct atom_mc_reg_table *reg_table) | |
1586 | { | |
1587 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); | |
1588 | u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; | |
1589 | u32 i = 0, j; | |
1590 | u16 data_offset, size; | |
1591 | union vram_info *vram_info; | |
1592 | ||
1593 | memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); | |
1594 | ||
1595 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1596 | &frev, &crev, &data_offset)) { | |
1597 | vram_info = (union vram_info *) | |
1598 | (adev->mode_info.atom_context->bios + data_offset); | |
1599 | switch (frev) { | |
1600 | case 1: | |
1601 | DRM_ERROR("old table version %d, %d\n", frev, crev); | |
1602 | return -EINVAL; | |
1603 | case 2: | |
1604 | switch (crev) { | |
1605 | case 1: | |
1606 | if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { | |
1607 | ATOM_INIT_REG_BLOCK *reg_block = | |
1608 | (ATOM_INIT_REG_BLOCK *) | |
1609 | ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); | |
1610 | ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = | |
1611 | (ATOM_MEMORY_SETTING_DATA_BLOCK *) | |
1612 | ((u8 *)reg_block + (2 * sizeof(u16)) + | |
1613 | le16_to_cpu(reg_block->usRegIndexTblSize)); | |
1614 | ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; | |
1615 | num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / | |
1616 | sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; | |
1617 | if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) | |
1618 | return -EINVAL; | |
1619 | while (i < num_entries) { | |
1620 | if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) | |
1621 | break; | |
1622 | reg_table->mc_reg_address[i].s1 = | |
1623 | (u16)(le16_to_cpu(format->usRegIndex)); | |
1624 | reg_table->mc_reg_address[i].pre_reg_data = | |
1625 | (u8)(format->ucPreRegDataLength); | |
1626 | i++; | |
1627 | format = (ATOM_INIT_REG_INDEX_FORMAT *) | |
1628 | ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); | |
1629 | } | |
1630 | reg_table->last = i; | |
1631 | while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && | |
1632 | (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { | |
1633 | t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) | |
1634 | >> MEM_ID_SHIFT); | |
1635 | if (module_index == t_mem_id) { | |
1636 | reg_table->mc_reg_table_entry[num_ranges].mclk_max = | |
1637 | (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) | |
1638 | >> CLOCK_RANGE_SHIFT); | |
1639 | for (i = 0, j = 1; i < reg_table->last; i++) { | |
1640 | if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { | |
1641 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | |
1642 | (u32)le32_to_cpu(*((u32 *)reg_data + j)); | |
1643 | j++; | |
1644 | } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { | |
1645 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | |
1646 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; | |
1647 | } | |
1648 | } | |
1649 | num_ranges++; | |
1650 | } | |
1651 | reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) | |
1652 | ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); | |
1653 | } | |
1654 | if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) | |
1655 | return -EINVAL; | |
1656 | reg_table->num_entries = num_ranges; | |
1657 | } else | |
1658 | return -EINVAL; | |
1659 | break; | |
1660 | default: | |
1661 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1662 | return -EINVAL; | |
1663 | } | |
1664 | break; | |
1665 | default: | |
1666 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1667 | return -EINVAL; | |
1668 | } | |
1669 | return 0; | |
1670 | } | |
1671 | return -EINVAL; | |
1672 | } | |
1673 | ||
e74adf20 AD |
1674 | bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev) |
1675 | { | |
1676 | int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo); | |
1677 | u8 frev, crev; | |
1678 | u16 data_offset, size; | |
1679 | ||
1680 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1681 | &frev, &crev, &data_offset)) | |
1682 | return true; | |
1683 | ||
1684 | return false; | |
1685 | } | |
1686 | ||
d38ceaf9 AD |
1687 | void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) |
1688 | { | |
1689 | uint32_t bios_6_scratch; | |
1690 | ||
3164cba3 | 1691 | bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); |
d38ceaf9 AD |
1692 | |
1693 | if (lock) { | |
1694 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; | |
1695 | bios_6_scratch &= ~ATOM_S6_ACC_MODE; | |
1696 | } else { | |
1697 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; | |
1698 | bios_6_scratch |= ATOM_S6_ACC_MODE; | |
1699 | } | |
1700 | ||
3164cba3 | 1701 | WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); |
d38ceaf9 AD |
1702 | } |
1703 | ||
4e89df63 | 1704 | static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1705 | { |
1706 | uint32_t bios_2_scratch, bios_6_scratch; | |
1707 | ||
3164cba3 AD |
1708 | adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0; |
1709 | ||
1710 | bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2); | |
1711 | bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); | |
d38ceaf9 AD |
1712 | |
1713 | /* let the bios control the backlight */ | |
1714 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; | |
1715 | ||
1716 | /* tell the bios not to handle mode switching */ | |
1717 | bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; | |
1718 | ||
1719 | /* clear the vbios dpms state */ | |
1720 | bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; | |
1721 | ||
3164cba3 AD |
1722 | WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch); |
1723 | WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); | |
d38ceaf9 AD |
1724 | } |
1725 | ||
72a57438 AD |
1726 | void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, |
1727 | bool hung) | |
1728 | { | |
3164cba3 | 1729 | u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3); |
72a57438 AD |
1730 | |
1731 | if (hung) | |
1732 | tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
1733 | else | |
1734 | tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
1735 | ||
3164cba3 | 1736 | WREG32(adev->bios_scratch_reg_offset + 3, tmp); |
72a57438 AD |
1737 | } |
1738 | ||
4426826c AD |
1739 | bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev) |
1740 | { | |
1741 | u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7); | |
1742 | ||
1743 | if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK) | |
1744 | return false; | |
1745 | else | |
1746 | return true; | |
1747 | } | |
1748 | ||
4f626a4a RK |
1749 | /* Atom needs data in little endian format so swap as appropriate when copying |
1750 | * data to or from atom. Note that atom operates on dw units. | |
1751 | * | |
1752 | * Use to_le=true when sending data to atom and provide at least | |
1753 | * ALIGN(num_bytes,4) bytes in the dst buffer. | |
1754 | * | |
1755 | * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4) | |
1756 | * byes in the src buffer. | |
d38ceaf9 AD |
1757 | */ |
1758 | void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) | |
1759 | { | |
1760 | #ifdef __BIG_ENDIAN | |
4f626a4a | 1761 | u32 src_tmp[5], dst_tmp[5]; |
d38ceaf9 | 1762 | int i; |
4f626a4a | 1763 | u8 align_num_bytes = ALIGN(num_bytes, 4); |
d38ceaf9 | 1764 | |
d38ceaf9 | 1765 | if (to_le) { |
4f626a4a RK |
1766 | memcpy(src_tmp, src, num_bytes); |
1767 | for (i = 0; i < align_num_bytes / 4; i++) | |
1768 | dst_tmp[i] = cpu_to_le32(src_tmp[i]); | |
1769 | memcpy(dst, dst_tmp, align_num_bytes); | |
d38ceaf9 | 1770 | } else { |
4f626a4a RK |
1771 | memcpy(src_tmp, src, align_num_bytes); |
1772 | for (i = 0; i < align_num_bytes / 4; i++) | |
1773 | dst_tmp[i] = le32_to_cpu(src_tmp[i]); | |
1774 | memcpy(dst, dst_tmp, num_bytes); | |
d38ceaf9 AD |
1775 | } |
1776 | #else | |
1777 | memcpy(dst, src, num_bytes); | |
1778 | #endif | |
1779 | } | |
43bf11bd | 1780 | |
4e89df63 | 1781 | static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev) |
43bf11bd AD |
1782 | { |
1783 | struct atom_context *ctx = adev->mode_info.atom_context; | |
1784 | int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); | |
1785 | uint16_t data_offset; | |
1786 | int usage_bytes = 0; | |
1787 | struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; | |
a05502e5 HC |
1788 | u64 start_addr; |
1789 | u64 size; | |
43bf11bd AD |
1790 | |
1791 | if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { | |
1792 | firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); | |
1793 | ||
1794 | DRM_DEBUG("atom firmware requested %08x %dkb\n", | |
1795 | le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), | |
1796 | le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); | |
1797 | ||
a05502e5 HC |
1798 | start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware; |
1799 | size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb; | |
1800 | ||
1801 | if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == | |
1802 | (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << | |
1803 | ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { | |
1804 | /* Firmware request VRAM reservation for SR-IOV */ | |
1805 | adev->fw_vram_usage.start_offset = (start_addr & | |
1806 | (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; | |
1807 | adev->fw_vram_usage.size = size << 10; | |
1808 | /* Use the default scratch size */ | |
1809 | usage_bytes = 0; | |
1810 | } else { | |
1811 | usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; | |
1812 | } | |
43bf11bd AD |
1813 | } |
1814 | ctx->scratch_size_bytes = 0; | |
1815 | if (usage_bytes == 0) | |
1816 | usage_bytes = 20 * 1024; | |
1817 | /* allocate some scratch memory */ | |
1818 | ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); | |
1819 | if (!ctx->scratch) | |
1820 | return -ENOMEM; | |
1821 | ctx->scratch_size_bytes = usage_bytes; | |
1822 | return 0; | |
1823 | } | |
4e89df63 AD |
1824 | |
1825 | /* ATOM accessor methods */ | |
1826 | /* | |
1827 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
1828 | * driver registers callbacks to access registers and the interpreter | |
1829 | * in the driver parses the tables and executes then to program specific | |
1830 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
1831 | * atombios.h, and atom.c | |
1832 | */ | |
1833 | ||
1834 | /** | |
1835 | * cail_pll_read - read PLL register | |
1836 | * | |
1837 | * @info: atom card_info pointer | |
1838 | * @reg: PLL register offset | |
1839 | * | |
1840 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
1841 | * Returns the value of the PLL register. | |
1842 | */ | |
1843 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
1844 | { | |
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | /** | |
1849 | * cail_pll_write - write PLL register | |
1850 | * | |
1851 | * @info: atom card_info pointer | |
1852 | * @reg: PLL register offset | |
1853 | * @val: value to write to the pll register | |
1854 | * | |
1855 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
1856 | */ | |
1857 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
1858 | { | |
1859 | ||
1860 | } | |
1861 | ||
1862 | /** | |
1863 | * cail_mc_read - read MC (Memory Controller) register | |
1864 | * | |
1865 | * @info: atom card_info pointer | |
1866 | * @reg: MC register offset | |
1867 | * | |
1868 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
1869 | * Returns the value of the MC register. | |
1870 | */ | |
1871 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
1872 | { | |
1873 | return 0; | |
1874 | } | |
1875 | ||
1876 | /** | |
1877 | * cail_mc_write - write MC (Memory Controller) register | |
1878 | * | |
1879 | * @info: atom card_info pointer | |
1880 | * @reg: MC register offset | |
1881 | * @val: value to write to the pll register | |
1882 | * | |
1883 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
1884 | */ | |
1885 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
1886 | { | |
1887 | ||
1888 | } | |
1889 | ||
1890 | /** | |
1891 | * cail_reg_write - write MMIO register | |
1892 | * | |
1893 | * @info: atom card_info pointer | |
1894 | * @reg: MMIO register offset | |
1895 | * @val: value to write to the pll register | |
1896 | * | |
1897 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
1898 | */ | |
1899 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
1900 | { | |
1901 | struct amdgpu_device *adev = info->dev->dev_private; | |
1902 | ||
1903 | WREG32(reg, val); | |
1904 | } | |
1905 | ||
1906 | /** | |
1907 | * cail_reg_read - read MMIO register | |
1908 | * | |
1909 | * @info: atom card_info pointer | |
1910 | * @reg: MMIO register offset | |
1911 | * | |
1912 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
1913 | * Returns the value of the MMIO register. | |
1914 | */ | |
1915 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
1916 | { | |
1917 | struct amdgpu_device *adev = info->dev->dev_private; | |
1918 | uint32_t r; | |
1919 | ||
1920 | r = RREG32(reg); | |
1921 | return r; | |
1922 | } | |
1923 | ||
1924 | /** | |
1925 | * cail_ioreg_write - write IO register | |
1926 | * | |
1927 | * @info: atom card_info pointer | |
1928 | * @reg: IO register offset | |
1929 | * @val: value to write to the pll register | |
1930 | * | |
1931 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
1932 | */ | |
1933 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
1934 | { | |
1935 | struct amdgpu_device *adev = info->dev->dev_private; | |
1936 | ||
1937 | WREG32_IO(reg, val); | |
1938 | } | |
1939 | ||
1940 | /** | |
1941 | * cail_ioreg_read - read IO register | |
1942 | * | |
1943 | * @info: atom card_info pointer | |
1944 | * @reg: IO register offset | |
1945 | * | |
1946 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
1947 | * Returns the value of the IO register. | |
1948 | */ | |
1949 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
1950 | { | |
1951 | struct amdgpu_device *adev = info->dev->dev_private; | |
1952 | uint32_t r; | |
1953 | ||
1954 | r = RREG32_IO(reg); | |
1955 | return r; | |
1956 | } | |
1957 | ||
1958 | static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, | |
1959 | struct device_attribute *attr, | |
1960 | char *buf) | |
1961 | { | |
1962 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1963 | struct amdgpu_device *adev = ddev->dev_private; | |
1964 | struct atom_context *ctx = adev->mode_info.atom_context; | |
1965 | ||
1966 | return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version); | |
1967 | } | |
1968 | ||
1969 | static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, | |
1970 | NULL); | |
1971 | ||
1972 | /** | |
1973 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
1974 | * | |
1975 | * @adev: amdgpu_device pointer | |
1976 | * | |
1977 | * Frees the driver info and register access callbacks for the ATOM | |
1978 | * interpreter (r4xx+). | |
1979 | * Called at driver shutdown. | |
1980 | */ | |
1981 | void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
1982 | { | |
1983 | if (adev->mode_info.atom_context) { | |
1984 | kfree(adev->mode_info.atom_context->scratch); | |
1985 | kfree(adev->mode_info.atom_context->iio); | |
1986 | } | |
1987 | kfree(adev->mode_info.atom_context); | |
1988 | adev->mode_info.atom_context = NULL; | |
1989 | kfree(adev->mode_info.atom_card_info); | |
1990 | adev->mode_info.atom_card_info = NULL; | |
1991 | device_remove_file(adev->dev, &dev_attr_vbios_version); | |
1992 | } | |
1993 | ||
1994 | /** | |
1995 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
1996 | * | |
1997 | * @adev: amdgpu_device pointer | |
1998 | * | |
1999 | * Initializes the driver info and register access callbacks for the | |
2000 | * ATOM interpreter (r4xx+). | |
2001 | * Returns 0 on sucess, -ENOMEM on failure. | |
2002 | * Called at driver startup. | |
2003 | */ | |
2004 | int amdgpu_atombios_init(struct amdgpu_device *adev) | |
2005 | { | |
2006 | struct card_info *atom_card_info = | |
2007 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
2008 | int ret; | |
2009 | ||
2010 | if (!atom_card_info) | |
2011 | return -ENOMEM; | |
2012 | ||
2013 | adev->mode_info.atom_card_info = atom_card_info; | |
2014 | atom_card_info->dev = adev->ddev; | |
2015 | atom_card_info->reg_read = cail_reg_read; | |
2016 | atom_card_info->reg_write = cail_reg_write; | |
2017 | /* needed for iio ops */ | |
2018 | if (adev->rio_mem) { | |
2019 | atom_card_info->ioreg_read = cail_ioreg_read; | |
2020 | atom_card_info->ioreg_write = cail_ioreg_write; | |
2021 | } else { | |
2022 | DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); | |
2023 | atom_card_info->ioreg_read = cail_reg_read; | |
2024 | atom_card_info->ioreg_write = cail_reg_write; | |
2025 | } | |
2026 | atom_card_info->mc_read = cail_mc_read; | |
2027 | atom_card_info->mc_write = cail_mc_write; | |
2028 | atom_card_info->pll_read = cail_pll_read; | |
2029 | atom_card_info->pll_write = cail_pll_write; | |
2030 | ||
2031 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
2032 | if (!adev->mode_info.atom_context) { | |
2033 | amdgpu_atombios_fini(adev); | |
2034 | return -ENOMEM; | |
2035 | } | |
2036 | ||
2037 | mutex_init(&adev->mode_info.atom_context->mutex); | |
2038 | if (adev->is_atom_fw) { | |
2039 | amdgpu_atomfirmware_scratch_regs_init(adev); | |
2040 | amdgpu_atomfirmware_allocate_fb_scratch(adev); | |
2041 | } else { | |
2042 | amdgpu_atombios_scratch_regs_init(adev); | |
2043 | amdgpu_atombios_allocate_fb_scratch(adev); | |
2044 | } | |
2045 | ||
2046 | ret = device_create_file(adev->dev, &dev_attr_vbios_version); | |
2047 | if (ret) { | |
2048 | DRM_ERROR("Failed to create device file for VBIOS version\n"); | |
2049 | return ret; | |
2050 | } | |
2051 | ||
2052 | return 0; | |
2053 | } | |
2054 |