[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */

#ifndef AMDGPU_AMDKFD_H_INCLUDED
#define AMDGPU_AMDKFD_H_INCLUDED

#include <linux/types.h>
#include <linux/mm.h>
#include <linux/kthread.h>
#include <linux/workqueue.h>
#include <linux/mmu_notifier.h>
#include <kgd_kfd_interface.h>
#include <drm/ttm/ttm_execbuf_util.h>
#include "amdgpu_sync.h"
#include "amdgpu_vm.h"

extern uint64_t amdgpu_amdkfd_total_mem_size;

enum TLB_FLUSH_TYPE {
	TLB_FLUSH_LEGACY = 0,
	TLB_FLUSH_LIGHTWEIGHT,
	TLB_FLUSH_HEAVYWEIGHT
};

struct amdgpu_device;

enum kfd_mem_attachment_type {
	KFD_MEM_ATT_SHARED,	/* Share kgd_mem->bo or another attachment's */
	KFD_MEM_ATT_USERPTR,	/* SG bo to DMA map pages from a userptr bo */
	KFD_MEM_ATT_DMABUF,	/* DMAbuf to DMA map TTM BOs */
	KFD_MEM_ATT_SG		/* Tag to DMA map SG BOs */
};

struct kfd_mem_attachment {
	struct list_head list;
	enum kfd_mem_attachment_type type;
	bool is_mapped;
	struct amdgpu_bo_va *bo_va;
	struct amdgpu_device *adev;
	uint64_t va;
	uint64_t pte_flags;
};

struct kgd_mem {
	struct mutex lock;
	struct amdgpu_bo *bo;
	struct dma_buf *dmabuf;
	struct hmm_range *range;
	struct list_head attachments;
	/* protected by amdkfd_process_info.lock */
	struct ttm_validate_buffer validate_list;
	struct ttm_validate_buffer resv_list;
	uint32_t domain;
	unsigned int mapped_to_gpu_memory;
	uint64_t va;

	uint32_t alloc_flags;

	uint32_t invalid;
	struct amdkfd_process_info *process_info;

	struct amdgpu_sync sync;

	bool aql_queue;
	bool is_imported;
};

/* KFD Memory Eviction */
struct amdgpu_amdkfd_fence {
	struct dma_fence base;
	struct mm_struct *mm;
	spinlock_t lock;
	char timeline_name[TASK_COMM_LEN];
	struct svm_range_bo *svm_bo;
};

struct amdgpu_kfd_dev {
	struct kfd_dev *dev;
	int64_t vram_used;
	uint64_t vram_used_aligned;
	bool init_complete;
	struct work_struct reset_work;
};

enum kgd_engine_type {
	KGD_ENGINE_PFP = 1,
	KGD_ENGINE_ME,
	KGD_ENGINE_CE,
	KGD_ENGINE_MEC1,
	KGD_ENGINE_MEC2,
	KGD_ENGINE_RLC,
	KGD_ENGINE_SDMA1,
	KGD_ENGINE_SDMA2,
	KGD_ENGINE_MAX
};


struct amdkfd_process_info {
	/* List head of all VMs that belong to a KFD process */
	struct list_head vm_list_head;
	/* List head for all KFD BOs that belong to a KFD process. */
	struct list_head kfd_bo_list;
	/* List of userptr BOs that are valid or invalid */
	struct list_head userptr_valid_list;
	struct list_head userptr_inval_list;
	/* Lock to protect kfd_bo_list */
	struct mutex lock;

	/* Number of VMs */
	unsigned int n_vms;
	/* Eviction Fence */
	struct amdgpu_amdkfd_fence *eviction_fence;

	/* MMU-notifier related fields */
	struct mutex notifier_lock;
	uint32_t evicted_bos;
	struct delayed_work restore_userptr_work;
	struct pid *pid;
	bool block_mmu_notifications;
};

int amdgpu_amdkfd_init(void);
void amdgpu_amdkfd_fini(void);

void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev);
int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
			const void *ih_ring_entry);
void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
				enum kgd_engine_type engine,
				uint32_t vmid, uint64_t gpu_addr,
				uint32_t *ib_cmd, uint32_t ib_len);
void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
				uint16_t vmid);
int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
				uint16_t pasid, enum TLB_FLUSH_TYPE flush_type);

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);

int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);

int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);

void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);

int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
					int queue_bit);

struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
				struct mm_struct *mm,
				struct svm_range_bo *svm_bo);
#if defined(CONFIG_DEBUG_FS)
int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
#endif
#if IS_ENABLED(CONFIG_HSA_AMD)
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
				unsigned long cur_seq, struct kgd_mem *mem);
#else
static inline
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
{
	return false;
}

static inline
struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
{
	return NULL;
}

static inline
int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
{
	return 0;
}

static inline
int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
				unsigned long cur_seq, struct kgd_mem *mem)
{
	return 0;
}
#endif
/* Shared API */
int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
				void **mem_obj, uint64_t *gpu_addr,
				void **cpu_ptr, bool mqd_gfx9);
void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj);
int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
				void **mem_obj);
void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
				      enum kgd_engine_type type);
void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
				      struct kfd_local_mem_info *mem_info);
uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);

uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev,
			       struct kfd_cu_info *cu_info);
int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
				  struct amdgpu_device **dmabuf_adev,
				  uint64_t *bo_size, void *metadata_buffer,
				  size_t buffer_size, uint32_t *metadata_size,
				  uint32_t *flags);
uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
					  struct amdgpu_device *src);
int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
					    struct amdgpu_device *src,
					    bool is_min);
int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);

/* Read user wptr from a specified user address space with page fault
 * disabled. The memory must be pinned and mapped to the hardware when
 * this is called in hqd_load functions, so it should never fault in
 * the first place. This resolves a circular lock dependency involving
 * four locks, including the DQM lock and mmap_lock.
 */
#define read_user_wptr(mmptr, wptr, dst)				\
	({								\
		bool valid = false;					\
		if ((mmptr) && (wptr)) {				\
			pagefault_disable();				\
			if ((mmptr) == current->mm) {			\
				valid = !get_user((dst), (wptr));	\
			} else if (current->flags & PF_KTHREAD) {	\
				kthread_use_mm(mmptr);			\
				valid = !get_user((dst), (wptr));	\
				kthread_unuse_mm(mmptr);		\
			}						\
			pagefault_enable();				\
		}							\
		valid;							\
	})

/* GPUVM API */
#define drm_priv_to_vm(drm_priv)					\
	(&((struct amdgpu_fpriv *)					\
		((struct drm_file *)(drm_priv))->driver_priv)->vm)

int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
				     struct amdgpu_vm *avm, u32 pasid);
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
					struct amdgpu_vm *avm,
					void **process_info,
					struct dma_fence **ef);
void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
					void *drm_priv);
uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev);
int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
		struct amdgpu_device *adev, uint64_t va, uint64_t size,
		void *drm_priv, struct kgd_mem **mem,
		uint64_t *offset, uint32_t flags, bool criu_resume);
int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
		uint64_t *size);
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
					  struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_sync_memory(
		struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
					     void **kptr, uint64_t *size);
void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);

int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo);

int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
					    struct dma_fence **ef);
int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
					      struct kfd_vm_fault_info *info);
int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
				      struct dma_buf *dmabuf,
				      uint64_t va, void *drm_priv,
				      struct kgd_mem **mem, uint64_t *size,
				      uint64_t *mmap_offset);
int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
				      struct dma_buf **dmabuf);
int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
				struct tile_config *config);
void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
				bool reset);
bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);
void amdgpu_amdkfd_block_mmu_notifications(void *p);
int amdgpu_amdkfd_criu_resume(void *p);
bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
		uint64_t size, u32 alloc_flag);
void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
		uint64_t size, u32 alloc_flag);

#if IS_ENABLED(CONFIG_HSA_AMD)
void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
				struct amdgpu_vm *vm);

/**
 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
 *
 * Allows KFD to release its resources associated with the GEM object.
 */
void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
#else
static inline
void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
{
}

static inline
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
					struct amdgpu_vm *vm)
{
}

static inline
void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
{
}
#endif
/* KGD2KFD callbacks */
int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
int kgd2kfd_resume_mm(struct mm_struct *mm);
int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
						struct dma_fence *fence);
#if IS_ENABLED(CONFIG_HSA_AMD)
int kgd2kfd_init(void);
void kgd2kfd_exit(void);
struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
bool kgd2kfd_device_init(struct kfd_dev *kfd,
			 const struct kgd2kfd_shared_resources *gpu_resources);
void kgd2kfd_device_exit(struct kfd_dev *kfd);
void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
int kgd2kfd_resume_iommu(struct kfd_dev *kfd);
int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
int kgd2kfd_pre_reset(struct kfd_dev *kfd);
int kgd2kfd_post_reset(struct kfd_dev *kfd);
void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
#else
static inline int kgd2kfd_init(void)
{
	return -ENOENT;
}

static inline void kgd2kfd_exit(void)
{
}

static inline
struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
{
	return NULL;
}

static inline
bool kgd2kfd_device_init(struct kfd_dev *kfd,
				const struct kgd2kfd_shared_resources *gpu_resources)
{
	return false;
}

static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
{
}

static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
{
}

static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd)
{
	return 0;
}

static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
{
	return 0;
}

static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
{
	return 0;
}

static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
{
	return 0;
}

static inline
void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
{
}

static inline
void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
{
}

static inline
void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
{
}
#endif
#endif /* AMDGPU_AMDKFD_H_INCLUDED */
Commit	Line	Data
130e0371 OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
	24
	25	#ifndef AMDGPU_AMDKFD_H_INCLUDED
	26	#define AMDGPU_AMDKFD_H_INCLUDED
	27
	28	#include <linux/types.h>
7420f482	29	#include <linux/mm.h>
9bf5b9eb	30	#include <linux/kthread.h>
5ae0283e	31	#include <linux/workqueue.h>
f95f51a4	32	#include <linux/mmu_notifier.h>
130e0371	33	#include <kgd_kfd_interface.h>
a46a2cd1 FK	34	#include <drm/ttm/ttm_execbuf_util.h>
	35	#include "amdgpu_sync.h"
	36	#include "amdgpu_vm.h"
130e0371	37
611736d8	38	extern uint64_t amdgpu_amdkfd_total_mem_size;
d8d019cc	39
765385ec PY	40	enum TLB_FLUSH_TYPE {
	41	TLB_FLUSH_LEGACY = 0,
	42	TLB_FLUSH_LIGHTWEIGHT,
	43	TLB_FLUSH_HEAVYWEIGHT
	44	};
	45
130e0371 OG	46	struct amdgpu_device;
130e0371 OG	47
264fb4d3 FK	48	enum kfd_mem_attachment_type {
	49	KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
	50	KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
5ac3c3e4	51	KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
08a2fd23	52	KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */
264fb4d3 FK	53	};
264fb4d3 FK	54
c780b2ee FK	55	struct kfd_mem_attachment {
c780b2ee FK	56	struct list_head list;
264fb4d3	57	enum kfd_mem_attachment_type type;
a46a2cd1	58	bool is_mapped;
a46a2cd1	59	struct amdgpu_bo_va *bo_va;
c780b2ee	60	struct amdgpu_device *adev;
a46a2cd1 FK	61	uint64_t va;
	62	uint64_t pte_flags;
	63	};
	64
130e0371	65	struct kgd_mem {
a46a2cd1	66	struct mutex lock;
130e0371	67	struct amdgpu_bo *bo;
5ac3c3e4	68	struct dma_buf *dmabuf;
f95f51a4	69	struct hmm_range *range;
c780b2ee	70	struct list_head attachments;
a46a2cd1 FK	71	/* protected by amdkfd_process_info.lock */
	72	struct ttm_validate_buffer validate_list;
	73	struct ttm_validate_buffer resv_list;
	74	uint32_t domain;
	75	unsigned int mapped_to_gpu_memory;
	76	uint64_t va;
	77
d0ba51b1	78	uint32_t alloc_flags;
a46a2cd1	79
f95f51a4	80	uint32_t invalid;
a46a2cd1 FK	81	struct amdkfd_process_info *process_info;
	82
	83	struct amdgpu_sync sync;
	84
	85	bool aql_queue;
d4566dee	86	bool is_imported;
130e0371 OG	87	};
130e0371 OG	88
d8d019cc FK	89	/* KFD Memory Eviction */
	90	struct amdgpu_amdkfd_fence {
	91	struct dma_fence base;
	92	struct mm_struct *mm;
	93	spinlock_t lock;
	94	char timeline_name[TASK_COMM_LEN];
eb2cec55	95	struct svm_range_bo *svm_bo;
d8d019cc FK	96	};
d8d019cc FK	97
611736d8 FK	98	struct amdgpu_kfd_dev {
611736d8 FK	99	struct kfd_dev *dev;
0c2dece8	100	int64_t vram_used;
1ac354be	101	uint64_t vram_used_aligned;
8e2712e7	102	bool init_complete;
b5fd0cf3	103	struct work_struct reset_work;
611736d8 FK	104	};
611736d8 FK	105
0da8b10e AL	106	enum kgd_engine_type {
	107	KGD_ENGINE_PFP = 1,
	108	KGD_ENGINE_ME,
	109	KGD_ENGINE_CE,
	110	KGD_ENGINE_MEC1,
	111	KGD_ENGINE_MEC2,
	112	KGD_ENGINE_RLC,
	113	KGD_ENGINE_SDMA1,
	114	KGD_ENGINE_SDMA2,
	115	KGD_ENGINE_MAX
	116	};
	117
d8d019cc	118
a46a2cd1 FK	119	struct amdkfd_process_info {
	120	/* List head of all VMs that belong to a KFD process */
	121	struct list_head vm_list_head;
	122	/* List head for all KFD BOs that belong to a KFD process. */
	123	struct list_head kfd_bo_list;
5ae0283e FK	124	/* List of userptr BOs that are valid or invalid */
	125	struct list_head userptr_valid_list;
	126	struct list_head userptr_inval_list;
a46a2cd1 FK	127	/* Lock to protect kfd_bo_list */
	128	struct mutex lock;
	129
	130	/* Number of VMs */
	131	unsigned int n_vms;
	132	/* Eviction Fence */
	133	struct amdgpu_amdkfd_fence *eviction_fence;
5ae0283e FK	134
5ae0283e FK	135	/* MMU-notifier related fields */
f95f51a4 FK	136	struct mutex notifier_lock;
f95f51a4 FK	137	uint32_t evicted_bos;
5ae0283e FK	138	struct delayed_work restore_userptr_work;
5ae0283e FK	139	struct pid *pid;
011bbb03	140	bool block_mmu_notifications;
a46a2cd1 FK	141	};
a46a2cd1 FK	142
efb1c658	143	int amdgpu_amdkfd_init(void);
130e0371 OG	144	void amdgpu_amdkfd_fini(void);
130e0371 OG	145
9593f4d6	146	void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
80660084	147	int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev);
9593f4d6	148	int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
dc102c43	149	void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
130e0371	150	const void *ih_ring_entry);
dc102c43 AR	151	void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
dc102c43 AR	152	void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
e9669fb7	153	void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
6bfc7c7e GS	154	int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
6bfc7c7e GS	155	enum kgd_engine_type engine,
4c660c8f FK	156	uint32_t vmid, uint64_t gpu_addr,
4c660c8f FK	157	uint32_t *ib_cmd, uint32_t ib_len);
6bfc7c7e GS	158	void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
	159	bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
	160	int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
	161	uint16_t vmid);
	162	int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
	163	uint16_t pasid, enum TLB_FLUSH_TYPE flush_type);
4c660c8f	164
155494db FK	165	bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
155494db FK	166
5c6dd71e SL	167	int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
	168
	169	int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
	170
6bfc7c7e	171	void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);
24da5a9c	172
d09f85d5 YZ	173	int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
	174	int queue_bit);
	175
cd63989e	176	struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
eb2cec55 AS	177	struct mm_struct *mm,
eb2cec55 AS	178	struct svm_range_bo *svm_bo);
3d2af401 AS	179	#if defined(CONFIG_DEBUG_FS)
	180	int kfd_debugfs_kfd_mem_limits(struct seq_file m, void data);
	181	#endif
cd63989e LY	182	#if IS_ENABLED(CONFIG_HSA_AMD)
	183	bool amdkfd_fence_check_mm(struct dma_fence f, struct mm_struct mm);
	184	struct amdgpu_amdkfd_fence to_amdgpu_amdkfd_fence(struct dma_fence f);
	185	int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
f95f51a4 FK	186	int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
f95f51a4 FK	187	unsigned long cur_seq, struct kgd_mem *mem);
cd63989e LY	188	#else
	189	static inline
	190	bool amdkfd_fence_check_mm(struct dma_fence f, struct mm_struct mm)
	191	{
	192	return false;
	193	}
	194
	195	static inline
	196	struct amdgpu_amdkfd_fence to_amdgpu_amdkfd_fence(struct dma_fence f)
	197	{
	198	return NULL;
	199	}
	200
	201	static inline
	202	int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
	203	{
	204	return 0;
	205	}
	206
	207	static inline
f95f51a4 FK	208	int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
f95f51a4 FK	209	unsigned long cur_seq, struct kgd_mem *mem)
cd63989e LY	210	{
	211	return 0;
	212	}
	213	#endif
130e0371	214	/* Shared API */
6bfc7c7e	215	int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
7cd52c91 AL	216	void *mem_obj, uint64_t gpu_addr,
7cd52c91 AL	217	void **cpu_ptr, bool mqd_gfx9);
6bfc7c7e GS	218	void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device adev, void mem_obj);
	219	int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
	220	void **mem_obj);
	221	void amdgpu_amdkfd_free_gws(struct amdgpu_device adev, void mem_obj);
71efab6a OZ	222	int amdgpu_amdkfd_add_gws_to_process(void info, void gws, struct kgd_mem **mem);
71efab6a OZ	223	int amdgpu_amdkfd_remove_gws_from_process(void info, void mem);
574c4183	224	uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
0da8b10e	225	enum kgd_engine_type type);
574c4183	226	void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
7cd52c91	227	struct kfd_local_mem_info *mem_info);
574c4183	228	uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
7cd52c91	229
574c4183 GS	230	uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
	231	void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev,
	232	struct kfd_cu_info *cu_info);
	233	int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
	234	struct amdgpu_device **dmabuf_adev,
1dde0ea9 FK	235	uint64_t bo_size, void metadata_buffer,
	236	size_t buffer_size, uint32_t *metadata_size,
	237	uint32_t *flags);
574c4183 GS	238	uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
	239	struct amdgpu_device *src);
	240	int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
	241	struct amdgpu_device *src,
	242	bool is_min);
	243	int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
130e0371	244
cd05c865 FK	245	/* Read user wptr from a specified user address space with page fault
	246	* disabled. The memory must be pinned and mapped to the hardware when
	247	* this is called in hqd_load functions, so it should never fault in
	248	* the first place. This resolves a circular lock dependency involving
c1e8d7c6	249	* four locks, including the DQM lock and mmap_lock.
cd05c865	250	*/
70539bd7 FK	251	#define read_user_wptr(mmptr, wptr, dst) \
	252	({ \
	253	bool valid = false; \
	254	if ((mmptr) && (wptr)) { \
cd05c865	255	pagefault_disable(); \
70539bd7 FK	256	if ((mmptr) == current->mm) { \
70539bd7 FK	257	valid = !get_user((dst), (wptr)); \
8449d150	258	} else if (current->flags & PF_KTHREAD) { \
f5678e7f	259	kthread_use_mm(mmptr); \
70539bd7	260	valid = !get_user((dst), (wptr)); \
f5678e7f	261	kthread_unuse_mm(mmptr); \
70539bd7	262	} \
cd05c865	263	pagefault_enable(); \
70539bd7 FK	264	} \
	265	valid; \
	266	})
	267
a46a2cd1	268	/* GPUVM API */
f80fe9d3 FK	269	#define drm_priv_to_vm(drm_priv) \
	270	(&((struct amdgpu_fpriv *) \
	271	((struct drm_file *)(drm_priv))->driver_priv)->vm)
	272
41d82649	273	int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
23b02b0e	274	struct amdgpu_vm *avm, u32 pasid);
dff63da9	275	int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
23b02b0e	276	struct amdgpu_vm *avm,
b40a6ab2	277	void **process_info,
fcdfa432	278	struct dma_fence **ef);
dff63da9 GS	279	void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
dff63da9 GS	280	void *drm_priv);
b40a6ab2	281	uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
9731dd4c	282	size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev);
a46a2cd1	283	int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
dff63da9	284	struct amdgpu_device *adev, uint64_t va, uint64_t size,
b40a6ab2	285	void drm_priv, struct kgd_mem *mem,
011bbb03	286	uint64_t *offset, uint32_t flags, bool criu_resume);
a46a2cd1	287	int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
dff63da9	288	struct amdgpu_device adev, struct kgd_mem mem, void *drm_priv,
d4ec4bdc	289	uint64_t *size);
4d30a83c CK	290	int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
4d30a83c CK	291	struct kgd_mem mem, void drm_priv);
a46a2cd1	292	int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
dff63da9	293	struct amdgpu_device adev, struct kgd_mem mem, void *drm_priv);
a46a2cd1	294	int amdgpu_amdkfd_gpuvm_sync_memory(
dff63da9	295	struct amdgpu_device adev, struct kgd_mem mem, bool intr);
4e2d1044 FK	296	int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
	297	void *kptr, uint64_t size);
	298	void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
68df0f19	299
e77a541f GS	300	int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device adev, struct amdgpu_bo bo);
e77a541f GS	301
a46a2cd1 FK	302	int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
a46a2cd1 FK	303	struct dma_fence **ef);
dff63da9	304	int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
b97dfa27	305	struct kfd_vm_fault_info *info);
dff63da9	306	int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
1dde0ea9	307	struct dma_buf *dmabuf,
b40a6ab2	308	uint64_t va, void *drm_priv,
1dde0ea9 FK	309	struct kgd_mem *mem, uint64_t size,
1dde0ea9 FK	310	uint64_t *mmap_offset);
fd234e75 FK	311	int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
fd234e75 FK	312	struct dma_buf **dmabuf);
dff63da9	313	int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
fd7d08ba	314	struct tile_config *config);
b6485bed TZ	315	void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
b6485bed TZ	316	bool reset);
5ccbb057	317	bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device adev, struct kgd_mem mem);
011bbb03 RB	318	void amdgpu_amdkfd_block_mmu_notifications(void *p);
011bbb03 RB	319	int amdgpu_amdkfd_criu_resume(void *p);
6475ae2b	320	bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
f9af3c16 AS	321	int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
	322	uint64_t size, u32 alloc_flag);
	323	void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
	324	uint64_t size, u32 alloc_flag);
011bbb03	325
cd63989e LY	326	#if IS_ENABLED(CONFIG_HSA_AMD)
	327	void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
	328	void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
	329	struct amdgpu_vm *vm);
f441dd33 RE	330
	331	/**
	332	* @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
	333	*
	334	* Allows KFD to release its resources associated with the GEM object.
	335	*/
5702d052	336	void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
c46ebb6a	337	void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
cd63989e LY	338	#else
	339	static inline
	340	void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
	341	{
	342	}
fd7d08ba	343
cd63989e LY	344	static inline
	345	void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
	346	struct amdgpu_vm *vm)
	347	{
	348	}
	349
	350	static inline
5702d052	351	void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
cd63989e LY	352	{
	353	}
	354	#endif
2d3d25b6	355	/* KGD2KFD callbacks */
c7f21978	356	int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
cd63989e LY	357	int kgd2kfd_resume_mm(struct mm_struct *mm);
	358	int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
	359	struct dma_fence *fence);
	360	#if IS_ENABLED(CONFIG_HSA_AMD)
308176d6	361	int kgd2kfd_init(void);
2d3d25b6	362	void kgd2kfd_exit(void);
b5d1d755	363	struct kfd_dev kgd2kfd_probe(struct amdgpu_device adev, bool vf);
2d3d25b6 AL	364	bool kgd2kfd_device_init(struct kfd_dev *kfd,
	365	const struct kgd2kfd_shared_resources *gpu_resources);
	366	void kgd2kfd_device_exit(struct kfd_dev *kfd);
9593f4d6	367	void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
fefc01f0	368	int kgd2kfd_resume_iommu(struct kfd_dev *kfd);
9593f4d6	369	int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
2d3d25b6 AL	370	int kgd2kfd_pre_reset(struct kfd_dev *kfd);
	371	int kgd2kfd_post_reset(struct kfd_dev *kfd);
	372	void kgd2kfd_interrupt(struct kfd_dev kfd, const void ih_ring_entry);
9b54d201	373	void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
410e302e	374	void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
cd63989e LY	375	#else
	376	static inline int kgd2kfd_init(void)
	377	{
	378	return -ENOENT;
	379	}
2d3d25b6	380
cd63989e LY	381	static inline void kgd2kfd_exit(void)
	382	{
	383	}
	384
	385	static inline
b5d1d755	386	struct kfd_dev kgd2kfd_probe(struct amdgpu_device adev, bool vf)
cd63989e LY	387	{
	388	return NULL;
	389	}
	390
	391	static inline
d69a3b76	392	bool kgd2kfd_device_init(struct kfd_dev *kfd,
cd63989e LY	393	const struct kgd2kfd_shared_resources *gpu_resources)
	394	{
	395	return false;
	396	}
	397
	398	static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
	399	{
	400	}
	401
	402	static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
	403	{
	404	}
	405
fefc01f0 JZ	406	static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd)
	407	{
	408	return 0;
	409	}
	410
cd63989e LY	411	static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
	412	{
	413	return 0;
	414	}
	415
	416	static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
	417	{
	418	return 0;
	419	}
	420
	421	static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
	422	{
	423	return 0;
	424	}
	425
	426	static inline
	427	void kgd2kfd_interrupt(struct kfd_dev kfd, const void ih_ring_entry)
	428	{
	429	}
	430
	431	static inline
	432	void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
	433	{
	434	}
	435
	436	static inline
410e302e	437	void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
cd63989e LY	438	{
	439	}
	440	#endif
130e0371	441	#endif /* AMDGPU_AMDKFD_H_INCLUDED */