[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */

#ifndef AMDGPU_AMDKFD_H_INCLUDED
#define AMDGPU_AMDKFD_H_INCLUDED

#include <linux/list.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/kthread.h>
#include <linux/workqueue.h>
#include <linux/mmu_notifier.h>
#include <linux/memremap.h>
#include <kgd_kfd_interface.h>
#include <drm/drm_client.h>
#include "amdgpu_sync.h"
#include "amdgpu_vm.h"
#include "amdgpu_xcp.h"

extern uint64_t amdgpu_amdkfd_total_mem_size;

enum TLB_FLUSH_TYPE {
	TLB_FLUSH_LEGACY = 0,
	TLB_FLUSH_LIGHTWEIGHT,
	TLB_FLUSH_HEAVYWEIGHT
};

struct amdgpu_device;

enum kfd_mem_attachment_type {
	KFD_MEM_ATT_SHARED,	/* Share kgd_mem->bo or another attachment's */
	KFD_MEM_ATT_USERPTR,	/* SG bo to DMA map pages from a userptr bo */
	KFD_MEM_ATT_DMABUF,	/* DMAbuf to DMA map TTM BOs */
	KFD_MEM_ATT_SG		/* Tag to DMA map SG BOs */
};

struct kfd_mem_attachment {
	struct list_head list;
	enum kfd_mem_attachment_type type;
	bool is_mapped;
	struct amdgpu_bo_va *bo_va;
	struct amdgpu_device *adev;
	uint64_t va;
	uint64_t pte_flags;
};

struct kgd_mem {
	struct mutex lock;
	struct amdgpu_bo *bo;
	struct dma_buf *dmabuf;
	struct hmm_range *range;
	struct list_head attachments;
	/* protected by amdkfd_process_info.lock */
	struct list_head validate_list;
	uint32_t domain;
	unsigned int mapped_to_gpu_memory;
	uint64_t va;

	uint32_t alloc_flags;

	uint32_t invalid;
	struct amdkfd_process_info *process_info;

	struct amdgpu_sync sync;

	uint32_t gem_handle;
	bool aql_queue;
	bool is_imported;
};

/* KFD Memory Eviction */
struct amdgpu_amdkfd_fence {
	struct dma_fence base;
	struct mm_struct *mm;
	spinlock_t lock;
	char timeline_name[TASK_COMM_LEN];
	struct svm_range_bo *svm_bo;
};

struct amdgpu_kfd_dev {
	struct kfd_dev *dev;
	int64_t vram_used[MAX_XCP];
	uint64_t vram_used_aligned[MAX_XCP];
	bool init_complete;
	struct work_struct reset_work;

	/* HMM page migration MEMORY_DEVICE_PRIVATE mapping */
	struct dev_pagemap pgmap;

	/* Client for KFD BO GEM handle allocations */
	struct drm_client_dev client;
};

enum kgd_engine_type {
	KGD_ENGINE_PFP = 1,
	KGD_ENGINE_ME,
	KGD_ENGINE_CE,
	KGD_ENGINE_MEC1,
	KGD_ENGINE_MEC2,
	KGD_ENGINE_RLC,
	KGD_ENGINE_SDMA1,
	KGD_ENGINE_SDMA2,
	KGD_ENGINE_MAX
};


struct amdkfd_process_info {
	/* List head of all VMs that belong to a KFD process */
	struct list_head vm_list_head;
	/* List head for all KFD BOs that belong to a KFD process. */
	struct list_head kfd_bo_list;
	/* List of userptr BOs that are valid or invalid */
	struct list_head userptr_valid_list;
	struct list_head userptr_inval_list;
	/* Lock to protect kfd_bo_list */
	struct mutex lock;

	/* Number of VMs */
	unsigned int n_vms;
	/* Eviction Fence */
	struct amdgpu_amdkfd_fence *eviction_fence;

	/* MMU-notifier related fields */
	struct mutex notifier_lock;
	uint32_t evicted_bos;
	struct delayed_work restore_userptr_work;
	struct pid *pid;
	bool block_mmu_notifications;
};

int amdgpu_amdkfd_init(void);
void amdgpu_amdkfd_fini(void);

void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
			const void *ih_ring_entry);
void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev);
void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev);
int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
				enum kgd_engine_type engine,
				uint32_t vmid, uint64_t gpu_addr,
				uint32_t *ib_cmd, uint32_t ib_len);
void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);

int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);

int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);

void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);

int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
					int queue_bit);

struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
				struct mm_struct *mm,
				struct svm_range_bo *svm_bo);
#if defined(CONFIG_DEBUG_FS)
int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
#endif
#if IS_ENABLED(CONFIG_HSA_AMD)
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
				unsigned long cur_seq, struct kgd_mem *mem);
#else
static inline
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
{
	return false;
}

static inline
struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
{
	return NULL;
}

static inline
int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
{
	return 0;
}

static inline
int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
				unsigned long cur_seq, struct kgd_mem *mem)
{
	return 0;
}
#endif
/* Shared API */
int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
				void **mem_obj, uint64_t *gpu_addr,
				void **cpu_ptr, bool mqd_gfx9);
void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj);
int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
				void **mem_obj);
void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
				      enum kgd_engine_type type);
void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
				      struct kfd_local_mem_info *mem_info,
				      struct amdgpu_xcp *xcp);
uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);

uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
				  struct amdgpu_device **dmabuf_adev,
				  uint64_t *bo_size, void *metadata_buffer,
				  size_t buffer_size, uint32_t *metadata_size,
				  uint32_t *flags, int8_t *xcp_id);
uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
					  struct amdgpu_device *src);
int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
					    struct amdgpu_device *src,
					    bool is_min);
int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
					uint32_t *payload);
int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
				u32 inst);

/* Read user wptr from a specified user address space with page fault
 * disabled. The memory must be pinned and mapped to the hardware when
 * this is called in hqd_load functions, so it should never fault in
 * the first place. This resolves a circular lock dependency involving
 * four locks, including the DQM lock and mmap_lock.
 */
#define read_user_wptr(mmptr, wptr, dst)				\
	({								\
		bool valid = false;					\
		if ((mmptr) && (wptr)) {				\
			pagefault_disable();				\
			if ((mmptr) == current->mm) {			\
				valid = !get_user((dst), (wptr));	\
			} else if (current->flags & PF_KTHREAD) {	\
				kthread_use_mm(mmptr);			\
				valid = !get_user((dst), (wptr));	\
				kthread_unuse_mm(mmptr);		\
			}						\
			pagefault_enable();				\
		}							\
		valid;							\
	})

/* GPUVM API */
#define drm_priv_to_vm(drm_priv)					\
	(&((struct amdgpu_fpriv *)					\
		((struct drm_file *)(drm_priv))->driver_priv)->vm)

int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
				     struct amdgpu_vm *avm, u32 pasid);
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
					struct amdgpu_vm *avm,
					void **process_info,
					struct dma_fence **ef);
void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
					void *drm_priv);
uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
					uint8_t xcp_id);
int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
		struct amdgpu_device *adev, uint64_t va, uint64_t size,
		void *drm_priv, struct kgd_mem **mem,
		uint64_t *offset, uint32_t flags, bool criu_resume);
int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
		uint64_t *size);
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
					  struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_sync_memory(
		struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
					     void **kptr, uint64_t *size);
void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);

int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo);

int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
					    struct dma_fence **ef);
int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
					      struct kfd_vm_fault_info *info);
int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
				      struct dma_buf *dmabuf,
				      uint64_t va, void *drm_priv,
				      struct kgd_mem **mem, uint64_t *size,
				      uint64_t *mmap_offset);
int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
				      struct dma_buf **dmabuf);
void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);
int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
				struct tile_config *config);
void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
				bool reset);
bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);
void amdgpu_amdkfd_block_mmu_notifications(void *p);
int amdgpu_amdkfd_criu_resume(void *p);
bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
		uint64_t size, u32 alloc_flag, int8_t xcp_id);
void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
		uint64_t size, u32 alloc_flag, int8_t xcp_id);

u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id);

#define KFD_XCP_MEM_ID(adev, xcp_id) \
		((adev)->xcp_mgr && (xcp_id) >= 0 ?\
		(adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1)

#define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id))


#if IS_ENABLED(CONFIG_HSA_AMD)
void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
				struct amdgpu_vm *vm);

/**
 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
 *
 * Allows KFD to release its resources associated with the GEM object.
 */
void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
#else
static inline
void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
{
}

static inline
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
					struct amdgpu_vm *vm)
{
}

static inline
void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
{
}
#endif

#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
int kgd2kfd_init_zone_device(struct amdgpu_device *adev);
#else
static inline
int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
{
	return 0;
}
#endif

/* KGD2KFD callbacks */
int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
int kgd2kfd_resume_mm(struct mm_struct *mm);
int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
						struct dma_fence *fence);
#if IS_ENABLED(CONFIG_HSA_AMD)
int kgd2kfd_init(void);
void kgd2kfd_exit(void);
struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
bool kgd2kfd_device_init(struct kfd_dev *kfd,
			 const struct kgd2kfd_shared_resources *gpu_resources);
void kgd2kfd_device_exit(struct kfd_dev *kfd);
void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
int kgd2kfd_pre_reset(struct kfd_dev *kfd);
int kgd2kfd_post_reset(struct kfd_dev *kfd);
void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
int kgd2kfd_check_and_lock_kfd(void);
void kgd2kfd_unlock_kfd(void);
#else
static inline int kgd2kfd_init(void)
{
	return -ENOENT;
}

static inline void kgd2kfd_exit(void)
{
}

static inline
struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
{
	return NULL;
}

static inline
bool kgd2kfd_device_init(struct kfd_dev *kfd,
				const struct kgd2kfd_shared_resources *gpu_resources)
{
	return false;
}

static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
{
}

static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
{
}

static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
{
	return 0;
}

static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
{
	return 0;
}

static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
{
	return 0;
}

static inline
void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
{
}

static inline
void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
{
}

static inline
void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
{
}

static inline int kgd2kfd_check_and_lock_kfd(void)
{
	return 0;
}

static inline void kgd2kfd_unlock_kfd(void)
{
}
#endif
#endif /* AMDGPU_AMDKFD_H_INCLUDED */
Commit	Line	Data
130e0371 OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
	24
	25	#ifndef AMDGPU_AMDKFD_H_INCLUDED
	26	#define AMDGPU_AMDKFD_H_INCLUDED
	27
8abc1eb2	28	#include <linux/list.h>
130e0371	29	#include <linux/types.h>
7420f482	30	#include <linux/mm.h>
9bf5b9eb	31	#include <linux/kthread.h>
5ae0283e	32	#include <linux/workqueue.h>
f95f51a4	33	#include <linux/mmu_notifier.h>
610dab11	34	#include <linux/memremap.h>
130e0371	35	#include <kgd_kfd_interface.h>
18192001	36	#include <drm/drm_client.h>
a46a2cd1 FK	37	#include "amdgpu_sync.h"
a46a2cd1 FK	38	#include "amdgpu_vm.h"
1c77527a	39	#include "amdgpu_xcp.h"
130e0371	40
611736d8	41	extern uint64_t amdgpu_amdkfd_total_mem_size;
d8d019cc	42
765385ec PY	43	enum TLB_FLUSH_TYPE {
	44	TLB_FLUSH_LEGACY = 0,
	45	TLB_FLUSH_LIGHTWEIGHT,
	46	TLB_FLUSH_HEAVYWEIGHT
	47	};
	48
130e0371 OG	49	struct amdgpu_device;
130e0371 OG	50
264fb4d3 FK	51	enum kfd_mem_attachment_type {
	52	KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
	53	KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
5ac3c3e4	54	KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
08a2fd23	55	KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */
264fb4d3 FK	56	};
264fb4d3 FK	57
c780b2ee FK	58	struct kfd_mem_attachment {
c780b2ee FK	59	struct list_head list;
264fb4d3	60	enum kfd_mem_attachment_type type;
a46a2cd1	61	bool is_mapped;
a46a2cd1	62	struct amdgpu_bo_va *bo_va;
c780b2ee	63	struct amdgpu_device *adev;
a46a2cd1 FK	64	uint64_t va;
	65	uint64_t pte_flags;
	66	};
	67
130e0371	68	struct kgd_mem {
a46a2cd1	69	struct mutex lock;
130e0371	70	struct amdgpu_bo *bo;
5ac3c3e4	71	struct dma_buf *dmabuf;
f95f51a4	72	struct hmm_range *range;
c780b2ee	73	struct list_head attachments;
a46a2cd1	74	/* protected by amdkfd_process_info.lock */
8abc1eb2	75	struct list_head validate_list;
a46a2cd1 FK	76	uint32_t domain;
	77	unsigned int mapped_to_gpu_memory;
	78	uint64_t va;
	79
d0ba51b1	80	uint32_t alloc_flags;
a46a2cd1	81
f95f51a4	82	uint32_t invalid;
a46a2cd1 FK	83	struct amdkfd_process_info *process_info;
	84
	85	struct amdgpu_sync sync;
	86
18192001	87	uint32_t gem_handle;
a46a2cd1	88	bool aql_queue;
d4566dee	89	bool is_imported;
130e0371 OG	90	};
130e0371 OG	91
d8d019cc FK	92	/* KFD Memory Eviction */
	93	struct amdgpu_amdkfd_fence {
	94	struct dma_fence base;
	95	struct mm_struct *mm;
	96	spinlock_t lock;
	97	char timeline_name[TASK_COMM_LEN];
eb2cec55	98	struct svm_range_bo *svm_bo;
d8d019cc FK	99	};
d8d019cc FK	100
611736d8 FK	101	struct amdgpu_kfd_dev {
611736d8 FK	102	struct kfd_dev *dev;
1c77527a MJ	103	int64_t vram_used[MAX_XCP];
1c77527a MJ	104	uint64_t vram_used_aligned[MAX_XCP];
8e2712e7	105	bool init_complete;
b5fd0cf3	106	struct work_struct reset_work;
610dab11 PY	107
	108	/* HMM page migration MEMORY_DEVICE_PRIVATE mapping */
	109	struct dev_pagemap pgmap;
18192001 FK	110
	111	/* Client for KFD BO GEM handle allocations */
	112	struct drm_client_dev client;
611736d8 FK	113	};
611736d8 FK	114
0da8b10e AL	115	enum kgd_engine_type {
	116	KGD_ENGINE_PFP = 1,
	117	KGD_ENGINE_ME,
	118	KGD_ENGINE_CE,
	119	KGD_ENGINE_MEC1,
	120	KGD_ENGINE_MEC2,
	121	KGD_ENGINE_RLC,
	122	KGD_ENGINE_SDMA1,
	123	KGD_ENGINE_SDMA2,
	124	KGD_ENGINE_MAX
	125	};
	126
d8d019cc	127
a46a2cd1 FK	128	struct amdkfd_process_info {
	129	/* List head of all VMs that belong to a KFD process */
	130	struct list_head vm_list_head;
	131	/* List head for all KFD BOs that belong to a KFD process. */
	132	struct list_head kfd_bo_list;
5ae0283e FK	133	/* List of userptr BOs that are valid or invalid */
	134	struct list_head userptr_valid_list;
	135	struct list_head userptr_inval_list;
a46a2cd1 FK	136	/* Lock to protect kfd_bo_list */
	137	struct mutex lock;
	138
	139	/* Number of VMs */
	140	unsigned int n_vms;
	141	/* Eviction Fence */
	142	struct amdgpu_amdkfd_fence *eviction_fence;
5ae0283e FK	143
5ae0283e FK	144	/* MMU-notifier related fields */
f95f51a4 FK	145	struct mutex notifier_lock;
f95f51a4 FK	146	uint32_t evicted_bos;
5ae0283e FK	147	struct delayed_work restore_userptr_work;
5ae0283e FK	148	struct pid *pid;
011bbb03	149	bool block_mmu_notifications;
a46a2cd1 FK	150	};
a46a2cd1 FK	151
efb1c658	152	int amdgpu_amdkfd_init(void);
130e0371 OG	153	void amdgpu_amdkfd_fini(void);
130e0371 OG	154
9593f4d6 RB	155	void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
9593f4d6 RB	156	int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
dc102c43	157	void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
130e0371	158	const void *ih_ring_entry);
dc102c43 AR	159	void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
dc102c43 AR	160	void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
e9669fb7	161	void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
0c7315e7 MJ	162	int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev);
0c7315e7 MJ	163	void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev);
6bfc7c7e GS	164	int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
6bfc7c7e GS	165	enum kgd_engine_type engine,
4c660c8f FK	166	uint32_t vmid, uint64_t gpu_addr,
4c660c8f FK	167	uint32_t *ib_cmd, uint32_t ib_len);
6bfc7c7e GS	168	void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
6bfc7c7e GS	169	bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
4c660c8f	170
155494db FK	171	bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
155494db FK	172
5c6dd71e SL	173	int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
	174
	175	int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
	176
6bfc7c7e	177	void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);
24da5a9c	178
d09f85d5 YZ	179	int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
	180	int queue_bit);
	181
cd63989e	182	struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
eb2cec55 AS	183	struct mm_struct *mm,
eb2cec55 AS	184	struct svm_range_bo *svm_bo);
3d2af401 AS	185	#if defined(CONFIG_DEBUG_FS)
	186	int kfd_debugfs_kfd_mem_limits(struct seq_file m, void data);
	187	#endif
cd63989e LY	188	#if IS_ENABLED(CONFIG_HSA_AMD)
	189	bool amdkfd_fence_check_mm(struct dma_fence f, struct mm_struct mm);
	190	struct amdgpu_amdkfd_fence to_amdgpu_amdkfd_fence(struct dma_fence f);
	191	int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
f95f51a4 FK	192	int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
f95f51a4 FK	193	unsigned long cur_seq, struct kgd_mem *mem);
cd63989e LY	194	#else
	195	static inline
	196	bool amdkfd_fence_check_mm(struct dma_fence f, struct mm_struct mm)
	197	{
	198	return false;
	199	}
	200
	201	static inline
	202	struct amdgpu_amdkfd_fence to_amdgpu_amdkfd_fence(struct dma_fence f)
	203	{
	204	return NULL;
	205	}
	206
	207	static inline
	208	int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
	209	{
	210	return 0;
	211	}
	212
	213	static inline
f95f51a4 FK	214	int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
f95f51a4 FK	215	unsigned long cur_seq, struct kgd_mem *mem)
cd63989e LY	216	{
	217	return 0;
	218	}
	219	#endif
130e0371	220	/* Shared API */
6bfc7c7e	221	int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
7cd52c91 AL	222	void *mem_obj, uint64_t gpu_addr,
7cd52c91 AL	223	void **cpu_ptr, bool mqd_gfx9);
6bfc7c7e GS	224	void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device adev, void mem_obj);
	225	int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
	226	void **mem_obj);
	227	void amdgpu_amdkfd_free_gws(struct amdgpu_device adev, void mem_obj);
71efab6a OZ	228	int amdgpu_amdkfd_add_gws_to_process(void info, void gws, struct kgd_mem **mem);
71efab6a OZ	229	int amdgpu_amdkfd_remove_gws_from_process(void info, void mem);
574c4183	230	uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
0da8b10e	231	enum kgd_engine_type type);
574c4183	232	void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
315e29ec	233	struct kfd_local_mem_info *mem_info,
9a3ce1a7	234	struct amdgpu_xcp *xcp);
574c4183	235	uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
7cd52c91	236
574c4183	237	uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
574c4183 GS	238	int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
574c4183 GS	239	struct amdgpu_device **dmabuf_adev,
1dde0ea9 FK	240	uint64_t bo_size, void metadata_buffer,
1dde0ea9 FK	241	size_t buffer_size, uint32_t *metadata_size,
2fa9ff25	242	uint32_t flags, int8_t xcp_id);
574c4183 GS	243	uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
	244	struct amdgpu_device *src);
	245	int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
	246	struct amdgpu_device *src,
	247	bool is_min);
	248	int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
12fb1ad7 JK	249	int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
12fb1ad7 JK	250	uint32_t *payload);
9041b53a MJ	251	int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
9041b53a MJ	252	u32 inst);
130e0371	253
cd05c865 FK	254	/* Read user wptr from a specified user address space with page fault
	255	* disabled. The memory must be pinned and mapped to the hardware when
	256	* this is called in hqd_load functions, so it should never fault in
	257	* the first place. This resolves a circular lock dependency involving
c1e8d7c6	258	* four locks, including the DQM lock and mmap_lock.
cd05c865	259	*/
70539bd7 FK	260	#define read_user_wptr(mmptr, wptr, dst) \
	261	({ \
	262	bool valid = false; \
	263	if ((mmptr) && (wptr)) { \
cd05c865	264	pagefault_disable(); \
70539bd7 FK	265	if ((mmptr) == current->mm) { \
70539bd7 FK	266	valid = !get_user((dst), (wptr)); \
8449d150	267	} else if (current->flags & PF_KTHREAD) { \
f5678e7f	268	kthread_use_mm(mmptr); \
70539bd7	269	valid = !get_user((dst), (wptr)); \
f5678e7f	270	kthread_unuse_mm(mmptr); \
70539bd7	271	} \
cd05c865	272	pagefault_enable(); \
70539bd7 FK	273	} \
	274	valid; \
	275	})
	276
a46a2cd1	277	/* GPUVM API */
f80fe9d3 FK	278	#define drm_priv_to_vm(drm_priv) \
	279	(&((struct amdgpu_fpriv *) \
	280	((struct drm_file *)(drm_priv))->driver_priv)->vm)
	281
41d82649	282	int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
23b02b0e	283	struct amdgpu_vm *avm, u32 pasid);
dff63da9	284	int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
23b02b0e	285	struct amdgpu_vm *avm,
b40a6ab2	286	void **process_info,
fcdfa432	287	struct dma_fence **ef);
dff63da9 GS	288	void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
dff63da9 GS	289	void *drm_priv);
b40a6ab2	290	uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
1c77527a MJ	291	size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1c77527a MJ	292	uint8_t xcp_id);
a46a2cd1	293	int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
dff63da9	294	struct amdgpu_device *adev, uint64_t va, uint64_t size,
b40a6ab2	295	void drm_priv, struct kgd_mem *mem,
011bbb03	296	uint64_t *offset, uint32_t flags, bool criu_resume);
a46a2cd1	297	int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
dff63da9	298	struct amdgpu_device adev, struct kgd_mem mem, void *drm_priv,
d4ec4bdc	299	uint64_t *size);
4d30a83c CK	300	int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
4d30a83c CK	301	struct kgd_mem mem, void drm_priv);
a46a2cd1	302	int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
dff63da9	303	struct amdgpu_device adev, struct kgd_mem mem, void *drm_priv);
101b8104	304	void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem mem, void drm_priv);
a46a2cd1	305	int amdgpu_amdkfd_gpuvm_sync_memory(
dff63da9	306	struct amdgpu_device adev, struct kgd_mem mem, bool intr);
4e2d1044 FK	307	int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
	308	void *kptr, uint64_t size);
	309	void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
68df0f19	310
e77a541f GS	311	int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device adev, struct amdgpu_bo bo);
e77a541f GS	312
a46a2cd1 FK	313	int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
a46a2cd1 FK	314	struct dma_fence **ef);
dff63da9	315	int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
b97dfa27	316	struct kfd_vm_fault_info *info);
dff63da9	317	int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
1dde0ea9	318	struct dma_buf *dmabuf,
b40a6ab2	319	uint64_t va, void *drm_priv,
1dde0ea9 FK	320	struct kgd_mem *mem, uint64_t size,
1dde0ea9 FK	321	uint64_t *mmap_offset);
fd234e75 FK	322	int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
fd234e75 FK	323	struct dma_buf **dmabuf);
a70a93fa	324	void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);
dff63da9	325	int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
fd7d08ba	326	struct tile_config *config);
b6485bed TZ	327	void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
b6485bed TZ	328	bool reset);
5ccbb057	329	bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device adev, struct kgd_mem mem);
011bbb03 RB	330	void amdgpu_amdkfd_block_mmu_notifications(void *p);
011bbb03 RB	331	int amdgpu_amdkfd_criu_resume(void *p);
6475ae2b	332	bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
f9af3c16	333	int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
1c77527a	334	uint64_t size, u32 alloc_flag, int8_t xcp_id);
f9af3c16	335	void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
1c77527a	336	uint64_t size, u32 alloc_flag, int8_t xcp_id);
011bbb03	337
45b3a914 AD	338	u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id);
45b3a914 AD	339
3ebfd221 PY	340	#define KFD_XCP_MEM_ID(adev, xcp_id) \
	341	((adev)->xcp_mgr && (xcp_id) >= 0 ?\
	342	(adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1)
	343
45b3a914 AD	344	#define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id))
45b3a914 AD	345
4c6ce75f	346
cd63989e LY	347	#if IS_ENABLED(CONFIG_HSA_AMD)
	348	void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
	349	void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
	350	struct amdgpu_vm *vm);
f441dd33 RE	351
	352	/**
	353	* @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
	354	*
	355	* Allows KFD to release its resources associated with the GEM object.
	356	*/
5702d052	357	void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
c46ebb6a	358	void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
cd63989e LY	359	#else
	360	static inline
	361	void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
	362	{
	363	}
fd7d08ba	364
cd63989e LY	365	static inline
	366	void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
	367	struct amdgpu_vm *vm)
	368	{
	369	}
	370
	371	static inline
5702d052	372	void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
cd63989e LY	373	{
	374	}
	375	#endif
84b4dd3f PY	376
	377	#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
	378	int kgd2kfd_init_zone_device(struct amdgpu_device *adev);
	379	#else
	380	static inline
	381	int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
	382	{
	383	return 0;
	384	}
	385	#endif
	386
2d3d25b6	387	/* KGD2KFD callbacks */
c7f21978	388	int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
cd63989e LY	389	int kgd2kfd_resume_mm(struct mm_struct *mm);
	390	int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
	391	struct dma_fence *fence);
	392	#if IS_ENABLED(CONFIG_HSA_AMD)
308176d6	393	int kgd2kfd_init(void);
2d3d25b6	394	void kgd2kfd_exit(void);
b5d1d755	395	struct kfd_dev kgd2kfd_probe(struct amdgpu_device adev, bool vf);
2d3d25b6 AL	396	bool kgd2kfd_device_init(struct kfd_dev *kfd,
	397	const struct kgd2kfd_shared_resources *gpu_resources);
	398	void kgd2kfd_device_exit(struct kfd_dev *kfd);
9593f4d6 RB	399	void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
9593f4d6 RB	400	int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
2d3d25b6 AL	401	int kgd2kfd_pre_reset(struct kfd_dev *kfd);
	402	int kgd2kfd_post_reset(struct kfd_dev *kfd);
	403	void kgd2kfd_interrupt(struct kfd_dev kfd, const void ih_ring_entry);
9b54d201	404	void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
410e302e	405	void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
0c7315e7 MJ	406	int kgd2kfd_check_and_lock_kfd(void);
0c7315e7 MJ	407	void kgd2kfd_unlock_kfd(void);
cd63989e LY	408	#else
	409	static inline int kgd2kfd_init(void)
	410	{
	411	return -ENOENT;
	412	}
2d3d25b6	413
cd63989e LY	414	static inline void kgd2kfd_exit(void)
	415	{
	416	}
	417
	418	static inline
b5d1d755	419	struct kfd_dev kgd2kfd_probe(struct amdgpu_device adev, bool vf)
cd63989e LY	420	{
	421	return NULL;
	422	}
	423
	424	static inline
d69a3b76	425	bool kgd2kfd_device_init(struct kfd_dev *kfd,
cd63989e LY	426	const struct kgd2kfd_shared_resources *gpu_resources)
	427	{
	428	return false;
	429	}
	430
	431	static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
	432	{
	433	}
	434
	435	static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
	436	{
	437	}
	438
	439	static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
	440	{
	441	return 0;
	442	}
	443
	444	static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
	445	{
	446	return 0;
	447	}
	448
	449	static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
	450	{
	451	return 0;
	452	}
	453
	454	static inline
	455	void kgd2kfd_interrupt(struct kfd_dev kfd, const void ih_ring_entry)
	456	{
	457	}
	458
	459	static inline
	460	void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
	461	{
	462	}
	463
	464	static inline
410e302e	465	void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
cd63989e LY	466	{
cd63989e LY	467	}
0c7315e7 MJ	468
	469	static inline int kgd2kfd_check_and_lock_kfd(void)
	470	{
	471	return 0;
	472	}
	473
	474	static inline void kgd2kfd_unlock_kfd(void)
	475	{
	476	}
cd63989e	477	#endif
130e0371	478	#endif /* AMDGPU_AMDKFD_H_INCLUDED */