[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include "amdgpu_amdkfd.h"
#include "amd_shared.h"
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_gfx.h"
#include <linux/module.h>

const struct kgd2kfd_calls *kgd2kfd;
bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);

static const unsigned int compute_vmid_bitmap = 0xFF00;

int amdgpu_amdkfd_init(void)
{
	int ret;

#if defined(CONFIG_HSA_AMD_MODULE)
	int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);

	kgd2kfd_init_p = symbol_request(kgd2kfd_init);

	if (kgd2kfd_init_p == NULL)
		return -ENOENT;

	ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
	if (ret) {
		symbol_put(kgd2kfd_init);
		kgd2kfd = NULL;
	}


#elif defined(CONFIG_HSA_AMD)

	ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
	if (ret)
		kgd2kfd = NULL;

#else
	kgd2kfd = NULL;
	ret = -ENOENT;
#endif

#if defined(CONFIG_HSA_AMD_MODULE) || defined(CONFIG_HSA_AMD)
	amdgpu_amdkfd_gpuvm_init_mem_limits();
#endif

	return ret;
}

void amdgpu_amdkfd_fini(void)
{
	if (kgd2kfd) {
		kgd2kfd->exit();
		symbol_put(kgd2kfd_init);
	}
}

void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
{
	const struct kfd2kgd_calls *kfd2kgd;

	if (!kgd2kfd)
		return;

	switch (adev->asic_type) {
#ifdef CONFIG_DRM_AMDGPU_CIK
	case CHIP_KAVERI:
	case CHIP_HAWAII:
		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
		break;
#endif
	case CHIP_CARRIZO:
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_POLARIS10:
	case CHIP_POLARIS11:
		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
		break;
	case CHIP_VEGA10:
	case CHIP_RAVEN:
		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
		break;
	default:
		dev_info(adev->dev, "kfd not supported on this ASIC\n");
		return;
	}

	adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
				   adev->pdev, kfd2kgd);
}

/**
 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 *                                setup amdkfd
 *
 * @adev: amdgpu_device pointer
 * @aperture_base: output returning doorbell aperture base physical address
 * @aperture_size: output returning doorbell aperture size in bytes
 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 *
 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 * takes doorbells required for its own rings and reports the setup to amdkfd.
 * amdgpu reserved doorbells are at the start of the doorbell aperture.
 */
static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
					 phys_addr_t *aperture_base,
					 size_t *aperture_size,
					 size_t *start_offset)
{
	/*
	 * The first num_doorbells are used by amdgpu.
	 * amdkfd takes whatever's left in the aperture.
	 */
	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
		*aperture_base = adev->doorbell.base;
		*aperture_size = adev->doorbell.size;
		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
	} else {
		*aperture_base = 0;
		*aperture_size = 0;
		*start_offset = 0;
	}
}

void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
{
	int i;
	int last_valid_bit;
	if (adev->kfd) {
		struct kgd2kfd_shared_resources gpu_resources = {
			.compute_vmid_bitmap = compute_vmid_bitmap,
			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
			.gpuvm_size = min(adev->vm_manager.max_pfn
					  << AMDGPU_GPU_PAGE_SHIFT,
					  AMDGPU_VA_HOLE_START),
			.drm_render_minor = adev->ddev->render->index
		};

		/* this is going to have a few of the MSBs set that we need to
		 * clear */
		bitmap_complement(gpu_resources.queue_bitmap,
				  adev->gfx.mec.queue_bitmap,
				  KGD_MAX_QUEUES);

		/* remove the KIQ bit as well */
		if (adev->gfx.kiq.ring.ready)
			clear_bit(amdgpu_gfx_queue_to_bit(adev,
							  adev->gfx.kiq.ring.me - 1,
							  adev->gfx.kiq.ring.pipe,
							  adev->gfx.kiq.ring.queue),
				  gpu_resources.queue_bitmap);

		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
		 * nbits is not compile time constant */
		last_valid_bit = 1 /* only first MEC can have compute queues */
				* adev->gfx.mec.num_pipe_per_mec
				* adev->gfx.mec.num_queue_per_pipe;
		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
			clear_bit(i, gpu_resources.queue_bitmap);

		amdgpu_doorbell_get_kfd_info(adev,
				&gpu_resources.doorbell_physical_address,
				&gpu_resources.doorbell_aperture_size,
				&gpu_resources.doorbell_start_offset);
		if (adev->asic_type >= CHIP_VEGA10) {
			/* On SOC15 the BIF is involved in routing
			 * doorbells using the low 12 bits of the
			 * address. Communicate the assignments to
			 * KFD. KFD uses two doorbell pages per
			 * process in case of 64-bit doorbells so we
			 * can use each doorbell assignment twice.
			 */
			gpu_resources.sdma_doorbell[0][0] =
				AMDGPU_DOORBELL64_sDMA_ENGINE0;
			gpu_resources.sdma_doorbell[0][1] =
				AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
			gpu_resources.sdma_doorbell[1][0] =
				AMDGPU_DOORBELL64_sDMA_ENGINE1;
			gpu_resources.sdma_doorbell[1][1] =
				AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
			/* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
			 * SDMA, IH and VCN. So don't use them for the CP.
			 */
			gpu_resources.reserved_doorbell_mask = 0x1f0;
			gpu_resources.reserved_doorbell_val  = 0x0f0;
		}

		kgd2kfd->device_init(adev->kfd, &gpu_resources);
	}
}

void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
{
	if (adev->kfd) {
		kgd2kfd->device_exit(adev->kfd);
		adev->kfd = NULL;
	}
}

void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
		const void *ih_ring_entry)
{
	if (adev->kfd)
		kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
}

void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
{
	if (adev->kfd)
		kgd2kfd->suspend(adev->kfd);
}

int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
{
	int r = 0;

	if (adev->kfd)
		r = kgd2kfd->resume(adev->kfd);

	return r;
}

int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
{
	int r = 0;

	if (adev->kfd)
		r = kgd2kfd->pre_reset(adev->kfd);

	return r;
}

int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
{
	int r = 0;

	if (adev->kfd)
		r = kgd2kfd->post_reset(adev->kfd);

	return r;
}

void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	amdgpu_device_gpu_recover(adev, NULL, false);
}

int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
			void **mem_obj, uint64_t *gpu_addr,
			void **cpu_ptr, bool mqd_gfx9)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	struct amdgpu_bo *bo = NULL;
	struct amdgpu_bo_param bp;
	int r;
	void *cpu_ptr_tmp = NULL;

	memset(&bp, 0, sizeof(bp));
	bp.size = size;
	bp.byte_align = PAGE_SIZE;
	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
	bp.type = ttm_bo_type_kernel;
	bp.resv = NULL;

	if (mqd_gfx9)
		bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;

	r = amdgpu_bo_create(adev, &bp, &bo);
	if (r) {
		dev_err(adev->dev,
			"failed to allocate BO for amdkfd (%d)\n", r);
		return r;
	}

	/* map the buffer */
	r = amdgpu_bo_reserve(bo, true);
	if (r) {
		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
		goto allocate_mem_reserve_bo_failed;
	}

	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
	if (r) {
		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
		goto allocate_mem_pin_bo_failed;
	}

	r = amdgpu_ttm_alloc_gart(&bo->tbo);
	if (r) {
		dev_err(adev->dev, "%p bind failed\n", bo);
		goto allocate_mem_kmap_bo_failed;
	}

	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
	if (r) {
		dev_err(adev->dev,
			"(%d) failed to map bo to kernel for amdkfd\n", r);
		goto allocate_mem_kmap_bo_failed;
	}

	*mem_obj = bo;
	*gpu_addr = amdgpu_bo_gpu_offset(bo);
	*cpu_ptr = cpu_ptr_tmp;

	amdgpu_bo_unreserve(bo);

	return 0;

allocate_mem_kmap_bo_failed:
	amdgpu_bo_unpin(bo);
allocate_mem_pin_bo_failed:
	amdgpu_bo_unreserve(bo);
allocate_mem_reserve_bo_failed:
	amdgpu_bo_unref(&bo);

	return r;
}

void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
{
	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;

	amdgpu_bo_reserve(bo, true);
	amdgpu_bo_kunmap(bo);
	amdgpu_bo_unpin(bo);
	amdgpu_bo_unreserve(bo);
	amdgpu_bo_unref(&(bo));
}

void get_local_mem_info(struct kgd_dev *kgd,
			struct kfd_local_mem_info *mem_info)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
					     ~((1ULL << 32) - 1);
	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;

	memset(mem_info, 0, sizeof(*mem_info));
	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
		mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
		mem_info->local_mem_size_private = adev->gmc.real_vram_size -
				adev->gmc.visible_vram_size;
	} else {
		mem_info->local_mem_size_public = 0;
		mem_info->local_mem_size_private = adev->gmc.real_vram_size;
	}
	mem_info->vram_width = adev->gmc.vram_width;

	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
			&adev->gmc.aper_base, &aper_limit,
			mem_info->local_mem_size_public,
			mem_info->local_mem_size_private);

	if (amdgpu_sriov_vf(adev))
		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
	else if (adev->powerplay.pp_funcs)
		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
	else
		mem_info->mem_clk_max = 100;
}

uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	if (adev->gfx.funcs->get_gpu_clock_counter)
		return adev->gfx.funcs->get_gpu_clock_counter(adev);
	return 0;
}

uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	/* the sclk is in quantas of 10kHz */
	if (amdgpu_sriov_vf(adev))
		return adev->clock.default_sclk / 100;
	else if (adev->powerplay.pp_funcs)
		return amdgpu_dpm_get_sclk(adev, false) / 100;
	else
		return 100;
}

void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;

	memset(cu_info, 0, sizeof(*cu_info));
	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
		return;

	cu_info->cu_active_number = acu_info.number;
	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
	       sizeof(acu_info.bitmap));
	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
	cu_info->simd_per_cu = acu_info.simd_per_cu;
	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
	cu_info->wave_front_size = acu_info.wave_front_size;
	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
	cu_info->lds_size = acu_info.lds_size;
}

uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
}

int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
				uint32_t vmid, uint64_t gpu_addr,
				uint32_t *ib_cmd, uint32_t ib_len)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
	struct amdgpu_job *job;
	struct amdgpu_ib *ib;
	struct amdgpu_ring *ring;
	struct dma_fence *f = NULL;
	int ret;

	switch (engine) {
	case KGD_ENGINE_MEC1:
		ring = &adev->gfx.compute_ring[0];
		break;
	case KGD_ENGINE_SDMA1:
		ring = &adev->sdma.instance[0].ring;
		break;
	case KGD_ENGINE_SDMA2:
		ring = &adev->sdma.instance[1].ring;
		break;
	default:
		pr_err("Invalid engine in IB submission: %d\n", engine);
		ret = -EINVAL;
		goto err;
	}

	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
	if (ret)
		goto err;

	ib = &job->ibs[0];
	memset(ib, 0, sizeof(struct amdgpu_ib));

	ib->gpu_addr = gpu_addr;
	ib->ptr = ib_cmd;
	ib->length_dw = ib_len;
	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
	job->vmid = vmid;

	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
	if (ret) {
		DRM_ERROR("amdgpu: failed to schedule IB.\n");
		goto err_ib_sched;
	}

	ret = dma_fence_wait(f, false);

err_ib_sched:
	dma_fence_put(f);
	amdgpu_job_free(job);
err:
	return ret;
}

void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	amdgpu_dpm_switch_power_profile(adev,
					PP_SMC_POWER_PROFILE_COMPUTE, !idle);
}

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
{
	if (adev->kfd) {
		if ((1 << vmid) & compute_vmid_bitmap)
			return true;
	}

	return false;
}

#if !defined(CONFIG_HSA_AMD_MODULE) && !defined(CONFIG_HSA_AMD)
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
{
	return false;
}

void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
{
}

void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
					struct amdgpu_vm *vm)
{
}

struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
{
	return NULL;
}

int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
{
	return 0;
}

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
{
	return NULL;
}

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
{
	return NULL;
}

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
{
	return NULL;
}
#endif
Commit	Line	Data
130e0371 OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#include "amdgpu_amdkfd.h"
2f7d10b3	24	#include "amd_shared.h"
130e0371 OG	25	#include <drm/drmP.h>
130e0371 OG	26	#include "amdgpu.h"
2db0cdbe	27	#include "amdgpu_gfx.h"
130e0371 OG	28	#include <linux/module.h>
130e0371 OG	29
130e0371	30	const struct kgd2kfd_calls *kgd2kfd;
8eabaf54	31	bool (kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls*);
130e0371	32
155494db FK	33	static const unsigned int compute_vmid_bitmap = 0xFF00;
155494db FK	34
efb1c658	35	int amdgpu_amdkfd_init(void)
130e0371	36	{
efb1c658 OG	37	int ret;
efb1c658 OG	38
130e0371	39	#if defined(CONFIG_HSA_AMD_MODULE)
8eabaf54	40	int (kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls*);
130e0371 OG	41
	42	kgd2kfd_init_p = symbol_request(kgd2kfd_init);
	43
	44	if (kgd2kfd_init_p == NULL)
efb1c658 OG	45	return -ENOENT;
	46
	47	ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
	48	if (ret) {
	49	symbol_put(kgd2kfd_init);
	50	kgd2kfd = NULL;
	51	}
	52
fcdfa432	53
efb1c658	54	#elif defined(CONFIG_HSA_AMD)
fcdfa432	55
efb1c658 OG	56	ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
	57	if (ret)
	58	kgd2kfd = NULL;
	59
	60	#else
fcdfa432	61	kgd2kfd = NULL;
efb1c658	62	ret = -ENOENT;
130e0371	63	#endif
fcdfa432 OG	64
fcdfa432 OG	65	#if defined(CONFIG_HSA_AMD_MODULE) \|\| defined(CONFIG_HSA_AMD)
a46a2cd1	66	amdgpu_amdkfd_gpuvm_init_mem_limits();
fcdfa432	67	#endif
efb1c658 OG	68
efb1c658 OG	69	return ret;
130e0371 OG	70	}
130e0371 OG	71
5c33f214 FK	72	void amdgpu_amdkfd_fini(void)
	73	{
	74	if (kgd2kfd) {
	75	kgd2kfd->exit();
	76	symbol_put(kgd2kfd_init);
	77	}
	78	}
	79
	80	void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
130e0371	81	{
5c33f214 FK	82	const struct kfd2kgd_calls *kfd2kgd;
	83
	84	if (!kgd2kfd)
	85	return;
	86
dc102c43	87	switch (adev->asic_type) {
41548ef7	88	#ifdef CONFIG_DRM_AMDGPU_CIK
130e0371	89	case CHIP_KAVERI:
30d13424	90	case CHIP_HAWAII:
32c22e99 OG	91	kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
32c22e99 OG	92	break;
41548ef7	93	#endif
ff758a12	94	case CHIP_CARRIZO:
30d13424 FK	95	case CHIP_TONGA:
	96	case CHIP_FIJI:
	97	case CHIP_POLARIS10:
	98	case CHIP_POLARIS11:
ff758a12 BG	99	kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
ff758a12 BG	100	break;
d5a114a6 FK	101	case CHIP_VEGA10:
	102	case CHIP_RAVEN:
	103	kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
	104	break;
130e0371	105	default:
c3032fd9	106	dev_info(adev->dev, "kfd not supported on this ASIC\n");
5c33f214	107	return;
130e0371 OG	108	}
130e0371 OG	109
5c33f214 FK	110	adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
5c33f214 FK	111	adev->pdev, kfd2kgd);
130e0371 OG	112	}
130e0371 OG	113
22cb0164 AD	114	/**
	115	* amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
	116	* setup amdkfd
	117	*
	118	* @adev: amdgpu_device pointer
	119	* @aperture_base: output returning doorbell aperture base physical address
	120	* @aperture_size: output returning doorbell aperture size in bytes
	121	* @start_offset: output returning # of doorbell bytes reserved for amdgpu.
	122	*
	123	* amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
	124	* takes doorbells required for its own rings and reports the setup to amdkfd.
	125	* amdgpu reserved doorbells are at the start of the doorbell aperture.
	126	*/
	127	static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
	128	phys_addr_t *aperture_base,
	129	size_t *aperture_size,
	130	size_t *start_offset)
	131	{
	132	/*
	133	* The first num_doorbells are used by amdgpu.
	134	* amdkfd takes whatever's left in the aperture.
	135	*/
	136	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
	137	*aperture_base = adev->doorbell.base;
	138	*aperture_size = adev->doorbell.size;
	139	start_offset = adev->doorbell.num_doorbells sizeof(u32);
	140	} else {
	141	*aperture_base = 0;
	142	*aperture_size = 0;
	143	*start_offset = 0;
	144	}
	145	}
	146
dc102c43	147	void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
130e0371	148	{
d0b63bb3 AR	149	int i;
d0b63bb3 AR	150	int last_valid_bit;
dc102c43	151	if (adev->kfd) {
130e0371	152	struct kgd2kfd_shared_resources gpu_resources = {
155494db	153	.compute_vmid_bitmap = compute_vmid_bitmap,
d0b63bb3	154	.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
155494db FK	155	.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
	156	.gpuvm_size = min(adev->vm_manager.max_pfn
	157	<< AMDGPU_GPU_PAGE_SHIFT,
	158	AMDGPU_VA_HOLE_START),
	159	.drm_render_minor = adev->ddev->render->index
130e0371 OG	160	};
130e0371 OG	161
d0b63bb3 AR	162	/* this is going to have a few of the MSBs set that we need to
	163	* clear */
	164	bitmap_complement(gpu_resources.queue_bitmap,
	165	adev->gfx.mec.queue_bitmap,
	166	KGD_MAX_QUEUES);
	167
7b2124a5 AR	168	/* remove the KIQ bit as well */
7b2124a5 AR	169	if (adev->gfx.kiq.ring.ready)
2db0cdbe AD	170	clear_bit(amdgpu_gfx_queue_to_bit(adev,
	171	adev->gfx.kiq.ring.me - 1,
	172	adev->gfx.kiq.ring.pipe,
	173	adev->gfx.kiq.ring.queue),
7b2124a5 AR	174	gpu_resources.queue_bitmap);
7b2124a5 AR	175
d0b63bb3 AR	176	/* According to linux/bitmap.h we shouldn't use bitmap_clear if
d0b63bb3 AR	177	* nbits is not compile time constant */
3447d220	178	last_valid_bit = 1 /* only first MEC can have compute queues */
d0b63bb3 AR	179	* adev->gfx.mec.num_pipe_per_mec
	180	* adev->gfx.mec.num_queue_per_pipe;
	181	for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
	182	clear_bit(i, gpu_resources.queue_bitmap);
	183
dc102c43	184	amdgpu_doorbell_get_kfd_info(adev,
130e0371 OG	185	&gpu_resources.doorbell_physical_address,
	186	&gpu_resources.doorbell_aperture_size,
	187	&gpu_resources.doorbell_start_offset);
642a0e80 FK	188	if (adev->asic_type >= CHIP_VEGA10) {
	189	/* On SOC15 the BIF is involved in routing
	190	* doorbells using the low 12 bits of the
	191	* address. Communicate the assignments to
	192	* KFD. KFD uses two doorbell pages per
	193	* process in case of 64-bit doorbells so we
	194	* can use each doorbell assignment twice.
	195	*/
	196	gpu_resources.sdma_doorbell[0][0] =
	197	AMDGPU_DOORBELL64_sDMA_ENGINE0;
	198	gpu_resources.sdma_doorbell[0][1] =
	199	AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
	200	gpu_resources.sdma_doorbell[1][0] =
	201	AMDGPU_DOORBELL64_sDMA_ENGINE1;
	202	gpu_resources.sdma_doorbell[1][1] =
	203	AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
	204	/* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
	205	* SDMA, IH and VCN. So don't use them for the CP.
	206	*/
	207	gpu_resources.reserved_doorbell_mask = 0x1f0;
	208	gpu_resources.reserved_doorbell_val = 0x0f0;
	209	}
130e0371	210
dc102c43	211	kgd2kfd->device_init(adev->kfd, &gpu_resources);
130e0371 OG	212	}
	213	}
	214
dc102c43	215	void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
130e0371	216	{
dc102c43 AR	217	if (adev->kfd) {
	218	kgd2kfd->device_exit(adev->kfd);
	219	adev->kfd = NULL;
130e0371 OG	220	}
	221	}
	222
dc102c43	223	void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
130e0371 OG	224	const void *ih_ring_entry)
130e0371 OG	225	{
dc102c43 AR	226	if (adev->kfd)
dc102c43 AR	227	kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
130e0371 OG	228	}
130e0371 OG	229
dc102c43	230	void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
130e0371	231	{
dc102c43 AR	232	if (adev->kfd)
dc102c43 AR	233	kgd2kfd->suspend(adev->kfd);
130e0371 OG	234	}
130e0371 OG	235
dc102c43	236	int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
130e0371 OG	237	{
	238	int r = 0;
	239
dc102c43 AR	240	if (adev->kfd)
dc102c43 AR	241	r = kgd2kfd->resume(adev->kfd);
130e0371 OG	242
	243	return r;
	244	}
	245
5c6dd71e SL	246	int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
	247	{
	248	int r = 0;
	249
	250	if (adev->kfd)
	251	r = kgd2kfd->pre_reset(adev->kfd);
	252
	253	return r;
	254	}
	255
	256	int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
	257	{
	258	int r = 0;
	259
	260	if (adev->kfd)
	261	r = kgd2kfd->post_reset(adev->kfd);
	262
	263	return r;
	264	}
	265
24da5a9c SL	266	void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
	267	{
	268	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	269
	270	amdgpu_device_gpu_recover(adev, NULL, false);
	271	}
	272
130e0371 OG	273	int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
130e0371 OG	274	void *mem_obj, uint64_t gpu_addr,
15426dbb	275	void **cpu_ptr, bool mqd_gfx9)
130e0371	276	{
dc102c43	277	struct amdgpu_device adev = (struct amdgpu_device )kgd;
473fee47	278	struct amdgpu_bo *bo = NULL;
3216c6b7	279	struct amdgpu_bo_param bp;
130e0371	280	int r;
473fee47	281	void *cpu_ptr_tmp = NULL;
130e0371	282
3216c6b7 CZ	283	memset(&bp, 0, sizeof(bp));
	284	bp.size = size;
	285	bp.byte_align = PAGE_SIZE;
	286	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
	287	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
	288	bp.type = ttm_bo_type_kernel;
	289	bp.resv = NULL;
15426dbb YZ	290
	291	if (mqd_gfx9)
	292	bp.flags \|= AMDGPU_GEM_CREATE_MQD_GFX9;
	293
3216c6b7	294	r = amdgpu_bo_create(adev, &bp, &bo);
130e0371	295	if (r) {
dc102c43	296	dev_err(adev->dev,
130e0371 OG	297	"failed to allocate BO for amdkfd (%d)\n", r);
	298	return r;
	299	}
	300
	301	/* map the buffer */
473fee47	302	r = amdgpu_bo_reserve(bo, true);
130e0371	303	if (r) {
dc102c43	304	dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
130e0371 OG	305	goto allocate_mem_reserve_bo_failed;
	306	}
	307
7b7c6c81	308	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
130e0371	309	if (r) {
dc102c43	310	dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
130e0371 OG	311	goto allocate_mem_pin_bo_failed;
130e0371 OG	312	}
130e0371	313
bb812f1e JZ	314	r = amdgpu_ttm_alloc_gart(&bo->tbo);
	315	if (r) {
	316	dev_err(adev->dev, "%p bind failed\n", bo);
	317	goto allocate_mem_kmap_bo_failed;
	318	}
	319
473fee47	320	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
130e0371	321	if (r) {
dc102c43	322	dev_err(adev->dev,
130e0371 OG	323	"(%d) failed to map bo to kernel for amdkfd\n", r);
	324	goto allocate_mem_kmap_bo_failed;
	325	}
130e0371	326
473fee47	327	*mem_obj = bo;
7b7c6c81	328	*gpu_addr = amdgpu_bo_gpu_offset(bo);
473fee47 YZ	329	*cpu_ptr = cpu_ptr_tmp;
	330
	331	amdgpu_bo_unreserve(bo);
130e0371 OG	332
	333	return 0;
	334
	335	allocate_mem_kmap_bo_failed:
473fee47	336	amdgpu_bo_unpin(bo);
130e0371	337	allocate_mem_pin_bo_failed:
473fee47	338	amdgpu_bo_unreserve(bo);
130e0371	339	allocate_mem_reserve_bo_failed:
473fee47	340	amdgpu_bo_unref(&bo);
130e0371 OG	341
	342	return r;
	343	}
	344
	345	void free_gtt_mem(struct kgd_dev kgd, void mem_obj)
	346	{
473fee47 YZ	347	struct amdgpu_bo bo = (struct amdgpu_bo ) mem_obj;
	348
	349	amdgpu_bo_reserve(bo, true);
	350	amdgpu_bo_kunmap(bo);
	351	amdgpu_bo_unpin(bo);
	352	amdgpu_bo_unreserve(bo);
	353	amdgpu_bo_unref(&(bo));
130e0371 OG	354	}
130e0371 OG	355
30f1c042 HK	356	void get_local_mem_info(struct kgd_dev *kgd,
	357	struct kfd_local_mem_info *mem_info)
	358	{
	359	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	360	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
	361	~((1ULL << 32) - 1);
770d13b1	362	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
30f1c042 HK	363
30f1c042 HK	364	memset(mem_info, 0, sizeof(*mem_info));
770d13b1 CK	365	if (!(adev->gmc.aper_base & address_mask \|\| aper_limit & address_mask)) {
	366	mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
	367	mem_info->local_mem_size_private = adev->gmc.real_vram_size -
	368	adev->gmc.visible_vram_size;
30f1c042 HK	369	} else {
30f1c042 HK	370	mem_info->local_mem_size_public = 0;
770d13b1	371	mem_info->local_mem_size_private = adev->gmc.real_vram_size;
30f1c042	372	}
770d13b1	373	mem_info->vram_width = adev->gmc.vram_width;
30f1c042	374
fb8baefc	375	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
770d13b1	376	&adev->gmc.aper_base, &aper_limit,
30f1c042 HK	377	mem_info->local_mem_size_public,
	378	mem_info->local_mem_size_private);
	379
	380	if (amdgpu_sriov_vf(adev))
	381	mem_info->mem_clk_max = adev->clock.default_mclk / 100;
7ba01f9e	382	else if (adev->powerplay.pp_funcs)
30f1c042	383	mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
7ba01f9e SL	384	else
7ba01f9e SL	385	mem_info->mem_clk_max = 100;
30f1c042 HK	386	}
30f1c042 HK	387
130e0371 OG	388	uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
130e0371 OG	389	{
dc102c43	390	struct amdgpu_device adev = (struct amdgpu_device )kgd;
130e0371	391
dc102c43 AR	392	if (adev->gfx.funcs->get_gpu_clock_counter)
dc102c43 AR	393	return adev->gfx.funcs->get_gpu_clock_counter(adev);
130e0371 OG	394	return 0;
	395	}
	396
	397	uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
	398	{
dc102c43	399	struct amdgpu_device adev = (struct amdgpu_device )kgd;
130e0371	400
a9efcc19 FK	401	/* the sclk is in quantas of 10kHz */
	402	if (amdgpu_sriov_vf(adev))
	403	return adev->clock.default_sclk / 100;
7ba01f9e SL	404	else if (adev->powerplay.pp_funcs)
	405	return amdgpu_dpm_get_sclk(adev, false) / 100;
	406	else
	407	return 100;
130e0371	408	}
ebdebf42 FC	409
	410	void get_cu_info(struct kgd_dev kgd, struct kfd_cu_info cu_info)
	411	{
	412	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	413	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
	414
	415	memset(cu_info, 0, sizeof(*cu_info));
	416	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
	417	return;
	418
	419	cu_info->cu_active_number = acu_info.number;
	420	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
	421	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
	422	sizeof(acu_info.bitmap));
	423	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
	424	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
	425	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
	426	cu_info->simd_per_cu = acu_info.simd_per_cu;
	427	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
	428	cu_info->wave_front_size = acu_info.wave_front_size;
	429	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
	430	cu_info->lds_size = acu_info.lds_size;
	431	}
9f0a0b41 KR	432
	433	uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
	434	{
	435	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	436
	437	return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
	438	}
155494db	439
4c660c8f FK	440	int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
	441	uint32_t vmid, uint64_t gpu_addr,
	442	uint32_t *ib_cmd, uint32_t ib_len)
	443	{
	444	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	445	struct amdgpu_job *job;
	446	struct amdgpu_ib *ib;
	447	struct amdgpu_ring *ring;
	448	struct dma_fence *f = NULL;
	449	int ret;
	450
	451	switch (engine) {
	452	case KGD_ENGINE_MEC1:
	453	ring = &adev->gfx.compute_ring[0];
	454	break;
	455	case KGD_ENGINE_SDMA1:
	456	ring = &adev->sdma.instance[0].ring;
	457	break;
	458	case KGD_ENGINE_SDMA2:
	459	ring = &adev->sdma.instance[1].ring;
	460	break;
	461	default:
	462	pr_err("Invalid engine in IB submission: %d\n", engine);
	463	ret = -EINVAL;
	464	goto err;
	465	}
	466
	467	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
	468	if (ret)
	469	goto err;
	470
	471	ib = &job->ibs[0];
	472	memset(ib, 0, sizeof(struct amdgpu_ib));
	473
	474	ib->gpu_addr = gpu_addr;
	475	ib->ptr = ib_cmd;
	476	ib->length_dw = ib_len;
	477	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
	478	job->vmid = vmid;
	479
	480	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
	481	if (ret) {
	482	DRM_ERROR("amdgpu: failed to schedule IB.\n");
	483	goto err_ib_sched;
	484	}
	485
	486	ret = dma_fence_wait(f, false);
	487
	488	err_ib_sched:
	489	dma_fence_put(f);
	490	amdgpu_job_free(job);
	491	err:
	492	return ret;
	493	}
	494
01c097db FK	495	void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
	496	{
	497	struct amdgpu_device adev = (struct amdgpu_device )kgd;
	498
	499	amdgpu_dpm_switch_power_profile(adev,
	500	PP_SMC_POWER_PROFILE_COMPUTE, !idle);
	501	}
	502
155494db FK	503	bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
	504	{
	505	if (adev->kfd) {
	506	if ((1 << vmid) & compute_vmid_bitmap)
	507	return true;
	508	}
	509
	510	return false;
	511	}
fcdfa432 OG	512
	513	#if !defined(CONFIG_HSA_AMD_MODULE) && !defined(CONFIG_HSA_AMD)
	514	bool amdkfd_fence_check_mm(struct dma_fence f, struct mm_struct mm)
	515	{
	516	return false;
	517	}
	518
	519	void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
	520	{
	521	}
	522
	523	void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
	524	struct amdgpu_vm *vm)
	525	{
	526	}
	527
	528	struct amdgpu_amdkfd_fence to_amdgpu_amdkfd_fence(struct dma_fence f)
	529	{
	530	return NULL;
	531	}
	532
	533	int amdgpu_amdkfd_evict_userptr(struct kgd_mem mem, struct mm_struct mm)
	534	{
	535	return 0;
	536	}
	537
	538	struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
	539	{
	540	return NULL;
	541	}
	542
	543	struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
	544	{
	545	return NULL;
	546	}
	547
	548	struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
	549	{
	550	return NULL;
	551	}
	552	#endif