[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_acp.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include <linux/irqdomain.h>
#include <linux/pci.h>
#include <linux/pm_domain.h>
#include <linux/platform_device.h>
#include <sound/designware_i2s.h>
#include <sound/pcm.h>

#include "amdgpu.h"
#include "atom.h"
#include "amdgpu_acp.h"

#include "acp_gfx_if.h"

#define ACP_TILE_ON_MASK			0x03
#define ACP_TILE_OFF_MASK			0x02
#define ACP_TILE_ON_RETAIN_REG_MASK		0x1f
#define ACP_TILE_OFF_RETAIN_REG_MASK		0x20

#define ACP_TILE_P1_MASK			0x3e
#define ACP_TILE_P2_MASK			0x3d
#define ACP_TILE_DSP0_MASK			0x3b
#define ACP_TILE_DSP1_MASK			0x37

#define ACP_TILE_DSP2_MASK			0x2f

#define ACP_DMA_REGS_END			0x146c0
#define ACP_I2S_PLAY_REGS_START			0x14840
#define ACP_I2S_PLAY_REGS_END			0x148b4
#define ACP_I2S_CAP_REGS_START			0x148b8
#define ACP_I2S_CAP_REGS_END			0x1496c

#define ACP_I2S_COMP1_CAP_REG_OFFSET		0xac
#define ACP_I2S_COMP2_CAP_REG_OFFSET		0xa8
#define ACP_I2S_COMP1_PLAY_REG_OFFSET		0x6c
#define ACP_I2S_COMP2_PLAY_REG_OFFSET		0x68
#define ACP_BT_PLAY_REGS_START			0x14970
#define ACP_BT_PLAY_REGS_END			0x14a24
#define ACP_BT_COMP1_REG_OFFSET			0xac
#define ACP_BT_COMP2_REG_OFFSET			0xa8

#define mmACP_PGFSM_RETAIN_REG			0x51c9
#define mmACP_PGFSM_CONFIG_REG			0x51ca
#define mmACP_PGFSM_READ_REG_0			0x51cc

#define mmACP_MEM_SHUT_DOWN_REQ_LO		0x51f8
#define mmACP_MEM_SHUT_DOWN_REQ_HI		0x51f9
#define mmACP_MEM_SHUT_DOWN_STS_LO		0x51fa
#define mmACP_MEM_SHUT_DOWN_STS_HI		0x51fb

#define mmACP_CONTROL				0x5131
#define mmACP_STATUS				0x5133
#define mmACP_SOFT_RESET			0x5134
#define ACP_CONTROL__ClkEn_MASK			0x1
#define ACP_SOFT_RESET__SoftResetAud_MASK	0x100
#define ACP_SOFT_RESET__SoftResetAudDone_MASK	0x1000000
#define ACP_CLOCK_EN_TIME_OUT_VALUE		0x000000FF
#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE	0x000000FF

#define ACP_TIMEOUT_LOOP			0x000000FF
#define ACP_DEVS				4
#define ACP_SRC_ID				162

enum {
	ACP_TILE_P1 = 0,
	ACP_TILE_P2,
	ACP_TILE_DSP0,
	ACP_TILE_DSP1,
	ACP_TILE_DSP2,
};

static int acp_sw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	adev->acp.parent = adev->dev;

	adev->acp.cgs_device =
		amdgpu_cgs_create_device(adev);
	if (!adev->acp.cgs_device)
		return -EINVAL;

	return 0;
}

static int acp_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (adev->acp.cgs_device)
		amdgpu_cgs_destroy_device(adev->acp.cgs_device);

	return 0;
}

struct acp_pm_domain {
	void *adev;
	struct generic_pm_domain gpd;
};

static int acp_poweroff(struct generic_pm_domain *genpd)
{
	struct acp_pm_domain *apd;
	struct amdgpu_device *adev;

	apd = container_of(genpd, struct acp_pm_domain, gpd);
	if (apd != NULL) {
		adev = apd->adev;
	/* call smu to POWER GATE ACP block
	 * smu will
	 * 1. turn off the acp clock
	 * 2. power off the acp tiles
	 * 3. check and enter ulv state
	 */
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
	}
	return 0;
}

static int acp_poweron(struct generic_pm_domain *genpd)
{
	struct acp_pm_domain *apd;
	struct amdgpu_device *adev;

	apd = container_of(genpd, struct acp_pm_domain, gpd);
	if (apd != NULL) {
		adev = apd->adev;
	/* call smu to UNGATE ACP block
	 * smu will
	 * 1. exit ulv
	 * 2. turn on acp clock
	 * 3. power on acp tiles
	 */
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
	}
	return 0;
}

static int acp_genpd_add_device(struct device *dev, void *data)
{
	struct generic_pm_domain *gpd = data;
	int ret;

	ret = pm_genpd_add_device(gpd, dev);
	if (ret)
		dev_err(dev, "Failed to add dev to genpd %d\n", ret);

	return ret;
}

static int acp_genpd_remove_device(struct device *dev, void *data)
{
	int ret;

	ret = pm_genpd_remove_device(dev);
	if (ret)
		dev_err(dev, "Failed to remove dev from genpd %d\n", ret);

	/* Continue to remove */
	return 0;
}

/**
 * acp_hw_init - start and test ACP block
 *
 * @handle: handle used to pass amdgpu_device pointer
 *
 */
static int acp_hw_init(void *handle)
{
	int r;
	uint64_t acp_base;
	u32 val = 0;
	u32 count = 0;
	struct i2s_platform_data *i2s_pdata = NULL;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	const struct amdgpu_ip_block *ip_block =
		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);

	if (!ip_block)
		return -EINVAL;

	r = amd_acp_hw_init(adev->acp.cgs_device,
			    ip_block->version->major, ip_block->version->minor);
	/* -ENODEV means board uses AZ rather than ACP */
	if (r == -ENODEV) {
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
		return 0;
	} else if (r) {
		return r;
	}

	if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
		return -EINVAL;

	acp_base = adev->rmmio_base;


	adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
	if (adev->acp.acp_genpd == NULL)
		return -ENOMEM;

	adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
	adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
	adev->acp.acp_genpd->gpd.power_on = acp_poweron;


	adev->acp.acp_genpd->adev = adev;

	pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);

	adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
							GFP_KERNEL);

	if (adev->acp.acp_cell == NULL) {
		r = -ENOMEM;
		goto failure;
	}

	adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
	if (adev->acp.acp_res == NULL) {
		r = -ENOMEM;
		goto failure;
	}

	i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
	if (i2s_pdata == NULL) {
		r = -ENOMEM;
		goto failure;
	}

	switch (adev->asic_type) {
	case CHIP_STONEY:
		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
		break;
	default:
		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	}
	i2s_pdata[0].cap = DWC_I2S_PLAY;
	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
	switch (adev->asic_type) {
	case CHIP_STONEY:
		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
			DW_I2S_QUIRK_COMP_PARAM1 |
			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
		break;
	default:
		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
			DW_I2S_QUIRK_COMP_PARAM1;
	}

	i2s_pdata[1].cap = DWC_I2S_RECORD;
	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;

	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	switch (adev->asic_type) {
	case CHIP_STONEY:
		i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
		break;
	default:
		break;
	}

	i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
	i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
	i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
	i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;

	adev->acp.acp_res[0].name = "acp2x_dma";
	adev->acp.acp_res[0].flags = IORESOURCE_MEM;
	adev->acp.acp_res[0].start = acp_base;
	adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;

	adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
	adev->acp.acp_res[1].flags = IORESOURCE_MEM;
	adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
	adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;

	adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
	adev->acp.acp_res[2].flags = IORESOURCE_MEM;
	adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
	adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;

	adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
	adev->acp.acp_res[3].flags = IORESOURCE_MEM;
	adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
	adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;

	adev->acp.acp_res[4].name = "acp2x_dma_irq";
	adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
	adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
	adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;

	adev->acp.acp_cell[0].name = "acp_audio_dma";
	adev->acp.acp_cell[0].num_resources = 5;
	adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
	adev->acp.acp_cell[0].platform_data = &adev->asic_type;
	adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);

	adev->acp.acp_cell[1].name = "designware-i2s";
	adev->acp.acp_cell[1].num_resources = 1;
	adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
	adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
	adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);

	adev->acp.acp_cell[2].name = "designware-i2s";
	adev->acp.acp_cell[2].num_resources = 1;
	adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
	adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
	adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);

	adev->acp.acp_cell[3].name = "designware-i2s";
	adev->acp.acp_cell[3].num_resources = 1;
	adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
	adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
	adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);

	r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
								ACP_DEVS);
	if (r)
		goto failure;

	r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
				  acp_genpd_add_device);
	if (r)
		goto failure;

	/* Assert Soft reset of ACP */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);

	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);

	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			r = -ETIMEDOUT;
			goto failure;
		}
		udelay(100);
	}
	/* Enable clock to ACP and wait until the clock is enabled */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	val = val | ACP_CONTROL__ClkEn_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);

	count = ACP_CLOCK_EN_TIME_OUT_VALUE;

	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
		if (val & (u32) 0x1)
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			r = -ETIMEDOUT;
			goto failure;
		}
		udelay(100);
	}
	/* Deassert the SOFT RESET flags */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
	return 0;

failure:
	kfree(i2s_pdata);
	kfree(adev->acp.acp_res);
	kfree(adev->acp.acp_cell);
	kfree(adev->acp.acp_genpd);
	return r;
}

/**
 * acp_hw_fini - stop the hardware block
 *
 * @handle: handle used to pass amdgpu_device pointer
 *
 */
static int acp_hw_fini(void *handle)
{
	u32 val = 0;
	u32 count = 0;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* return early if no ACP */
	if (!adev->acp.acp_genpd) {
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
		return 0;
	}

	/* Assert Soft reset of ACP */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);

	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);

	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}
	/* Disable ACP clock */
	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	val &= ~ACP_CONTROL__ClkEn_MASK;
	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);

	count = ACP_CLOCK_EN_TIME_OUT_VALUE;

	while (true) {
		val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
		if (val & (u32) 0x1)
			break;
		if (--count == 0) {
			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
			return -ETIMEDOUT;
		}
		udelay(100);
	}

	device_for_each_child(adev->acp.parent, NULL,
			      acp_genpd_remove_device);

	mfd_remove_devices(adev->acp.parent);
	kfree(adev->acp.acp_res);
	kfree(adev->acp.acp_genpd);
	kfree(adev->acp.acp_cell);

	return 0;
}

static int acp_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* power up on suspend */
	if (!adev->acp.acp_cell)
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
	return 0;
}

static int acp_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* power down again on resume */
	if (!adev->acp.acp_cell)
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
	return 0;
}

static int acp_early_init(void *handle)
{
	return 0;
}

static bool acp_is_idle(void *handle)
{
	return true;
}

static int acp_wait_for_idle(void *handle)
{
	return 0;
}

static int acp_soft_reset(void *handle)
{
	return 0;
}

static int acp_set_clockgating_state(void *handle,
				     enum amd_clockgating_state state)
{
	return 0;
}

static int acp_set_powergating_state(void *handle,
				     enum amd_powergating_state state)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	bool enable = (state == AMD_PG_STATE_GATE);

	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);

	return 0;
}

static const struct amd_ip_funcs acp_ip_funcs = {
	.name = "acp_ip",
	.early_init = acp_early_init,
	.late_init = NULL,
	.sw_init = acp_sw_init,
	.sw_fini = acp_sw_fini,
	.hw_init = acp_hw_init,
	.hw_fini = acp_hw_fini,
	.suspend = acp_suspend,
	.resume = acp_resume,
	.is_idle = acp_is_idle,
	.wait_for_idle = acp_wait_for_idle,
	.soft_reset = acp_soft_reset,
	.set_clockgating_state = acp_set_clockgating_state,
	.set_powergating_state = acp_set_powergating_state,
};

const struct amdgpu_ip_block_version acp_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_ACP,
	.major = 2,
	.minor = 2,
	.rev = 0,
	.funcs = &acp_ip_funcs,
};
Commit	Line	Data
a8fe58ce MB	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include <linux/irqdomain.h>
841d0023	27	#include <linux/pci.h>
25030321	28	#include <linux/pm_domain.h>
a8fe58ce MB	29	#include <linux/platform_device.h>
	30	#include <sound/designware_i2s.h>
	31	#include <sound/pcm.h>
	32
	33	#include "amdgpu.h"
	34	#include "atom.h"
	35	#include "amdgpu_acp.h"
	36
	37	#include "acp_gfx_if.h"
	38
f3729f7b DV	39	#define ACP_TILE_ON_MASK 0x03
	40	#define ACP_TILE_OFF_MASK 0x02
	41	#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
	42	#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
37c5f2c9	43
f3729f7b DV	44	#define ACP_TILE_P1_MASK 0x3e
	45	#define ACP_TILE_P2_MASK 0x3d
	46	#define ACP_TILE_DSP0_MASK 0x3b
	47	#define ACP_TILE_DSP1_MASK 0x37
37c5f2c9	48
f3729f7b	49	#define ACP_TILE_DSP2_MASK 0x2f
37c5f2c9 AA	50
	51	#define ACP_DMA_REGS_END 0x146c0
	52	#define ACP_I2S_PLAY_REGS_START 0x14840
	53	#define ACP_I2S_PLAY_REGS_END 0x148b4
	54	#define ACP_I2S_CAP_REGS_START 0x148b8
	55	#define ACP_I2S_CAP_REGS_END 0x1496c
	56
	57	#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
	58	#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
	59	#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
	60	#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
2d95ceb4 VM	61	#define ACP_BT_PLAY_REGS_START 0x14970
	62	#define ACP_BT_PLAY_REGS_END 0x14a24
	63	#define ACP_BT_COMP1_REG_OFFSET 0xac
	64	#define ACP_BT_COMP2_REG_OFFSET 0xa8
37c5f2c9 AA	65
	66	#define mmACP_PGFSM_RETAIN_REG 0x51c9
	67	#define mmACP_PGFSM_CONFIG_REG 0x51ca
	68	#define mmACP_PGFSM_READ_REG_0 0x51cc
	69
	70	#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
	71	#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
	72	#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
	73	#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
	74
	75	#define mmACP_CONTROL 0x5131
	76	#define mmACP_STATUS 0x5133
	77	#define mmACP_SOFT_RESET 0x5134
f3729f7b DV	78	#define ACP_CONTROL__ClkEn_MASK 0x1
f3729f7b DV	79	#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
37c5f2c9 AA	80	#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
	81	#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
	82	#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
	83
	84	#define ACP_TIMEOUT_LOOP 0x000000FF
2d95ceb4	85	#define ACP_DEVS 4
37c5f2c9	86	#define ACP_SRC_ID 162
a8fe58ce MB	87
	88	enum {
	89	ACP_TILE_P1 = 0,
	90	ACP_TILE_P2,
	91	ACP_TILE_DSP0,
	92	ACP_TILE_DSP1,
	93	ACP_TILE_DSP2,
	94	};
	95
	96	static int acp_sw_init(void *handle)
	97	{
	98	struct amdgpu_device adev = (struct amdgpu_device )handle;
	99
	100	adev->acp.parent = adev->dev;
	101
	102	adev->acp.cgs_device =
	103	amdgpu_cgs_create_device(adev);
	104	if (!adev->acp.cgs_device)
	105	return -EINVAL;
	106
	107	return 0;
	108	}
	109
	110	static int acp_sw_fini(void *handle)
	111	{
	112	struct amdgpu_device adev = (struct amdgpu_device )handle;
	113
	114	if (adev->acp.cgs_device)
	115	amdgpu_cgs_destroy_device(adev->acp.cgs_device);
	116
	117	return 0;
	118	}
	119
25030321	120	struct acp_pm_domain {
3a54d2c8	121	void *adev;
25030321 MSB	122	struct generic_pm_domain gpd;
	123	};
	124
	125	static int acp_poweroff(struct generic_pm_domain *genpd)
	126	{
25030321	127	struct acp_pm_domain *apd;
3a54d2c8	128	struct amdgpu_device *adev;
25030321 MSB	129
	130	apd = container_of(genpd, struct acp_pm_domain, gpd);
	131	if (apd != NULL) {
3a54d2c8 RZ	132	adev = apd->adev;
	133	/* call smu to POWER GATE ACP block
	134	* smu will
	135	* 1. turn off the acp clock
	136	* 2. power off the acp tiles
	137	* 3. check and enter ulv state
	138	*/
70bdb6ed	139	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
25030321 MSB	140	}
	141	return 0;
	142	}
	143
	144	static int acp_poweron(struct generic_pm_domain *genpd)
	145	{
25030321	146	struct acp_pm_domain *apd;
3a54d2c8	147	struct amdgpu_device *adev;
25030321 MSB	148
	149	apd = container_of(genpd, struct acp_pm_domain, gpd);
	150	if (apd != NULL) {
3a54d2c8 RZ	151	adev = apd->adev;
	152	/* call smu to UNGATE ACP block
	153	* smu will
	154	* 1. exit ulv
	155	* 2. turn on acp clock
	156	* 3. power on acp tiles
	157	*/
70bdb6ed	158	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
25030321 MSB	159	}
	160	return 0;
	161	}
	162
aff89028	163	static int acp_genpd_add_device(struct device dev, void data)
25030321	164	{
aff89028 KHF	165	struct generic_pm_domain *gpd = data;
aff89028 KHF	166	int ret;
25030321	167
aff89028 KHF	168	ret = pm_genpd_add_device(gpd, dev);
	169	if (ret)
	170	dev_err(dev, "Failed to add dev to genpd %d\n", ret);
25030321	171
aff89028 KHF	172	return ret;
	173	}
	174
	175	static int acp_genpd_remove_device(struct device dev, void data)
	176	{
	177	int ret;
	178
	179	ret = pm_genpd_remove_device(dev);
	180	if (ret)
	181	dev_err(dev, "Failed to remove dev from genpd %d\n", ret);
	182
	183	/* Continue to remove */
	184	return 0;
25030321 MSB	185	}
25030321 MSB	186
a8fe58ce MB	187	/**
	188	* acp_hw_init - start and test ACP block
	189	*
adf0125a	190	* @handle: handle used to pass amdgpu_device pointer
a8fe58ce MB	191	*
	192	*/
	193	static int acp_hw_init(void *handle)
	194	{
aff89028	195	int r;
a8fe58ce	196	uint64_t acp_base;
37c5f2c9 AA	197	u32 val = 0;
37c5f2c9 AA	198	u32 count = 0;
57be09c6	199	struct i2s_platform_data *i2s_pdata = NULL;
a8fe58ce MB	200
	201	struct amdgpu_device adev = (struct amdgpu_device )handle;
	202
a1255107	203	const struct amdgpu_ip_block *ip_block =
2990a1fc	204	amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
a8fe58ce	205
a1255107	206	if (!ip_block)
a8fe58ce MB	207	return -EINVAL;
	208
	209	r = amd_acp_hw_init(adev->acp.cgs_device,
a1255107	210	ip_block->version->major, ip_block->version->minor);
a8fe58ce	211	/* -ENODEV means board uses AZ rather than ACP */
be2d6aa5 RZ	212	if (r == -ENODEV) {
be2d6aa5 RZ	213	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
a8fe58ce	214	return 0;
be2d6aa5	215	} else if (r) {
a8fe58ce	216	return r;
be2d6aa5	217	}
a8fe58ce	218
d32d6617 RZ	219	if (adev->rmmio_size == 0 \|\| adev->rmmio_size < 0x5289)
	220	return -EINVAL;
	221
	222	acp_base = adev->rmmio_base;
	223
a8fe58ce	224
1062ddb6 VM	225	adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
	226	if (adev->acp.acp_genpd == NULL)
	227	return -ENOMEM;
25030321	228
1062ddb6 VM	229	adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
	230	adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
	231	adev->acp.acp_genpd->gpd.power_on = acp_poweron;
25030321	232
25030321	233
3a54d2c8	234	adev->acp.acp_genpd->adev = adev;
1062ddb6 VM	235
1062ddb6 VM	236	pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
25030321	237
6396bb22	238	adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
a8fe58ce MB	239	GFP_KERNEL);
a8fe58ce MB	240
57be09c6 NE	241	if (adev->acp.acp_cell == NULL) {
	242	r = -ENOMEM;
	243	goto failure;
	244	}
a8fe58ce	245
2d95ceb4	246	adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
a8fe58ce	247	if (adev->acp.acp_res == NULL) {
57be09c6 NE	248	r = -ENOMEM;
57be09c6 NE	249	goto failure;
a8fe58ce MB	250	}
a8fe58ce MB	251
2d95ceb4	252	i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
a8fe58ce	253	if (i2s_pdata == NULL) {
57be09c6 NE	254	r = -ENOMEM;
57be09c6 NE	255	goto failure;
a8fe58ce MB	256	}
a8fe58ce MB	257
81454cad VM	258	switch (adev->asic_type) {
	259	case CHIP_STONEY:
	260	i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET \|
	261	DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
	262	break;
	263	default:
	264	i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	265	}
a8fe58ce MB	266	i2s_pdata[0].cap = DWC_I2S_PLAY;
	267	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
	268	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
	269	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
81454cad VM	270	switch (adev->asic_type) {
	271	case CHIP_STONEY:
	272	i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET \|
	273	DW_I2S_QUIRK_COMP_PARAM1 \|
	274	DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
	275	break;
	276	default:
	277	i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET \|
	278	DW_I2S_QUIRK_COMP_PARAM1;
	279	}
a8fe58ce	280
a8fe58ce MB	281	i2s_pdata[1].cap = DWC_I2S_RECORD;
	282	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
	283	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
	284	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
	285
2d95ceb4 VM	286	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
	287	switch (adev->asic_type) {
	288	case CHIP_STONEY:
	289	i2s_pdata[2].quirks \|= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
	290	break;
	291	default:
	292	break;
	293	}
	294
	295	i2s_pdata[2].cap = DWC_I2S_PLAY \| DWC_I2S_RECORD;
	296	i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
	297	i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
	298	i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
	299
a8fe58ce MB	300	adev->acp.acp_res[0].name = "acp2x_dma";
	301	adev->acp.acp_res[0].flags = IORESOURCE_MEM;
	302	adev->acp.acp_res[0].start = acp_base;
	303	adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
	304
	305	adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
	306	adev->acp.acp_res[1].flags = IORESOURCE_MEM;
	307	adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
	308	adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
	309
	310	adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
	311	adev->acp.acp_res[2].flags = IORESOURCE_MEM;
	312	adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
	313	adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
	314
2d95ceb4 VM	315	adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
	316	adev->acp.acp_res[3].flags = IORESOURCE_MEM;
	317	adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
	318	adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
	319
	320	adev->acp.acp_res[4].name = "acp2x_dma_irq";
	321	adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
	322	adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
	323	adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
a8fe58ce MB	324
a8fe58ce MB	325	adev->acp.acp_cell[0].name = "acp_audio_dma";
2d95ceb4	326	adev->acp.acp_cell[0].num_resources = 5;
a8fe58ce	327	adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
1fd16f36 VM	328	adev->acp.acp_cell[0].platform_data = &adev->asic_type;
1fd16f36 VM	329	adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
a8fe58ce MB	330
	331	adev->acp.acp_cell[1].name = "designware-i2s";
	332	adev->acp.acp_cell[1].num_resources = 1;
	333	adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
	334	adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
	335	adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
	336
	337	adev->acp.acp_cell[2].name = "designware-i2s";
	338	adev->acp.acp_cell[2].num_resources = 1;
	339	adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
	340	adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
	341	adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
	342
2d95ceb4 VM	343	adev->acp.acp_cell[3].name = "designware-i2s";
	344	adev->acp.acp_cell[3].num_resources = 1;
	345	adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
	346	adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
	347	adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
	348
a8fe58ce MB	349	r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
	350	ACP_DEVS);
	351	if (r)
57be09c6	352	goto failure;
a8fe58ce	353
aff89028 KHF	354	r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
	355	acp_genpd_add_device);
	356	if (r)
	357	goto failure;
1062ddb6	358
37c5f2c9 AA	359	/* Assert Soft reset of ACP */
	360	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	361
	362	val \|= ACP_SOFT_RESET__SoftResetAud_MASK;
	363	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
	364
	365	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	366	while (true) {
	367	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	368	if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
	369	(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
	370	break;
	371	if (--count == 0) {
	372	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
57be09c6 NE	373	r = -ETIMEDOUT;
57be09c6 NE	374	goto failure;
37c5f2c9 AA	375	}
	376	udelay(100);
	377	}
	378	/* Enable clock to ACP and wait until the clock is enabled */
	379	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	380	val = val \| ACP_CONTROL__ClkEn_MASK;
	381	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
	382
	383	count = ACP_CLOCK_EN_TIME_OUT_VALUE;
	384
	385	while (true) {
	386	val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
	387	if (val & (u32) 0x1)
	388	break;
	389	if (--count == 0) {
	390	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
57be09c6 NE	391	r = -ETIMEDOUT;
57be09c6 NE	392	goto failure;
37c5f2c9 AA	393	}
	394	udelay(100);
	395	}
	396	/* Deassert the SOFT RESET flags */
	397	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	398	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
	399	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
a8fe58ce	400	return 0;
57be09c6 NE	401
	402	failure:
	403	kfree(i2s_pdata);
	404	kfree(adev->acp.acp_res);
	405	kfree(adev->acp.acp_cell);
	406	kfree(adev->acp.acp_genpd);
	407	return r;
a8fe58ce MB	408	}
	409
	410	/**
	411	* acp_hw_fini - stop the hardware block
	412	*
adf0125a	413	* @handle: handle used to pass amdgpu_device pointer
a8fe58ce MB	414	*
	415	*/
	416	static int acp_hw_fini(void *handle)
	417	{
37c5f2c9 AA	418	u32 val = 0;
37c5f2c9 AA	419	u32 count = 0;
a8fe58ce MB	420	struct amdgpu_device adev = (struct amdgpu_device )handle;
a8fe58ce MB	421
757124d9	422	/* return early if no ACP */
1062ddb6	423	if (!adev->acp.acp_genpd) {
be2d6aa5	424	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
757124d9	425	return 0;
be2d6aa5	426	}
757124d9	427
37c5f2c9 AA	428	/* Assert Soft reset of ACP */
	429	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	430
	431	val \|= ACP_SOFT_RESET__SoftResetAud_MASK;
	432	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
	433
	434	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
	435	while (true) {
	436	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
	437	if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
	438	(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
	439	break;
	440	if (--count == 0) {
	441	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
	442	return -ETIMEDOUT;
	443	}
	444	udelay(100);
	445	}
	446	/* Disable ACP clock */
	447	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
	448	val &= ~ACP_CONTROL__ClkEn_MASK;
	449	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
	450
	451	count = ACP_CLOCK_EN_TIME_OUT_VALUE;
	452
	453	while (true) {
	454	val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
	455	if (val & (u32) 0x1)
	456	break;
	457	if (--count == 0) {
	458	dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
	459	return -ETIMEDOUT;
	460	}
	461	udelay(100);
	462	}
	463
aff89028 KHF	464	device_for_each_child(adev->acp.parent, NULL,
aff89028 KHF	465	acp_genpd_remove_device);
25030321	466
a8fe58ce MB	467	mfd_remove_devices(adev->acp.parent);
a8fe58ce MB	468	kfree(adev->acp.acp_res);
1062ddb6	469	kfree(adev->acp.acp_genpd);
a8fe58ce MB	470	kfree(adev->acp.acp_cell);
	471
	472	return 0;
	473	}
	474
	475	static int acp_suspend(void *handle)
	476	{
be2d6aa5 RZ	477	struct amdgpu_device adev = (struct amdgpu_device )handle;
	478
	479	/* power up on suspend */
	480	if (!adev->acp.acp_cell)
	481	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
a8fe58ce MB	482	return 0;
	483	}
	484
	485	static int acp_resume(void *handle)
	486	{
be2d6aa5 RZ	487	struct amdgpu_device adev = (struct amdgpu_device )handle;
	488
	489	/* power down again on resume */
	490	if (!adev->acp.acp_cell)
	491	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
a8fe58ce MB	492	return 0;
	493	}
	494
	495	static int acp_early_init(void *handle)
	496	{
	497	return 0;
	498	}
	499
	500	static bool acp_is_idle(void *handle)
	501	{
	502	return true;
	503	}
	504
	505	static int acp_wait_for_idle(void *handle)
	506	{
	507	return 0;
	508	}
	509
	510	static int acp_soft_reset(void *handle)
	511	{
	512	return 0;
	513	}
	514
a8fe58ce MB	515	static int acp_set_clockgating_state(void *handle,
	516	enum amd_clockgating_state state)
	517	{
	518	return 0;
	519	}
	520
	521	static int acp_set_powergating_state(void *handle,
	522	enum amd_powergating_state state)
	523	{
c36628d8	524	struct amdgpu_device adev = (struct amdgpu_device )handle;
a9d4fe2f	525	bool enable = (state == AMD_PG_STATE_GATE);
c36628d8	526
70bdb6ed	527	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
c36628d8	528
a8fe58ce MB	529	return 0;
	530	}
	531
a1255107	532	static const struct amd_ip_funcs acp_ip_funcs = {
88a907d6	533	.name = "acp_ip",
a8fe58ce MB	534	.early_init = acp_early_init,
	535	.late_init = NULL,
	536	.sw_init = acp_sw_init,
	537	.sw_fini = acp_sw_fini,
	538	.hw_init = acp_hw_init,
	539	.hw_fini = acp_hw_fini,
	540	.suspend = acp_suspend,
	541	.resume = acp_resume,
	542	.is_idle = acp_is_idle,
	543	.wait_for_idle = acp_wait_for_idle,
	544	.soft_reset = acp_soft_reset,
a8fe58ce MB	545	.set_clockgating_state = acp_set_clockgating_state,
	546	.set_powergating_state = acp_set_powergating_state,
	547	};
a1255107 AD	548
	549	const struct amdgpu_ip_block_version acp_ip_block =
	550	{
	551	.type = AMD_IP_BLOCK_TYPE_ACP,
	552	.major = 2,
	553	.minor = 2,
	554	.rev = 0,
	555	.funcs = &acp_ip_funcs,
	556	};